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nvme-hwmon: rework to avoid devm allocation
[linux-2.6-block.git] / drivers / nvme / host / pci.c
CommitLineData
5f37396d 1// SPDX-License-Identifier: GPL-2.0
b60503ba
MW		 2/*
3 * NVM Express device driver
6eb0d698 4 * Copyright (c) 2011-2014, Intel Corporation.
b60503ba
MW		 5 */
6
df4f9bc4 7#include <linux/acpi.h>
a0a3408e 8#include <linux/aer.h>
18119775 9#include <linux/async.h>
b60503ba 10#include <linux/blkdev.h>
a4aea562 11#include <linux/blk-mq.h>
dca51e78 12#include <linux/blk-mq-pci.h>
ff5350a8 13#include <linux/dmi.h>
b60503ba
MW		 14#include <linux/init.h>
15#include <linux/interrupt.h>
16#include <linux/io.h>
b60503ba
MW		 17#include <linux/mm.h>
18#include <linux/module.h>
77bf25ea 19#include <linux/mutex.h>
d0877473 20#include <linux/once.h>
b60503ba 21#include <linux/pci.h>
d916b1be 22#include <linux/suspend.h>
e1e5e564 23#include <linux/t10-pi.h>
b60503ba 24#include <linux/types.h>
2f8e2c87 25#include <linux/io-64-nonatomic-lo-hi.h>
20d3bb92 26#include <linux/io-64-nonatomic-hi-lo.h>
a98e58e5 27#include <linux/sed-opal.h>
0f238ff5 28#include <linux/pci-p2pdma.h>
797a796a 29
604c01d5 30#include "trace.h"
f11bb3e2
CH		 31#include "nvme.h"
32
c1e0cc7e 33#define SQ_SIZE(q) ((q)->q_depth << (q)->sqes)
8a1d09a6 34#define CQ_SIZE(q) ((q)->q_depth * sizeof(struct nvme_completion))
c965809c 35
a7a7cbe3 36#define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc))
9d43cf64 37
943e942e
JA		 38/*
39 * These can be higher, but we need to ensure that any command doesn't
40 * require an sg allocation that needs more than a page of data.
41 */
42#define NVME_MAX_KB_SZ 4096
43#define NVME_MAX_SEGS 127
44
58ffacb5
MW		 45static int use_threaded_interrupts;
46module_param(use_threaded_interrupts, int, 0);
47
8ffaadf7 48static bool use_cmb_sqes = true;
69f4eb9f 49module_param(use_cmb_sqes, bool, 0444);
8ffaadf7
JD		 50MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
51
87ad72a5
CH		 52static unsigned int max_host_mem_size_mb = 128;
53module_param(max_host_mem_size_mb, uint, 0444);
54MODULE_PARM_DESC(max_host_mem_size_mb,
55 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
1fa6aead 56
a7a7cbe3
CK		 57static unsigned int sgl_threshold = SZ_32K;
58module_param(sgl_threshold, uint, 0644);
59MODULE_PARM_DESC(sgl_threshold,
60 "Use SGLs when average request segment size is larger or equal to "
61 "this size. Use 0 to disable SGLs.");
62
b27c1e68 63static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
64static const struct kernel_param_ops io_queue_depth_ops = {
65 .set = io_queue_depth_set,
61f3b896 66 .get = param_get_uint,
b27c1e68 67};
68
61f3b896 69static unsigned int io_queue_depth = 1024;
b27c1e68 70module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
71MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2");
72
9c9e76d5
WZ		 73static int io_queue_count_set(const char *val, const struct kernel_param *kp)
74{
75 unsigned int n;
76 int ret;
77
78 ret = kstrtouint(val, 10, &n);
79 if (ret != 0 || n > num_possible_cpus())
80 return -EINVAL;
81 return param_set_uint(val, kp);
82}
83
84static const struct kernel_param_ops io_queue_count_ops = {
85 .set = io_queue_count_set,
86 .get = param_get_uint,
87};
88
3f68baf7 89static unsigned int write_queues;
9c9e76d5 90module_param_cb(write_queues, &io_queue_count_ops, &write_queues, 0644);
3b6592f7
JA		 91MODULE_PARM_DESC(write_queues,
92 "Number of queues to use for writes. If not set, reads and writes "
93 "will share a queue set.");
94
3f68baf7 95static unsigned int poll_queues;
9c9e76d5 96module_param_cb(poll_queues, &io_queue_count_ops, &poll_queues, 0644);
4b04cc6a
JA		 97MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO.");
98
df4f9bc4
DB		 99static bool noacpi;
100module_param(noacpi, bool, 0444);
101MODULE_PARM_DESC(noacpi, "disable acpi bios quirks");
102
1c63dc66
CH		 103struct nvme_dev;
104struct nvme_queue;
b3fffdef 105
a5cdb68c 106static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
8fae268b 107static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode);
d4b4ff8e 108
1c63dc66
CH		 109/*
110 * Represents an NVM Express device. Each nvme_dev is a PCI function.
111 */
112struct nvme_dev {
147b27e4 113 struct nvme_queue *queues;
1c63dc66
CH		 114 struct blk_mq_tag_set tagset;
115 struct blk_mq_tag_set admin_tagset;
116 u32 __iomem *dbs;
117 struct device *dev;
118 struct dma_pool *prp_page_pool;
119 struct dma_pool *prp_small_pool;
1c63dc66
CH		 120 unsigned online_queues;
121 unsigned max_qid;
e20ba6e1 122 unsigned io_queues[HCTX_MAX_TYPES];
22b55601 123 unsigned int num_vecs;
7442ddce 124 u32 q_depth;
c1e0cc7e 125 int io_sqes;
1c63dc66 126 u32 db_stride;
1c63dc66 127 void __iomem *bar;
97f6ef64 128 unsigned long bar_mapped_size;
5c8809e6 129 struct work_struct remove_work;
77bf25ea 130 struct mutex shutdown_lock;
1c63dc66 131 bool subsystem;
1c63dc66 132 u64 cmb_size;
0f238ff5 133 bool cmb_use_sqes;
1c63dc66 134 u32 cmbsz;
202021c1 135 u32 cmbloc;
1c63dc66 136 struct nvme_ctrl ctrl;
d916b1be 137 u32 last_ps;
87ad72a5 138
943e942e
JA		 139 mempool_t *iod_mempool;
140
87ad72a5 141 /* shadow doorbell buffer support: */
f9f38e33
HK		 142 u32 *dbbuf_dbs;
143 dma_addr_t dbbuf_dbs_dma_addr;
144 u32 *dbbuf_eis;
145 dma_addr_t dbbuf_eis_dma_addr;
87ad72a5
CH		 146
147 /* host memory buffer support: */
148 u64 host_mem_size;
149 u32 nr_host_mem_descs;
4033f35d 150 dma_addr_t host_mem_descs_dma;
87ad72a5
CH		 151 struct nvme_host_mem_buf_desc *host_mem_descs;
152 void **host_mem_desc_bufs;
2a5bcfdd
WZ		 153 unsigned int nr_allocated_queues;
154 unsigned int nr_write_queues;
155 unsigned int nr_poll_queues;
4d115420 156};
1fa6aead 157
b27c1e68 158static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
159{
61f3b896 160 int ret;
7442ddce 161 u32 n;
b27c1e68 162
7442ddce 163 ret = kstrtou32(val, 10, &n);
b27c1e68 164 if (ret != 0 || n < 2)
165 return -EINVAL;
166
7442ddce 167 return param_set_uint(val, kp);
b27c1e68 168}
169
f9f38e33
HK		 170static inline unsigned int sq_idx(unsigned int qid, u32 stride)
171{
172 return qid * 2 * stride;
173}
174
175static inline unsigned int cq_idx(unsigned int qid, u32 stride)
176{
177 return (qid * 2 + 1) * stride;
178}
179
1c63dc66
CH		 180static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
181{
182 return container_of(ctrl, struct nvme_dev, ctrl);
183}
184
b60503ba
MW		 185/*
186 * An NVM Express queue. Each device has at least two (one for admin
187 * commands and one for I/O commands).
188 */
189struct nvme_queue {
091b6092 190 struct nvme_dev *dev;
1ab0cd69 191 spinlock_t sq_lock;
c1e0cc7e 192 void *sq_cmds;
3a7afd8e
CH		 193 /* only used for poll queues: */
194 spinlock_t cq_poll_lock ____cacheline_aligned_in_smp;
74943d45 195 struct nvme_completion *cqes;
b60503ba
MW		 196 dma_addr_t sq_dma_addr;
197 dma_addr_t cq_dma_addr;
b60503ba 198 u32 __iomem *q_db;
7442ddce 199 u32 q_depth;
7c349dde 200 u16 cq_vector;
b60503ba 201 u16 sq_tail;
38210800 202 u16 last_sq_tail;
b60503ba 203 u16 cq_head;
c30341dc 204 u16 qid;
e9539f47 205 u8 cq_phase;
c1e0cc7e 206 u8 sqes;
4e224106
CH		 207 unsigned long flags;
208#define NVMEQ_ENABLED 0
63223078 209#define NVMEQ_SQ_CMB 1
d1ed6aa1 210#define NVMEQ_DELETE_ERROR 2
7c349dde 211#define NVMEQ_POLLED 3
f9f38e33
HK		 212 u32 *dbbuf_sq_db;
213 u32 *dbbuf_cq_db;
214 u32 *dbbuf_sq_ei;
215 u32 *dbbuf_cq_ei;
d1ed6aa1 216 struct completion delete_done;
b60503ba
MW		 217};
218
71bd150c 219/*
9b048119
CH		 220 * The nvme_iod describes the data in an I/O.
221 *
222 * The sg pointer contains the list of PRP/SGL chunk allocations in addition
223 * to the actual struct scatterlist.
71bd150c
CH		 224 */
225struct nvme_iod {
d49187e9 226 struct nvme_request req;
f4800d6d 227 struct nvme_queue *nvmeq;
a7a7cbe3 228 bool use_sgl;
f4800d6d 229 int aborted;
71bd150c 230 int npages; /* In the PRP list. 0 means small pool in use */
71bd150c 231 int nents; /* Used in scatterlist */
71bd150c 232 dma_addr_t first_dma;
dff824b2 233 unsigned int dma_len; /* length of single DMA segment mapping */
783b94bd 234 dma_addr_t meta_dma;
f4800d6d 235 struct scatterlist *sg;
b60503ba
MW		 236};
237
2a5bcfdd 238static inline unsigned int nvme_dbbuf_size(struct nvme_dev *dev)
3b6592f7 239{
2a5bcfdd 240 return dev->nr_allocated_queues * 8 * dev->db_stride;
f9f38e33
HK		 241}
242
243static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
244{
2a5bcfdd 245 unsigned int mem_size = nvme_dbbuf_size(dev);
f9f38e33
HK		 246
247 if (dev->dbbuf_dbs)
248 return 0;
249
250 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
251 &dev->dbbuf_dbs_dma_addr,
252 GFP_KERNEL);
253 if (!dev->dbbuf_dbs)
254 return -ENOMEM;
255 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
256 &dev->dbbuf_eis_dma_addr,
257 GFP_KERNEL);
258 if (!dev->dbbuf_eis) {
259 dma_free_coherent(dev->dev, mem_size,
260 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
261 dev->dbbuf_dbs = NULL;
262 return -ENOMEM;
263 }
264
265 return 0;
266}
267
268static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
269{
2a5bcfdd 270 unsigned int mem_size = nvme_dbbuf_size(dev);
f9f38e33
HK		 271
272 if (dev->dbbuf_dbs) {
273 dma_free_coherent(dev->dev, mem_size,
274 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
275 dev->dbbuf_dbs = NULL;
276 }
277 if (dev->dbbuf_eis) {
278 dma_free_coherent(dev->dev, mem_size,
279 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
280 dev->dbbuf_eis = NULL;
281 }
282}
283
284static void nvme_dbbuf_init(struct nvme_dev *dev,
285 struct nvme_queue *nvmeq, int qid)
286{
287 if (!dev->dbbuf_dbs || !qid)
288 return;
289
290 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
291 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
292 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
293 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
294}
295
0f0d2c87
MI		 296static void nvme_dbbuf_free(struct nvme_queue *nvmeq)
297{
298 if (!nvmeq->qid)
299 return;
300
301 nvmeq->dbbuf_sq_db = NULL;
302 nvmeq->dbbuf_cq_db = NULL;
303 nvmeq->dbbuf_sq_ei = NULL;
304 nvmeq->dbbuf_cq_ei = NULL;
305}
306
f9f38e33
HK		 307static void nvme_dbbuf_set(struct nvme_dev *dev)
308{
309 struct nvme_command c;
0f0d2c87 310 unsigned int i;
f9f38e33
HK		 311
312 if (!dev->dbbuf_dbs)
313 return;
314
315 memset(&c, 0, sizeof(c));
316 c.dbbuf.opcode = nvme_admin_dbbuf;
317 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
318 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
319
320 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
9bdcfb10 321 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
f9f38e33
HK		 322 /* Free memory and continue on */
323 nvme_dbbuf_dma_free(dev);
0f0d2c87
MI		 324
325 for (i = 1; i <= dev->online_queues; i++)
326 nvme_dbbuf_free(&dev->queues[i]);
f9f38e33
HK		 327 }
328}
329
330static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
331{
332 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
333}
334
335/* Update dbbuf and return true if an MMIO is required */
336static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
337 volatile u32 *dbbuf_ei)
338{
339 if (dbbuf_db) {
340 u16 old_value;
341
342 /*
343 * Ensure that the queue is written before updating
344 * the doorbell in memory
345 */
346 wmb();
347
348 old_value = *dbbuf_db;
349 *dbbuf_db = value;
350
f1ed3df2
MW		 351 /*
352 * Ensure that the doorbell is updated before reading the event
353 * index from memory. The controller needs to provide similar
354 * ordering to ensure the envent index is updated before reading
355 * the doorbell.
356 */
357 mb();
358
f9f38e33
HK		 359 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value))
360 return false;
361 }
362
363 return true;
b60503ba
MW		 364}
365
ac3dd5bd
JA		 366/*
367 * Will slightly overestimate the number of pages needed. This is OK
368 * as it only leads to a small amount of wasted memory for the lifetime of
369 * the I/O.
370 */
b13c6393 371static int nvme_pci_npages_prp(void)
ac3dd5bd 372{
b13c6393 373 unsigned nprps = DIV_ROUND_UP(NVME_MAX_KB_SZ + NVME_CTRL_PAGE_SIZE,
6c3c05b0 374 NVME_CTRL_PAGE_SIZE);
ac3dd5bd
JA		 375 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
376}
377
a7a7cbe3
CK		 378/*
379 * Calculates the number of pages needed for the SGL segments. For example a 4k
380 * page can accommodate 256 SGL descriptors.
381 */
b13c6393 382static int nvme_pci_npages_sgl(void)
ac3dd5bd 383{
b13c6393
CK		 384 return DIV_ROUND_UP(NVME_MAX_SEGS * sizeof(struct nvme_sgl_desc),
385 PAGE_SIZE);
f4800d6d 386}
ac3dd5bd 387
b13c6393 388static size_t nvme_pci_iod_alloc_size(void)
f4800d6d 389{
b13c6393 390 size_t npages = max(nvme_pci_npages_prp(), nvme_pci_npages_sgl());
a7a7cbe3 391
b13c6393
CK		 392 return sizeof(__le64 *) * npages +
393 sizeof(struct scatterlist) * NVME_MAX_SEGS;
f4800d6d 394}
ac3dd5bd 395
a4aea562
MB		 396static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
397 unsigned int hctx_idx)
e85248e5 398{
a4aea562 399 struct nvme_dev *dev = data;
147b27e4 400 struct nvme_queue *nvmeq = &dev->queues[0];
a4aea562 401
42483228
KB		 402 WARN_ON(hctx_idx != 0);
403 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
42483228 404
a4aea562
MB		 405 hctx->driver_data = nvmeq;
406 return 0;
e85248e5
MW		 407}
408
a4aea562
MB		 409static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
410 unsigned int hctx_idx)
b60503ba 411{
a4aea562 412 struct nvme_dev *dev = data;
147b27e4 413 struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
a4aea562 414
42483228 415 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
a4aea562
MB		 416 hctx->driver_data = nvmeq;
417 return 0;
b60503ba
MW		 418}
419
d6296d39
CH		 420static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req,
421 unsigned int hctx_idx, unsigned int numa_node)
b60503ba 422{
d6296d39 423 struct nvme_dev *dev = set->driver_data;
f4800d6d 424 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
0350815a 425 int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0;
147b27e4 426 struct nvme_queue *nvmeq = &dev->queues[queue_idx];
a4aea562
MB		 427
428 BUG_ON(!nvmeq);
f4800d6d 429 iod->nvmeq = nvmeq;
59e29ce6
SG		 430
431 nvme_req(req)->ctrl = &dev->ctrl;
a4aea562
MB		 432 return 0;
433}
434
3b6592f7
JA		 435static int queue_irq_offset(struct nvme_dev *dev)
436{
437 /* if we have more than 1 vec, admin queue offsets us by 1 */
438 if (dev->num_vecs > 1)
439 return 1;
440
441 return 0;
442}
443
dca51e78
CH		 444static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
445{
446 struct nvme_dev *dev = set->driver_data;
3b6592f7
JA		 447 int i, qoff, offset;
448
449 offset = queue_irq_offset(dev);
450 for (i = 0, qoff = 0; i < set->nr_maps; i++) {
451 struct blk_mq_queue_map *map = &set->map[i];
452
453 map->nr_queues = dev->io_queues[i];
454 if (!map->nr_queues) {
e20ba6e1 455 BUG_ON(i == HCTX_TYPE_DEFAULT);
7e849dd9 456 continue;
3b6592f7
JA		 457 }
458
4b04cc6a
JA		 459 /*
460 * The poll queue(s) doesn't have an IRQ (and hence IRQ
461 * affinity), so use the regular blk-mq cpu mapping
462 */
3b6592f7 463 map->queue_offset = qoff;
cb9e0e50 464 if (i != HCTX_TYPE_POLL && offset)
4b04cc6a
JA		 465 blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset);
466 else
467 blk_mq_map_queues(map);
3b6592f7
JA		 468 qoff += map->nr_queues;
469 offset += map->nr_queues;
470 }
471
472 return 0;
dca51e78
CH		 473}
474
38210800
KB		 475/*
476 * Write sq tail if we are asked to, or if the next command would wrap.
477 */
478static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq)
04f3eafd 479{
38210800
KB		 480 if (!write_sq) {
481 u16 next_tail = nvmeq->sq_tail + 1;
482
483 if (next_tail == nvmeq->q_depth)
484 next_tail = 0;
485 if (next_tail != nvmeq->last_sq_tail)
486 return;
487 }
488
04f3eafd
JA		 489 if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail,
490 nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei))
491 writel(nvmeq->sq_tail, nvmeq->q_db);
38210800 492 nvmeq->last_sq_tail = nvmeq->sq_tail;
04f3eafd
JA		 493}
494
b60503ba 495/**
90ea5ca4 496 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
b60503ba
MW		 497 * @nvmeq: The queue to use
498 * @cmd: The command to send
04f3eafd 499 * @write_sq: whether to write to the SQ doorbell
b60503ba 500 */
04f3eafd
JA		 501static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd,
502 bool write_sq)
b60503ba 503{
90ea5ca4 504 spin_lock(&nvmeq->sq_lock);
c1e0cc7e
BH		 505 memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes),
506 cmd, sizeof(*cmd));
90ea5ca4
CH		 507 if (++nvmeq->sq_tail == nvmeq->q_depth)
508 nvmeq->sq_tail = 0;
38210800 509 nvme_write_sq_db(nvmeq, write_sq);
04f3eafd
JA		 510 spin_unlock(&nvmeq->sq_lock);
511}
512
513static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx)
514{
515 struct nvme_queue *nvmeq = hctx->driver_data;
516
517 spin_lock(&nvmeq->sq_lock);
38210800
KB		 518 if (nvmeq->sq_tail != nvmeq->last_sq_tail)
519 nvme_write_sq_db(nvmeq, true);
90ea5ca4 520 spin_unlock(&nvmeq->sq_lock);
b60503ba
MW		 521}
522
a7a7cbe3 523static void **nvme_pci_iod_list(struct request *req)
b60503ba 524{
f4800d6d 525 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3 526 return (void **)(iod->sg + blk_rq_nr_phys_segments(req));
b60503ba
MW		 527}
528
955b1b5a
MI		 529static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req)
530{
531 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
20469a37 532 int nseg = blk_rq_nr_phys_segments(req);
955b1b5a
MI		 533 unsigned int avg_seg_size;
534
20469a37 535 avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
955b1b5a
MI		 536
537 if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1))))
538 return false;
539 if (!iod->nvmeq->qid)
540 return false;
541 if (!sgl_threshold || avg_seg_size < sgl_threshold)
542 return false;
543 return true;
544}
545
9275c206 546static void nvme_free_prps(struct nvme_dev *dev, struct request *req)
b60503ba 547{
6c3c05b0 548 const int last_prp = NVME_CTRL_PAGE_SIZE / sizeof(__le64) - 1;
9275c206
CH		 549 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
550 dma_addr_t dma_addr = iod->first_dma;
eca18b23 551 int i;
eca18b23 552
9275c206
CH		 553 for (i = 0; i < iod->npages; i++) {
554 __le64 *prp_list = nvme_pci_iod_list(req)[i];
555 dma_addr_t next_dma_addr = le64_to_cpu(prp_list[last_prp]);
556
557 dma_pool_free(dev->prp_page_pool, prp_list, dma_addr);
558 dma_addr = next_dma_addr;
7fe07d14
CH		 559 }
560
9275c206 561}
dff824b2 562
9275c206
CH		 563static void nvme_free_sgls(struct nvme_dev *dev, struct request *req)
564{
565 const int last_sg = SGES_PER_PAGE - 1;
566 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
567 dma_addr_t dma_addr = iod->first_dma;
568 int i;
dff824b2 569
9275c206
CH		 570 for (i = 0; i < iod->npages; i++) {
571 struct nvme_sgl_desc *sg_list = nvme_pci_iod_list(req)[i];
572 dma_addr_t next_dma_addr = le64_to_cpu((sg_list[last_sg]).addr);
dff824b2 573
9275c206
CH		 574 dma_pool_free(dev->prp_page_pool, sg_list, dma_addr);
575 dma_addr = next_dma_addr;
576 }
a7a7cbe3 577
9275c206 578}
a7a7cbe3 579
9275c206
CH		 580static void nvme_unmap_sg(struct nvme_dev *dev, struct request *req)
581{
582 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3 583
9275c206
CH		 584 if (is_pci_p2pdma_page(sg_page(iod->sg)))
585 pci_p2pdma_unmap_sg(dev->dev, iod->sg, iod->nents,
586 rq_dma_dir(req));
587 else
588 dma_unmap_sg(dev->dev, iod->sg, iod->nents, rq_dma_dir(req));
589}
a7a7cbe3 590
9275c206
CH		 591static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
592{
593 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3 594
9275c206
CH		 595 if (iod->dma_len) {
596 dma_unmap_page(dev->dev, iod->first_dma, iod->dma_len,
597 rq_dma_dir(req));
598 return;
eca18b23 599 }
ac3dd5bd 600
9275c206
CH		 601 WARN_ON_ONCE(!iod->nents);
602
603 nvme_unmap_sg(dev, req);
604 if (iod->npages == 0)
605 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0],
606 iod->first_dma);
607 else if (iod->use_sgl)
608 nvme_free_sgls(dev, req);
609 else
610 nvme_free_prps(dev, req);
d43f1ccf 611 mempool_free(iod->sg, dev->iod_mempool);
b4ff9c8d
KB		 612}
613
d0877473
KB		 614static void nvme_print_sgl(struct scatterlist *sgl, int nents)
615{
616 int i;
617 struct scatterlist *sg;
618
619 for_each_sg(sgl, sg, nents, i) {
620 dma_addr_t phys = sg_phys(sg);
621 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
622 "dma_address:%pad dma_length:%d\n",
623 i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
624 sg_dma_len(sg));
625 }
626}
627
a7a7cbe3
CK		 628static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
629 struct request *req, struct nvme_rw_command *cmnd)
ff22b54f 630{
f4800d6d 631 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
99802a7a 632 struct dma_pool *pool;
b131c61d 633 int length = blk_rq_payload_bytes(req);
eca18b23 634 struct scatterlist *sg = iod->sg;
ff22b54f
MW		 635 int dma_len = sg_dma_len(sg);
636 u64 dma_addr = sg_dma_address(sg);
6c3c05b0 637 int offset = dma_addr & (NVME_CTRL_PAGE_SIZE - 1);
e025344c 638 __le64 *prp_list;
a7a7cbe3 639 void **list = nvme_pci_iod_list(req);
e025344c 640 dma_addr_t prp_dma;
eca18b23 641 int nprps, i;
ff22b54f 642
6c3c05b0 643 length -= (NVME_CTRL_PAGE_SIZE - offset);
5228b328
JS		 644 if (length <= 0) {
645 iod->first_dma = 0;
a7a7cbe3 646 goto done;
5228b328 647 }
ff22b54f 648
6c3c05b0 649 dma_len -= (NVME_CTRL_PAGE_SIZE - offset);
ff22b54f 650 if (dma_len) {
6c3c05b0 651 dma_addr += (NVME_CTRL_PAGE_SIZE - offset);
ff22b54f
MW		 652 } else {
653 sg = sg_next(sg);
654 dma_addr = sg_dma_address(sg);
655 dma_len = sg_dma_len(sg);
656 }
657
6c3c05b0 658 if (length <= NVME_CTRL_PAGE_SIZE) {
edd10d33 659 iod->first_dma = dma_addr;
a7a7cbe3 660 goto done;
e025344c
SMM		 661 }
662
6c3c05b0 663 nprps = DIV_ROUND_UP(length, NVME_CTRL_PAGE_SIZE);
99802a7a
MW		 664 if (nprps <= (256 / 8)) {
665 pool = dev->prp_small_pool;
eca18b23 666 iod->npages = 0;
99802a7a
MW		 667 } else {
668 pool = dev->prp_page_pool;
eca18b23 669 iod->npages = 1;
99802a7a
MW		 670 }
671
69d2b571 672 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
b77954cb 673 if (!prp_list) {
edd10d33 674 iod->first_dma = dma_addr;
eca18b23 675 iod->npages = -1;
86eea289 676 return BLK_STS_RESOURCE;
b77954cb 677 }
eca18b23
MW		 678 list[0] = prp_list;
679 iod->first_dma = prp_dma;
e025344c
SMM		 680 i = 0;
681 for (;;) {
6c3c05b0 682 if (i == NVME_CTRL_PAGE_SIZE >> 3) {
e025344c 683 __le64 *old_prp_list = prp_list;
69d2b571 684 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
eca18b23 685 if (!prp_list)
fa073216 686 goto free_prps;
eca18b23 687 list[iod->npages++] = prp_list;
7523d834
MW		 688 prp_list[0] = old_prp_list[i - 1];
689 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
690 i = 1;
e025344c
SMM		 691 }
692 prp_list[i++] = cpu_to_le64(dma_addr);
6c3c05b0
CK		 693 dma_len -= NVME_CTRL_PAGE_SIZE;
694 dma_addr += NVME_CTRL_PAGE_SIZE;
695 length -= NVME_CTRL_PAGE_SIZE;
e025344c
SMM		 696 if (length <= 0)
697 break;
698 if (dma_len > 0)
699 continue;
86eea289
KB		 700 if (unlikely(dma_len < 0))
701 goto bad_sgl;
e025344c
SMM		 702 sg = sg_next(sg);
703 dma_addr = sg_dma_address(sg);
704 dma_len = sg_dma_len(sg);
ff22b54f 705 }
a7a7cbe3
CK		 706done:
707 cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
708 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
86eea289 709 return BLK_STS_OK;
fa073216
CH		 710free_prps:
711 nvme_free_prps(dev, req);
712 return BLK_STS_RESOURCE;
713bad_sgl:
d0877473
KB		 714 WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents),
715 "Invalid SGL for payload:%d nents:%d\n",
716 blk_rq_payload_bytes(req), iod->nents);
86eea289 717 return BLK_STS_IOERR;
ff22b54f
MW		 718}
719
a7a7cbe3
CK		 720static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
721 struct scatterlist *sg)
722{
723 sge->addr = cpu_to_le64(sg_dma_address(sg));
724 sge->length = cpu_to_le32(sg_dma_len(sg));
725 sge->type = NVME_SGL_FMT_DATA_DESC << 4;
726}
727
728static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
729 dma_addr_t dma_addr, int entries)
730{
731 sge->addr = cpu_to_le64(dma_addr);
732 if (entries < SGES_PER_PAGE) {
733 sge->length = cpu_to_le32(entries * sizeof(*sge));
734 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
735 } else {
736 sge->length = cpu_to_le32(PAGE_SIZE);
737 sge->type = NVME_SGL_FMT_SEG_DESC << 4;
738 }
739}
740
741static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
b0f2853b 742 struct request *req, struct nvme_rw_command *cmd, int entries)
a7a7cbe3
CK		 743{
744 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3
CK		 745 struct dma_pool *pool;
746 struct nvme_sgl_desc *sg_list;
747 struct scatterlist *sg = iod->sg;
a7a7cbe3 748 dma_addr_t sgl_dma;
b0f2853b 749 int i = 0;
a7a7cbe3 750
a7a7cbe3
CK		 751 /* setting the transfer type as SGL */
752 cmd->flags = NVME_CMD_SGL_METABUF;
753
b0f2853b 754 if (entries == 1) {
a7a7cbe3
CK		 755 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
756 return BLK_STS_OK;
757 }
758
759 if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
760 pool = dev->prp_small_pool;
761 iod->npages = 0;
762 } else {
763 pool = dev->prp_page_pool;
764 iod->npages = 1;
765 }
766
767 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
768 if (!sg_list) {
769 iod->npages = -1;
770 return BLK_STS_RESOURCE;
771 }
772
773 nvme_pci_iod_list(req)[0] = sg_list;
774 iod->first_dma = sgl_dma;
775
776 nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
777
778 do {
779 if (i == SGES_PER_PAGE) {
780 struct nvme_sgl_desc *old_sg_desc = sg_list;
781 struct nvme_sgl_desc *link = &old_sg_desc[i - 1];
782
783 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
784 if (!sg_list)
fa073216 785 goto free_sgls;
a7a7cbe3
CK		 786
787 i = 0;
788 nvme_pci_iod_list(req)[iod->npages++] = sg_list;
789 sg_list[i++] = *link;
790 nvme_pci_sgl_set_seg(link, sgl_dma, entries);
791 }
792
793 nvme_pci_sgl_set_data(&sg_list[i++], sg);
a7a7cbe3 794 sg = sg_next(sg);
b0f2853b 795 } while (--entries > 0);
a7a7cbe3 796
a7a7cbe3 797 return BLK_STS_OK;
fa073216
CH		 798free_sgls:
799 nvme_free_sgls(dev, req);
800 return BLK_STS_RESOURCE;
a7a7cbe3
CK		 801}
802
dff824b2
CH		 803static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev,
804 struct request *req, struct nvme_rw_command *cmnd,
805 struct bio_vec *bv)
806{
807 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
6c3c05b0
CK		 808 unsigned int offset = bv->bv_offset & (NVME_CTRL_PAGE_SIZE - 1);
809 unsigned int first_prp_len = NVME_CTRL_PAGE_SIZE - offset;
dff824b2
CH		 810
811 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
812 if (dma_mapping_error(dev->dev, iod->first_dma))
813 return BLK_STS_RESOURCE;
814 iod->dma_len = bv->bv_len;
815
816 cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma);
817 if (bv->bv_len > first_prp_len)
818 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len);
359c1f88 819 return BLK_STS_OK;
dff824b2
CH		 820}
821
29791057
CH		 822static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev,
823 struct request *req, struct nvme_rw_command *cmnd,
824 struct bio_vec *bv)
825{
826 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
827
828 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
829 if (dma_mapping_error(dev->dev, iod->first_dma))
830 return BLK_STS_RESOURCE;
831 iod->dma_len = bv->bv_len;
832
049bf372 833 cmnd->flags = NVME_CMD_SGL_METABUF;
29791057
CH		 834 cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma);
835 cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len);
836 cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4;
359c1f88 837 return BLK_STS_OK;
29791057
CH		 838}
839
fc17b653 840static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
b131c61d 841 struct nvme_command *cmnd)
d29ec824 842{
f4800d6d 843 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
70479b71 844 blk_status_t ret = BLK_STS_RESOURCE;
b0f2853b 845 int nr_mapped;
d29ec824 846
dff824b2
CH		 847 if (blk_rq_nr_phys_segments(req) == 1) {
848 struct bio_vec bv = req_bvec(req);
849
850 if (!is_pci_p2pdma_page(bv.bv_page)) {
6c3c05b0 851 if (bv.bv_offset + bv.bv_len <= NVME_CTRL_PAGE_SIZE * 2)
dff824b2
CH		 852 return nvme_setup_prp_simple(dev, req,
853 &cmnd->rw, &bv);
29791057
CH		 854
855 if (iod->nvmeq->qid &&
856 dev->ctrl.sgls & ((1 << 0) | (1 << 1)))
857 return nvme_setup_sgl_simple(dev, req,
858 &cmnd->rw, &bv);
dff824b2
CH		 859 }
860 }
861
862 iod->dma_len = 0;
d43f1ccf
CH		 863 iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC);
864 if (!iod->sg)
865 return BLK_STS_RESOURCE;
f9d03f96 866 sg_init_table(iod->sg, blk_rq_nr_phys_segments(req));
70479b71 867 iod->nents = blk_rq_map_sg(req->q, req, iod->sg);
ba1ca37e 868 if (!iod->nents)
fa073216 869 goto out_free_sg;
d29ec824 870
e0596ab2 871 if (is_pci_p2pdma_page(sg_page(iod->sg)))
2b9f4bb2
LG		 872 nr_mapped = pci_p2pdma_map_sg_attrs(dev->dev, iod->sg,
873 iod->nents, rq_dma_dir(req), DMA_ATTR_NO_WARN);
e0596ab2
LG		 874 else
875 nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents,
70479b71 876 rq_dma_dir(req), DMA_ATTR_NO_WARN);
b0f2853b 877 if (!nr_mapped)
fa073216 878 goto out_free_sg;
d29ec824 879
70479b71 880 iod->use_sgl = nvme_pci_use_sgls(dev, req);
955b1b5a 881 if (iod->use_sgl)
b0f2853b 882 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped);
a7a7cbe3
CK		 883 else
884 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
86eea289 885 if (ret != BLK_STS_OK)
fa073216
CH		 886 goto out_unmap_sg;
887 return BLK_STS_OK;
888
889out_unmap_sg:
890 nvme_unmap_sg(dev, req);
891out_free_sg:
892 mempool_free(iod->sg, dev->iod_mempool);
4aedb705
CH		 893 return ret;
894}
3045c0d0 895
4aedb705
CH		 896static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req,
897 struct nvme_command *cmnd)
898{
899 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
00df5cb4 900
4aedb705
CH		 901 iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req),
902 rq_dma_dir(req), 0);
903 if (dma_mapping_error(dev->dev, iod->meta_dma))
904 return BLK_STS_IOERR;
905 cmnd->rw.metadata = cpu_to_le64(iod->meta_dma);
359c1f88 906 return BLK_STS_OK;
00df5cb4
MW		 907}
908
d29ec824
CH		 909/*
910 * NOTE: ns is NULL when called on the admin queue.
911 */
fc17b653 912static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
a4aea562 913 const struct blk_mq_queue_data *bd)
edd10d33 914{
a4aea562
MB		 915 struct nvme_ns *ns = hctx->queue->queuedata;
916 struct nvme_queue *nvmeq = hctx->driver_data;
d29ec824 917 struct nvme_dev *dev = nvmeq->dev;
a4aea562 918 struct request *req = bd->rq;
9b048119 919 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
ba1ca37e 920 struct nvme_command cmnd;
ebe6d874 921 blk_status_t ret;
e1e5e564 922
9b048119
CH		 923 iod->aborted = 0;
924 iod->npages = -1;
925 iod->nents = 0;
926
d1f06f4a
JA		 927 /*
928 * We should not need to do this, but we're still using this to
929 * ensure we can drain requests on a dying queue.
930 */
4e224106 931 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
d1f06f4a
JA		 932 return BLK_STS_IOERR;
933
f9d03f96 934 ret = nvme_setup_cmd(ns, req, &cmnd);
fc17b653 935 if (ret)
f4800d6d 936 return ret;
a4aea562 937
fc17b653 938 if (blk_rq_nr_phys_segments(req)) {
b131c61d 939 ret = nvme_map_data(dev, req, &cmnd);
fc17b653 940 if (ret)
9b048119 941 goto out_free_cmd;
fc17b653 942 }
a4aea562 943
4aedb705
CH		 944 if (blk_integrity_rq(req)) {
945 ret = nvme_map_metadata(dev, req, &cmnd);
946 if (ret)
947 goto out_unmap_data;
948 }
949
aae239e1 950 blk_mq_start_request(req);
04f3eafd 951 nvme_submit_cmd(nvmeq, &cmnd, bd->last);
fc17b653 952 return BLK_STS_OK;
4aedb705
CH		 953out_unmap_data:
954 nvme_unmap_data(dev, req);
f9d03f96
CH		 955out_free_cmd:
956 nvme_cleanup_cmd(req);
ba1ca37e 957 return ret;
b60503ba 958}
e1e5e564 959
77f02a7a 960static void nvme_pci_complete_rq(struct request *req)
eee417b0 961{
f4800d6d 962 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
4aedb705 963 struct nvme_dev *dev = iod->nvmeq->dev;
a4aea562 964
4aedb705
CH		 965 if (blk_integrity_rq(req))
966 dma_unmap_page(dev->dev, iod->meta_dma,
967 rq_integrity_vec(req)->bv_len, rq_data_dir(req));
b15c592d 968 if (blk_rq_nr_phys_segments(req))
4aedb705 969 nvme_unmap_data(dev, req);
77f02a7a 970 nvme_complete_rq(req);
b60503ba
MW		 971}
972
d783e0bd 973/* We read the CQE phase first to check if the rest of the entry is valid */
750dde44 974static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq)
d783e0bd 975{
74943d45
KB		 976 struct nvme_completion *hcqe = &nvmeq->cqes[nvmeq->cq_head];
977
978 return (le16_to_cpu(READ_ONCE(hcqe->status)) & 1) == nvmeq->cq_phase;
d783e0bd
MR		 979}
980
eb281c82 981static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
b60503ba 982{
eb281c82 983 u16 head = nvmeq->cq_head;
adf68f21 984
397c699f
KB		 985 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
986 nvmeq->dbbuf_cq_ei))
987 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
eb281c82 988}
aae239e1 989
cfa27356
CH		 990static inline struct blk_mq_tags *nvme_queue_tagset(struct nvme_queue *nvmeq)
991{
992 if (!nvmeq->qid)
993 return nvmeq->dev->admin_tagset.tags[0];
994 return nvmeq->dev->tagset.tags[nvmeq->qid - 1];
995}
996
5cb525c8 997static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx)
83a12fb7 998{
74943d45 999 struct nvme_completion *cqe = &nvmeq->cqes[idx];
62df8016 1000 __u16 command_id = READ_ONCE(cqe->command_id);
83a12fb7 1001 struct request *req;
adf68f21 1002
83a12fb7
SG		 1003 /*
1004 * AEN requests are special as they don't time out and can
1005 * survive any kind of queue freeze and often don't respond to
1006 * aborts. We don't even bother to allocate a struct request
1007 * for them but rather special case them here.
1008 */
62df8016 1009 if (unlikely(nvme_is_aen_req(nvmeq->qid, command_id))) {
83a12fb7
SG		 1010 nvme_complete_async_event(&nvmeq->dev->ctrl,
1011 cqe->status, &cqe->result);
a0fa9647 1012 return;
83a12fb7 1013 }
b60503ba 1014
62df8016 1015 req = blk_mq_tag_to_rq(nvme_queue_tagset(nvmeq), command_id);
50b7c243
XT		 1016 if (unlikely(!req)) {
1017 dev_warn(nvmeq->dev->ctrl.device,
1018 "invalid id %d completed on queue %d\n",
62df8016 1019 command_id, le16_to_cpu(cqe->sq_id));
50b7c243
XT		 1020 return;
1021 }
1022
604c01d5 1023 trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail);
2eb81a33 1024 if (!nvme_try_complete_req(req, cqe->status, cqe->result))
ff029451 1025 nvme_pci_complete_rq(req);
83a12fb7 1026}
b60503ba 1027
5cb525c8
JA		 1028static inline void nvme_update_cq_head(struct nvme_queue *nvmeq)
1029{
a8de6639
AD		 1030 u16 tmp = nvmeq->cq_head + 1;
1031
1032 if (tmp == nvmeq->q_depth) {
5cb525c8 1033 nvmeq->cq_head = 0;
e2a366a4 1034 nvmeq->cq_phase ^= 1;
a8de6639
AD		 1035 } else {
1036 nvmeq->cq_head = tmp;
b60503ba 1037 }
a0fa9647
JA		 1038}
1039
324b494c 1040static inline int nvme_process_cq(struct nvme_queue *nvmeq)
a0fa9647 1041{
1052b8ac 1042 int found = 0;
b60503ba 1043
1052b8ac 1044 while (nvme_cqe_pending(nvmeq)) {
bf392a5d 1045 found++;
b69e2ef2
KB		 1046 /*
1047 * load-load control dependency between phase and the rest of
1048 * the cqe requires a full read memory barrier
1049 */
1050 dma_rmb();
324b494c 1051 nvme_handle_cqe(nvmeq, nvmeq->cq_head);
5cb525c8 1052 nvme_update_cq_head(nvmeq);
920d13a8 1053 }
eb281c82 1054
324b494c 1055 if (found)
920d13a8 1056 nvme_ring_cq_doorbell(nvmeq);
5cb525c8 1057 return found;
b60503ba
MW		 1058}
1059
1060static irqreturn_t nvme_irq(int irq, void *data)
58ffacb5 1061{
58ffacb5 1062 struct nvme_queue *nvmeq = data;
68fa9dbe 1063 irqreturn_t ret = IRQ_NONE;
5cb525c8 1064
3a7afd8e
CH		 1065 /*
1066 * The rmb/wmb pair ensures we see all updates from a previous run of
1067 * the irq handler, even if that was on another CPU.
1068 */
1069 rmb();
324b494c
KB		 1070 if (nvme_process_cq(nvmeq))
1071 ret = IRQ_HANDLED;
3a7afd8e 1072 wmb();
5cb525c8 1073
68fa9dbe 1074 return ret;
58ffacb5
MW		 1075}
1076
1077static irqreturn_t nvme_irq_check(int irq, void *data)
1078{
1079 struct nvme_queue *nvmeq = data;
4e523547 1080
750dde44 1081 if (nvme_cqe_pending(nvmeq))
d783e0bd
MR		 1082 return IRQ_WAKE_THREAD;
1083 return IRQ_NONE;
58ffacb5
MW		 1084}
1085
0b2a8a9f 1086/*
fa059b85 1087 * Poll for completions for any interrupt driven queue
0b2a8a9f
CH		 1088 * Can be called from any context.
1089 */
fa059b85 1090static void nvme_poll_irqdisable(struct nvme_queue *nvmeq)
a0fa9647 1091{
3a7afd8e 1092 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
a0fa9647 1093
fa059b85 1094 WARN_ON_ONCE(test_bit(NVMEQ_POLLED, &nvmeq->flags));
442e19b7 1095
fa059b85
KB		 1096 disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1097 nvme_process_cq(nvmeq);
1098 enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
a0fa9647
JA		 1099}
1100
9743139c 1101static int nvme_poll(struct blk_mq_hw_ctx *hctx)
dabcefab
JA		 1102{
1103 struct nvme_queue *nvmeq = hctx->driver_data;
dabcefab
JA		 1104 bool found;
1105
1106 if (!nvme_cqe_pending(nvmeq))
1107 return 0;
1108
3a7afd8e 1109 spin_lock(&nvmeq->cq_poll_lock);
324b494c 1110 found = nvme_process_cq(nvmeq);
3a7afd8e 1111 spin_unlock(&nvmeq->cq_poll_lock);
dabcefab 1112
dabcefab
JA		 1113 return found;
1114}
1115
ad22c355 1116static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
b60503ba 1117{
f866fc42 1118 struct nvme_dev *dev = to_nvme_dev(ctrl);
147b27e4 1119 struct nvme_queue *nvmeq = &dev->queues[0];
a4aea562 1120 struct nvme_command c;
b60503ba 1121
a4aea562
MB		 1122 memset(&c, 0, sizeof(c));
1123 c.common.opcode = nvme_admin_async_event;
ad22c355 1124 c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
04f3eafd 1125 nvme_submit_cmd(nvmeq, &c, true);
f705f837
CH		 1126}
1127
b60503ba 1128static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
f705f837 1129{
b60503ba
MW		 1130 struct nvme_command c;
1131
1132 memset(&c, 0, sizeof(c));
1133 c.delete_queue.opcode = opcode;
1134 c.delete_queue.qid = cpu_to_le16(id);
1135
1c63dc66 1136 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1137}
1138
b60503ba 1139static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
a8e3e0bb 1140 struct nvme_queue *nvmeq, s16 vector)
b60503ba 1141{
b60503ba 1142 struct nvme_command c;
4b04cc6a
JA		 1143 int flags = NVME_QUEUE_PHYS_CONTIG;
1144
7c349dde 1145 if (!test_bit(NVMEQ_POLLED, &nvmeq->flags))
4b04cc6a 1146 flags |= NVME_CQ_IRQ_ENABLED;
b60503ba 1147
d29ec824 1148 /*
16772ae6 1149 * Note: we (ab)use the fact that the prp fields survive if no data
d29ec824
CH		 1150 * is attached to the request.
1151 */
b60503ba
MW		 1152 memset(&c, 0, sizeof(c));
1153 c.create_cq.opcode = nvme_admin_create_cq;
1154 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1155 c.create_cq.cqid = cpu_to_le16(qid);
1156 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1157 c.create_cq.cq_flags = cpu_to_le16(flags);
7c349dde 1158 c.create_cq.irq_vector = cpu_to_le16(vector);
b60503ba 1159
1c63dc66 1160 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1161}
1162
1163static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1164 struct nvme_queue *nvmeq)
1165{
9abd68ef 1166 struct nvme_ctrl *ctrl = &dev->ctrl;
b60503ba 1167 struct nvme_command c;
81c1cd98 1168 int flags = NVME_QUEUE_PHYS_CONTIG;
b60503ba 1169
9abd68ef
JA		 1170 /*
1171 * Some drives have a bug that auto-enables WRRU if MEDIUM isn't
1172 * set. Since URGENT priority is zeroes, it makes all queues
1173 * URGENT.
1174 */
1175 if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ)
1176 flags |= NVME_SQ_PRIO_MEDIUM;
1177
d29ec824 1178 /*
16772ae6 1179 * Note: we (ab)use the fact that the prp fields survive if no data
d29ec824
CH		 1180 * is attached to the request.
1181 */
b60503ba
MW		 1182 memset(&c, 0, sizeof(c));
1183 c.create_sq.opcode = nvme_admin_create_sq;
1184 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1185 c.create_sq.sqid = cpu_to_le16(qid);
1186 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1187 c.create_sq.sq_flags = cpu_to_le16(flags);
1188 c.create_sq.cqid = cpu_to_le16(qid);
1189
1c63dc66 1190 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1191}
1192
1193static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1194{
1195 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1196}
1197
1198static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1199{
1200 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1201}
1202
2a842aca 1203static void abort_endio(struct request *req, blk_status_t error)
bc5fc7e4 1204{
f4800d6d
CH		 1205 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1206 struct nvme_queue *nvmeq = iod->nvmeq;
e44ac588 1207
27fa9bc5
CH		 1208 dev_warn(nvmeq->dev->ctrl.device,
1209 "Abort status: 0x%x", nvme_req(req)->status);
e7a2a87d 1210 atomic_inc(&nvmeq->dev->ctrl.abort_limit);
e7a2a87d 1211 blk_mq_free_request(req);
bc5fc7e4
MW		 1212}
1213
b2a0eb1a
KB		 1214static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1215{
b2a0eb1a
KB		 1216 /* If true, indicates loss of adapter communication, possibly by a
1217 * NVMe Subsystem reset.
1218 */
1219 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1220
ad70062c
JW		 1221 /* If there is a reset/reinit ongoing, we shouldn't reset again. */
1222 switch (dev->ctrl.state) {
1223 case NVME_CTRL_RESETTING:
ad6a0a52 1224 case NVME_CTRL_CONNECTING:
b2a0eb1a 1225 return false;
ad70062c
JW		 1226 default:
1227 break;
1228 }
b2a0eb1a
KB		 1229
1230 /* We shouldn't reset unless the controller is on fatal error state
1231 * _or_ if we lost the communication with it.
1232 */
1233 if (!(csts & NVME_CSTS_CFS) && !nssro)
1234 return false;
1235
b2a0eb1a
KB		 1236 return true;
1237}
1238
1239static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1240{
1241 /* Read a config register to help see what died. */
1242 u16 pci_status;
1243 int result;
1244
1245 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1246 &pci_status);
1247 if (result == PCIBIOS_SUCCESSFUL)
1248 dev_warn(dev->ctrl.device,
1249 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1250 csts, pci_status);
1251 else
1252 dev_warn(dev->ctrl.device,
1253 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1254 csts, result);
1255}
1256
31c7c7d2 1257static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
c30341dc 1258{
f4800d6d
CH		 1259 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1260 struct nvme_queue *nvmeq = iod->nvmeq;
c30341dc 1261 struct nvme_dev *dev = nvmeq->dev;
a4aea562 1262 struct request *abort_req;
a4aea562 1263 struct nvme_command cmd;
b2a0eb1a
KB		 1264 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1265
651438bb
WX		 1266 /* If PCI error recovery process is happening, we cannot reset or
1267 * the recovery mechanism will surely fail.
1268 */
1269 mb();
1270 if (pci_channel_offline(to_pci_dev(dev->dev)))
1271 return BLK_EH_RESET_TIMER;
1272
b2a0eb1a
KB		 1273 /*
1274 * Reset immediately if the controller is failed
1275 */
1276 if (nvme_should_reset(dev, csts)) {
1277 nvme_warn_reset(dev, csts);
1278 nvme_dev_disable(dev, false);
d86c4d8e 1279 nvme_reset_ctrl(&dev->ctrl);
db8c48e4 1280 return BLK_EH_DONE;
b2a0eb1a 1281 }
c30341dc 1282
7776db1c
KB		 1283 /*
1284 * Did we miss an interrupt?
1285 */
fa059b85
KB		 1286 if (test_bit(NVMEQ_POLLED, &nvmeq->flags))
1287 nvme_poll(req->mq_hctx);
1288 else
1289 nvme_poll_irqdisable(nvmeq);
1290
bf392a5d 1291 if (blk_mq_request_completed(req)) {
7776db1c
KB		 1292 dev_warn(dev->ctrl.device,
1293 "I/O %d QID %d timeout, completion polled\n",
1294 req->tag, nvmeq->qid);
db8c48e4 1295 return BLK_EH_DONE;
7776db1c
KB		 1296 }
1297
31c7c7d2 1298 /*
fd634f41
CH		 1299 * Shutdown immediately if controller times out while starting. The
1300 * reset work will see the pci device disabled when it gets the forced
1301 * cancellation error. All outstanding requests are completed on
db8c48e4 1302 * shutdown, so we return BLK_EH_DONE.
fd634f41 1303 */
4244140d
KB		 1304 switch (dev->ctrl.state) {
1305 case NVME_CTRL_CONNECTING:
2036f726 1306 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
df561f66 1307 fallthrough;
2036f726 1308 case NVME_CTRL_DELETING:
b9cac43c 1309 dev_warn_ratelimited(dev->ctrl.device,
fd634f41
CH		 1310 "I/O %d QID %d timeout, disable controller\n",
1311 req->tag, nvmeq->qid);
27fa9bc5 1312 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
7ad92f65 1313 nvme_dev_disable(dev, true);
db8c48e4 1314 return BLK_EH_DONE;
39a9dd81
KB		 1315 case NVME_CTRL_RESETTING:
1316 return BLK_EH_RESET_TIMER;
4244140d
KB		 1317 default:
1318 break;
c30341dc
KB		 1319 }
1320
fd634f41 1321 /*
ee0d96d3
BW		 1322 * Shutdown the controller immediately and schedule a reset if the
1323 * command was already aborted once before and still hasn't been
1324 * returned to the driver, or if this is the admin queue.
31c7c7d2 1325 */
f4800d6d 1326 if (!nvmeq->qid || iod->aborted) {
1b3c47c1 1327 dev_warn(dev->ctrl.device,
e1569a16
KB		 1328 "I/O %d QID %d timeout, reset controller\n",
1329 req->tag, nvmeq->qid);
7ad92f65 1330 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
a5cdb68c 1331 nvme_dev_disable(dev, false);
d86c4d8e 1332 nvme_reset_ctrl(&dev->ctrl);
c30341dc 1333
db8c48e4 1334 return BLK_EH_DONE;
c30341dc 1335 }
c30341dc 1336
e7a2a87d 1337 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
6bf25d16 1338 atomic_inc(&dev->ctrl.abort_limit);
31c7c7d2 1339 return BLK_EH_RESET_TIMER;
6bf25d16 1340 }
7bf7d778 1341 iod->aborted = 1;
a4aea562 1342
c30341dc
KB		 1343 memset(&cmd, 0, sizeof(cmd));
1344 cmd.abort.opcode = nvme_admin_abort_cmd;
a4aea562 1345 cmd.abort.cid = req->tag;
c30341dc 1346 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
c30341dc 1347
1b3c47c1
SG		 1348 dev_warn(nvmeq->dev->ctrl.device,
1349 "I/O %d QID %d timeout, aborting\n",
1350 req->tag, nvmeq->qid);
e7a2a87d
CH		 1351
1352 abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
39dfe844 1353 BLK_MQ_REQ_NOWAIT);
e7a2a87d
CH		 1354 if (IS_ERR(abort_req)) {
1355 atomic_inc(&dev->ctrl.abort_limit);
1356 return BLK_EH_RESET_TIMER;
1357 }
1358
e7a2a87d 1359 abort_req->end_io_data = NULL;
8eeed0b5 1360 blk_execute_rq_nowait(NULL, abort_req, 0, abort_endio);
c30341dc 1361
31c7c7d2
CH		 1362 /*
1363 * The aborted req will be completed on receiving the abort req.
1364 * We enable the timer again. If hit twice, it'll cause a device reset,
1365 * as the device then is in a faulty state.
1366 */
1367 return BLK_EH_RESET_TIMER;
c30341dc
KB		 1368}
1369
a4aea562
MB		 1370static void nvme_free_queue(struct nvme_queue *nvmeq)
1371{
8a1d09a6 1372 dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq),
9e866774 1373 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
63223078
CH		 1374 if (!nvmeq->sq_cmds)
1375 return;
0f238ff5 1376
63223078 1377 if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) {
88a041f4 1378 pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev),
8a1d09a6 1379 nvmeq->sq_cmds, SQ_SIZE(nvmeq));
63223078 1380 } else {
8a1d09a6 1381 dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq),
63223078 1382 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
0f238ff5 1383 }
9e866774
MW		 1384}
1385
a1a5ef99 1386static void nvme_free_queues(struct nvme_dev *dev, int lowest)
22404274
KB		 1387{
1388 int i;
1389
d858e5f0 1390 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
d858e5f0 1391 dev->ctrl.queue_count--;
147b27e4 1392 nvme_free_queue(&dev->queues[i]);
121c7ad4 1393 }
22404274
KB		 1394}
1395
4d115420
KB		 1396/**
1397 * nvme_suspend_queue - put queue into suspended state
40581d1a 1398 * @nvmeq: queue to suspend
4d115420
KB		 1399 */
1400static int nvme_suspend_queue(struct nvme_queue *nvmeq)
b60503ba 1401{
4e224106 1402 if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags))
2b25d981 1403 return 1;
a09115b2 1404
4e224106 1405 /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */
d1f06f4a 1406 mb();
a09115b2 1407
4e224106 1408 nvmeq->dev->online_queues--;
1c63dc66 1409 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
c81545f9 1410 blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q);
7c349dde
KB		 1411 if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags))
1412 pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq);
4d115420
KB		 1413 return 0;
1414}
b60503ba 1415
8fae268b
KB		 1416static void nvme_suspend_io_queues(struct nvme_dev *dev)
1417{
1418 int i;
1419
1420 for (i = dev->ctrl.queue_count - 1; i > 0; i--)
1421 nvme_suspend_queue(&dev->queues[i]);
1422}
1423
a5cdb68c 1424static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
4d115420 1425{
147b27e4 1426 struct nvme_queue *nvmeq = &dev->queues[0];
4d115420 1427
a5cdb68c
KB		 1428 if (shutdown)
1429 nvme_shutdown_ctrl(&dev->ctrl);
1430 else
b5b05048 1431 nvme_disable_ctrl(&dev->ctrl);
07836e65 1432
bf392a5d 1433 nvme_poll_irqdisable(nvmeq);
b60503ba
MW		 1434}
1435
fa46c6fb
KB		 1436/*
1437 * Called only on a device that has been disabled and after all other threads
9210c075
DZ		 1438 * that can check this device's completion queues have synced, except
1439 * nvme_poll(). This is the last chance for the driver to see a natural
1440 * completion before nvme_cancel_request() terminates all incomplete requests.
fa46c6fb
KB		 1441 */
1442static void nvme_reap_pending_cqes(struct nvme_dev *dev)
1443{
fa46c6fb
KB		 1444 int i;
1445
9210c075
DZ		 1446 for (i = dev->ctrl.queue_count - 1; i > 0; i--) {
1447 spin_lock(&dev->queues[i].cq_poll_lock);
324b494c 1448 nvme_process_cq(&dev->queues[i]);
9210c075
DZ		 1449 spin_unlock(&dev->queues[i].cq_poll_lock);
1450 }
fa46c6fb
KB		 1451}
1452
8ffaadf7
JD		 1453static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1454 int entry_size)
1455{
1456 int q_depth = dev->q_depth;
5fd4ce1b 1457 unsigned q_size_aligned = roundup(q_depth * entry_size,
6c3c05b0 1458 NVME_CTRL_PAGE_SIZE);
8ffaadf7
JD		 1459
1460 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
c45f5c99 1461 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
4e523547 1462
6c3c05b0 1463 mem_per_q = round_down(mem_per_q, NVME_CTRL_PAGE_SIZE);
c45f5c99 1464 q_depth = div_u64(mem_per_q, entry_size);
8ffaadf7
JD		 1465
1466 /*
1467 * Ensure the reduced q_depth is above some threshold where it
1468 * would be better to map queues in system memory with the
1469 * original depth
1470 */
1471 if (q_depth < 64)
1472 return -ENOMEM;
1473 }
1474
1475 return q_depth;
1476}
1477
1478static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
8a1d09a6 1479 int qid)
8ffaadf7 1480{
0f238ff5
LG		 1481 struct pci_dev *pdev = to_pci_dev(dev->dev);
1482
1483 if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
8a1d09a6 1484 nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq));
bfac8e9f
AM		 1485 if (nvmeq->sq_cmds) {
1486 nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev,
1487 nvmeq->sq_cmds);
1488 if (nvmeq->sq_dma_addr) {
1489 set_bit(NVMEQ_SQ_CMB, &nvmeq->flags);
1490 return 0;
1491 }
1492
8a1d09a6 1493 pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq));
63223078 1494 }
0f238ff5 1495 }
8ffaadf7 1496
8a1d09a6 1497 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq),
63223078 1498 &nvmeq->sq_dma_addr, GFP_KERNEL);
815c6704
KB		 1499 if (!nvmeq->sq_cmds)
1500 return -ENOMEM;
8ffaadf7
JD		 1501 return 0;
1502}
1503
a6ff7262 1504static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
b60503ba 1505{
147b27e4 1506 struct nvme_queue *nvmeq = &dev->queues[qid];
b60503ba 1507
62314e40
KB		 1508 if (dev->ctrl.queue_count > qid)
1509 return 0;
b60503ba 1510
c1e0cc7e 1511 nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES;
8a1d09a6
BH		 1512 nvmeq->q_depth = depth;
1513 nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq),
750afb08 1514 &nvmeq->cq_dma_addr, GFP_KERNEL);
b60503ba
MW		 1515 if (!nvmeq->cqes)
1516 goto free_nvmeq;
b60503ba 1517
8a1d09a6 1518 if (nvme_alloc_sq_cmds(dev, nvmeq, qid))
b60503ba
MW		 1519 goto free_cqdma;
1520
091b6092 1521 nvmeq->dev = dev;
1ab0cd69 1522 spin_lock_init(&nvmeq->sq_lock);
3a7afd8e 1523 spin_lock_init(&nvmeq->cq_poll_lock);
b60503ba 1524 nvmeq->cq_head = 0;
82123460 1525 nvmeq->cq_phase = 1;
b80d5ccc 1526 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
c30341dc 1527 nvmeq->qid = qid;
d858e5f0 1528 dev->ctrl.queue_count++;
36a7e993 1529
147b27e4 1530 return 0;
b60503ba
MW		 1531
1532 free_cqdma:
8a1d09a6
BH		 1533 dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes,
1534 nvmeq->cq_dma_addr);
b60503ba 1535 free_nvmeq:
147b27e4 1536 return -ENOMEM;
b60503ba
MW		 1537}
1538
dca51e78 1539static int queue_request_irq(struct nvme_queue *nvmeq)
3001082c 1540{
0ff199cb
CH		 1541 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1542 int nr = nvmeq->dev->ctrl.instance;
1543
1544 if (use_threaded_interrupts) {
1545 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1546 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1547 } else {
1548 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1549 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1550 }
3001082c
MW		 1551}
1552
22404274 1553static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
b60503ba 1554{
22404274 1555 struct nvme_dev *dev = nvmeq->dev;
b60503ba 1556
22404274 1557 nvmeq->sq_tail = 0;
38210800 1558 nvmeq->last_sq_tail = 0;
22404274
KB		 1559 nvmeq->cq_head = 0;
1560 nvmeq->cq_phase = 1;
b80d5ccc 1561 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
8a1d09a6 1562 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq));
f9f38e33 1563 nvme_dbbuf_init(dev, nvmeq, qid);
42f61420 1564 dev->online_queues++;
3a7afd8e 1565 wmb(); /* ensure the first interrupt sees the initialization */
22404274
KB		 1566}
1567
4b04cc6a 1568static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled)
22404274
KB		 1569{
1570 struct nvme_dev *dev = nvmeq->dev;
1571 int result;
7c349dde 1572 u16 vector = 0;
3f85d50b 1573
d1ed6aa1
CH		 1574 clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
1575
22b55601
KB		 1576 /*
1577 * A queue's vector matches the queue identifier unless the controller
1578 * has only one vector available.
1579 */
4b04cc6a
JA		 1580 if (!polled)
1581 vector = dev->num_vecs == 1 ? 0 : qid;
1582 else
7c349dde 1583 set_bit(NVMEQ_POLLED, &nvmeq->flags);
4b04cc6a 1584
a8e3e0bb 1585 result = adapter_alloc_cq(dev, qid, nvmeq, vector);
ded45505
KB		 1586 if (result)
1587 return result;
b60503ba
MW		 1588
1589 result = adapter_alloc_sq(dev, qid, nvmeq);
1590 if (result < 0)
ded45505 1591 return result;
c80b36cd 1592 if (result)
b60503ba
MW		 1593 goto release_cq;
1594
a8e3e0bb 1595 nvmeq->cq_vector = vector;
161b8be2 1596 nvme_init_queue(nvmeq, qid);
4b04cc6a 1597
7c349dde 1598 if (!polled) {
4b04cc6a
JA		 1599 result = queue_request_irq(nvmeq);
1600 if (result < 0)
1601 goto release_sq;
1602 }
b60503ba 1603
4e224106 1604 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
22404274 1605 return result;
b60503ba 1606
a8e3e0bb 1607release_sq:
f25a2dfc 1608 dev->online_queues--;
b60503ba 1609 adapter_delete_sq(dev, qid);
a8e3e0bb 1610release_cq:
b60503ba 1611 adapter_delete_cq(dev, qid);
22404274 1612 return result;
b60503ba
MW		 1613}
1614
f363b089 1615static const struct blk_mq_ops nvme_mq_admin_ops = {
d29ec824 1616 .queue_rq = nvme_queue_rq,
77f02a7a 1617 .complete = nvme_pci_complete_rq,
a4aea562 1618 .init_hctx = nvme_admin_init_hctx,
0350815a 1619 .init_request = nvme_init_request,
a4aea562
MB		 1620 .timeout = nvme_timeout,
1621};
1622
f363b089 1623static const struct blk_mq_ops nvme_mq_ops = {
376f7ef8
CH		 1624 .queue_rq = nvme_queue_rq,
1625 .complete = nvme_pci_complete_rq,
1626 .commit_rqs = nvme_commit_rqs,
1627 .init_hctx = nvme_init_hctx,
1628 .init_request = nvme_init_request,
1629 .map_queues = nvme_pci_map_queues,
1630 .timeout = nvme_timeout,
1631 .poll = nvme_poll,
dabcefab
JA		 1632};
1633
ea191d2f
KB		 1634static void nvme_dev_remove_admin(struct nvme_dev *dev)
1635{
1c63dc66 1636 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
69d9a99c
KB		 1637 /*
1638 * If the controller was reset during removal, it's possible
1639 * user requests may be waiting on a stopped queue. Start the
1640 * queue to flush these to completion.
1641 */
c81545f9 1642 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1c63dc66 1643 blk_cleanup_queue(dev->ctrl.admin_q);
ea191d2f
KB		 1644 blk_mq_free_tag_set(&dev->admin_tagset);
1645 }
1646}
1647
a4aea562
MB		 1648static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1649{
1c63dc66 1650 if (!dev->ctrl.admin_q) {
a4aea562
MB		 1651 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1652 dev->admin_tagset.nr_hw_queues = 1;
e3e9d50c 1653
38dabe21 1654 dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH;
dc96f938 1655 dev->admin_tagset.timeout = NVME_ADMIN_TIMEOUT;
d4ec47f1 1656 dev->admin_tagset.numa_node = dev->ctrl.numa_node;
d43f1ccf 1657 dev->admin_tagset.cmd_size = sizeof(struct nvme_iod);
d3484991 1658 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED;
a4aea562
MB		 1659 dev->admin_tagset.driver_data = dev;
1660
1661 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1662 return -ENOMEM;
34b6c231 1663 dev->ctrl.admin_tagset = &dev->admin_tagset;
a4aea562 1664
1c63dc66
CH		 1665 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1666 if (IS_ERR(dev->ctrl.admin_q)) {
a4aea562
MB		 1667 blk_mq_free_tag_set(&dev->admin_tagset);
1668 return -ENOMEM;
1669 }
1c63dc66 1670 if (!blk_get_queue(dev->ctrl.admin_q)) {
ea191d2f 1671 nvme_dev_remove_admin(dev);
1c63dc66 1672 dev->ctrl.admin_q = NULL;
ea191d2f
KB		 1673 return -ENODEV;
1674 }
0fb59cbc 1675 } else
c81545f9 1676 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
a4aea562
MB		 1677
1678 return 0;
1679}
1680
97f6ef64
XY		 1681static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1682{
1683 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1684}
1685
1686static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1687{
1688 struct pci_dev *pdev = to_pci_dev(dev->dev);
1689
1690 if (size <= dev->bar_mapped_size)
1691 return 0;
1692 if (size > pci_resource_len(pdev, 0))
1693 return -ENOMEM;
1694 if (dev->bar)
1695 iounmap(dev->bar);
1696 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1697 if (!dev->bar) {
1698 dev->bar_mapped_size = 0;
1699 return -ENOMEM;
1700 }
1701 dev->bar_mapped_size = size;
1702 dev->dbs = dev->bar + NVME_REG_DBS;
1703
1704 return 0;
1705}
1706
01ad0990 1707static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
b60503ba 1708{
ba47e386 1709 int result;
b60503ba
MW		 1710 u32 aqa;
1711 struct nvme_queue *nvmeq;
1712
97f6ef64
XY		 1713 result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1714 if (result < 0)
1715 return result;
1716
8ef2074d 1717 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
20d0dfe6 1718 NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
dfbac8c7 1719
7a67cbea
CH		 1720 if (dev->subsystem &&
1721 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1722 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
dfbac8c7 1723
b5b05048 1724 result = nvme_disable_ctrl(&dev->ctrl);
ba47e386
MW		 1725 if (result < 0)
1726 return result;
b60503ba 1727
a6ff7262 1728 result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
147b27e4
SG		 1729 if (result)
1730 return result;
b60503ba 1731
635333e4
MG		 1732 dev->ctrl.numa_node = dev_to_node(dev->dev);
1733
147b27e4 1734 nvmeq = &dev->queues[0];
b60503ba
MW		 1735 aqa = nvmeq->q_depth - 1;
1736 aqa |= aqa << 16;
1737
7a67cbea
CH		 1738 writel(aqa, dev->bar + NVME_REG_AQA);
1739 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1740 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
b60503ba 1741
c0f2f45b 1742 result = nvme_enable_ctrl(&dev->ctrl);
025c557a 1743 if (result)
d4875622 1744 return result;
a4aea562 1745
2b25d981 1746 nvmeq->cq_vector = 0;
161b8be2 1747 nvme_init_queue(nvmeq, 0);
dca51e78 1748 result = queue_request_irq(nvmeq);
758dd7fd 1749 if (result) {
7c349dde 1750 dev->online_queues--;
d4875622 1751 return result;
758dd7fd 1752 }
025c557a 1753
4e224106 1754 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
b60503ba
MW		 1755 return result;
1756}
1757
749941f2 1758static int nvme_create_io_queues(struct nvme_dev *dev)
42f61420 1759{
4b04cc6a 1760 unsigned i, max, rw_queues;
749941f2 1761 int ret = 0;
42f61420 1762
d858e5f0 1763 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
a6ff7262 1764 if (nvme_alloc_queue(dev, i, dev->q_depth)) {
749941f2 1765 ret = -ENOMEM;
42f61420 1766 break;
749941f2
CH		 1767 }
1768 }
42f61420 1769
d858e5f0 1770 max = min(dev->max_qid, dev->ctrl.queue_count - 1);
e20ba6e1
CH		 1771 if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) {
1772 rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] +
1773 dev->io_queues[HCTX_TYPE_READ];
4b04cc6a
JA		 1774 } else {
1775 rw_queues = max;
1776 }
1777
949928c1 1778 for (i = dev->online_queues; i <= max; i++) {
4b04cc6a
JA		 1779 bool polled = i > rw_queues;
1780
1781 ret = nvme_create_queue(&dev->queues[i], i, polled);
d4875622 1782 if (ret)
42f61420 1783 break;
27e8166c 1784 }
749941f2
CH		 1785
1786 /*
1787 * Ignore failing Create SQ/CQ commands, we can continue with less
8adb8c14
MI		 1788 * than the desired amount of queues, and even a controller without
1789 * I/O queues can still be used to issue admin commands. This might
749941f2
CH		 1790 * be useful to upgrade a buggy firmware for example.
1791 */
1792 return ret >= 0 ? 0 : ret;
b60503ba
MW		 1793}
1794
202021c1
SB		 1795static ssize_t nvme_cmb_show(struct device *dev,
1796 struct device_attribute *attr,
1797 char *buf)
1798{
1799 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
1800
c965809c 1801 return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n",
202021c1
SB		 1802 ndev->cmbloc, ndev->cmbsz);
1803}
1804static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL);
1805
88de4598 1806static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
8ffaadf7 1807{
88de4598
CH		 1808 u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
1809
1810 return 1ULL << (12 + 4 * szu);
1811}
1812
1813static u32 nvme_cmb_size(struct nvme_dev *dev)
1814{
1815 return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
1816}
1817
f65efd6d 1818static void nvme_map_cmb(struct nvme_dev *dev)
8ffaadf7 1819{
88de4598 1820 u64 size, offset;
8ffaadf7
JD		 1821 resource_size_t bar_size;
1822 struct pci_dev *pdev = to_pci_dev(dev->dev);
8969f1f8 1823 int bar;
8ffaadf7 1824
9fe5c59f
KB		 1825 if (dev->cmb_size)
1826 return;
1827
20d3bb92
KJ		 1828 if (NVME_CAP_CMBS(dev->ctrl.cap))
1829 writel(NVME_CMBMSC_CRE, dev->bar + NVME_REG_CMBMSC);
1830
7a67cbea 1831 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
f65efd6d
CH		 1832 if (!dev->cmbsz)
1833 return;
202021c1 1834 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
8ffaadf7 1835
88de4598
CH		 1836 size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
1837 offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
8969f1f8
CH		 1838 bar = NVME_CMB_BIR(dev->cmbloc);
1839 bar_size = pci_resource_len(pdev, bar);
8ffaadf7
JD		 1840
1841 if (offset > bar_size)
f65efd6d 1842 return;
8ffaadf7 1843
20d3bb92
KJ		 1844 /*
1845 * Tell the controller about the host side address mapping the CMB,
1846 * and enable CMB decoding for the NVMe 1.4+ scheme:
1847 */
1848 if (NVME_CAP_CMBS(dev->ctrl.cap)) {
1849 hi_lo_writeq(NVME_CMBMSC_CRE | NVME_CMBMSC_CMSE |
1850 (pci_bus_address(pdev, bar) + offset),
1851 dev->bar + NVME_REG_CMBMSC);
1852 }
1853
8ffaadf7
JD		 1854 /*
1855 * Controllers may support a CMB size larger than their BAR,
1856 * for example, due to being behind a bridge. Reduce the CMB to
1857 * the reported size of the BAR
1858 */
1859 if (size > bar_size - offset)
1860 size = bar_size - offset;
1861
0f238ff5
LG		 1862 if (pci_p2pdma_add_resource(pdev, bar, size, offset)) {
1863 dev_warn(dev->ctrl.device,
1864 "failed to register the CMB\n");
f65efd6d 1865 return;
0f238ff5
LG		 1866 }
1867
8ffaadf7 1868 dev->cmb_size = size;
0f238ff5
LG		 1869 dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS);
1870
1871 if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) ==
1872 (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS))
1873 pci_p2pmem_publish(pdev, true);
f65efd6d
CH		 1874
1875 if (sysfs_add_file_to_group(&dev->ctrl.device->kobj,
1876 &dev_attr_cmb.attr, NULL))
1877 dev_warn(dev->ctrl.device,
1878 "failed to add sysfs attribute for CMB\n");
8ffaadf7
JD		 1879}
1880
1881static inline void nvme_release_cmb(struct nvme_dev *dev)
1882{
0f238ff5 1883 if (dev->cmb_size) {
1c78f773
MG		 1884 sysfs_remove_file_from_group(&dev->ctrl.device->kobj,
1885 &dev_attr_cmb.attr, NULL);
0f238ff5 1886 dev->cmb_size = 0;
8ffaadf7
JD		 1887 }
1888}
1889
87ad72a5
CH		 1890static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1891{
6c3c05b0 1892 u32 host_mem_size = dev->host_mem_size >> NVME_CTRL_PAGE_SHIFT;
4033f35d 1893 u64 dma_addr = dev->host_mem_descs_dma;
87ad72a5 1894 struct nvme_command c;
87ad72a5
CH		 1895 int ret;
1896
87ad72a5
CH		 1897 memset(&c, 0, sizeof(c));
1898 c.features.opcode = nvme_admin_set_features;
1899 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1900 c.features.dword11 = cpu_to_le32(bits);
6c3c05b0 1901 c.features.dword12 = cpu_to_le32(host_mem_size);
87ad72a5
CH		 1902 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr));
1903 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr));
1904 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs);
1905
1906 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1907 if (ret) {
1908 dev_warn(dev->ctrl.device,
1909 "failed to set host mem (err %d, flags %#x).\n",
1910 ret, bits);
1911 }
87ad72a5
CH		 1912 return ret;
1913}
1914
1915static void nvme_free_host_mem(struct nvme_dev *dev)
1916{
1917 int i;
1918
1919 for (i = 0; i < dev->nr_host_mem_descs; i++) {
1920 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
6c3c05b0 1921 size_t size = le32_to_cpu(desc->size) * NVME_CTRL_PAGE_SIZE;
87ad72a5 1922
cc667f6d
LD		 1923 dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i],
1924 le64_to_cpu(desc->addr),
1925 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
87ad72a5
CH		 1926 }
1927
1928 kfree(dev->host_mem_desc_bufs);
1929 dev->host_mem_desc_bufs = NULL;
4033f35d
CH		 1930 dma_free_coherent(dev->dev,
1931 dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
1932 dev->host_mem_descs, dev->host_mem_descs_dma);
87ad72a5 1933 dev->host_mem_descs = NULL;
7e5dd57e 1934 dev->nr_host_mem_descs = 0;
87ad72a5
CH		 1935}
1936
92dc6895
CH		 1937static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
1938 u32 chunk_size)
9d713c2b 1939{
87ad72a5 1940 struct nvme_host_mem_buf_desc *descs;
92dc6895 1941 u32 max_entries, len;
4033f35d 1942 dma_addr_t descs_dma;
2ee0e4ed 1943 int i = 0;
87ad72a5 1944 void **bufs;
6fbcde66 1945 u64 size, tmp;
87ad72a5 1946
87ad72a5
CH		 1947 tmp = (preferred + chunk_size - 1);
1948 do_div(tmp, chunk_size);
1949 max_entries = tmp;
044a9df1
CH		 1950
1951 if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
1952 max_entries = dev->ctrl.hmmaxd;
1953
750afb08
LC		 1954 descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs),
1955 &descs_dma, GFP_KERNEL);
87ad72a5
CH		 1956 if (!descs)
1957 goto out;
1958
1959 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
1960 if (!bufs)
1961 goto out_free_descs;
1962
244a8fe4 1963 for (size = 0; size < preferred && i < max_entries; size += len) {
87ad72a5
CH		 1964 dma_addr_t dma_addr;
1965
50cdb7c6 1966 len = min_t(u64, chunk_size, preferred - size);
87ad72a5
CH		 1967 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
1968 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1969 if (!bufs[i])
1970 break;
1971
1972 descs[i].addr = cpu_to_le64(dma_addr);
6c3c05b0 1973 descs[i].size = cpu_to_le32(len / NVME_CTRL_PAGE_SIZE);
87ad72a5
CH		 1974 i++;
1975 }
1976
92dc6895 1977 if (!size)
87ad72a5 1978 goto out_free_bufs;
87ad72a5 1979
87ad72a5
CH		 1980 dev->nr_host_mem_descs = i;
1981 dev->host_mem_size = size;
1982 dev->host_mem_descs = descs;
4033f35d 1983 dev->host_mem_descs_dma = descs_dma;
87ad72a5
CH		 1984 dev->host_mem_desc_bufs = bufs;
1985 return 0;
1986
1987out_free_bufs:
1988 while (--i >= 0) {
6c3c05b0 1989 size_t size = le32_to_cpu(descs[i].size) * NVME_CTRL_PAGE_SIZE;
87ad72a5 1990
cc667f6d
LD		 1991 dma_free_attrs(dev->dev, size, bufs[i],
1992 le64_to_cpu(descs[i].addr),
1993 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
87ad72a5
CH		 1994 }
1995
1996 kfree(bufs);
1997out_free_descs:
4033f35d
CH		 1998 dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
1999 descs_dma);
87ad72a5 2000out:
87ad72a5
CH		 2001 dev->host_mem_descs = NULL;
2002 return -ENOMEM;
2003}
2004
92dc6895
CH		 2005static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
2006{
9dc54a0d
CK		 2007 u64 min_chunk = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
2008 u64 hmminds = max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
2009 u64 chunk_size;
92dc6895
CH		 2010
2011 /* start big and work our way down */
9dc54a0d 2012 for (chunk_size = min_chunk; chunk_size >= hmminds; chunk_size /= 2) {
92dc6895
CH		 2013 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
2014 if (!min || dev->host_mem_size >= min)
2015 return 0;
2016 nvme_free_host_mem(dev);
2017 }
2018 }
2019
2020 return -ENOMEM;
2021}
2022
9620cfba 2023static int nvme_setup_host_mem(struct nvme_dev *dev)
87ad72a5
CH		 2024{
2025 u64 max = (u64)max_host_mem_size_mb * SZ_1M;
2026 u64 preferred = (u64)dev->ctrl.hmpre * 4096;
2027 u64 min = (u64)dev->ctrl.hmmin * 4096;
2028 u32 enable_bits = NVME_HOST_MEM_ENABLE;
6fbcde66 2029 int ret;
87ad72a5
CH		 2030
2031 preferred = min(preferred, max);
2032 if (min > max) {
2033 dev_warn(dev->ctrl.device,
2034 "min host memory (%lld MiB) above limit (%d MiB).\n",
2035 min >> ilog2(SZ_1M), max_host_mem_size_mb);
2036 nvme_free_host_mem(dev);
9620cfba 2037 return 0;
87ad72a5
CH		 2038 }
2039
2040 /*
2041 * If we already have a buffer allocated check if we can reuse it.
2042 */
2043 if (dev->host_mem_descs) {
2044 if (dev->host_mem_size >= min)
2045 enable_bits |= NVME_HOST_MEM_RETURN;
2046 else
2047 nvme_free_host_mem(dev);
2048 }
2049
2050 if (!dev->host_mem_descs) {
92dc6895
CH		 2051 if (nvme_alloc_host_mem(dev, min, preferred)) {
2052 dev_warn(dev->ctrl.device,
2053 "failed to allocate host memory buffer.\n");
9620cfba 2054 return 0; /* controller must work without HMB */
92dc6895
CH		 2055 }
2056
2057 dev_info(dev->ctrl.device,
2058 "allocated %lld MiB host memory buffer.\n",
2059 dev->host_mem_size >> ilog2(SZ_1M));
87ad72a5
CH		 2060 }
2061
9620cfba
CH		 2062 ret = nvme_set_host_mem(dev, enable_bits);
2063 if (ret)
87ad72a5 2064 nvme_free_host_mem(dev);
9620cfba 2065 return ret;
9d713c2b
KB		 2066}
2067
612b7286
ML		 2068/*
2069 * nirqs is the number of interrupts available for write and read
2070 * queues. The core already reserved an interrupt for the admin queue.
2071 */
2072static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs)
3b6592f7 2073{
612b7286 2074 struct nvme_dev *dev = affd->priv;
2a5bcfdd 2075 unsigned int nr_read_queues, nr_write_queues = dev->nr_write_queues;
3b6592f7
JA		 2076
2077 /*
ee0d96d3 2078 * If there is no interrupt available for queues, ensure that
612b7286
ML		 2079 * the default queue is set to 1. The affinity set size is
2080 * also set to one, but the irq core ignores it for this case.
2081 *
2082 * If only one interrupt is available or 'write_queue' == 0, combine
2083 * write and read queues.
2084 *
2085 * If 'write_queues' > 0, ensure it leaves room for at least one read
2086 * queue.
3b6592f7 2087 */
612b7286
ML		 2088 if (!nrirqs) {
2089 nrirqs = 1;
2090 nr_read_queues = 0;
2a5bcfdd 2091 } else if (nrirqs == 1 || !nr_write_queues) {
612b7286 2092 nr_read_queues = 0;
2a5bcfdd 2093 } else if (nr_write_queues >= nrirqs) {
612b7286 2094 nr_read_queues = 1;
3b6592f7 2095 } else {
2a5bcfdd 2096 nr_read_queues = nrirqs - nr_write_queues;
3b6592f7 2097 }
612b7286
ML		 2098
2099 dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2100 affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2101 dev->io_queues[HCTX_TYPE_READ] = nr_read_queues;
2102 affd->set_size[HCTX_TYPE_READ] = nr_read_queues;
2103 affd->nr_sets = nr_read_queues ? 2 : 1;
3b6592f7
JA		 2104}
2105
6451fe73 2106static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues)
3b6592f7
JA		 2107{
2108 struct pci_dev *pdev = to_pci_dev(dev->dev);
3b6592f7 2109 struct irq_affinity affd = {
9cfef55b 2110 .pre_vectors = 1,
612b7286
ML		 2111 .calc_sets = nvme_calc_irq_sets,
2112 .priv = dev,
3b6592f7 2113 };
21cc2f3f 2114 unsigned int irq_queues, poll_queues;
6451fe73
JA		 2115
2116 /*
21cc2f3f
JX		 2117 * Poll queues don't need interrupts, but we need at least one I/O queue
2118 * left over for non-polled I/O.
6451fe73 2119 */
21cc2f3f
JX		 2120 poll_queues = min(dev->nr_poll_queues, nr_io_queues - 1);
2121 dev->io_queues[HCTX_TYPE_POLL] = poll_queues;
3b6592f7 2122
21cc2f3f
JX		 2123 /*
2124 * Initialize for the single interrupt case, will be updated in
2125 * nvme_calc_irq_sets().
2126 */
612b7286
ML		 2127 dev->io_queues[HCTX_TYPE_DEFAULT] = 1;
2128 dev->io_queues[HCTX_TYPE_READ] = 0;
3b6592f7 2129
66341331 2130 /*
21cc2f3f
JX		 2131 * We need interrupts for the admin queue and each non-polled I/O queue,
2132 * but some Apple controllers require all queues to use the first
2133 * vector.
66341331 2134 */
21cc2f3f
JX		 2135 irq_queues = 1;
2136 if (!(dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR))
2137 irq_queues += (nr_io_queues - poll_queues);
612b7286
ML		 2138 return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues,
2139 PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd);
3b6592f7
JA		 2140}
2141
8fae268b
KB		 2142static void nvme_disable_io_queues(struct nvme_dev *dev)
2143{
2144 if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq))
2145 __nvme_disable_io_queues(dev, nvme_admin_delete_cq);
2146}
2147
2a5bcfdd
WZ		 2148static unsigned int nvme_max_io_queues(struct nvme_dev *dev)
2149{
e3aef095
NS		 2150 /*
2151 * If tags are shared with admin queue (Apple bug), then
2152 * make sure we only use one IO queue.
2153 */
2154 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2155 return 1;
2a5bcfdd
WZ		 2156 return num_possible_cpus() + dev->nr_write_queues + dev->nr_poll_queues;
2157}
2158
8d85fce7 2159static int nvme_setup_io_queues(struct nvme_dev *dev)
b60503ba 2160{
147b27e4 2161 struct nvme_queue *adminq = &dev->queues[0];
e75ec752 2162 struct pci_dev *pdev = to_pci_dev(dev->dev);
2a5bcfdd 2163 unsigned int nr_io_queues;
97f6ef64 2164 unsigned long size;
2a5bcfdd 2165 int result;
b60503ba 2166
2a5bcfdd
WZ		 2167 /*
2168 * Sample the module parameters once at reset time so that we have
2169 * stable values to work with.
2170 */
2171 dev->nr_write_queues = write_queues;
2172 dev->nr_poll_queues = poll_queues;
d38e9f04 2173
e3aef095 2174 nr_io_queues = dev->nr_allocated_queues - 1;
9a0be7ab
CH		 2175 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
2176 if (result < 0)
1b23484b 2177 return result;
9a0be7ab 2178
f5fa90dc 2179 if (nr_io_queues == 0)
a5229050 2180 return 0;
4e224106
CH		 2181
2182 clear_bit(NVMEQ_ENABLED, &adminq->flags);
b60503ba 2183
0f238ff5 2184 if (dev->cmb_use_sqes) {
8ffaadf7
JD		 2185 result = nvme_cmb_qdepth(dev, nr_io_queues,
2186 sizeof(struct nvme_command));
2187 if (result > 0)
2188 dev->q_depth = result;
2189 else
0f238ff5 2190 dev->cmb_use_sqes = false;
8ffaadf7
JD		 2191 }
2192
97f6ef64
XY		 2193 do {
2194 size = db_bar_size(dev, nr_io_queues);
2195 result = nvme_remap_bar(dev, size);
2196 if (!result)
2197 break;
2198 if (!--nr_io_queues)
2199 return -ENOMEM;
2200 } while (1);
2201 adminq->q_db = dev->dbs;
f1938f6e 2202
8fae268b 2203 retry:
9d713c2b 2204 /* Deregister the admin queue's interrupt */
0ff199cb 2205 pci_free_irq(pdev, 0, adminq);
9d713c2b 2206
e32efbfc
JA		 2207 /*
2208 * If we enable msix early due to not intx, disable it again before
2209 * setting up the full range we need.
2210 */
dca51e78 2211 pci_free_irq_vectors(pdev);
3b6592f7
JA		 2212
2213 result = nvme_setup_irqs(dev, nr_io_queues);
22b55601 2214 if (result <= 0)
dca51e78 2215 return -EIO;
3b6592f7 2216
22b55601 2217 dev->num_vecs = result;
4b04cc6a 2218 result = max(result - 1, 1);
e20ba6e1 2219 dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL];
fa08a396 2220
063a8096
MW		 2221 /*
2222 * Should investigate if there's a performance win from allocating
2223 * more queues than interrupt vectors; it might allow the submission
2224 * path to scale better, even if the receive path is limited by the
2225 * number of interrupts.
2226 */
dca51e78 2227 result = queue_request_irq(adminq);
7c349dde 2228 if (result)
d4875622 2229 return result;
4e224106 2230 set_bit(NVMEQ_ENABLED, &adminq->flags);
8fae268b
KB		 2231
2232 result = nvme_create_io_queues(dev);
2233 if (result || dev->online_queues < 2)
2234 return result;
2235
2236 if (dev->online_queues - 1 < dev->max_qid) {
2237 nr_io_queues = dev->online_queues - 1;
2238 nvme_disable_io_queues(dev);
2239 nvme_suspend_io_queues(dev);
2240 goto retry;
2241 }
2242 dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n",
2243 dev->io_queues[HCTX_TYPE_DEFAULT],
2244 dev->io_queues[HCTX_TYPE_READ],
2245 dev->io_queues[HCTX_TYPE_POLL]);
2246 return 0;
b60503ba
MW		 2247}
2248
2a842aca 2249static void nvme_del_queue_end(struct request *req, blk_status_t error)
a5768aa8 2250{
db3cbfff 2251 struct nvme_queue *nvmeq = req->end_io_data;
b5875222 2252
db3cbfff 2253 blk_mq_free_request(req);
d1ed6aa1 2254 complete(&nvmeq->delete_done);
a5768aa8
KB		 2255}
2256
2a842aca 2257static void nvme_del_cq_end(struct request *req, blk_status_t error)
a5768aa8 2258{
db3cbfff 2259 struct nvme_queue *nvmeq = req->end_io_data;
a5768aa8 2260
d1ed6aa1
CH		 2261 if (error)
2262 set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
db3cbfff
KB		 2263
2264 nvme_del_queue_end(req, error);
a5768aa8
KB		 2265}
2266
db3cbfff 2267static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
bda4e0fb 2268{
db3cbfff
KB		 2269 struct request_queue *q = nvmeq->dev->ctrl.admin_q;
2270 struct request *req;
2271 struct nvme_command cmd;
bda4e0fb 2272
db3cbfff
KB		 2273 memset(&cmd, 0, sizeof(cmd));
2274 cmd.delete_queue.opcode = opcode;
2275 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
bda4e0fb 2276
39dfe844 2277 req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT);
db3cbfff
KB		 2278 if (IS_ERR(req))
2279 return PTR_ERR(req);
bda4e0fb 2280
db3cbfff
KB		 2281 req->end_io_data = nvmeq;
2282
d1ed6aa1 2283 init_completion(&nvmeq->delete_done);
8eeed0b5 2284 blk_execute_rq_nowait(NULL, req, false,
db3cbfff
KB		 2285 opcode == nvme_admin_delete_cq ?
2286 nvme_del_cq_end : nvme_del_queue_end);
2287 return 0;
bda4e0fb
KB		 2288}
2289
8fae268b 2290static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode)
a5768aa8 2291{
5271edd4 2292 int nr_queues = dev->online_queues - 1, sent = 0;
db3cbfff 2293 unsigned long timeout;
a5768aa8 2294
db3cbfff 2295 retry:
dc96f938 2296 timeout = NVME_ADMIN_TIMEOUT;
5271edd4
CH		 2297 while (nr_queues > 0) {
2298 if (nvme_delete_queue(&dev->queues[nr_queues], opcode))
2299 break;
2300 nr_queues--;
2301 sent++;
db3cbfff 2302 }
d1ed6aa1
CH		 2303 while (sent) {
2304 struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent];
2305
2306 timeout = wait_for_completion_io_timeout(&nvmeq->delete_done,
5271edd4
CH		 2307 timeout);
2308 if (timeout == 0)
2309 return false;
d1ed6aa1 2310
d1ed6aa1 2311 sent--;
5271edd4
CH		 2312 if (nr_queues)
2313 goto retry;
2314 }
2315 return true;
a5768aa8
KB		 2316}
2317
5d02a5c1 2318static void nvme_dev_add(struct nvme_dev *dev)
b60503ba 2319{
2b1b7e78
JW		 2320 int ret;
2321
5bae7f73 2322 if (!dev->ctrl.tagset) {
376f7ef8 2323 dev->tagset.ops = &nvme_mq_ops;
ffe7704d 2324 dev->tagset.nr_hw_queues = dev->online_queues - 1;
8fe34be1 2325 dev->tagset.nr_maps = 2; /* default + read */
ed92ad37
CH		 2326 if (dev->io_queues[HCTX_TYPE_POLL])
2327 dev->tagset.nr_maps++;
ffe7704d 2328 dev->tagset.timeout = NVME_IO_TIMEOUT;
d4ec47f1 2329 dev->tagset.numa_node = dev->ctrl.numa_node;
61f3b896
CK		 2330 dev->tagset.queue_depth = min_t(unsigned int, dev->q_depth,
2331 BLK_MQ_MAX_DEPTH) - 1;
d43f1ccf 2332 dev->tagset.cmd_size = sizeof(struct nvme_iod);
ffe7704d
KB		 2333 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2334 dev->tagset.driver_data = dev;
b60503ba 2335
d38e9f04
BH		 2336 /*
2337 * Some Apple controllers requires tags to be unique
2338 * across admin and IO queue, so reserve the first 32
2339 * tags of the IO queue.
2340 */
2341 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2342 dev->tagset.reserved_tags = NVME_AQ_DEPTH;
2343
2b1b7e78
JW		 2344 ret = blk_mq_alloc_tag_set(&dev->tagset);
2345 if (ret) {
2346 dev_warn(dev->ctrl.device,
2347 "IO queues tagset allocation failed %d\n", ret);
5d02a5c1 2348 return;
2b1b7e78 2349 }
5bae7f73 2350 dev->ctrl.tagset = &dev->tagset;
949928c1
KB		 2351 } else {
2352 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2353
2354 /* Free previously allocated queues that are no longer usable */
2355 nvme_free_queues(dev, dev->online_queues);
ffe7704d 2356 }
949928c1 2357
e8fd41bb 2358 nvme_dbbuf_set(dev);
b60503ba
MW		 2359}
2360
b00a726a 2361static int nvme_pci_enable(struct nvme_dev *dev)
0877cb0d 2362{
b00a726a 2363 int result = -ENOMEM;
e75ec752 2364 struct pci_dev *pdev = to_pci_dev(dev->dev);
0877cb0d
KB		 2365
2366 if (pci_enable_device_mem(pdev))
2367 return result;
2368
0877cb0d 2369 pci_set_master(pdev);
0877cb0d 2370
4fe06923 2371 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)))
052d0efa 2372 goto disable;
0877cb0d 2373
7a67cbea 2374 if (readl(dev->bar + NVME_REG_CSTS) == -1) {
0e53d180 2375 result = -ENODEV;
b00a726a 2376 goto disable;
0e53d180 2377 }
e32efbfc
JA		 2378
2379 /*
a5229050
KB		 2380 * Some devices and/or platforms don't advertise or work with INTx
2381 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2382 * adjust this later.
e32efbfc 2383 */
dca51e78
CH		 2384 result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
2385 if (result < 0)
2386 return result;
e32efbfc 2387
20d0dfe6 2388 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
7a67cbea 2389
7442ddce 2390 dev->q_depth = min_t(u32, NVME_CAP_MQES(dev->ctrl.cap) + 1,
b27c1e68 2391 io_queue_depth);
aa22c8e6 2392 dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */
20d0dfe6 2393 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
7a67cbea 2394 dev->dbs = dev->bar + 4096;
1f390c1f 2395
66341331
BH		 2396 /*
2397 * Some Apple controllers require a non-standard SQE size.
2398 * Interestingly they also seem to ignore the CC:IOSQES register
2399 * so we don't bother updating it here.
2400 */
2401 if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES)
2402 dev->io_sqes = 7;
2403 else
2404 dev->io_sqes = NVME_NVM_IOSQES;
1f390c1f
SG		 2405
2406 /*
2407 * Temporary fix for the Apple controller found in the MacBook8,1 and
2408 * some MacBook7,1 to avoid controller resets and data loss.
2409 */
2410 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
2411 dev->q_depth = 2;
9bdcfb10
CH		 2412 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
2413 "set queue depth=%u to work around controller resets\n",
1f390c1f 2414 dev->q_depth);
d554b5e1
MP		 2415 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2416 (pdev->device == 0xa821 || pdev->device == 0xa822) &&
20d0dfe6 2417 NVME_CAP_MQES(dev->ctrl.cap) == 0) {
d554b5e1
MP		 2418 dev->q_depth = 64;
2419 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2420 "set queue depth=%u\n", dev->q_depth);
1f390c1f
SG		 2421 }
2422
d38e9f04
BH		 2423 /*
2424 * Controllers with the shared tags quirk need the IO queue to be
2425 * big enough so that we get 32 tags for the admin queue
2426 */
2427 if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) &&
2428 (dev->q_depth < (NVME_AQ_DEPTH + 2))) {
2429 dev->q_depth = NVME_AQ_DEPTH + 2;
2430 dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n",
2431 dev->q_depth);
2432 }
2433
2434
f65efd6d 2435 nvme_map_cmb(dev);
202021c1 2436
a0a3408e
KB		 2437 pci_enable_pcie_error_reporting(pdev);
2438 pci_save_state(pdev);
0877cb0d
KB		 2439 return 0;
2440
2441 disable:
0877cb0d
KB		 2442 pci_disable_device(pdev);
2443 return result;
2444}
2445
2446static void nvme_dev_unmap(struct nvme_dev *dev)
b00a726a
KB		 2447{
2448 if (dev->bar)
2449 iounmap(dev->bar);
a1f447b3 2450 pci_release_mem_regions(to_pci_dev(dev->dev));
b00a726a
KB		 2451}
2452
2453static void nvme_pci_disable(struct nvme_dev *dev)
0877cb0d 2454{
e75ec752
CH		 2455 struct pci_dev *pdev = to_pci_dev(dev->dev);
2456
dca51e78 2457 pci_free_irq_vectors(pdev);
0877cb0d 2458
a0a3408e
KB		 2459 if (pci_is_enabled(pdev)) {
2460 pci_disable_pcie_error_reporting(pdev);
e75ec752 2461 pci_disable_device(pdev);
4d115420 2462 }
4d115420
KB		 2463}
2464
a5cdb68c 2465static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
b60503ba 2466{
e43269e6 2467 bool dead = true, freeze = false;
302ad8cc 2468 struct pci_dev *pdev = to_pci_dev(dev->dev);
22404274 2469
77bf25ea 2470 mutex_lock(&dev->shutdown_lock);
302ad8cc
KB		 2471 if (pci_is_enabled(pdev)) {
2472 u32 csts = readl(dev->bar + NVME_REG_CSTS);
2473
ebef7368 2474 if (dev->ctrl.state == NVME_CTRL_LIVE ||
e43269e6
KB		 2475 dev->ctrl.state == NVME_CTRL_RESETTING) {
2476 freeze = true;
302ad8cc 2477 nvme_start_freeze(&dev->ctrl);
e43269e6 2478 }
302ad8cc
KB		 2479 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
2480 pdev->error_state != pci_channel_io_normal);
c9d3bf88 2481 }
c21377f8 2482
302ad8cc
KB		 2483 /*
2484 * Give the controller a chance to complete all entered requests if
2485 * doing a safe shutdown.
2486 */
e43269e6
KB		 2487 if (!dead && shutdown && freeze)
2488 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
9a915a5b
JW		 2489
2490 nvme_stop_queues(&dev->ctrl);
87ad72a5 2491
64ee0ac0 2492 if (!dead && dev->ctrl.queue_count > 0) {
8fae268b 2493 nvme_disable_io_queues(dev);
a5cdb68c 2494 nvme_disable_admin_queue(dev, shutdown);
4d115420 2495 }
8fae268b
KB		 2496 nvme_suspend_io_queues(dev);
2497 nvme_suspend_queue(&dev->queues[0]);
b00a726a 2498 nvme_pci_disable(dev);
fa46c6fb 2499 nvme_reap_pending_cqes(dev);
07836e65 2500
e1958e65
ML		 2501 blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
2502 blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
622b8b68
ML		 2503 blk_mq_tagset_wait_completed_request(&dev->tagset);
2504 blk_mq_tagset_wait_completed_request(&dev->admin_tagset);
302ad8cc
KB		 2505
2506 /*
2507 * The driver will not be starting up queues again if shutting down so
2508 * must flush all entered requests to their failed completion to avoid
2509 * deadlocking blk-mq hot-cpu notifier.
2510 */
c8e9e9b7 2511 if (shutdown) {
302ad8cc 2512 nvme_start_queues(&dev->ctrl);
c8e9e9b7
KB		 2513 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q))
2514 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
2515 }
77bf25ea 2516 mutex_unlock(&dev->shutdown_lock);
b60503ba
MW		 2517}
2518
c1ac9a4b
KB		 2519static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown)
2520{
2521 if (!nvme_wait_reset(&dev->ctrl))
2522 return -EBUSY;
2523 nvme_dev_disable(dev, shutdown);
2524 return 0;
2525}
2526
091b6092
MW		 2527static int nvme_setup_prp_pools(struct nvme_dev *dev)
2528{
e75ec752 2529 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
c61b82c7
CH		 2530 NVME_CTRL_PAGE_SIZE,
2531 NVME_CTRL_PAGE_SIZE, 0);
091b6092
MW		 2532 if (!dev->prp_page_pool)
2533 return -ENOMEM;
2534
99802a7a 2535 /* Optimisation for I/Os between 4k and 128k */
e75ec752 2536 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
99802a7a
MW		 2537 256, 256, 0);
2538 if (!dev->prp_small_pool) {
2539 dma_pool_destroy(dev->prp_page_pool);
2540 return -ENOMEM;
2541 }
091b6092
MW		 2542 return 0;
2543}
2544
2545static void nvme_release_prp_pools(struct nvme_dev *dev)
2546{
2547 dma_pool_destroy(dev->prp_page_pool);
99802a7a 2548 dma_pool_destroy(dev->prp_small_pool);
091b6092
MW		 2549}
2550
770597ec
KB		 2551static void nvme_free_tagset(struct nvme_dev *dev)
2552{
2553 if (dev->tagset.tags)
2554 blk_mq_free_tag_set(&dev->tagset);
2555 dev->ctrl.tagset = NULL;
2556}
2557
1673f1f0 2558static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
5e82e952 2559{
1673f1f0 2560 struct nvme_dev *dev = to_nvme_dev(ctrl);
9ac27090 2561
f9f38e33 2562 nvme_dbbuf_dma_free(dev);
770597ec 2563 nvme_free_tagset(dev);
1c63dc66
CH		 2564 if (dev->ctrl.admin_q)
2565 blk_put_queue(dev->ctrl.admin_q);
e286bcfc 2566 free_opal_dev(dev->ctrl.opal_dev);
943e942e 2567 mempool_destroy(dev->iod_mempool);
253fd4ac
IR		 2568 put_device(dev->dev);
2569 kfree(dev->queues);
5e82e952
KB		 2570 kfree(dev);
2571}
2572
7c1ce408 2573static void nvme_remove_dead_ctrl(struct nvme_dev *dev)
f58944e2 2574{
c1ac9a4b
KB		 2575 /*
2576 * Set state to deleting now to avoid blocking nvme_wait_reset(), which
2577 * may be holding this pci_dev's device lock.
2578 */
2579 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
d22524a4 2580 nvme_get_ctrl(&dev->ctrl);
69d9a99c 2581 nvme_dev_disable(dev, false);
9f9cafc1 2582 nvme_kill_queues(&dev->ctrl);
03e0f3a6 2583 if (!queue_work(nvme_wq, &dev->remove_work))
f58944e2
KB		 2584 nvme_put_ctrl(&dev->ctrl);
2585}
2586
fd634f41 2587static void nvme_reset_work(struct work_struct *work)
5e82e952 2588{
d86c4d8e
CH		 2589 struct nvme_dev *dev =
2590 container_of(work, struct nvme_dev, ctrl.reset_work);
a98e58e5 2591 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
e71afda4 2592 int result;
5e82e952 2593
e71afda4
CK		 2594 if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING)) {
2595 result = -ENODEV;
fd634f41 2596 goto out;
e71afda4 2597 }
5e82e952 2598
fd634f41
CH		 2599 /*
2600 * If we're called to reset a live controller first shut it down before
2601 * moving on.
2602 */
b00a726a 2603 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
a5cdb68c 2604 nvme_dev_disable(dev, false);
d6135c3a 2605 nvme_sync_queues(&dev->ctrl);
5e82e952 2606
5c959d73 2607 mutex_lock(&dev->shutdown_lock);
b00a726a 2608 result = nvme_pci_enable(dev);
f0b50732 2609 if (result)
4726bcf3 2610 goto out_unlock;
f0b50732 2611
01ad0990 2612 result = nvme_pci_configure_admin_queue(dev);
f0b50732 2613 if (result)
4726bcf3 2614 goto out_unlock;
f0b50732 2615
0fb59cbc
KB		 2616 result = nvme_alloc_admin_tags(dev);
2617 if (result)
4726bcf3 2618 goto out_unlock;
b9afca3e 2619
943e942e
JA		 2620 /*
2621 * Limit the max command size to prevent iod->sg allocations going
2622 * over a single page.
2623 */
7637de31
CH		 2624 dev->ctrl.max_hw_sectors = min_t(u32,
2625 NVME_MAX_KB_SZ << 1, dma_max_mapping_size(dev->dev) >> 9);
943e942e 2626 dev->ctrl.max_segments = NVME_MAX_SEGS;
a48bc520
CH		 2627
2628 /*
2629 * Don't limit the IOMMU merged segment size.
2630 */
2631 dma_set_max_seg_size(dev->dev, 0xffffffff);
2632
5c959d73
KB		 2633 mutex_unlock(&dev->shutdown_lock);
2634
2635 /*
2636 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
2637 * initializing procedure here.
2638 */
2639 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
2640 dev_warn(dev->ctrl.device,
2641 "failed to mark controller CONNECTING\n");
cee6c269 2642 result = -EBUSY;
5c959d73
KB		 2643 goto out;
2644 }
943e942e 2645
95093350
MG		 2646 /*
2647 * We do not support an SGL for metadata (yet), so we are limited to a
2648 * single integrity segment for the separate metadata pointer.
2649 */
2650 dev->ctrl.max_integrity_segments = 1;
2651
ce4541f4
CH		 2652 result = nvme_init_identify(&dev->ctrl);
2653 if (result)
f58944e2 2654 goto out;
ce4541f4 2655
e286bcfc
SB		 2656 if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
2657 if (!dev->ctrl.opal_dev)
2658 dev->ctrl.opal_dev =
2659 init_opal_dev(&dev->ctrl, &nvme_sec_submit);
2660 else if (was_suspend)
2661 opal_unlock_from_suspend(dev->ctrl.opal_dev);
2662 } else {
2663 free_opal_dev(dev->ctrl.opal_dev);
2664 dev->ctrl.opal_dev = NULL;
4f1244c8 2665 }
a98e58e5 2666
f9f38e33
HK		 2667 if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) {
2668 result = nvme_dbbuf_dma_alloc(dev);
2669 if (result)
2670 dev_warn(dev->dev,
2671 "unable to allocate dma for dbbuf\n");
2672 }
2673
9620cfba
CH		 2674 if (dev->ctrl.hmpre) {
2675 result = nvme_setup_host_mem(dev);
2676 if (result < 0)
2677 goto out;
2678 }
87ad72a5 2679
f0b50732 2680 result = nvme_setup_io_queues(dev);
badc34d4 2681 if (result)
f58944e2 2682 goto out;
f0b50732 2683
2659e57b
CH		 2684 /*
2685 * Keep the controller around but remove all namespaces if we don't have
2686 * any working I/O queue.
2687 */
3cf519b5 2688 if (dev->online_queues < 2) {
1b3c47c1 2689 dev_warn(dev->ctrl.device, "IO queues not created\n");
3b24774e 2690 nvme_kill_queues(&dev->ctrl);
5bae7f73 2691 nvme_remove_namespaces(&dev->ctrl);
770597ec 2692 nvme_free_tagset(dev);
3cf519b5 2693 } else {
25646264 2694 nvme_start_queues(&dev->ctrl);
302ad8cc 2695 nvme_wait_freeze(&dev->ctrl);
5d02a5c1 2696 nvme_dev_add(dev);
302ad8cc 2697 nvme_unfreeze(&dev->ctrl);
3cf519b5
CH		 2698 }
2699
2b1b7e78
JW		 2700 /*
2701 * If only admin queue live, keep it to do further investigation or
2702 * recovery.
2703 */
5d02a5c1 2704 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
2b1b7e78 2705 dev_warn(dev->ctrl.device,
5d02a5c1 2706 "failed to mark controller live state\n");
e71afda4 2707 result = -ENODEV;
bb8d261e
CH		 2708 goto out;
2709 }
92911a55 2710
d09f2b45 2711 nvme_start_ctrl(&dev->ctrl);
3cf519b5 2712 return;
f0b50732 2713
4726bcf3
KB		 2714 out_unlock:
2715 mutex_unlock(&dev->shutdown_lock);
3cf519b5 2716 out:
7c1ce408
CK		 2717 if (result)
2718 dev_warn(dev->ctrl.device,
2719 "Removing after probe failure status: %d\n", result);
2720 nvme_remove_dead_ctrl(dev);
f0b50732
KB		 2721}
2722
5c8809e6 2723static void nvme_remove_dead_ctrl_work(struct work_struct *work)
9a6b9458 2724{
5c8809e6 2725 struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
e75ec752 2726 struct pci_dev *pdev = to_pci_dev(dev->dev);
9a6b9458
KB		 2727
2728 if (pci_get_drvdata(pdev))
921920ab 2729 device_release_driver(&pdev->dev);
1673f1f0 2730 nvme_put_ctrl(&dev->ctrl);
9a6b9458
KB		 2731}
2732
1c63dc66 2733static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
9ca97374 2734{
1c63dc66 2735 *val = readl(to_nvme_dev(ctrl)->bar + off);
90667892 2736 return 0;
9ca97374
TH		 2737}
2738
5fd4ce1b 2739static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
4cc06521 2740{
5fd4ce1b
CH		 2741 writel(val, to_nvme_dev(ctrl)->bar + off);
2742 return 0;
2743}
4cc06521 2744
7fd8930f
CH		 2745static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2746{
3a8ecc93 2747 *val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off);
7fd8930f 2748 return 0;
4cc06521
KB		 2749}
2750
97c12223
KB		 2751static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
2752{
2753 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2754
2db24e4a 2755 return snprintf(buf, size, "%s\n", dev_name(&pdev->dev));
97c12223
KB		 2756}
2757
1c63dc66 2758static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
1a353d85 2759 .name = "pcie",
e439bb12 2760 .module = THIS_MODULE,
e0596ab2
LG		 2761 .flags = NVME_F_METADATA_SUPPORTED |
2762 NVME_F_PCI_P2PDMA,
1c63dc66 2763 .reg_read32 = nvme_pci_reg_read32,
5fd4ce1b 2764 .reg_write32 = nvme_pci_reg_write32,
7fd8930f 2765 .reg_read64 = nvme_pci_reg_read64,
1673f1f0 2766 .free_ctrl = nvme_pci_free_ctrl,
f866fc42 2767 .submit_async_event = nvme_pci_submit_async_event,
97c12223 2768 .get_address = nvme_pci_get_address,
1c63dc66 2769};
4cc06521 2770
b00a726a
KB		 2771static int nvme_dev_map(struct nvme_dev *dev)
2772{
b00a726a
KB		 2773 struct pci_dev *pdev = to_pci_dev(dev->dev);
2774
a1f447b3 2775 if (pci_request_mem_regions(pdev, "nvme"))
b00a726a
KB		 2776 return -ENODEV;
2777
97f6ef64 2778 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
b00a726a
KB		 2779 goto release;
2780
9fa196e7 2781 return 0;
b00a726a 2782 release:
9fa196e7
MG		 2783 pci_release_mem_regions(pdev);
2784 return -ENODEV;
b00a726a
KB		 2785}
2786
8427bbc2 2787static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
ff5350a8
AL		 2788{
2789 if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
2790 /*
2791 * Several Samsung devices seem to drop off the PCIe bus
2792 * randomly when APST is on and uses the deepest sleep state.
2793 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2794 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2795 * 950 PRO 256GB", but it seems to be restricted to two Dell
2796 * laptops.
2797 */
2798 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
2799 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
2800 dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
2801 return NVME_QUIRK_NO_DEEPEST_PS;
8427bbc2
KHF		 2802 } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
2803 /*
2804 * Samsung SSD 960 EVO drops off the PCIe bus after system
467c77d4
JJ		 2805 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
2806 * within few minutes after bootup on a Coffee Lake board -
2807 * ASUS PRIME Z370-A
8427bbc2
KHF		 2808 */
2809 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
467c77d4
JJ		 2810 (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") ||
2811 dmi_match(DMI_BOARD_NAME, "PRIME Z370-A")))
8427bbc2 2812 return NVME_QUIRK_NO_APST;
1fae37ac
S		 2813 } else if ((pdev->vendor == 0x144d && (pdev->device == 0xa801 ||
2814 pdev->device == 0xa808 || pdev->device == 0xa809)) ||
2815 (pdev->vendor == 0x1e0f && pdev->device == 0x0001)) {
2816 /*
2817 * Forcing to use host managed nvme power settings for
2818 * lowest idle power with quick resume latency on
2819 * Samsung and Toshiba SSDs based on suspend behavior
2820 * on Coffee Lake board for LENOVO C640
2821 */
2822 if ((dmi_match(DMI_BOARD_VENDOR, "LENOVO")) &&
2823 dmi_match(DMI_BOARD_NAME, "LNVNB161216"))
2824 return NVME_QUIRK_SIMPLE_SUSPEND;
ff5350a8
AL		 2825 }
2826
2827 return 0;
2828}
2829
df4f9bc4
DB		 2830#ifdef CONFIG_ACPI
2831static bool nvme_acpi_storage_d3(struct pci_dev *dev)
2832{
2833 struct acpi_device *adev;
2834 struct pci_dev *root;
2835 acpi_handle handle;
2836 acpi_status status;
2837 u8 val;
2838
2839 /*
2840 * Look for _DSD property specifying that the storage device on the port
2841 * must use D3 to support deep platform power savings during
2842 * suspend-to-idle.
2843 */
2844 root = pcie_find_root_port(dev);
2845 if (!root)
2846 return false;
2847
2848 adev = ACPI_COMPANION(&root->dev);
2849 if (!adev)
2850 return false;
2851
2852 /*
2853 * The property is defined in the PXSX device for South complex ports
2854 * and in the PEGP device for North complex ports.
2855 */
2856 status = acpi_get_handle(adev->handle, "PXSX", &handle);
2857 if (ACPI_FAILURE(status)) {
2858 status = acpi_get_handle(adev->handle, "PEGP", &handle);
2859 if (ACPI_FAILURE(status))
2860 return false;
2861 }
2862
2863 if (acpi_bus_get_device(handle, &adev))
2864 return false;
2865
2866 if (fwnode_property_read_u8(acpi_fwnode_handle(adev), "StorageD3Enable",
2867 &val))
2868 return false;
2869 return val == 1;
2870}
2871#else
2872static inline bool nvme_acpi_storage_d3(struct pci_dev *dev)
2873{
2874 return false;
2875}
2876#endif /* CONFIG_ACPI */
2877
18119775
KB		 2878static void nvme_async_probe(void *data, async_cookie_t cookie)
2879{
2880 struct nvme_dev *dev = data;
80f513b5 2881
bd46a906 2882 flush_work(&dev->ctrl.reset_work);
18119775 2883 flush_work(&dev->ctrl.scan_work);
80f513b5 2884 nvme_put_ctrl(&dev->ctrl);
18119775
KB		 2885}
2886
8d85fce7 2887static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
b60503ba 2888{
a4aea562 2889 int node, result = -ENOMEM;
b60503ba 2890 struct nvme_dev *dev;
ff5350a8 2891 unsigned long quirks = id->driver_data;
943e942e 2892 size_t alloc_size;
b60503ba 2893
a4aea562
MB		 2894 node = dev_to_node(&pdev->dev);
2895 if (node == NUMA_NO_NODE)
2fa84351 2896 set_dev_node(&pdev->dev, first_memory_node);
a4aea562
MB		 2897
2898 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
b60503ba
MW		 2899 if (!dev)
2900 return -ENOMEM;
147b27e4 2901
2a5bcfdd
WZ		 2902 dev->nr_write_queues = write_queues;
2903 dev->nr_poll_queues = poll_queues;
2904 dev->nr_allocated_queues = nvme_max_io_queues(dev) + 1;
2905 dev->queues = kcalloc_node(dev->nr_allocated_queues,
2906 sizeof(struct nvme_queue), GFP_KERNEL, node);
b60503ba
MW		 2907 if (!dev->queues)
2908 goto free;
2909
e75ec752 2910 dev->dev = get_device(&pdev->dev);
9a6b9458 2911 pci_set_drvdata(pdev, dev);
1c63dc66 2912
b00a726a
KB		 2913 result = nvme_dev_map(dev);
2914 if (result)
b00c9b7a 2915 goto put_pci;
b00a726a 2916
d86c4d8e 2917 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
5c8809e6 2918 INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
77bf25ea 2919 mutex_init(&dev->shutdown_lock);
b60503ba 2920
091b6092
MW		 2921 result = nvme_setup_prp_pools(dev);
2922 if (result)
b00c9b7a 2923 goto unmap;
4cc06521 2924
8427bbc2 2925 quirks |= check_vendor_combination_bug(pdev);
ff5350a8 2926
df4f9bc4
DB		 2927 if (!noacpi && nvme_acpi_storage_d3(pdev)) {
2928 /*
2929 * Some systems use a bios work around to ask for D3 on
2930 * platforms that support kernel managed suspend.
2931 */
2932 dev_info(&pdev->dev,
2933 "platform quirk: setting simple suspend\n");
2934 quirks |= NVME_QUIRK_SIMPLE_SUSPEND;
2935 }
2936
943e942e
JA		 2937 /*
2938 * Double check that our mempool alloc size will cover the biggest
2939 * command we support.
2940 */
b13c6393 2941 alloc_size = nvme_pci_iod_alloc_size();
943e942e
JA		 2942 WARN_ON_ONCE(alloc_size > PAGE_SIZE);
2943
2944 dev->iod_mempool = mempool_create_node(1, mempool_kmalloc,
2945 mempool_kfree,
2946 (void *) alloc_size,
2947 GFP_KERNEL, node);
2948 if (!dev->iod_mempool) {
2949 result = -ENOMEM;
2950 goto release_pools;
2951 }
2952
b6e44b4c
KB		 2953 result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
2954 quirks);
2955 if (result)
2956 goto release_mempool;
2957
1b3c47c1
SG		 2958 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
2959
bd46a906 2960 nvme_reset_ctrl(&dev->ctrl);
18119775 2961 async_schedule(nvme_async_probe, dev);
4caff8fc 2962
b60503ba
MW		 2963 return 0;
2964
b6e44b4c
KB		 2965 release_mempool:
2966 mempool_destroy(dev->iod_mempool);
0877cb0d 2967 release_pools:
091b6092 2968 nvme_release_prp_pools(dev);
b00c9b7a
CJ		 2969 unmap:
2970 nvme_dev_unmap(dev);
a96d4f5c 2971 put_pci:
e75ec752 2972 put_device(dev->dev);
b60503ba
MW		 2973 free:
2974 kfree(dev->queues);
b60503ba
MW		 2975 kfree(dev);
2976 return result;
2977}
2978
775755ed 2979static void nvme_reset_prepare(struct pci_dev *pdev)
f0d54a54 2980{
a6739479 2981 struct nvme_dev *dev = pci_get_drvdata(pdev);
c1ac9a4b
KB		 2982
2983 /*
2984 * We don't need to check the return value from waiting for the reset
2985 * state as pci_dev device lock is held, making it impossible to race
2986 * with ->remove().
2987 */
2988 nvme_disable_prepare_reset(dev, false);
2989 nvme_sync_queues(&dev->ctrl);
775755ed 2990}
f0d54a54 2991
775755ed
CH		 2992static void nvme_reset_done(struct pci_dev *pdev)
2993{
f263fbb8 2994 struct nvme_dev *dev = pci_get_drvdata(pdev);
c1ac9a4b
KB		 2995
2996 if (!nvme_try_sched_reset(&dev->ctrl))
2997 flush_work(&dev->ctrl.reset_work);
f0d54a54
KB		 2998}
2999
09ece142
KB		 3000static void nvme_shutdown(struct pci_dev *pdev)
3001{
3002 struct nvme_dev *dev = pci_get_drvdata(pdev);
4e523547 3003
c1ac9a4b 3004 nvme_disable_prepare_reset(dev, true);
09ece142
KB		 3005}
3006
f58944e2
KB		 3007/*
3008 * The driver's remove may be called on a device in a partially initialized
3009 * state. This function must not have any dependencies on the device state in
3010 * order to proceed.
3011 */
8d85fce7 3012static void nvme_remove(struct pci_dev *pdev)
b60503ba
MW		 3013{
3014 struct nvme_dev *dev = pci_get_drvdata(pdev);
9a6b9458 3015
bb8d261e 3016 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
9a6b9458 3017 pci_set_drvdata(pdev, NULL);
0ff9d4e1 3018
6db28eda 3019 if (!pci_device_is_present(pdev)) {
0ff9d4e1 3020 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
1d39e692 3021 nvme_dev_disable(dev, true);
cb4bfda6 3022 nvme_dev_remove_admin(dev);
6db28eda 3023 }
0ff9d4e1 3024
d86c4d8e 3025 flush_work(&dev->ctrl.reset_work);
d09f2b45
SG		 3026 nvme_stop_ctrl(&dev->ctrl);
3027 nvme_remove_namespaces(&dev->ctrl);
a5cdb68c 3028 nvme_dev_disable(dev, true);
9fe5c59f 3029 nvme_release_cmb(dev);
87ad72a5 3030 nvme_free_host_mem(dev);
a4aea562 3031 nvme_dev_remove_admin(dev);
a1a5ef99 3032 nvme_free_queues(dev, 0);
9a6b9458 3033 nvme_release_prp_pools(dev);
b00a726a 3034 nvme_dev_unmap(dev);
726612b6 3035 nvme_uninit_ctrl(&dev->ctrl);
b60503ba
MW		 3036}
3037
671a6018 3038#ifdef CONFIG_PM_SLEEP
d916b1be
KB		 3039static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps)
3040{
3041 return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps);
3042}
3043
3044static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps)
3045{
3046 return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL);
3047}
3048
3049static int nvme_resume(struct device *dev)
3050{
3051 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
3052 struct nvme_ctrl *ctrl = &ndev->ctrl;
3053
4eaefe8c 3054 if (ndev->last_ps == U32_MAX ||
d916b1be 3055 nvme_set_power_state(ctrl, ndev->last_ps) != 0)
c1ac9a4b 3056 return nvme_try_sched_reset(&ndev->ctrl);
d916b1be
KB		 3057 return 0;
3058}
3059
cd638946
KB		 3060static int nvme_suspend(struct device *dev)
3061{
3062 struct pci_dev *pdev = to_pci_dev(dev);
3063 struct nvme_dev *ndev = pci_get_drvdata(pdev);
d916b1be
KB		 3064 struct nvme_ctrl *ctrl = &ndev->ctrl;
3065 int ret = -EBUSY;
3066
4eaefe8c
RW		 3067 ndev->last_ps = U32_MAX;
3068
d916b1be
KB		 3069 /*
3070 * The platform does not remove power for a kernel managed suspend so
3071 * use host managed nvme power settings for lowest idle power if
3072 * possible. This should have quicker resume latency than a full device
3073 * shutdown. But if the firmware is involved after the suspend or the
3074 * device does not support any non-default power states, shut down the
3075 * device fully.
4eaefe8c
RW		 3076 *
3077 * If ASPM is not enabled for the device, shut down the device and allow
3078 * the PCI bus layer to put it into D3 in order to take the PCIe link
3079 * down, so as to allow the platform to achieve its minimum low-power
3080 * state (which may not be possible if the link is up).
b97120b1
CH		 3081 *
3082 * If a host memory buffer is enabled, shut down the device as the NVMe
3083 * specification allows the device to access the host memory buffer in
3084 * host DRAM from all power states, but hosts will fail access to DRAM
3085 * during S3.
d916b1be 3086 */
4eaefe8c 3087 if (pm_suspend_via_firmware() || !ctrl->npss ||
cb32de1b 3088 !pcie_aspm_enabled(pdev) ||
b97120b1 3089 ndev->nr_host_mem_descs ||
c1ac9a4b
KB		 3090 (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND))
3091 return nvme_disable_prepare_reset(ndev, true);
d916b1be
KB		 3092
3093 nvme_start_freeze(ctrl);
3094 nvme_wait_freeze(ctrl);
3095 nvme_sync_queues(ctrl);
3096
5d02a5c1 3097 if (ctrl->state != NVME_CTRL_LIVE)
d916b1be
KB		 3098 goto unfreeze;
3099
d916b1be
KB		 3100 ret = nvme_get_power_state(ctrl, &ndev->last_ps);
3101 if (ret < 0)
3102 goto unfreeze;
3103
7cbb5c6f
ML		 3104 /*
3105 * A saved state prevents pci pm from generically controlling the
3106 * device's power. If we're using protocol specific settings, we don't
3107 * want pci interfering.
3108 */
3109 pci_save_state(pdev);
3110
d916b1be
KB		 3111 ret = nvme_set_power_state(ctrl, ctrl->npss);
3112 if (ret < 0)
3113 goto unfreeze;
3114
3115 if (ret) {
7cbb5c6f
ML		 3116 /* discard the saved state */
3117 pci_load_saved_state(pdev, NULL);
3118
d916b1be
KB		 3119 /*
3120 * Clearing npss forces a controller reset on resume. The
05d3046f 3121 * correct value will be rediscovered then.
d916b1be 3122 */
c1ac9a4b 3123 ret = nvme_disable_prepare_reset(ndev, true);
d916b1be 3124 ctrl->npss = 0;
d916b1be 3125 }
d916b1be
KB		 3126unfreeze:
3127 nvme_unfreeze(ctrl);
3128 return ret;
3129}
3130
3131static int nvme_simple_suspend(struct device *dev)
3132{
3133 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
4e523547 3134
c1ac9a4b 3135 return nvme_disable_prepare_reset(ndev, true);
cd638946
KB		 3136}
3137
d916b1be 3138static int nvme_simple_resume(struct device *dev)
cd638946
KB		 3139{
3140 struct pci_dev *pdev = to_pci_dev(dev);
3141 struct nvme_dev *ndev = pci_get_drvdata(pdev);
cd638946 3142
c1ac9a4b 3143 return nvme_try_sched_reset(&ndev->ctrl);
cd638946
KB		 3144}
3145
21774222 3146static const struct dev_pm_ops nvme_dev_pm_ops = {
d916b1be
KB		 3147 .suspend = nvme_suspend,
3148 .resume = nvme_resume,
3149 .freeze = nvme_simple_suspend,
3150 .thaw = nvme_simple_resume,
3151 .poweroff = nvme_simple_suspend,
3152 .restore = nvme_simple_resume,
3153};
3154#endif /* CONFIG_PM_SLEEP */
b60503ba 3155
a0a3408e
KB		 3156static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
3157 pci_channel_state_t state)
3158{
3159 struct nvme_dev *dev = pci_get_drvdata(pdev);
3160
3161 /*
3162 * A frozen channel requires a reset. When detected, this method will
3163 * shutdown the controller to quiesce. The controller will be restarted
3164 * after the slot reset through driver's slot_reset callback.
3165 */
a0a3408e
KB		 3166 switch (state) {
3167 case pci_channel_io_normal:
3168 return PCI_ERS_RESULT_CAN_RECOVER;
3169 case pci_channel_io_frozen:
d011fb31
KB		 3170 dev_warn(dev->ctrl.device,
3171 "frozen state error detected, reset controller\n");
a5cdb68c 3172 nvme_dev_disable(dev, false);
a0a3408e
KB		 3173 return PCI_ERS_RESULT_NEED_RESET;
3174 case pci_channel_io_perm_failure:
d011fb31
KB		 3175 dev_warn(dev->ctrl.device,
3176 "failure state error detected, request disconnect\n");
a0a3408e
KB		 3177 return PCI_ERS_RESULT_DISCONNECT;
3178 }
3179 return PCI_ERS_RESULT_NEED_RESET;
3180}
3181
3182static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
3183{
3184 struct nvme_dev *dev = pci_get_drvdata(pdev);
3185
1b3c47c1 3186 dev_info(dev->ctrl.device, "restart after slot reset\n");
a0a3408e 3187 pci_restore_state(pdev);
d86c4d8e 3188 nvme_reset_ctrl(&dev->ctrl);
a0a3408e
KB		 3189 return PCI_ERS_RESULT_RECOVERED;
3190}
3191
3192static void nvme_error_resume(struct pci_dev *pdev)
3193{
72cd4cc2
KB		 3194 struct nvme_dev *dev = pci_get_drvdata(pdev);
3195
3196 flush_work(&dev->ctrl.reset_work);
a0a3408e
KB		 3197}
3198
1d352035 3199static const struct pci_error_handlers nvme_err_handler = {
b60503ba 3200 .error_detected = nvme_error_detected,
b60503ba
MW		 3201 .slot_reset = nvme_slot_reset,
3202 .resume = nvme_error_resume,
775755ed
CH		 3203 .reset_prepare = nvme_reset_prepare,
3204 .reset_done = nvme_reset_done,
b60503ba
MW		 3205};
3206
6eb0d698 3207static const struct pci_device_id nvme_id_table[] = {
972b13e2 3208 { PCI_VDEVICE(INTEL, 0x0953), /* Intel 750/P3500/P3600/P3700 */
08095e70 3209 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 3210 NVME_QUIRK_DEALLOCATE_ZEROES, },
972b13e2 3211 { PCI_VDEVICE(INTEL, 0x0a53), /* Intel P3520 */
99466e70 3212 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 3213 NVME_QUIRK_DEALLOCATE_ZEROES, },
972b13e2 3214 { PCI_VDEVICE(INTEL, 0x0a54), /* Intel P4500/P4600 */
99466e70 3215 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 3216 NVME_QUIRK_DEALLOCATE_ZEROES, },
972b13e2 3217 { PCI_VDEVICE(INTEL, 0x0a55), /* Dell Express Flash P4600 */
f99cb7af
DWF		 3218 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3219 NVME_QUIRK_DEALLOCATE_ZEROES, },
50af47d0 3220 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */
9abd68ef 3221 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
6c6aa2f2 3222 NVME_QUIRK_MEDIUM_PRIO_SQ |
ce4cc313
DM		 3223 NVME_QUIRK_NO_TEMP_THRESH_CHANGE |
3224 NVME_QUIRK_DISABLE_WRITE_ZEROES, },
6299358d
JD		 3225 { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */
3226 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
540c801c 3227 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */
7b210e4e
CH		 3228 .driver_data = NVME_QUIRK_IDENTIFY_CNS |
3229 NVME_QUIRK_DISABLE_WRITE_ZEROES, },
5bedd3af
CH		 3230 { PCI_DEVICE(0x126f, 0x2263), /* Silicon Motion unidentified */
3231 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST, },
0302ae60
MP		 3232 { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */
3233 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
54adc010
GP		 3234 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
3235 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
8c97eecc
JL		 3236 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */
3237 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
015282c9
WW		 3238 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
3239 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
d554b5e1
MP		 3240 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */
3241 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3242 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */
7ee5c78c
GT		 3243 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
3244 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
608cc4b1
CH		 3245 { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */
3246 .driver_data = NVME_QUIRK_LIGHTNVM, },
3247 { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */
3248 .driver_data = NVME_QUIRK_LIGHTNVM, },
ea48e877
WX		 3249 { PCI_DEVICE(0x1d1d, 0x2601), /* CNEX Granby */
3250 .driver_data = NVME_QUIRK_LIGHTNVM, },
08b903b5
MN		 3251 { PCI_DEVICE(0x10ec, 0x5762), /* ADATA SX6000LNP */
3252 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
f03e42c6
GC		 3253 { PCI_DEVICE(0x1cc1, 0x8201), /* ADATA SX8200PNP 512GB */
3254 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3255 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
5611ec2b
KHF		 3256 { PCI_DEVICE(0x1c5c, 0x1504), /* SK Hynix PC400 */
3257 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
02ca079c
KHF		 3258 { PCI_DEVICE(0x15b7, 0x2001), /* Sandisk Skyhawk */
3259 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
98f7b86a
AS		 3260 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001),
3261 .driver_data = NVME_QUIRK_SINGLE_VECTOR },
124298bd 3262 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
66341331
BH		 3263 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005),
3264 .driver_data = NVME_QUIRK_SINGLE_VECTOR |
d38e9f04
BH		 3265 NVME_QUIRK_128_BYTES_SQES |
3266 NVME_QUIRK_SHARED_TAGS },
0b85f59d
AS		 3267
3268 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
b60503ba
MW		 3269 { 0, }
3270};
3271MODULE_DEVICE_TABLE(pci, nvme_id_table);
3272
3273static struct pci_driver nvme_driver = {
3274 .name = "nvme",
3275 .id_table = nvme_id_table,
3276 .probe = nvme_probe,
8d85fce7 3277 .remove = nvme_remove,
09ece142 3278 .shutdown = nvme_shutdown,
d916b1be 3279#ifdef CONFIG_PM_SLEEP
cd638946
KB		 3280 .driver = {
3281 .pm = &nvme_dev_pm_ops,
3282 },
d916b1be 3283#endif
74d986ab 3284 .sriov_configure = pci_sriov_configure_simple,
b60503ba
MW		 3285 .err_handler = &nvme_err_handler,
3286};
3287
3288static int __init nvme_init(void)
3289{
81101540
CH		 3290 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
3291 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
3292 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
612b7286 3293 BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2);
17c33167 3294
9a6327d2 3295 return pci_register_driver(&nvme_driver);
b60503ba
MW		 3296}
3297
3298static void __exit nvme_exit(void)
3299{
3300 pci_unregister_driver(&nvme_driver);
03e0f3a6 3301 flush_workqueue(nvme_wq);
b60503ba
MW		 3302}
3303
3304MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3305MODULE_LICENSE("GPL");
c78b4713 3306MODULE_VERSION("1.0");
b60503ba
MW		 3307module_init(nvme_init);
3308module_exit(nvme_exit);
Linux 6.x block layer and io_uring tree(s)