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nvme: host: core: fix precedence of ternary operator
[linux-2.6-block.git] / drivers / nvme / host / pci.c
CommitLineData
b60503ba
MW		 1/*
2 * NVM Express device driver
6eb0d698 3 * Copyright (c) 2011-2014, Intel Corporation.
b60503ba
MW		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
b60503ba
MW		 13 */
14
a0a3408e 15#include <linux/aer.h>
18119775 16#include <linux/async.h>
b60503ba 17#include <linux/blkdev.h>
a4aea562 18#include <linux/blk-mq.h>
dca51e78 19#include <linux/blk-mq-pci.h>
ff5350a8 20#include <linux/dmi.h>
b60503ba
MW		 21#include <linux/init.h>
22#include <linux/interrupt.h>
23#include <linux/io.h>
b60503ba
MW		 24#include <linux/mm.h>
25#include <linux/module.h>
77bf25ea 26#include <linux/mutex.h>
d0877473 27#include <linux/once.h>
b60503ba 28#include <linux/pci.h>
e1e5e564 29#include <linux/t10-pi.h>
b60503ba 30#include <linux/types.h>
2f8e2c87 31#include <linux/io-64-nonatomic-lo-hi.h>
a98e58e5 32#include <linux/sed-opal.h>
797a796a 33
f11bb3e2
CH		 34#include "nvme.h"
35
b60503ba
MW		 36#define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
37#define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
c965809c 38
a7a7cbe3 39#define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc))
9d43cf64 40
58ffacb5
MW		 41static int use_threaded_interrupts;
42module_param(use_threaded_interrupts, int, 0);
43
8ffaadf7
JD		 44static bool use_cmb_sqes = true;
45module_param(use_cmb_sqes, bool, 0644);
46MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
47
87ad72a5
CH		 48static unsigned int max_host_mem_size_mb = 128;
49module_param(max_host_mem_size_mb, uint, 0444);
50MODULE_PARM_DESC(max_host_mem_size_mb,
51 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
1fa6aead 52
a7a7cbe3
CK		 53static unsigned int sgl_threshold = SZ_32K;
54module_param(sgl_threshold, uint, 0644);
55MODULE_PARM_DESC(sgl_threshold,
56 "Use SGLs when average request segment size is larger or equal to "
57 "this size. Use 0 to disable SGLs.");
58
b27c1e68 59static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
60static const struct kernel_param_ops io_queue_depth_ops = {
61 .set = io_queue_depth_set,
62 .get = param_get_int,
63};
64
65static int io_queue_depth = 1024;
66module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
67MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2");
68
1c63dc66
CH		 69struct nvme_dev;
70struct nvme_queue;
b3fffdef 71
a5cdb68c 72static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
d4b4ff8e 73
1c63dc66
CH		 74/*
75 * Represents an NVM Express device. Each nvme_dev is a PCI function.
76 */
77struct nvme_dev {
147b27e4 78 struct nvme_queue *queues;
1c63dc66
CH		 79 struct blk_mq_tag_set tagset;
80 struct blk_mq_tag_set admin_tagset;
81 u32 __iomem *dbs;
82 struct device *dev;
83 struct dma_pool *prp_page_pool;
84 struct dma_pool *prp_small_pool;
1c63dc66
CH		 85 unsigned online_queues;
86 unsigned max_qid;
22b55601 87 unsigned int num_vecs;
1c63dc66
CH		 88 int q_depth;
89 u32 db_stride;
1c63dc66 90 void __iomem *bar;
97f6ef64 91 unsigned long bar_mapped_size;
5c8809e6 92 struct work_struct remove_work;
77bf25ea 93 struct mutex shutdown_lock;
1c63dc66 94 bool subsystem;
1c63dc66 95 void __iomem *cmb;
8969f1f8 96 pci_bus_addr_t cmb_bus_addr;
1c63dc66
CH		 97 u64 cmb_size;
98 u32 cmbsz;
202021c1 99 u32 cmbloc;
1c63dc66 100 struct nvme_ctrl ctrl;
db3cbfff 101 struct completion ioq_wait;
87ad72a5
CH		 102
103 /* shadow doorbell buffer support: */
f9f38e33
HK		 104 u32 *dbbuf_dbs;
105 dma_addr_t dbbuf_dbs_dma_addr;
106 u32 *dbbuf_eis;
107 dma_addr_t dbbuf_eis_dma_addr;
87ad72a5
CH		 108
109 /* host memory buffer support: */
110 u64 host_mem_size;
111 u32 nr_host_mem_descs;
4033f35d 112 dma_addr_t host_mem_descs_dma;
87ad72a5
CH		 113 struct nvme_host_mem_buf_desc *host_mem_descs;
114 void **host_mem_desc_bufs;
4d115420 115};
1fa6aead 116
b27c1e68 117static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
118{
119 int n = 0, ret;
120
121 ret = kstrtoint(val, 10, &n);
122 if (ret != 0 || n < 2)
123 return -EINVAL;
124
125 return param_set_int(val, kp);
126}
127
f9f38e33
HK		 128static inline unsigned int sq_idx(unsigned int qid, u32 stride)
129{
130 return qid * 2 * stride;
131}
132
133static inline unsigned int cq_idx(unsigned int qid, u32 stride)
134{
135 return (qid * 2 + 1) * stride;
136}
137
1c63dc66
CH		 138static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
139{
140 return container_of(ctrl, struct nvme_dev, ctrl);
141}
142
b60503ba
MW		 143/*
144 * An NVM Express queue. Each device has at least two (one for admin
145 * commands and one for I/O commands).
146 */
147struct nvme_queue {
148 struct device *q_dmadev;
091b6092 149 struct nvme_dev *dev;
1ab0cd69 150 spinlock_t sq_lock;
b60503ba 151 struct nvme_command *sq_cmds;
8ffaadf7 152 struct nvme_command __iomem *sq_cmds_io;
1ab0cd69 153 spinlock_t cq_lock ____cacheline_aligned_in_smp;
b60503ba 154 volatile struct nvme_completion *cqes;
42483228 155 struct blk_mq_tags **tags;
b60503ba
MW		 156 dma_addr_t sq_dma_addr;
157 dma_addr_t cq_dma_addr;
b60503ba
MW		 158 u32 __iomem *q_db;
159 u16 q_depth;
6222d172 160 s16 cq_vector;
b60503ba
MW		 161 u16 sq_tail;
162 u16 cq_head;
68fa9dbe 163 u16 last_cq_head;
c30341dc 164 u16 qid;
e9539f47 165 u8 cq_phase;
f9f38e33
HK		 166 u32 *dbbuf_sq_db;
167 u32 *dbbuf_cq_db;
168 u32 *dbbuf_sq_ei;
169 u32 *dbbuf_cq_ei;
b60503ba
MW		 170};
171
71bd150c
CH		 172/*
173 * The nvme_iod describes the data in an I/O, including the list of PRP
174 * entries. You can't see it in this data structure because C doesn't let
f4800d6d 175 * me express that. Use nvme_init_iod to ensure there's enough space
71bd150c
CH		 176 * allocated to store the PRP list.
177 */
178struct nvme_iod {
d49187e9 179 struct nvme_request req;
f4800d6d 180 struct nvme_queue *nvmeq;
a7a7cbe3 181 bool use_sgl;
f4800d6d 182 int aborted;
71bd150c 183 int npages; /* In the PRP list. 0 means small pool in use */
71bd150c
CH		 184 int nents; /* Used in scatterlist */
185 int length; /* Of data, in bytes */
186 dma_addr_t first_dma;
bf684057 187 struct scatterlist meta_sg; /* metadata requires single contiguous buffer */
f4800d6d
CH		 188 struct scatterlist *sg;
189 struct scatterlist inline_sg[0];
b60503ba
MW		 190};
191
192/*
193 * Check we didin't inadvertently grow the command struct
194 */
195static inline void _nvme_check_size(void)
196{
197 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
198 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
199 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
200 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
201 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
f8ebf840 202 BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
c30341dc 203 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
b60503ba 204 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
0add5e8e
JT		 205 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != NVME_IDENTIFY_DATA_SIZE);
206 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != NVME_IDENTIFY_DATA_SIZE);
b60503ba 207 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
6ecec745 208 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
f9f38e33
HK		 209 BUILD_BUG_ON(sizeof(struct nvme_dbbuf) != 64);
210}
211
212static inline unsigned int nvme_dbbuf_size(u32 stride)
213{
214 return ((num_possible_cpus() + 1) * 8 * stride);
215}
216
217static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
218{
219 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
220
221 if (dev->dbbuf_dbs)
222 return 0;
223
224 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
225 &dev->dbbuf_dbs_dma_addr,
226 GFP_KERNEL);
227 if (!dev->dbbuf_dbs)
228 return -ENOMEM;
229 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
230 &dev->dbbuf_eis_dma_addr,
231 GFP_KERNEL);
232 if (!dev->dbbuf_eis) {
233 dma_free_coherent(dev->dev, mem_size,
234 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
235 dev->dbbuf_dbs = NULL;
236 return -ENOMEM;
237 }
238
239 return 0;
240}
241
242static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
243{
244 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
245
246 if (dev->dbbuf_dbs) {
247 dma_free_coherent(dev->dev, mem_size,
248 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
249 dev->dbbuf_dbs = NULL;
250 }
251 if (dev->dbbuf_eis) {
252 dma_free_coherent(dev->dev, mem_size,
253 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
254 dev->dbbuf_eis = NULL;
255 }
256}
257
258static void nvme_dbbuf_init(struct nvme_dev *dev,
259 struct nvme_queue *nvmeq, int qid)
260{
261 if (!dev->dbbuf_dbs || !qid)
262 return;
263
264 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
265 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
266 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
267 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
268}
269
270static void nvme_dbbuf_set(struct nvme_dev *dev)
271{
272 struct nvme_command c;
273
274 if (!dev->dbbuf_dbs)
275 return;
276
277 memset(&c, 0, sizeof(c));
278 c.dbbuf.opcode = nvme_admin_dbbuf;
279 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
280 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
281
282 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
9bdcfb10 283 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
f9f38e33
HK		 284 /* Free memory and continue on */
285 nvme_dbbuf_dma_free(dev);
286 }
287}
288
289static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
290{
291 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
292}
293
294/* Update dbbuf and return true if an MMIO is required */
295static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
296 volatile u32 *dbbuf_ei)
297{
298 if (dbbuf_db) {
299 u16 old_value;
300
301 /*
302 * Ensure that the queue is written before updating
303 * the doorbell in memory
304 */
305 wmb();
306
307 old_value = *dbbuf_db;
308 *dbbuf_db = value;
309
310 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value))
311 return false;
312 }
313
314 return true;
b60503ba
MW		 315}
316
ac3dd5bd
JA		 317/*
318 * Max size of iod being embedded in the request payload
319 */
320#define NVME_INT_PAGES 2
5fd4ce1b 321#define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size)
ac3dd5bd
JA		 322
323/*
324 * Will slightly overestimate the number of pages needed. This is OK
325 * as it only leads to a small amount of wasted memory for the lifetime of
326 * the I/O.
327 */
328static int nvme_npages(unsigned size, struct nvme_dev *dev)
329{
5fd4ce1b
CH		 330 unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size,
331 dev->ctrl.page_size);
ac3dd5bd
JA		 332 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
333}
334
a7a7cbe3
CK		 335/*
336 * Calculates the number of pages needed for the SGL segments. For example a 4k
337 * page can accommodate 256 SGL descriptors.
338 */
339static int nvme_pci_npages_sgl(unsigned int num_seg)
ac3dd5bd 340{
a7a7cbe3 341 return DIV_ROUND_UP(num_seg * sizeof(struct nvme_sgl_desc), PAGE_SIZE);
f4800d6d 342}
ac3dd5bd 343
a7a7cbe3
CK		 344static unsigned int nvme_pci_iod_alloc_size(struct nvme_dev *dev,
345 unsigned int size, unsigned int nseg, bool use_sgl)
f4800d6d 346{
a7a7cbe3
CK		 347 size_t alloc_size;
348
349 if (use_sgl)
350 alloc_size = sizeof(__le64 *) * nvme_pci_npages_sgl(nseg);
351 else
352 alloc_size = sizeof(__le64 *) * nvme_npages(size, dev);
353
354 return alloc_size + sizeof(struct scatterlist) * nseg;
f4800d6d 355}
ac3dd5bd 356
a7a7cbe3 357static unsigned int nvme_pci_cmd_size(struct nvme_dev *dev, bool use_sgl)
f4800d6d 358{
a7a7cbe3
CK		 359 unsigned int alloc_size = nvme_pci_iod_alloc_size(dev,
360 NVME_INT_BYTES(dev), NVME_INT_PAGES,
361 use_sgl);
362
363 return sizeof(struct nvme_iod) + alloc_size;
ac3dd5bd
JA		 364}
365
a4aea562
MB		 366static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
367 unsigned int hctx_idx)
e85248e5 368{
a4aea562 369 struct nvme_dev *dev = data;
147b27e4 370 struct nvme_queue *nvmeq = &dev->queues[0];
a4aea562 371
42483228
KB		 372 WARN_ON(hctx_idx != 0);
373 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
374 WARN_ON(nvmeq->tags);
375
a4aea562 376 hctx->driver_data = nvmeq;
42483228 377 nvmeq->tags = &dev->admin_tagset.tags[0];
a4aea562 378 return 0;
e85248e5
MW		 379}
380
4af0e21c
KB		 381static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
382{
383 struct nvme_queue *nvmeq = hctx->driver_data;
384
385 nvmeq->tags = NULL;
386}
387
a4aea562
MB		 388static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
389 unsigned int hctx_idx)
b60503ba 390{
a4aea562 391 struct nvme_dev *dev = data;
147b27e4 392 struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
a4aea562 393
42483228
KB		 394 if (!nvmeq->tags)
395 nvmeq->tags = &dev->tagset.tags[hctx_idx];
b60503ba 396
42483228 397 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
a4aea562
MB		 398 hctx->driver_data = nvmeq;
399 return 0;
b60503ba
MW		 400}
401
d6296d39
CH		 402static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req,
403 unsigned int hctx_idx, unsigned int numa_node)
b60503ba 404{
d6296d39 405 struct nvme_dev *dev = set->driver_data;
f4800d6d 406 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
0350815a 407 int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0;
147b27e4 408 struct nvme_queue *nvmeq = &dev->queues[queue_idx];
a4aea562
MB		 409
410 BUG_ON(!nvmeq);
f4800d6d 411 iod->nvmeq = nvmeq;
a4aea562
MB		 412 return 0;
413}
414
dca51e78
CH		 415static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
416{
417 struct nvme_dev *dev = set->driver_data;
418
22b55601
KB		 419 return blk_mq_pci_map_queues(set, to_pci_dev(dev->dev),
420 dev->num_vecs > 1 ? 1 /* admin queue */ : 0);
dca51e78
CH		 421}
422
b60503ba 423/**
adf68f21 424 * __nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
b60503ba
MW		 425 * @nvmeq: The queue to use
426 * @cmd: The command to send
427 *
428 * Safe to use from interrupt context
429 */
e3f879bf
SB		 430static void __nvme_submit_cmd(struct nvme_queue *nvmeq,
431 struct nvme_command *cmd)
b60503ba 432{
a4aea562
MB		 433 u16 tail = nvmeq->sq_tail;
434
8ffaadf7
JD		 435 if (nvmeq->sq_cmds_io)
436 memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd));
437 else
438 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
439
b60503ba
MW		 440 if (++tail == nvmeq->q_depth)
441 tail = 0;
f9f38e33
HK		 442 if (nvme_dbbuf_update_and_check_event(tail, nvmeq->dbbuf_sq_db,
443 nvmeq->dbbuf_sq_ei))
444 writel(tail, nvmeq->q_db);
b60503ba 445 nvmeq->sq_tail = tail;
b60503ba
MW		 446}
447
a7a7cbe3 448static void **nvme_pci_iod_list(struct request *req)
b60503ba 449{
f4800d6d 450 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3 451 return (void **)(iod->sg + blk_rq_nr_phys_segments(req));
b60503ba
MW		 452}
453
955b1b5a
MI		 454static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req)
455{
456 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
20469a37 457 int nseg = blk_rq_nr_phys_segments(req);
955b1b5a
MI		 458 unsigned int avg_seg_size;
459
20469a37
KB		 460 if (nseg == 0)
461 return false;
462
463 avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
955b1b5a
MI		 464
465 if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1))))
466 return false;
467 if (!iod->nvmeq->qid)
468 return false;
469 if (!sgl_threshold || avg_seg_size < sgl_threshold)
470 return false;
471 return true;
472}
473
fc17b653 474static blk_status_t nvme_init_iod(struct request *rq, struct nvme_dev *dev)
ac3dd5bd 475{
f4800d6d 476 struct nvme_iod *iod = blk_mq_rq_to_pdu(rq);
f9d03f96 477 int nseg = blk_rq_nr_phys_segments(rq);
b131c61d 478 unsigned int size = blk_rq_payload_bytes(rq);
ac3dd5bd 479
955b1b5a
MI		 480 iod->use_sgl = nvme_pci_use_sgls(dev, rq);
481
f4800d6d 482 if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) {
a7a7cbe3
CK		 483 size_t alloc_size = nvme_pci_iod_alloc_size(dev, size, nseg,
484 iod->use_sgl);
485
486 iod->sg = kmalloc(alloc_size, GFP_ATOMIC);
f4800d6d 487 if (!iod->sg)
fc17b653 488 return BLK_STS_RESOURCE;
f4800d6d
CH		 489 } else {
490 iod->sg = iod->inline_sg;
ac3dd5bd
JA		 491 }
492
f4800d6d
CH		 493 iod->aborted = 0;
494 iod->npages = -1;
495 iod->nents = 0;
496 iod->length = size;
f80ec966 497
fc17b653 498 return BLK_STS_OK;
ac3dd5bd
JA		 499}
500
f4800d6d 501static void nvme_free_iod(struct nvme_dev *dev, struct request *req)
b60503ba 502{
f4800d6d 503 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3
CK		 504 const int last_prp = dev->ctrl.page_size / sizeof(__le64) - 1;
505 dma_addr_t dma_addr = iod->first_dma, next_dma_addr;
506
eca18b23 507 int i;
eca18b23
MW		 508
509 if (iod->npages == 0)
a7a7cbe3
CK		 510 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0],
511 dma_addr);
512
eca18b23 513 for (i = 0; i < iod->npages; i++) {
a7a7cbe3
CK		 514 void *addr = nvme_pci_iod_list(req)[i];
515
516 if (iod->use_sgl) {
517 struct nvme_sgl_desc *sg_list = addr;
518
519 next_dma_addr =
520 le64_to_cpu((sg_list[SGES_PER_PAGE - 1]).addr);
521 } else {
522 __le64 *prp_list = addr;
523
524 next_dma_addr = le64_to_cpu(prp_list[last_prp]);
525 }
526
527 dma_pool_free(dev->prp_page_pool, addr, dma_addr);
528 dma_addr = next_dma_addr;
eca18b23 529 }
ac3dd5bd 530
f4800d6d
CH		 531 if (iod->sg != iod->inline_sg)
532 kfree(iod->sg);
b4ff9c8d
KB		 533}
534
52b68d7e 535#ifdef CONFIG_BLK_DEV_INTEGRITY
e1e5e564
KB		 536static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
537{
538 if (be32_to_cpu(pi->ref_tag) == v)
539 pi->ref_tag = cpu_to_be32(p);
540}
541
542static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
543{
544 if (be32_to_cpu(pi->ref_tag) == p)
545 pi->ref_tag = cpu_to_be32(v);
546}
547
548/**
549 * nvme_dif_remap - remaps ref tags to bip seed and physical lba
550 *
551 * The virtual start sector is the one that was originally submitted by the
552 * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical
553 * start sector may be different. Remap protection information to match the
554 * physical LBA on writes, and back to the original seed on reads.
555 *
556 * Type 0 and 3 do not have a ref tag, so no remapping required.
557 */
558static void nvme_dif_remap(struct request *req,
559 void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
560{
561 struct nvme_ns *ns = req->rq_disk->private_data;
562 struct bio_integrity_payload *bip;
563 struct t10_pi_tuple *pi;
564 void *p, *pmap;
565 u32 i, nlb, ts, phys, virt;
566
567 if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3)
568 return;
569
570 bip = bio_integrity(req->bio);
571 if (!bip)
572 return;
573
574 pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset;
e1e5e564
KB		 575
576 p = pmap;
577 virt = bip_get_seed(bip);
578 phys = nvme_block_nr(ns, blk_rq_pos(req));
579 nlb = (blk_rq_bytes(req) >> ns->lba_shift);
ac6fc48c 580 ts = ns->disk->queue->integrity.tuple_size;
e1e5e564
KB		 581
582 for (i = 0; i < nlb; i++, virt++, phys++) {
583 pi = (struct t10_pi_tuple *)p;
584 dif_swap(phys, virt, pi);
585 p += ts;
586 }
587 kunmap_atomic(pmap);
588}
52b68d7e
KB		 589#else /* CONFIG_BLK_DEV_INTEGRITY */
590static void nvme_dif_remap(struct request *req,
591 void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
592{
593}
594static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
595{
596}
597static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
598{
599}
52b68d7e
KB		 600#endif
601
d0877473
KB		 602static void nvme_print_sgl(struct scatterlist *sgl, int nents)
603{
604 int i;
605 struct scatterlist *sg;
606
607 for_each_sg(sgl, sg, nents, i) {
608 dma_addr_t phys = sg_phys(sg);
609 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
610 "dma_address:%pad dma_length:%d\n",
611 i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
612 sg_dma_len(sg));
613 }
614}
615
a7a7cbe3
CK		 616static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
617 struct request *req, struct nvme_rw_command *cmnd)
ff22b54f 618{
f4800d6d 619 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
99802a7a 620 struct dma_pool *pool;
b131c61d 621 int length = blk_rq_payload_bytes(req);
eca18b23 622 struct scatterlist *sg = iod->sg;
ff22b54f
MW		 623 int dma_len = sg_dma_len(sg);
624 u64 dma_addr = sg_dma_address(sg);
5fd4ce1b 625 u32 page_size = dev->ctrl.page_size;
f137e0f1 626 int offset = dma_addr & (page_size - 1);
e025344c 627 __le64 *prp_list;
a7a7cbe3 628 void **list = nvme_pci_iod_list(req);
e025344c 629 dma_addr_t prp_dma;
eca18b23 630 int nprps, i;
ff22b54f 631
1d090624 632 length -= (page_size - offset);
5228b328
JS		 633 if (length <= 0) {
634 iod->first_dma = 0;
a7a7cbe3 635 goto done;
5228b328 636 }
ff22b54f 637
1d090624 638 dma_len -= (page_size - offset);
ff22b54f 639 if (dma_len) {
1d090624 640 dma_addr += (page_size - offset);
ff22b54f
MW		 641 } else {
642 sg = sg_next(sg);
643 dma_addr = sg_dma_address(sg);
644 dma_len = sg_dma_len(sg);
645 }
646
1d090624 647 if (length <= page_size) {
edd10d33 648 iod->first_dma = dma_addr;
a7a7cbe3 649 goto done;
e025344c
SMM		 650 }
651
1d090624 652 nprps = DIV_ROUND_UP(length, page_size);
99802a7a
MW		 653 if (nprps <= (256 / 8)) {
654 pool = dev->prp_small_pool;
eca18b23 655 iod->npages = 0;
99802a7a
MW		 656 } else {
657 pool = dev->prp_page_pool;
eca18b23 658 iod->npages = 1;
99802a7a
MW		 659 }
660
69d2b571 661 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
b77954cb 662 if (!prp_list) {
edd10d33 663 iod->first_dma = dma_addr;
eca18b23 664 iod->npages = -1;
86eea289 665 return BLK_STS_RESOURCE;
b77954cb 666 }
eca18b23
MW		 667 list[0] = prp_list;
668 iod->first_dma = prp_dma;
e025344c
SMM		 669 i = 0;
670 for (;;) {
1d090624 671 if (i == page_size >> 3) {
e025344c 672 __le64 *old_prp_list = prp_list;
69d2b571 673 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
eca18b23 674 if (!prp_list)
86eea289 675 return BLK_STS_RESOURCE;
eca18b23 676 list[iod->npages++] = prp_list;
7523d834
MW		 677 prp_list[0] = old_prp_list[i - 1];
678 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
679 i = 1;
e025344c
SMM		 680 }
681 prp_list[i++] = cpu_to_le64(dma_addr);
1d090624
KB		 682 dma_len -= page_size;
683 dma_addr += page_size;
684 length -= page_size;
e025344c
SMM		 685 if (length <= 0)
686 break;
687 if (dma_len > 0)
688 continue;
86eea289
KB		 689 if (unlikely(dma_len < 0))
690 goto bad_sgl;
e025344c
SMM		 691 sg = sg_next(sg);
692 dma_addr = sg_dma_address(sg);
693 dma_len = sg_dma_len(sg);
ff22b54f
MW		 694 }
695
a7a7cbe3
CK		 696done:
697 cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
698 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
699
86eea289
KB		 700 return BLK_STS_OK;
701
702 bad_sgl:
d0877473
KB		 703 WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents),
704 "Invalid SGL for payload:%d nents:%d\n",
705 blk_rq_payload_bytes(req), iod->nents);
86eea289 706 return BLK_STS_IOERR;
ff22b54f
MW		 707}
708
a7a7cbe3
CK		 709static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
710 struct scatterlist *sg)
711{
712 sge->addr = cpu_to_le64(sg_dma_address(sg));
713 sge->length = cpu_to_le32(sg_dma_len(sg));
714 sge->type = NVME_SGL_FMT_DATA_DESC << 4;
715}
716
717static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
718 dma_addr_t dma_addr, int entries)
719{
720 sge->addr = cpu_to_le64(dma_addr);
721 if (entries < SGES_PER_PAGE) {
722 sge->length = cpu_to_le32(entries * sizeof(*sge));
723 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
724 } else {
725 sge->length = cpu_to_le32(PAGE_SIZE);
726 sge->type = NVME_SGL_FMT_SEG_DESC << 4;
727 }
728}
729
730static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
b0f2853b 731 struct request *req, struct nvme_rw_command *cmd, int entries)
a7a7cbe3
CK		 732{
733 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3
CK		 734 struct dma_pool *pool;
735 struct nvme_sgl_desc *sg_list;
736 struct scatterlist *sg = iod->sg;
a7a7cbe3 737 dma_addr_t sgl_dma;
b0f2853b 738 int i = 0;
a7a7cbe3 739
a7a7cbe3
CK		 740 /* setting the transfer type as SGL */
741 cmd->flags = NVME_CMD_SGL_METABUF;
742
b0f2853b 743 if (entries == 1) {
a7a7cbe3
CK		 744 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
745 return BLK_STS_OK;
746 }
747
748 if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
749 pool = dev->prp_small_pool;
750 iod->npages = 0;
751 } else {
752 pool = dev->prp_page_pool;
753 iod->npages = 1;
754 }
755
756 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
757 if (!sg_list) {
758 iod->npages = -1;
759 return BLK_STS_RESOURCE;
760 }
761
762 nvme_pci_iod_list(req)[0] = sg_list;
763 iod->first_dma = sgl_dma;
764
765 nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
766
767 do {
768 if (i == SGES_PER_PAGE) {
769 struct nvme_sgl_desc *old_sg_desc = sg_list;
770 struct nvme_sgl_desc *link = &old_sg_desc[i - 1];
771
772 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
773 if (!sg_list)
774 return BLK_STS_RESOURCE;
775
776 i = 0;
777 nvme_pci_iod_list(req)[iod->npages++] = sg_list;
778 sg_list[i++] = *link;
779 nvme_pci_sgl_set_seg(link, sgl_dma, entries);
780 }
781
782 nvme_pci_sgl_set_data(&sg_list[i++], sg);
a7a7cbe3 783 sg = sg_next(sg);
b0f2853b 784 } while (--entries > 0);
a7a7cbe3 785
a7a7cbe3
CK		 786 return BLK_STS_OK;
787}
788
fc17b653 789static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
b131c61d 790 struct nvme_command *cmnd)
d29ec824 791{
f4800d6d 792 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
ba1ca37e
CH		 793 struct request_queue *q = req->q;
794 enum dma_data_direction dma_dir = rq_data_dir(req) ?
795 DMA_TO_DEVICE : DMA_FROM_DEVICE;
fc17b653 796 blk_status_t ret = BLK_STS_IOERR;
b0f2853b 797 int nr_mapped;
d29ec824 798
f9d03f96 799 sg_init_table(iod->sg, blk_rq_nr_phys_segments(req));
ba1ca37e
CH		 800 iod->nents = blk_rq_map_sg(q, req, iod->sg);
801 if (!iod->nents)
802 goto out;
d29ec824 803
fc17b653 804 ret = BLK_STS_RESOURCE;
b0f2853b
CH		 805 nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, dma_dir,
806 DMA_ATTR_NO_WARN);
807 if (!nr_mapped)
ba1ca37e 808 goto out;
d29ec824 809
955b1b5a 810 if (iod->use_sgl)
b0f2853b 811 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped);
a7a7cbe3
CK		 812 else
813 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
814
86eea289 815 if (ret != BLK_STS_OK)
ba1ca37e 816 goto out_unmap;
0e5e4f0e 817
fc17b653 818 ret = BLK_STS_IOERR;
ba1ca37e
CH		 819 if (blk_integrity_rq(req)) {
820 if (blk_rq_count_integrity_sg(q, req->bio) != 1)
821 goto out_unmap;
0e5e4f0e 822
bf684057
CH		 823 sg_init_table(&iod->meta_sg, 1);
824 if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1)
ba1ca37e 825 goto out_unmap;
0e5e4f0e 826
b5d8af5b 827 if (req_op(req) == REQ_OP_WRITE)
ba1ca37e 828 nvme_dif_remap(req, nvme_dif_prep);
0e5e4f0e 829
bf684057 830 if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir))
ba1ca37e 831 goto out_unmap;
d29ec824 832 }
00df5cb4 833
ba1ca37e 834 if (blk_integrity_rq(req))
bf684057 835 cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg));
fc17b653 836 return BLK_STS_OK;
00df5cb4 837
ba1ca37e
CH		 838out_unmap:
839 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
840out:
841 return ret;
00df5cb4
MW		 842}
843
f4800d6d 844static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
b60503ba 845{
f4800d6d 846 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
d4f6c3ab
CH		 847 enum dma_data_direction dma_dir = rq_data_dir(req) ?
848 DMA_TO_DEVICE : DMA_FROM_DEVICE;
849
850 if (iod->nents) {
851 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
852 if (blk_integrity_rq(req)) {
b5d8af5b 853 if (req_op(req) == REQ_OP_READ)
d4f6c3ab 854 nvme_dif_remap(req, nvme_dif_complete);
bf684057 855 dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir);
e1e5e564 856 }
e19b127f 857 }
e1e5e564 858
f9d03f96 859 nvme_cleanup_cmd(req);
f4800d6d 860 nvme_free_iod(dev, req);
d4f6c3ab 861}
b60503ba 862
d29ec824
CH		 863/*
864 * NOTE: ns is NULL when called on the admin queue.
865 */
fc17b653 866static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
a4aea562 867 const struct blk_mq_queue_data *bd)
edd10d33 868{
a4aea562
MB		 869 struct nvme_ns *ns = hctx->queue->queuedata;
870 struct nvme_queue *nvmeq = hctx->driver_data;
d29ec824 871 struct nvme_dev *dev = nvmeq->dev;
a4aea562 872 struct request *req = bd->rq;
ba1ca37e 873 struct nvme_command cmnd;
ebe6d874 874 blk_status_t ret;
e1e5e564 875
d1f06f4a
JA		 876 /*
877 * We should not need to do this, but we're still using this to
878 * ensure we can drain requests on a dying queue.
879 */
880 if (unlikely(nvmeq->cq_vector < 0))
881 return BLK_STS_IOERR;
882
f9d03f96 883 ret = nvme_setup_cmd(ns, req, &cmnd);
fc17b653 884 if (ret)
f4800d6d 885 return ret;
a4aea562 886
b131c61d 887 ret = nvme_init_iod(req, dev);
fc17b653 888 if (ret)
f9d03f96 889 goto out_free_cmd;
a4aea562 890
fc17b653 891 if (blk_rq_nr_phys_segments(req)) {
b131c61d 892 ret = nvme_map_data(dev, req, &cmnd);
fc17b653
CH		 893 if (ret)
894 goto out_cleanup_iod;
895 }
a4aea562 896
aae239e1 897 blk_mq_start_request(req);
a4aea562 898
1eae349d 899 spin_lock(&nvmeq->sq_lock);
ba1ca37e 900 __nvme_submit_cmd(nvmeq, &cmnd);
1eae349d 901 spin_unlock(&nvmeq->sq_lock);
fc17b653 902 return BLK_STS_OK;
f9d03f96 903out_cleanup_iod:
f4800d6d 904 nvme_free_iod(dev, req);
f9d03f96
CH		 905out_free_cmd:
906 nvme_cleanup_cmd(req);
ba1ca37e 907 return ret;
b60503ba 908}
e1e5e564 909
77f02a7a 910static void nvme_pci_complete_rq(struct request *req)
eee417b0 911{
f4800d6d 912 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a4aea562 913
77f02a7a
CH		 914 nvme_unmap_data(iod->nvmeq->dev, req);
915 nvme_complete_rq(req);
b60503ba
MW		 916}
917
d783e0bd 918/* We read the CQE phase first to check if the rest of the entry is valid */
750dde44 919static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq)
d783e0bd 920{
750dde44
CH		 921 return (le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) ==
922 nvmeq->cq_phase;
d783e0bd
MR		 923}
924
eb281c82 925static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
b60503ba 926{
eb281c82 927 u16 head = nvmeq->cq_head;
adf68f21 928
eb281c82
SG		 929 if (likely(nvmeq->cq_vector >= 0)) {
930 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
931 nvmeq->dbbuf_cq_ei))
932 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
933 }
934}
aae239e1 935
5cb525c8 936static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx)
83a12fb7 937{
5cb525c8 938 volatile struct nvme_completion *cqe = &nvmeq->cqes[idx];
83a12fb7 939 struct request *req;
adf68f21 940
83a12fb7
SG		 941 if (unlikely(cqe->command_id >= nvmeq->q_depth)) {
942 dev_warn(nvmeq->dev->ctrl.device,
943 "invalid id %d completed on queue %d\n",
944 cqe->command_id, le16_to_cpu(cqe->sq_id));
945 return;
b60503ba
MW		 946 }
947
83a12fb7
SG		 948 /*
949 * AEN requests are special as they don't time out and can
950 * survive any kind of queue freeze and often don't respond to
951 * aborts. We don't even bother to allocate a struct request
952 * for them but rather special case them here.
953 */
954 if (unlikely(nvmeq->qid == 0 &&
38dabe21 955 cqe->command_id >= NVME_AQ_BLK_MQ_DEPTH)) {
83a12fb7
SG		 956 nvme_complete_async_event(&nvmeq->dev->ctrl,
957 cqe->status, &cqe->result);
a0fa9647 958 return;
83a12fb7 959 }
b60503ba 960
83a12fb7
SG		 961 req = blk_mq_tag_to_rq(*nvmeq->tags, cqe->command_id);
962 nvme_end_request(req, cqe->status, cqe->result);
963}
b60503ba 964
5cb525c8 965static void nvme_complete_cqes(struct nvme_queue *nvmeq, u16 start, u16 end)
b60503ba 966{
5cb525c8
JA		 967 while (start != end) {
968 nvme_handle_cqe(nvmeq, start);
969 if (++start == nvmeq->q_depth)
970 start = 0;
971 }
972}
adf68f21 973
5cb525c8
JA		 974static inline void nvme_update_cq_head(struct nvme_queue *nvmeq)
975{
976 if (++nvmeq->cq_head == nvmeq->q_depth) {
977 nvmeq->cq_head = 0;
978 nvmeq->cq_phase = !nvmeq->cq_phase;
b60503ba 979 }
a0fa9647
JA		 980}
981
5cb525c8
JA		 982static inline bool nvme_process_cq(struct nvme_queue *nvmeq, u16 *start,
983 u16 *end, int tag)
a0fa9647 984{
5cb525c8 985 bool found = false;
b60503ba 986
5cb525c8
JA		 987 *start = nvmeq->cq_head;
988 while (!found && nvme_cqe_pending(nvmeq)) {
989 if (nvmeq->cqes[nvmeq->cq_head].command_id == tag)
990 found = true;
991 nvme_update_cq_head(nvmeq);
920d13a8 992 }
5cb525c8 993 *end = nvmeq->cq_head;
eb281c82 994
5cb525c8 995 if (*start != *end)
920d13a8 996 nvme_ring_cq_doorbell(nvmeq);
5cb525c8 997 return found;
b60503ba
MW		 998}
999
1000static irqreturn_t nvme_irq(int irq, void *data)
58ffacb5 1001{
58ffacb5 1002 struct nvme_queue *nvmeq = data;
68fa9dbe 1003 irqreturn_t ret = IRQ_NONE;
5cb525c8
JA		 1004 u16 start, end;
1005
1ab0cd69 1006 spin_lock(&nvmeq->cq_lock);
68fa9dbe
JA		 1007 if (nvmeq->cq_head != nvmeq->last_cq_head)
1008 ret = IRQ_HANDLED;
5cb525c8 1009 nvme_process_cq(nvmeq, &start, &end, -1);
68fa9dbe 1010 nvmeq->last_cq_head = nvmeq->cq_head;
1ab0cd69 1011 spin_unlock(&nvmeq->cq_lock);
5cb525c8 1012
68fa9dbe
JA		 1013 if (start != end) {
1014 nvme_complete_cqes(nvmeq, start, end);
1015 return IRQ_HANDLED;
1016 }
1017
1018 return ret;
58ffacb5
MW		 1019}
1020
1021static irqreturn_t nvme_irq_check(int irq, void *data)
1022{
1023 struct nvme_queue *nvmeq = data;
750dde44 1024 if (nvme_cqe_pending(nvmeq))
d783e0bd
MR		 1025 return IRQ_WAKE_THREAD;
1026 return IRQ_NONE;
58ffacb5
MW		 1027}
1028
7776db1c 1029static int __nvme_poll(struct nvme_queue *nvmeq, unsigned int tag)
a0fa9647 1030{
5cb525c8
JA		 1031 u16 start, end;
1032 bool found;
a0fa9647 1033
750dde44 1034 if (!nvme_cqe_pending(nvmeq))
442e19b7 1035 return 0;
a0fa9647 1036
1ab0cd69 1037 spin_lock_irq(&nvmeq->cq_lock);
5cb525c8 1038 found = nvme_process_cq(nvmeq, &start, &end, tag);
1ab0cd69 1039 spin_unlock_irq(&nvmeq->cq_lock);
442e19b7 1040
5cb525c8 1041 nvme_complete_cqes(nvmeq, start, end);
442e19b7 1042 return found;
a0fa9647
JA		 1043}
1044
7776db1c
KB		 1045static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag)
1046{
1047 struct nvme_queue *nvmeq = hctx->driver_data;
1048
1049 return __nvme_poll(nvmeq, tag);
1050}
1051
ad22c355 1052static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
b60503ba 1053{
f866fc42 1054 struct nvme_dev *dev = to_nvme_dev(ctrl);
147b27e4 1055 struct nvme_queue *nvmeq = &dev->queues[0];
a4aea562 1056 struct nvme_command c;
b60503ba 1057
a4aea562
MB		 1058 memset(&c, 0, sizeof(c));
1059 c.common.opcode = nvme_admin_async_event;
ad22c355 1060 c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
3c0cf138 1061
1eae349d 1062 spin_lock(&nvmeq->sq_lock);
f866fc42 1063 __nvme_submit_cmd(nvmeq, &c);
1eae349d 1064 spin_unlock(&nvmeq->sq_lock);
f705f837
CH		 1065}
1066
b60503ba 1067static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
f705f837 1068{
b60503ba
MW		 1069 struct nvme_command c;
1070
1071 memset(&c, 0, sizeof(c));
1072 c.delete_queue.opcode = opcode;
1073 c.delete_queue.qid = cpu_to_le16(id);
1074
1c63dc66 1075 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1076}
1077
b60503ba
MW		 1078static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
1079 struct nvme_queue *nvmeq)
1080{
b60503ba
MW		 1081 struct nvme_command c;
1082 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
1083
d29ec824 1084 /*
16772ae6 1085 * Note: we (ab)use the fact that the prp fields survive if no data
d29ec824
CH		 1086 * is attached to the request.
1087 */
b60503ba
MW		 1088 memset(&c, 0, sizeof(c));
1089 c.create_cq.opcode = nvme_admin_create_cq;
1090 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1091 c.create_cq.cqid = cpu_to_le16(qid);
1092 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1093 c.create_cq.cq_flags = cpu_to_le16(flags);
1094 c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
1095
1c63dc66 1096 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1097}
1098
1099static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1100 struct nvme_queue *nvmeq)
1101{
b60503ba 1102 struct nvme_command c;
81c1cd98 1103 int flags = NVME_QUEUE_PHYS_CONTIG;
b60503ba 1104
d29ec824 1105 /*
16772ae6 1106 * Note: we (ab)use the fact that the prp fields survive if no data
d29ec824
CH		 1107 * is attached to the request.
1108 */
b60503ba
MW		 1109 memset(&c, 0, sizeof(c));
1110 c.create_sq.opcode = nvme_admin_create_sq;
1111 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1112 c.create_sq.sqid = cpu_to_le16(qid);
1113 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1114 c.create_sq.sq_flags = cpu_to_le16(flags);
1115 c.create_sq.cqid = cpu_to_le16(qid);
1116
1c63dc66 1117 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1118}
1119
1120static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1121{
1122 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1123}
1124
1125static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1126{
1127 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1128}
1129
2a842aca 1130static void abort_endio(struct request *req, blk_status_t error)
bc5fc7e4 1131{
f4800d6d
CH		 1132 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1133 struct nvme_queue *nvmeq = iod->nvmeq;
e44ac588 1134
27fa9bc5
CH		 1135 dev_warn(nvmeq->dev->ctrl.device,
1136 "Abort status: 0x%x", nvme_req(req)->status);
e7a2a87d 1137 atomic_inc(&nvmeq->dev->ctrl.abort_limit);
e7a2a87d 1138 blk_mq_free_request(req);
bc5fc7e4
MW		 1139}
1140
b2a0eb1a
KB		 1141static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1142{
1143
1144 /* If true, indicates loss of adapter communication, possibly by a
1145 * NVMe Subsystem reset.
1146 */
1147 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1148
ad70062c
JW		 1149 /* If there is a reset/reinit ongoing, we shouldn't reset again. */
1150 switch (dev->ctrl.state) {
1151 case NVME_CTRL_RESETTING:
ad6a0a52 1152 case NVME_CTRL_CONNECTING:
b2a0eb1a 1153 return false;
ad70062c
JW		 1154 default:
1155 break;
1156 }
b2a0eb1a
KB		 1157
1158 /* We shouldn't reset unless the controller is on fatal error state
1159 * _or_ if we lost the communication with it.
1160 */
1161 if (!(csts & NVME_CSTS_CFS) && !nssro)
1162 return false;
1163
b2a0eb1a
KB		 1164 return true;
1165}
1166
1167static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1168{
1169 /* Read a config register to help see what died. */
1170 u16 pci_status;
1171 int result;
1172
1173 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1174 &pci_status);
1175 if (result == PCIBIOS_SUCCESSFUL)
1176 dev_warn(dev->ctrl.device,
1177 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1178 csts, pci_status);
1179 else
1180 dev_warn(dev->ctrl.device,
1181 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1182 csts, result);
1183}
1184
31c7c7d2 1185static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
c30341dc 1186{
f4800d6d
CH		 1187 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1188 struct nvme_queue *nvmeq = iod->nvmeq;
c30341dc 1189 struct nvme_dev *dev = nvmeq->dev;
a4aea562 1190 struct request *abort_req;
a4aea562 1191 struct nvme_command cmd;
b2a0eb1a
KB		 1192 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1193
651438bb
WX		 1194 /* If PCI error recovery process is happening, we cannot reset or
1195 * the recovery mechanism will surely fail.
1196 */
1197 mb();
1198 if (pci_channel_offline(to_pci_dev(dev->dev)))
1199 return BLK_EH_RESET_TIMER;
1200
b2a0eb1a
KB		 1201 /*
1202 * Reset immediately if the controller is failed
1203 */
1204 if (nvme_should_reset(dev, csts)) {
1205 nvme_warn_reset(dev, csts);
1206 nvme_dev_disable(dev, false);
d86c4d8e 1207 nvme_reset_ctrl(&dev->ctrl);
b2a0eb1a
KB		 1208 return BLK_EH_HANDLED;
1209 }
c30341dc 1210
7776db1c
KB		 1211 /*
1212 * Did we miss an interrupt?
1213 */
1214 if (__nvme_poll(nvmeq, req->tag)) {
1215 dev_warn(dev->ctrl.device,
1216 "I/O %d QID %d timeout, completion polled\n",
1217 req->tag, nvmeq->qid);
1218 return BLK_EH_HANDLED;
1219 }
1220
31c7c7d2 1221 /*
fd634f41
CH		 1222 * Shutdown immediately if controller times out while starting. The
1223 * reset work will see the pci device disabled when it gets the forced
1224 * cancellation error. All outstanding requests are completed on
1225 * shutdown, so we return BLK_EH_HANDLED.
1226 */
4244140d
KB		 1227 switch (dev->ctrl.state) {
1228 case NVME_CTRL_CONNECTING:
1229 case NVME_CTRL_RESETTING:
1b3c47c1 1230 dev_warn(dev->ctrl.device,
fd634f41
CH		 1231 "I/O %d QID %d timeout, disable controller\n",
1232 req->tag, nvmeq->qid);
a5cdb68c 1233 nvme_dev_disable(dev, false);
27fa9bc5 1234 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
fd634f41 1235 return BLK_EH_HANDLED;
4244140d
KB		 1236 default:
1237 break;
c30341dc
KB		 1238 }
1239
fd634f41
CH		 1240 /*
1241 * Shutdown the controller immediately and schedule a reset if the
1242 * command was already aborted once before and still hasn't been
1243 * returned to the driver, or if this is the admin queue.
31c7c7d2 1244 */
f4800d6d 1245 if (!nvmeq->qid || iod->aborted) {
1b3c47c1 1246 dev_warn(dev->ctrl.device,
e1569a16
KB		 1247 "I/O %d QID %d timeout, reset controller\n",
1248 req->tag, nvmeq->qid);
a5cdb68c 1249 nvme_dev_disable(dev, false);
d86c4d8e 1250 nvme_reset_ctrl(&dev->ctrl);
c30341dc 1251
e1569a16
KB		 1252 /*
1253 * Mark the request as handled, since the inline shutdown
1254 * forces all outstanding requests to complete.
1255 */
27fa9bc5 1256 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
e1569a16 1257 return BLK_EH_HANDLED;
c30341dc 1258 }
c30341dc 1259
e7a2a87d 1260 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
6bf25d16 1261 atomic_inc(&dev->ctrl.abort_limit);
31c7c7d2 1262 return BLK_EH_RESET_TIMER;
6bf25d16 1263 }
7bf7d778 1264 iod->aborted = 1;
a4aea562 1265
c30341dc
KB		 1266 memset(&cmd, 0, sizeof(cmd));
1267 cmd.abort.opcode = nvme_admin_abort_cmd;
a4aea562 1268 cmd.abort.cid = req->tag;
c30341dc 1269 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
c30341dc 1270
1b3c47c1
SG		 1271 dev_warn(nvmeq->dev->ctrl.device,
1272 "I/O %d QID %d timeout, aborting\n",
1273 req->tag, nvmeq->qid);
e7a2a87d
CH		 1274
1275 abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
eb71f435 1276 BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
e7a2a87d
CH		 1277 if (IS_ERR(abort_req)) {
1278 atomic_inc(&dev->ctrl.abort_limit);
1279 return BLK_EH_RESET_TIMER;
1280 }
1281
1282 abort_req->timeout = ADMIN_TIMEOUT;
1283 abort_req->end_io_data = NULL;
1284 blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio);
c30341dc 1285
31c7c7d2
CH		 1286 /*
1287 * The aborted req will be completed on receiving the abort req.
1288 * We enable the timer again. If hit twice, it'll cause a device reset,
1289 * as the device then is in a faulty state.
1290 */
1291 return BLK_EH_RESET_TIMER;
c30341dc
KB		 1292}
1293
a4aea562
MB		 1294static void nvme_free_queue(struct nvme_queue *nvmeq)
1295{
9e866774
MW		 1296 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1297 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
8ffaadf7
JD		 1298 if (nvmeq->sq_cmds)
1299 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
9e866774 1300 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
9e866774
MW		 1301}
1302
a1a5ef99 1303static void nvme_free_queues(struct nvme_dev *dev, int lowest)
22404274
KB		 1304{
1305 int i;
1306
d858e5f0 1307 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
d858e5f0 1308 dev->ctrl.queue_count--;
147b27e4 1309 nvme_free_queue(&dev->queues[i]);
121c7ad4 1310 }
22404274
KB		 1311}
1312
4d115420
KB		 1313/**
1314 * nvme_suspend_queue - put queue into suspended state
1315 * @nvmeq - queue to suspend
4d115420
KB		 1316 */
1317static int nvme_suspend_queue(struct nvme_queue *nvmeq)
b60503ba 1318{
2b25d981 1319 int vector;
b60503ba 1320
1ab0cd69 1321 spin_lock_irq(&nvmeq->cq_lock);
2b25d981 1322 if (nvmeq->cq_vector == -1) {
1ab0cd69 1323 spin_unlock_irq(&nvmeq->cq_lock);
2b25d981
KB		 1324 return 1;
1325 }
0ff199cb 1326 vector = nvmeq->cq_vector;
42f61420 1327 nvmeq->dev->online_queues--;
2b25d981 1328 nvmeq->cq_vector = -1;
1ab0cd69 1329 spin_unlock_irq(&nvmeq->cq_lock);
a09115b2 1330
d1f06f4a
JA		 1331 /*
1332 * Ensure that nvme_queue_rq() sees it ->cq_vector == -1 without
1333 * having to grab the lock.
1334 */
1335 mb();
1336
1c63dc66 1337 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
c81545f9 1338 blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q);
6df3dbc8 1339
0ff199cb 1340 pci_free_irq(to_pci_dev(nvmeq->dev->dev), vector, nvmeq);
b60503ba 1341
4d115420
KB		 1342 return 0;
1343}
b60503ba 1344
a5cdb68c 1345static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
4d115420 1346{
147b27e4 1347 struct nvme_queue *nvmeq = &dev->queues[0];
5cb525c8 1348 u16 start, end;
4d115420 1349
a5cdb68c
KB		 1350 if (shutdown)
1351 nvme_shutdown_ctrl(&dev->ctrl);
1352 else
20d0dfe6 1353 nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap);
07836e65 1354
1ab0cd69 1355 spin_lock_irq(&nvmeq->cq_lock);
5cb525c8 1356 nvme_process_cq(nvmeq, &start, &end, -1);
1ab0cd69 1357 spin_unlock_irq(&nvmeq->cq_lock);
5cb525c8
JA		 1358
1359 nvme_complete_cqes(nvmeq, start, end);
b60503ba
MW		 1360}
1361
8ffaadf7
JD		 1362static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1363 int entry_size)
1364{
1365 int q_depth = dev->q_depth;
5fd4ce1b
CH		 1366 unsigned q_size_aligned = roundup(q_depth * entry_size,
1367 dev->ctrl.page_size);
8ffaadf7
JD		 1368
1369 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
c45f5c99 1370 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
5fd4ce1b 1371 mem_per_q = round_down(mem_per_q, dev->ctrl.page_size);
c45f5c99 1372 q_depth = div_u64(mem_per_q, entry_size);
8ffaadf7
JD		 1373
1374 /*
1375 * Ensure the reduced q_depth is above some threshold where it
1376 * would be better to map queues in system memory with the
1377 * original depth
1378 */
1379 if (q_depth < 64)
1380 return -ENOMEM;
1381 }
1382
1383 return q_depth;
1384}
1385
1386static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1387 int qid, int depth)
1388{
815c6704
KB		 1389 /* CMB SQEs will be mapped before creation */
1390 if (qid && dev->cmb && use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS))
1391 return 0;
8ffaadf7 1392
815c6704
KB		 1393 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
1394 &nvmeq->sq_dma_addr, GFP_KERNEL);
1395 if (!nvmeq->sq_cmds)
1396 return -ENOMEM;
8ffaadf7
JD		 1397 return 0;
1398}
1399
a6ff7262 1400static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
b60503ba 1401{
147b27e4 1402 struct nvme_queue *nvmeq = &dev->queues[qid];
b60503ba 1403
62314e40
KB		 1404 if (dev->ctrl.queue_count > qid)
1405 return 0;
b60503ba 1406
e75ec752 1407 nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth),
4d51abf9 1408 &nvmeq->cq_dma_addr, GFP_KERNEL);
b60503ba
MW		 1409 if (!nvmeq->cqes)
1410 goto free_nvmeq;
b60503ba 1411
8ffaadf7 1412 if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth))
b60503ba
MW		 1413 goto free_cqdma;
1414
e75ec752 1415 nvmeq->q_dmadev = dev->dev;
091b6092 1416 nvmeq->dev = dev;
1ab0cd69
JA		 1417 spin_lock_init(&nvmeq->sq_lock);
1418 spin_lock_init(&nvmeq->cq_lock);
b60503ba 1419 nvmeq->cq_head = 0;
82123460 1420 nvmeq->cq_phase = 1;
b80d5ccc 1421 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
b60503ba 1422 nvmeq->q_depth = depth;
c30341dc 1423 nvmeq->qid = qid;
758dd7fd 1424 nvmeq->cq_vector = -1;
d858e5f0 1425 dev->ctrl.queue_count++;
36a7e993 1426
147b27e4 1427 return 0;
b60503ba
MW		 1428
1429 free_cqdma:
e75ec752 1430 dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes,
b60503ba
MW		 1431 nvmeq->cq_dma_addr);
1432 free_nvmeq:
147b27e4 1433 return -ENOMEM;
b60503ba
MW		 1434}
1435
dca51e78 1436static int queue_request_irq(struct nvme_queue *nvmeq)
3001082c 1437{
0ff199cb
CH		 1438 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1439 int nr = nvmeq->dev->ctrl.instance;
1440
1441 if (use_threaded_interrupts) {
1442 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1443 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1444 } else {
1445 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1446 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1447 }
3001082c
MW		 1448}
1449
22404274 1450static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
b60503ba 1451{
22404274 1452 struct nvme_dev *dev = nvmeq->dev;
b60503ba 1453
1ab0cd69 1454 spin_lock_irq(&nvmeq->cq_lock);
22404274
KB		 1455 nvmeq->sq_tail = 0;
1456 nvmeq->cq_head = 0;
1457 nvmeq->cq_phase = 1;
b80d5ccc 1458 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
22404274 1459 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
f9f38e33 1460 nvme_dbbuf_init(dev, nvmeq, qid);
42f61420 1461 dev->online_queues++;
1ab0cd69 1462 spin_unlock_irq(&nvmeq->cq_lock);
22404274
KB		 1463}
1464
1465static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1466{
1467 struct nvme_dev *dev = nvmeq->dev;
1468 int result;
3f85d50b 1469
815c6704
KB		 1470 if (dev->cmb && use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
1471 unsigned offset = (qid - 1) * roundup(SQ_SIZE(nvmeq->q_depth),
1472 dev->ctrl.page_size);
1473 nvmeq->sq_dma_addr = dev->cmb_bus_addr + offset;
1474 nvmeq->sq_cmds_io = dev->cmb + offset;
1475 }
1476
22b55601
KB		 1477 /*
1478 * A queue's vector matches the queue identifier unless the controller
1479 * has only one vector available.
1480 */
1481 nvmeq->cq_vector = dev->num_vecs == 1 ? 0 : qid;
b60503ba
MW		 1482 result = adapter_alloc_cq(dev, qid, nvmeq);
1483 if (result < 0)
f25a2dfc 1484 goto release_vector;
b60503ba
MW		 1485
1486 result = adapter_alloc_sq(dev, qid, nvmeq);
1487 if (result < 0)
1488 goto release_cq;
1489
161b8be2 1490 nvme_init_queue(nvmeq, qid);
dca51e78 1491 result = queue_request_irq(nvmeq);
b60503ba
MW		 1492 if (result < 0)
1493 goto release_sq;
1494
22404274 1495 return result;
b60503ba
MW		 1496
1497 release_sq:
f25a2dfc 1498 dev->online_queues--;
b60503ba
MW		 1499 adapter_delete_sq(dev, qid);
1500 release_cq:
1501 adapter_delete_cq(dev, qid);
f25a2dfc
JW		 1502 release_vector:
1503 nvmeq->cq_vector = -1;
22404274 1504 return result;
b60503ba
MW		 1505}
1506
f363b089 1507static const struct blk_mq_ops nvme_mq_admin_ops = {
d29ec824 1508 .queue_rq = nvme_queue_rq,
77f02a7a 1509 .complete = nvme_pci_complete_rq,
a4aea562 1510 .init_hctx = nvme_admin_init_hctx,
4af0e21c 1511 .exit_hctx = nvme_admin_exit_hctx,
0350815a 1512 .init_request = nvme_init_request,
a4aea562
MB		 1513 .timeout = nvme_timeout,
1514};
1515
f363b089 1516static const struct blk_mq_ops nvme_mq_ops = {
a4aea562 1517 .queue_rq = nvme_queue_rq,
77f02a7a 1518 .complete = nvme_pci_complete_rq,
a4aea562
MB		 1519 .init_hctx = nvme_init_hctx,
1520 .init_request = nvme_init_request,
dca51e78 1521 .map_queues = nvme_pci_map_queues,
a4aea562 1522 .timeout = nvme_timeout,
a0fa9647 1523 .poll = nvme_poll,
a4aea562
MB		 1524};
1525
ea191d2f
KB		 1526static void nvme_dev_remove_admin(struct nvme_dev *dev)
1527{
1c63dc66 1528 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
69d9a99c
KB		 1529 /*
1530 * If the controller was reset during removal, it's possible
1531 * user requests may be waiting on a stopped queue. Start the
1532 * queue to flush these to completion.
1533 */
c81545f9 1534 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1c63dc66 1535 blk_cleanup_queue(dev->ctrl.admin_q);
ea191d2f
KB		 1536 blk_mq_free_tag_set(&dev->admin_tagset);
1537 }
1538}
1539
a4aea562
MB		 1540static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1541{
1c63dc66 1542 if (!dev->ctrl.admin_q) {
a4aea562
MB		 1543 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1544 dev->admin_tagset.nr_hw_queues = 1;
e3e9d50c 1545
38dabe21 1546 dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH;
a4aea562 1547 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
e75ec752 1548 dev->admin_tagset.numa_node = dev_to_node(dev->dev);
a7a7cbe3 1549 dev->admin_tagset.cmd_size = nvme_pci_cmd_size(dev, false);
d3484991 1550 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED;
a4aea562
MB		 1551 dev->admin_tagset.driver_data = dev;
1552
1553 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1554 return -ENOMEM;
34b6c231 1555 dev->ctrl.admin_tagset = &dev->admin_tagset;
a4aea562 1556
1c63dc66
CH		 1557 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1558 if (IS_ERR(dev->ctrl.admin_q)) {
a4aea562
MB		 1559 blk_mq_free_tag_set(&dev->admin_tagset);
1560 return -ENOMEM;
1561 }
1c63dc66 1562 if (!blk_get_queue(dev->ctrl.admin_q)) {
ea191d2f 1563 nvme_dev_remove_admin(dev);
1c63dc66 1564 dev->ctrl.admin_q = NULL;
ea191d2f
KB		 1565 return -ENODEV;
1566 }
0fb59cbc 1567 } else
c81545f9 1568 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
a4aea562
MB		 1569
1570 return 0;
1571}
1572
97f6ef64
XY		 1573static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1574{
1575 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1576}
1577
1578static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1579{
1580 struct pci_dev *pdev = to_pci_dev(dev->dev);
1581
1582 if (size <= dev->bar_mapped_size)
1583 return 0;
1584 if (size > pci_resource_len(pdev, 0))
1585 return -ENOMEM;
1586 if (dev->bar)
1587 iounmap(dev->bar);
1588 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1589 if (!dev->bar) {
1590 dev->bar_mapped_size = 0;
1591 return -ENOMEM;
1592 }
1593 dev->bar_mapped_size = size;
1594 dev->dbs = dev->bar + NVME_REG_DBS;
1595
1596 return 0;
1597}
1598
01ad0990 1599static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
b60503ba 1600{
ba47e386 1601 int result;
b60503ba
MW		 1602 u32 aqa;
1603 struct nvme_queue *nvmeq;
1604
97f6ef64
XY		 1605 result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1606 if (result < 0)
1607 return result;
1608
8ef2074d 1609 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
20d0dfe6 1610 NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
dfbac8c7 1611
7a67cbea
CH		 1612 if (dev->subsystem &&
1613 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1614 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
dfbac8c7 1615
20d0dfe6 1616 result = nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap);
ba47e386
MW		 1617 if (result < 0)
1618 return result;
b60503ba 1619
a6ff7262 1620 result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
147b27e4
SG		 1621 if (result)
1622 return result;
b60503ba 1623
147b27e4 1624 nvmeq = &dev->queues[0];
b60503ba
MW		 1625 aqa = nvmeq->q_depth - 1;
1626 aqa |= aqa << 16;
1627
7a67cbea
CH		 1628 writel(aqa, dev->bar + NVME_REG_AQA);
1629 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1630 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
b60503ba 1631
20d0dfe6 1632 result = nvme_enable_ctrl(&dev->ctrl, dev->ctrl.cap);
025c557a 1633 if (result)
d4875622 1634 return result;
a4aea562 1635
2b25d981 1636 nvmeq->cq_vector = 0;
161b8be2 1637 nvme_init_queue(nvmeq, 0);
dca51e78 1638 result = queue_request_irq(nvmeq);
758dd7fd
JD		 1639 if (result) {
1640 nvmeq->cq_vector = -1;
d4875622 1641 return result;
758dd7fd 1642 }
025c557a 1643
b60503ba
MW		 1644 return result;
1645}
1646
749941f2 1647static int nvme_create_io_queues(struct nvme_dev *dev)
42f61420 1648{
949928c1 1649 unsigned i, max;
749941f2 1650 int ret = 0;
42f61420 1651
d858e5f0 1652 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
a6ff7262 1653 if (nvme_alloc_queue(dev, i, dev->q_depth)) {
749941f2 1654 ret = -ENOMEM;
42f61420 1655 break;
749941f2
CH		 1656 }
1657 }
42f61420 1658
d858e5f0 1659 max = min(dev->max_qid, dev->ctrl.queue_count - 1);
949928c1 1660 for (i = dev->online_queues; i <= max; i++) {
147b27e4 1661 ret = nvme_create_queue(&dev->queues[i], i);
d4875622 1662 if (ret)
42f61420 1663 break;
27e8166c 1664 }
749941f2
CH		 1665
1666 /*
1667 * Ignore failing Create SQ/CQ commands, we can continue with less
8adb8c14
MI		 1668 * than the desired amount of queues, and even a controller without
1669 * I/O queues can still be used to issue admin commands. This might
749941f2
CH		 1670 * be useful to upgrade a buggy firmware for example.
1671 */
1672 return ret >= 0 ? 0 : ret;
b60503ba
MW		 1673}
1674
202021c1
SB		 1675static ssize_t nvme_cmb_show(struct device *dev,
1676 struct device_attribute *attr,
1677 char *buf)
1678{
1679 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
1680
c965809c 1681 return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n",
202021c1
SB		 1682 ndev->cmbloc, ndev->cmbsz);
1683}
1684static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL);
1685
88de4598 1686static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
8ffaadf7 1687{
88de4598
CH		 1688 u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
1689
1690 return 1ULL << (12 + 4 * szu);
1691}
1692
1693static u32 nvme_cmb_size(struct nvme_dev *dev)
1694{
1695 return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
1696}
1697
f65efd6d 1698static void nvme_map_cmb(struct nvme_dev *dev)
8ffaadf7 1699{
88de4598 1700 u64 size, offset;
8ffaadf7
JD		 1701 resource_size_t bar_size;
1702 struct pci_dev *pdev = to_pci_dev(dev->dev);
8969f1f8 1703 int bar;
8ffaadf7 1704
7a67cbea 1705 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
f65efd6d
CH		 1706 if (!dev->cmbsz)
1707 return;
202021c1 1708 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
8ffaadf7 1709
202021c1 1710 if (!use_cmb_sqes)
f65efd6d 1711 return;
8ffaadf7 1712
88de4598
CH		 1713 size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
1714 offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
8969f1f8
CH		 1715 bar = NVME_CMB_BIR(dev->cmbloc);
1716 bar_size = pci_resource_len(pdev, bar);
8ffaadf7
JD		 1717
1718 if (offset > bar_size)
f65efd6d 1719 return;
8ffaadf7
JD		 1720
1721 /*
1722 * Controllers may support a CMB size larger than their BAR,
1723 * for example, due to being behind a bridge. Reduce the CMB to
1724 * the reported size of the BAR
1725 */
1726 if (size > bar_size - offset)
1727 size = bar_size - offset;
1728
f65efd6d
CH		 1729 dev->cmb = ioremap_wc(pci_resource_start(pdev, bar) + offset, size);
1730 if (!dev->cmb)
1731 return;
8969f1f8 1732 dev->cmb_bus_addr = pci_bus_address(pdev, bar) + offset;
8ffaadf7 1733 dev->cmb_size = size;
f65efd6d
CH		 1734
1735 if (sysfs_add_file_to_group(&dev->ctrl.device->kobj,
1736 &dev_attr_cmb.attr, NULL))
1737 dev_warn(dev->ctrl.device,
1738 "failed to add sysfs attribute for CMB\n");
8ffaadf7
JD		 1739}
1740
1741static inline void nvme_release_cmb(struct nvme_dev *dev)
1742{
1743 if (dev->cmb) {
1744 iounmap(dev->cmb);
1745 dev->cmb = NULL;
1c78f773
MG		 1746 sysfs_remove_file_from_group(&dev->ctrl.device->kobj,
1747 &dev_attr_cmb.attr, NULL);
1748 dev->cmbsz = 0;
8ffaadf7
JD		 1749 }
1750}
1751
87ad72a5
CH		 1752static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1753{
4033f35d 1754 u64 dma_addr = dev->host_mem_descs_dma;
87ad72a5 1755 struct nvme_command c;
87ad72a5
CH		 1756 int ret;
1757
87ad72a5
CH		 1758 memset(&c, 0, sizeof(c));
1759 c.features.opcode = nvme_admin_set_features;
1760 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1761 c.features.dword11 = cpu_to_le32(bits);
1762 c.features.dword12 = cpu_to_le32(dev->host_mem_size >>
1763 ilog2(dev->ctrl.page_size));
1764 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr));
1765 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr));
1766 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs);
1767
1768 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1769 if (ret) {
1770 dev_warn(dev->ctrl.device,
1771 "failed to set host mem (err %d, flags %#x).\n",
1772 ret, bits);
1773 }
87ad72a5
CH		 1774 return ret;
1775}
1776
1777static void nvme_free_host_mem(struct nvme_dev *dev)
1778{
1779 int i;
1780
1781 for (i = 0; i < dev->nr_host_mem_descs; i++) {
1782 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
1783 size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size;
1784
1785 dma_free_coherent(dev->dev, size, dev->host_mem_desc_bufs[i],
1786 le64_to_cpu(desc->addr));
1787 }
1788
1789 kfree(dev->host_mem_desc_bufs);
1790 dev->host_mem_desc_bufs = NULL;
4033f35d
CH		 1791 dma_free_coherent(dev->dev,
1792 dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
1793 dev->host_mem_descs, dev->host_mem_descs_dma);
87ad72a5 1794 dev->host_mem_descs = NULL;
7e5dd57e 1795 dev->nr_host_mem_descs = 0;
87ad72a5
CH		 1796}
1797
92dc6895
CH		 1798static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
1799 u32 chunk_size)
9d713c2b 1800{
87ad72a5 1801 struct nvme_host_mem_buf_desc *descs;
92dc6895 1802 u32 max_entries, len;
4033f35d 1803 dma_addr_t descs_dma;
2ee0e4ed 1804 int i = 0;
87ad72a5 1805 void **bufs;
6fbcde66 1806 u64 size, tmp;
87ad72a5 1807
87ad72a5
CH		 1808 tmp = (preferred + chunk_size - 1);
1809 do_div(tmp, chunk_size);
1810 max_entries = tmp;
044a9df1
CH		 1811
1812 if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
1813 max_entries = dev->ctrl.hmmaxd;
1814
4033f35d
CH		 1815 descs = dma_zalloc_coherent(dev->dev, max_entries * sizeof(*descs),
1816 &descs_dma, GFP_KERNEL);
87ad72a5
CH		 1817 if (!descs)
1818 goto out;
1819
1820 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
1821 if (!bufs)
1822 goto out_free_descs;
1823
244a8fe4 1824 for (size = 0; size < preferred && i < max_entries; size += len) {
87ad72a5
CH		 1825 dma_addr_t dma_addr;
1826
50cdb7c6 1827 len = min_t(u64, chunk_size, preferred - size);
87ad72a5
CH		 1828 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
1829 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1830 if (!bufs[i])
1831 break;
1832
1833 descs[i].addr = cpu_to_le64(dma_addr);
1834 descs[i].size = cpu_to_le32(len / dev->ctrl.page_size);
1835 i++;
1836 }
1837
92dc6895 1838 if (!size)
87ad72a5 1839 goto out_free_bufs;
87ad72a5 1840
87ad72a5
CH		 1841 dev->nr_host_mem_descs = i;
1842 dev->host_mem_size = size;
1843 dev->host_mem_descs = descs;
4033f35d 1844 dev->host_mem_descs_dma = descs_dma;
87ad72a5
CH		 1845 dev->host_mem_desc_bufs = bufs;
1846 return 0;
1847
1848out_free_bufs:
1849 while (--i >= 0) {
1850 size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size;
1851
1852 dma_free_coherent(dev->dev, size, bufs[i],
1853 le64_to_cpu(descs[i].addr));
1854 }
1855
1856 kfree(bufs);
1857out_free_descs:
4033f35d
CH		 1858 dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
1859 descs_dma);
87ad72a5 1860out:
87ad72a5
CH		 1861 dev->host_mem_descs = NULL;
1862 return -ENOMEM;
1863}
1864
92dc6895
CH		 1865static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
1866{
1867 u32 chunk_size;
1868
1869 /* start big and work our way down */
30f92d62 1870 for (chunk_size = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
044a9df1 1871 chunk_size >= max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
92dc6895
CH		 1872 chunk_size /= 2) {
1873 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
1874 if (!min || dev->host_mem_size >= min)
1875 return 0;
1876 nvme_free_host_mem(dev);
1877 }
1878 }
1879
1880 return -ENOMEM;
1881}
1882
9620cfba 1883static int nvme_setup_host_mem(struct nvme_dev *dev)
87ad72a5
CH		 1884{
1885 u64 max = (u64)max_host_mem_size_mb * SZ_1M;
1886 u64 preferred = (u64)dev->ctrl.hmpre * 4096;
1887 u64 min = (u64)dev->ctrl.hmmin * 4096;
1888 u32 enable_bits = NVME_HOST_MEM_ENABLE;
6fbcde66 1889 int ret;
87ad72a5
CH		 1890
1891 preferred = min(preferred, max);
1892 if (min > max) {
1893 dev_warn(dev->ctrl.device,
1894 "min host memory (%lld MiB) above limit (%d MiB).\n",
1895 min >> ilog2(SZ_1M), max_host_mem_size_mb);
1896 nvme_free_host_mem(dev);
9620cfba 1897 return 0;
87ad72a5
CH		 1898 }
1899
1900 /*
1901 * If we already have a buffer allocated check if we can reuse it.
1902 */
1903 if (dev->host_mem_descs) {
1904 if (dev->host_mem_size >= min)
1905 enable_bits |= NVME_HOST_MEM_RETURN;
1906 else
1907 nvme_free_host_mem(dev);
1908 }
1909
1910 if (!dev->host_mem_descs) {
92dc6895
CH		 1911 if (nvme_alloc_host_mem(dev, min, preferred)) {
1912 dev_warn(dev->ctrl.device,
1913 "failed to allocate host memory buffer.\n");
9620cfba 1914 return 0; /* controller must work without HMB */
92dc6895
CH		 1915 }
1916
1917 dev_info(dev->ctrl.device,
1918 "allocated %lld MiB host memory buffer.\n",
1919 dev->host_mem_size >> ilog2(SZ_1M));
87ad72a5
CH		 1920 }
1921
9620cfba
CH		 1922 ret = nvme_set_host_mem(dev, enable_bits);
1923 if (ret)
87ad72a5 1924 nvme_free_host_mem(dev);
9620cfba 1925 return ret;
9d713c2b
KB		 1926}
1927
8d85fce7 1928static int nvme_setup_io_queues(struct nvme_dev *dev)
b60503ba 1929{
147b27e4 1930 struct nvme_queue *adminq = &dev->queues[0];
e75ec752 1931 struct pci_dev *pdev = to_pci_dev(dev->dev);
97f6ef64
XY		 1932 int result, nr_io_queues;
1933 unsigned long size;
b60503ba 1934
22b55601
KB		 1935 struct irq_affinity affd = {
1936 .pre_vectors = 1
1937 };
1938
16ccfff2 1939 nr_io_queues = num_possible_cpus();
9a0be7ab
CH		 1940 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
1941 if (result < 0)
1b23484b 1942 return result;
9a0be7ab 1943
f5fa90dc 1944 if (nr_io_queues == 0)
a5229050 1945 return 0;
b60503ba 1946
88de4598 1947 if (dev->cmb && (dev->cmbsz & NVME_CMBSZ_SQS)) {
8ffaadf7
JD		 1948 result = nvme_cmb_qdepth(dev, nr_io_queues,
1949 sizeof(struct nvme_command));
1950 if (result > 0)
1951 dev->q_depth = result;
1952 else
1953 nvme_release_cmb(dev);
1954 }
1955
97f6ef64
XY		 1956 do {
1957 size = db_bar_size(dev, nr_io_queues);
1958 result = nvme_remap_bar(dev, size);
1959 if (!result)
1960 break;
1961 if (!--nr_io_queues)
1962 return -ENOMEM;
1963 } while (1);
1964 adminq->q_db = dev->dbs;
f1938f6e 1965
9d713c2b 1966 /* Deregister the admin queue's interrupt */
0ff199cb 1967 pci_free_irq(pdev, 0, adminq);
9d713c2b 1968
e32efbfc
JA		 1969 /*
1970 * If we enable msix early due to not intx, disable it again before
1971 * setting up the full range we need.
1972 */
dca51e78 1973 pci_free_irq_vectors(pdev);
22b55601
KB		 1974 result = pci_alloc_irq_vectors_affinity(pdev, 1, nr_io_queues + 1,
1975 PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd);
1976 if (result <= 0)
dca51e78 1977 return -EIO;
22b55601
KB		 1978 dev->num_vecs = result;
1979 dev->max_qid = max(result - 1, 1);
fa08a396 1980
063a8096
MW		 1981 /*
1982 * Should investigate if there's a performance win from allocating
1983 * more queues than interrupt vectors; it might allow the submission
1984 * path to scale better, even if the receive path is limited by the
1985 * number of interrupts.
1986 */
063a8096 1987
dca51e78 1988 result = queue_request_irq(adminq);
758dd7fd
JD		 1989 if (result) {
1990 adminq->cq_vector = -1;
d4875622 1991 return result;
758dd7fd 1992 }
749941f2 1993 return nvme_create_io_queues(dev);
b60503ba
MW		 1994}
1995
2a842aca 1996static void nvme_del_queue_end(struct request *req, blk_status_t error)
a5768aa8 1997{
db3cbfff 1998 struct nvme_queue *nvmeq = req->end_io_data;
b5875222 1999
db3cbfff
KB		 2000 blk_mq_free_request(req);
2001 complete(&nvmeq->dev->ioq_wait);
a5768aa8
KB		 2002}
2003
2a842aca 2004static void nvme_del_cq_end(struct request *req, blk_status_t error)
a5768aa8 2005{
db3cbfff 2006 struct nvme_queue *nvmeq = req->end_io_data;
5cb525c8 2007 u16 start, end;
a5768aa8 2008
db3cbfff
KB		 2009 if (!error) {
2010 unsigned long flags;
2011
2e39e0f6 2012 /*
1ab0cd69
JA		 2013 * We might be called with the AQ cq_lock held
2014 * and the I/O queue cq_lock should always
2e39e0f6
ML		 2015 * nest inside the AQ one.
2016 */
1ab0cd69 2017 spin_lock_irqsave_nested(&nvmeq->cq_lock, flags,
2e39e0f6 2018 SINGLE_DEPTH_NESTING);
5cb525c8 2019 nvme_process_cq(nvmeq, &start, &end, -1);
1ab0cd69 2020 spin_unlock_irqrestore(&nvmeq->cq_lock, flags);
5cb525c8
JA		 2021
2022 nvme_complete_cqes(nvmeq, start, end);
a5768aa8 2023 }
db3cbfff
KB		 2024
2025 nvme_del_queue_end(req, error);
a5768aa8
KB		 2026}
2027
db3cbfff 2028static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
bda4e0fb 2029{
db3cbfff
KB		 2030 struct request_queue *q = nvmeq->dev->ctrl.admin_q;
2031 struct request *req;
2032 struct nvme_command cmd;
bda4e0fb 2033
db3cbfff
KB		 2034 memset(&cmd, 0, sizeof(cmd));
2035 cmd.delete_queue.opcode = opcode;
2036 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
bda4e0fb 2037
eb71f435 2038 req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
db3cbfff
KB		 2039 if (IS_ERR(req))
2040 return PTR_ERR(req);
bda4e0fb 2041
db3cbfff
KB		 2042 req->timeout = ADMIN_TIMEOUT;
2043 req->end_io_data = nvmeq;
2044
2045 blk_execute_rq_nowait(q, NULL, req, false,
2046 opcode == nvme_admin_delete_cq ?
2047 nvme_del_cq_end : nvme_del_queue_end);
2048 return 0;
bda4e0fb
KB		 2049}
2050
ee9aebb2 2051static void nvme_disable_io_queues(struct nvme_dev *dev)
a5768aa8 2052{
ee9aebb2 2053 int pass, queues = dev->online_queues - 1;
db3cbfff
KB		 2054 unsigned long timeout;
2055 u8 opcode = nvme_admin_delete_sq;
a5768aa8 2056
db3cbfff 2057 for (pass = 0; pass < 2; pass++) {
014a0d60 2058 int sent = 0, i = queues;
db3cbfff
KB		 2059
2060 reinit_completion(&dev->ioq_wait);
2061 retry:
2062 timeout = ADMIN_TIMEOUT;
c21377f8 2063 for (; i > 0; i--, sent++)
147b27e4 2064 if (nvme_delete_queue(&dev->queues[i], opcode))
db3cbfff 2065 break;
c21377f8 2066
db3cbfff
KB		 2067 while (sent--) {
2068 timeout = wait_for_completion_io_timeout(&dev->ioq_wait, timeout);
2069 if (timeout == 0)
2070 return;
2071 if (i)
2072 goto retry;
2073 }
2074 opcode = nvme_admin_delete_cq;
2075 }
a5768aa8
KB		 2076}
2077
422ef0c7 2078/*
2b1b7e78 2079 * return error value only when tagset allocation failed
422ef0c7 2080 */
8d85fce7 2081static int nvme_dev_add(struct nvme_dev *dev)
b60503ba 2082{
2b1b7e78
JW		 2083 int ret;
2084
5bae7f73 2085 if (!dev->ctrl.tagset) {
ffe7704d
KB		 2086 dev->tagset.ops = &nvme_mq_ops;
2087 dev->tagset.nr_hw_queues = dev->online_queues - 1;
2088 dev->tagset.timeout = NVME_IO_TIMEOUT;
2089 dev->tagset.numa_node = dev_to_node(dev->dev);
2090 dev->tagset.queue_depth =
a4aea562 2091 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
a7a7cbe3
CK		 2092 dev->tagset.cmd_size = nvme_pci_cmd_size(dev, false);
2093 if ((dev->ctrl.sgls & ((1 << 0) | (1 << 1))) && sgl_threshold) {
2094 dev->tagset.cmd_size = max(dev->tagset.cmd_size,
2095 nvme_pci_cmd_size(dev, true));
2096 }
ffe7704d
KB		 2097 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2098 dev->tagset.driver_data = dev;
b60503ba 2099
2b1b7e78
JW		 2100 ret = blk_mq_alloc_tag_set(&dev->tagset);
2101 if (ret) {
2102 dev_warn(dev->ctrl.device,
2103 "IO queues tagset allocation failed %d\n", ret);
2104 return ret;
2105 }
5bae7f73 2106 dev->ctrl.tagset = &dev->tagset;
f9f38e33
HK		 2107
2108 nvme_dbbuf_set(dev);
949928c1
KB		 2109 } else {
2110 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2111
2112 /* Free previously allocated queues that are no longer usable */
2113 nvme_free_queues(dev, dev->online_queues);
ffe7704d 2114 }
949928c1 2115
e1e5e564 2116 return 0;
b60503ba
MW		 2117}
2118
b00a726a 2119static int nvme_pci_enable(struct nvme_dev *dev)
0877cb0d 2120{
b00a726a 2121 int result = -ENOMEM;
e75ec752 2122 struct pci_dev *pdev = to_pci_dev(dev->dev);
0877cb0d
KB		 2123
2124 if (pci_enable_device_mem(pdev))
2125 return result;
2126
0877cb0d 2127 pci_set_master(pdev);
0877cb0d 2128
e75ec752
CH		 2129 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) &&
2130 dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32)))
052d0efa 2131 goto disable;
0877cb0d 2132
7a67cbea 2133 if (readl(dev->bar + NVME_REG_CSTS) == -1) {
0e53d180 2134 result = -ENODEV;
b00a726a 2135 goto disable;
0e53d180 2136 }
e32efbfc
JA		 2137
2138 /*
a5229050
KB		 2139 * Some devices and/or platforms don't advertise or work with INTx
2140 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2141 * adjust this later.
e32efbfc 2142 */
dca51e78
CH		 2143 result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
2144 if (result < 0)
2145 return result;
e32efbfc 2146
20d0dfe6 2147 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
7a67cbea 2148
20d0dfe6 2149 dev->q_depth = min_t(int, NVME_CAP_MQES(dev->ctrl.cap) + 1,
b27c1e68 2150 io_queue_depth);
20d0dfe6 2151 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
7a67cbea 2152 dev->dbs = dev->bar + 4096;
1f390c1f
SG		 2153
2154 /*
2155 * Temporary fix for the Apple controller found in the MacBook8,1 and
2156 * some MacBook7,1 to avoid controller resets and data loss.
2157 */
2158 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
2159 dev->q_depth = 2;
9bdcfb10
CH		 2160 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
2161 "set queue depth=%u to work around controller resets\n",
1f390c1f 2162 dev->q_depth);
d554b5e1
MP		 2163 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2164 (pdev->device == 0xa821 || pdev->device == 0xa822) &&
20d0dfe6 2165 NVME_CAP_MQES(dev->ctrl.cap) == 0) {
d554b5e1
MP		 2166 dev->q_depth = 64;
2167 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2168 "set queue depth=%u\n", dev->q_depth);
1f390c1f
SG		 2169 }
2170
f65efd6d 2171 nvme_map_cmb(dev);
202021c1 2172
a0a3408e
KB		 2173 pci_enable_pcie_error_reporting(pdev);
2174 pci_save_state(pdev);
0877cb0d
KB		 2175 return 0;
2176
2177 disable:
0877cb0d
KB		 2178 pci_disable_device(pdev);
2179 return result;
2180}
2181
2182static void nvme_dev_unmap(struct nvme_dev *dev)
b00a726a
KB		 2183{
2184 if (dev->bar)
2185 iounmap(dev->bar);
a1f447b3 2186 pci_release_mem_regions(to_pci_dev(dev->dev));
b00a726a
KB		 2187}
2188
2189static void nvme_pci_disable(struct nvme_dev *dev)
0877cb0d 2190{
e75ec752
CH		 2191 struct pci_dev *pdev = to_pci_dev(dev->dev);
2192
f63572df 2193 nvme_release_cmb(dev);
dca51e78 2194 pci_free_irq_vectors(pdev);
0877cb0d 2195
a0a3408e
KB		 2196 if (pci_is_enabled(pdev)) {
2197 pci_disable_pcie_error_reporting(pdev);
e75ec752 2198 pci_disable_device(pdev);
4d115420 2199 }
4d115420
KB		 2200}
2201
a5cdb68c 2202static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
b60503ba 2203{
ee9aebb2 2204 int i;
302ad8cc
KB		 2205 bool dead = true;
2206 struct pci_dev *pdev = to_pci_dev(dev->dev);
22404274 2207
77bf25ea 2208 mutex_lock(&dev->shutdown_lock);
302ad8cc
KB		 2209 if (pci_is_enabled(pdev)) {
2210 u32 csts = readl(dev->bar + NVME_REG_CSTS);
2211
ebef7368
KB		 2212 if (dev->ctrl.state == NVME_CTRL_LIVE ||
2213 dev->ctrl.state == NVME_CTRL_RESETTING)
302ad8cc
KB		 2214 nvme_start_freeze(&dev->ctrl);
2215 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
2216 pdev->error_state != pci_channel_io_normal);
c9d3bf88 2217 }
c21377f8 2218
302ad8cc
KB		 2219 /*
2220 * Give the controller a chance to complete all entered requests if
2221 * doing a safe shutdown.
2222 */
87ad72a5
CH		 2223 if (!dead) {
2224 if (shutdown)
2225 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
9a915a5b
JW		 2226 }
2227
2228 nvme_stop_queues(&dev->ctrl);
87ad72a5 2229
64ee0ac0 2230 if (!dead && dev->ctrl.queue_count > 0) {
87ad72a5
CH		 2231 /*
2232 * If the controller is still alive tell it to stop using the
2233 * host memory buffer. In theory the shutdown / reset should
2234 * make sure that it doesn't access the host memoery anymore,
2235 * but I'd rather be safe than sorry..
2236 */
2237 if (dev->host_mem_descs)
2238 nvme_set_host_mem(dev, 0);
ee9aebb2 2239 nvme_disable_io_queues(dev);
a5cdb68c 2240 nvme_disable_admin_queue(dev, shutdown);
4d115420 2241 }
ee9aebb2
KB		 2242 for (i = dev->ctrl.queue_count - 1; i >= 0; i--)
2243 nvme_suspend_queue(&dev->queues[i]);
2244
b00a726a 2245 nvme_pci_disable(dev);
07836e65 2246
e1958e65
ML		 2247 blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
2248 blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
302ad8cc
KB		 2249
2250 /*
2251 * The driver will not be starting up queues again if shutting down so
2252 * must flush all entered requests to their failed completion to avoid
2253 * deadlocking blk-mq hot-cpu notifier.
2254 */
2255 if (shutdown)
2256 nvme_start_queues(&dev->ctrl);
77bf25ea 2257 mutex_unlock(&dev->shutdown_lock);
b60503ba
MW		 2258}
2259
091b6092
MW		 2260static int nvme_setup_prp_pools(struct nvme_dev *dev)
2261{
e75ec752 2262 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
091b6092
MW		 2263 PAGE_SIZE, PAGE_SIZE, 0);
2264 if (!dev->prp_page_pool)
2265 return -ENOMEM;
2266
99802a7a 2267 /* Optimisation for I/Os between 4k and 128k */
e75ec752 2268 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
99802a7a
MW		 2269 256, 256, 0);
2270 if (!dev->prp_small_pool) {
2271 dma_pool_destroy(dev->prp_page_pool);
2272 return -ENOMEM;
2273 }
091b6092
MW		 2274 return 0;
2275}
2276
2277static void nvme_release_prp_pools(struct nvme_dev *dev)
2278{
2279 dma_pool_destroy(dev->prp_page_pool);
99802a7a 2280 dma_pool_destroy(dev->prp_small_pool);
091b6092
MW		 2281}
2282
1673f1f0 2283static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
5e82e952 2284{
1673f1f0 2285 struct nvme_dev *dev = to_nvme_dev(ctrl);
9ac27090 2286
f9f38e33 2287 nvme_dbbuf_dma_free(dev);
e75ec752 2288 put_device(dev->dev);
4af0e21c
KB		 2289 if (dev->tagset.tags)
2290 blk_mq_free_tag_set(&dev->tagset);
1c63dc66
CH		 2291 if (dev->ctrl.admin_q)
2292 blk_put_queue(dev->ctrl.admin_q);
5e82e952 2293 kfree(dev->queues);
e286bcfc 2294 free_opal_dev(dev->ctrl.opal_dev);
5e82e952
KB		 2295 kfree(dev);
2296}
2297
f58944e2
KB		 2298static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status)
2299{
237045fc 2300 dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status);
f58944e2 2301
d22524a4 2302 nvme_get_ctrl(&dev->ctrl);
69d9a99c 2303 nvme_dev_disable(dev, false);
03e0f3a6 2304 if (!queue_work(nvme_wq, &dev->remove_work))
f58944e2
KB		 2305 nvme_put_ctrl(&dev->ctrl);
2306}
2307
fd634f41 2308static void nvme_reset_work(struct work_struct *work)
5e82e952 2309{
d86c4d8e
CH		 2310 struct nvme_dev *dev =
2311 container_of(work, struct nvme_dev, ctrl.reset_work);
a98e58e5 2312 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
f58944e2 2313 int result = -ENODEV;
2b1b7e78 2314 enum nvme_ctrl_state new_state = NVME_CTRL_LIVE;
5e82e952 2315
82b057ca 2316 if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING))
fd634f41 2317 goto out;
5e82e952 2318
fd634f41
CH		 2319 /*
2320 * If we're called to reset a live controller first shut it down before
2321 * moving on.
2322 */
b00a726a 2323 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
a5cdb68c 2324 nvme_dev_disable(dev, false);
5e82e952 2325
ad70062c 2326 /*
ad6a0a52 2327 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
ad70062c
JW		 2328 * initializing procedure here.
2329 */
ad6a0a52 2330 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
ad70062c 2331 dev_warn(dev->ctrl.device,
ad6a0a52 2332 "failed to mark controller CONNECTING\n");
ad70062c
JW		 2333 goto out;
2334 }
2335
b00a726a 2336 result = nvme_pci_enable(dev);
f0b50732 2337 if (result)
3cf519b5 2338 goto out;
f0b50732 2339
01ad0990 2340 result = nvme_pci_configure_admin_queue(dev);
f0b50732 2341 if (result)
f58944e2 2342 goto out;
f0b50732 2343
0fb59cbc
KB		 2344 result = nvme_alloc_admin_tags(dev);
2345 if (result)
f58944e2 2346 goto out;
b9afca3e 2347
ce4541f4
CH		 2348 result = nvme_init_identify(&dev->ctrl);
2349 if (result)
f58944e2 2350 goto out;
ce4541f4 2351
e286bcfc
SB		 2352 if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
2353 if (!dev->ctrl.opal_dev)
2354 dev->ctrl.opal_dev =
2355 init_opal_dev(&dev->ctrl, &nvme_sec_submit);
2356 else if (was_suspend)
2357 opal_unlock_from_suspend(dev->ctrl.opal_dev);
2358 } else {
2359 free_opal_dev(dev->ctrl.opal_dev);
2360 dev->ctrl.opal_dev = NULL;
4f1244c8 2361 }
a98e58e5 2362
f9f38e33
HK		 2363 if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) {
2364 result = nvme_dbbuf_dma_alloc(dev);
2365 if (result)
2366 dev_warn(dev->dev,
2367 "unable to allocate dma for dbbuf\n");
2368 }
2369
9620cfba
CH		 2370 if (dev->ctrl.hmpre) {
2371 result = nvme_setup_host_mem(dev);
2372 if (result < 0)
2373 goto out;
2374 }
87ad72a5 2375
f0b50732 2376 result = nvme_setup_io_queues(dev);
badc34d4 2377 if (result)
f58944e2 2378 goto out;
f0b50732 2379
2659e57b
CH		 2380 /*
2381 * Keep the controller around but remove all namespaces if we don't have
2382 * any working I/O queue.
2383 */
3cf519b5 2384 if (dev->online_queues < 2) {
1b3c47c1 2385 dev_warn(dev->ctrl.device, "IO queues not created\n");
3b24774e 2386 nvme_kill_queues(&dev->ctrl);
5bae7f73 2387 nvme_remove_namespaces(&dev->ctrl);
2b1b7e78 2388 new_state = NVME_CTRL_ADMIN_ONLY;
3cf519b5 2389 } else {
25646264 2390 nvme_start_queues(&dev->ctrl);
302ad8cc 2391 nvme_wait_freeze(&dev->ctrl);
2b1b7e78
JW		 2392 /* hit this only when allocate tagset fails */
2393 if (nvme_dev_add(dev))
2394 new_state = NVME_CTRL_ADMIN_ONLY;
302ad8cc 2395 nvme_unfreeze(&dev->ctrl);
3cf519b5
CH		 2396 }
2397
2b1b7e78
JW		 2398 /*
2399 * If only admin queue live, keep it to do further investigation or
2400 * recovery.
2401 */
2402 if (!nvme_change_ctrl_state(&dev->ctrl, new_state)) {
2403 dev_warn(dev->ctrl.device,
2404 "failed to mark controller state %d\n", new_state);
bb8d261e
CH		 2405 goto out;
2406 }
92911a55 2407
d09f2b45 2408 nvme_start_ctrl(&dev->ctrl);
3cf519b5 2409 return;
f0b50732 2410
3cf519b5 2411 out:
f58944e2 2412 nvme_remove_dead_ctrl(dev, result);
f0b50732
KB		 2413}
2414
5c8809e6 2415static void nvme_remove_dead_ctrl_work(struct work_struct *work)
9a6b9458 2416{
5c8809e6 2417 struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
e75ec752 2418 struct pci_dev *pdev = to_pci_dev(dev->dev);
9a6b9458 2419
69d9a99c 2420 nvme_kill_queues(&dev->ctrl);
9a6b9458 2421 if (pci_get_drvdata(pdev))
921920ab 2422 device_release_driver(&pdev->dev);
1673f1f0 2423 nvme_put_ctrl(&dev->ctrl);
9a6b9458
KB		 2424}
2425
1c63dc66 2426static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
9ca97374 2427{
1c63dc66 2428 *val = readl(to_nvme_dev(ctrl)->bar + off);
90667892 2429 return 0;
9ca97374
TH		 2430}
2431
5fd4ce1b 2432static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
4cc06521 2433{
5fd4ce1b
CH		 2434 writel(val, to_nvme_dev(ctrl)->bar + off);
2435 return 0;
2436}
4cc06521 2437
7fd8930f
CH		 2438static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2439{
2440 *val = readq(to_nvme_dev(ctrl)->bar + off);
2441 return 0;
4cc06521
KB		 2442}
2443
97c12223
KB		 2444static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
2445{
2446 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2447
2448 return snprintf(buf, size, "%s", dev_name(&pdev->dev));
2449}
2450
1c63dc66 2451static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
1a353d85 2452 .name = "pcie",
e439bb12 2453 .module = THIS_MODULE,
c81bfba9 2454 .flags = NVME_F_METADATA_SUPPORTED,
1c63dc66 2455 .reg_read32 = nvme_pci_reg_read32,
5fd4ce1b 2456 .reg_write32 = nvme_pci_reg_write32,
7fd8930f 2457 .reg_read64 = nvme_pci_reg_read64,
1673f1f0 2458 .free_ctrl = nvme_pci_free_ctrl,
f866fc42 2459 .submit_async_event = nvme_pci_submit_async_event,
97c12223 2460 .get_address = nvme_pci_get_address,
1c63dc66 2461};
4cc06521 2462
b00a726a
KB		 2463static int nvme_dev_map(struct nvme_dev *dev)
2464{
b00a726a
KB		 2465 struct pci_dev *pdev = to_pci_dev(dev->dev);
2466
a1f447b3 2467 if (pci_request_mem_regions(pdev, "nvme"))
b00a726a
KB		 2468 return -ENODEV;
2469
97f6ef64 2470 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
b00a726a
KB		 2471 goto release;
2472
9fa196e7 2473 return 0;
b00a726a 2474 release:
9fa196e7
MG		 2475 pci_release_mem_regions(pdev);
2476 return -ENODEV;
b00a726a
KB		 2477}
2478
8427bbc2 2479static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
ff5350a8
AL		 2480{
2481 if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
2482 /*
2483 * Several Samsung devices seem to drop off the PCIe bus
2484 * randomly when APST is on and uses the deepest sleep state.
2485 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2486 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2487 * 950 PRO 256GB", but it seems to be restricted to two Dell
2488 * laptops.
2489 */
2490 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
2491 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
2492 dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
2493 return NVME_QUIRK_NO_DEEPEST_PS;
8427bbc2
KHF		 2494 } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
2495 /*
2496 * Samsung SSD 960 EVO drops off the PCIe bus after system
467c77d4
JJ		 2497 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
2498 * within few minutes after bootup on a Coffee Lake board -
2499 * ASUS PRIME Z370-A
8427bbc2
KHF		 2500 */
2501 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
467c77d4
JJ		 2502 (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") ||
2503 dmi_match(DMI_BOARD_NAME, "PRIME Z370-A")))
8427bbc2 2504 return NVME_QUIRK_NO_APST;
ff5350a8
AL		 2505 }
2506
2507 return 0;
2508}
2509
18119775
KB		 2510static void nvme_async_probe(void *data, async_cookie_t cookie)
2511{
2512 struct nvme_dev *dev = data;
80f513b5 2513
18119775
KB		 2514 nvme_reset_ctrl_sync(&dev->ctrl);
2515 flush_work(&dev->ctrl.scan_work);
80f513b5 2516 nvme_put_ctrl(&dev->ctrl);
18119775
KB		 2517}
2518
8d85fce7 2519static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
b60503ba 2520{
a4aea562 2521 int node, result = -ENOMEM;
b60503ba 2522 struct nvme_dev *dev;
ff5350a8 2523 unsigned long quirks = id->driver_data;
b60503ba 2524
a4aea562
MB		 2525 node = dev_to_node(&pdev->dev);
2526 if (node == NUMA_NO_NODE)
2fa84351 2527 set_dev_node(&pdev->dev, first_memory_node);
a4aea562
MB		 2528
2529 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
b60503ba
MW		 2530 if (!dev)
2531 return -ENOMEM;
147b27e4
SG		 2532
2533 dev->queues = kcalloc_node(num_possible_cpus() + 1,
2534 sizeof(struct nvme_queue), GFP_KERNEL, node);
b60503ba
MW		 2535 if (!dev->queues)
2536 goto free;
2537
e75ec752 2538 dev->dev = get_device(&pdev->dev);
9a6b9458 2539 pci_set_drvdata(pdev, dev);
1c63dc66 2540
b00a726a
KB		 2541 result = nvme_dev_map(dev);
2542 if (result)
b00c9b7a 2543 goto put_pci;
b00a726a 2544
d86c4d8e 2545 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
5c8809e6 2546 INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
77bf25ea 2547 mutex_init(&dev->shutdown_lock);
db3cbfff 2548 init_completion(&dev->ioq_wait);
b60503ba 2549
091b6092
MW		 2550 result = nvme_setup_prp_pools(dev);
2551 if (result)
b00c9b7a 2552 goto unmap;
4cc06521 2553
8427bbc2 2554 quirks |= check_vendor_combination_bug(pdev);
ff5350a8 2555
f3ca80fc 2556 result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
ff5350a8 2557 quirks);
4cc06521 2558 if (result)
2e1d8448 2559 goto release_pools;
740216fc 2560
1b3c47c1
SG		 2561 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
2562
80f513b5 2563 nvme_get_ctrl(&dev->ctrl);
18119775 2564 async_schedule(nvme_async_probe, dev);
4caff8fc 2565
b60503ba
MW		 2566 return 0;
2567
0877cb0d 2568 release_pools:
091b6092 2569 nvme_release_prp_pools(dev);
b00c9b7a
CJ		 2570 unmap:
2571 nvme_dev_unmap(dev);
a96d4f5c 2572 put_pci:
e75ec752 2573 put_device(dev->dev);
b60503ba
MW		 2574 free:
2575 kfree(dev->queues);
b60503ba
MW		 2576 kfree(dev);
2577 return result;
2578}
2579
775755ed 2580static void nvme_reset_prepare(struct pci_dev *pdev)
f0d54a54 2581{
a6739479 2582 struct nvme_dev *dev = pci_get_drvdata(pdev);
f263fbb8 2583 nvme_dev_disable(dev, false);
775755ed 2584}
f0d54a54 2585
775755ed
CH		 2586static void nvme_reset_done(struct pci_dev *pdev)
2587{
f263fbb8 2588 struct nvme_dev *dev = pci_get_drvdata(pdev);
79c48ccf 2589 nvme_reset_ctrl_sync(&dev->ctrl);
f0d54a54
KB		 2590}
2591
09ece142
KB		 2592static void nvme_shutdown(struct pci_dev *pdev)
2593{
2594 struct nvme_dev *dev = pci_get_drvdata(pdev);
a5cdb68c 2595 nvme_dev_disable(dev, true);
09ece142
KB		 2596}
2597
f58944e2
KB		 2598/*
2599 * The driver's remove may be called on a device in a partially initialized
2600 * state. This function must not have any dependencies on the device state in
2601 * order to proceed.
2602 */
8d85fce7 2603static void nvme_remove(struct pci_dev *pdev)
b60503ba
MW		 2604{
2605 struct nvme_dev *dev = pci_get_drvdata(pdev);
9a6b9458 2606
bb8d261e
CH		 2607 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
2608
d86c4d8e 2609 cancel_work_sync(&dev->ctrl.reset_work);
9a6b9458 2610 pci_set_drvdata(pdev, NULL);
0ff9d4e1 2611
6db28eda 2612 if (!pci_device_is_present(pdev)) {
0ff9d4e1 2613 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
6db28eda
KB		 2614 nvme_dev_disable(dev, false);
2615 }
0ff9d4e1 2616
d86c4d8e 2617 flush_work(&dev->ctrl.reset_work);
d09f2b45
SG		 2618 nvme_stop_ctrl(&dev->ctrl);
2619 nvme_remove_namespaces(&dev->ctrl);
a5cdb68c 2620 nvme_dev_disable(dev, true);
87ad72a5 2621 nvme_free_host_mem(dev);
a4aea562 2622 nvme_dev_remove_admin(dev);
a1a5ef99 2623 nvme_free_queues(dev, 0);
d09f2b45 2624 nvme_uninit_ctrl(&dev->ctrl);
9a6b9458 2625 nvme_release_prp_pools(dev);
b00a726a 2626 nvme_dev_unmap(dev);
1673f1f0 2627 nvme_put_ctrl(&dev->ctrl);
b60503ba
MW		 2628}
2629
13880f5b
KB		 2630static int nvme_pci_sriov_configure(struct pci_dev *pdev, int numvfs)
2631{
2632 int ret = 0;
2633
2634 if (numvfs == 0) {
2635 if (pci_vfs_assigned(pdev)) {
2636 dev_warn(&pdev->dev,
2637 "Cannot disable SR-IOV VFs while assigned\n");
2638 return -EPERM;
2639 }
2640 pci_disable_sriov(pdev);
2641 return 0;
2642 }
2643
2644 ret = pci_enable_sriov(pdev, numvfs);
2645 return ret ? ret : numvfs;
2646}
2647
671a6018 2648#ifdef CONFIG_PM_SLEEP
cd638946
KB		 2649static int nvme_suspend(struct device *dev)
2650{
2651 struct pci_dev *pdev = to_pci_dev(dev);
2652 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2653
a5cdb68c 2654 nvme_dev_disable(ndev, true);
cd638946
KB		 2655 return 0;
2656}
2657
2658static int nvme_resume(struct device *dev)
2659{
2660 struct pci_dev *pdev = to_pci_dev(dev);
2661 struct nvme_dev *ndev = pci_get_drvdata(pdev);
cd638946 2662
d86c4d8e 2663 nvme_reset_ctrl(&ndev->ctrl);
9a6b9458 2664 return 0;
cd638946 2665}
671a6018 2666#endif
cd638946
KB		 2667
2668static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
b60503ba 2669
a0a3408e
KB		 2670static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
2671 pci_channel_state_t state)
2672{
2673 struct nvme_dev *dev = pci_get_drvdata(pdev);
2674
2675 /*
2676 * A frozen channel requires a reset. When detected, this method will
2677 * shutdown the controller to quiesce. The controller will be restarted
2678 * after the slot reset through driver's slot_reset callback.
2679 */
a0a3408e
KB		 2680 switch (state) {
2681 case pci_channel_io_normal:
2682 return PCI_ERS_RESULT_CAN_RECOVER;
2683 case pci_channel_io_frozen:
d011fb31
KB		 2684 dev_warn(dev->ctrl.device,
2685 "frozen state error detected, reset controller\n");
a5cdb68c 2686 nvme_dev_disable(dev, false);
a0a3408e
KB		 2687 return PCI_ERS_RESULT_NEED_RESET;
2688 case pci_channel_io_perm_failure:
d011fb31
KB		 2689 dev_warn(dev->ctrl.device,
2690 "failure state error detected, request disconnect\n");
a0a3408e
KB		 2691 return PCI_ERS_RESULT_DISCONNECT;
2692 }
2693 return PCI_ERS_RESULT_NEED_RESET;
2694}
2695
2696static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
2697{
2698 struct nvme_dev *dev = pci_get_drvdata(pdev);
2699
1b3c47c1 2700 dev_info(dev->ctrl.device, "restart after slot reset\n");
a0a3408e 2701 pci_restore_state(pdev);
cc1d5e74
KB		 2702 nvme_reset_ctrl_sync(&dev->ctrl);
2703
2704 switch (dev->ctrl.state) {
2705 case NVME_CTRL_LIVE:
2706 case NVME_CTRL_ADMIN_ONLY:
2707 return PCI_ERS_RESULT_RECOVERED;
2708 default:
2709 return PCI_ERS_RESULT_DISCONNECT;
2710 }
a0a3408e
KB		 2711}
2712
2713static void nvme_error_resume(struct pci_dev *pdev)
2714{
2715 pci_cleanup_aer_uncorrect_error_status(pdev);
2716}
2717
1d352035 2718static const struct pci_error_handlers nvme_err_handler = {
b60503ba 2719 .error_detected = nvme_error_detected,
b60503ba
MW		 2720 .slot_reset = nvme_slot_reset,
2721 .resume = nvme_error_resume,
775755ed
CH		 2722 .reset_prepare = nvme_reset_prepare,
2723 .reset_done = nvme_reset_done,
b60503ba
MW		 2724};
2725
6eb0d698 2726static const struct pci_device_id nvme_id_table[] = {
106198ed 2727 { PCI_VDEVICE(INTEL, 0x0953),
08095e70 2728 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 2729 NVME_QUIRK_DEALLOCATE_ZEROES, },
99466e70
KB		 2730 { PCI_VDEVICE(INTEL, 0x0a53),
2731 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 2732 NVME_QUIRK_DEALLOCATE_ZEROES, },
99466e70
KB		 2733 { PCI_VDEVICE(INTEL, 0x0a54),
2734 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 2735 NVME_QUIRK_DEALLOCATE_ZEROES, },
f99cb7af
DWF		 2736 { PCI_VDEVICE(INTEL, 0x0a55),
2737 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2738 NVME_QUIRK_DEALLOCATE_ZEROES, },
50af47d0
AL		 2739 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */
2740 .driver_data = NVME_QUIRK_NO_DEEPEST_PS },
540c801c
KB		 2741 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */
2742 .driver_data = NVME_QUIRK_IDENTIFY_CNS, },
0302ae60
MP		 2743 { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */
2744 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
54adc010
GP		 2745 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
2746 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
8c97eecc
JL		 2747 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */
2748 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
015282c9
WW		 2749 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
2750 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
d554b5e1
MP		 2751 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */
2752 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2753 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */
2754 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
608cc4b1
CH		 2755 { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */
2756 .driver_data = NVME_QUIRK_LIGHTNVM, },
2757 { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */
2758 .driver_data = NVME_QUIRK_LIGHTNVM, },
ea48e877
WX		 2759 { PCI_DEVICE(0x1d1d, 0x2601), /* CNEX Granby */
2760 .driver_data = NVME_QUIRK_LIGHTNVM, },
b60503ba 2761 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
c74dc780 2762 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) },
124298bd 2763 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
b60503ba
MW		 2764 { 0, }
2765};
2766MODULE_DEVICE_TABLE(pci, nvme_id_table);
2767
2768static struct pci_driver nvme_driver = {
2769 .name = "nvme",
2770 .id_table = nvme_id_table,
2771 .probe = nvme_probe,
8d85fce7 2772 .remove = nvme_remove,
09ece142 2773 .shutdown = nvme_shutdown,
cd638946
KB		 2774 .driver = {
2775 .pm = &nvme_dev_pm_ops,
2776 },
13880f5b 2777 .sriov_configure = nvme_pci_sriov_configure,
b60503ba
MW		 2778 .err_handler = &nvme_err_handler,
2779};
2780
2781static int __init nvme_init(void)
2782{
9a6327d2 2783 return pci_register_driver(&nvme_driver);
b60503ba
MW		 2784}
2785
2786static void __exit nvme_exit(void)
2787{
2788 pci_unregister_driver(&nvme_driver);
03e0f3a6 2789 flush_workqueue(nvme_wq);
21bd78bc 2790 _nvme_check_size();
b60503ba
MW		 2791}
2792
2793MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2794MODULE_LICENSE("GPL");
c78b4713 2795MODULE_VERSION("1.0");
b60503ba
MW		 2796module_init(nvme_init);
2797module_exit(nvme_exit);
Linux 6.x block layer and io_uring tree(s)