nvme: lock NS list changes while handling command effects
[linux-2.6-block.git] / drivers / nvme / host / pci.c
CommitLineData
b60503ba
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1/*
2 * NVM Express device driver
6eb0d698 3 * Copyright (c) 2011-2014, Intel Corporation.
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4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
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13 */
14
a0a3408e 15#include <linux/aer.h>
18119775 16#include <linux/async.h>
b60503ba 17#include <linux/blkdev.h>
a4aea562 18#include <linux/blk-mq.h>
dca51e78 19#include <linux/blk-mq-pci.h>
ff5350a8 20#include <linux/dmi.h>
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21#include <linux/init.h>
22#include <linux/interrupt.h>
23#include <linux/io.h>
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24#include <linux/mm.h>
25#include <linux/module.h>
77bf25ea 26#include <linux/mutex.h>
d0877473 27#include <linux/once.h>
b60503ba 28#include <linux/pci.h>
e1e5e564 29#include <linux/t10-pi.h>
b60503ba 30#include <linux/types.h>
2f8e2c87 31#include <linux/io-64-nonatomic-lo-hi.h>
a98e58e5 32#include <linux/sed-opal.h>
0f238ff5 33#include <linux/pci-p2pdma.h>
797a796a 34
604c01d5 35#include "trace.h"
f11bb3e2
CH
36#include "nvme.h"
37
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38#define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
39#define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
c965809c 40
a7a7cbe3 41#define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc))
9d43cf64 42
943e942e
JA
43/*
44 * These can be higher, but we need to ensure that any command doesn't
45 * require an sg allocation that needs more than a page of data.
46 */
47#define NVME_MAX_KB_SZ 4096
48#define NVME_MAX_SEGS 127
49
58ffacb5
MW
50static int use_threaded_interrupts;
51module_param(use_threaded_interrupts, int, 0);
52
8ffaadf7 53static bool use_cmb_sqes = true;
69f4eb9f 54module_param(use_cmb_sqes, bool, 0444);
8ffaadf7
JD
55MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
56
87ad72a5
CH
57static unsigned int max_host_mem_size_mb = 128;
58module_param(max_host_mem_size_mb, uint, 0444);
59MODULE_PARM_DESC(max_host_mem_size_mb,
60 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
1fa6aead 61
a7a7cbe3
CK
62static unsigned int sgl_threshold = SZ_32K;
63module_param(sgl_threshold, uint, 0644);
64MODULE_PARM_DESC(sgl_threshold,
65 "Use SGLs when average request segment size is larger or equal to "
66 "this size. Use 0 to disable SGLs.");
67
b27c1e68 68static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
69static const struct kernel_param_ops io_queue_depth_ops = {
70 .set = io_queue_depth_set,
71 .get = param_get_int,
72};
73
74static int io_queue_depth = 1024;
75module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
76MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2");
77
3b6592f7
JA
78static int queue_count_set(const char *val, const struct kernel_param *kp);
79static const struct kernel_param_ops queue_count_ops = {
80 .set = queue_count_set,
81 .get = param_get_int,
82};
83
84static int write_queues;
85module_param_cb(write_queues, &queue_count_ops, &write_queues, 0644);
86MODULE_PARM_DESC(write_queues,
87 "Number of queues to use for writes. If not set, reads and writes "
88 "will share a queue set.");
89
a4668d9b 90static int poll_queues = 0;
4b04cc6a
JA
91module_param_cb(poll_queues, &queue_count_ops, &poll_queues, 0644);
92MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO.");
93
1c63dc66
CH
94struct nvme_dev;
95struct nvme_queue;
b3fffdef 96
a5cdb68c 97static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
8fae268b 98static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode);
d4b4ff8e 99
1c63dc66
CH
100/*
101 * Represents an NVM Express device. Each nvme_dev is a PCI function.
102 */
103struct nvme_dev {
147b27e4 104 struct nvme_queue *queues;
1c63dc66
CH
105 struct blk_mq_tag_set tagset;
106 struct blk_mq_tag_set admin_tagset;
107 u32 __iomem *dbs;
108 struct device *dev;
109 struct dma_pool *prp_page_pool;
110 struct dma_pool *prp_small_pool;
1c63dc66
CH
111 unsigned online_queues;
112 unsigned max_qid;
e20ba6e1 113 unsigned io_queues[HCTX_MAX_TYPES];
22b55601 114 unsigned int num_vecs;
1c63dc66
CH
115 int q_depth;
116 u32 db_stride;
1c63dc66 117 void __iomem *bar;
97f6ef64 118 unsigned long bar_mapped_size;
5c8809e6 119 struct work_struct remove_work;
77bf25ea 120 struct mutex shutdown_lock;
1c63dc66 121 bool subsystem;
1c63dc66 122 u64 cmb_size;
0f238ff5 123 bool cmb_use_sqes;
1c63dc66 124 u32 cmbsz;
202021c1 125 u32 cmbloc;
1c63dc66 126 struct nvme_ctrl ctrl;
87ad72a5 127
943e942e
JA
128 mempool_t *iod_mempool;
129
87ad72a5 130 /* shadow doorbell buffer support: */
f9f38e33
HK
131 u32 *dbbuf_dbs;
132 dma_addr_t dbbuf_dbs_dma_addr;
133 u32 *dbbuf_eis;
134 dma_addr_t dbbuf_eis_dma_addr;
87ad72a5
CH
135
136 /* host memory buffer support: */
137 u64 host_mem_size;
138 u32 nr_host_mem_descs;
4033f35d 139 dma_addr_t host_mem_descs_dma;
87ad72a5
CH
140 struct nvme_host_mem_buf_desc *host_mem_descs;
141 void **host_mem_desc_bufs;
4d115420 142};
1fa6aead 143
b27c1e68 144static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
145{
146 int n = 0, ret;
147
148 ret = kstrtoint(val, 10, &n);
149 if (ret != 0 || n < 2)
150 return -EINVAL;
151
152 return param_set_int(val, kp);
153}
154
3b6592f7
JA
155static int queue_count_set(const char *val, const struct kernel_param *kp)
156{
157 int n = 0, ret;
158
159 ret = kstrtoint(val, 10, &n);
160 if (n > num_possible_cpus())
161 n = num_possible_cpus();
162
163 return param_set_int(val, kp);
164}
165
f9f38e33
HK
166static inline unsigned int sq_idx(unsigned int qid, u32 stride)
167{
168 return qid * 2 * stride;
169}
170
171static inline unsigned int cq_idx(unsigned int qid, u32 stride)
172{
173 return (qid * 2 + 1) * stride;
174}
175
1c63dc66
CH
176static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
177{
178 return container_of(ctrl, struct nvme_dev, ctrl);
179}
180
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181/*
182 * An NVM Express queue. Each device has at least two (one for admin
183 * commands and one for I/O commands).
184 */
185struct nvme_queue {
186 struct device *q_dmadev;
091b6092 187 struct nvme_dev *dev;
1ab0cd69 188 spinlock_t sq_lock;
b60503ba 189 struct nvme_command *sq_cmds;
3a7afd8e
CH
190 /* only used for poll queues: */
191 spinlock_t cq_poll_lock ____cacheline_aligned_in_smp;
b60503ba 192 volatile struct nvme_completion *cqes;
42483228 193 struct blk_mq_tags **tags;
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194 dma_addr_t sq_dma_addr;
195 dma_addr_t cq_dma_addr;
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196 u32 __iomem *q_db;
197 u16 q_depth;
6222d172 198 s16 cq_vector;
b60503ba 199 u16 sq_tail;
04f3eafd 200 u16 last_sq_tail;
b60503ba 201 u16 cq_head;
68fa9dbe 202 u16 last_cq_head;
c30341dc 203 u16 qid;
e9539f47 204 u8 cq_phase;
4e224106
CH
205 unsigned long flags;
206#define NVMEQ_ENABLED 0
63223078 207#define NVMEQ_SQ_CMB 1
d1ed6aa1 208#define NVMEQ_DELETE_ERROR 2
f9f38e33
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209 u32 *dbbuf_sq_db;
210 u32 *dbbuf_cq_db;
211 u32 *dbbuf_sq_ei;
212 u32 *dbbuf_cq_ei;
d1ed6aa1 213 struct completion delete_done;
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214};
215
71bd150c
CH
216/*
217 * The nvme_iod describes the data in an I/O, including the list of PRP
218 * entries. You can't see it in this data structure because C doesn't let
f4800d6d 219 * me express that. Use nvme_init_iod to ensure there's enough space
71bd150c
CH
220 * allocated to store the PRP list.
221 */
222struct nvme_iod {
d49187e9 223 struct nvme_request req;
f4800d6d 224 struct nvme_queue *nvmeq;
a7a7cbe3 225 bool use_sgl;
f4800d6d 226 int aborted;
71bd150c 227 int npages; /* In the PRP list. 0 means small pool in use */
71bd150c
CH
228 int nents; /* Used in scatterlist */
229 int length; /* Of data, in bytes */
230 dma_addr_t first_dma;
bf684057 231 struct scatterlist meta_sg; /* metadata requires single contiguous buffer */
f4800d6d
CH
232 struct scatterlist *sg;
233 struct scatterlist inline_sg[0];
b60503ba
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234};
235
236/*
237 * Check we didin't inadvertently grow the command struct
238 */
239static inline void _nvme_check_size(void)
240{
241 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
242 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
243 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
244 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
245 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
f8ebf840 246 BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
c30341dc 247 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
b60503ba 248 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
0add5e8e
JT
249 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != NVME_IDENTIFY_DATA_SIZE);
250 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != NVME_IDENTIFY_DATA_SIZE);
b60503ba 251 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
6ecec745 252 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
f9f38e33
HK
253 BUILD_BUG_ON(sizeof(struct nvme_dbbuf) != 64);
254}
255
3b6592f7
JA
256static unsigned int max_io_queues(void)
257{
4b04cc6a 258 return num_possible_cpus() + write_queues + poll_queues;
3b6592f7
JA
259}
260
261static unsigned int max_queue_count(void)
262{
263 /* IO queues + admin queue */
264 return 1 + max_io_queues();
265}
266
f9f38e33
HK
267static inline unsigned int nvme_dbbuf_size(u32 stride)
268{
3b6592f7 269 return (max_queue_count() * 8 * stride);
f9f38e33
HK
270}
271
272static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
273{
274 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
275
276 if (dev->dbbuf_dbs)
277 return 0;
278
279 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
280 &dev->dbbuf_dbs_dma_addr,
281 GFP_KERNEL);
282 if (!dev->dbbuf_dbs)
283 return -ENOMEM;
284 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
285 &dev->dbbuf_eis_dma_addr,
286 GFP_KERNEL);
287 if (!dev->dbbuf_eis) {
288 dma_free_coherent(dev->dev, mem_size,
289 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
290 dev->dbbuf_dbs = NULL;
291 return -ENOMEM;
292 }
293
294 return 0;
295}
296
297static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
298{
299 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
300
301 if (dev->dbbuf_dbs) {
302 dma_free_coherent(dev->dev, mem_size,
303 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
304 dev->dbbuf_dbs = NULL;
305 }
306 if (dev->dbbuf_eis) {
307 dma_free_coherent(dev->dev, mem_size,
308 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
309 dev->dbbuf_eis = NULL;
310 }
311}
312
313static void nvme_dbbuf_init(struct nvme_dev *dev,
314 struct nvme_queue *nvmeq, int qid)
315{
316 if (!dev->dbbuf_dbs || !qid)
317 return;
318
319 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
320 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
321 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
322 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
323}
324
325static void nvme_dbbuf_set(struct nvme_dev *dev)
326{
327 struct nvme_command c;
328
329 if (!dev->dbbuf_dbs)
330 return;
331
332 memset(&c, 0, sizeof(c));
333 c.dbbuf.opcode = nvme_admin_dbbuf;
334 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
335 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
336
337 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
9bdcfb10 338 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
f9f38e33
HK
339 /* Free memory and continue on */
340 nvme_dbbuf_dma_free(dev);
341 }
342}
343
344static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
345{
346 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
347}
348
349/* Update dbbuf and return true if an MMIO is required */
350static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
351 volatile u32 *dbbuf_ei)
352{
353 if (dbbuf_db) {
354 u16 old_value;
355
356 /*
357 * Ensure that the queue is written before updating
358 * the doorbell in memory
359 */
360 wmb();
361
362 old_value = *dbbuf_db;
363 *dbbuf_db = value;
364
f1ed3df2
MW
365 /*
366 * Ensure that the doorbell is updated before reading the event
367 * index from memory. The controller needs to provide similar
368 * ordering to ensure the envent index is updated before reading
369 * the doorbell.
370 */
371 mb();
372
f9f38e33
HK
373 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value))
374 return false;
375 }
376
377 return true;
b60503ba
MW
378}
379
ac3dd5bd
JA
380/*
381 * Max size of iod being embedded in the request payload
382 */
383#define NVME_INT_PAGES 2
5fd4ce1b 384#define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size)
ac3dd5bd
JA
385
386/*
387 * Will slightly overestimate the number of pages needed. This is OK
388 * as it only leads to a small amount of wasted memory for the lifetime of
389 * the I/O.
390 */
391static int nvme_npages(unsigned size, struct nvme_dev *dev)
392{
5fd4ce1b
CH
393 unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size,
394 dev->ctrl.page_size);
ac3dd5bd
JA
395 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
396}
397
a7a7cbe3
CK
398/*
399 * Calculates the number of pages needed for the SGL segments. For example a 4k
400 * page can accommodate 256 SGL descriptors.
401 */
402static int nvme_pci_npages_sgl(unsigned int num_seg)
ac3dd5bd 403{
a7a7cbe3 404 return DIV_ROUND_UP(num_seg * sizeof(struct nvme_sgl_desc), PAGE_SIZE);
f4800d6d 405}
ac3dd5bd 406
a7a7cbe3
CK
407static unsigned int nvme_pci_iod_alloc_size(struct nvme_dev *dev,
408 unsigned int size, unsigned int nseg, bool use_sgl)
f4800d6d 409{
a7a7cbe3
CK
410 size_t alloc_size;
411
412 if (use_sgl)
413 alloc_size = sizeof(__le64 *) * nvme_pci_npages_sgl(nseg);
414 else
415 alloc_size = sizeof(__le64 *) * nvme_npages(size, dev);
416
417 return alloc_size + sizeof(struct scatterlist) * nseg;
f4800d6d 418}
ac3dd5bd 419
a7a7cbe3 420static unsigned int nvme_pci_cmd_size(struct nvme_dev *dev, bool use_sgl)
f4800d6d 421{
a7a7cbe3
CK
422 unsigned int alloc_size = nvme_pci_iod_alloc_size(dev,
423 NVME_INT_BYTES(dev), NVME_INT_PAGES,
424 use_sgl);
425
426 return sizeof(struct nvme_iod) + alloc_size;
ac3dd5bd
JA
427}
428
a4aea562
MB
429static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
430 unsigned int hctx_idx)
e85248e5 431{
a4aea562 432 struct nvme_dev *dev = data;
147b27e4 433 struct nvme_queue *nvmeq = &dev->queues[0];
a4aea562 434
42483228
KB
435 WARN_ON(hctx_idx != 0);
436 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
437 WARN_ON(nvmeq->tags);
438
a4aea562 439 hctx->driver_data = nvmeq;
42483228 440 nvmeq->tags = &dev->admin_tagset.tags[0];
a4aea562 441 return 0;
e85248e5
MW
442}
443
4af0e21c
KB
444static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
445{
446 struct nvme_queue *nvmeq = hctx->driver_data;
447
448 nvmeq->tags = NULL;
449}
450
a4aea562
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451static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
452 unsigned int hctx_idx)
b60503ba 453{
a4aea562 454 struct nvme_dev *dev = data;
147b27e4 455 struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
a4aea562 456
42483228
KB
457 if (!nvmeq->tags)
458 nvmeq->tags = &dev->tagset.tags[hctx_idx];
b60503ba 459
42483228 460 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
a4aea562
MB
461 hctx->driver_data = nvmeq;
462 return 0;
b60503ba
MW
463}
464
d6296d39
CH
465static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req,
466 unsigned int hctx_idx, unsigned int numa_node)
b60503ba 467{
d6296d39 468 struct nvme_dev *dev = set->driver_data;
f4800d6d 469 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
0350815a 470 int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0;
147b27e4 471 struct nvme_queue *nvmeq = &dev->queues[queue_idx];
a4aea562
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472
473 BUG_ON(!nvmeq);
f4800d6d 474 iod->nvmeq = nvmeq;
59e29ce6
SG
475
476 nvme_req(req)->ctrl = &dev->ctrl;
a4aea562
MB
477 return 0;
478}
479
3b6592f7
JA
480static int queue_irq_offset(struct nvme_dev *dev)
481{
482 /* if we have more than 1 vec, admin queue offsets us by 1 */
483 if (dev->num_vecs > 1)
484 return 1;
485
486 return 0;
487}
488
dca51e78
CH
489static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
490{
491 struct nvme_dev *dev = set->driver_data;
3b6592f7
JA
492 int i, qoff, offset;
493
494 offset = queue_irq_offset(dev);
495 for (i = 0, qoff = 0; i < set->nr_maps; i++) {
496 struct blk_mq_queue_map *map = &set->map[i];
497
498 map->nr_queues = dev->io_queues[i];
499 if (!map->nr_queues) {
e20ba6e1 500 BUG_ON(i == HCTX_TYPE_DEFAULT);
7e849dd9 501 continue;
3b6592f7
JA
502 }
503
4b04cc6a
JA
504 /*
505 * The poll queue(s) doesn't have an IRQ (and hence IRQ
506 * affinity), so use the regular blk-mq cpu mapping
507 */
3b6592f7 508 map->queue_offset = qoff;
e20ba6e1 509 if (i != HCTX_TYPE_POLL)
4b04cc6a
JA
510 blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset);
511 else
512 blk_mq_map_queues(map);
3b6592f7
JA
513 qoff += map->nr_queues;
514 offset += map->nr_queues;
515 }
516
517 return 0;
dca51e78
CH
518}
519
04f3eafd
JA
520/*
521 * Write sq tail if we are asked to, or if the next command would wrap.
522 */
523static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq)
524{
525 if (!write_sq) {
526 u16 next_tail = nvmeq->sq_tail + 1;
527
528 if (next_tail == nvmeq->q_depth)
529 next_tail = 0;
530 if (next_tail != nvmeq->last_sq_tail)
531 return;
532 }
533
534 if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail,
535 nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei))
536 writel(nvmeq->sq_tail, nvmeq->q_db);
537 nvmeq->last_sq_tail = nvmeq->sq_tail;
538}
539
b60503ba 540/**
90ea5ca4 541 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
b60503ba
MW
542 * @nvmeq: The queue to use
543 * @cmd: The command to send
04f3eafd 544 * @write_sq: whether to write to the SQ doorbell
b60503ba 545 */
04f3eafd
JA
546static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd,
547 bool write_sq)
b60503ba 548{
90ea5ca4 549 spin_lock(&nvmeq->sq_lock);
0f238ff5 550 memcpy(&nvmeq->sq_cmds[nvmeq->sq_tail], cmd, sizeof(*cmd));
90ea5ca4
CH
551 if (++nvmeq->sq_tail == nvmeq->q_depth)
552 nvmeq->sq_tail = 0;
04f3eafd
JA
553 nvme_write_sq_db(nvmeq, write_sq);
554 spin_unlock(&nvmeq->sq_lock);
555}
556
557static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx)
558{
559 struct nvme_queue *nvmeq = hctx->driver_data;
560
561 spin_lock(&nvmeq->sq_lock);
562 if (nvmeq->sq_tail != nvmeq->last_sq_tail)
563 nvme_write_sq_db(nvmeq, true);
90ea5ca4 564 spin_unlock(&nvmeq->sq_lock);
b60503ba
MW
565}
566
a7a7cbe3 567static void **nvme_pci_iod_list(struct request *req)
b60503ba 568{
f4800d6d 569 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3 570 return (void **)(iod->sg + blk_rq_nr_phys_segments(req));
b60503ba
MW
571}
572
955b1b5a
MI
573static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req)
574{
575 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
20469a37 576 int nseg = blk_rq_nr_phys_segments(req);
955b1b5a
MI
577 unsigned int avg_seg_size;
578
20469a37
KB
579 if (nseg == 0)
580 return false;
581
582 avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
955b1b5a
MI
583
584 if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1))))
585 return false;
586 if (!iod->nvmeq->qid)
587 return false;
588 if (!sgl_threshold || avg_seg_size < sgl_threshold)
589 return false;
590 return true;
591}
592
fc17b653 593static blk_status_t nvme_init_iod(struct request *rq, struct nvme_dev *dev)
ac3dd5bd 594{
f4800d6d 595 struct nvme_iod *iod = blk_mq_rq_to_pdu(rq);
f9d03f96 596 int nseg = blk_rq_nr_phys_segments(rq);
b131c61d 597 unsigned int size = blk_rq_payload_bytes(rq);
ac3dd5bd 598
955b1b5a
MI
599 iod->use_sgl = nvme_pci_use_sgls(dev, rq);
600
f4800d6d 601 if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) {
943e942e 602 iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC);
f4800d6d 603 if (!iod->sg)
fc17b653 604 return BLK_STS_RESOURCE;
f4800d6d
CH
605 } else {
606 iod->sg = iod->inline_sg;
ac3dd5bd
JA
607 }
608
f4800d6d
CH
609 iod->aborted = 0;
610 iod->npages = -1;
611 iod->nents = 0;
612 iod->length = size;
f80ec966 613
fc17b653 614 return BLK_STS_OK;
ac3dd5bd
JA
615}
616
f4800d6d 617static void nvme_free_iod(struct nvme_dev *dev, struct request *req)
b60503ba 618{
f4800d6d 619 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3
CK
620 const int last_prp = dev->ctrl.page_size / sizeof(__le64) - 1;
621 dma_addr_t dma_addr = iod->first_dma, next_dma_addr;
622
eca18b23 623 int i;
eca18b23
MW
624
625 if (iod->npages == 0)
a7a7cbe3
CK
626 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0],
627 dma_addr);
628
eca18b23 629 for (i = 0; i < iod->npages; i++) {
a7a7cbe3
CK
630 void *addr = nvme_pci_iod_list(req)[i];
631
632 if (iod->use_sgl) {
633 struct nvme_sgl_desc *sg_list = addr;
634
635 next_dma_addr =
636 le64_to_cpu((sg_list[SGES_PER_PAGE - 1]).addr);
637 } else {
638 __le64 *prp_list = addr;
639
640 next_dma_addr = le64_to_cpu(prp_list[last_prp]);
641 }
642
643 dma_pool_free(dev->prp_page_pool, addr, dma_addr);
644 dma_addr = next_dma_addr;
eca18b23 645 }
ac3dd5bd 646
f4800d6d 647 if (iod->sg != iod->inline_sg)
943e942e 648 mempool_free(iod->sg, dev->iod_mempool);
b4ff9c8d
KB
649}
650
d0877473
KB
651static void nvme_print_sgl(struct scatterlist *sgl, int nents)
652{
653 int i;
654 struct scatterlist *sg;
655
656 for_each_sg(sgl, sg, nents, i) {
657 dma_addr_t phys = sg_phys(sg);
658 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
659 "dma_address:%pad dma_length:%d\n",
660 i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
661 sg_dma_len(sg));
662 }
663}
664
a7a7cbe3
CK
665static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
666 struct request *req, struct nvme_rw_command *cmnd)
ff22b54f 667{
f4800d6d 668 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
99802a7a 669 struct dma_pool *pool;
b131c61d 670 int length = blk_rq_payload_bytes(req);
eca18b23 671 struct scatterlist *sg = iod->sg;
ff22b54f
MW
672 int dma_len = sg_dma_len(sg);
673 u64 dma_addr = sg_dma_address(sg);
5fd4ce1b 674 u32 page_size = dev->ctrl.page_size;
f137e0f1 675 int offset = dma_addr & (page_size - 1);
e025344c 676 __le64 *prp_list;
a7a7cbe3 677 void **list = nvme_pci_iod_list(req);
e025344c 678 dma_addr_t prp_dma;
eca18b23 679 int nprps, i;
ff22b54f 680
1d090624 681 length -= (page_size - offset);
5228b328
JS
682 if (length <= 0) {
683 iod->first_dma = 0;
a7a7cbe3 684 goto done;
5228b328 685 }
ff22b54f 686
1d090624 687 dma_len -= (page_size - offset);
ff22b54f 688 if (dma_len) {
1d090624 689 dma_addr += (page_size - offset);
ff22b54f
MW
690 } else {
691 sg = sg_next(sg);
692 dma_addr = sg_dma_address(sg);
693 dma_len = sg_dma_len(sg);
694 }
695
1d090624 696 if (length <= page_size) {
edd10d33 697 iod->first_dma = dma_addr;
a7a7cbe3 698 goto done;
e025344c
SMM
699 }
700
1d090624 701 nprps = DIV_ROUND_UP(length, page_size);
99802a7a
MW
702 if (nprps <= (256 / 8)) {
703 pool = dev->prp_small_pool;
eca18b23 704 iod->npages = 0;
99802a7a
MW
705 } else {
706 pool = dev->prp_page_pool;
eca18b23 707 iod->npages = 1;
99802a7a
MW
708 }
709
69d2b571 710 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
b77954cb 711 if (!prp_list) {
edd10d33 712 iod->first_dma = dma_addr;
eca18b23 713 iod->npages = -1;
86eea289 714 return BLK_STS_RESOURCE;
b77954cb 715 }
eca18b23
MW
716 list[0] = prp_list;
717 iod->first_dma = prp_dma;
e025344c
SMM
718 i = 0;
719 for (;;) {
1d090624 720 if (i == page_size >> 3) {
e025344c 721 __le64 *old_prp_list = prp_list;
69d2b571 722 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
eca18b23 723 if (!prp_list)
86eea289 724 return BLK_STS_RESOURCE;
eca18b23 725 list[iod->npages++] = prp_list;
7523d834
MW
726 prp_list[0] = old_prp_list[i - 1];
727 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
728 i = 1;
e025344c
SMM
729 }
730 prp_list[i++] = cpu_to_le64(dma_addr);
1d090624
KB
731 dma_len -= page_size;
732 dma_addr += page_size;
733 length -= page_size;
e025344c
SMM
734 if (length <= 0)
735 break;
736 if (dma_len > 0)
737 continue;
86eea289
KB
738 if (unlikely(dma_len < 0))
739 goto bad_sgl;
e025344c
SMM
740 sg = sg_next(sg);
741 dma_addr = sg_dma_address(sg);
742 dma_len = sg_dma_len(sg);
ff22b54f
MW
743 }
744
a7a7cbe3
CK
745done:
746 cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
747 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
748
86eea289
KB
749 return BLK_STS_OK;
750
751 bad_sgl:
d0877473
KB
752 WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents),
753 "Invalid SGL for payload:%d nents:%d\n",
754 blk_rq_payload_bytes(req), iod->nents);
86eea289 755 return BLK_STS_IOERR;
ff22b54f
MW
756}
757
a7a7cbe3
CK
758static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
759 struct scatterlist *sg)
760{
761 sge->addr = cpu_to_le64(sg_dma_address(sg));
762 sge->length = cpu_to_le32(sg_dma_len(sg));
763 sge->type = NVME_SGL_FMT_DATA_DESC << 4;
764}
765
766static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
767 dma_addr_t dma_addr, int entries)
768{
769 sge->addr = cpu_to_le64(dma_addr);
770 if (entries < SGES_PER_PAGE) {
771 sge->length = cpu_to_le32(entries * sizeof(*sge));
772 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
773 } else {
774 sge->length = cpu_to_le32(PAGE_SIZE);
775 sge->type = NVME_SGL_FMT_SEG_DESC << 4;
776 }
777}
778
779static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
b0f2853b 780 struct request *req, struct nvme_rw_command *cmd, int entries)
a7a7cbe3
CK
781{
782 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3
CK
783 struct dma_pool *pool;
784 struct nvme_sgl_desc *sg_list;
785 struct scatterlist *sg = iod->sg;
a7a7cbe3 786 dma_addr_t sgl_dma;
b0f2853b 787 int i = 0;
a7a7cbe3 788
a7a7cbe3
CK
789 /* setting the transfer type as SGL */
790 cmd->flags = NVME_CMD_SGL_METABUF;
791
b0f2853b 792 if (entries == 1) {
a7a7cbe3
CK
793 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
794 return BLK_STS_OK;
795 }
796
797 if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
798 pool = dev->prp_small_pool;
799 iod->npages = 0;
800 } else {
801 pool = dev->prp_page_pool;
802 iod->npages = 1;
803 }
804
805 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
806 if (!sg_list) {
807 iod->npages = -1;
808 return BLK_STS_RESOURCE;
809 }
810
811 nvme_pci_iod_list(req)[0] = sg_list;
812 iod->first_dma = sgl_dma;
813
814 nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
815
816 do {
817 if (i == SGES_PER_PAGE) {
818 struct nvme_sgl_desc *old_sg_desc = sg_list;
819 struct nvme_sgl_desc *link = &old_sg_desc[i - 1];
820
821 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
822 if (!sg_list)
823 return BLK_STS_RESOURCE;
824
825 i = 0;
826 nvme_pci_iod_list(req)[iod->npages++] = sg_list;
827 sg_list[i++] = *link;
828 nvme_pci_sgl_set_seg(link, sgl_dma, entries);
829 }
830
831 nvme_pci_sgl_set_data(&sg_list[i++], sg);
a7a7cbe3 832 sg = sg_next(sg);
b0f2853b 833 } while (--entries > 0);
a7a7cbe3 834
a7a7cbe3
CK
835 return BLK_STS_OK;
836}
837
fc17b653 838static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
b131c61d 839 struct nvme_command *cmnd)
d29ec824 840{
f4800d6d 841 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
ba1ca37e
CH
842 struct request_queue *q = req->q;
843 enum dma_data_direction dma_dir = rq_data_dir(req) ?
844 DMA_TO_DEVICE : DMA_FROM_DEVICE;
fc17b653 845 blk_status_t ret = BLK_STS_IOERR;
b0f2853b 846 int nr_mapped;
d29ec824 847
f9d03f96 848 sg_init_table(iod->sg, blk_rq_nr_phys_segments(req));
ba1ca37e
CH
849 iod->nents = blk_rq_map_sg(q, req, iod->sg);
850 if (!iod->nents)
851 goto out;
d29ec824 852
fc17b653 853 ret = BLK_STS_RESOURCE;
e0596ab2
LG
854
855 if (is_pci_p2pdma_page(sg_page(iod->sg)))
856 nr_mapped = pci_p2pdma_map_sg(dev->dev, iod->sg, iod->nents,
857 dma_dir);
858 else
859 nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents,
860 dma_dir, DMA_ATTR_NO_WARN);
b0f2853b 861 if (!nr_mapped)
ba1ca37e 862 goto out;
d29ec824 863
955b1b5a 864 if (iod->use_sgl)
b0f2853b 865 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped);
a7a7cbe3
CK
866 else
867 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
868
86eea289 869 if (ret != BLK_STS_OK)
ba1ca37e 870 goto out_unmap;
0e5e4f0e 871
fc17b653 872 ret = BLK_STS_IOERR;
ba1ca37e
CH
873 if (blk_integrity_rq(req)) {
874 if (blk_rq_count_integrity_sg(q, req->bio) != 1)
875 goto out_unmap;
0e5e4f0e 876
bf684057
CH
877 sg_init_table(&iod->meta_sg, 1);
878 if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1)
ba1ca37e 879 goto out_unmap;
0e5e4f0e 880
bf684057 881 if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir))
ba1ca37e 882 goto out_unmap;
00df5cb4 883
bf684057 884 cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg));
3045c0d0
CK
885 }
886
fc17b653 887 return BLK_STS_OK;
00df5cb4 888
ba1ca37e
CH
889out_unmap:
890 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
891out:
892 return ret;
00df5cb4
MW
893}
894
f4800d6d 895static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
b60503ba 896{
f4800d6d 897 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
d4f6c3ab
CH
898 enum dma_data_direction dma_dir = rq_data_dir(req) ?
899 DMA_TO_DEVICE : DMA_FROM_DEVICE;
900
901 if (iod->nents) {
e0596ab2
LG
902 /* P2PDMA requests do not need to be unmapped */
903 if (!is_pci_p2pdma_page(sg_page(iod->sg)))
904 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
905
f7f1fc36 906 if (blk_integrity_rq(req))
bf684057 907 dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir);
e19b127f 908 }
e1e5e564 909
f9d03f96 910 nvme_cleanup_cmd(req);
f4800d6d 911 nvme_free_iod(dev, req);
d4f6c3ab 912}
b60503ba 913
d29ec824
CH
914/*
915 * NOTE: ns is NULL when called on the admin queue.
916 */
fc17b653 917static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
a4aea562 918 const struct blk_mq_queue_data *bd)
edd10d33 919{
a4aea562
MB
920 struct nvme_ns *ns = hctx->queue->queuedata;
921 struct nvme_queue *nvmeq = hctx->driver_data;
d29ec824 922 struct nvme_dev *dev = nvmeq->dev;
a4aea562 923 struct request *req = bd->rq;
ba1ca37e 924 struct nvme_command cmnd;
ebe6d874 925 blk_status_t ret;
e1e5e564 926
d1f06f4a
JA
927 /*
928 * We should not need to do this, but we're still using this to
929 * ensure we can drain requests on a dying queue.
930 */
4e224106 931 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
d1f06f4a
JA
932 return BLK_STS_IOERR;
933
f9d03f96 934 ret = nvme_setup_cmd(ns, req, &cmnd);
fc17b653 935 if (ret)
f4800d6d 936 return ret;
a4aea562 937
b131c61d 938 ret = nvme_init_iod(req, dev);
fc17b653 939 if (ret)
f9d03f96 940 goto out_free_cmd;
a4aea562 941
fc17b653 942 if (blk_rq_nr_phys_segments(req)) {
b131c61d 943 ret = nvme_map_data(dev, req, &cmnd);
fc17b653
CH
944 if (ret)
945 goto out_cleanup_iod;
946 }
a4aea562 947
aae239e1 948 blk_mq_start_request(req);
04f3eafd 949 nvme_submit_cmd(nvmeq, &cmnd, bd->last);
fc17b653 950 return BLK_STS_OK;
f9d03f96 951out_cleanup_iod:
f4800d6d 952 nvme_free_iod(dev, req);
f9d03f96
CH
953out_free_cmd:
954 nvme_cleanup_cmd(req);
ba1ca37e 955 return ret;
b60503ba 956}
e1e5e564 957
77f02a7a 958static void nvme_pci_complete_rq(struct request *req)
eee417b0 959{
f4800d6d 960 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a4aea562 961
77f02a7a
CH
962 nvme_unmap_data(iod->nvmeq->dev, req);
963 nvme_complete_rq(req);
b60503ba
MW
964}
965
d783e0bd 966/* We read the CQE phase first to check if the rest of the entry is valid */
750dde44 967static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq)
d783e0bd 968{
750dde44
CH
969 return (le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) ==
970 nvmeq->cq_phase;
d783e0bd
MR
971}
972
eb281c82 973static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
b60503ba 974{
eb281c82 975 u16 head = nvmeq->cq_head;
adf68f21 976
397c699f
KB
977 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
978 nvmeq->dbbuf_cq_ei))
979 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
eb281c82 980}
aae239e1 981
5cb525c8 982static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx)
83a12fb7 983{
5cb525c8 984 volatile struct nvme_completion *cqe = &nvmeq->cqes[idx];
83a12fb7 985 struct request *req;
adf68f21 986
83a12fb7
SG
987 if (unlikely(cqe->command_id >= nvmeq->q_depth)) {
988 dev_warn(nvmeq->dev->ctrl.device,
989 "invalid id %d completed on queue %d\n",
990 cqe->command_id, le16_to_cpu(cqe->sq_id));
991 return;
b60503ba
MW
992 }
993
83a12fb7
SG
994 /*
995 * AEN requests are special as they don't time out and can
996 * survive any kind of queue freeze and often don't respond to
997 * aborts. We don't even bother to allocate a struct request
998 * for them but rather special case them here.
999 */
1000 if (unlikely(nvmeq->qid == 0 &&
38dabe21 1001 cqe->command_id >= NVME_AQ_BLK_MQ_DEPTH)) {
83a12fb7
SG
1002 nvme_complete_async_event(&nvmeq->dev->ctrl,
1003 cqe->status, &cqe->result);
a0fa9647 1004 return;
83a12fb7 1005 }
b60503ba 1006
83a12fb7 1007 req = blk_mq_tag_to_rq(*nvmeq->tags, cqe->command_id);
604c01d5 1008 trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail);
83a12fb7
SG
1009 nvme_end_request(req, cqe->status, cqe->result);
1010}
b60503ba 1011
5cb525c8 1012static void nvme_complete_cqes(struct nvme_queue *nvmeq, u16 start, u16 end)
b60503ba 1013{
5cb525c8
JA
1014 while (start != end) {
1015 nvme_handle_cqe(nvmeq, start);
1016 if (++start == nvmeq->q_depth)
1017 start = 0;
1018 }
1019}
adf68f21 1020
5cb525c8
JA
1021static inline void nvme_update_cq_head(struct nvme_queue *nvmeq)
1022{
dcca1662 1023 if (nvmeq->cq_head == nvmeq->q_depth - 1) {
5cb525c8
JA
1024 nvmeq->cq_head = 0;
1025 nvmeq->cq_phase = !nvmeq->cq_phase;
dcca1662
HY
1026 } else {
1027 nvmeq->cq_head++;
b60503ba 1028 }
a0fa9647
JA
1029}
1030
1052b8ac
JA
1031static inline int nvme_process_cq(struct nvme_queue *nvmeq, u16 *start,
1032 u16 *end, unsigned int tag)
a0fa9647 1033{
1052b8ac 1034 int found = 0;
b60503ba 1035
5cb525c8 1036 *start = nvmeq->cq_head;
1052b8ac
JA
1037 while (nvme_cqe_pending(nvmeq)) {
1038 if (tag == -1U || nvmeq->cqes[nvmeq->cq_head].command_id == tag)
1039 found++;
5cb525c8 1040 nvme_update_cq_head(nvmeq);
920d13a8 1041 }
5cb525c8 1042 *end = nvmeq->cq_head;
eb281c82 1043
5cb525c8 1044 if (*start != *end)
920d13a8 1045 nvme_ring_cq_doorbell(nvmeq);
5cb525c8 1046 return found;
b60503ba
MW
1047}
1048
1049static irqreturn_t nvme_irq(int irq, void *data)
58ffacb5 1050{
58ffacb5 1051 struct nvme_queue *nvmeq = data;
68fa9dbe 1052 irqreturn_t ret = IRQ_NONE;
5cb525c8
JA
1053 u16 start, end;
1054
3a7afd8e
CH
1055 /*
1056 * The rmb/wmb pair ensures we see all updates from a previous run of
1057 * the irq handler, even if that was on another CPU.
1058 */
1059 rmb();
68fa9dbe
JA
1060 if (nvmeq->cq_head != nvmeq->last_cq_head)
1061 ret = IRQ_HANDLED;
5cb525c8 1062 nvme_process_cq(nvmeq, &start, &end, -1);
68fa9dbe 1063 nvmeq->last_cq_head = nvmeq->cq_head;
3a7afd8e 1064 wmb();
5cb525c8 1065
68fa9dbe
JA
1066 if (start != end) {
1067 nvme_complete_cqes(nvmeq, start, end);
1068 return IRQ_HANDLED;
1069 }
1070
1071 return ret;
58ffacb5
MW
1072}
1073
1074static irqreturn_t nvme_irq_check(int irq, void *data)
1075{
1076 struct nvme_queue *nvmeq = data;
750dde44 1077 if (nvme_cqe_pending(nvmeq))
d783e0bd
MR
1078 return IRQ_WAKE_THREAD;
1079 return IRQ_NONE;
58ffacb5
MW
1080}
1081
0b2a8a9f
CH
1082/*
1083 * Poll for completions any queue, including those not dedicated to polling.
1084 * Can be called from any context.
1085 */
1086static int nvme_poll_irqdisable(struct nvme_queue *nvmeq, unsigned int tag)
a0fa9647 1087{
3a7afd8e 1088 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
5cb525c8 1089 u16 start, end;
1052b8ac 1090 int found;
a0fa9647 1091
3a7afd8e
CH
1092 /*
1093 * For a poll queue we need to protect against the polling thread
1094 * using the CQ lock. For normal interrupt driven threads we have
1095 * to disable the interrupt to avoid racing with it.
1096 */
91a509f8 1097 if (nvmeq->cq_vector == -1) {
3a7afd8e 1098 spin_lock(&nvmeq->cq_poll_lock);
91a509f8 1099 found = nvme_process_cq(nvmeq, &start, &end, tag);
3a7afd8e 1100 spin_unlock(&nvmeq->cq_poll_lock);
91a509f8
CH
1101 } else {
1102 disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1103 found = nvme_process_cq(nvmeq, &start, &end, tag);
3a7afd8e 1104 enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
91a509f8 1105 }
442e19b7 1106
5cb525c8 1107 nvme_complete_cqes(nvmeq, start, end);
442e19b7 1108 return found;
a0fa9647
JA
1109}
1110
9743139c 1111static int nvme_poll(struct blk_mq_hw_ctx *hctx)
dabcefab
JA
1112{
1113 struct nvme_queue *nvmeq = hctx->driver_data;
1114 u16 start, end;
1115 bool found;
1116
1117 if (!nvme_cqe_pending(nvmeq))
1118 return 0;
1119
3a7afd8e 1120 spin_lock(&nvmeq->cq_poll_lock);
9743139c 1121 found = nvme_process_cq(nvmeq, &start, &end, -1);
3a7afd8e 1122 spin_unlock(&nvmeq->cq_poll_lock);
dabcefab
JA
1123
1124 nvme_complete_cqes(nvmeq, start, end);
1125 return found;
1126}
1127
ad22c355 1128static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
b60503ba 1129{
f866fc42 1130 struct nvme_dev *dev = to_nvme_dev(ctrl);
147b27e4 1131 struct nvme_queue *nvmeq = &dev->queues[0];
a4aea562 1132 struct nvme_command c;
b60503ba 1133
a4aea562
MB
1134 memset(&c, 0, sizeof(c));
1135 c.common.opcode = nvme_admin_async_event;
ad22c355 1136 c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
04f3eafd 1137 nvme_submit_cmd(nvmeq, &c, true);
f705f837
CH
1138}
1139
b60503ba 1140static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
f705f837 1141{
b60503ba
MW
1142 struct nvme_command c;
1143
1144 memset(&c, 0, sizeof(c));
1145 c.delete_queue.opcode = opcode;
1146 c.delete_queue.qid = cpu_to_le16(id);
1147
1c63dc66 1148 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW
1149}
1150
b60503ba 1151static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
a8e3e0bb 1152 struct nvme_queue *nvmeq, s16 vector)
b60503ba 1153{
b60503ba 1154 struct nvme_command c;
4b04cc6a
JA
1155 int flags = NVME_QUEUE_PHYS_CONTIG;
1156
1157 if (vector != -1)
1158 flags |= NVME_CQ_IRQ_ENABLED;
b60503ba 1159
d29ec824 1160 /*
16772ae6 1161 * Note: we (ab)use the fact that the prp fields survive if no data
d29ec824
CH
1162 * is attached to the request.
1163 */
b60503ba
MW
1164 memset(&c, 0, sizeof(c));
1165 c.create_cq.opcode = nvme_admin_create_cq;
1166 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1167 c.create_cq.cqid = cpu_to_le16(qid);
1168 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1169 c.create_cq.cq_flags = cpu_to_le16(flags);
4b04cc6a
JA
1170 if (vector != -1)
1171 c.create_cq.irq_vector = cpu_to_le16(vector);
1172 else
1173 c.create_cq.irq_vector = 0;
b60503ba 1174
1c63dc66 1175 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW
1176}
1177
1178static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1179 struct nvme_queue *nvmeq)
1180{
9abd68ef 1181 struct nvme_ctrl *ctrl = &dev->ctrl;
b60503ba 1182 struct nvme_command c;
81c1cd98 1183 int flags = NVME_QUEUE_PHYS_CONTIG;
b60503ba 1184
9abd68ef
JA
1185 /*
1186 * Some drives have a bug that auto-enables WRRU if MEDIUM isn't
1187 * set. Since URGENT priority is zeroes, it makes all queues
1188 * URGENT.
1189 */
1190 if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ)
1191 flags |= NVME_SQ_PRIO_MEDIUM;
1192
d29ec824 1193 /*
16772ae6 1194 * Note: we (ab)use the fact that the prp fields survive if no data
d29ec824
CH
1195 * is attached to the request.
1196 */
b60503ba
MW
1197 memset(&c, 0, sizeof(c));
1198 c.create_sq.opcode = nvme_admin_create_sq;
1199 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1200 c.create_sq.sqid = cpu_to_le16(qid);
1201 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1202 c.create_sq.sq_flags = cpu_to_le16(flags);
1203 c.create_sq.cqid = cpu_to_le16(qid);
1204
1c63dc66 1205 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW
1206}
1207
1208static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1209{
1210 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1211}
1212
1213static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1214{
1215 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1216}
1217
2a842aca 1218static void abort_endio(struct request *req, blk_status_t error)
bc5fc7e4 1219{
f4800d6d
CH
1220 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1221 struct nvme_queue *nvmeq = iod->nvmeq;
e44ac588 1222
27fa9bc5
CH
1223 dev_warn(nvmeq->dev->ctrl.device,
1224 "Abort status: 0x%x", nvme_req(req)->status);
e7a2a87d 1225 atomic_inc(&nvmeq->dev->ctrl.abort_limit);
e7a2a87d 1226 blk_mq_free_request(req);
bc5fc7e4
MW
1227}
1228
b2a0eb1a
KB
1229static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1230{
1231
1232 /* If true, indicates loss of adapter communication, possibly by a
1233 * NVMe Subsystem reset.
1234 */
1235 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1236
ad70062c
JW
1237 /* If there is a reset/reinit ongoing, we shouldn't reset again. */
1238 switch (dev->ctrl.state) {
1239 case NVME_CTRL_RESETTING:
ad6a0a52 1240 case NVME_CTRL_CONNECTING:
b2a0eb1a 1241 return false;
ad70062c
JW
1242 default:
1243 break;
1244 }
b2a0eb1a
KB
1245
1246 /* We shouldn't reset unless the controller is on fatal error state
1247 * _or_ if we lost the communication with it.
1248 */
1249 if (!(csts & NVME_CSTS_CFS) && !nssro)
1250 return false;
1251
b2a0eb1a
KB
1252 return true;
1253}
1254
1255static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1256{
1257 /* Read a config register to help see what died. */
1258 u16 pci_status;
1259 int result;
1260
1261 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1262 &pci_status);
1263 if (result == PCIBIOS_SUCCESSFUL)
1264 dev_warn(dev->ctrl.device,
1265 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1266 csts, pci_status);
1267 else
1268 dev_warn(dev->ctrl.device,
1269 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1270 csts, result);
1271}
1272
31c7c7d2 1273static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
c30341dc 1274{
f4800d6d
CH
1275 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1276 struct nvme_queue *nvmeq = iod->nvmeq;
c30341dc 1277 struct nvme_dev *dev = nvmeq->dev;
a4aea562 1278 struct request *abort_req;
a4aea562 1279 struct nvme_command cmd;
b2a0eb1a
KB
1280 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1281
651438bb
WX
1282 /* If PCI error recovery process is happening, we cannot reset or
1283 * the recovery mechanism will surely fail.
1284 */
1285 mb();
1286 if (pci_channel_offline(to_pci_dev(dev->dev)))
1287 return BLK_EH_RESET_TIMER;
1288
b2a0eb1a
KB
1289 /*
1290 * Reset immediately if the controller is failed
1291 */
1292 if (nvme_should_reset(dev, csts)) {
1293 nvme_warn_reset(dev, csts);
1294 nvme_dev_disable(dev, false);
d86c4d8e 1295 nvme_reset_ctrl(&dev->ctrl);
db8c48e4 1296 return BLK_EH_DONE;
b2a0eb1a 1297 }
c30341dc 1298
7776db1c
KB
1299 /*
1300 * Did we miss an interrupt?
1301 */
0b2a8a9f 1302 if (nvme_poll_irqdisable(nvmeq, req->tag)) {
7776db1c
KB
1303 dev_warn(dev->ctrl.device,
1304 "I/O %d QID %d timeout, completion polled\n",
1305 req->tag, nvmeq->qid);
db8c48e4 1306 return BLK_EH_DONE;
7776db1c
KB
1307 }
1308
31c7c7d2 1309 /*
fd634f41
CH
1310 * Shutdown immediately if controller times out while starting. The
1311 * reset work will see the pci device disabled when it gets the forced
1312 * cancellation error. All outstanding requests are completed on
db8c48e4 1313 * shutdown, so we return BLK_EH_DONE.
fd634f41 1314 */
4244140d
KB
1315 switch (dev->ctrl.state) {
1316 case NVME_CTRL_CONNECTING:
1317 case NVME_CTRL_RESETTING:
b9cac43c 1318 dev_warn_ratelimited(dev->ctrl.device,
fd634f41
CH
1319 "I/O %d QID %d timeout, disable controller\n",
1320 req->tag, nvmeq->qid);
a5cdb68c 1321 nvme_dev_disable(dev, false);
27fa9bc5 1322 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
db8c48e4 1323 return BLK_EH_DONE;
4244140d
KB
1324 default:
1325 break;
c30341dc
KB
1326 }
1327
fd634f41
CH
1328 /*
1329 * Shutdown the controller immediately and schedule a reset if the
1330 * command was already aborted once before and still hasn't been
1331 * returned to the driver, or if this is the admin queue.
31c7c7d2 1332 */
f4800d6d 1333 if (!nvmeq->qid || iod->aborted) {
1b3c47c1 1334 dev_warn(dev->ctrl.device,
e1569a16
KB
1335 "I/O %d QID %d timeout, reset controller\n",
1336 req->tag, nvmeq->qid);
a5cdb68c 1337 nvme_dev_disable(dev, false);
d86c4d8e 1338 nvme_reset_ctrl(&dev->ctrl);
c30341dc 1339
27fa9bc5 1340 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
db8c48e4 1341 return BLK_EH_DONE;
c30341dc 1342 }
c30341dc 1343
e7a2a87d 1344 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
6bf25d16 1345 atomic_inc(&dev->ctrl.abort_limit);
31c7c7d2 1346 return BLK_EH_RESET_TIMER;
6bf25d16 1347 }
7bf7d778 1348 iod->aborted = 1;
a4aea562 1349
c30341dc
KB
1350 memset(&cmd, 0, sizeof(cmd));
1351 cmd.abort.opcode = nvme_admin_abort_cmd;
a4aea562 1352 cmd.abort.cid = req->tag;
c30341dc 1353 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
c30341dc 1354
1b3c47c1
SG
1355 dev_warn(nvmeq->dev->ctrl.device,
1356 "I/O %d QID %d timeout, aborting\n",
1357 req->tag, nvmeq->qid);
e7a2a87d
CH
1358
1359 abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
eb71f435 1360 BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
e7a2a87d
CH
1361 if (IS_ERR(abort_req)) {
1362 atomic_inc(&dev->ctrl.abort_limit);
1363 return BLK_EH_RESET_TIMER;
1364 }
1365
1366 abort_req->timeout = ADMIN_TIMEOUT;
1367 abort_req->end_io_data = NULL;
1368 blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio);
c30341dc 1369
31c7c7d2
CH
1370 /*
1371 * The aborted req will be completed on receiving the abort req.
1372 * We enable the timer again. If hit twice, it'll cause a device reset,
1373 * as the device then is in a faulty state.
1374 */
1375 return BLK_EH_RESET_TIMER;
c30341dc
KB
1376}
1377
a4aea562
MB
1378static void nvme_free_queue(struct nvme_queue *nvmeq)
1379{
9e866774
MW
1380 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1381 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
63223078
CH
1382 if (!nvmeq->sq_cmds)
1383 return;
0f238ff5 1384
63223078
CH
1385 if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) {
1386 pci_free_p2pmem(to_pci_dev(nvmeq->q_dmadev),
1387 nvmeq->sq_cmds, SQ_SIZE(nvmeq->q_depth));
1388 } else {
1389 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
1390 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
0f238ff5 1391 }
9e866774
MW
1392}
1393
a1a5ef99 1394static void nvme_free_queues(struct nvme_dev *dev, int lowest)
22404274
KB
1395{
1396 int i;
1397
d858e5f0 1398 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
d858e5f0 1399 dev->ctrl.queue_count--;
147b27e4 1400 nvme_free_queue(&dev->queues[i]);
121c7ad4 1401 }
22404274
KB
1402}
1403
4d115420
KB
1404/**
1405 * nvme_suspend_queue - put queue into suspended state
40581d1a 1406 * @nvmeq: queue to suspend
4d115420
KB
1407 */
1408static int nvme_suspend_queue(struct nvme_queue *nvmeq)
b60503ba 1409{
4e224106 1410 if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags))
2b25d981 1411 return 1;
a09115b2 1412
4e224106 1413 /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */
d1f06f4a 1414 mb();
a09115b2 1415
4e224106 1416 nvmeq->dev->online_queues--;
1c63dc66 1417 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
c81545f9 1418 blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q);
4e224106
CH
1419 if (nvmeq->cq_vector == -1)
1420 return 0;
1421 pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq);
1422 nvmeq->cq_vector = -1;
4d115420
KB
1423 return 0;
1424}
b60503ba 1425
8fae268b
KB
1426static void nvme_suspend_io_queues(struct nvme_dev *dev)
1427{
1428 int i;
1429
1430 for (i = dev->ctrl.queue_count - 1; i > 0; i--)
1431 nvme_suspend_queue(&dev->queues[i]);
1432}
1433
a5cdb68c 1434static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
4d115420 1435{
147b27e4 1436 struct nvme_queue *nvmeq = &dev->queues[0];
4d115420 1437
a5cdb68c
KB
1438 if (shutdown)
1439 nvme_shutdown_ctrl(&dev->ctrl);
1440 else
20d0dfe6 1441 nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap);
07836e65 1442
0b2a8a9f 1443 nvme_poll_irqdisable(nvmeq, -1);
b60503ba
MW
1444}
1445
8ffaadf7
JD
1446static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1447 int entry_size)
1448{
1449 int q_depth = dev->q_depth;
5fd4ce1b
CH
1450 unsigned q_size_aligned = roundup(q_depth * entry_size,
1451 dev->ctrl.page_size);
8ffaadf7
JD
1452
1453 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
c45f5c99 1454 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
5fd4ce1b 1455 mem_per_q = round_down(mem_per_q, dev->ctrl.page_size);
c45f5c99 1456 q_depth = div_u64(mem_per_q, entry_size);
8ffaadf7
JD
1457
1458 /*
1459 * Ensure the reduced q_depth is above some threshold where it
1460 * would be better to map queues in system memory with the
1461 * original depth
1462 */
1463 if (q_depth < 64)
1464 return -ENOMEM;
1465 }
1466
1467 return q_depth;
1468}
1469
1470static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1471 int qid, int depth)
1472{
0f238ff5
LG
1473 struct pci_dev *pdev = to_pci_dev(dev->dev);
1474
1475 if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
1476 nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(depth));
1477 nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev,
1478 nvmeq->sq_cmds);
63223078
CH
1479 if (nvmeq->sq_dma_addr) {
1480 set_bit(NVMEQ_SQ_CMB, &nvmeq->flags);
1481 return 0;
1482 }
0f238ff5 1483 }
8ffaadf7 1484
63223078
CH
1485 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
1486 &nvmeq->sq_dma_addr, GFP_KERNEL);
815c6704
KB
1487 if (!nvmeq->sq_cmds)
1488 return -ENOMEM;
8ffaadf7
JD
1489 return 0;
1490}
1491
a6ff7262 1492static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
b60503ba 1493{
147b27e4 1494 struct nvme_queue *nvmeq = &dev->queues[qid];
b60503ba 1495
62314e40
KB
1496 if (dev->ctrl.queue_count > qid)
1497 return 0;
b60503ba 1498
750afb08
LC
1499 nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(depth),
1500 &nvmeq->cq_dma_addr, GFP_KERNEL);
b60503ba
MW
1501 if (!nvmeq->cqes)
1502 goto free_nvmeq;
b60503ba 1503
8ffaadf7 1504 if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth))
b60503ba
MW
1505 goto free_cqdma;
1506
e75ec752 1507 nvmeq->q_dmadev = dev->dev;
091b6092 1508 nvmeq->dev = dev;
1ab0cd69 1509 spin_lock_init(&nvmeq->sq_lock);
3a7afd8e 1510 spin_lock_init(&nvmeq->cq_poll_lock);
b60503ba 1511 nvmeq->cq_head = 0;
82123460 1512 nvmeq->cq_phase = 1;
b80d5ccc 1513 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
b60503ba 1514 nvmeq->q_depth = depth;
c30341dc 1515 nvmeq->qid = qid;
758dd7fd 1516 nvmeq->cq_vector = -1;
d858e5f0 1517 dev->ctrl.queue_count++;
36a7e993 1518
147b27e4 1519 return 0;
b60503ba
MW
1520
1521 free_cqdma:
e75ec752 1522 dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes,
b60503ba
MW
1523 nvmeq->cq_dma_addr);
1524 free_nvmeq:
147b27e4 1525 return -ENOMEM;
b60503ba
MW
1526}
1527
dca51e78 1528static int queue_request_irq(struct nvme_queue *nvmeq)
3001082c 1529{
0ff199cb
CH
1530 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1531 int nr = nvmeq->dev->ctrl.instance;
1532
1533 if (use_threaded_interrupts) {
1534 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1535 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1536 } else {
1537 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1538 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1539 }
3001082c
MW
1540}
1541
22404274 1542static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
b60503ba 1543{
22404274 1544 struct nvme_dev *dev = nvmeq->dev;
b60503ba 1545
22404274 1546 nvmeq->sq_tail = 0;
04f3eafd 1547 nvmeq->last_sq_tail = 0;
22404274
KB
1548 nvmeq->cq_head = 0;
1549 nvmeq->cq_phase = 1;
b80d5ccc 1550 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
22404274 1551 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
f9f38e33 1552 nvme_dbbuf_init(dev, nvmeq, qid);
42f61420 1553 dev->online_queues++;
3a7afd8e 1554 wmb(); /* ensure the first interrupt sees the initialization */
22404274
KB
1555}
1556
4b04cc6a 1557static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled)
22404274
KB
1558{
1559 struct nvme_dev *dev = nvmeq->dev;
1560 int result;
a8e3e0bb 1561 s16 vector;
3f85d50b 1562
d1ed6aa1
CH
1563 clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
1564
22b55601
KB
1565 /*
1566 * A queue's vector matches the queue identifier unless the controller
1567 * has only one vector available.
1568 */
4b04cc6a
JA
1569 if (!polled)
1570 vector = dev->num_vecs == 1 ? 0 : qid;
1571 else
1572 vector = -1;
1573
a8e3e0bb 1574 result = adapter_alloc_cq(dev, qid, nvmeq, vector);
ded45505
KB
1575 if (result)
1576 return result;
b60503ba
MW
1577
1578 result = adapter_alloc_sq(dev, qid, nvmeq);
1579 if (result < 0)
ded45505
KB
1580 return result;
1581 else if (result)
b60503ba
MW
1582 goto release_cq;
1583
a8e3e0bb 1584 nvmeq->cq_vector = vector;
161b8be2 1585 nvme_init_queue(nvmeq, qid);
4b04cc6a
JA
1586
1587 if (vector != -1) {
1588 result = queue_request_irq(nvmeq);
1589 if (result < 0)
1590 goto release_sq;
1591 }
b60503ba 1592
4e224106 1593 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
22404274 1594 return result;
b60503ba 1595
a8e3e0bb
JW
1596release_sq:
1597 nvmeq->cq_vector = -1;
f25a2dfc 1598 dev->online_queues--;
b60503ba 1599 adapter_delete_sq(dev, qid);
a8e3e0bb 1600release_cq:
b60503ba 1601 adapter_delete_cq(dev, qid);
22404274 1602 return result;
b60503ba
MW
1603}
1604
f363b089 1605static const struct blk_mq_ops nvme_mq_admin_ops = {
d29ec824 1606 .queue_rq = nvme_queue_rq,
77f02a7a 1607 .complete = nvme_pci_complete_rq,
a4aea562 1608 .init_hctx = nvme_admin_init_hctx,
4af0e21c 1609 .exit_hctx = nvme_admin_exit_hctx,
0350815a 1610 .init_request = nvme_init_request,
a4aea562
MB
1611 .timeout = nvme_timeout,
1612};
1613
f363b089 1614static const struct blk_mq_ops nvme_mq_ops = {
376f7ef8
CH
1615 .queue_rq = nvme_queue_rq,
1616 .complete = nvme_pci_complete_rq,
1617 .commit_rqs = nvme_commit_rqs,
1618 .init_hctx = nvme_init_hctx,
1619 .init_request = nvme_init_request,
1620 .map_queues = nvme_pci_map_queues,
1621 .timeout = nvme_timeout,
1622 .poll = nvme_poll,
dabcefab
JA
1623};
1624
ea191d2f
KB
1625static void nvme_dev_remove_admin(struct nvme_dev *dev)
1626{
1c63dc66 1627 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
69d9a99c
KB
1628 /*
1629 * If the controller was reset during removal, it's possible
1630 * user requests may be waiting on a stopped queue. Start the
1631 * queue to flush these to completion.
1632 */
c81545f9 1633 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1c63dc66 1634 blk_cleanup_queue(dev->ctrl.admin_q);
ea191d2f
KB
1635 blk_mq_free_tag_set(&dev->admin_tagset);
1636 }
1637}
1638
a4aea562
MB
1639static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1640{
1c63dc66 1641 if (!dev->ctrl.admin_q) {
a4aea562
MB
1642 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1643 dev->admin_tagset.nr_hw_queues = 1;
e3e9d50c 1644
38dabe21 1645 dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH;
a4aea562 1646 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
e75ec752 1647 dev->admin_tagset.numa_node = dev_to_node(dev->dev);
a7a7cbe3 1648 dev->admin_tagset.cmd_size = nvme_pci_cmd_size(dev, false);
d3484991 1649 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED;
a4aea562
MB
1650 dev->admin_tagset.driver_data = dev;
1651
1652 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1653 return -ENOMEM;
34b6c231 1654 dev->ctrl.admin_tagset = &dev->admin_tagset;
a4aea562 1655
1c63dc66
CH
1656 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1657 if (IS_ERR(dev->ctrl.admin_q)) {
a4aea562
MB
1658 blk_mq_free_tag_set(&dev->admin_tagset);
1659 return -ENOMEM;
1660 }
1c63dc66 1661 if (!blk_get_queue(dev->ctrl.admin_q)) {
ea191d2f 1662 nvme_dev_remove_admin(dev);
1c63dc66 1663 dev->ctrl.admin_q = NULL;
ea191d2f
KB
1664 return -ENODEV;
1665 }
0fb59cbc 1666 } else
c81545f9 1667 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
a4aea562
MB
1668
1669 return 0;
1670}
1671
97f6ef64
XY
1672static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1673{
1674 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1675}
1676
1677static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1678{
1679 struct pci_dev *pdev = to_pci_dev(dev->dev);
1680
1681 if (size <= dev->bar_mapped_size)
1682 return 0;
1683 if (size > pci_resource_len(pdev, 0))
1684 return -ENOMEM;
1685 if (dev->bar)
1686 iounmap(dev->bar);
1687 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1688 if (!dev->bar) {
1689 dev->bar_mapped_size = 0;
1690 return -ENOMEM;
1691 }
1692 dev->bar_mapped_size = size;
1693 dev->dbs = dev->bar + NVME_REG_DBS;
1694
1695 return 0;
1696}
1697
01ad0990 1698static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
b60503ba 1699{
ba47e386 1700 int result;
b60503ba
MW
1701 u32 aqa;
1702 struct nvme_queue *nvmeq;
1703
97f6ef64
XY
1704 result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1705 if (result < 0)
1706 return result;
1707
8ef2074d 1708 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
20d0dfe6 1709 NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
dfbac8c7 1710
7a67cbea
CH
1711 if (dev->subsystem &&
1712 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1713 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
dfbac8c7 1714
20d0dfe6 1715 result = nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap);
ba47e386
MW
1716 if (result < 0)
1717 return result;
b60503ba 1718
a6ff7262 1719 result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
147b27e4
SG
1720 if (result)
1721 return result;
b60503ba 1722
147b27e4 1723 nvmeq = &dev->queues[0];
b60503ba
MW
1724 aqa = nvmeq->q_depth - 1;
1725 aqa |= aqa << 16;
1726
7a67cbea
CH
1727 writel(aqa, dev->bar + NVME_REG_AQA);
1728 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1729 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
b60503ba 1730
20d0dfe6 1731 result = nvme_enable_ctrl(&dev->ctrl, dev->ctrl.cap);
025c557a 1732 if (result)
d4875622 1733 return result;
a4aea562 1734
2b25d981 1735 nvmeq->cq_vector = 0;
161b8be2 1736 nvme_init_queue(nvmeq, 0);
dca51e78 1737 result = queue_request_irq(nvmeq);
758dd7fd
JD
1738 if (result) {
1739 nvmeq->cq_vector = -1;
d4875622 1740 return result;
758dd7fd 1741 }
025c557a 1742
4e224106 1743 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
b60503ba
MW
1744 return result;
1745}
1746
749941f2 1747static int nvme_create_io_queues(struct nvme_dev *dev)
42f61420 1748{
4b04cc6a 1749 unsigned i, max, rw_queues;
749941f2 1750 int ret = 0;
42f61420 1751
d858e5f0 1752 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
a6ff7262 1753 if (nvme_alloc_queue(dev, i, dev->q_depth)) {
749941f2 1754 ret = -ENOMEM;
42f61420 1755 break;
749941f2
CH
1756 }
1757 }
42f61420 1758
d858e5f0 1759 max = min(dev->max_qid, dev->ctrl.queue_count - 1);
e20ba6e1
CH
1760 if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) {
1761 rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] +
1762 dev->io_queues[HCTX_TYPE_READ];
4b04cc6a
JA
1763 } else {
1764 rw_queues = max;
1765 }
1766
949928c1 1767 for (i = dev->online_queues; i <= max; i++) {
4b04cc6a
JA
1768 bool polled = i > rw_queues;
1769
1770 ret = nvme_create_queue(&dev->queues[i], i, polled);
d4875622 1771 if (ret)
42f61420 1772 break;
27e8166c 1773 }
749941f2
CH
1774
1775 /*
1776 * Ignore failing Create SQ/CQ commands, we can continue with less
8adb8c14
MI
1777 * than the desired amount of queues, and even a controller without
1778 * I/O queues can still be used to issue admin commands. This might
749941f2
CH
1779 * be useful to upgrade a buggy firmware for example.
1780 */
1781 return ret >= 0 ? 0 : ret;
b60503ba
MW
1782}
1783
202021c1
SB
1784static ssize_t nvme_cmb_show(struct device *dev,
1785 struct device_attribute *attr,
1786 char *buf)
1787{
1788 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
1789
c965809c 1790 return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n",
202021c1
SB
1791 ndev->cmbloc, ndev->cmbsz);
1792}
1793static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL);
1794
88de4598 1795static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
8ffaadf7 1796{
88de4598
CH
1797 u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
1798
1799 return 1ULL << (12 + 4 * szu);
1800}
1801
1802static u32 nvme_cmb_size(struct nvme_dev *dev)
1803{
1804 return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
1805}
1806
f65efd6d 1807static void nvme_map_cmb(struct nvme_dev *dev)
8ffaadf7 1808{
88de4598 1809 u64 size, offset;
8ffaadf7
JD
1810 resource_size_t bar_size;
1811 struct pci_dev *pdev = to_pci_dev(dev->dev);
8969f1f8 1812 int bar;
8ffaadf7 1813
9fe5c59f
KB
1814 if (dev->cmb_size)
1815 return;
1816
7a67cbea 1817 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
f65efd6d
CH
1818 if (!dev->cmbsz)
1819 return;
202021c1 1820 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
8ffaadf7 1821
88de4598
CH
1822 size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
1823 offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
8969f1f8
CH
1824 bar = NVME_CMB_BIR(dev->cmbloc);
1825 bar_size = pci_resource_len(pdev, bar);
8ffaadf7
JD
1826
1827 if (offset > bar_size)
f65efd6d 1828 return;
8ffaadf7
JD
1829
1830 /*
1831 * Controllers may support a CMB size larger than their BAR,
1832 * for example, due to being behind a bridge. Reduce the CMB to
1833 * the reported size of the BAR
1834 */
1835 if (size > bar_size - offset)
1836 size = bar_size - offset;
1837
0f238ff5
LG
1838 if (pci_p2pdma_add_resource(pdev, bar, size, offset)) {
1839 dev_warn(dev->ctrl.device,
1840 "failed to register the CMB\n");
f65efd6d 1841 return;
0f238ff5
LG
1842 }
1843
8ffaadf7 1844 dev->cmb_size = size;
0f238ff5
LG
1845 dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS);
1846
1847 if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) ==
1848 (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS))
1849 pci_p2pmem_publish(pdev, true);
f65efd6d
CH
1850
1851 if (sysfs_add_file_to_group(&dev->ctrl.device->kobj,
1852 &dev_attr_cmb.attr, NULL))
1853 dev_warn(dev->ctrl.device,
1854 "failed to add sysfs attribute for CMB\n");
8ffaadf7
JD
1855}
1856
1857static inline void nvme_release_cmb(struct nvme_dev *dev)
1858{
0f238ff5 1859 if (dev->cmb_size) {
1c78f773
MG
1860 sysfs_remove_file_from_group(&dev->ctrl.device->kobj,
1861 &dev_attr_cmb.attr, NULL);
0f238ff5 1862 dev->cmb_size = 0;
8ffaadf7
JD
1863 }
1864}
1865
87ad72a5
CH
1866static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1867{
4033f35d 1868 u64 dma_addr = dev->host_mem_descs_dma;
87ad72a5 1869 struct nvme_command c;
87ad72a5
CH
1870 int ret;
1871
87ad72a5
CH
1872 memset(&c, 0, sizeof(c));
1873 c.features.opcode = nvme_admin_set_features;
1874 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1875 c.features.dword11 = cpu_to_le32(bits);
1876 c.features.dword12 = cpu_to_le32(dev->host_mem_size >>
1877 ilog2(dev->ctrl.page_size));
1878 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr));
1879 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr));
1880 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs);
1881
1882 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1883 if (ret) {
1884 dev_warn(dev->ctrl.device,
1885 "failed to set host mem (err %d, flags %#x).\n",
1886 ret, bits);
1887 }
87ad72a5
CH
1888 return ret;
1889}
1890
1891static void nvme_free_host_mem(struct nvme_dev *dev)
1892{
1893 int i;
1894
1895 for (i = 0; i < dev->nr_host_mem_descs; i++) {
1896 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
1897 size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size;
1898
cc667f6d
LD
1899 dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i],
1900 le64_to_cpu(desc->addr),
1901 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
87ad72a5
CH
1902 }
1903
1904 kfree(dev->host_mem_desc_bufs);
1905 dev->host_mem_desc_bufs = NULL;
4033f35d
CH
1906 dma_free_coherent(dev->dev,
1907 dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
1908 dev->host_mem_descs, dev->host_mem_descs_dma);
87ad72a5 1909 dev->host_mem_descs = NULL;
7e5dd57e 1910 dev->nr_host_mem_descs = 0;
87ad72a5
CH
1911}
1912
92dc6895
CH
1913static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
1914 u32 chunk_size)
9d713c2b 1915{
87ad72a5 1916 struct nvme_host_mem_buf_desc *descs;
92dc6895 1917 u32 max_entries, len;
4033f35d 1918 dma_addr_t descs_dma;
2ee0e4ed 1919 int i = 0;
87ad72a5 1920 void **bufs;
6fbcde66 1921 u64 size, tmp;
87ad72a5 1922
87ad72a5
CH
1923 tmp = (preferred + chunk_size - 1);
1924 do_div(tmp, chunk_size);
1925 max_entries = tmp;
044a9df1
CH
1926
1927 if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
1928 max_entries = dev->ctrl.hmmaxd;
1929
750afb08
LC
1930 descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs),
1931 &descs_dma, GFP_KERNEL);
87ad72a5
CH
1932 if (!descs)
1933 goto out;
1934
1935 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
1936 if (!bufs)
1937 goto out_free_descs;
1938
244a8fe4 1939 for (size = 0; size < preferred && i < max_entries; size += len) {
87ad72a5
CH
1940 dma_addr_t dma_addr;
1941
50cdb7c6 1942 len = min_t(u64, chunk_size, preferred - size);
87ad72a5
CH
1943 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
1944 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1945 if (!bufs[i])
1946 break;
1947
1948 descs[i].addr = cpu_to_le64(dma_addr);
1949 descs[i].size = cpu_to_le32(len / dev->ctrl.page_size);
1950 i++;
1951 }
1952
92dc6895 1953 if (!size)
87ad72a5 1954 goto out_free_bufs;
87ad72a5 1955
87ad72a5
CH
1956 dev->nr_host_mem_descs = i;
1957 dev->host_mem_size = size;
1958 dev->host_mem_descs = descs;
4033f35d 1959 dev->host_mem_descs_dma = descs_dma;
87ad72a5
CH
1960 dev->host_mem_desc_bufs = bufs;
1961 return 0;
1962
1963out_free_bufs:
1964 while (--i >= 0) {
1965 size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size;
1966
cc667f6d
LD
1967 dma_free_attrs(dev->dev, size, bufs[i],
1968 le64_to_cpu(descs[i].addr),
1969 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
87ad72a5
CH
1970 }
1971
1972 kfree(bufs);
1973out_free_descs:
4033f35d
CH
1974 dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
1975 descs_dma);
87ad72a5 1976out:
87ad72a5
CH
1977 dev->host_mem_descs = NULL;
1978 return -ENOMEM;
1979}
1980
92dc6895
CH
1981static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
1982{
1983 u32 chunk_size;
1984
1985 /* start big and work our way down */
30f92d62 1986 for (chunk_size = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
044a9df1 1987 chunk_size >= max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
92dc6895
CH
1988 chunk_size /= 2) {
1989 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
1990 if (!min || dev->host_mem_size >= min)
1991 return 0;
1992 nvme_free_host_mem(dev);
1993 }
1994 }
1995
1996 return -ENOMEM;
1997}
1998
9620cfba 1999static int nvme_setup_host_mem(struct nvme_dev *dev)
87ad72a5
CH
2000{
2001 u64 max = (u64)max_host_mem_size_mb * SZ_1M;
2002 u64 preferred = (u64)dev->ctrl.hmpre * 4096;
2003 u64 min = (u64)dev->ctrl.hmmin * 4096;
2004 u32 enable_bits = NVME_HOST_MEM_ENABLE;
6fbcde66 2005 int ret;
87ad72a5
CH
2006
2007 preferred = min(preferred, max);
2008 if (min > max) {
2009 dev_warn(dev->ctrl.device,
2010 "min host memory (%lld MiB) above limit (%d MiB).\n",
2011 min >> ilog2(SZ_1M), max_host_mem_size_mb);
2012 nvme_free_host_mem(dev);
9620cfba 2013 return 0;
87ad72a5
CH
2014 }
2015
2016 /*
2017 * If we already have a buffer allocated check if we can reuse it.
2018 */
2019 if (dev->host_mem_descs) {
2020 if (dev->host_mem_size >= min)
2021 enable_bits |= NVME_HOST_MEM_RETURN;
2022 else
2023 nvme_free_host_mem(dev);
2024 }
2025
2026 if (!dev->host_mem_descs) {
92dc6895
CH
2027 if (nvme_alloc_host_mem(dev, min, preferred)) {
2028 dev_warn(dev->ctrl.device,
2029 "failed to allocate host memory buffer.\n");
9620cfba 2030 return 0; /* controller must work without HMB */
92dc6895
CH
2031 }
2032
2033 dev_info(dev->ctrl.device,
2034 "allocated %lld MiB host memory buffer.\n",
2035 dev->host_mem_size >> ilog2(SZ_1M));
87ad72a5
CH
2036 }
2037
9620cfba
CH
2038 ret = nvme_set_host_mem(dev, enable_bits);
2039 if (ret)
87ad72a5 2040 nvme_free_host_mem(dev);
9620cfba 2041 return ret;
9d713c2b
KB
2042}
2043
c45b1fa2 2044/* irq_queues covers admin queue */
6451fe73 2045static void nvme_calc_io_queues(struct nvme_dev *dev, unsigned int irq_queues)
3b6592f7
JA
2046{
2047 unsigned int this_w_queues = write_queues;
2048
c45b1fa2
ML
2049 WARN_ON(!irq_queues);
2050
3b6592f7 2051 /*
c45b1fa2
ML
2052 * Setup read/write queue split, assign admin queue one independent
2053 * irq vector if irq_queues is > 1.
3b6592f7 2054 */
c45b1fa2 2055 if (irq_queues <= 2) {
e20ba6e1
CH
2056 dev->io_queues[HCTX_TYPE_DEFAULT] = 1;
2057 dev->io_queues[HCTX_TYPE_READ] = 0;
3b6592f7
JA
2058 return;
2059 }
2060
2061 /*
2062 * If 'write_queues' is set, ensure it leaves room for at least
c45b1fa2 2063 * one read queue and one admin queue
3b6592f7 2064 */
6451fe73 2065 if (this_w_queues >= irq_queues)
c45b1fa2 2066 this_w_queues = irq_queues - 2;
3b6592f7
JA
2067
2068 /*
2069 * If 'write_queues' is set to zero, reads and writes will share
2070 * a queue set.
2071 */
2072 if (!this_w_queues) {
c45b1fa2 2073 dev->io_queues[HCTX_TYPE_DEFAULT] = irq_queues - 1;
e20ba6e1 2074 dev->io_queues[HCTX_TYPE_READ] = 0;
3b6592f7 2075 } else {
e20ba6e1 2076 dev->io_queues[HCTX_TYPE_DEFAULT] = this_w_queues;
c45b1fa2 2077 dev->io_queues[HCTX_TYPE_READ] = irq_queues - this_w_queues - 1;
3b6592f7
JA
2078 }
2079}
2080
6451fe73 2081static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues)
3b6592f7
JA
2082{
2083 struct pci_dev *pdev = to_pci_dev(dev->dev);
2084 int irq_sets[2];
2085 struct irq_affinity affd = {
2086 .pre_vectors = 1,
2087 .nr_sets = ARRAY_SIZE(irq_sets),
2088 .sets = irq_sets,
2089 };
30e06628 2090 int result = 0;
6451fe73
JA
2091 unsigned int irq_queues, this_p_queues;
2092
2093 /*
2094 * Poll queues don't need interrupts, but we need at least one IO
2095 * queue left over for non-polled IO.
2096 */
2097 this_p_queues = poll_queues;
2098 if (this_p_queues >= nr_io_queues) {
2099 this_p_queues = nr_io_queues - 1;
2100 irq_queues = 1;
2101 } else {
c45b1fa2 2102 irq_queues = nr_io_queues - this_p_queues + 1;
6451fe73
JA
2103 }
2104 dev->io_queues[HCTX_TYPE_POLL] = this_p_queues;
3b6592f7
JA
2105
2106 /*
2107 * For irq sets, we have to ask for minvec == maxvec. This passes
2108 * any reduction back to us, so we can adjust our queue counts and
2109 * IRQ vector needs.
2110 */
2111 do {
6451fe73 2112 nvme_calc_io_queues(dev, irq_queues);
e20ba6e1
CH
2113 irq_sets[0] = dev->io_queues[HCTX_TYPE_DEFAULT];
2114 irq_sets[1] = dev->io_queues[HCTX_TYPE_READ];
3b6592f7
JA
2115 if (!irq_sets[1])
2116 affd.nr_sets = 1;
2117
2118 /*
db29eb05
JA
2119 * If we got a failure and we're down to asking for just
2120 * 1 + 1 queues, just ask for a single vector. We'll share
2121 * that between the single IO queue and the admin queue.
c45b1fa2 2122 * Otherwise, we assign one independent vector to admin queue.
3b6592f7 2123 */
c45b1fa2 2124 if (irq_queues > 1)
6451fe73 2125 irq_queues = irq_sets[0] + irq_sets[1] + 1;
3b6592f7 2126
6451fe73
JA
2127 result = pci_alloc_irq_vectors_affinity(pdev, irq_queues,
2128 irq_queues,
3b6592f7
JA
2129 PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd);
2130
2131 /*
db29eb05
JA
2132 * Need to reduce our vec counts. If we get ENOSPC, the
2133 * platform should support mulitple vecs, we just need
2134 * to decrease our ask. If we get EINVAL, the platform
2135 * likely does not. Back down to ask for just one vector.
3b6592f7
JA
2136 */
2137 if (result == -ENOSPC) {
6451fe73
JA
2138 irq_queues--;
2139 if (!irq_queues)
3b6592f7
JA
2140 return result;
2141 continue;
db29eb05 2142 } else if (result == -EINVAL) {
6451fe73 2143 irq_queues = 1;
db29eb05 2144 continue;
3b6592f7
JA
2145 } else if (result <= 0)
2146 return -EIO;
2147 break;
2148 } while (1);
2149
2150 return result;
2151}
2152
8fae268b
KB
2153static void nvme_disable_io_queues(struct nvme_dev *dev)
2154{
2155 if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq))
2156 __nvme_disable_io_queues(dev, nvme_admin_delete_cq);
2157}
2158
8d85fce7 2159static int nvme_setup_io_queues(struct nvme_dev *dev)
b60503ba 2160{
147b27e4 2161 struct nvme_queue *adminq = &dev->queues[0];
e75ec752 2162 struct pci_dev *pdev = to_pci_dev(dev->dev);
97f6ef64
XY
2163 int result, nr_io_queues;
2164 unsigned long size;
b60503ba 2165
3b6592f7 2166 nr_io_queues = max_io_queues();
9a0be7ab
CH
2167 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
2168 if (result < 0)
1b23484b 2169 return result;
9a0be7ab 2170
f5fa90dc 2171 if (nr_io_queues == 0)
a5229050 2172 return 0;
4e224106
CH
2173
2174 clear_bit(NVMEQ_ENABLED, &adminq->flags);
b60503ba 2175
0f238ff5 2176 if (dev->cmb_use_sqes) {
8ffaadf7
JD
2177 result = nvme_cmb_qdepth(dev, nr_io_queues,
2178 sizeof(struct nvme_command));
2179 if (result > 0)
2180 dev->q_depth = result;
2181 else
0f238ff5 2182 dev->cmb_use_sqes = false;
8ffaadf7
JD
2183 }
2184
97f6ef64
XY
2185 do {
2186 size = db_bar_size(dev, nr_io_queues);
2187 result = nvme_remap_bar(dev, size);
2188 if (!result)
2189 break;
2190 if (!--nr_io_queues)
2191 return -ENOMEM;
2192 } while (1);
2193 adminq->q_db = dev->dbs;
f1938f6e 2194
8fae268b 2195 retry:
9d713c2b 2196 /* Deregister the admin queue's interrupt */
0ff199cb 2197 pci_free_irq(pdev, 0, adminq);
9d713c2b 2198
e32efbfc
JA
2199 /*
2200 * If we enable msix early due to not intx, disable it again before
2201 * setting up the full range we need.
2202 */
dca51e78 2203 pci_free_irq_vectors(pdev);
3b6592f7
JA
2204
2205 result = nvme_setup_irqs(dev, nr_io_queues);
22b55601 2206 if (result <= 0)
dca51e78 2207 return -EIO;
3b6592f7 2208
22b55601 2209 dev->num_vecs = result;
4b04cc6a 2210 result = max(result - 1, 1);
e20ba6e1 2211 dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL];
fa08a396 2212
063a8096
MW
2213 /*
2214 * Should investigate if there's a performance win from allocating
2215 * more queues than interrupt vectors; it might allow the submission
2216 * path to scale better, even if the receive path is limited by the
2217 * number of interrupts.
2218 */
dca51e78 2219 result = queue_request_irq(adminq);
758dd7fd
JD
2220 if (result) {
2221 adminq->cq_vector = -1;
d4875622 2222 return result;
758dd7fd 2223 }
4e224106 2224 set_bit(NVMEQ_ENABLED, &adminq->flags);
8fae268b
KB
2225
2226 result = nvme_create_io_queues(dev);
2227 if (result || dev->online_queues < 2)
2228 return result;
2229
2230 if (dev->online_queues - 1 < dev->max_qid) {
2231 nr_io_queues = dev->online_queues - 1;
2232 nvme_disable_io_queues(dev);
2233 nvme_suspend_io_queues(dev);
2234 goto retry;
2235 }
2236 dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n",
2237 dev->io_queues[HCTX_TYPE_DEFAULT],
2238 dev->io_queues[HCTX_TYPE_READ],
2239 dev->io_queues[HCTX_TYPE_POLL]);
2240 return 0;
b60503ba
MW
2241}
2242
2a842aca 2243static void nvme_del_queue_end(struct request *req, blk_status_t error)
a5768aa8 2244{
db3cbfff 2245 struct nvme_queue *nvmeq = req->end_io_data;
b5875222 2246
db3cbfff 2247 blk_mq_free_request(req);
d1ed6aa1 2248 complete(&nvmeq->delete_done);
a5768aa8
KB
2249}
2250
2a842aca 2251static void nvme_del_cq_end(struct request *req, blk_status_t error)
a5768aa8 2252{
db3cbfff 2253 struct nvme_queue *nvmeq = req->end_io_data;
a5768aa8 2254
d1ed6aa1
CH
2255 if (error)
2256 set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
db3cbfff
KB
2257
2258 nvme_del_queue_end(req, error);
a5768aa8
KB
2259}
2260
db3cbfff 2261static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
bda4e0fb 2262{
db3cbfff
KB
2263 struct request_queue *q = nvmeq->dev->ctrl.admin_q;
2264 struct request *req;
2265 struct nvme_command cmd;
bda4e0fb 2266
db3cbfff
KB
2267 memset(&cmd, 0, sizeof(cmd));
2268 cmd.delete_queue.opcode = opcode;
2269 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
bda4e0fb 2270
eb71f435 2271 req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
db3cbfff
KB
2272 if (IS_ERR(req))
2273 return PTR_ERR(req);
bda4e0fb 2274
db3cbfff
KB
2275 req->timeout = ADMIN_TIMEOUT;
2276 req->end_io_data = nvmeq;
2277
d1ed6aa1 2278 init_completion(&nvmeq->delete_done);
db3cbfff
KB
2279 blk_execute_rq_nowait(q, NULL, req, false,
2280 opcode == nvme_admin_delete_cq ?
2281 nvme_del_cq_end : nvme_del_queue_end);
2282 return 0;
bda4e0fb
KB
2283}
2284
8fae268b 2285static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode)
a5768aa8 2286{
5271edd4 2287 int nr_queues = dev->online_queues - 1, sent = 0;
db3cbfff 2288 unsigned long timeout;
a5768aa8 2289
db3cbfff 2290 retry:
5271edd4
CH
2291 timeout = ADMIN_TIMEOUT;
2292 while (nr_queues > 0) {
2293 if (nvme_delete_queue(&dev->queues[nr_queues], opcode))
2294 break;
2295 nr_queues--;
2296 sent++;
db3cbfff 2297 }
d1ed6aa1
CH
2298 while (sent) {
2299 struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent];
2300
2301 timeout = wait_for_completion_io_timeout(&nvmeq->delete_done,
5271edd4
CH
2302 timeout);
2303 if (timeout == 0)
2304 return false;
d1ed6aa1
CH
2305
2306 /* handle any remaining CQEs */
2307 if (opcode == nvme_admin_delete_cq &&
2308 !test_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags))
2309 nvme_poll_irqdisable(nvmeq, -1);
2310
2311 sent--;
5271edd4
CH
2312 if (nr_queues)
2313 goto retry;
2314 }
2315 return true;
a5768aa8
KB
2316}
2317
422ef0c7 2318/*
2b1b7e78 2319 * return error value only when tagset allocation failed
422ef0c7 2320 */
8d85fce7 2321static int nvme_dev_add(struct nvme_dev *dev)
b60503ba 2322{
2b1b7e78
JW
2323 int ret;
2324
5bae7f73 2325 if (!dev->ctrl.tagset) {
376f7ef8 2326 dev->tagset.ops = &nvme_mq_ops;
ffe7704d 2327 dev->tagset.nr_hw_queues = dev->online_queues - 1;
ed92ad37
CH
2328 dev->tagset.nr_maps = 2; /* default + read */
2329 if (dev->io_queues[HCTX_TYPE_POLL])
2330 dev->tagset.nr_maps++;
ffe7704d
KB
2331 dev->tagset.timeout = NVME_IO_TIMEOUT;
2332 dev->tagset.numa_node = dev_to_node(dev->dev);
2333 dev->tagset.queue_depth =
a4aea562 2334 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
a7a7cbe3
CK
2335 dev->tagset.cmd_size = nvme_pci_cmd_size(dev, false);
2336 if ((dev->ctrl.sgls & ((1 << 0) | (1 << 1))) && sgl_threshold) {
2337 dev->tagset.cmd_size = max(dev->tagset.cmd_size,
2338 nvme_pci_cmd_size(dev, true));
2339 }
ffe7704d
KB
2340 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2341 dev->tagset.driver_data = dev;
b60503ba 2342
2b1b7e78
JW
2343 ret = blk_mq_alloc_tag_set(&dev->tagset);
2344 if (ret) {
2345 dev_warn(dev->ctrl.device,
2346 "IO queues tagset allocation failed %d\n", ret);
2347 return ret;
2348 }
5bae7f73 2349 dev->ctrl.tagset = &dev->tagset;
f9f38e33
HK
2350
2351 nvme_dbbuf_set(dev);
949928c1
KB
2352 } else {
2353 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2354
2355 /* Free previously allocated queues that are no longer usable */
2356 nvme_free_queues(dev, dev->online_queues);
ffe7704d 2357 }
949928c1 2358
e1e5e564 2359 return 0;
b60503ba
MW
2360}
2361
b00a726a 2362static int nvme_pci_enable(struct nvme_dev *dev)
0877cb0d 2363{
b00a726a 2364 int result = -ENOMEM;
e75ec752 2365 struct pci_dev *pdev = to_pci_dev(dev->dev);
0877cb0d
KB
2366
2367 if (pci_enable_device_mem(pdev))
2368 return result;
2369
0877cb0d 2370 pci_set_master(pdev);
0877cb0d 2371
e75ec752
CH
2372 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) &&
2373 dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32)))
052d0efa 2374 goto disable;
0877cb0d 2375
7a67cbea 2376 if (readl(dev->bar + NVME_REG_CSTS) == -1) {
0e53d180 2377 result = -ENODEV;
b00a726a 2378 goto disable;
0e53d180 2379 }
e32efbfc
JA
2380
2381 /*
a5229050
KB
2382 * Some devices and/or platforms don't advertise or work with INTx
2383 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2384 * adjust this later.
e32efbfc 2385 */
dca51e78
CH
2386 result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
2387 if (result < 0)
2388 return result;
e32efbfc 2389
20d0dfe6 2390 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
7a67cbea 2391
20d0dfe6 2392 dev->q_depth = min_t(int, NVME_CAP_MQES(dev->ctrl.cap) + 1,
b27c1e68 2393 io_queue_depth);
20d0dfe6 2394 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
7a67cbea 2395 dev->dbs = dev->bar + 4096;
1f390c1f
SG
2396
2397 /*
2398 * Temporary fix for the Apple controller found in the MacBook8,1 and
2399 * some MacBook7,1 to avoid controller resets and data loss.
2400 */
2401 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
2402 dev->q_depth = 2;
9bdcfb10
CH
2403 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
2404 "set queue depth=%u to work around controller resets\n",
1f390c1f 2405 dev->q_depth);
d554b5e1
MP
2406 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2407 (pdev->device == 0xa821 || pdev->device == 0xa822) &&
20d0dfe6 2408 NVME_CAP_MQES(dev->ctrl.cap) == 0) {
d554b5e1
MP
2409 dev->q_depth = 64;
2410 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2411 "set queue depth=%u\n", dev->q_depth);
1f390c1f
SG
2412 }
2413
f65efd6d 2414 nvme_map_cmb(dev);
202021c1 2415
a0a3408e
KB
2416 pci_enable_pcie_error_reporting(pdev);
2417 pci_save_state(pdev);
0877cb0d
KB
2418 return 0;
2419
2420 disable:
0877cb0d
KB
2421 pci_disable_device(pdev);
2422 return result;
2423}
2424
2425static void nvme_dev_unmap(struct nvme_dev *dev)
b00a726a
KB
2426{
2427 if (dev->bar)
2428 iounmap(dev->bar);
a1f447b3 2429 pci_release_mem_regions(to_pci_dev(dev->dev));
b00a726a
KB
2430}
2431
2432static void nvme_pci_disable(struct nvme_dev *dev)
0877cb0d 2433{
e75ec752
CH
2434 struct pci_dev *pdev = to_pci_dev(dev->dev);
2435
dca51e78 2436 pci_free_irq_vectors(pdev);
0877cb0d 2437
a0a3408e
KB
2438 if (pci_is_enabled(pdev)) {
2439 pci_disable_pcie_error_reporting(pdev);
e75ec752 2440 pci_disable_device(pdev);
4d115420 2441 }
4d115420
KB
2442}
2443
a5cdb68c 2444static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
b60503ba 2445{
302ad8cc
KB
2446 bool dead = true;
2447 struct pci_dev *pdev = to_pci_dev(dev->dev);
22404274 2448
77bf25ea 2449 mutex_lock(&dev->shutdown_lock);
302ad8cc
KB
2450 if (pci_is_enabled(pdev)) {
2451 u32 csts = readl(dev->bar + NVME_REG_CSTS);
2452
ebef7368
KB
2453 if (dev->ctrl.state == NVME_CTRL_LIVE ||
2454 dev->ctrl.state == NVME_CTRL_RESETTING)
302ad8cc
KB
2455 nvme_start_freeze(&dev->ctrl);
2456 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
2457 pdev->error_state != pci_channel_io_normal);
c9d3bf88 2458 }
c21377f8 2459
302ad8cc
KB
2460 /*
2461 * Give the controller a chance to complete all entered requests if
2462 * doing a safe shutdown.
2463 */
87ad72a5
CH
2464 if (!dead) {
2465 if (shutdown)
2466 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
9a915a5b
JW
2467 }
2468
2469 nvme_stop_queues(&dev->ctrl);
87ad72a5 2470
64ee0ac0 2471 if (!dead && dev->ctrl.queue_count > 0) {
8fae268b 2472 nvme_disable_io_queues(dev);
a5cdb68c 2473 nvme_disable_admin_queue(dev, shutdown);
4d115420 2474 }
8fae268b
KB
2475 nvme_suspend_io_queues(dev);
2476 nvme_suspend_queue(&dev->queues[0]);
b00a726a 2477 nvme_pci_disable(dev);
07836e65 2478
e1958e65
ML
2479 blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
2480 blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
302ad8cc
KB
2481
2482 /*
2483 * The driver will not be starting up queues again if shutting down so
2484 * must flush all entered requests to their failed completion to avoid
2485 * deadlocking blk-mq hot-cpu notifier.
2486 */
2487 if (shutdown)
2488 nvme_start_queues(&dev->ctrl);
77bf25ea 2489 mutex_unlock(&dev->shutdown_lock);
b60503ba
MW
2490}
2491
091b6092
MW
2492static int nvme_setup_prp_pools(struct nvme_dev *dev)
2493{
e75ec752 2494 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
091b6092
MW
2495 PAGE_SIZE, PAGE_SIZE, 0);
2496 if (!dev->prp_page_pool)
2497 return -ENOMEM;
2498
99802a7a 2499 /* Optimisation for I/Os between 4k and 128k */
e75ec752 2500 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
99802a7a
MW
2501 256, 256, 0);
2502 if (!dev->prp_small_pool) {
2503 dma_pool_destroy(dev->prp_page_pool);
2504 return -ENOMEM;
2505 }
091b6092
MW
2506 return 0;
2507}
2508
2509static void nvme_release_prp_pools(struct nvme_dev *dev)
2510{
2511 dma_pool_destroy(dev->prp_page_pool);
99802a7a 2512 dma_pool_destroy(dev->prp_small_pool);
091b6092
MW
2513}
2514
1673f1f0 2515static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
5e82e952 2516{
1673f1f0 2517 struct nvme_dev *dev = to_nvme_dev(ctrl);
9ac27090 2518
f9f38e33 2519 nvme_dbbuf_dma_free(dev);
e75ec752 2520 put_device(dev->dev);
4af0e21c
KB
2521 if (dev->tagset.tags)
2522 blk_mq_free_tag_set(&dev->tagset);
1c63dc66
CH
2523 if (dev->ctrl.admin_q)
2524 blk_put_queue(dev->ctrl.admin_q);
5e82e952 2525 kfree(dev->queues);
e286bcfc 2526 free_opal_dev(dev->ctrl.opal_dev);
943e942e 2527 mempool_destroy(dev->iod_mempool);
5e82e952
KB
2528 kfree(dev);
2529}
2530
f58944e2
KB
2531static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status)
2532{
237045fc 2533 dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status);
f58944e2 2534
d22524a4 2535 nvme_get_ctrl(&dev->ctrl);
69d9a99c 2536 nvme_dev_disable(dev, false);
9f9cafc1 2537 nvme_kill_queues(&dev->ctrl);
03e0f3a6 2538 if (!queue_work(nvme_wq, &dev->remove_work))
f58944e2
KB
2539 nvme_put_ctrl(&dev->ctrl);
2540}
2541
fd634f41 2542static void nvme_reset_work(struct work_struct *work)
5e82e952 2543{
d86c4d8e
CH
2544 struct nvme_dev *dev =
2545 container_of(work, struct nvme_dev, ctrl.reset_work);
a98e58e5 2546 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
f58944e2 2547 int result = -ENODEV;
2b1b7e78 2548 enum nvme_ctrl_state new_state = NVME_CTRL_LIVE;
5e82e952 2549
82b057ca 2550 if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING))
fd634f41 2551 goto out;
5e82e952 2552
fd634f41
CH
2553 /*
2554 * If we're called to reset a live controller first shut it down before
2555 * moving on.
2556 */
b00a726a 2557 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
a5cdb68c 2558 nvme_dev_disable(dev, false);
5e82e952 2559
ad70062c 2560 /*
ad6a0a52 2561 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
ad70062c
JW
2562 * initializing procedure here.
2563 */
ad6a0a52 2564 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
ad70062c 2565 dev_warn(dev->ctrl.device,
ad6a0a52 2566 "failed to mark controller CONNECTING\n");
ad70062c
JW
2567 goto out;
2568 }
2569
b00a726a 2570 result = nvme_pci_enable(dev);
f0b50732 2571 if (result)
3cf519b5 2572 goto out;
f0b50732 2573
01ad0990 2574 result = nvme_pci_configure_admin_queue(dev);
f0b50732 2575 if (result)
f58944e2 2576 goto out;
f0b50732 2577
0fb59cbc
KB
2578 result = nvme_alloc_admin_tags(dev);
2579 if (result)
f58944e2 2580 goto out;
b9afca3e 2581
943e942e
JA
2582 /*
2583 * Limit the max command size to prevent iod->sg allocations going
2584 * over a single page.
2585 */
2586 dev->ctrl.max_hw_sectors = NVME_MAX_KB_SZ << 1;
2587 dev->ctrl.max_segments = NVME_MAX_SEGS;
2588
ce4541f4
CH
2589 result = nvme_init_identify(&dev->ctrl);
2590 if (result)
f58944e2 2591 goto out;
ce4541f4 2592
e286bcfc
SB
2593 if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
2594 if (!dev->ctrl.opal_dev)
2595 dev->ctrl.opal_dev =
2596 init_opal_dev(&dev->ctrl, &nvme_sec_submit);
2597 else if (was_suspend)
2598 opal_unlock_from_suspend(dev->ctrl.opal_dev);
2599 } else {
2600 free_opal_dev(dev->ctrl.opal_dev);
2601 dev->ctrl.opal_dev = NULL;
4f1244c8 2602 }
a98e58e5 2603
f9f38e33
HK
2604 if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) {
2605 result = nvme_dbbuf_dma_alloc(dev);
2606 if (result)
2607 dev_warn(dev->dev,
2608 "unable to allocate dma for dbbuf\n");
2609 }
2610
9620cfba
CH
2611 if (dev->ctrl.hmpre) {
2612 result = nvme_setup_host_mem(dev);
2613 if (result < 0)
2614 goto out;
2615 }
87ad72a5 2616
f0b50732 2617 result = nvme_setup_io_queues(dev);
badc34d4 2618 if (result)
f58944e2 2619 goto out;
f0b50732 2620
2659e57b
CH
2621 /*
2622 * Keep the controller around but remove all namespaces if we don't have
2623 * any working I/O queue.
2624 */
3cf519b5 2625 if (dev->online_queues < 2) {
1b3c47c1 2626 dev_warn(dev->ctrl.device, "IO queues not created\n");
3b24774e 2627 nvme_kill_queues(&dev->ctrl);
5bae7f73 2628 nvme_remove_namespaces(&dev->ctrl);
2b1b7e78 2629 new_state = NVME_CTRL_ADMIN_ONLY;
3cf519b5 2630 } else {
25646264 2631 nvme_start_queues(&dev->ctrl);
302ad8cc 2632 nvme_wait_freeze(&dev->ctrl);
2b1b7e78
JW
2633 /* hit this only when allocate tagset fails */
2634 if (nvme_dev_add(dev))
2635 new_state = NVME_CTRL_ADMIN_ONLY;
302ad8cc 2636 nvme_unfreeze(&dev->ctrl);
3cf519b5
CH
2637 }
2638
2b1b7e78
JW
2639 /*
2640 * If only admin queue live, keep it to do further investigation or
2641 * recovery.
2642 */
2643 if (!nvme_change_ctrl_state(&dev->ctrl, new_state)) {
2644 dev_warn(dev->ctrl.device,
2645 "failed to mark controller state %d\n", new_state);
bb8d261e
CH
2646 goto out;
2647 }
92911a55 2648
d09f2b45 2649 nvme_start_ctrl(&dev->ctrl);
3cf519b5 2650 return;
f0b50732 2651
3cf519b5 2652 out:
f58944e2 2653 nvme_remove_dead_ctrl(dev, result);
f0b50732
KB
2654}
2655
5c8809e6 2656static void nvme_remove_dead_ctrl_work(struct work_struct *work)
9a6b9458 2657{
5c8809e6 2658 struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
e75ec752 2659 struct pci_dev *pdev = to_pci_dev(dev->dev);
9a6b9458
KB
2660
2661 if (pci_get_drvdata(pdev))
921920ab 2662 device_release_driver(&pdev->dev);
1673f1f0 2663 nvme_put_ctrl(&dev->ctrl);
9a6b9458
KB
2664}
2665
1c63dc66 2666static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
9ca97374 2667{
1c63dc66 2668 *val = readl(to_nvme_dev(ctrl)->bar + off);
90667892 2669 return 0;
9ca97374
TH
2670}
2671
5fd4ce1b 2672static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
4cc06521 2673{
5fd4ce1b
CH
2674 writel(val, to_nvme_dev(ctrl)->bar + off);
2675 return 0;
2676}
4cc06521 2677
7fd8930f
CH
2678static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2679{
2680 *val = readq(to_nvme_dev(ctrl)->bar + off);
2681 return 0;
4cc06521
KB
2682}
2683
97c12223
KB
2684static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
2685{
2686 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2687
2688 return snprintf(buf, size, "%s", dev_name(&pdev->dev));
2689}
2690
1c63dc66 2691static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
1a353d85 2692 .name = "pcie",
e439bb12 2693 .module = THIS_MODULE,
e0596ab2
LG
2694 .flags = NVME_F_METADATA_SUPPORTED |
2695 NVME_F_PCI_P2PDMA,
1c63dc66 2696 .reg_read32 = nvme_pci_reg_read32,
5fd4ce1b 2697 .reg_write32 = nvme_pci_reg_write32,
7fd8930f 2698 .reg_read64 = nvme_pci_reg_read64,
1673f1f0 2699 .free_ctrl = nvme_pci_free_ctrl,
f866fc42 2700 .submit_async_event = nvme_pci_submit_async_event,
97c12223 2701 .get_address = nvme_pci_get_address,
1c63dc66 2702};
4cc06521 2703
b00a726a
KB
2704static int nvme_dev_map(struct nvme_dev *dev)
2705{
b00a726a
KB
2706 struct pci_dev *pdev = to_pci_dev(dev->dev);
2707
a1f447b3 2708 if (pci_request_mem_regions(pdev, "nvme"))
b00a726a
KB
2709 return -ENODEV;
2710
97f6ef64 2711 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
b00a726a
KB
2712 goto release;
2713
9fa196e7 2714 return 0;
b00a726a 2715 release:
9fa196e7
MG
2716 pci_release_mem_regions(pdev);
2717 return -ENODEV;
b00a726a
KB
2718}
2719
8427bbc2 2720static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
ff5350a8
AL
2721{
2722 if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
2723 /*
2724 * Several Samsung devices seem to drop off the PCIe bus
2725 * randomly when APST is on and uses the deepest sleep state.
2726 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2727 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2728 * 950 PRO 256GB", but it seems to be restricted to two Dell
2729 * laptops.
2730 */
2731 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
2732 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
2733 dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
2734 return NVME_QUIRK_NO_DEEPEST_PS;
8427bbc2
KHF
2735 } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
2736 /*
2737 * Samsung SSD 960 EVO drops off the PCIe bus after system
467c77d4
JJ
2738 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
2739 * within few minutes after bootup on a Coffee Lake board -
2740 * ASUS PRIME Z370-A
8427bbc2
KHF
2741 */
2742 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
467c77d4
JJ
2743 (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") ||
2744 dmi_match(DMI_BOARD_NAME, "PRIME Z370-A")))
8427bbc2 2745 return NVME_QUIRK_NO_APST;
ff5350a8
AL
2746 }
2747
2748 return 0;
2749}
2750
18119775
KB
2751static void nvme_async_probe(void *data, async_cookie_t cookie)
2752{
2753 struct nvme_dev *dev = data;
80f513b5 2754
18119775
KB
2755 nvme_reset_ctrl_sync(&dev->ctrl);
2756 flush_work(&dev->ctrl.scan_work);
80f513b5 2757 nvme_put_ctrl(&dev->ctrl);
18119775
KB
2758}
2759
8d85fce7 2760static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
b60503ba 2761{
a4aea562 2762 int node, result = -ENOMEM;
b60503ba 2763 struct nvme_dev *dev;
ff5350a8 2764 unsigned long quirks = id->driver_data;
943e942e 2765 size_t alloc_size;
b60503ba 2766
a4aea562
MB
2767 node = dev_to_node(&pdev->dev);
2768 if (node == NUMA_NO_NODE)
2fa84351 2769 set_dev_node(&pdev->dev, first_memory_node);
a4aea562
MB
2770
2771 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
b60503ba
MW
2772 if (!dev)
2773 return -ENOMEM;
147b27e4 2774
3b6592f7
JA
2775 dev->queues = kcalloc_node(max_queue_count(), sizeof(struct nvme_queue),
2776 GFP_KERNEL, node);
b60503ba
MW
2777 if (!dev->queues)
2778 goto free;
2779
e75ec752 2780 dev->dev = get_device(&pdev->dev);
9a6b9458 2781 pci_set_drvdata(pdev, dev);
1c63dc66 2782
b00a726a
KB
2783 result = nvme_dev_map(dev);
2784 if (result)
b00c9b7a 2785 goto put_pci;
b00a726a 2786
d86c4d8e 2787 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
5c8809e6 2788 INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
77bf25ea 2789 mutex_init(&dev->shutdown_lock);
b60503ba 2790
091b6092
MW
2791 result = nvme_setup_prp_pools(dev);
2792 if (result)
b00c9b7a 2793 goto unmap;
4cc06521 2794
8427bbc2 2795 quirks |= check_vendor_combination_bug(pdev);
ff5350a8 2796
943e942e
JA
2797 /*
2798 * Double check that our mempool alloc size will cover the biggest
2799 * command we support.
2800 */
2801 alloc_size = nvme_pci_iod_alloc_size(dev, NVME_MAX_KB_SZ,
2802 NVME_MAX_SEGS, true);
2803 WARN_ON_ONCE(alloc_size > PAGE_SIZE);
2804
2805 dev->iod_mempool = mempool_create_node(1, mempool_kmalloc,
2806 mempool_kfree,
2807 (void *) alloc_size,
2808 GFP_KERNEL, node);
2809 if (!dev->iod_mempool) {
2810 result = -ENOMEM;
2811 goto release_pools;
2812 }
2813
b6e44b4c
KB
2814 result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
2815 quirks);
2816 if (result)
2817 goto release_mempool;
2818
1b3c47c1
SG
2819 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
2820
80f513b5 2821 nvme_get_ctrl(&dev->ctrl);
18119775 2822 async_schedule(nvme_async_probe, dev);
4caff8fc 2823
b60503ba
MW
2824 return 0;
2825
b6e44b4c
KB
2826 release_mempool:
2827 mempool_destroy(dev->iod_mempool);
0877cb0d 2828 release_pools:
091b6092 2829 nvme_release_prp_pools(dev);
b00c9b7a
CJ
2830 unmap:
2831 nvme_dev_unmap(dev);
a96d4f5c 2832 put_pci:
e75ec752 2833 put_device(dev->dev);
b60503ba
MW
2834 free:
2835 kfree(dev->queues);
b60503ba
MW
2836 kfree(dev);
2837 return result;
2838}
2839
775755ed 2840static void nvme_reset_prepare(struct pci_dev *pdev)
f0d54a54 2841{
a6739479 2842 struct nvme_dev *dev = pci_get_drvdata(pdev);
f263fbb8 2843 nvme_dev_disable(dev, false);
775755ed 2844}
f0d54a54 2845
775755ed
CH
2846static void nvme_reset_done(struct pci_dev *pdev)
2847{
f263fbb8 2848 struct nvme_dev *dev = pci_get_drvdata(pdev);
79c48ccf 2849 nvme_reset_ctrl_sync(&dev->ctrl);
f0d54a54
KB
2850}
2851
09ece142
KB
2852static void nvme_shutdown(struct pci_dev *pdev)
2853{
2854 struct nvme_dev *dev = pci_get_drvdata(pdev);
a5cdb68c 2855 nvme_dev_disable(dev, true);
09ece142
KB
2856}
2857
f58944e2
KB
2858/*
2859 * The driver's remove may be called on a device in a partially initialized
2860 * state. This function must not have any dependencies on the device state in
2861 * order to proceed.
2862 */
8d85fce7 2863static void nvme_remove(struct pci_dev *pdev)
b60503ba
MW
2864{
2865 struct nvme_dev *dev = pci_get_drvdata(pdev);
9a6b9458 2866
bb8d261e 2867 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
9a6b9458 2868 pci_set_drvdata(pdev, NULL);
0ff9d4e1 2869
6db28eda 2870 if (!pci_device_is_present(pdev)) {
0ff9d4e1 2871 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
1d39e692 2872 nvme_dev_disable(dev, true);
cb4bfda6 2873 nvme_dev_remove_admin(dev);
6db28eda 2874 }
0ff9d4e1 2875
d86c4d8e 2876 flush_work(&dev->ctrl.reset_work);
d09f2b45
SG
2877 nvme_stop_ctrl(&dev->ctrl);
2878 nvme_remove_namespaces(&dev->ctrl);
a5cdb68c 2879 nvme_dev_disable(dev, true);
9fe5c59f 2880 nvme_release_cmb(dev);
87ad72a5 2881 nvme_free_host_mem(dev);
a4aea562 2882 nvme_dev_remove_admin(dev);
a1a5ef99 2883 nvme_free_queues(dev, 0);
d09f2b45 2884 nvme_uninit_ctrl(&dev->ctrl);
9a6b9458 2885 nvme_release_prp_pools(dev);
b00a726a 2886 nvme_dev_unmap(dev);
1673f1f0 2887 nvme_put_ctrl(&dev->ctrl);
b60503ba
MW
2888}
2889
671a6018 2890#ifdef CONFIG_PM_SLEEP
cd638946
KB
2891static int nvme_suspend(struct device *dev)
2892{
2893 struct pci_dev *pdev = to_pci_dev(dev);
2894 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2895
a5cdb68c 2896 nvme_dev_disable(ndev, true);
cd638946
KB
2897 return 0;
2898}
2899
2900static int nvme_resume(struct device *dev)
2901{
2902 struct pci_dev *pdev = to_pci_dev(dev);
2903 struct nvme_dev *ndev = pci_get_drvdata(pdev);
cd638946 2904
d86c4d8e 2905 nvme_reset_ctrl(&ndev->ctrl);
9a6b9458 2906 return 0;
cd638946 2907}
671a6018 2908#endif
cd638946
KB
2909
2910static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
b60503ba 2911
a0a3408e
KB
2912static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
2913 pci_channel_state_t state)
2914{
2915 struct nvme_dev *dev = pci_get_drvdata(pdev);
2916
2917 /*
2918 * A frozen channel requires a reset. When detected, this method will
2919 * shutdown the controller to quiesce. The controller will be restarted
2920 * after the slot reset through driver's slot_reset callback.
2921 */
a0a3408e
KB
2922 switch (state) {
2923 case pci_channel_io_normal:
2924 return PCI_ERS_RESULT_CAN_RECOVER;
2925 case pci_channel_io_frozen:
d011fb31
KB
2926 dev_warn(dev->ctrl.device,
2927 "frozen state error detected, reset controller\n");
a5cdb68c 2928 nvme_dev_disable(dev, false);
a0a3408e
KB
2929 return PCI_ERS_RESULT_NEED_RESET;
2930 case pci_channel_io_perm_failure:
d011fb31
KB
2931 dev_warn(dev->ctrl.device,
2932 "failure state error detected, request disconnect\n");
a0a3408e
KB
2933 return PCI_ERS_RESULT_DISCONNECT;
2934 }
2935 return PCI_ERS_RESULT_NEED_RESET;
2936}
2937
2938static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
2939{
2940 struct nvme_dev *dev = pci_get_drvdata(pdev);
2941
1b3c47c1 2942 dev_info(dev->ctrl.device, "restart after slot reset\n");
a0a3408e 2943 pci_restore_state(pdev);
d86c4d8e 2944 nvme_reset_ctrl(&dev->ctrl);
a0a3408e
KB
2945 return PCI_ERS_RESULT_RECOVERED;
2946}
2947
2948static void nvme_error_resume(struct pci_dev *pdev)
2949{
72cd4cc2
KB
2950 struct nvme_dev *dev = pci_get_drvdata(pdev);
2951
2952 flush_work(&dev->ctrl.reset_work);
a0a3408e
KB
2953}
2954
1d352035 2955static const struct pci_error_handlers nvme_err_handler = {
b60503ba 2956 .error_detected = nvme_error_detected,
b60503ba
MW
2957 .slot_reset = nvme_slot_reset,
2958 .resume = nvme_error_resume,
775755ed
CH
2959 .reset_prepare = nvme_reset_prepare,
2960 .reset_done = nvme_reset_done,
b60503ba
MW
2961};
2962
6eb0d698 2963static const struct pci_device_id nvme_id_table[] = {
106198ed 2964 { PCI_VDEVICE(INTEL, 0x0953),
08095e70 2965 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 2966 NVME_QUIRK_DEALLOCATE_ZEROES, },
99466e70
KB
2967 { PCI_VDEVICE(INTEL, 0x0a53),
2968 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 2969 NVME_QUIRK_DEALLOCATE_ZEROES, },
99466e70
KB
2970 { PCI_VDEVICE(INTEL, 0x0a54),
2971 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 2972 NVME_QUIRK_DEALLOCATE_ZEROES, },
f99cb7af
DWF
2973 { PCI_VDEVICE(INTEL, 0x0a55),
2974 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2975 NVME_QUIRK_DEALLOCATE_ZEROES, },
50af47d0 2976 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */
9abd68ef
JA
2977 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
2978 NVME_QUIRK_MEDIUM_PRIO_SQ },
6299358d
JD
2979 { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */
2980 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
540c801c
KB
2981 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */
2982 .driver_data = NVME_QUIRK_IDENTIFY_CNS, },
0302ae60
MP
2983 { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */
2984 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
54adc010
GP
2985 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
2986 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
8c97eecc
JL
2987 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */
2988 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
015282c9
WW
2989 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
2990 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
d554b5e1
MP
2991 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */
2992 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2993 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */
2994 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
608cc4b1
CH
2995 { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */
2996 .driver_data = NVME_QUIRK_LIGHTNVM, },
2997 { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */
2998 .driver_data = NVME_QUIRK_LIGHTNVM, },
ea48e877
WX
2999 { PCI_DEVICE(0x1d1d, 0x2601), /* CNEX Granby */
3000 .driver_data = NVME_QUIRK_LIGHTNVM, },
b60503ba 3001 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
c74dc780 3002 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) },
124298bd 3003 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
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MW
3004 { 0, }
3005};
3006MODULE_DEVICE_TABLE(pci, nvme_id_table);
3007
3008static struct pci_driver nvme_driver = {
3009 .name = "nvme",
3010 .id_table = nvme_id_table,
3011 .probe = nvme_probe,
8d85fce7 3012 .remove = nvme_remove,
09ece142 3013 .shutdown = nvme_shutdown,
cd638946
KB
3014 .driver = {
3015 .pm = &nvme_dev_pm_ops,
3016 },
74d986ab 3017 .sriov_configure = pci_sriov_configure_simple,
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MW
3018 .err_handler = &nvme_err_handler,
3019};
3020
3021static int __init nvme_init(void)
3022{
9a6327d2 3023 return pci_register_driver(&nvme_driver);
b60503ba
MW
3024}
3025
3026static void __exit nvme_exit(void)
3027{
3028 pci_unregister_driver(&nvme_driver);
03e0f3a6 3029 flush_workqueue(nvme_wq);
21bd78bc 3030 _nvme_check_size();
b60503ba
MW
3031}
3032
3033MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3034MODULE_LICENSE("GPL");
c78b4713 3035MODULE_VERSION("1.0");
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MW
3036module_init(nvme_init);
3037module_exit(nvme_exit);