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nvme: code command_id with a genctr for use-after-free validation
[linux-2.6-block.git] / drivers / nvme / host / pci.c
CommitLineData
5f37396d 1// SPDX-License-Identifier: GPL-2.0
b60503ba
MW		 2/*
3 * NVM Express device driver
6eb0d698 4 * Copyright (c) 2011-2014, Intel Corporation.
b60503ba
MW		 5 */
6
df4f9bc4 7#include <linux/acpi.h>
a0a3408e 8#include <linux/aer.h>
18119775 9#include <linux/async.h>
b60503ba 10#include <linux/blkdev.h>
a4aea562 11#include <linux/blk-mq.h>
dca51e78 12#include <linux/blk-mq-pci.h>
ff5350a8 13#include <linux/dmi.h>
b60503ba
MW		 14#include <linux/init.h>
15#include <linux/interrupt.h>
16#include <linux/io.h>
b60503ba
MW		 17#include <linux/mm.h>
18#include <linux/module.h>
77bf25ea 19#include <linux/mutex.h>
d0877473 20#include <linux/once.h>
b60503ba 21#include <linux/pci.h>
d916b1be 22#include <linux/suspend.h>
e1e5e564 23#include <linux/t10-pi.h>
b60503ba 24#include <linux/types.h>
2f8e2c87 25#include <linux/io-64-nonatomic-lo-hi.h>
20d3bb92 26#include <linux/io-64-nonatomic-hi-lo.h>
a98e58e5 27#include <linux/sed-opal.h>
0f238ff5 28#include <linux/pci-p2pdma.h>
797a796a 29
604c01d5 30#include "trace.h"
f11bb3e2
CH		 31#include "nvme.h"
32
c1e0cc7e 33#define SQ_SIZE(q) ((q)->q_depth << (q)->sqes)
8a1d09a6 34#define CQ_SIZE(q) ((q)->q_depth * sizeof(struct nvme_completion))
c965809c 35
a7a7cbe3 36#define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc))
9d43cf64 37
943e942e
JA		 38/*
39 * These can be higher, but we need to ensure that any command doesn't
40 * require an sg allocation that needs more than a page of data.
41 */
42#define NVME_MAX_KB_SZ 4096
43#define NVME_MAX_SEGS 127
44
58ffacb5
MW		 45static int use_threaded_interrupts;
46module_param(use_threaded_interrupts, int, 0);
47
8ffaadf7 48static bool use_cmb_sqes = true;
69f4eb9f 49module_param(use_cmb_sqes, bool, 0444);
8ffaadf7
JD		 50MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
51
87ad72a5
CH		 52static unsigned int max_host_mem_size_mb = 128;
53module_param(max_host_mem_size_mb, uint, 0444);
54MODULE_PARM_DESC(max_host_mem_size_mb,
55 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
1fa6aead 56
a7a7cbe3
CK		 57static unsigned int sgl_threshold = SZ_32K;
58module_param(sgl_threshold, uint, 0644);
59MODULE_PARM_DESC(sgl_threshold,
60 "Use SGLs when average request segment size is larger or equal to "
61 "this size. Use 0 to disable SGLs.");
62
27453b45
SG		 63#define NVME_PCI_MIN_QUEUE_SIZE 2
64#define NVME_PCI_MAX_QUEUE_SIZE 4095
b27c1e68 65static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
66static const struct kernel_param_ops io_queue_depth_ops = {
67 .set = io_queue_depth_set,
61f3b896 68 .get = param_get_uint,
b27c1e68 69};
70
61f3b896 71static unsigned int io_queue_depth = 1024;
b27c1e68 72module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
27453b45 73MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2 and < 4096");
b27c1e68 74
9c9e76d5
WZ		 75static int io_queue_count_set(const char *val, const struct kernel_param *kp)
76{
77 unsigned int n;
78 int ret;
79
80 ret = kstrtouint(val, 10, &n);
81 if (ret != 0 || n > num_possible_cpus())
82 return -EINVAL;
83 return param_set_uint(val, kp);
84}
85
86static const struct kernel_param_ops io_queue_count_ops = {
87 .set = io_queue_count_set,
88 .get = param_get_uint,
89};
90
3f68baf7 91static unsigned int write_queues;
9c9e76d5 92module_param_cb(write_queues, &io_queue_count_ops, &write_queues, 0644);
3b6592f7
JA		 93MODULE_PARM_DESC(write_queues,
94 "Number of queues to use for writes. If not set, reads and writes "
95 "will share a queue set.");
96
3f68baf7 97static unsigned int poll_queues;
9c9e76d5 98module_param_cb(poll_queues, &io_queue_count_ops, &poll_queues, 0644);
4b04cc6a
JA		 99MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO.");
100
df4f9bc4
DB		 101static bool noacpi;
102module_param(noacpi, bool, 0444);
103MODULE_PARM_DESC(noacpi, "disable acpi bios quirks");
104
1c63dc66
CH		 105struct nvme_dev;
106struct nvme_queue;
b3fffdef 107
a5cdb68c 108static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
8fae268b 109static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode);
d4b4ff8e 110
1c63dc66
CH		 111/*
112 * Represents an NVM Express device. Each nvme_dev is a PCI function.
113 */
114struct nvme_dev {
147b27e4 115 struct nvme_queue *queues;
1c63dc66
CH		 116 struct blk_mq_tag_set tagset;
117 struct blk_mq_tag_set admin_tagset;
118 u32 __iomem *dbs;
119 struct device *dev;
120 struct dma_pool *prp_page_pool;
121 struct dma_pool *prp_small_pool;
1c63dc66
CH		 122 unsigned online_queues;
123 unsigned max_qid;
e20ba6e1 124 unsigned io_queues[HCTX_MAX_TYPES];
22b55601 125 unsigned int num_vecs;
7442ddce 126 u32 q_depth;
c1e0cc7e 127 int io_sqes;
1c63dc66 128 u32 db_stride;
1c63dc66 129 void __iomem *bar;
97f6ef64 130 unsigned long bar_mapped_size;
5c8809e6 131 struct work_struct remove_work;
77bf25ea 132 struct mutex shutdown_lock;
1c63dc66 133 bool subsystem;
1c63dc66 134 u64 cmb_size;
0f238ff5 135 bool cmb_use_sqes;
1c63dc66 136 u32 cmbsz;
202021c1 137 u32 cmbloc;
1c63dc66 138 struct nvme_ctrl ctrl;
d916b1be 139 u32 last_ps;
87ad72a5 140
943e942e
JA		 141 mempool_t *iod_mempool;
142
87ad72a5 143 /* shadow doorbell buffer support: */
f9f38e33
HK		 144 u32 *dbbuf_dbs;
145 dma_addr_t dbbuf_dbs_dma_addr;
146 u32 *dbbuf_eis;
147 dma_addr_t dbbuf_eis_dma_addr;
87ad72a5
CH		 148
149 /* host memory buffer support: */
150 u64 host_mem_size;
151 u32 nr_host_mem_descs;
4033f35d 152 dma_addr_t host_mem_descs_dma;
87ad72a5
CH		 153 struct nvme_host_mem_buf_desc *host_mem_descs;
154 void **host_mem_desc_bufs;
2a5bcfdd
WZ		 155 unsigned int nr_allocated_queues;
156 unsigned int nr_write_queues;
157 unsigned int nr_poll_queues;
4d115420 158};
1fa6aead 159
b27c1e68 160static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
161{
27453b45
SG		 162 return param_set_uint_minmax(val, kp, NVME_PCI_MIN_QUEUE_SIZE,
163 NVME_PCI_MAX_QUEUE_SIZE);
b27c1e68 164}
165
f9f38e33
HK		 166static inline unsigned int sq_idx(unsigned int qid, u32 stride)
167{
168 return qid * 2 * stride;
169}
170
171static inline unsigned int cq_idx(unsigned int qid, u32 stride)
172{
173 return (qid * 2 + 1) * stride;
174}
175
1c63dc66
CH		 176static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
177{
178 return container_of(ctrl, struct nvme_dev, ctrl);
179}
180
b60503ba
MW		 181/*
182 * An NVM Express queue. Each device has at least two (one for admin
183 * commands and one for I/O commands).
184 */
185struct nvme_queue {
091b6092 186 struct nvme_dev *dev;
1ab0cd69 187 spinlock_t sq_lock;
c1e0cc7e 188 void *sq_cmds;
3a7afd8e
CH		 189 /* only used for poll queues: */
190 spinlock_t cq_poll_lock ____cacheline_aligned_in_smp;
74943d45 191 struct nvme_completion *cqes;
b60503ba
MW		 192 dma_addr_t sq_dma_addr;
193 dma_addr_t cq_dma_addr;
b60503ba 194 u32 __iomem *q_db;
7442ddce 195 u32 q_depth;
7c349dde 196 u16 cq_vector;
b60503ba 197 u16 sq_tail;
38210800 198 u16 last_sq_tail;
b60503ba 199 u16 cq_head;
c30341dc 200 u16 qid;
e9539f47 201 u8 cq_phase;
c1e0cc7e 202 u8 sqes;
4e224106
CH		 203 unsigned long flags;
204#define NVMEQ_ENABLED 0
63223078 205#define NVMEQ_SQ_CMB 1
d1ed6aa1 206#define NVMEQ_DELETE_ERROR 2
7c349dde 207#define NVMEQ_POLLED 3
f9f38e33
HK		 208 u32 *dbbuf_sq_db;
209 u32 *dbbuf_cq_db;
210 u32 *dbbuf_sq_ei;
211 u32 *dbbuf_cq_ei;
d1ed6aa1 212 struct completion delete_done;
b60503ba
MW		 213};
214
71bd150c 215/*
9b048119
CH		 216 * The nvme_iod describes the data in an I/O.
217 *
218 * The sg pointer contains the list of PRP/SGL chunk allocations in addition
219 * to the actual struct scatterlist.
71bd150c
CH		 220 */
221struct nvme_iod {
d49187e9 222 struct nvme_request req;
af7fae85 223 struct nvme_command cmd;
f4800d6d 224 struct nvme_queue *nvmeq;
a7a7cbe3 225 bool use_sgl;
f4800d6d 226 int aborted;
71bd150c 227 int npages; /* In the PRP list. 0 means small pool in use */
71bd150c 228 int nents; /* Used in scatterlist */
71bd150c 229 dma_addr_t first_dma;
dff824b2 230 unsigned int dma_len; /* length of single DMA segment mapping */
783b94bd 231 dma_addr_t meta_dma;
f4800d6d 232 struct scatterlist *sg;
b60503ba
MW		 233};
234
2a5bcfdd 235static inline unsigned int nvme_dbbuf_size(struct nvme_dev *dev)
3b6592f7 236{
2a5bcfdd 237 return dev->nr_allocated_queues * 8 * dev->db_stride;
f9f38e33
HK		 238}
239
240static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
241{
2a5bcfdd 242 unsigned int mem_size = nvme_dbbuf_size(dev);
f9f38e33
HK		 243
244 if (dev->dbbuf_dbs)
245 return 0;
246
247 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
248 &dev->dbbuf_dbs_dma_addr,
249 GFP_KERNEL);
250 if (!dev->dbbuf_dbs)
251 return -ENOMEM;
252 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
253 &dev->dbbuf_eis_dma_addr,
254 GFP_KERNEL);
255 if (!dev->dbbuf_eis) {
256 dma_free_coherent(dev->dev, mem_size,
257 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
258 dev->dbbuf_dbs = NULL;
259 return -ENOMEM;
260 }
261
262 return 0;
263}
264
265static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
266{
2a5bcfdd 267 unsigned int mem_size = nvme_dbbuf_size(dev);
f9f38e33
HK		 268
269 if (dev->dbbuf_dbs) {
270 dma_free_coherent(dev->dev, mem_size,
271 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
272 dev->dbbuf_dbs = NULL;
273 }
274 if (dev->dbbuf_eis) {
275 dma_free_coherent(dev->dev, mem_size,
276 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
277 dev->dbbuf_eis = NULL;
278 }
279}
280
281static void nvme_dbbuf_init(struct nvme_dev *dev,
282 struct nvme_queue *nvmeq, int qid)
283{
284 if (!dev->dbbuf_dbs || !qid)
285 return;
286
287 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
288 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
289 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
290 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
291}
292
0f0d2c87
MI		 293static void nvme_dbbuf_free(struct nvme_queue *nvmeq)
294{
295 if (!nvmeq->qid)
296 return;
297
298 nvmeq->dbbuf_sq_db = NULL;
299 nvmeq->dbbuf_cq_db = NULL;
300 nvmeq->dbbuf_sq_ei = NULL;
301 nvmeq->dbbuf_cq_ei = NULL;
302}
303
f9f38e33
HK		 304static void nvme_dbbuf_set(struct nvme_dev *dev)
305{
f66e2804 306 struct nvme_command c = { };
0f0d2c87 307 unsigned int i;
f9f38e33
HK		 308
309 if (!dev->dbbuf_dbs)
310 return;
311
f9f38e33
HK		 312 c.dbbuf.opcode = nvme_admin_dbbuf;
313 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
314 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
315
316 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
9bdcfb10 317 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
f9f38e33
HK		 318 /* Free memory and continue on */
319 nvme_dbbuf_dma_free(dev);
0f0d2c87
MI		 320
321 for (i = 1; i <= dev->online_queues; i++)
322 nvme_dbbuf_free(&dev->queues[i]);
f9f38e33
HK		 323 }
324}
325
326static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
327{
328 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
329}
330
331/* Update dbbuf and return true if an MMIO is required */
332static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
333 volatile u32 *dbbuf_ei)
334{
335 if (dbbuf_db) {
336 u16 old_value;
337
338 /*
339 * Ensure that the queue is written before updating
340 * the doorbell in memory
341 */
342 wmb();
343
344 old_value = *dbbuf_db;
345 *dbbuf_db = value;
346
f1ed3df2
MW		 347 /*
348 * Ensure that the doorbell is updated before reading the event
349 * index from memory. The controller needs to provide similar
350 * ordering to ensure the envent index is updated before reading
351 * the doorbell.
352 */
353 mb();
354
f9f38e33
HK		 355 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value))
356 return false;
357 }
358
359 return true;
b60503ba
MW		 360}
361
ac3dd5bd
JA		 362/*
363 * Will slightly overestimate the number of pages needed. This is OK
364 * as it only leads to a small amount of wasted memory for the lifetime of
365 * the I/O.
366 */
b13c6393 367static int nvme_pci_npages_prp(void)
ac3dd5bd 368{
b13c6393 369 unsigned nprps = DIV_ROUND_UP(NVME_MAX_KB_SZ + NVME_CTRL_PAGE_SIZE,
6c3c05b0 370 NVME_CTRL_PAGE_SIZE);
ac3dd5bd
JA		 371 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
372}
373
a7a7cbe3
CK		 374/*
375 * Calculates the number of pages needed for the SGL segments. For example a 4k
376 * page can accommodate 256 SGL descriptors.
377 */
b13c6393 378static int nvme_pci_npages_sgl(void)
ac3dd5bd 379{
b13c6393
CK		 380 return DIV_ROUND_UP(NVME_MAX_SEGS * sizeof(struct nvme_sgl_desc),
381 PAGE_SIZE);
f4800d6d 382}
ac3dd5bd 383
b13c6393 384static size_t nvme_pci_iod_alloc_size(void)
f4800d6d 385{
b13c6393 386 size_t npages = max(nvme_pci_npages_prp(), nvme_pci_npages_sgl());
a7a7cbe3 387
b13c6393
CK		 388 return sizeof(__le64 *) * npages +
389 sizeof(struct scatterlist) * NVME_MAX_SEGS;
f4800d6d 390}
ac3dd5bd 391
a4aea562
MB		 392static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
393 unsigned int hctx_idx)
e85248e5 394{
a4aea562 395 struct nvme_dev *dev = data;
147b27e4 396 struct nvme_queue *nvmeq = &dev->queues[0];
a4aea562 397
42483228
KB		 398 WARN_ON(hctx_idx != 0);
399 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
42483228 400
a4aea562
MB		 401 hctx->driver_data = nvmeq;
402 return 0;
e85248e5
MW		 403}
404
a4aea562
MB		 405static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
406 unsigned int hctx_idx)
b60503ba 407{
a4aea562 408 struct nvme_dev *dev = data;
147b27e4 409 struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
a4aea562 410
42483228 411 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
a4aea562
MB		 412 hctx->driver_data = nvmeq;
413 return 0;
b60503ba
MW		 414}
415
d6296d39
CH		 416static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req,
417 unsigned int hctx_idx, unsigned int numa_node)
b60503ba 418{
d6296d39 419 struct nvme_dev *dev = set->driver_data;
f4800d6d 420 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
0350815a 421 int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0;
147b27e4 422 struct nvme_queue *nvmeq = &dev->queues[queue_idx];
a4aea562
MB		 423
424 BUG_ON(!nvmeq);
f4800d6d 425 iod->nvmeq = nvmeq;
59e29ce6
SG		 426
427 nvme_req(req)->ctrl = &dev->ctrl;
f4b9e6c9 428 nvme_req(req)->cmd = &iod->cmd;
a4aea562
MB		 429 return 0;
430}
431
3b6592f7
JA		 432static int queue_irq_offset(struct nvme_dev *dev)
433{
434 /* if we have more than 1 vec, admin queue offsets us by 1 */
435 if (dev->num_vecs > 1)
436 return 1;
437
438 return 0;
439}
440
dca51e78
CH		 441static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
442{
443 struct nvme_dev *dev = set->driver_data;
3b6592f7
JA		 444 int i, qoff, offset;
445
446 offset = queue_irq_offset(dev);
447 for (i = 0, qoff = 0; i < set->nr_maps; i++) {
448 struct blk_mq_queue_map *map = &set->map[i];
449
450 map->nr_queues = dev->io_queues[i];
451 if (!map->nr_queues) {
e20ba6e1 452 BUG_ON(i == HCTX_TYPE_DEFAULT);
7e849dd9 453 continue;
3b6592f7
JA		 454 }
455
4b04cc6a
JA		 456 /*
457 * The poll queue(s) doesn't have an IRQ (and hence IRQ
458 * affinity), so use the regular blk-mq cpu mapping
459 */
3b6592f7 460 map->queue_offset = qoff;
cb9e0e50 461 if (i != HCTX_TYPE_POLL && offset)
4b04cc6a
JA		 462 blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset);
463 else
464 blk_mq_map_queues(map);
3b6592f7
JA		 465 qoff += map->nr_queues;
466 offset += map->nr_queues;
467 }
468
469 return 0;
dca51e78
CH		 470}
471
38210800
KB		 472/*
473 * Write sq tail if we are asked to, or if the next command would wrap.
474 */
475static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq)
04f3eafd 476{
38210800
KB		 477 if (!write_sq) {
478 u16 next_tail = nvmeq->sq_tail + 1;
479
480 if (next_tail == nvmeq->q_depth)
481 next_tail = 0;
482 if (next_tail != nvmeq->last_sq_tail)
483 return;
484 }
485
04f3eafd
JA		 486 if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail,
487 nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei))
488 writel(nvmeq->sq_tail, nvmeq->q_db);
38210800 489 nvmeq->last_sq_tail = nvmeq->sq_tail;
04f3eafd
JA		 490}
491
b60503ba 492/**
90ea5ca4 493 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
b60503ba
MW		 494 * @nvmeq: The queue to use
495 * @cmd: The command to send
04f3eafd 496 * @write_sq: whether to write to the SQ doorbell
b60503ba 497 */
04f3eafd
JA		 498static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd,
499 bool write_sq)
b60503ba 500{
90ea5ca4 501 spin_lock(&nvmeq->sq_lock);
c1e0cc7e
BH		 502 memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes),
503 cmd, sizeof(*cmd));
90ea5ca4
CH		 504 if (++nvmeq->sq_tail == nvmeq->q_depth)
505 nvmeq->sq_tail = 0;
38210800 506 nvme_write_sq_db(nvmeq, write_sq);
04f3eafd
JA		 507 spin_unlock(&nvmeq->sq_lock);
508}
509
510static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx)
511{
512 struct nvme_queue *nvmeq = hctx->driver_data;
513
514 spin_lock(&nvmeq->sq_lock);
38210800
KB		 515 if (nvmeq->sq_tail != nvmeq->last_sq_tail)
516 nvme_write_sq_db(nvmeq, true);
90ea5ca4 517 spin_unlock(&nvmeq->sq_lock);
b60503ba
MW		 518}
519
a7a7cbe3 520static void **nvme_pci_iod_list(struct request *req)
b60503ba 521{
f4800d6d 522 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3 523 return (void **)(iod->sg + blk_rq_nr_phys_segments(req));
b60503ba
MW		 524}
525
955b1b5a
MI		 526static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req)
527{
528 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
20469a37 529 int nseg = blk_rq_nr_phys_segments(req);
955b1b5a
MI		 530 unsigned int avg_seg_size;
531
20469a37 532 avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
955b1b5a 533
253a0b76 534 if (!nvme_ctrl_sgl_supported(&dev->ctrl))
955b1b5a
MI		 535 return false;
536 if (!iod->nvmeq->qid)
537 return false;
538 if (!sgl_threshold || avg_seg_size < sgl_threshold)
539 return false;
540 return true;
541}
542
9275c206 543static void nvme_free_prps(struct nvme_dev *dev, struct request *req)
b60503ba 544{
6c3c05b0 545 const int last_prp = NVME_CTRL_PAGE_SIZE / sizeof(__le64) - 1;
9275c206
CH		 546 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
547 dma_addr_t dma_addr = iod->first_dma;
eca18b23 548 int i;
eca18b23 549
9275c206
CH		 550 for (i = 0; i < iod->npages; i++) {
551 __le64 *prp_list = nvme_pci_iod_list(req)[i];
552 dma_addr_t next_dma_addr = le64_to_cpu(prp_list[last_prp]);
553
554 dma_pool_free(dev->prp_page_pool, prp_list, dma_addr);
555 dma_addr = next_dma_addr;
7fe07d14 556 }
9275c206 557}
dff824b2 558
9275c206
CH		 559static void nvme_free_sgls(struct nvme_dev *dev, struct request *req)
560{
561 const int last_sg = SGES_PER_PAGE - 1;
562 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
563 dma_addr_t dma_addr = iod->first_dma;
564 int i;
dff824b2 565
9275c206
CH		 566 for (i = 0; i < iod->npages; i++) {
567 struct nvme_sgl_desc *sg_list = nvme_pci_iod_list(req)[i];
568 dma_addr_t next_dma_addr = le64_to_cpu((sg_list[last_sg]).addr);
dff824b2 569
9275c206
CH		 570 dma_pool_free(dev->prp_page_pool, sg_list, dma_addr);
571 dma_addr = next_dma_addr;
572 }
9275c206 573}
a7a7cbe3 574
9275c206
CH		 575static void nvme_unmap_sg(struct nvme_dev *dev, struct request *req)
576{
577 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3 578
9275c206
CH		 579 if (is_pci_p2pdma_page(sg_page(iod->sg)))
580 pci_p2pdma_unmap_sg(dev->dev, iod->sg, iod->nents,
581 rq_dma_dir(req));
582 else
583 dma_unmap_sg(dev->dev, iod->sg, iod->nents, rq_dma_dir(req));
584}
a7a7cbe3 585
9275c206
CH		 586static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
587{
588 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3 589
9275c206
CH		 590 if (iod->dma_len) {
591 dma_unmap_page(dev->dev, iod->first_dma, iod->dma_len,
592 rq_dma_dir(req));
593 return;
eca18b23 594 }
ac3dd5bd 595
9275c206
CH		 596 WARN_ON_ONCE(!iod->nents);
597
598 nvme_unmap_sg(dev, req);
599 if (iod->npages == 0)
600 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0],
601 iod->first_dma);
602 else if (iod->use_sgl)
603 nvme_free_sgls(dev, req);
604 else
605 nvme_free_prps(dev, req);
d43f1ccf 606 mempool_free(iod->sg, dev->iod_mempool);
b4ff9c8d
KB		 607}
608
d0877473
KB		 609static void nvme_print_sgl(struct scatterlist *sgl, int nents)
610{
611 int i;
612 struct scatterlist *sg;
613
614 for_each_sg(sgl, sg, nents, i) {
615 dma_addr_t phys = sg_phys(sg);
616 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
617 "dma_address:%pad dma_length:%d\n",
618 i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
619 sg_dma_len(sg));
620 }
621}
622
a7a7cbe3
CK		 623static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
624 struct request *req, struct nvme_rw_command *cmnd)
ff22b54f 625{
f4800d6d 626 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
99802a7a 627 struct dma_pool *pool;
b131c61d 628 int length = blk_rq_payload_bytes(req);
eca18b23 629 struct scatterlist *sg = iod->sg;
ff22b54f
MW		 630 int dma_len = sg_dma_len(sg);
631 u64 dma_addr = sg_dma_address(sg);
6c3c05b0 632 int offset = dma_addr & (NVME_CTRL_PAGE_SIZE - 1);
e025344c 633 __le64 *prp_list;
a7a7cbe3 634 void **list = nvme_pci_iod_list(req);
e025344c 635 dma_addr_t prp_dma;
eca18b23 636 int nprps, i;
ff22b54f 637
6c3c05b0 638 length -= (NVME_CTRL_PAGE_SIZE - offset);
5228b328
JS		 639 if (length <= 0) {
640 iod->first_dma = 0;
a7a7cbe3 641 goto done;
5228b328 642 }
ff22b54f 643
6c3c05b0 644 dma_len -= (NVME_CTRL_PAGE_SIZE - offset);
ff22b54f 645 if (dma_len) {
6c3c05b0 646 dma_addr += (NVME_CTRL_PAGE_SIZE - offset);
ff22b54f
MW		 647 } else {
648 sg = sg_next(sg);
649 dma_addr = sg_dma_address(sg);
650 dma_len = sg_dma_len(sg);
651 }
652
6c3c05b0 653 if (length <= NVME_CTRL_PAGE_SIZE) {
edd10d33 654 iod->first_dma = dma_addr;
a7a7cbe3 655 goto done;
e025344c
SMM		 656 }
657
6c3c05b0 658 nprps = DIV_ROUND_UP(length, NVME_CTRL_PAGE_SIZE);
99802a7a
MW		 659 if (nprps <= (256 / 8)) {
660 pool = dev->prp_small_pool;
eca18b23 661 iod->npages = 0;
99802a7a
MW		 662 } else {
663 pool = dev->prp_page_pool;
eca18b23 664 iod->npages = 1;
99802a7a
MW		 665 }
666
69d2b571 667 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
b77954cb 668 if (!prp_list) {
edd10d33 669 iod->first_dma = dma_addr;
eca18b23 670 iod->npages = -1;
86eea289 671 return BLK_STS_RESOURCE;
b77954cb 672 }
eca18b23
MW		 673 list[0] = prp_list;
674 iod->first_dma = prp_dma;
e025344c
SMM		 675 i = 0;
676 for (;;) {
6c3c05b0 677 if (i == NVME_CTRL_PAGE_SIZE >> 3) {
e025344c 678 __le64 *old_prp_list = prp_list;
69d2b571 679 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
eca18b23 680 if (!prp_list)
fa073216 681 goto free_prps;
eca18b23 682 list[iod->npages++] = prp_list;
7523d834
MW		 683 prp_list[0] = old_prp_list[i - 1];
684 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
685 i = 1;
e025344c
SMM		 686 }
687 prp_list[i++] = cpu_to_le64(dma_addr);
6c3c05b0
CK		 688 dma_len -= NVME_CTRL_PAGE_SIZE;
689 dma_addr += NVME_CTRL_PAGE_SIZE;
690 length -= NVME_CTRL_PAGE_SIZE;
e025344c
SMM		 691 if (length <= 0)
692 break;
693 if (dma_len > 0)
694 continue;
86eea289
KB		 695 if (unlikely(dma_len < 0))
696 goto bad_sgl;
e025344c
SMM		 697 sg = sg_next(sg);
698 dma_addr = sg_dma_address(sg);
699 dma_len = sg_dma_len(sg);
ff22b54f 700 }
a7a7cbe3
CK		 701done:
702 cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
703 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
86eea289 704 return BLK_STS_OK;
fa073216
CH		 705free_prps:
706 nvme_free_prps(dev, req);
707 return BLK_STS_RESOURCE;
708bad_sgl:
d0877473
KB		 709 WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents),
710 "Invalid SGL for payload:%d nents:%d\n",
711 blk_rq_payload_bytes(req), iod->nents);
86eea289 712 return BLK_STS_IOERR;
ff22b54f
MW		 713}
714
a7a7cbe3
CK		 715static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
716 struct scatterlist *sg)
717{
718 sge->addr = cpu_to_le64(sg_dma_address(sg));
719 sge->length = cpu_to_le32(sg_dma_len(sg));
720 sge->type = NVME_SGL_FMT_DATA_DESC << 4;
721}
722
723static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
724 dma_addr_t dma_addr, int entries)
725{
726 sge->addr = cpu_to_le64(dma_addr);
727 if (entries < SGES_PER_PAGE) {
728 sge->length = cpu_to_le32(entries * sizeof(*sge));
729 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
730 } else {
731 sge->length = cpu_to_le32(PAGE_SIZE);
732 sge->type = NVME_SGL_FMT_SEG_DESC << 4;
733 }
734}
735
736static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
b0f2853b 737 struct request *req, struct nvme_rw_command *cmd, int entries)
a7a7cbe3
CK		 738{
739 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3
CK		 740 struct dma_pool *pool;
741 struct nvme_sgl_desc *sg_list;
742 struct scatterlist *sg = iod->sg;
a7a7cbe3 743 dma_addr_t sgl_dma;
b0f2853b 744 int i = 0;
a7a7cbe3 745
a7a7cbe3
CK		 746 /* setting the transfer type as SGL */
747 cmd->flags = NVME_CMD_SGL_METABUF;
748
b0f2853b 749 if (entries == 1) {
a7a7cbe3
CK		 750 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
751 return BLK_STS_OK;
752 }
753
754 if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
755 pool = dev->prp_small_pool;
756 iod->npages = 0;
757 } else {
758 pool = dev->prp_page_pool;
759 iod->npages = 1;
760 }
761
762 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
763 if (!sg_list) {
764 iod->npages = -1;
765 return BLK_STS_RESOURCE;
766 }
767
768 nvme_pci_iod_list(req)[0] = sg_list;
769 iod->first_dma = sgl_dma;
770
771 nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
772
773 do {
774 if (i == SGES_PER_PAGE) {
775 struct nvme_sgl_desc *old_sg_desc = sg_list;
776 struct nvme_sgl_desc *link = &old_sg_desc[i - 1];
777
778 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
779 if (!sg_list)
fa073216 780 goto free_sgls;
a7a7cbe3
CK		 781
782 i = 0;
783 nvme_pci_iod_list(req)[iod->npages++] = sg_list;
784 sg_list[i++] = *link;
785 nvme_pci_sgl_set_seg(link, sgl_dma, entries);
786 }
787
788 nvme_pci_sgl_set_data(&sg_list[i++], sg);
a7a7cbe3 789 sg = sg_next(sg);
b0f2853b 790 } while (--entries > 0);
a7a7cbe3 791
a7a7cbe3 792 return BLK_STS_OK;
fa073216
CH		 793free_sgls:
794 nvme_free_sgls(dev, req);
795 return BLK_STS_RESOURCE;
a7a7cbe3
CK		 796}
797
dff824b2
CH		 798static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev,
799 struct request *req, struct nvme_rw_command *cmnd,
800 struct bio_vec *bv)
801{
802 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
6c3c05b0
CK		 803 unsigned int offset = bv->bv_offset & (NVME_CTRL_PAGE_SIZE - 1);
804 unsigned int first_prp_len = NVME_CTRL_PAGE_SIZE - offset;
dff824b2
CH		 805
806 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
807 if (dma_mapping_error(dev->dev, iod->first_dma))
808 return BLK_STS_RESOURCE;
809 iod->dma_len = bv->bv_len;
810
811 cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma);
812 if (bv->bv_len > first_prp_len)
813 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len);
359c1f88 814 return BLK_STS_OK;
dff824b2
CH		 815}
816
29791057
CH		 817static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev,
818 struct request *req, struct nvme_rw_command *cmnd,
819 struct bio_vec *bv)
820{
821 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
822
823 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
824 if (dma_mapping_error(dev->dev, iod->first_dma))
825 return BLK_STS_RESOURCE;
826 iod->dma_len = bv->bv_len;
827
049bf372 828 cmnd->flags = NVME_CMD_SGL_METABUF;
29791057
CH		 829 cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma);
830 cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len);
831 cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4;
359c1f88 832 return BLK_STS_OK;
29791057
CH		 833}
834
fc17b653 835static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
b131c61d 836 struct nvme_command *cmnd)
d29ec824 837{
f4800d6d 838 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
70479b71 839 blk_status_t ret = BLK_STS_RESOURCE;
b0f2853b 840 int nr_mapped;
d29ec824 841
dff824b2
CH		 842 if (blk_rq_nr_phys_segments(req) == 1) {
843 struct bio_vec bv = req_bvec(req);
844
845 if (!is_pci_p2pdma_page(bv.bv_page)) {
6c3c05b0 846 if (bv.bv_offset + bv.bv_len <= NVME_CTRL_PAGE_SIZE * 2)
dff824b2
CH		 847 return nvme_setup_prp_simple(dev, req,
848 &cmnd->rw, &bv);
29791057 849
e51183be 850 if (iod->nvmeq->qid && sgl_threshold &&
253a0b76 851 nvme_ctrl_sgl_supported(&dev->ctrl))
29791057
CH		 852 return nvme_setup_sgl_simple(dev, req,
853 &cmnd->rw, &bv);
dff824b2
CH		 854 }
855 }
856
857 iod->dma_len = 0;
d43f1ccf
CH		 858 iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC);
859 if (!iod->sg)
860 return BLK_STS_RESOURCE;
f9d03f96 861 sg_init_table(iod->sg, blk_rq_nr_phys_segments(req));
70479b71 862 iod->nents = blk_rq_map_sg(req->q, req, iod->sg);
ba1ca37e 863 if (!iod->nents)
fa073216 864 goto out_free_sg;
d29ec824 865
e0596ab2 866 if (is_pci_p2pdma_page(sg_page(iod->sg)))
2b9f4bb2
LG		 867 nr_mapped = pci_p2pdma_map_sg_attrs(dev->dev, iod->sg,
868 iod->nents, rq_dma_dir(req), DMA_ATTR_NO_WARN);
e0596ab2
LG		 869 else
870 nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents,
70479b71 871 rq_dma_dir(req), DMA_ATTR_NO_WARN);
b0f2853b 872 if (!nr_mapped)
fa073216 873 goto out_free_sg;
d29ec824 874
70479b71 875 iod->use_sgl = nvme_pci_use_sgls(dev, req);
955b1b5a 876 if (iod->use_sgl)
b0f2853b 877 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped);
a7a7cbe3
CK		 878 else
879 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
86eea289 880 if (ret != BLK_STS_OK)
fa073216
CH		 881 goto out_unmap_sg;
882 return BLK_STS_OK;
883
884out_unmap_sg:
885 nvme_unmap_sg(dev, req);
886out_free_sg:
887 mempool_free(iod->sg, dev->iod_mempool);
4aedb705
CH		 888 return ret;
889}
3045c0d0 890
4aedb705
CH		 891static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req,
892 struct nvme_command *cmnd)
893{
894 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
00df5cb4 895
4aedb705
CH		 896 iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req),
897 rq_dma_dir(req), 0);
898 if (dma_mapping_error(dev->dev, iod->meta_dma))
899 return BLK_STS_IOERR;
900 cmnd->rw.metadata = cpu_to_le64(iod->meta_dma);
359c1f88 901 return BLK_STS_OK;
00df5cb4
MW		 902}
903
d29ec824
CH		 904/*
905 * NOTE: ns is NULL when called on the admin queue.
906 */
fc17b653 907static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
a4aea562 908 const struct blk_mq_queue_data *bd)
edd10d33 909{
a4aea562
MB		 910 struct nvme_ns *ns = hctx->queue->queuedata;
911 struct nvme_queue *nvmeq = hctx->driver_data;
d29ec824 912 struct nvme_dev *dev = nvmeq->dev;
a4aea562 913 struct request *req = bd->rq;
9b048119 914 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
af7fae85 915 struct nvme_command *cmnd = &iod->cmd;
ebe6d874 916 blk_status_t ret;
e1e5e564 917
9b048119
CH		 918 iod->aborted = 0;
919 iod->npages = -1;
920 iod->nents = 0;
921
d1f06f4a
JA		 922 /*
923 * We should not need to do this, but we're still using this to
924 * ensure we can drain requests on a dying queue.
925 */
4e224106 926 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
d1f06f4a
JA		 927 return BLK_STS_IOERR;
928
d4060d2b
TC		 929 if (!nvme_check_ready(&dev->ctrl, req, true))
930 return nvme_fail_nonready_command(&dev->ctrl, req);
931
f4b9e6c9 932 ret = nvme_setup_cmd(ns, req);
fc17b653 933 if (ret)
f4800d6d 934 return ret;
a4aea562 935
fc17b653 936 if (blk_rq_nr_phys_segments(req)) {
af7fae85 937 ret = nvme_map_data(dev, req, cmnd);
fc17b653 938 if (ret)
9b048119 939 goto out_free_cmd;
fc17b653 940 }
a4aea562 941
4aedb705 942 if (blk_integrity_rq(req)) {
af7fae85 943 ret = nvme_map_metadata(dev, req, cmnd);
4aedb705
CH		 944 if (ret)
945 goto out_unmap_data;
946 }
947
aae239e1 948 blk_mq_start_request(req);
af7fae85 949 nvme_submit_cmd(nvmeq, cmnd, bd->last);
fc17b653 950 return BLK_STS_OK;
4aedb705
CH		 951out_unmap_data:
952 nvme_unmap_data(dev, req);
f9d03f96
CH		 953out_free_cmd:
954 nvme_cleanup_cmd(req);
ba1ca37e 955 return ret;
b60503ba 956}
e1e5e564 957
77f02a7a 958static void nvme_pci_complete_rq(struct request *req)
eee417b0 959{
f4800d6d 960 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
4aedb705 961 struct nvme_dev *dev = iod->nvmeq->dev;
a4aea562 962
4aedb705
CH		 963 if (blk_integrity_rq(req))
964 dma_unmap_page(dev->dev, iod->meta_dma,
965 rq_integrity_vec(req)->bv_len, rq_data_dir(req));
b15c592d 966 if (blk_rq_nr_phys_segments(req))
4aedb705 967 nvme_unmap_data(dev, req);
77f02a7a 968 nvme_complete_rq(req);
b60503ba
MW		 969}
970
d783e0bd 971/* We read the CQE phase first to check if the rest of the entry is valid */
750dde44 972static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq)
d783e0bd 973{
74943d45
KB		 974 struct nvme_completion *hcqe = &nvmeq->cqes[nvmeq->cq_head];
975
976 return (le16_to_cpu(READ_ONCE(hcqe->status)) & 1) == nvmeq->cq_phase;
d783e0bd
MR		 977}
978
eb281c82 979static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
b60503ba 980{
eb281c82 981 u16 head = nvmeq->cq_head;
adf68f21 982
397c699f
KB		 983 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
984 nvmeq->dbbuf_cq_ei))
985 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
eb281c82 986}
aae239e1 987
cfa27356
CH		 988static inline struct blk_mq_tags *nvme_queue_tagset(struct nvme_queue *nvmeq)
989{
990 if (!nvmeq->qid)
991 return nvmeq->dev->admin_tagset.tags[0];
992 return nvmeq->dev->tagset.tags[nvmeq->qid - 1];
993}
994
5cb525c8 995static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx)
83a12fb7 996{
74943d45 997 struct nvme_completion *cqe = &nvmeq->cqes[idx];
62df8016 998 __u16 command_id = READ_ONCE(cqe->command_id);
83a12fb7 999 struct request *req;
adf68f21 1000
83a12fb7
SG		 1001 /*
1002 * AEN requests are special as they don't time out and can
1003 * survive any kind of queue freeze and often don't respond to
1004 * aborts. We don't even bother to allocate a struct request
1005 * for them but rather special case them here.
1006 */
62df8016 1007 if (unlikely(nvme_is_aen_req(nvmeq->qid, command_id))) {
83a12fb7
SG		 1008 nvme_complete_async_event(&nvmeq->dev->ctrl,
1009 cqe->status, &cqe->result);
a0fa9647 1010 return;
83a12fb7 1011 }
b60503ba 1012
e7006de6 1013 req = nvme_find_rq(nvme_queue_tagset(nvmeq), command_id);
50b7c243
XT		 1014 if (unlikely(!req)) {
1015 dev_warn(nvmeq->dev->ctrl.device,
1016 "invalid id %d completed on queue %d\n",
62df8016 1017 command_id, le16_to_cpu(cqe->sq_id));
50b7c243
XT		 1018 return;
1019 }
1020
604c01d5 1021 trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail);
2eb81a33 1022 if (!nvme_try_complete_req(req, cqe->status, cqe->result))
ff029451 1023 nvme_pci_complete_rq(req);
83a12fb7 1024}
b60503ba 1025
5cb525c8
JA		 1026static inline void nvme_update_cq_head(struct nvme_queue *nvmeq)
1027{
a0aac973 1028 u32 tmp = nvmeq->cq_head + 1;
a8de6639
AD		 1029
1030 if (tmp == nvmeq->q_depth) {
5cb525c8 1031 nvmeq->cq_head = 0;
e2a366a4 1032 nvmeq->cq_phase ^= 1;
a8de6639
AD		 1033 } else {
1034 nvmeq->cq_head = tmp;
b60503ba 1035 }
a0fa9647
JA		 1036}
1037
324b494c 1038static inline int nvme_process_cq(struct nvme_queue *nvmeq)
a0fa9647 1039{
1052b8ac 1040 int found = 0;
b60503ba 1041
1052b8ac 1042 while (nvme_cqe_pending(nvmeq)) {
bf392a5d 1043 found++;
b69e2ef2
KB		 1044 /*
1045 * load-load control dependency between phase and the rest of
1046 * the cqe requires a full read memory barrier
1047 */
1048 dma_rmb();
324b494c 1049 nvme_handle_cqe(nvmeq, nvmeq->cq_head);
5cb525c8 1050 nvme_update_cq_head(nvmeq);
920d13a8 1051 }
eb281c82 1052
324b494c 1053 if (found)
920d13a8 1054 nvme_ring_cq_doorbell(nvmeq);
5cb525c8 1055 return found;
b60503ba
MW		 1056}
1057
1058static irqreturn_t nvme_irq(int irq, void *data)
58ffacb5 1059{
58ffacb5 1060 struct nvme_queue *nvmeq = data;
5cb525c8 1061
324b494c 1062 if (nvme_process_cq(nvmeq))
05fae499
CK		 1063 return IRQ_HANDLED;
1064 return IRQ_NONE;
58ffacb5
MW		 1065}
1066
1067static irqreturn_t nvme_irq_check(int irq, void *data)
1068{
1069 struct nvme_queue *nvmeq = data;
4e523547 1070
750dde44 1071 if (nvme_cqe_pending(nvmeq))
d783e0bd
MR		 1072 return IRQ_WAKE_THREAD;
1073 return IRQ_NONE;
58ffacb5
MW		 1074}
1075
0b2a8a9f 1076/*
fa059b85 1077 * Poll for completions for any interrupt driven queue
0b2a8a9f
CH		 1078 * Can be called from any context.
1079 */
fa059b85 1080static void nvme_poll_irqdisable(struct nvme_queue *nvmeq)
a0fa9647 1081{
3a7afd8e 1082 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
a0fa9647 1083
fa059b85 1084 WARN_ON_ONCE(test_bit(NVMEQ_POLLED, &nvmeq->flags));
442e19b7 1085
fa059b85
KB		 1086 disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1087 nvme_process_cq(nvmeq);
1088 enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
a0fa9647
JA		 1089}
1090
9743139c 1091static int nvme_poll(struct blk_mq_hw_ctx *hctx)
dabcefab
JA		 1092{
1093 struct nvme_queue *nvmeq = hctx->driver_data;
dabcefab
JA		 1094 bool found;
1095
1096 if (!nvme_cqe_pending(nvmeq))
1097 return 0;
1098
3a7afd8e 1099 spin_lock(&nvmeq->cq_poll_lock);
324b494c 1100 found = nvme_process_cq(nvmeq);
3a7afd8e 1101 spin_unlock(&nvmeq->cq_poll_lock);
dabcefab 1102
dabcefab
JA		 1103 return found;
1104}
1105
ad22c355 1106static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
b60503ba 1107{
f866fc42 1108 struct nvme_dev *dev = to_nvme_dev(ctrl);
147b27e4 1109 struct nvme_queue *nvmeq = &dev->queues[0];
f66e2804 1110 struct nvme_command c = { };
b60503ba 1111
a4aea562 1112 c.common.opcode = nvme_admin_async_event;
ad22c355 1113 c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
04f3eafd 1114 nvme_submit_cmd(nvmeq, &c, true);
f705f837
CH		 1115}
1116
b60503ba 1117static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
f705f837 1118{
f66e2804 1119 struct nvme_command c = { };
b60503ba 1120
b60503ba
MW		 1121 c.delete_queue.opcode = opcode;
1122 c.delete_queue.qid = cpu_to_le16(id);
1123
1c63dc66 1124 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1125}
1126
b60503ba 1127static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
a8e3e0bb 1128 struct nvme_queue *nvmeq, s16 vector)
b60503ba 1129{
f66e2804 1130 struct nvme_command c = { };
4b04cc6a
JA		 1131 int flags = NVME_QUEUE_PHYS_CONTIG;
1132
7c349dde 1133 if (!test_bit(NVMEQ_POLLED, &nvmeq->flags))
4b04cc6a 1134 flags |= NVME_CQ_IRQ_ENABLED;
b60503ba 1135
d29ec824 1136 /*
16772ae6 1137 * Note: we (ab)use the fact that the prp fields survive if no data
d29ec824
CH		 1138 * is attached to the request.
1139 */
b60503ba
MW		 1140 c.create_cq.opcode = nvme_admin_create_cq;
1141 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1142 c.create_cq.cqid = cpu_to_le16(qid);
1143 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1144 c.create_cq.cq_flags = cpu_to_le16(flags);
7c349dde 1145 c.create_cq.irq_vector = cpu_to_le16(vector);
b60503ba 1146
1c63dc66 1147 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1148}
1149
1150static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1151 struct nvme_queue *nvmeq)
1152{
9abd68ef 1153 struct nvme_ctrl *ctrl = &dev->ctrl;
f66e2804 1154 struct nvme_command c = { };
81c1cd98 1155 int flags = NVME_QUEUE_PHYS_CONTIG;
b60503ba 1156
9abd68ef
JA		 1157 /*
1158 * Some drives have a bug that auto-enables WRRU if MEDIUM isn't
1159 * set. Since URGENT priority is zeroes, it makes all queues
1160 * URGENT.
1161 */
1162 if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ)
1163 flags |= NVME_SQ_PRIO_MEDIUM;
1164
d29ec824 1165 /*
16772ae6 1166 * Note: we (ab)use the fact that the prp fields survive if no data
d29ec824
CH		 1167 * is attached to the request.
1168 */
b60503ba
MW		 1169 c.create_sq.opcode = nvme_admin_create_sq;
1170 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1171 c.create_sq.sqid = cpu_to_le16(qid);
1172 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1173 c.create_sq.sq_flags = cpu_to_le16(flags);
1174 c.create_sq.cqid = cpu_to_le16(qid);
1175
1c63dc66 1176 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1177}
1178
1179static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1180{
1181 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1182}
1183
1184static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1185{
1186 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1187}
1188
2a842aca 1189static void abort_endio(struct request *req, blk_status_t error)
bc5fc7e4 1190{
f4800d6d
CH		 1191 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1192 struct nvme_queue *nvmeq = iod->nvmeq;
e44ac588 1193
27fa9bc5
CH		 1194 dev_warn(nvmeq->dev->ctrl.device,
1195 "Abort status: 0x%x", nvme_req(req)->status);
e7a2a87d 1196 atomic_inc(&nvmeq->dev->ctrl.abort_limit);
e7a2a87d 1197 blk_mq_free_request(req);
bc5fc7e4
MW		 1198}
1199
b2a0eb1a
KB		 1200static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1201{
b2a0eb1a
KB		 1202 /* If true, indicates loss of adapter communication, possibly by a
1203 * NVMe Subsystem reset.
1204 */
1205 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1206
ad70062c
JW		 1207 /* If there is a reset/reinit ongoing, we shouldn't reset again. */
1208 switch (dev->ctrl.state) {
1209 case NVME_CTRL_RESETTING:
ad6a0a52 1210 case NVME_CTRL_CONNECTING:
b2a0eb1a 1211 return false;
ad70062c
JW		 1212 default:
1213 break;
1214 }
b2a0eb1a
KB		 1215
1216 /* We shouldn't reset unless the controller is on fatal error state
1217 * _or_ if we lost the communication with it.
1218 */
1219 if (!(csts & NVME_CSTS_CFS) && !nssro)
1220 return false;
1221
b2a0eb1a
KB		 1222 return true;
1223}
1224
1225static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1226{
1227 /* Read a config register to help see what died. */
1228 u16 pci_status;
1229 int result;
1230
1231 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1232 &pci_status);
1233 if (result == PCIBIOS_SUCCESSFUL)
1234 dev_warn(dev->ctrl.device,
1235 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1236 csts, pci_status);
1237 else
1238 dev_warn(dev->ctrl.device,
1239 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1240 csts, result);
1241}
1242
31c7c7d2 1243static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
c30341dc 1244{
f4800d6d
CH		 1245 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1246 struct nvme_queue *nvmeq = iod->nvmeq;
c30341dc 1247 struct nvme_dev *dev = nvmeq->dev;
a4aea562 1248 struct request *abort_req;
f66e2804 1249 struct nvme_command cmd = { };
b2a0eb1a
KB		 1250 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1251
651438bb
WX		 1252 /* If PCI error recovery process is happening, we cannot reset or
1253 * the recovery mechanism will surely fail.
1254 */
1255 mb();
1256 if (pci_channel_offline(to_pci_dev(dev->dev)))
1257 return BLK_EH_RESET_TIMER;
1258
b2a0eb1a
KB		 1259 /*
1260 * Reset immediately if the controller is failed
1261 */
1262 if (nvme_should_reset(dev, csts)) {
1263 nvme_warn_reset(dev, csts);
1264 nvme_dev_disable(dev, false);
d86c4d8e 1265 nvme_reset_ctrl(&dev->ctrl);
db8c48e4 1266 return BLK_EH_DONE;
b2a0eb1a 1267 }
c30341dc 1268
7776db1c
KB		 1269 /*
1270 * Did we miss an interrupt?
1271 */
fa059b85
KB		 1272 if (test_bit(NVMEQ_POLLED, &nvmeq->flags))
1273 nvme_poll(req->mq_hctx);
1274 else
1275 nvme_poll_irqdisable(nvmeq);
1276
bf392a5d 1277 if (blk_mq_request_completed(req)) {
7776db1c
KB		 1278 dev_warn(dev->ctrl.device,
1279 "I/O %d QID %d timeout, completion polled\n",
1280 req->tag, nvmeq->qid);
db8c48e4 1281 return BLK_EH_DONE;
7776db1c
KB		 1282 }
1283
31c7c7d2 1284 /*
fd634f41
CH		 1285 * Shutdown immediately if controller times out while starting. The
1286 * reset work will see the pci device disabled when it gets the forced
1287 * cancellation error. All outstanding requests are completed on
db8c48e4 1288 * shutdown, so we return BLK_EH_DONE.
fd634f41 1289 */
4244140d
KB		 1290 switch (dev->ctrl.state) {
1291 case NVME_CTRL_CONNECTING:
2036f726 1292 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
df561f66 1293 fallthrough;
2036f726 1294 case NVME_CTRL_DELETING:
b9cac43c 1295 dev_warn_ratelimited(dev->ctrl.device,
fd634f41
CH		 1296 "I/O %d QID %d timeout, disable controller\n",
1297 req->tag, nvmeq->qid);
27fa9bc5 1298 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
7ad92f65 1299 nvme_dev_disable(dev, true);
db8c48e4 1300 return BLK_EH_DONE;
39a9dd81
KB		 1301 case NVME_CTRL_RESETTING:
1302 return BLK_EH_RESET_TIMER;
4244140d
KB		 1303 default:
1304 break;
c30341dc
KB		 1305 }
1306
fd634f41 1307 /*
ee0d96d3
BW		 1308 * Shutdown the controller immediately and schedule a reset if the
1309 * command was already aborted once before and still hasn't been
1310 * returned to the driver, or if this is the admin queue.
31c7c7d2 1311 */
f4800d6d 1312 if (!nvmeq->qid || iod->aborted) {
1b3c47c1 1313 dev_warn(dev->ctrl.device,
e1569a16
KB		 1314 "I/O %d QID %d timeout, reset controller\n",
1315 req->tag, nvmeq->qid);
7ad92f65 1316 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
a5cdb68c 1317 nvme_dev_disable(dev, false);
d86c4d8e 1318 nvme_reset_ctrl(&dev->ctrl);
c30341dc 1319
db8c48e4 1320 return BLK_EH_DONE;
c30341dc 1321 }
c30341dc 1322
e7a2a87d 1323 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
6bf25d16 1324 atomic_inc(&dev->ctrl.abort_limit);
31c7c7d2 1325 return BLK_EH_RESET_TIMER;
6bf25d16 1326 }
7bf7d778 1327 iod->aborted = 1;
a4aea562 1328
c30341dc 1329 cmd.abort.opcode = nvme_admin_abort_cmd;
a4aea562 1330 cmd.abort.cid = req->tag;
c30341dc 1331 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
c30341dc 1332
1b3c47c1
SG		 1333 dev_warn(nvmeq->dev->ctrl.device,
1334 "I/O %d QID %d timeout, aborting\n",
1335 req->tag, nvmeq->qid);
e7a2a87d
CH		 1336
1337 abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
39dfe844 1338 BLK_MQ_REQ_NOWAIT);
e7a2a87d
CH		 1339 if (IS_ERR(abort_req)) {
1340 atomic_inc(&dev->ctrl.abort_limit);
1341 return BLK_EH_RESET_TIMER;
1342 }
1343
e7a2a87d 1344 abort_req->end_io_data = NULL;
8eeed0b5 1345 blk_execute_rq_nowait(NULL, abort_req, 0, abort_endio);
c30341dc 1346
31c7c7d2
CH		 1347 /*
1348 * The aborted req will be completed on receiving the abort req.
1349 * We enable the timer again. If hit twice, it'll cause a device reset,
1350 * as the device then is in a faulty state.
1351 */
1352 return BLK_EH_RESET_TIMER;
c30341dc
KB		 1353}
1354
a4aea562
MB		 1355static void nvme_free_queue(struct nvme_queue *nvmeq)
1356{
8a1d09a6 1357 dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq),
9e866774 1358 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
63223078
CH		 1359 if (!nvmeq->sq_cmds)
1360 return;
0f238ff5 1361
63223078 1362 if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) {
88a041f4 1363 pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev),
8a1d09a6 1364 nvmeq->sq_cmds, SQ_SIZE(nvmeq));
63223078 1365 } else {
8a1d09a6 1366 dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq),
63223078 1367 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
0f238ff5 1368 }
9e866774
MW		 1369}
1370
a1a5ef99 1371static void nvme_free_queues(struct nvme_dev *dev, int lowest)
22404274
KB		 1372{
1373 int i;
1374
d858e5f0 1375 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
d858e5f0 1376 dev->ctrl.queue_count--;
147b27e4 1377 nvme_free_queue(&dev->queues[i]);
121c7ad4 1378 }
22404274
KB		 1379}
1380
4d115420
KB		 1381/**
1382 * nvme_suspend_queue - put queue into suspended state
40581d1a 1383 * @nvmeq: queue to suspend
4d115420
KB		 1384 */
1385static int nvme_suspend_queue(struct nvme_queue *nvmeq)
b60503ba 1386{
4e224106 1387 if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags))
2b25d981 1388 return 1;
a09115b2 1389
4e224106 1390 /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */
d1f06f4a 1391 mb();
a09115b2 1392
4e224106 1393 nvmeq->dev->online_queues--;
1c63dc66 1394 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
c81545f9 1395 blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q);
7c349dde
KB		 1396 if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags))
1397 pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq);
4d115420
KB		 1398 return 0;
1399}
b60503ba 1400
8fae268b
KB		 1401static void nvme_suspend_io_queues(struct nvme_dev *dev)
1402{
1403 int i;
1404
1405 for (i = dev->ctrl.queue_count - 1; i > 0; i--)
1406 nvme_suspend_queue(&dev->queues[i]);
1407}
1408
a5cdb68c 1409static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
4d115420 1410{
147b27e4 1411 struct nvme_queue *nvmeq = &dev->queues[0];
4d115420 1412
a5cdb68c
KB		 1413 if (shutdown)
1414 nvme_shutdown_ctrl(&dev->ctrl);
1415 else
b5b05048 1416 nvme_disable_ctrl(&dev->ctrl);
07836e65 1417
bf392a5d 1418 nvme_poll_irqdisable(nvmeq);
b60503ba
MW		 1419}
1420
fa46c6fb
KB		 1421/*
1422 * Called only on a device that has been disabled and after all other threads
9210c075
DZ		 1423 * that can check this device's completion queues have synced, except
1424 * nvme_poll(). This is the last chance for the driver to see a natural
1425 * completion before nvme_cancel_request() terminates all incomplete requests.
fa46c6fb
KB		 1426 */
1427static void nvme_reap_pending_cqes(struct nvme_dev *dev)
1428{
fa46c6fb
KB		 1429 int i;
1430
9210c075
DZ		 1431 for (i = dev->ctrl.queue_count - 1; i > 0; i--) {
1432 spin_lock(&dev->queues[i].cq_poll_lock);
324b494c 1433 nvme_process_cq(&dev->queues[i]);
9210c075
DZ		 1434 spin_unlock(&dev->queues[i].cq_poll_lock);
1435 }
fa46c6fb
KB		 1436}
1437
8ffaadf7
JD		 1438static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1439 int entry_size)
1440{
1441 int q_depth = dev->q_depth;
5fd4ce1b 1442 unsigned q_size_aligned = roundup(q_depth * entry_size,
6c3c05b0 1443 NVME_CTRL_PAGE_SIZE);
8ffaadf7
JD		 1444
1445 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
c45f5c99 1446 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
4e523547 1447
6c3c05b0 1448 mem_per_q = round_down(mem_per_q, NVME_CTRL_PAGE_SIZE);
c45f5c99 1449 q_depth = div_u64(mem_per_q, entry_size);
8ffaadf7
JD		 1450
1451 /*
1452 * Ensure the reduced q_depth is above some threshold where it
1453 * would be better to map queues in system memory with the
1454 * original depth
1455 */
1456 if (q_depth < 64)
1457 return -ENOMEM;
1458 }
1459
1460 return q_depth;
1461}
1462
1463static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
8a1d09a6 1464 int qid)
8ffaadf7 1465{
0f238ff5
LG		 1466 struct pci_dev *pdev = to_pci_dev(dev->dev);
1467
1468 if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
8a1d09a6 1469 nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq));
bfac8e9f
AM		 1470 if (nvmeq->sq_cmds) {
1471 nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev,
1472 nvmeq->sq_cmds);
1473 if (nvmeq->sq_dma_addr) {
1474 set_bit(NVMEQ_SQ_CMB, &nvmeq->flags);
1475 return 0;
1476 }
1477
8a1d09a6 1478 pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq));
63223078 1479 }
0f238ff5 1480 }
8ffaadf7 1481
8a1d09a6 1482 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq),
63223078 1483 &nvmeq->sq_dma_addr, GFP_KERNEL);
815c6704
KB		 1484 if (!nvmeq->sq_cmds)
1485 return -ENOMEM;
8ffaadf7
JD		 1486 return 0;
1487}
1488
a6ff7262 1489static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
b60503ba 1490{
147b27e4 1491 struct nvme_queue *nvmeq = &dev->queues[qid];
b60503ba 1492
62314e40
KB		 1493 if (dev->ctrl.queue_count > qid)
1494 return 0;
b60503ba 1495
c1e0cc7e 1496 nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES;
8a1d09a6
BH		 1497 nvmeq->q_depth = depth;
1498 nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq),
750afb08 1499 &nvmeq->cq_dma_addr, GFP_KERNEL);
b60503ba
MW		 1500 if (!nvmeq->cqes)
1501 goto free_nvmeq;
b60503ba 1502
8a1d09a6 1503 if (nvme_alloc_sq_cmds(dev, nvmeq, qid))
b60503ba
MW		 1504 goto free_cqdma;
1505
091b6092 1506 nvmeq->dev = dev;
1ab0cd69 1507 spin_lock_init(&nvmeq->sq_lock);
3a7afd8e 1508 spin_lock_init(&nvmeq->cq_poll_lock);
b60503ba 1509 nvmeq->cq_head = 0;
82123460 1510 nvmeq->cq_phase = 1;
b80d5ccc 1511 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
c30341dc 1512 nvmeq->qid = qid;
d858e5f0 1513 dev->ctrl.queue_count++;
36a7e993 1514
147b27e4 1515 return 0;
b60503ba
MW		 1516
1517 free_cqdma:
8a1d09a6
BH		 1518 dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes,
1519 nvmeq->cq_dma_addr);
b60503ba 1520 free_nvmeq:
147b27e4 1521 return -ENOMEM;
b60503ba
MW		 1522}
1523
dca51e78 1524static int queue_request_irq(struct nvme_queue *nvmeq)
3001082c 1525{
0ff199cb
CH		 1526 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1527 int nr = nvmeq->dev->ctrl.instance;
1528
1529 if (use_threaded_interrupts) {
1530 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1531 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1532 } else {
1533 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1534 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1535 }
3001082c
MW		 1536}
1537
22404274 1538static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
b60503ba 1539{
22404274 1540 struct nvme_dev *dev = nvmeq->dev;
b60503ba 1541
22404274 1542 nvmeq->sq_tail = 0;
38210800 1543 nvmeq->last_sq_tail = 0;
22404274
KB		 1544 nvmeq->cq_head = 0;
1545 nvmeq->cq_phase = 1;
b80d5ccc 1546 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
8a1d09a6 1547 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq));
f9f38e33 1548 nvme_dbbuf_init(dev, nvmeq, qid);
42f61420 1549 dev->online_queues++;
3a7afd8e 1550 wmb(); /* ensure the first interrupt sees the initialization */
22404274
KB		 1551}
1552
e4b9852a
CC		 1553/*
1554 * Try getting shutdown_lock while setting up IO queues.
1555 */
1556static int nvme_setup_io_queues_trylock(struct nvme_dev *dev)
1557{
1558 /*
1559 * Give up if the lock is being held by nvme_dev_disable.
1560 */
1561 if (!mutex_trylock(&dev->shutdown_lock))
1562 return -ENODEV;
1563
1564 /*
1565 * Controller is in wrong state, fail early.
1566 */
1567 if (dev->ctrl.state != NVME_CTRL_CONNECTING) {
1568 mutex_unlock(&dev->shutdown_lock);
1569 return -ENODEV;
1570 }
1571
1572 return 0;
1573}
1574
4b04cc6a 1575static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled)
22404274
KB		 1576{
1577 struct nvme_dev *dev = nvmeq->dev;
1578 int result;
7c349dde 1579 u16 vector = 0;
3f85d50b 1580
d1ed6aa1
CH		 1581 clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
1582
22b55601
KB		 1583 /*
1584 * A queue's vector matches the queue identifier unless the controller
1585 * has only one vector available.
1586 */
4b04cc6a
JA		 1587 if (!polled)
1588 vector = dev->num_vecs == 1 ? 0 : qid;
1589 else
7c349dde 1590 set_bit(NVMEQ_POLLED, &nvmeq->flags);
4b04cc6a 1591
a8e3e0bb 1592 result = adapter_alloc_cq(dev, qid, nvmeq, vector);
ded45505
KB		 1593 if (result)
1594 return result;
b60503ba
MW		 1595
1596 result = adapter_alloc_sq(dev, qid, nvmeq);
1597 if (result < 0)
ded45505 1598 return result;
c80b36cd 1599 if (result)
b60503ba
MW		 1600 goto release_cq;
1601
a8e3e0bb 1602 nvmeq->cq_vector = vector;
4b04cc6a 1603
e4b9852a
CC		 1604 result = nvme_setup_io_queues_trylock(dev);
1605 if (result)
1606 return result;
1607 nvme_init_queue(nvmeq, qid);
7c349dde 1608 if (!polled) {
4b04cc6a
JA		 1609 result = queue_request_irq(nvmeq);
1610 if (result < 0)
1611 goto release_sq;
1612 }
b60503ba 1613
4e224106 1614 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
e4b9852a 1615 mutex_unlock(&dev->shutdown_lock);
22404274 1616 return result;
b60503ba 1617
a8e3e0bb 1618release_sq:
f25a2dfc 1619 dev->online_queues--;
e4b9852a 1620 mutex_unlock(&dev->shutdown_lock);
b60503ba 1621 adapter_delete_sq(dev, qid);
a8e3e0bb 1622release_cq:
b60503ba 1623 adapter_delete_cq(dev, qid);
22404274 1624 return result;
b60503ba
MW		 1625}
1626
f363b089 1627static const struct blk_mq_ops nvme_mq_admin_ops = {
d29ec824 1628 .queue_rq = nvme_queue_rq,
77f02a7a 1629 .complete = nvme_pci_complete_rq,
a4aea562 1630 .init_hctx = nvme_admin_init_hctx,
0350815a 1631 .init_request = nvme_init_request,
a4aea562
MB		 1632 .timeout = nvme_timeout,
1633};
1634
f363b089 1635static const struct blk_mq_ops nvme_mq_ops = {
376f7ef8
CH		 1636 .queue_rq = nvme_queue_rq,
1637 .complete = nvme_pci_complete_rq,
1638 .commit_rqs = nvme_commit_rqs,
1639 .init_hctx = nvme_init_hctx,
1640 .init_request = nvme_init_request,
1641 .map_queues = nvme_pci_map_queues,
1642 .timeout = nvme_timeout,
1643 .poll = nvme_poll,
dabcefab
JA		 1644};
1645
ea191d2f
KB		 1646static void nvme_dev_remove_admin(struct nvme_dev *dev)
1647{
1c63dc66 1648 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
69d9a99c
KB		 1649 /*
1650 * If the controller was reset during removal, it's possible
1651 * user requests may be waiting on a stopped queue. Start the
1652 * queue to flush these to completion.
1653 */
c81545f9 1654 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1c63dc66 1655 blk_cleanup_queue(dev->ctrl.admin_q);
ea191d2f
KB		 1656 blk_mq_free_tag_set(&dev->admin_tagset);
1657 }
1658}
1659
a4aea562
MB		 1660static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1661{
1c63dc66 1662 if (!dev->ctrl.admin_q) {
a4aea562
MB		 1663 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1664 dev->admin_tagset.nr_hw_queues = 1;
e3e9d50c 1665
38dabe21 1666 dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH;
dc96f938 1667 dev->admin_tagset.timeout = NVME_ADMIN_TIMEOUT;
d4ec47f1 1668 dev->admin_tagset.numa_node = dev->ctrl.numa_node;
d43f1ccf 1669 dev->admin_tagset.cmd_size = sizeof(struct nvme_iod);
d3484991 1670 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED;
a4aea562
MB		 1671 dev->admin_tagset.driver_data = dev;
1672
1673 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1674 return -ENOMEM;
34b6c231 1675 dev->ctrl.admin_tagset = &dev->admin_tagset;
a4aea562 1676
1c63dc66
CH		 1677 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1678 if (IS_ERR(dev->ctrl.admin_q)) {
a4aea562
MB		 1679 blk_mq_free_tag_set(&dev->admin_tagset);
1680 return -ENOMEM;
1681 }
1c63dc66 1682 if (!blk_get_queue(dev->ctrl.admin_q)) {
ea191d2f 1683 nvme_dev_remove_admin(dev);
1c63dc66 1684 dev->ctrl.admin_q = NULL;
ea191d2f
KB		 1685 return -ENODEV;
1686 }
0fb59cbc 1687 } else
c81545f9 1688 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
a4aea562
MB		 1689
1690 return 0;
1691}
1692
97f6ef64
XY		 1693static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1694{
1695 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1696}
1697
1698static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1699{
1700 struct pci_dev *pdev = to_pci_dev(dev->dev);
1701
1702 if (size <= dev->bar_mapped_size)
1703 return 0;
1704 if (size > pci_resource_len(pdev, 0))
1705 return -ENOMEM;
1706 if (dev->bar)
1707 iounmap(dev->bar);
1708 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1709 if (!dev->bar) {
1710 dev->bar_mapped_size = 0;
1711 return -ENOMEM;
1712 }
1713 dev->bar_mapped_size = size;
1714 dev->dbs = dev->bar + NVME_REG_DBS;
1715
1716 return 0;
1717}
1718
01ad0990 1719static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
b60503ba 1720{
ba47e386 1721 int result;
b60503ba
MW		 1722 u32 aqa;
1723 struct nvme_queue *nvmeq;
1724
97f6ef64
XY		 1725 result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1726 if (result < 0)
1727 return result;
1728
8ef2074d 1729 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
20d0dfe6 1730 NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
dfbac8c7 1731
7a67cbea
CH		 1732 if (dev->subsystem &&
1733 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1734 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
dfbac8c7 1735
b5b05048 1736 result = nvme_disable_ctrl(&dev->ctrl);
ba47e386
MW		 1737 if (result < 0)
1738 return result;
b60503ba 1739
a6ff7262 1740 result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
147b27e4
SG		 1741 if (result)
1742 return result;
b60503ba 1743
635333e4
MG		 1744 dev->ctrl.numa_node = dev_to_node(dev->dev);
1745
147b27e4 1746 nvmeq = &dev->queues[0];
b60503ba
MW		 1747 aqa = nvmeq->q_depth - 1;
1748 aqa |= aqa << 16;
1749
7a67cbea
CH		 1750 writel(aqa, dev->bar + NVME_REG_AQA);
1751 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1752 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
b60503ba 1753
c0f2f45b 1754 result = nvme_enable_ctrl(&dev->ctrl);
025c557a 1755 if (result)
d4875622 1756 return result;
a4aea562 1757
2b25d981 1758 nvmeq->cq_vector = 0;
161b8be2 1759 nvme_init_queue(nvmeq, 0);
dca51e78 1760 result = queue_request_irq(nvmeq);
758dd7fd 1761 if (result) {
7c349dde 1762 dev->online_queues--;
d4875622 1763 return result;
758dd7fd 1764 }
025c557a 1765
4e224106 1766 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
b60503ba
MW		 1767 return result;
1768}
1769
749941f2 1770static int nvme_create_io_queues(struct nvme_dev *dev)
42f61420 1771{
4b04cc6a 1772 unsigned i, max, rw_queues;
749941f2 1773 int ret = 0;
42f61420 1774
d858e5f0 1775 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
a6ff7262 1776 if (nvme_alloc_queue(dev, i, dev->q_depth)) {
749941f2 1777 ret = -ENOMEM;
42f61420 1778 break;
749941f2
CH		 1779 }
1780 }
42f61420 1781
d858e5f0 1782 max = min(dev->max_qid, dev->ctrl.queue_count - 1);
e20ba6e1
CH		 1783 if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) {
1784 rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] +
1785 dev->io_queues[HCTX_TYPE_READ];
4b04cc6a
JA		 1786 } else {
1787 rw_queues = max;
1788 }
1789
949928c1 1790 for (i = dev->online_queues; i <= max; i++) {
4b04cc6a
JA		 1791 bool polled = i > rw_queues;
1792
1793 ret = nvme_create_queue(&dev->queues[i], i, polled);
d4875622 1794 if (ret)
42f61420 1795 break;
27e8166c 1796 }
749941f2
CH		 1797
1798 /*
1799 * Ignore failing Create SQ/CQ commands, we can continue with less
8adb8c14
MI		 1800 * than the desired amount of queues, and even a controller without
1801 * I/O queues can still be used to issue admin commands. This might
749941f2
CH		 1802 * be useful to upgrade a buggy firmware for example.
1803 */
1804 return ret >= 0 ? 0 : ret;
b60503ba
MW		 1805}
1806
202021c1
SB		 1807static ssize_t nvme_cmb_show(struct device *dev,
1808 struct device_attribute *attr,
1809 char *buf)
1810{
1811 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
1812
c965809c 1813 return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n",
202021c1
SB		 1814 ndev->cmbloc, ndev->cmbsz);
1815}
1816static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL);
1817
88de4598 1818static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
8ffaadf7 1819{
88de4598
CH		 1820 u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
1821
1822 return 1ULL << (12 + 4 * szu);
1823}
1824
1825static u32 nvme_cmb_size(struct nvme_dev *dev)
1826{
1827 return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
1828}
1829
f65efd6d 1830static void nvme_map_cmb(struct nvme_dev *dev)
8ffaadf7 1831{
88de4598 1832 u64 size, offset;
8ffaadf7
JD		 1833 resource_size_t bar_size;
1834 struct pci_dev *pdev = to_pci_dev(dev->dev);
8969f1f8 1835 int bar;
8ffaadf7 1836
9fe5c59f
KB		 1837 if (dev->cmb_size)
1838 return;
1839
20d3bb92
KJ		 1840 if (NVME_CAP_CMBS(dev->ctrl.cap))
1841 writel(NVME_CMBMSC_CRE, dev->bar + NVME_REG_CMBMSC);
1842
7a67cbea 1843 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
f65efd6d
CH		 1844 if (!dev->cmbsz)
1845 return;
202021c1 1846 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
8ffaadf7 1847
88de4598
CH		 1848 size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
1849 offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
8969f1f8
CH		 1850 bar = NVME_CMB_BIR(dev->cmbloc);
1851 bar_size = pci_resource_len(pdev, bar);
8ffaadf7
JD		 1852
1853 if (offset > bar_size)
f65efd6d 1854 return;
8ffaadf7 1855
20d3bb92
KJ		 1856 /*
1857 * Tell the controller about the host side address mapping the CMB,
1858 * and enable CMB decoding for the NVMe 1.4+ scheme:
1859 */
1860 if (NVME_CAP_CMBS(dev->ctrl.cap)) {
1861 hi_lo_writeq(NVME_CMBMSC_CRE | NVME_CMBMSC_CMSE |
1862 (pci_bus_address(pdev, bar) + offset),
1863 dev->bar + NVME_REG_CMBMSC);
1864 }
1865
8ffaadf7
JD		 1866 /*
1867 * Controllers may support a CMB size larger than their BAR,
1868 * for example, due to being behind a bridge. Reduce the CMB to
1869 * the reported size of the BAR
1870 */
1871 if (size > bar_size - offset)
1872 size = bar_size - offset;
1873
0f238ff5
LG		 1874 if (pci_p2pdma_add_resource(pdev, bar, size, offset)) {
1875 dev_warn(dev->ctrl.device,
1876 "failed to register the CMB\n");
f65efd6d 1877 return;
0f238ff5
LG		 1878 }
1879
8ffaadf7 1880 dev->cmb_size = size;
0f238ff5
LG		 1881 dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS);
1882
1883 if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) ==
1884 (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS))
1885 pci_p2pmem_publish(pdev, true);
f65efd6d
CH		 1886
1887 if (sysfs_add_file_to_group(&dev->ctrl.device->kobj,
1888 &dev_attr_cmb.attr, NULL))
1889 dev_warn(dev->ctrl.device,
1890 "failed to add sysfs attribute for CMB\n");
8ffaadf7
JD		 1891}
1892
1893static inline void nvme_release_cmb(struct nvme_dev *dev)
1894{
0f238ff5 1895 if (dev->cmb_size) {
1c78f773
MG		 1896 sysfs_remove_file_from_group(&dev->ctrl.device->kobj,
1897 &dev_attr_cmb.attr, NULL);
0f238ff5 1898 dev->cmb_size = 0;
8ffaadf7
JD		 1899 }
1900}
1901
87ad72a5
CH		 1902static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1903{
6c3c05b0 1904 u32 host_mem_size = dev->host_mem_size >> NVME_CTRL_PAGE_SHIFT;
4033f35d 1905 u64 dma_addr = dev->host_mem_descs_dma;
f66e2804 1906 struct nvme_command c = { };
87ad72a5
CH		 1907 int ret;
1908
87ad72a5
CH		 1909 c.features.opcode = nvme_admin_set_features;
1910 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1911 c.features.dword11 = cpu_to_le32(bits);
6c3c05b0 1912 c.features.dword12 = cpu_to_le32(host_mem_size);
87ad72a5
CH		 1913 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr));
1914 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr));
1915 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs);
1916
1917 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1918 if (ret) {
1919 dev_warn(dev->ctrl.device,
1920 "failed to set host mem (err %d, flags %#x).\n",
1921 ret, bits);
1922 }
87ad72a5
CH		 1923 return ret;
1924}
1925
1926static void nvme_free_host_mem(struct nvme_dev *dev)
1927{
1928 int i;
1929
1930 for (i = 0; i < dev->nr_host_mem_descs; i++) {
1931 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
6c3c05b0 1932 size_t size = le32_to_cpu(desc->size) * NVME_CTRL_PAGE_SIZE;
87ad72a5 1933
cc667f6d
LD		 1934 dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i],
1935 le64_to_cpu(desc->addr),
1936 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
87ad72a5
CH		 1937 }
1938
1939 kfree(dev->host_mem_desc_bufs);
1940 dev->host_mem_desc_bufs = NULL;
4033f35d
CH		 1941 dma_free_coherent(dev->dev,
1942 dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
1943 dev->host_mem_descs, dev->host_mem_descs_dma);
87ad72a5 1944 dev->host_mem_descs = NULL;
7e5dd57e 1945 dev->nr_host_mem_descs = 0;
87ad72a5
CH		 1946}
1947
92dc6895
CH		 1948static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
1949 u32 chunk_size)
9d713c2b 1950{
87ad72a5 1951 struct nvme_host_mem_buf_desc *descs;
92dc6895 1952 u32 max_entries, len;
4033f35d 1953 dma_addr_t descs_dma;
2ee0e4ed 1954 int i = 0;
87ad72a5 1955 void **bufs;
6fbcde66 1956 u64 size, tmp;
87ad72a5 1957
87ad72a5
CH		 1958 tmp = (preferred + chunk_size - 1);
1959 do_div(tmp, chunk_size);
1960 max_entries = tmp;
044a9df1
CH		 1961
1962 if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
1963 max_entries = dev->ctrl.hmmaxd;
1964
750afb08
LC		 1965 descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs),
1966 &descs_dma, GFP_KERNEL);
87ad72a5
CH		 1967 if (!descs)
1968 goto out;
1969
1970 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
1971 if (!bufs)
1972 goto out_free_descs;
1973
244a8fe4 1974 for (size = 0; size < preferred && i < max_entries; size += len) {
87ad72a5
CH		 1975 dma_addr_t dma_addr;
1976
50cdb7c6 1977 len = min_t(u64, chunk_size, preferred - size);
87ad72a5
CH		 1978 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
1979 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1980 if (!bufs[i])
1981 break;
1982
1983 descs[i].addr = cpu_to_le64(dma_addr);
6c3c05b0 1984 descs[i].size = cpu_to_le32(len / NVME_CTRL_PAGE_SIZE);
87ad72a5
CH		 1985 i++;
1986 }
1987
92dc6895 1988 if (!size)
87ad72a5 1989 goto out_free_bufs;
87ad72a5 1990
87ad72a5
CH		 1991 dev->nr_host_mem_descs = i;
1992 dev->host_mem_size = size;
1993 dev->host_mem_descs = descs;
4033f35d 1994 dev->host_mem_descs_dma = descs_dma;
87ad72a5
CH		 1995 dev->host_mem_desc_bufs = bufs;
1996 return 0;
1997
1998out_free_bufs:
1999 while (--i >= 0) {
6c3c05b0 2000 size_t size = le32_to_cpu(descs[i].size) * NVME_CTRL_PAGE_SIZE;
87ad72a5 2001
cc667f6d
LD		 2002 dma_free_attrs(dev->dev, size, bufs[i],
2003 le64_to_cpu(descs[i].addr),
2004 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
87ad72a5
CH		 2005 }
2006
2007 kfree(bufs);
2008out_free_descs:
4033f35d
CH		 2009 dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
2010 descs_dma);
87ad72a5 2011out:
87ad72a5
CH		 2012 dev->host_mem_descs = NULL;
2013 return -ENOMEM;
2014}
2015
92dc6895
CH		 2016static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
2017{
9dc54a0d
CK		 2018 u64 min_chunk = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
2019 u64 hmminds = max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
2020 u64 chunk_size;
92dc6895
CH		 2021
2022 /* start big and work our way down */
9dc54a0d 2023 for (chunk_size = min_chunk; chunk_size >= hmminds; chunk_size /= 2) {
92dc6895
CH		 2024 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
2025 if (!min || dev->host_mem_size >= min)
2026 return 0;
2027 nvme_free_host_mem(dev);
2028 }
2029 }
2030
2031 return -ENOMEM;
2032}
2033
9620cfba 2034static int nvme_setup_host_mem(struct nvme_dev *dev)
87ad72a5
CH		 2035{
2036 u64 max = (u64)max_host_mem_size_mb * SZ_1M;
2037 u64 preferred = (u64)dev->ctrl.hmpre * 4096;
2038 u64 min = (u64)dev->ctrl.hmmin * 4096;
2039 u32 enable_bits = NVME_HOST_MEM_ENABLE;
6fbcde66 2040 int ret;
87ad72a5
CH		 2041
2042 preferred = min(preferred, max);
2043 if (min > max) {
2044 dev_warn(dev->ctrl.device,
2045 "min host memory (%lld MiB) above limit (%d MiB).\n",
2046 min >> ilog2(SZ_1M), max_host_mem_size_mb);
2047 nvme_free_host_mem(dev);
9620cfba 2048 return 0;
87ad72a5
CH		 2049 }
2050
2051 /*
2052 * If we already have a buffer allocated check if we can reuse it.
2053 */
2054 if (dev->host_mem_descs) {
2055 if (dev->host_mem_size >= min)
2056 enable_bits |= NVME_HOST_MEM_RETURN;
2057 else
2058 nvme_free_host_mem(dev);
2059 }
2060
2061 if (!dev->host_mem_descs) {
92dc6895
CH		 2062 if (nvme_alloc_host_mem(dev, min, preferred)) {
2063 dev_warn(dev->ctrl.device,
2064 "failed to allocate host memory buffer.\n");
9620cfba 2065 return 0; /* controller must work without HMB */
92dc6895
CH		 2066 }
2067
2068 dev_info(dev->ctrl.device,
2069 "allocated %lld MiB host memory buffer.\n",
2070 dev->host_mem_size >> ilog2(SZ_1M));
87ad72a5
CH		 2071 }
2072
9620cfba
CH		 2073 ret = nvme_set_host_mem(dev, enable_bits);
2074 if (ret)
87ad72a5 2075 nvme_free_host_mem(dev);
9620cfba 2076 return ret;
9d713c2b
KB		 2077}
2078
612b7286
ML		 2079/*
2080 * nirqs is the number of interrupts available for write and read
2081 * queues. The core already reserved an interrupt for the admin queue.
2082 */
2083static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs)
3b6592f7 2084{
612b7286 2085 struct nvme_dev *dev = affd->priv;
2a5bcfdd 2086 unsigned int nr_read_queues, nr_write_queues = dev->nr_write_queues;
3b6592f7
JA		 2087
2088 /*
ee0d96d3 2089 * If there is no interrupt available for queues, ensure that
612b7286
ML		 2090 * the default queue is set to 1. The affinity set size is
2091 * also set to one, but the irq core ignores it for this case.
2092 *
2093 * If only one interrupt is available or 'write_queue' == 0, combine
2094 * write and read queues.
2095 *
2096 * If 'write_queues' > 0, ensure it leaves room for at least one read
2097 * queue.
3b6592f7 2098 */
612b7286
ML		 2099 if (!nrirqs) {
2100 nrirqs = 1;
2101 nr_read_queues = 0;
2a5bcfdd 2102 } else if (nrirqs == 1 || !nr_write_queues) {
612b7286 2103 nr_read_queues = 0;
2a5bcfdd 2104 } else if (nr_write_queues >= nrirqs) {
612b7286 2105 nr_read_queues = 1;
3b6592f7 2106 } else {
2a5bcfdd 2107 nr_read_queues = nrirqs - nr_write_queues;
3b6592f7 2108 }
612b7286
ML		 2109
2110 dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2111 affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2112 dev->io_queues[HCTX_TYPE_READ] = nr_read_queues;
2113 affd->set_size[HCTX_TYPE_READ] = nr_read_queues;
2114 affd->nr_sets = nr_read_queues ? 2 : 1;
3b6592f7
JA		 2115}
2116
6451fe73 2117static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues)
3b6592f7
JA		 2118{
2119 struct pci_dev *pdev = to_pci_dev(dev->dev);
3b6592f7 2120 struct irq_affinity affd = {
9cfef55b 2121 .pre_vectors = 1,
612b7286
ML		 2122 .calc_sets = nvme_calc_irq_sets,
2123 .priv = dev,
3b6592f7 2124 };
21cc2f3f 2125 unsigned int irq_queues, poll_queues;
6451fe73
JA		 2126
2127 /*
21cc2f3f
JX		 2128 * Poll queues don't need interrupts, but we need at least one I/O queue
2129 * left over for non-polled I/O.
6451fe73 2130 */
21cc2f3f
JX		 2131 poll_queues = min(dev->nr_poll_queues, nr_io_queues - 1);
2132 dev->io_queues[HCTX_TYPE_POLL] = poll_queues;
3b6592f7 2133
21cc2f3f
JX		 2134 /*
2135 * Initialize for the single interrupt case, will be updated in
2136 * nvme_calc_irq_sets().
2137 */
612b7286
ML		 2138 dev->io_queues[HCTX_TYPE_DEFAULT] = 1;
2139 dev->io_queues[HCTX_TYPE_READ] = 0;
3b6592f7 2140
66341331 2141 /*
21cc2f3f
JX		 2142 * We need interrupts for the admin queue and each non-polled I/O queue,
2143 * but some Apple controllers require all queues to use the first
2144 * vector.
66341331 2145 */
21cc2f3f
JX		 2146 irq_queues = 1;
2147 if (!(dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR))
2148 irq_queues += (nr_io_queues - poll_queues);
612b7286
ML		 2149 return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues,
2150 PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd);
3b6592f7
JA		 2151}
2152
8fae268b
KB		 2153static void nvme_disable_io_queues(struct nvme_dev *dev)
2154{
2155 if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq))
2156 __nvme_disable_io_queues(dev, nvme_admin_delete_cq);
2157}
2158
2a5bcfdd
WZ		 2159static unsigned int nvme_max_io_queues(struct nvme_dev *dev)
2160{
e3aef095
NS		 2161 /*
2162 * If tags are shared with admin queue (Apple bug), then
2163 * make sure we only use one IO queue.
2164 */
2165 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2166 return 1;
2a5bcfdd
WZ		 2167 return num_possible_cpus() + dev->nr_write_queues + dev->nr_poll_queues;
2168}
2169
8d85fce7 2170static int nvme_setup_io_queues(struct nvme_dev *dev)
b60503ba 2171{
147b27e4 2172 struct nvme_queue *adminq = &dev->queues[0];
e75ec752 2173 struct pci_dev *pdev = to_pci_dev(dev->dev);
2a5bcfdd 2174 unsigned int nr_io_queues;
97f6ef64 2175 unsigned long size;
2a5bcfdd 2176 int result;
b60503ba 2177
2a5bcfdd
WZ		 2178 /*
2179 * Sample the module parameters once at reset time so that we have
2180 * stable values to work with.
2181 */
2182 dev->nr_write_queues = write_queues;
2183 dev->nr_poll_queues = poll_queues;
d38e9f04 2184
e3aef095 2185 nr_io_queues = dev->nr_allocated_queues - 1;
9a0be7ab
CH		 2186 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
2187 if (result < 0)
1b23484b 2188 return result;
9a0be7ab 2189
f5fa90dc 2190 if (nr_io_queues == 0)
a5229050 2191 return 0;
53dc180e 2192
e4b9852a
CC		 2193 /*
2194 * Free IRQ resources as soon as NVMEQ_ENABLED bit transitions
2195 * from set to unset. If there is a window to it is truely freed,
2196 * pci_free_irq_vectors() jumping into this window will crash.
2197 * And take lock to avoid racing with pci_free_irq_vectors() in
2198 * nvme_dev_disable() path.
2199 */
2200 result = nvme_setup_io_queues_trylock(dev);
2201 if (result)
2202 return result;
2203 if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags))
2204 pci_free_irq(pdev, 0, adminq);
b60503ba 2205
0f238ff5 2206 if (dev->cmb_use_sqes) {
8ffaadf7
JD		 2207 result = nvme_cmb_qdepth(dev, nr_io_queues,
2208 sizeof(struct nvme_command));
2209 if (result > 0)
2210 dev->q_depth = result;
2211 else
0f238ff5 2212 dev->cmb_use_sqes = false;
8ffaadf7
JD		 2213 }
2214
97f6ef64
XY		 2215 do {
2216 size = db_bar_size(dev, nr_io_queues);
2217 result = nvme_remap_bar(dev, size);
2218 if (!result)
2219 break;
e4b9852a
CC		 2220 if (!--nr_io_queues) {
2221 result = -ENOMEM;
2222 goto out_unlock;
2223 }
97f6ef64
XY		 2224 } while (1);
2225 adminq->q_db = dev->dbs;
f1938f6e 2226
8fae268b 2227 retry:
9d713c2b 2228 /* Deregister the admin queue's interrupt */
e4b9852a
CC		 2229 if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags))
2230 pci_free_irq(pdev, 0, adminq);
9d713c2b 2231
e32efbfc
JA		 2232 /*
2233 * If we enable msix early due to not intx, disable it again before
2234 * setting up the full range we need.
2235 */
dca51e78 2236 pci_free_irq_vectors(pdev);
3b6592f7
JA		 2237
2238 result = nvme_setup_irqs(dev, nr_io_queues);
e4b9852a
CC		 2239 if (result <= 0) {
2240 result = -EIO;
2241 goto out_unlock;
2242 }
3b6592f7 2243
22b55601 2244 dev->num_vecs = result;
4b04cc6a 2245 result = max(result - 1, 1);
e20ba6e1 2246 dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL];
fa08a396 2247
063a8096
MW		 2248 /*
2249 * Should investigate if there's a performance win from allocating
2250 * more queues than interrupt vectors; it might allow the submission
2251 * path to scale better, even if the receive path is limited by the
2252 * number of interrupts.
2253 */
dca51e78 2254 result = queue_request_irq(adminq);
7c349dde 2255 if (result)
e4b9852a 2256 goto out_unlock;
4e224106 2257 set_bit(NVMEQ_ENABLED, &adminq->flags);
e4b9852a 2258 mutex_unlock(&dev->shutdown_lock);
8fae268b
KB		 2259
2260 result = nvme_create_io_queues(dev);
2261 if (result || dev->online_queues < 2)
2262 return result;
2263
2264 if (dev->online_queues - 1 < dev->max_qid) {
2265 nr_io_queues = dev->online_queues - 1;
2266 nvme_disable_io_queues(dev);
e4b9852a
CC		 2267 result = nvme_setup_io_queues_trylock(dev);
2268 if (result)
2269 return result;
8fae268b
KB		 2270 nvme_suspend_io_queues(dev);
2271 goto retry;
2272 }
2273 dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n",
2274 dev->io_queues[HCTX_TYPE_DEFAULT],
2275 dev->io_queues[HCTX_TYPE_READ],
2276 dev->io_queues[HCTX_TYPE_POLL]);
2277 return 0;
e4b9852a
CC		 2278out_unlock:
2279 mutex_unlock(&dev->shutdown_lock);
2280 return result;
b60503ba
MW		 2281}
2282
2a842aca 2283static void nvme_del_queue_end(struct request *req, blk_status_t error)
a5768aa8 2284{
db3cbfff 2285 struct nvme_queue *nvmeq = req->end_io_data;
b5875222 2286
db3cbfff 2287 blk_mq_free_request(req);
d1ed6aa1 2288 complete(&nvmeq->delete_done);
a5768aa8
KB		 2289}
2290
2a842aca 2291static void nvme_del_cq_end(struct request *req, blk_status_t error)
a5768aa8 2292{
db3cbfff 2293 struct nvme_queue *nvmeq = req->end_io_data;
a5768aa8 2294
d1ed6aa1
CH		 2295 if (error)
2296 set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
db3cbfff
KB		 2297
2298 nvme_del_queue_end(req, error);
a5768aa8
KB		 2299}
2300
db3cbfff 2301static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
bda4e0fb 2302{
db3cbfff
KB		 2303 struct request_queue *q = nvmeq->dev->ctrl.admin_q;
2304 struct request *req;
f66e2804 2305 struct nvme_command cmd = { };
bda4e0fb 2306
db3cbfff
KB		 2307 cmd.delete_queue.opcode = opcode;
2308 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
bda4e0fb 2309
39dfe844 2310 req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT);
db3cbfff
KB		 2311 if (IS_ERR(req))
2312 return PTR_ERR(req);
bda4e0fb 2313
db3cbfff
KB		 2314 req->end_io_data = nvmeq;
2315
d1ed6aa1 2316 init_completion(&nvmeq->delete_done);
8eeed0b5 2317 blk_execute_rq_nowait(NULL, req, false,
db3cbfff
KB		 2318 opcode == nvme_admin_delete_cq ?
2319 nvme_del_cq_end : nvme_del_queue_end);
2320 return 0;
bda4e0fb
KB		 2321}
2322
8fae268b 2323static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode)
a5768aa8 2324{
5271edd4 2325 int nr_queues = dev->online_queues - 1, sent = 0;
db3cbfff 2326 unsigned long timeout;
a5768aa8 2327
db3cbfff 2328 retry:
dc96f938 2329 timeout = NVME_ADMIN_TIMEOUT;
5271edd4
CH		 2330 while (nr_queues > 0) {
2331 if (nvme_delete_queue(&dev->queues[nr_queues], opcode))
2332 break;
2333 nr_queues--;
2334 sent++;
db3cbfff 2335 }
d1ed6aa1
CH		 2336 while (sent) {
2337 struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent];
2338
2339 timeout = wait_for_completion_io_timeout(&nvmeq->delete_done,
5271edd4
CH		 2340 timeout);
2341 if (timeout == 0)
2342 return false;
d1ed6aa1 2343
d1ed6aa1 2344 sent--;
5271edd4
CH		 2345 if (nr_queues)
2346 goto retry;
2347 }
2348 return true;
a5768aa8
KB		 2349}
2350
5d02a5c1 2351static void nvme_dev_add(struct nvme_dev *dev)
b60503ba 2352{
2b1b7e78
JW		 2353 int ret;
2354
5bae7f73 2355 if (!dev->ctrl.tagset) {
376f7ef8 2356 dev->tagset.ops = &nvme_mq_ops;
ffe7704d 2357 dev->tagset.nr_hw_queues = dev->online_queues - 1;
8fe34be1 2358 dev->tagset.nr_maps = 2; /* default + read */
ed92ad37
CH		 2359 if (dev->io_queues[HCTX_TYPE_POLL])
2360 dev->tagset.nr_maps++;
ffe7704d 2361 dev->tagset.timeout = NVME_IO_TIMEOUT;
d4ec47f1 2362 dev->tagset.numa_node = dev->ctrl.numa_node;
61f3b896
CK		 2363 dev->tagset.queue_depth = min_t(unsigned int, dev->q_depth,
2364 BLK_MQ_MAX_DEPTH) - 1;
d43f1ccf 2365 dev->tagset.cmd_size = sizeof(struct nvme_iod);
ffe7704d
KB		 2366 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2367 dev->tagset.driver_data = dev;
b60503ba 2368
d38e9f04
BH		 2369 /*
2370 * Some Apple controllers requires tags to be unique
2371 * across admin and IO queue, so reserve the first 32
2372 * tags of the IO queue.
2373 */
2374 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2375 dev->tagset.reserved_tags = NVME_AQ_DEPTH;
2376
2b1b7e78
JW		 2377 ret = blk_mq_alloc_tag_set(&dev->tagset);
2378 if (ret) {
2379 dev_warn(dev->ctrl.device,
2380 "IO queues tagset allocation failed %d\n", ret);
5d02a5c1 2381 return;
2b1b7e78 2382 }
5bae7f73 2383 dev->ctrl.tagset = &dev->tagset;
949928c1
KB		 2384 } else {
2385 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2386
2387 /* Free previously allocated queues that are no longer usable */
2388 nvme_free_queues(dev, dev->online_queues);
ffe7704d 2389 }
949928c1 2390
e8fd41bb 2391 nvme_dbbuf_set(dev);
b60503ba
MW		 2392}
2393
b00a726a 2394static int nvme_pci_enable(struct nvme_dev *dev)
0877cb0d 2395{
b00a726a 2396 int result = -ENOMEM;
e75ec752 2397 struct pci_dev *pdev = to_pci_dev(dev->dev);
4bdf2603 2398 int dma_address_bits = 64;
0877cb0d
KB		 2399
2400 if (pci_enable_device_mem(pdev))
2401 return result;
2402
0877cb0d 2403 pci_set_master(pdev);
0877cb0d 2404
4bdf2603
FS		 2405 if (dev->ctrl.quirks & NVME_QUIRK_DMA_ADDRESS_BITS_48)
2406 dma_address_bits = 48;
2407 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(dma_address_bits)))
052d0efa 2408 goto disable;
0877cb0d 2409
7a67cbea 2410 if (readl(dev->bar + NVME_REG_CSTS) == -1) {
0e53d180 2411 result = -ENODEV;
b00a726a 2412 goto disable;
0e53d180 2413 }
e32efbfc
JA		 2414
2415 /*
a5229050
KB		 2416 * Some devices and/or platforms don't advertise or work with INTx
2417 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2418 * adjust this later.
e32efbfc 2419 */
dca51e78
CH		 2420 result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
2421 if (result < 0)
2422 return result;
e32efbfc 2423
20d0dfe6 2424 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
7a67cbea 2425
7442ddce 2426 dev->q_depth = min_t(u32, NVME_CAP_MQES(dev->ctrl.cap) + 1,
b27c1e68 2427 io_queue_depth);
aa22c8e6 2428 dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */
20d0dfe6 2429 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
7a67cbea 2430 dev->dbs = dev->bar + 4096;
1f390c1f 2431
66341331
BH		 2432 /*
2433 * Some Apple controllers require a non-standard SQE size.
2434 * Interestingly they also seem to ignore the CC:IOSQES register
2435 * so we don't bother updating it here.
2436 */
2437 if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES)
2438 dev->io_sqes = 7;
2439 else
2440 dev->io_sqes = NVME_NVM_IOSQES;
1f390c1f
SG		 2441
2442 /*
2443 * Temporary fix for the Apple controller found in the MacBook8,1 and
2444 * some MacBook7,1 to avoid controller resets and data loss.
2445 */
2446 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
2447 dev->q_depth = 2;
9bdcfb10
CH		 2448 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
2449 "set queue depth=%u to work around controller resets\n",
1f390c1f 2450 dev->q_depth);
d554b5e1
MP		 2451 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2452 (pdev->device == 0xa821 || pdev->device == 0xa822) &&
20d0dfe6 2453 NVME_CAP_MQES(dev->ctrl.cap) == 0) {
d554b5e1
MP		 2454 dev->q_depth = 64;
2455 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2456 "set queue depth=%u\n", dev->q_depth);
1f390c1f
SG		 2457 }
2458
d38e9f04
BH		 2459 /*
2460 * Controllers with the shared tags quirk need the IO queue to be
2461 * big enough so that we get 32 tags for the admin queue
2462 */
2463 if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) &&
2464 (dev->q_depth < (NVME_AQ_DEPTH + 2))) {
2465 dev->q_depth = NVME_AQ_DEPTH + 2;
2466 dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n",
2467 dev->q_depth);
2468 }
2469
2470
f65efd6d 2471 nvme_map_cmb(dev);
202021c1 2472
a0a3408e
KB		 2473 pci_enable_pcie_error_reporting(pdev);
2474 pci_save_state(pdev);
0877cb0d
KB		 2475 return 0;
2476
2477 disable:
0877cb0d
KB		 2478 pci_disable_device(pdev);
2479 return result;
2480}
2481
2482static void nvme_dev_unmap(struct nvme_dev *dev)
b00a726a
KB		 2483{
2484 if (dev->bar)
2485 iounmap(dev->bar);
a1f447b3 2486 pci_release_mem_regions(to_pci_dev(dev->dev));
b00a726a
KB		 2487}
2488
2489static void nvme_pci_disable(struct nvme_dev *dev)
0877cb0d 2490{
e75ec752
CH		 2491 struct pci_dev *pdev = to_pci_dev(dev->dev);
2492
dca51e78 2493 pci_free_irq_vectors(pdev);
0877cb0d 2494
a0a3408e
KB		 2495 if (pci_is_enabled(pdev)) {
2496 pci_disable_pcie_error_reporting(pdev);
e75ec752 2497 pci_disable_device(pdev);
4d115420 2498 }
4d115420
KB		 2499}
2500
a5cdb68c 2501static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
b60503ba 2502{
e43269e6 2503 bool dead = true, freeze = false;
302ad8cc 2504 struct pci_dev *pdev = to_pci_dev(dev->dev);
22404274 2505
77bf25ea 2506 mutex_lock(&dev->shutdown_lock);
302ad8cc
KB		 2507 if (pci_is_enabled(pdev)) {
2508 u32 csts = readl(dev->bar + NVME_REG_CSTS);
2509
ebef7368 2510 if (dev->ctrl.state == NVME_CTRL_LIVE ||
e43269e6
KB		 2511 dev->ctrl.state == NVME_CTRL_RESETTING) {
2512 freeze = true;
302ad8cc 2513 nvme_start_freeze(&dev->ctrl);
e43269e6 2514 }
302ad8cc
KB		 2515 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
2516 pdev->error_state != pci_channel_io_normal);
c9d3bf88 2517 }
c21377f8 2518
302ad8cc
KB		 2519 /*
2520 * Give the controller a chance to complete all entered requests if
2521 * doing a safe shutdown.
2522 */
e43269e6
KB		 2523 if (!dead && shutdown && freeze)
2524 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
9a915a5b
JW		 2525
2526 nvme_stop_queues(&dev->ctrl);
87ad72a5 2527
64ee0ac0 2528 if (!dead && dev->ctrl.queue_count > 0) {
8fae268b 2529 nvme_disable_io_queues(dev);
a5cdb68c 2530 nvme_disable_admin_queue(dev, shutdown);
4d115420 2531 }
8fae268b
KB		 2532 nvme_suspend_io_queues(dev);
2533 nvme_suspend_queue(&dev->queues[0]);
b00a726a 2534 nvme_pci_disable(dev);
fa46c6fb 2535 nvme_reap_pending_cqes(dev);
07836e65 2536
e1958e65
ML		 2537 blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
2538 blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
622b8b68
ML		 2539 blk_mq_tagset_wait_completed_request(&dev->tagset);
2540 blk_mq_tagset_wait_completed_request(&dev->admin_tagset);
302ad8cc
KB		 2541
2542 /*
2543 * The driver will not be starting up queues again if shutting down so
2544 * must flush all entered requests to their failed completion to avoid
2545 * deadlocking blk-mq hot-cpu notifier.
2546 */
c8e9e9b7 2547 if (shutdown) {
302ad8cc 2548 nvme_start_queues(&dev->ctrl);
c8e9e9b7
KB		 2549 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q))
2550 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
2551 }
77bf25ea 2552 mutex_unlock(&dev->shutdown_lock);
b60503ba
MW		 2553}
2554
c1ac9a4b
KB		 2555static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown)
2556{
2557 if (!nvme_wait_reset(&dev->ctrl))
2558 return -EBUSY;
2559 nvme_dev_disable(dev, shutdown);
2560 return 0;
2561}
2562
091b6092
MW		 2563static int nvme_setup_prp_pools(struct nvme_dev *dev)
2564{
e75ec752 2565 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
c61b82c7
CH		 2566 NVME_CTRL_PAGE_SIZE,
2567 NVME_CTRL_PAGE_SIZE, 0);
091b6092
MW		 2568 if (!dev->prp_page_pool)
2569 return -ENOMEM;
2570
99802a7a 2571 /* Optimisation for I/Os between 4k and 128k */
e75ec752 2572 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
99802a7a
MW		 2573 256, 256, 0);
2574 if (!dev->prp_small_pool) {
2575 dma_pool_destroy(dev->prp_page_pool);
2576 return -ENOMEM;
2577 }
091b6092
MW		 2578 return 0;
2579}
2580
2581static void nvme_release_prp_pools(struct nvme_dev *dev)
2582{
2583 dma_pool_destroy(dev->prp_page_pool);
99802a7a 2584 dma_pool_destroy(dev->prp_small_pool);
091b6092
MW		 2585}
2586
770597ec
KB		 2587static void nvme_free_tagset(struct nvme_dev *dev)
2588{
2589 if (dev->tagset.tags)
2590 blk_mq_free_tag_set(&dev->tagset);
2591 dev->ctrl.tagset = NULL;
2592}
2593
1673f1f0 2594static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
5e82e952 2595{
1673f1f0 2596 struct nvme_dev *dev = to_nvme_dev(ctrl);
9ac27090 2597
f9f38e33 2598 nvme_dbbuf_dma_free(dev);
770597ec 2599 nvme_free_tagset(dev);
1c63dc66
CH		 2600 if (dev->ctrl.admin_q)
2601 blk_put_queue(dev->ctrl.admin_q);
e286bcfc 2602 free_opal_dev(dev->ctrl.opal_dev);
943e942e 2603 mempool_destroy(dev->iod_mempool);
253fd4ac
IR		 2604 put_device(dev->dev);
2605 kfree(dev->queues);
5e82e952
KB		 2606 kfree(dev);
2607}
2608
7c1ce408 2609static void nvme_remove_dead_ctrl(struct nvme_dev *dev)
f58944e2 2610{
c1ac9a4b
KB		 2611 /*
2612 * Set state to deleting now to avoid blocking nvme_wait_reset(), which
2613 * may be holding this pci_dev's device lock.
2614 */
2615 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
d22524a4 2616 nvme_get_ctrl(&dev->ctrl);
69d9a99c 2617 nvme_dev_disable(dev, false);
9f9cafc1 2618 nvme_kill_queues(&dev->ctrl);
03e0f3a6 2619 if (!queue_work(nvme_wq, &dev->remove_work))
f58944e2
KB		 2620 nvme_put_ctrl(&dev->ctrl);
2621}
2622
fd634f41 2623static void nvme_reset_work(struct work_struct *work)
5e82e952 2624{
d86c4d8e
CH		 2625 struct nvme_dev *dev =
2626 container_of(work, struct nvme_dev, ctrl.reset_work);
a98e58e5 2627 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
e71afda4 2628 int result;
5e82e952 2629
7764656b
ZC		 2630 if (dev->ctrl.state != NVME_CTRL_RESETTING) {
2631 dev_warn(dev->ctrl.device, "ctrl state %d is not RESETTING\n",
2632 dev->ctrl.state);
e71afda4 2633 result = -ENODEV;
fd634f41 2634 goto out;
e71afda4 2635 }
5e82e952 2636
fd634f41
CH		 2637 /*
2638 * If we're called to reset a live controller first shut it down before
2639 * moving on.
2640 */
b00a726a 2641 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
a5cdb68c 2642 nvme_dev_disable(dev, false);
d6135c3a 2643 nvme_sync_queues(&dev->ctrl);
5e82e952 2644
5c959d73 2645 mutex_lock(&dev->shutdown_lock);
b00a726a 2646 result = nvme_pci_enable(dev);
f0b50732 2647 if (result)
4726bcf3 2648 goto out_unlock;
f0b50732 2649
01ad0990 2650 result = nvme_pci_configure_admin_queue(dev);
f0b50732 2651 if (result)
4726bcf3 2652 goto out_unlock;
f0b50732 2653
0fb59cbc
KB		 2654 result = nvme_alloc_admin_tags(dev);
2655 if (result)
4726bcf3 2656 goto out_unlock;
b9afca3e 2657
943e942e
JA		 2658 /*
2659 * Limit the max command size to prevent iod->sg allocations going
2660 * over a single page.
2661 */
7637de31
CH		 2662 dev->ctrl.max_hw_sectors = min_t(u32,
2663 NVME_MAX_KB_SZ << 1, dma_max_mapping_size(dev->dev) >> 9);
943e942e 2664 dev->ctrl.max_segments = NVME_MAX_SEGS;
a48bc520
CH		 2665
2666 /*
2667 * Don't limit the IOMMU merged segment size.
2668 */
2669 dma_set_max_seg_size(dev->dev, 0xffffffff);
3d2d861e 2670 dma_set_min_align_mask(dev->dev, NVME_CTRL_PAGE_SIZE - 1);
a48bc520 2671
5c959d73
KB		 2672 mutex_unlock(&dev->shutdown_lock);
2673
2674 /*
2675 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
2676 * initializing procedure here.
2677 */
2678 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
2679 dev_warn(dev->ctrl.device,
2680 "failed to mark controller CONNECTING\n");
cee6c269 2681 result = -EBUSY;
5c959d73
KB		 2682 goto out;
2683 }
943e942e 2684
95093350
MG		 2685 /*
2686 * We do not support an SGL for metadata (yet), so we are limited to a
2687 * single integrity segment for the separate metadata pointer.
2688 */
2689 dev->ctrl.max_integrity_segments = 1;
2690
f21c4769 2691 result = nvme_init_ctrl_finish(&dev->ctrl);
ce4541f4 2692 if (result)
f58944e2 2693 goto out;
ce4541f4 2694
e286bcfc
SB		 2695 if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
2696 if (!dev->ctrl.opal_dev)
2697 dev->ctrl.opal_dev =
2698 init_opal_dev(&dev->ctrl, &nvme_sec_submit);
2699 else if (was_suspend)
2700 opal_unlock_from_suspend(dev->ctrl.opal_dev);
2701 } else {
2702 free_opal_dev(dev->ctrl.opal_dev);
2703 dev->ctrl.opal_dev = NULL;
4f1244c8 2704 }
a98e58e5 2705
f9f38e33
HK		 2706 if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) {
2707 result = nvme_dbbuf_dma_alloc(dev);
2708 if (result)
2709 dev_warn(dev->dev,
2710 "unable to allocate dma for dbbuf\n");
2711 }
2712
9620cfba
CH		 2713 if (dev->ctrl.hmpre) {
2714 result = nvme_setup_host_mem(dev);
2715 if (result < 0)
2716 goto out;
2717 }
87ad72a5 2718
f0b50732 2719 result = nvme_setup_io_queues(dev);
badc34d4 2720 if (result)
f58944e2 2721 goto out;
f0b50732 2722
2659e57b
CH		 2723 /*
2724 * Keep the controller around but remove all namespaces if we don't have
2725 * any working I/O queue.
2726 */
3cf519b5 2727 if (dev->online_queues < 2) {
1b3c47c1 2728 dev_warn(dev->ctrl.device, "IO queues not created\n");
3b24774e 2729 nvme_kill_queues(&dev->ctrl);
5bae7f73 2730 nvme_remove_namespaces(&dev->ctrl);
770597ec 2731 nvme_free_tagset(dev);
3cf519b5 2732 } else {
25646264 2733 nvme_start_queues(&dev->ctrl);
302ad8cc 2734 nvme_wait_freeze(&dev->ctrl);
5d02a5c1 2735 nvme_dev_add(dev);
302ad8cc 2736 nvme_unfreeze(&dev->ctrl);
3cf519b5
CH		 2737 }
2738
2b1b7e78
JW		 2739 /*
2740 * If only admin queue live, keep it to do further investigation or
2741 * recovery.
2742 */
5d02a5c1 2743 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
2b1b7e78 2744 dev_warn(dev->ctrl.device,
5d02a5c1 2745 "failed to mark controller live state\n");
e71afda4 2746 result = -ENODEV;
bb8d261e
CH		 2747 goto out;
2748 }
92911a55 2749
d09f2b45 2750 nvme_start_ctrl(&dev->ctrl);
3cf519b5 2751 return;
f0b50732 2752
4726bcf3
KB		 2753 out_unlock:
2754 mutex_unlock(&dev->shutdown_lock);
3cf519b5 2755 out:
7c1ce408
CK		 2756 if (result)
2757 dev_warn(dev->ctrl.device,
2758 "Removing after probe failure status: %d\n", result);
2759 nvme_remove_dead_ctrl(dev);
f0b50732
KB		 2760}
2761
5c8809e6 2762static void nvme_remove_dead_ctrl_work(struct work_struct *work)
9a6b9458 2763{
5c8809e6 2764 struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
e75ec752 2765 struct pci_dev *pdev = to_pci_dev(dev->dev);
9a6b9458
KB		 2766
2767 if (pci_get_drvdata(pdev))
921920ab 2768 device_release_driver(&pdev->dev);
1673f1f0 2769 nvme_put_ctrl(&dev->ctrl);
9a6b9458
KB		 2770}
2771
1c63dc66 2772static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
9ca97374 2773{
1c63dc66 2774 *val = readl(to_nvme_dev(ctrl)->bar + off);
90667892 2775 return 0;
9ca97374
TH		 2776}
2777
5fd4ce1b 2778static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
4cc06521 2779{
5fd4ce1b
CH		 2780 writel(val, to_nvme_dev(ctrl)->bar + off);
2781 return 0;
2782}
4cc06521 2783
7fd8930f
CH		 2784static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2785{
3a8ecc93 2786 *val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off);
7fd8930f 2787 return 0;
4cc06521
KB		 2788}
2789
97c12223
KB		 2790static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
2791{
2792 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2793
2db24e4a 2794 return snprintf(buf, size, "%s\n", dev_name(&pdev->dev));
97c12223
KB		 2795}
2796
1c63dc66 2797static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
1a353d85 2798 .name = "pcie",
e439bb12 2799 .module = THIS_MODULE,
e0596ab2
LG		 2800 .flags = NVME_F_METADATA_SUPPORTED |
2801 NVME_F_PCI_P2PDMA,
1c63dc66 2802 .reg_read32 = nvme_pci_reg_read32,
5fd4ce1b 2803 .reg_write32 = nvme_pci_reg_write32,
7fd8930f 2804 .reg_read64 = nvme_pci_reg_read64,
1673f1f0 2805 .free_ctrl = nvme_pci_free_ctrl,
f866fc42 2806 .submit_async_event = nvme_pci_submit_async_event,
97c12223 2807 .get_address = nvme_pci_get_address,
1c63dc66 2808};
4cc06521 2809
b00a726a
KB		 2810static int nvme_dev_map(struct nvme_dev *dev)
2811{
b00a726a
KB		 2812 struct pci_dev *pdev = to_pci_dev(dev->dev);
2813
a1f447b3 2814 if (pci_request_mem_regions(pdev, "nvme"))
b00a726a
KB		 2815 return -ENODEV;
2816
97f6ef64 2817 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
b00a726a
KB		 2818 goto release;
2819
9fa196e7 2820 return 0;
b00a726a 2821 release:
9fa196e7
MG		 2822 pci_release_mem_regions(pdev);
2823 return -ENODEV;
b00a726a
KB		 2824}
2825
8427bbc2 2826static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
ff5350a8
AL		 2827{
2828 if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
2829 /*
2830 * Several Samsung devices seem to drop off the PCIe bus
2831 * randomly when APST is on and uses the deepest sleep state.
2832 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2833 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2834 * 950 PRO 256GB", but it seems to be restricted to two Dell
2835 * laptops.
2836 */
2837 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
2838 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
2839 dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
2840 return NVME_QUIRK_NO_DEEPEST_PS;
8427bbc2
KHF		 2841 } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
2842 /*
2843 * Samsung SSD 960 EVO drops off the PCIe bus after system
467c77d4
JJ		 2844 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
2845 * within few minutes after bootup on a Coffee Lake board -
2846 * ASUS PRIME Z370-A
8427bbc2
KHF		 2847 */
2848 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
467c77d4
JJ		 2849 (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") ||
2850 dmi_match(DMI_BOARD_NAME, "PRIME Z370-A")))
8427bbc2 2851 return NVME_QUIRK_NO_APST;
1fae37ac
S		 2852 } else if ((pdev->vendor == 0x144d && (pdev->device == 0xa801 ||
2853 pdev->device == 0xa808 || pdev->device == 0xa809)) ||
2854 (pdev->vendor == 0x1e0f && pdev->device == 0x0001)) {
2855 /*
2856 * Forcing to use host managed nvme power settings for
2857 * lowest idle power with quick resume latency on
2858 * Samsung and Toshiba SSDs based on suspend behavior
2859 * on Coffee Lake board for LENOVO C640
2860 */
2861 if ((dmi_match(DMI_BOARD_VENDOR, "LENOVO")) &&
2862 dmi_match(DMI_BOARD_NAME, "LNVNB161216"))
2863 return NVME_QUIRK_SIMPLE_SUSPEND;
ff5350a8
AL		 2864 }
2865
2866 return 0;
2867}
2868
18119775
KB		 2869static void nvme_async_probe(void *data, async_cookie_t cookie)
2870{
2871 struct nvme_dev *dev = data;
80f513b5 2872
bd46a906 2873 flush_work(&dev->ctrl.reset_work);
18119775 2874 flush_work(&dev->ctrl.scan_work);
80f513b5 2875 nvme_put_ctrl(&dev->ctrl);
18119775
KB		 2876}
2877
8d85fce7 2878static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
b60503ba 2879{
a4aea562 2880 int node, result = -ENOMEM;
b60503ba 2881 struct nvme_dev *dev;
ff5350a8 2882 unsigned long quirks = id->driver_data;
943e942e 2883 size_t alloc_size;
b60503ba 2884
a4aea562
MB		 2885 node = dev_to_node(&pdev->dev);
2886 if (node == NUMA_NO_NODE)
2fa84351 2887 set_dev_node(&pdev->dev, first_memory_node);
a4aea562
MB		 2888
2889 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
b60503ba
MW		 2890 if (!dev)
2891 return -ENOMEM;
147b27e4 2892
2a5bcfdd
WZ		 2893 dev->nr_write_queues = write_queues;
2894 dev->nr_poll_queues = poll_queues;
2895 dev->nr_allocated_queues = nvme_max_io_queues(dev) + 1;
2896 dev->queues = kcalloc_node(dev->nr_allocated_queues,
2897 sizeof(struct nvme_queue), GFP_KERNEL, node);
b60503ba
MW		 2898 if (!dev->queues)
2899 goto free;
2900
e75ec752 2901 dev->dev = get_device(&pdev->dev);
9a6b9458 2902 pci_set_drvdata(pdev, dev);
1c63dc66 2903
b00a726a
KB		 2904 result = nvme_dev_map(dev);
2905 if (result)
b00c9b7a 2906 goto put_pci;
b00a726a 2907
d86c4d8e 2908 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
5c8809e6 2909 INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
77bf25ea 2910 mutex_init(&dev->shutdown_lock);
b60503ba 2911
091b6092
MW		 2912 result = nvme_setup_prp_pools(dev);
2913 if (result)
b00c9b7a 2914 goto unmap;
4cc06521 2915
8427bbc2 2916 quirks |= check_vendor_combination_bug(pdev);
ff5350a8 2917
2744d7a0 2918 if (!noacpi && acpi_storage_d3(&pdev->dev)) {
df4f9bc4
DB		 2919 /*
2920 * Some systems use a bios work around to ask for D3 on
2921 * platforms that support kernel managed suspend.
2922 */
2923 dev_info(&pdev->dev,
2924 "platform quirk: setting simple suspend\n");
2925 quirks |= NVME_QUIRK_SIMPLE_SUSPEND;
2926 }
2927
943e942e
JA		 2928 /*
2929 * Double check that our mempool alloc size will cover the biggest
2930 * command we support.
2931 */
b13c6393 2932 alloc_size = nvme_pci_iod_alloc_size();
943e942e
JA		 2933 WARN_ON_ONCE(alloc_size > PAGE_SIZE);
2934
2935 dev->iod_mempool = mempool_create_node(1, mempool_kmalloc,
2936 mempool_kfree,
2937 (void *) alloc_size,
2938 GFP_KERNEL, node);
2939 if (!dev->iod_mempool) {
2940 result = -ENOMEM;
2941 goto release_pools;
2942 }
2943
b6e44b4c
KB		 2944 result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
2945 quirks);
2946 if (result)
2947 goto release_mempool;
2948
1b3c47c1
SG		 2949 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
2950
bd46a906 2951 nvme_reset_ctrl(&dev->ctrl);
18119775 2952 async_schedule(nvme_async_probe, dev);
4caff8fc 2953
b60503ba
MW		 2954 return 0;
2955
b6e44b4c
KB		 2956 release_mempool:
2957 mempool_destroy(dev->iod_mempool);
0877cb0d 2958 release_pools:
091b6092 2959 nvme_release_prp_pools(dev);
b00c9b7a
CJ		 2960 unmap:
2961 nvme_dev_unmap(dev);
a96d4f5c 2962 put_pci:
e75ec752 2963 put_device(dev->dev);
b60503ba
MW		 2964 free:
2965 kfree(dev->queues);
b60503ba
MW		 2966 kfree(dev);
2967 return result;
2968}
2969
775755ed 2970static void nvme_reset_prepare(struct pci_dev *pdev)
f0d54a54 2971{
a6739479 2972 struct nvme_dev *dev = pci_get_drvdata(pdev);
c1ac9a4b
KB		 2973
2974 /*
2975 * We don't need to check the return value from waiting for the reset
2976 * state as pci_dev device lock is held, making it impossible to race
2977 * with ->remove().
2978 */
2979 nvme_disable_prepare_reset(dev, false);
2980 nvme_sync_queues(&dev->ctrl);
775755ed 2981}
f0d54a54 2982
775755ed
CH		 2983static void nvme_reset_done(struct pci_dev *pdev)
2984{
f263fbb8 2985 struct nvme_dev *dev = pci_get_drvdata(pdev);
c1ac9a4b
KB		 2986
2987 if (!nvme_try_sched_reset(&dev->ctrl))
2988 flush_work(&dev->ctrl.reset_work);
f0d54a54
KB		 2989}
2990
09ece142
KB		 2991static void nvme_shutdown(struct pci_dev *pdev)
2992{
2993 struct nvme_dev *dev = pci_get_drvdata(pdev);
4e523547 2994
c1ac9a4b 2995 nvme_disable_prepare_reset(dev, true);
09ece142
KB		 2996}
2997
f58944e2
KB		 2998/*
2999 * The driver's remove may be called on a device in a partially initialized
3000 * state. This function must not have any dependencies on the device state in
3001 * order to proceed.
3002 */
8d85fce7 3003static void nvme_remove(struct pci_dev *pdev)
b60503ba
MW		 3004{
3005 struct nvme_dev *dev = pci_get_drvdata(pdev);
9a6b9458 3006
bb8d261e 3007 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
9a6b9458 3008 pci_set_drvdata(pdev, NULL);
0ff9d4e1 3009
6db28eda 3010 if (!pci_device_is_present(pdev)) {
0ff9d4e1 3011 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
1d39e692 3012 nvme_dev_disable(dev, true);
6db28eda 3013 }
0ff9d4e1 3014
d86c4d8e 3015 flush_work(&dev->ctrl.reset_work);
d09f2b45
SG		 3016 nvme_stop_ctrl(&dev->ctrl);
3017 nvme_remove_namespaces(&dev->ctrl);
a5cdb68c 3018 nvme_dev_disable(dev, true);
9fe5c59f 3019 nvme_release_cmb(dev);
87ad72a5 3020 nvme_free_host_mem(dev);
a4aea562 3021 nvme_dev_remove_admin(dev);
a1a5ef99 3022 nvme_free_queues(dev, 0);
9a6b9458 3023 nvme_release_prp_pools(dev);
b00a726a 3024 nvme_dev_unmap(dev);
726612b6 3025 nvme_uninit_ctrl(&dev->ctrl);
b60503ba
MW		 3026}
3027
671a6018 3028#ifdef CONFIG_PM_SLEEP
d916b1be
KB		 3029static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps)
3030{
3031 return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps);
3032}
3033
3034static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps)
3035{
3036 return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL);
3037}
3038
3039static int nvme_resume(struct device *dev)
3040{
3041 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
3042 struct nvme_ctrl *ctrl = &ndev->ctrl;
3043
4eaefe8c 3044 if (ndev->last_ps == U32_MAX ||
d916b1be 3045 nvme_set_power_state(ctrl, ndev->last_ps) != 0)
c1ac9a4b 3046 return nvme_try_sched_reset(&ndev->ctrl);
d916b1be
KB		 3047 return 0;
3048}
3049
cd638946
KB		 3050static int nvme_suspend(struct device *dev)
3051{
3052 struct pci_dev *pdev = to_pci_dev(dev);
3053 struct nvme_dev *ndev = pci_get_drvdata(pdev);
d916b1be
KB		 3054 struct nvme_ctrl *ctrl = &ndev->ctrl;
3055 int ret = -EBUSY;
3056
4eaefe8c
RW		 3057 ndev->last_ps = U32_MAX;
3058
d916b1be
KB		 3059 /*
3060 * The platform does not remove power for a kernel managed suspend so
3061 * use host managed nvme power settings for lowest idle power if
3062 * possible. This should have quicker resume latency than a full device
3063 * shutdown. But if the firmware is involved after the suspend or the
3064 * device does not support any non-default power states, shut down the
3065 * device fully.
4eaefe8c
RW		 3066 *
3067 * If ASPM is not enabled for the device, shut down the device and allow
3068 * the PCI bus layer to put it into D3 in order to take the PCIe link
3069 * down, so as to allow the platform to achieve its minimum low-power
3070 * state (which may not be possible if the link is up).
b97120b1
CH		 3071 *
3072 * If a host memory buffer is enabled, shut down the device as the NVMe
3073 * specification allows the device to access the host memory buffer in
3074 * host DRAM from all power states, but hosts will fail access to DRAM
3075 * during S3.
d916b1be 3076 */
4eaefe8c 3077 if (pm_suspend_via_firmware() || !ctrl->npss ||
cb32de1b 3078 !pcie_aspm_enabled(pdev) ||
b97120b1 3079 ndev->nr_host_mem_descs ||
c1ac9a4b
KB		 3080 (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND))
3081 return nvme_disable_prepare_reset(ndev, true);
d916b1be
KB		 3082
3083 nvme_start_freeze(ctrl);
3084 nvme_wait_freeze(ctrl);
3085 nvme_sync_queues(ctrl);
3086
5d02a5c1 3087 if (ctrl->state != NVME_CTRL_LIVE)
d916b1be
KB		 3088 goto unfreeze;
3089
d916b1be
KB		 3090 ret = nvme_get_power_state(ctrl, &ndev->last_ps);
3091 if (ret < 0)
3092 goto unfreeze;
3093
7cbb5c6f
ML		 3094 /*
3095 * A saved state prevents pci pm from generically controlling the
3096 * device's power. If we're using protocol specific settings, we don't
3097 * want pci interfering.
3098 */
3099 pci_save_state(pdev);
3100
d916b1be
KB		 3101 ret = nvme_set_power_state(ctrl, ctrl->npss);
3102 if (ret < 0)
3103 goto unfreeze;
3104
3105 if (ret) {
7cbb5c6f
ML		 3106 /* discard the saved state */
3107 pci_load_saved_state(pdev, NULL);
3108
d916b1be
KB		 3109 /*
3110 * Clearing npss forces a controller reset on resume. The
05d3046f 3111 * correct value will be rediscovered then.
d916b1be 3112 */
c1ac9a4b 3113 ret = nvme_disable_prepare_reset(ndev, true);
d916b1be 3114 ctrl->npss = 0;
d916b1be 3115 }
d916b1be
KB		 3116unfreeze:
3117 nvme_unfreeze(ctrl);
3118 return ret;
3119}
3120
3121static int nvme_simple_suspend(struct device *dev)
3122{
3123 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
4e523547 3124
c1ac9a4b 3125 return nvme_disable_prepare_reset(ndev, true);
cd638946
KB		 3126}
3127
d916b1be 3128static int nvme_simple_resume(struct device *dev)
cd638946
KB		 3129{
3130 struct pci_dev *pdev = to_pci_dev(dev);
3131 struct nvme_dev *ndev = pci_get_drvdata(pdev);
cd638946 3132
c1ac9a4b 3133 return nvme_try_sched_reset(&ndev->ctrl);
cd638946
KB		 3134}
3135
21774222 3136static const struct dev_pm_ops nvme_dev_pm_ops = {
d916b1be
KB		 3137 .suspend = nvme_suspend,
3138 .resume = nvme_resume,
3139 .freeze = nvme_simple_suspend,
3140 .thaw = nvme_simple_resume,
3141 .poweroff = nvme_simple_suspend,
3142 .restore = nvme_simple_resume,
3143};
3144#endif /* CONFIG_PM_SLEEP */
b60503ba 3145
a0a3408e
KB		 3146static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
3147 pci_channel_state_t state)
3148{
3149 struct nvme_dev *dev = pci_get_drvdata(pdev);
3150
3151 /*
3152 * A frozen channel requires a reset. When detected, this method will
3153 * shutdown the controller to quiesce. The controller will be restarted
3154 * after the slot reset through driver's slot_reset callback.
3155 */
a0a3408e
KB		 3156 switch (state) {
3157 case pci_channel_io_normal:
3158 return PCI_ERS_RESULT_CAN_RECOVER;
3159 case pci_channel_io_frozen:
d011fb31
KB		 3160 dev_warn(dev->ctrl.device,
3161 "frozen state error detected, reset controller\n");
a5cdb68c 3162 nvme_dev_disable(dev, false);
a0a3408e
KB		 3163 return PCI_ERS_RESULT_NEED_RESET;
3164 case pci_channel_io_perm_failure:
d011fb31
KB		 3165 dev_warn(dev->ctrl.device,
3166 "failure state error detected, request disconnect\n");
a0a3408e
KB		 3167 return PCI_ERS_RESULT_DISCONNECT;
3168 }
3169 return PCI_ERS_RESULT_NEED_RESET;
3170}
3171
3172static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
3173{
3174 struct nvme_dev *dev = pci_get_drvdata(pdev);
3175
1b3c47c1 3176 dev_info(dev->ctrl.device, "restart after slot reset\n");
a0a3408e 3177 pci_restore_state(pdev);
d86c4d8e 3178 nvme_reset_ctrl(&dev->ctrl);
a0a3408e
KB		 3179 return PCI_ERS_RESULT_RECOVERED;
3180}
3181
3182static void nvme_error_resume(struct pci_dev *pdev)
3183{
72cd4cc2
KB		 3184 struct nvme_dev *dev = pci_get_drvdata(pdev);
3185
3186 flush_work(&dev->ctrl.reset_work);
a0a3408e
KB		 3187}
3188
1d352035 3189static const struct pci_error_handlers nvme_err_handler = {
b60503ba 3190 .error_detected = nvme_error_detected,
b60503ba
MW		 3191 .slot_reset = nvme_slot_reset,
3192 .resume = nvme_error_resume,
775755ed
CH		 3193 .reset_prepare = nvme_reset_prepare,
3194 .reset_done = nvme_reset_done,
b60503ba
MW		 3195};
3196
6eb0d698 3197static const struct pci_device_id nvme_id_table[] = {
972b13e2 3198 { PCI_VDEVICE(INTEL, 0x0953), /* Intel 750/P3500/P3600/P3700 */
08095e70 3199 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 3200 NVME_QUIRK_DEALLOCATE_ZEROES, },
972b13e2 3201 { PCI_VDEVICE(INTEL, 0x0a53), /* Intel P3520 */
99466e70 3202 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 3203 NVME_QUIRK_DEALLOCATE_ZEROES, },
972b13e2 3204 { PCI_VDEVICE(INTEL, 0x0a54), /* Intel P4500/P4600 */
99466e70 3205 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 3206 NVME_QUIRK_DEALLOCATE_ZEROES, },
972b13e2 3207 { PCI_VDEVICE(INTEL, 0x0a55), /* Dell Express Flash P4600 */
f99cb7af
DWF		 3208 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3209 NVME_QUIRK_DEALLOCATE_ZEROES, },
50af47d0 3210 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */
9abd68ef 3211 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
6c6aa2f2 3212 NVME_QUIRK_MEDIUM_PRIO_SQ |
ce4cc313
DM		 3213 NVME_QUIRK_NO_TEMP_THRESH_CHANGE |
3214 NVME_QUIRK_DISABLE_WRITE_ZEROES, },
6299358d
JD		 3215 { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */
3216 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
540c801c 3217 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */
7b210e4e
CH		 3218 .driver_data = NVME_QUIRK_IDENTIFY_CNS |
3219 NVME_QUIRK_DISABLE_WRITE_ZEROES, },
5bedd3af
CH		 3220 { PCI_DEVICE(0x126f, 0x2263), /* Silicon Motion unidentified */
3221 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST, },
0302ae60 3222 { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */
5e112d3f
JE		 3223 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
3224 NVME_QUIRK_NO_NS_DESC_LIST, },
54adc010
GP		 3225 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
3226 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
8c97eecc
JL		 3227 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */
3228 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
015282c9
WW		 3229 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
3230 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
d554b5e1
MP		 3231 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */
3232 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3233 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */
7ee5c78c 3234 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
abbb5f59 3235 NVME_QUIRK_DISABLE_WRITE_ZEROES|
7ee5c78c 3236 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
c9e95c39
CS		 3237 { PCI_DEVICE(0x1987, 0x5016), /* Phison E16 */
3238 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
6e6a6828
PT		 3239 { PCI_DEVICE(0x1b4b, 0x1092), /* Lexar 256 GB SSD */
3240 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST |
3241 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
08b903b5
MN		 3242 { PCI_DEVICE(0x10ec, 0x5762), /* ADATA SX6000LNP */
3243 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
f03e42c6
GC		 3244 { PCI_DEVICE(0x1cc1, 0x8201), /* ADATA SX8200PNP 512GB */
3245 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3246 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
5611ec2b
KHF		 3247 { PCI_DEVICE(0x1c5c, 0x1504), /* SK Hynix PC400 */
3248 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
02ca079c
KHF		 3249 { PCI_DEVICE(0x15b7, 0x2001), /* Sandisk Skyhawk */
3250 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
89919929
CK		 3251 { PCI_DEVICE(0x1d97, 0x2263), /* SPCC */
3252 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
dc22c1c0
ZB		 3253 { PCI_DEVICE(0x2646, 0x2262), /* KINGSTON SKC2000 NVMe SSD */
3254 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
538e4a8c
TL		 3255 { PCI_DEVICE(0x2646, 0x2263), /* KINGSTON A2000 NVMe SSD */
3256 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
4bdf2603
FS		 3257 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0061),
3258 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3259 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0065),
3260 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3261 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x8061),
3262 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3263 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd00),
3264 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3265 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd01),
3266 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3267 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd02),
3268 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
98f7b86a
AS		 3269 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001),
3270 .driver_data = NVME_QUIRK_SINGLE_VECTOR },
124298bd 3271 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
66341331
BH		 3272 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005),
3273 .driver_data = NVME_QUIRK_SINGLE_VECTOR |
d38e9f04
BH		 3274 NVME_QUIRK_128_BYTES_SQES |
3275 NVME_QUIRK_SHARED_TAGS },
0b85f59d
AS		 3276
3277 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
b60503ba
MW		 3278 { 0, }
3279};
3280MODULE_DEVICE_TABLE(pci, nvme_id_table);
3281
3282static struct pci_driver nvme_driver = {
3283 .name = "nvme",
3284 .id_table = nvme_id_table,
3285 .probe = nvme_probe,
8d85fce7 3286 .remove = nvme_remove,
09ece142 3287 .shutdown = nvme_shutdown,
d916b1be 3288#ifdef CONFIG_PM_SLEEP
cd638946
KB		 3289 .driver = {
3290 .pm = &nvme_dev_pm_ops,
3291 },
d916b1be 3292#endif
74d986ab 3293 .sriov_configure = pci_sriov_configure_simple,
b60503ba
MW		 3294 .err_handler = &nvme_err_handler,
3295};
3296
3297static int __init nvme_init(void)
3298{
81101540
CH		 3299 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
3300 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
3301 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
612b7286 3302 BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2);
17c33167 3303
9a6327d2 3304 return pci_register_driver(&nvme_driver);
b60503ba
MW		 3305}
3306
3307static void __exit nvme_exit(void)
3308{
3309 pci_unregister_driver(&nvme_driver);
03e0f3a6 3310 flush_workqueue(nvme_wq);
b60503ba
MW		 3311}
3312
3313MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3314MODULE_LICENSE("GPL");
c78b4713 3315MODULE_VERSION("1.0");
b60503ba
MW		 3316module_init(nvme_init);
3317module_exit(nvme_exit);
Linux 6.x block layer and io_uring tree(s)