Commit | Line | Data |
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b60503ba MW |
1 | /* |
2 | * NVM Express device driver | |
6eb0d698 | 3 | * Copyright (c) 2011-2014, Intel Corporation. |
b60503ba MW |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
b60503ba MW |
13 | */ |
14 | ||
a0a3408e | 15 | #include <linux/aer.h> |
8de05535 | 16 | #include <linux/bitops.h> |
b60503ba | 17 | #include <linux/blkdev.h> |
a4aea562 | 18 | #include <linux/blk-mq.h> |
dca51e78 | 19 | #include <linux/blk-mq-pci.h> |
42f61420 | 20 | #include <linux/cpu.h> |
fd63e9ce | 21 | #include <linux/delay.h> |
b60503ba MW |
22 | #include <linux/errno.h> |
23 | #include <linux/fs.h> | |
24 | #include <linux/genhd.h> | |
4cc09e2d | 25 | #include <linux/hdreg.h> |
5aff9382 | 26 | #include <linux/idr.h> |
b60503ba MW |
27 | #include <linux/init.h> |
28 | #include <linux/interrupt.h> | |
29 | #include <linux/io.h> | |
30 | #include <linux/kdev_t.h> | |
31 | #include <linux/kernel.h> | |
32 | #include <linux/mm.h> | |
33 | #include <linux/module.h> | |
34 | #include <linux/moduleparam.h> | |
77bf25ea | 35 | #include <linux/mutex.h> |
b60503ba | 36 | #include <linux/pci.h> |
be7b6275 | 37 | #include <linux/poison.h> |
c3bfe717 | 38 | #include <linux/ptrace.h> |
b60503ba MW |
39 | #include <linux/sched.h> |
40 | #include <linux/slab.h> | |
e1e5e564 | 41 | #include <linux/t10-pi.h> |
2d55cd5f | 42 | #include <linux/timer.h> |
b60503ba | 43 | #include <linux/types.h> |
2f8e2c87 | 44 | #include <linux/io-64-nonatomic-lo-hi.h> |
1d277a63 | 45 | #include <asm/unaligned.h> |
797a796a | 46 | |
f11bb3e2 CH |
47 | #include "nvme.h" |
48 | ||
9d43cf64 | 49 | #define NVME_Q_DEPTH 1024 |
d31af0a3 | 50 | #define NVME_AQ_DEPTH 256 |
b60503ba MW |
51 | #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command)) |
52 | #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion)) | |
adf68f21 CH |
53 | |
54 | /* | |
55 | * We handle AEN commands ourselves and don't even let the | |
56 | * block layer know about them. | |
57 | */ | |
f866fc42 | 58 | #define NVME_AQ_BLKMQ_DEPTH (NVME_AQ_DEPTH - NVME_NR_AERS) |
9d43cf64 | 59 | |
58ffacb5 MW |
60 | static int use_threaded_interrupts; |
61 | module_param(use_threaded_interrupts, int, 0); | |
62 | ||
8ffaadf7 JD |
63 | static bool use_cmb_sqes = true; |
64 | module_param(use_cmb_sqes, bool, 0644); | |
65 | MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes"); | |
66 | ||
9a6b9458 | 67 | static struct workqueue_struct *nvme_workq; |
1fa6aead | 68 | |
1c63dc66 CH |
69 | struct nvme_dev; |
70 | struct nvme_queue; | |
b3fffdef | 71 | |
4cc06521 | 72 | static int nvme_reset(struct nvme_dev *dev); |
a0fa9647 | 73 | static void nvme_process_cq(struct nvme_queue *nvmeq); |
a5cdb68c | 74 | static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown); |
d4b4ff8e | 75 | |
1c63dc66 CH |
76 | /* |
77 | * Represents an NVM Express device. Each nvme_dev is a PCI function. | |
78 | */ | |
79 | struct nvme_dev { | |
1c63dc66 CH |
80 | struct nvme_queue **queues; |
81 | struct blk_mq_tag_set tagset; | |
82 | struct blk_mq_tag_set admin_tagset; | |
83 | u32 __iomem *dbs; | |
84 | struct device *dev; | |
85 | struct dma_pool *prp_page_pool; | |
86 | struct dma_pool *prp_small_pool; | |
87 | unsigned queue_count; | |
88 | unsigned online_queues; | |
89 | unsigned max_qid; | |
90 | int q_depth; | |
91 | u32 db_stride; | |
1c63dc66 | 92 | void __iomem *bar; |
1c63dc66 | 93 | struct work_struct reset_work; |
5c8809e6 | 94 | struct work_struct remove_work; |
2d55cd5f | 95 | struct timer_list watchdog_timer; |
77bf25ea | 96 | struct mutex shutdown_lock; |
1c63dc66 | 97 | bool subsystem; |
1c63dc66 CH |
98 | void __iomem *cmb; |
99 | dma_addr_t cmb_dma_addr; | |
100 | u64 cmb_size; | |
101 | u32 cmbsz; | |
202021c1 | 102 | u32 cmbloc; |
1c63dc66 | 103 | struct nvme_ctrl ctrl; |
db3cbfff | 104 | struct completion ioq_wait; |
4d115420 | 105 | }; |
1fa6aead | 106 | |
1c63dc66 CH |
107 | static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl) |
108 | { | |
109 | return container_of(ctrl, struct nvme_dev, ctrl); | |
110 | } | |
111 | ||
b60503ba MW |
112 | /* |
113 | * An NVM Express queue. Each device has at least two (one for admin | |
114 | * commands and one for I/O commands). | |
115 | */ | |
116 | struct nvme_queue { | |
117 | struct device *q_dmadev; | |
091b6092 | 118 | struct nvme_dev *dev; |
3193f07b | 119 | char irqname[24]; /* nvme4294967295-65535\0 */ |
b60503ba MW |
120 | spinlock_t q_lock; |
121 | struct nvme_command *sq_cmds; | |
8ffaadf7 | 122 | struct nvme_command __iomem *sq_cmds_io; |
b60503ba | 123 | volatile struct nvme_completion *cqes; |
42483228 | 124 | struct blk_mq_tags **tags; |
b60503ba MW |
125 | dma_addr_t sq_dma_addr; |
126 | dma_addr_t cq_dma_addr; | |
b60503ba MW |
127 | u32 __iomem *q_db; |
128 | u16 q_depth; | |
6222d172 | 129 | s16 cq_vector; |
b60503ba MW |
130 | u16 sq_tail; |
131 | u16 cq_head; | |
c30341dc | 132 | u16 qid; |
e9539f47 MW |
133 | u8 cq_phase; |
134 | u8 cqe_seen; | |
b60503ba MW |
135 | }; |
136 | ||
71bd150c CH |
137 | /* |
138 | * The nvme_iod describes the data in an I/O, including the list of PRP | |
139 | * entries. You can't see it in this data structure because C doesn't let | |
f4800d6d | 140 | * me express that. Use nvme_init_iod to ensure there's enough space |
71bd150c CH |
141 | * allocated to store the PRP list. |
142 | */ | |
143 | struct nvme_iod { | |
d49187e9 | 144 | struct nvme_request req; |
f4800d6d CH |
145 | struct nvme_queue *nvmeq; |
146 | int aborted; | |
71bd150c | 147 | int npages; /* In the PRP list. 0 means small pool in use */ |
71bd150c CH |
148 | int nents; /* Used in scatterlist */ |
149 | int length; /* Of data, in bytes */ | |
150 | dma_addr_t first_dma; | |
bf684057 | 151 | struct scatterlist meta_sg; /* metadata requires single contiguous buffer */ |
f4800d6d CH |
152 | struct scatterlist *sg; |
153 | struct scatterlist inline_sg[0]; | |
b60503ba MW |
154 | }; |
155 | ||
156 | /* | |
157 | * Check we didin't inadvertently grow the command struct | |
158 | */ | |
159 | static inline void _nvme_check_size(void) | |
160 | { | |
161 | BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64); | |
162 | BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); | |
163 | BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); | |
164 | BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); | |
165 | BUILD_BUG_ON(sizeof(struct nvme_features) != 64); | |
f8ebf840 | 166 | BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64); |
c30341dc | 167 | BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64); |
b60503ba MW |
168 | BUILD_BUG_ON(sizeof(struct nvme_command) != 64); |
169 | BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096); | |
170 | BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096); | |
171 | BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64); | |
6ecec745 | 172 | BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512); |
b60503ba MW |
173 | } |
174 | ||
ac3dd5bd JA |
175 | /* |
176 | * Max size of iod being embedded in the request payload | |
177 | */ | |
178 | #define NVME_INT_PAGES 2 | |
5fd4ce1b | 179 | #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size) |
ac3dd5bd JA |
180 | |
181 | /* | |
182 | * Will slightly overestimate the number of pages needed. This is OK | |
183 | * as it only leads to a small amount of wasted memory for the lifetime of | |
184 | * the I/O. | |
185 | */ | |
186 | static int nvme_npages(unsigned size, struct nvme_dev *dev) | |
187 | { | |
5fd4ce1b CH |
188 | unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size, |
189 | dev->ctrl.page_size); | |
ac3dd5bd JA |
190 | return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); |
191 | } | |
192 | ||
f4800d6d CH |
193 | static unsigned int nvme_iod_alloc_size(struct nvme_dev *dev, |
194 | unsigned int size, unsigned int nseg) | |
ac3dd5bd | 195 | { |
f4800d6d CH |
196 | return sizeof(__le64 *) * nvme_npages(size, dev) + |
197 | sizeof(struct scatterlist) * nseg; | |
198 | } | |
ac3dd5bd | 199 | |
f4800d6d CH |
200 | static unsigned int nvme_cmd_size(struct nvme_dev *dev) |
201 | { | |
202 | return sizeof(struct nvme_iod) + | |
203 | nvme_iod_alloc_size(dev, NVME_INT_BYTES(dev), NVME_INT_PAGES); | |
ac3dd5bd JA |
204 | } |
205 | ||
dca51e78 CH |
206 | static int nvmeq_irq(struct nvme_queue *nvmeq) |
207 | { | |
208 | return pci_irq_vector(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector); | |
209 | } | |
210 | ||
a4aea562 MB |
211 | static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, |
212 | unsigned int hctx_idx) | |
e85248e5 | 213 | { |
a4aea562 MB |
214 | struct nvme_dev *dev = data; |
215 | struct nvme_queue *nvmeq = dev->queues[0]; | |
216 | ||
42483228 KB |
217 | WARN_ON(hctx_idx != 0); |
218 | WARN_ON(dev->admin_tagset.tags[0] != hctx->tags); | |
219 | WARN_ON(nvmeq->tags); | |
220 | ||
a4aea562 | 221 | hctx->driver_data = nvmeq; |
42483228 | 222 | nvmeq->tags = &dev->admin_tagset.tags[0]; |
a4aea562 | 223 | return 0; |
e85248e5 MW |
224 | } |
225 | ||
4af0e21c KB |
226 | static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx) |
227 | { | |
228 | struct nvme_queue *nvmeq = hctx->driver_data; | |
229 | ||
230 | nvmeq->tags = NULL; | |
231 | } | |
232 | ||
a4aea562 MB |
233 | static int nvme_admin_init_request(void *data, struct request *req, |
234 | unsigned int hctx_idx, unsigned int rq_idx, | |
235 | unsigned int numa_node) | |
22404274 | 236 | { |
a4aea562 | 237 | struct nvme_dev *dev = data; |
f4800d6d | 238 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
a4aea562 MB |
239 | struct nvme_queue *nvmeq = dev->queues[0]; |
240 | ||
241 | BUG_ON(!nvmeq); | |
f4800d6d | 242 | iod->nvmeq = nvmeq; |
a4aea562 | 243 | return 0; |
22404274 KB |
244 | } |
245 | ||
a4aea562 MB |
246 | static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, |
247 | unsigned int hctx_idx) | |
b60503ba | 248 | { |
a4aea562 | 249 | struct nvme_dev *dev = data; |
42483228 | 250 | struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1]; |
a4aea562 | 251 | |
42483228 KB |
252 | if (!nvmeq->tags) |
253 | nvmeq->tags = &dev->tagset.tags[hctx_idx]; | |
b60503ba | 254 | |
42483228 | 255 | WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags); |
a4aea562 MB |
256 | hctx->driver_data = nvmeq; |
257 | return 0; | |
b60503ba MW |
258 | } |
259 | ||
a4aea562 MB |
260 | static int nvme_init_request(void *data, struct request *req, |
261 | unsigned int hctx_idx, unsigned int rq_idx, | |
262 | unsigned int numa_node) | |
b60503ba | 263 | { |
a4aea562 | 264 | struct nvme_dev *dev = data; |
f4800d6d | 265 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
a4aea562 MB |
266 | struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1]; |
267 | ||
268 | BUG_ON(!nvmeq); | |
f4800d6d | 269 | iod->nvmeq = nvmeq; |
a4aea562 MB |
270 | return 0; |
271 | } | |
272 | ||
dca51e78 CH |
273 | static int nvme_pci_map_queues(struct blk_mq_tag_set *set) |
274 | { | |
275 | struct nvme_dev *dev = set->driver_data; | |
276 | ||
277 | return blk_mq_pci_map_queues(set, to_pci_dev(dev->dev)); | |
278 | } | |
279 | ||
b60503ba | 280 | /** |
adf68f21 | 281 | * __nvme_submit_cmd() - Copy a command into a queue and ring the doorbell |
b60503ba MW |
282 | * @nvmeq: The queue to use |
283 | * @cmd: The command to send | |
284 | * | |
285 | * Safe to use from interrupt context | |
286 | */ | |
e3f879bf SB |
287 | static void __nvme_submit_cmd(struct nvme_queue *nvmeq, |
288 | struct nvme_command *cmd) | |
b60503ba | 289 | { |
a4aea562 MB |
290 | u16 tail = nvmeq->sq_tail; |
291 | ||
8ffaadf7 JD |
292 | if (nvmeq->sq_cmds_io) |
293 | memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd)); | |
294 | else | |
295 | memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd)); | |
296 | ||
b60503ba MW |
297 | if (++tail == nvmeq->q_depth) |
298 | tail = 0; | |
7547881d | 299 | writel(tail, nvmeq->q_db); |
b60503ba | 300 | nvmeq->sq_tail = tail; |
b60503ba MW |
301 | } |
302 | ||
f4800d6d | 303 | static __le64 **iod_list(struct request *req) |
b60503ba | 304 | { |
f4800d6d | 305 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
f9d03f96 | 306 | return (__le64 **)(iod->sg + blk_rq_nr_phys_segments(req)); |
b60503ba MW |
307 | } |
308 | ||
58b45602 ML |
309 | static int nvme_init_iod(struct request *rq, unsigned size, |
310 | struct nvme_dev *dev) | |
ac3dd5bd | 311 | { |
f4800d6d | 312 | struct nvme_iod *iod = blk_mq_rq_to_pdu(rq); |
f9d03f96 | 313 | int nseg = blk_rq_nr_phys_segments(rq); |
ac3dd5bd | 314 | |
f4800d6d CH |
315 | if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) { |
316 | iod->sg = kmalloc(nvme_iod_alloc_size(dev, size, nseg), GFP_ATOMIC); | |
317 | if (!iod->sg) | |
318 | return BLK_MQ_RQ_QUEUE_BUSY; | |
319 | } else { | |
320 | iod->sg = iod->inline_sg; | |
ac3dd5bd JA |
321 | } |
322 | ||
f4800d6d CH |
323 | iod->aborted = 0; |
324 | iod->npages = -1; | |
325 | iod->nents = 0; | |
326 | iod->length = size; | |
f80ec966 | 327 | |
e8064021 | 328 | if (!(rq->rq_flags & RQF_DONTPREP)) { |
f80ec966 | 329 | rq->retries = 0; |
e8064021 | 330 | rq->rq_flags |= RQF_DONTPREP; |
f80ec966 | 331 | } |
bac0000a | 332 | return BLK_MQ_RQ_QUEUE_OK; |
ac3dd5bd JA |
333 | } |
334 | ||
f4800d6d | 335 | static void nvme_free_iod(struct nvme_dev *dev, struct request *req) |
b60503ba | 336 | { |
f4800d6d | 337 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
5fd4ce1b | 338 | const int last_prp = dev->ctrl.page_size / 8 - 1; |
eca18b23 | 339 | int i; |
f4800d6d | 340 | __le64 **list = iod_list(req); |
eca18b23 MW |
341 | dma_addr_t prp_dma = iod->first_dma; |
342 | ||
343 | if (iod->npages == 0) | |
344 | dma_pool_free(dev->prp_small_pool, list[0], prp_dma); | |
345 | for (i = 0; i < iod->npages; i++) { | |
346 | __le64 *prp_list = list[i]; | |
347 | dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]); | |
348 | dma_pool_free(dev->prp_page_pool, prp_list, prp_dma); | |
349 | prp_dma = next_prp_dma; | |
350 | } | |
ac3dd5bd | 351 | |
f4800d6d CH |
352 | if (iod->sg != iod->inline_sg) |
353 | kfree(iod->sg); | |
b4ff9c8d KB |
354 | } |
355 | ||
52b68d7e | 356 | #ifdef CONFIG_BLK_DEV_INTEGRITY |
e1e5e564 KB |
357 | static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi) |
358 | { | |
359 | if (be32_to_cpu(pi->ref_tag) == v) | |
360 | pi->ref_tag = cpu_to_be32(p); | |
361 | } | |
362 | ||
363 | static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi) | |
364 | { | |
365 | if (be32_to_cpu(pi->ref_tag) == p) | |
366 | pi->ref_tag = cpu_to_be32(v); | |
367 | } | |
368 | ||
369 | /** | |
370 | * nvme_dif_remap - remaps ref tags to bip seed and physical lba | |
371 | * | |
372 | * The virtual start sector is the one that was originally submitted by the | |
373 | * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical | |
374 | * start sector may be different. Remap protection information to match the | |
375 | * physical LBA on writes, and back to the original seed on reads. | |
376 | * | |
377 | * Type 0 and 3 do not have a ref tag, so no remapping required. | |
378 | */ | |
379 | static void nvme_dif_remap(struct request *req, | |
380 | void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi)) | |
381 | { | |
382 | struct nvme_ns *ns = req->rq_disk->private_data; | |
383 | struct bio_integrity_payload *bip; | |
384 | struct t10_pi_tuple *pi; | |
385 | void *p, *pmap; | |
386 | u32 i, nlb, ts, phys, virt; | |
387 | ||
388 | if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3) | |
389 | return; | |
390 | ||
391 | bip = bio_integrity(req->bio); | |
392 | if (!bip) | |
393 | return; | |
394 | ||
395 | pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset; | |
e1e5e564 KB |
396 | |
397 | p = pmap; | |
398 | virt = bip_get_seed(bip); | |
399 | phys = nvme_block_nr(ns, blk_rq_pos(req)); | |
400 | nlb = (blk_rq_bytes(req) >> ns->lba_shift); | |
ac6fc48c | 401 | ts = ns->disk->queue->integrity.tuple_size; |
e1e5e564 KB |
402 | |
403 | for (i = 0; i < nlb; i++, virt++, phys++) { | |
404 | pi = (struct t10_pi_tuple *)p; | |
405 | dif_swap(phys, virt, pi); | |
406 | p += ts; | |
407 | } | |
408 | kunmap_atomic(pmap); | |
409 | } | |
52b68d7e KB |
410 | #else /* CONFIG_BLK_DEV_INTEGRITY */ |
411 | static void nvme_dif_remap(struct request *req, | |
412 | void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi)) | |
413 | { | |
414 | } | |
415 | static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi) | |
416 | { | |
417 | } | |
418 | static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi) | |
419 | { | |
420 | } | |
52b68d7e KB |
421 | #endif |
422 | ||
f4800d6d | 423 | static bool nvme_setup_prps(struct nvme_dev *dev, struct request *req, |
69d2b571 | 424 | int total_len) |
ff22b54f | 425 | { |
f4800d6d | 426 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
99802a7a | 427 | struct dma_pool *pool; |
eca18b23 MW |
428 | int length = total_len; |
429 | struct scatterlist *sg = iod->sg; | |
ff22b54f MW |
430 | int dma_len = sg_dma_len(sg); |
431 | u64 dma_addr = sg_dma_address(sg); | |
5fd4ce1b | 432 | u32 page_size = dev->ctrl.page_size; |
f137e0f1 | 433 | int offset = dma_addr & (page_size - 1); |
e025344c | 434 | __le64 *prp_list; |
f4800d6d | 435 | __le64 **list = iod_list(req); |
e025344c | 436 | dma_addr_t prp_dma; |
eca18b23 | 437 | int nprps, i; |
ff22b54f | 438 | |
1d090624 | 439 | length -= (page_size - offset); |
ff22b54f | 440 | if (length <= 0) |
69d2b571 | 441 | return true; |
ff22b54f | 442 | |
1d090624 | 443 | dma_len -= (page_size - offset); |
ff22b54f | 444 | if (dma_len) { |
1d090624 | 445 | dma_addr += (page_size - offset); |
ff22b54f MW |
446 | } else { |
447 | sg = sg_next(sg); | |
448 | dma_addr = sg_dma_address(sg); | |
449 | dma_len = sg_dma_len(sg); | |
450 | } | |
451 | ||
1d090624 | 452 | if (length <= page_size) { |
edd10d33 | 453 | iod->first_dma = dma_addr; |
69d2b571 | 454 | return true; |
e025344c SMM |
455 | } |
456 | ||
1d090624 | 457 | nprps = DIV_ROUND_UP(length, page_size); |
99802a7a MW |
458 | if (nprps <= (256 / 8)) { |
459 | pool = dev->prp_small_pool; | |
eca18b23 | 460 | iod->npages = 0; |
99802a7a MW |
461 | } else { |
462 | pool = dev->prp_page_pool; | |
eca18b23 | 463 | iod->npages = 1; |
99802a7a MW |
464 | } |
465 | ||
69d2b571 | 466 | prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); |
b77954cb | 467 | if (!prp_list) { |
edd10d33 | 468 | iod->first_dma = dma_addr; |
eca18b23 | 469 | iod->npages = -1; |
69d2b571 | 470 | return false; |
b77954cb | 471 | } |
eca18b23 MW |
472 | list[0] = prp_list; |
473 | iod->first_dma = prp_dma; | |
e025344c SMM |
474 | i = 0; |
475 | for (;;) { | |
1d090624 | 476 | if (i == page_size >> 3) { |
e025344c | 477 | __le64 *old_prp_list = prp_list; |
69d2b571 | 478 | prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); |
eca18b23 | 479 | if (!prp_list) |
69d2b571 | 480 | return false; |
eca18b23 | 481 | list[iod->npages++] = prp_list; |
7523d834 MW |
482 | prp_list[0] = old_prp_list[i - 1]; |
483 | old_prp_list[i - 1] = cpu_to_le64(prp_dma); | |
484 | i = 1; | |
e025344c SMM |
485 | } |
486 | prp_list[i++] = cpu_to_le64(dma_addr); | |
1d090624 KB |
487 | dma_len -= page_size; |
488 | dma_addr += page_size; | |
489 | length -= page_size; | |
e025344c SMM |
490 | if (length <= 0) |
491 | break; | |
492 | if (dma_len > 0) | |
493 | continue; | |
494 | BUG_ON(dma_len < 0); | |
495 | sg = sg_next(sg); | |
496 | dma_addr = sg_dma_address(sg); | |
497 | dma_len = sg_dma_len(sg); | |
ff22b54f MW |
498 | } |
499 | ||
69d2b571 | 500 | return true; |
ff22b54f MW |
501 | } |
502 | ||
f4800d6d | 503 | static int nvme_map_data(struct nvme_dev *dev, struct request *req, |
03b5929e | 504 | unsigned size, struct nvme_command *cmnd) |
d29ec824 | 505 | { |
f4800d6d | 506 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
ba1ca37e CH |
507 | struct request_queue *q = req->q; |
508 | enum dma_data_direction dma_dir = rq_data_dir(req) ? | |
509 | DMA_TO_DEVICE : DMA_FROM_DEVICE; | |
510 | int ret = BLK_MQ_RQ_QUEUE_ERROR; | |
d29ec824 | 511 | |
f9d03f96 | 512 | sg_init_table(iod->sg, blk_rq_nr_phys_segments(req)); |
ba1ca37e CH |
513 | iod->nents = blk_rq_map_sg(q, req, iod->sg); |
514 | if (!iod->nents) | |
515 | goto out; | |
d29ec824 | 516 | |
ba1ca37e | 517 | ret = BLK_MQ_RQ_QUEUE_BUSY; |
2b6b535d MFO |
518 | if (!dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, dma_dir, |
519 | DMA_ATTR_NO_WARN)) | |
ba1ca37e | 520 | goto out; |
d29ec824 | 521 | |
03b5929e | 522 | if (!nvme_setup_prps(dev, req, size)) |
ba1ca37e | 523 | goto out_unmap; |
0e5e4f0e | 524 | |
ba1ca37e CH |
525 | ret = BLK_MQ_RQ_QUEUE_ERROR; |
526 | if (blk_integrity_rq(req)) { | |
527 | if (blk_rq_count_integrity_sg(q, req->bio) != 1) | |
528 | goto out_unmap; | |
0e5e4f0e | 529 | |
bf684057 CH |
530 | sg_init_table(&iod->meta_sg, 1); |
531 | if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1) | |
ba1ca37e | 532 | goto out_unmap; |
0e5e4f0e | 533 | |
ba1ca37e CH |
534 | if (rq_data_dir(req)) |
535 | nvme_dif_remap(req, nvme_dif_prep); | |
0e5e4f0e | 536 | |
bf684057 | 537 | if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir)) |
ba1ca37e | 538 | goto out_unmap; |
d29ec824 | 539 | } |
00df5cb4 | 540 | |
eb793e2c CH |
541 | cmnd->rw.dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg)); |
542 | cmnd->rw.dptr.prp2 = cpu_to_le64(iod->first_dma); | |
ba1ca37e | 543 | if (blk_integrity_rq(req)) |
bf684057 | 544 | cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg)); |
ba1ca37e | 545 | return BLK_MQ_RQ_QUEUE_OK; |
00df5cb4 | 546 | |
ba1ca37e CH |
547 | out_unmap: |
548 | dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); | |
549 | out: | |
550 | return ret; | |
00df5cb4 MW |
551 | } |
552 | ||
f4800d6d | 553 | static void nvme_unmap_data(struct nvme_dev *dev, struct request *req) |
b60503ba | 554 | { |
f4800d6d | 555 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
d4f6c3ab CH |
556 | enum dma_data_direction dma_dir = rq_data_dir(req) ? |
557 | DMA_TO_DEVICE : DMA_FROM_DEVICE; | |
558 | ||
559 | if (iod->nents) { | |
560 | dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); | |
561 | if (blk_integrity_rq(req)) { | |
562 | if (!rq_data_dir(req)) | |
563 | nvme_dif_remap(req, nvme_dif_complete); | |
bf684057 | 564 | dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir); |
e1e5e564 | 565 | } |
e19b127f | 566 | } |
e1e5e564 | 567 | |
f9d03f96 | 568 | nvme_cleanup_cmd(req); |
f4800d6d | 569 | nvme_free_iod(dev, req); |
d4f6c3ab | 570 | } |
b60503ba | 571 | |
d29ec824 CH |
572 | /* |
573 | * NOTE: ns is NULL when called on the admin queue. | |
574 | */ | |
a4aea562 MB |
575 | static int nvme_queue_rq(struct blk_mq_hw_ctx *hctx, |
576 | const struct blk_mq_queue_data *bd) | |
edd10d33 | 577 | { |
a4aea562 MB |
578 | struct nvme_ns *ns = hctx->queue->queuedata; |
579 | struct nvme_queue *nvmeq = hctx->driver_data; | |
d29ec824 | 580 | struct nvme_dev *dev = nvmeq->dev; |
a4aea562 | 581 | struct request *req = bd->rq; |
ba1ca37e | 582 | struct nvme_command cmnd; |
58b45602 | 583 | unsigned map_len; |
ba1ca37e | 584 | int ret = BLK_MQ_RQ_QUEUE_OK; |
edd10d33 | 585 | |
e1e5e564 KB |
586 | /* |
587 | * If formated with metadata, require the block layer provide a buffer | |
588 | * unless this namespace is formated such that the metadata can be | |
589 | * stripped/generated by the controller with PRACT=1. | |
590 | */ | |
d29ec824 | 591 | if (ns && ns->ms && !blk_integrity_rq(req)) { |
71feb364 KB |
592 | if (!(ns->pi_type && ns->ms == 8) && |
593 | req->cmd_type != REQ_TYPE_DRV_PRIV) { | |
eee417b0 | 594 | blk_mq_end_request(req, -EFAULT); |
e1e5e564 KB |
595 | return BLK_MQ_RQ_QUEUE_OK; |
596 | } | |
597 | } | |
598 | ||
f9d03f96 | 599 | ret = nvme_setup_cmd(ns, req, &cmnd); |
bac0000a | 600 | if (ret != BLK_MQ_RQ_QUEUE_OK) |
f4800d6d | 601 | return ret; |
a4aea562 | 602 | |
f9d03f96 CH |
603 | map_len = nvme_map_len(req); |
604 | ret = nvme_init_iod(req, map_len, dev); | |
bac0000a | 605 | if (ret != BLK_MQ_RQ_QUEUE_OK) |
f9d03f96 | 606 | goto out_free_cmd; |
a4aea562 | 607 | |
f9d03f96 | 608 | if (blk_rq_nr_phys_segments(req)) |
03b5929e | 609 | ret = nvme_map_data(dev, req, map_len, &cmnd); |
a4aea562 | 610 | |
bac0000a | 611 | if (ret != BLK_MQ_RQ_QUEUE_OK) |
f9d03f96 | 612 | goto out_cleanup_iod; |
a4aea562 | 613 | |
aae239e1 | 614 | blk_mq_start_request(req); |
a4aea562 | 615 | |
ba1ca37e | 616 | spin_lock_irq(&nvmeq->q_lock); |
ae1fba20 | 617 | if (unlikely(nvmeq->cq_vector < 0)) { |
69d9a99c KB |
618 | if (ns && !test_bit(NVME_NS_DEAD, &ns->flags)) |
619 | ret = BLK_MQ_RQ_QUEUE_BUSY; | |
620 | else | |
621 | ret = BLK_MQ_RQ_QUEUE_ERROR; | |
ae1fba20 | 622 | spin_unlock_irq(&nvmeq->q_lock); |
f9d03f96 | 623 | goto out_cleanup_iod; |
ae1fba20 | 624 | } |
ba1ca37e | 625 | __nvme_submit_cmd(nvmeq, &cmnd); |
a4aea562 MB |
626 | nvme_process_cq(nvmeq); |
627 | spin_unlock_irq(&nvmeq->q_lock); | |
628 | return BLK_MQ_RQ_QUEUE_OK; | |
f9d03f96 | 629 | out_cleanup_iod: |
f4800d6d | 630 | nvme_free_iod(dev, req); |
f9d03f96 CH |
631 | out_free_cmd: |
632 | nvme_cleanup_cmd(req); | |
ba1ca37e | 633 | return ret; |
b60503ba | 634 | } |
e1e5e564 | 635 | |
eee417b0 CH |
636 | static void nvme_complete_rq(struct request *req) |
637 | { | |
f4800d6d CH |
638 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
639 | struct nvme_dev *dev = iod->nvmeq->dev; | |
eee417b0 | 640 | int error = 0; |
e1e5e564 | 641 | |
f4800d6d | 642 | nvme_unmap_data(dev, req); |
e1e5e564 | 643 | |
eee417b0 CH |
644 | if (unlikely(req->errors)) { |
645 | if (nvme_req_needs_retry(req, req->errors)) { | |
f80ec966 | 646 | req->retries++; |
eee417b0 CH |
647 | nvme_requeue_req(req); |
648 | return; | |
e1e5e564 | 649 | } |
1974b1ae | 650 | |
eee417b0 CH |
651 | if (req->cmd_type == REQ_TYPE_DRV_PRIV) |
652 | error = req->errors; | |
653 | else | |
654 | error = nvme_error_status(req->errors); | |
655 | } | |
a4aea562 | 656 | |
f4800d6d | 657 | if (unlikely(iod->aborted)) { |
1b3c47c1 | 658 | dev_warn(dev->ctrl.device, |
eee417b0 CH |
659 | "completing aborted command with status: %04x\n", |
660 | req->errors); | |
661 | } | |
a4aea562 | 662 | |
eee417b0 | 663 | blk_mq_end_request(req, error); |
b60503ba MW |
664 | } |
665 | ||
d783e0bd MR |
666 | /* We read the CQE phase first to check if the rest of the entry is valid */ |
667 | static inline bool nvme_cqe_valid(struct nvme_queue *nvmeq, u16 head, | |
668 | u16 phase) | |
669 | { | |
670 | return (le16_to_cpu(nvmeq->cqes[head].status) & 1) == phase; | |
671 | } | |
672 | ||
a0fa9647 | 673 | static void __nvme_process_cq(struct nvme_queue *nvmeq, unsigned int *tag) |
b60503ba | 674 | { |
82123460 | 675 | u16 head, phase; |
b60503ba | 676 | |
b60503ba | 677 | head = nvmeq->cq_head; |
82123460 | 678 | phase = nvmeq->cq_phase; |
b60503ba | 679 | |
d783e0bd | 680 | while (nvme_cqe_valid(nvmeq, head, phase)) { |
b60503ba | 681 | struct nvme_completion cqe = nvmeq->cqes[head]; |
eee417b0 | 682 | struct request *req; |
adf68f21 | 683 | |
b60503ba MW |
684 | if (++head == nvmeq->q_depth) { |
685 | head = 0; | |
82123460 | 686 | phase = !phase; |
b60503ba | 687 | } |
adf68f21 | 688 | |
a0fa9647 JA |
689 | if (tag && *tag == cqe.command_id) |
690 | *tag = -1; | |
adf68f21 | 691 | |
aae239e1 | 692 | if (unlikely(cqe.command_id >= nvmeq->q_depth)) { |
1b3c47c1 | 693 | dev_warn(nvmeq->dev->ctrl.device, |
aae239e1 CH |
694 | "invalid id %d completed on queue %d\n", |
695 | cqe.command_id, le16_to_cpu(cqe.sq_id)); | |
696 | continue; | |
697 | } | |
698 | ||
adf68f21 CH |
699 | /* |
700 | * AEN requests are special as they don't time out and can | |
701 | * survive any kind of queue freeze and often don't respond to | |
702 | * aborts. We don't even bother to allocate a struct request | |
703 | * for them but rather special case them here. | |
704 | */ | |
705 | if (unlikely(nvmeq->qid == 0 && | |
706 | cqe.command_id >= NVME_AQ_BLKMQ_DEPTH)) { | |
7bf58533 CH |
707 | nvme_complete_async_event(&nvmeq->dev->ctrl, |
708 | cqe.status, &cqe.result); | |
adf68f21 CH |
709 | continue; |
710 | } | |
711 | ||
eee417b0 | 712 | req = blk_mq_tag_to_rq(*nvmeq->tags, cqe.command_id); |
d49187e9 | 713 | nvme_req(req)->result = cqe.result; |
d783e0bd | 714 | blk_mq_complete_request(req, le16_to_cpu(cqe.status) >> 1); |
eee417b0 | 715 | |
b60503ba MW |
716 | } |
717 | ||
718 | /* If the controller ignores the cq head doorbell and continuously | |
719 | * writes to the queue, it is theoretically possible to wrap around | |
720 | * the queue twice and mistakenly return IRQ_NONE. Linux only | |
721 | * requires that 0.1% of your interrupts are handled, so this isn't | |
722 | * a big problem. | |
723 | */ | |
82123460 | 724 | if (head == nvmeq->cq_head && phase == nvmeq->cq_phase) |
a0fa9647 | 725 | return; |
b60503ba | 726 | |
604e8c8d KB |
727 | if (likely(nvmeq->cq_vector >= 0)) |
728 | writel(head, nvmeq->q_db + nvmeq->dev->db_stride); | |
b60503ba | 729 | nvmeq->cq_head = head; |
82123460 | 730 | nvmeq->cq_phase = phase; |
b60503ba | 731 | |
e9539f47 | 732 | nvmeq->cqe_seen = 1; |
a0fa9647 JA |
733 | } |
734 | ||
735 | static void nvme_process_cq(struct nvme_queue *nvmeq) | |
736 | { | |
737 | __nvme_process_cq(nvmeq, NULL); | |
b60503ba MW |
738 | } |
739 | ||
740 | static irqreturn_t nvme_irq(int irq, void *data) | |
58ffacb5 MW |
741 | { |
742 | irqreturn_t result; | |
743 | struct nvme_queue *nvmeq = data; | |
744 | spin_lock(&nvmeq->q_lock); | |
e9539f47 MW |
745 | nvme_process_cq(nvmeq); |
746 | result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE; | |
747 | nvmeq->cqe_seen = 0; | |
58ffacb5 MW |
748 | spin_unlock(&nvmeq->q_lock); |
749 | return result; | |
750 | } | |
751 | ||
752 | static irqreturn_t nvme_irq_check(int irq, void *data) | |
753 | { | |
754 | struct nvme_queue *nvmeq = data; | |
d783e0bd MR |
755 | if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase)) |
756 | return IRQ_WAKE_THREAD; | |
757 | return IRQ_NONE; | |
58ffacb5 MW |
758 | } |
759 | ||
a0fa9647 JA |
760 | static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag) |
761 | { | |
762 | struct nvme_queue *nvmeq = hctx->driver_data; | |
763 | ||
d783e0bd | 764 | if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase)) { |
a0fa9647 JA |
765 | spin_lock_irq(&nvmeq->q_lock); |
766 | __nvme_process_cq(nvmeq, &tag); | |
767 | spin_unlock_irq(&nvmeq->q_lock); | |
768 | ||
769 | if (tag == -1) | |
770 | return 1; | |
771 | } | |
772 | ||
773 | return 0; | |
774 | } | |
775 | ||
f866fc42 | 776 | static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl, int aer_idx) |
b60503ba | 777 | { |
f866fc42 | 778 | struct nvme_dev *dev = to_nvme_dev(ctrl); |
9396dec9 | 779 | struct nvme_queue *nvmeq = dev->queues[0]; |
a4aea562 | 780 | struct nvme_command c; |
b60503ba | 781 | |
a4aea562 MB |
782 | memset(&c, 0, sizeof(c)); |
783 | c.common.opcode = nvme_admin_async_event; | |
f866fc42 | 784 | c.common.command_id = NVME_AQ_BLKMQ_DEPTH + aer_idx; |
3c0cf138 | 785 | |
9396dec9 | 786 | spin_lock_irq(&nvmeq->q_lock); |
f866fc42 | 787 | __nvme_submit_cmd(nvmeq, &c); |
9396dec9 | 788 | spin_unlock_irq(&nvmeq->q_lock); |
f705f837 CH |
789 | } |
790 | ||
b60503ba | 791 | static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) |
f705f837 | 792 | { |
b60503ba MW |
793 | struct nvme_command c; |
794 | ||
795 | memset(&c, 0, sizeof(c)); | |
796 | c.delete_queue.opcode = opcode; | |
797 | c.delete_queue.qid = cpu_to_le16(id); | |
798 | ||
1c63dc66 | 799 | return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); |
b60503ba MW |
800 | } |
801 | ||
b60503ba MW |
802 | static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, |
803 | struct nvme_queue *nvmeq) | |
804 | { | |
b60503ba MW |
805 | struct nvme_command c; |
806 | int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED; | |
807 | ||
d29ec824 CH |
808 | /* |
809 | * Note: we (ab)use the fact the the prp fields survive if no data | |
810 | * is attached to the request. | |
811 | */ | |
b60503ba MW |
812 | memset(&c, 0, sizeof(c)); |
813 | c.create_cq.opcode = nvme_admin_create_cq; | |
814 | c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); | |
815 | c.create_cq.cqid = cpu_to_le16(qid); | |
816 | c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); | |
817 | c.create_cq.cq_flags = cpu_to_le16(flags); | |
818 | c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector); | |
819 | ||
1c63dc66 | 820 | return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); |
b60503ba MW |
821 | } |
822 | ||
823 | static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, | |
824 | struct nvme_queue *nvmeq) | |
825 | { | |
b60503ba MW |
826 | struct nvme_command c; |
827 | int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM; | |
828 | ||
d29ec824 CH |
829 | /* |
830 | * Note: we (ab)use the fact the the prp fields survive if no data | |
831 | * is attached to the request. | |
832 | */ | |
b60503ba MW |
833 | memset(&c, 0, sizeof(c)); |
834 | c.create_sq.opcode = nvme_admin_create_sq; | |
835 | c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); | |
836 | c.create_sq.sqid = cpu_to_le16(qid); | |
837 | c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); | |
838 | c.create_sq.sq_flags = cpu_to_le16(flags); | |
839 | c.create_sq.cqid = cpu_to_le16(qid); | |
840 | ||
1c63dc66 | 841 | return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); |
b60503ba MW |
842 | } |
843 | ||
844 | static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) | |
845 | { | |
846 | return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); | |
847 | } | |
848 | ||
849 | static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) | |
850 | { | |
851 | return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); | |
852 | } | |
853 | ||
e7a2a87d | 854 | static void abort_endio(struct request *req, int error) |
bc5fc7e4 | 855 | { |
f4800d6d CH |
856 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
857 | struct nvme_queue *nvmeq = iod->nvmeq; | |
e7a2a87d | 858 | u16 status = req->errors; |
e44ac588 | 859 | |
1cb3cce5 | 860 | dev_warn(nvmeq->dev->ctrl.device, "Abort status: 0x%x", status); |
e7a2a87d | 861 | atomic_inc(&nvmeq->dev->ctrl.abort_limit); |
e7a2a87d | 862 | blk_mq_free_request(req); |
bc5fc7e4 MW |
863 | } |
864 | ||
31c7c7d2 | 865 | static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved) |
c30341dc | 866 | { |
f4800d6d CH |
867 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
868 | struct nvme_queue *nvmeq = iod->nvmeq; | |
c30341dc | 869 | struct nvme_dev *dev = nvmeq->dev; |
a4aea562 | 870 | struct request *abort_req; |
a4aea562 | 871 | struct nvme_command cmd; |
c30341dc | 872 | |
31c7c7d2 | 873 | /* |
fd634f41 CH |
874 | * Shutdown immediately if controller times out while starting. The |
875 | * reset work will see the pci device disabled when it gets the forced | |
876 | * cancellation error. All outstanding requests are completed on | |
877 | * shutdown, so we return BLK_EH_HANDLED. | |
878 | */ | |
bb8d261e | 879 | if (dev->ctrl.state == NVME_CTRL_RESETTING) { |
1b3c47c1 | 880 | dev_warn(dev->ctrl.device, |
fd634f41 CH |
881 | "I/O %d QID %d timeout, disable controller\n", |
882 | req->tag, nvmeq->qid); | |
a5cdb68c | 883 | nvme_dev_disable(dev, false); |
fd634f41 CH |
884 | req->errors = NVME_SC_CANCELLED; |
885 | return BLK_EH_HANDLED; | |
c30341dc KB |
886 | } |
887 | ||
fd634f41 CH |
888 | /* |
889 | * Shutdown the controller immediately and schedule a reset if the | |
890 | * command was already aborted once before and still hasn't been | |
891 | * returned to the driver, or if this is the admin queue. | |
31c7c7d2 | 892 | */ |
f4800d6d | 893 | if (!nvmeq->qid || iod->aborted) { |
1b3c47c1 | 894 | dev_warn(dev->ctrl.device, |
e1569a16 KB |
895 | "I/O %d QID %d timeout, reset controller\n", |
896 | req->tag, nvmeq->qid); | |
a5cdb68c | 897 | nvme_dev_disable(dev, false); |
c5f6ce97 | 898 | nvme_reset(dev); |
c30341dc | 899 | |
e1569a16 KB |
900 | /* |
901 | * Mark the request as handled, since the inline shutdown | |
902 | * forces all outstanding requests to complete. | |
903 | */ | |
904 | req->errors = NVME_SC_CANCELLED; | |
905 | return BLK_EH_HANDLED; | |
c30341dc | 906 | } |
c30341dc | 907 | |
f4800d6d | 908 | iod->aborted = 1; |
c30341dc | 909 | |
e7a2a87d | 910 | if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) { |
6bf25d16 | 911 | atomic_inc(&dev->ctrl.abort_limit); |
31c7c7d2 | 912 | return BLK_EH_RESET_TIMER; |
6bf25d16 | 913 | } |
a4aea562 | 914 | |
c30341dc KB |
915 | memset(&cmd, 0, sizeof(cmd)); |
916 | cmd.abort.opcode = nvme_admin_abort_cmd; | |
a4aea562 | 917 | cmd.abort.cid = req->tag; |
c30341dc | 918 | cmd.abort.sqid = cpu_to_le16(nvmeq->qid); |
c30341dc | 919 | |
1b3c47c1 SG |
920 | dev_warn(nvmeq->dev->ctrl.device, |
921 | "I/O %d QID %d timeout, aborting\n", | |
922 | req->tag, nvmeq->qid); | |
e7a2a87d CH |
923 | |
924 | abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd, | |
eb71f435 | 925 | BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); |
e7a2a87d CH |
926 | if (IS_ERR(abort_req)) { |
927 | atomic_inc(&dev->ctrl.abort_limit); | |
928 | return BLK_EH_RESET_TIMER; | |
929 | } | |
930 | ||
931 | abort_req->timeout = ADMIN_TIMEOUT; | |
932 | abort_req->end_io_data = NULL; | |
933 | blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio); | |
c30341dc | 934 | |
31c7c7d2 CH |
935 | /* |
936 | * The aborted req will be completed on receiving the abort req. | |
937 | * We enable the timer again. If hit twice, it'll cause a device reset, | |
938 | * as the device then is in a faulty state. | |
939 | */ | |
940 | return BLK_EH_RESET_TIMER; | |
c30341dc KB |
941 | } |
942 | ||
a4aea562 MB |
943 | static void nvme_free_queue(struct nvme_queue *nvmeq) |
944 | { | |
9e866774 MW |
945 | dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth), |
946 | (void *)nvmeq->cqes, nvmeq->cq_dma_addr); | |
8ffaadf7 JD |
947 | if (nvmeq->sq_cmds) |
948 | dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth), | |
9e866774 MW |
949 | nvmeq->sq_cmds, nvmeq->sq_dma_addr); |
950 | kfree(nvmeq); | |
951 | } | |
952 | ||
a1a5ef99 | 953 | static void nvme_free_queues(struct nvme_dev *dev, int lowest) |
22404274 KB |
954 | { |
955 | int i; | |
956 | ||
a1a5ef99 | 957 | for (i = dev->queue_count - 1; i >= lowest; i--) { |
a4aea562 | 958 | struct nvme_queue *nvmeq = dev->queues[i]; |
22404274 | 959 | dev->queue_count--; |
a4aea562 | 960 | dev->queues[i] = NULL; |
f435c282 | 961 | nvme_free_queue(nvmeq); |
121c7ad4 | 962 | } |
22404274 KB |
963 | } |
964 | ||
4d115420 KB |
965 | /** |
966 | * nvme_suspend_queue - put queue into suspended state | |
967 | * @nvmeq - queue to suspend | |
4d115420 KB |
968 | */ |
969 | static int nvme_suspend_queue(struct nvme_queue *nvmeq) | |
b60503ba | 970 | { |
2b25d981 | 971 | int vector; |
b60503ba | 972 | |
a09115b2 | 973 | spin_lock_irq(&nvmeq->q_lock); |
2b25d981 KB |
974 | if (nvmeq->cq_vector == -1) { |
975 | spin_unlock_irq(&nvmeq->q_lock); | |
976 | return 1; | |
977 | } | |
dca51e78 | 978 | vector = nvmeq_irq(nvmeq); |
42f61420 | 979 | nvmeq->dev->online_queues--; |
2b25d981 | 980 | nvmeq->cq_vector = -1; |
a09115b2 MW |
981 | spin_unlock_irq(&nvmeq->q_lock); |
982 | ||
1c63dc66 | 983 | if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q) |
25646264 | 984 | blk_mq_stop_hw_queues(nvmeq->dev->ctrl.admin_q); |
6df3dbc8 | 985 | |
aba2080f | 986 | free_irq(vector, nvmeq); |
b60503ba | 987 | |
4d115420 KB |
988 | return 0; |
989 | } | |
b60503ba | 990 | |
a5cdb68c | 991 | static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown) |
4d115420 | 992 | { |
a5cdb68c | 993 | struct nvme_queue *nvmeq = dev->queues[0]; |
4d115420 KB |
994 | |
995 | if (!nvmeq) | |
996 | return; | |
997 | if (nvme_suspend_queue(nvmeq)) | |
998 | return; | |
999 | ||
a5cdb68c KB |
1000 | if (shutdown) |
1001 | nvme_shutdown_ctrl(&dev->ctrl); | |
1002 | else | |
1003 | nvme_disable_ctrl(&dev->ctrl, lo_hi_readq( | |
1004 | dev->bar + NVME_REG_CAP)); | |
07836e65 KB |
1005 | |
1006 | spin_lock_irq(&nvmeq->q_lock); | |
1007 | nvme_process_cq(nvmeq); | |
1008 | spin_unlock_irq(&nvmeq->q_lock); | |
b60503ba MW |
1009 | } |
1010 | ||
8ffaadf7 JD |
1011 | static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues, |
1012 | int entry_size) | |
1013 | { | |
1014 | int q_depth = dev->q_depth; | |
5fd4ce1b CH |
1015 | unsigned q_size_aligned = roundup(q_depth * entry_size, |
1016 | dev->ctrl.page_size); | |
8ffaadf7 JD |
1017 | |
1018 | if (q_size_aligned * nr_io_queues > dev->cmb_size) { | |
c45f5c99 | 1019 | u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues); |
5fd4ce1b | 1020 | mem_per_q = round_down(mem_per_q, dev->ctrl.page_size); |
c45f5c99 | 1021 | q_depth = div_u64(mem_per_q, entry_size); |
8ffaadf7 JD |
1022 | |
1023 | /* | |
1024 | * Ensure the reduced q_depth is above some threshold where it | |
1025 | * would be better to map queues in system memory with the | |
1026 | * original depth | |
1027 | */ | |
1028 | if (q_depth < 64) | |
1029 | return -ENOMEM; | |
1030 | } | |
1031 | ||
1032 | return q_depth; | |
1033 | } | |
1034 | ||
1035 | static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq, | |
1036 | int qid, int depth) | |
1037 | { | |
1038 | if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz)) { | |
5fd4ce1b CH |
1039 | unsigned offset = (qid - 1) * roundup(SQ_SIZE(depth), |
1040 | dev->ctrl.page_size); | |
8ffaadf7 JD |
1041 | nvmeq->sq_dma_addr = dev->cmb_dma_addr + offset; |
1042 | nvmeq->sq_cmds_io = dev->cmb + offset; | |
1043 | } else { | |
1044 | nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth), | |
1045 | &nvmeq->sq_dma_addr, GFP_KERNEL); | |
1046 | if (!nvmeq->sq_cmds) | |
1047 | return -ENOMEM; | |
1048 | } | |
1049 | ||
1050 | return 0; | |
1051 | } | |
1052 | ||
b60503ba | 1053 | static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid, |
2b25d981 | 1054 | int depth) |
b60503ba | 1055 | { |
a4aea562 | 1056 | struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq), GFP_KERNEL); |
b60503ba MW |
1057 | if (!nvmeq) |
1058 | return NULL; | |
1059 | ||
e75ec752 | 1060 | nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth), |
4d51abf9 | 1061 | &nvmeq->cq_dma_addr, GFP_KERNEL); |
b60503ba MW |
1062 | if (!nvmeq->cqes) |
1063 | goto free_nvmeq; | |
b60503ba | 1064 | |
8ffaadf7 | 1065 | if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth)) |
b60503ba MW |
1066 | goto free_cqdma; |
1067 | ||
e75ec752 | 1068 | nvmeq->q_dmadev = dev->dev; |
091b6092 | 1069 | nvmeq->dev = dev; |
3193f07b | 1070 | snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d", |
1c63dc66 | 1071 | dev->ctrl.instance, qid); |
b60503ba MW |
1072 | spin_lock_init(&nvmeq->q_lock); |
1073 | nvmeq->cq_head = 0; | |
82123460 | 1074 | nvmeq->cq_phase = 1; |
b80d5ccc | 1075 | nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; |
b60503ba | 1076 | nvmeq->q_depth = depth; |
c30341dc | 1077 | nvmeq->qid = qid; |
758dd7fd | 1078 | nvmeq->cq_vector = -1; |
a4aea562 | 1079 | dev->queues[qid] = nvmeq; |
36a7e993 JD |
1080 | dev->queue_count++; |
1081 | ||
b60503ba MW |
1082 | return nvmeq; |
1083 | ||
1084 | free_cqdma: | |
e75ec752 | 1085 | dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes, |
b60503ba MW |
1086 | nvmeq->cq_dma_addr); |
1087 | free_nvmeq: | |
1088 | kfree(nvmeq); | |
1089 | return NULL; | |
1090 | } | |
1091 | ||
dca51e78 | 1092 | static int queue_request_irq(struct nvme_queue *nvmeq) |
3001082c | 1093 | { |
58ffacb5 | 1094 | if (use_threaded_interrupts) |
dca51e78 CH |
1095 | return request_threaded_irq(nvmeq_irq(nvmeq), nvme_irq_check, |
1096 | nvme_irq, IRQF_SHARED, nvmeq->irqname, nvmeq); | |
1097 | else | |
1098 | return request_irq(nvmeq_irq(nvmeq), nvme_irq, IRQF_SHARED, | |
1099 | nvmeq->irqname, nvmeq); | |
3001082c MW |
1100 | } |
1101 | ||
22404274 | 1102 | static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) |
b60503ba | 1103 | { |
22404274 | 1104 | struct nvme_dev *dev = nvmeq->dev; |
b60503ba | 1105 | |
7be50e93 | 1106 | spin_lock_irq(&nvmeq->q_lock); |
22404274 KB |
1107 | nvmeq->sq_tail = 0; |
1108 | nvmeq->cq_head = 0; | |
1109 | nvmeq->cq_phase = 1; | |
b80d5ccc | 1110 | nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; |
22404274 | 1111 | memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth)); |
42f61420 | 1112 | dev->online_queues++; |
7be50e93 | 1113 | spin_unlock_irq(&nvmeq->q_lock); |
22404274 KB |
1114 | } |
1115 | ||
1116 | static int nvme_create_queue(struct nvme_queue *nvmeq, int qid) | |
1117 | { | |
1118 | struct nvme_dev *dev = nvmeq->dev; | |
1119 | int result; | |
3f85d50b | 1120 | |
2b25d981 | 1121 | nvmeq->cq_vector = qid - 1; |
b60503ba MW |
1122 | result = adapter_alloc_cq(dev, qid, nvmeq); |
1123 | if (result < 0) | |
22404274 | 1124 | return result; |
b60503ba MW |
1125 | |
1126 | result = adapter_alloc_sq(dev, qid, nvmeq); | |
1127 | if (result < 0) | |
1128 | goto release_cq; | |
1129 | ||
dca51e78 | 1130 | result = queue_request_irq(nvmeq); |
b60503ba MW |
1131 | if (result < 0) |
1132 | goto release_sq; | |
1133 | ||
22404274 | 1134 | nvme_init_queue(nvmeq, qid); |
22404274 | 1135 | return result; |
b60503ba MW |
1136 | |
1137 | release_sq: | |
1138 | adapter_delete_sq(dev, qid); | |
1139 | release_cq: | |
1140 | adapter_delete_cq(dev, qid); | |
22404274 | 1141 | return result; |
b60503ba MW |
1142 | } |
1143 | ||
a4aea562 | 1144 | static struct blk_mq_ops nvme_mq_admin_ops = { |
d29ec824 | 1145 | .queue_rq = nvme_queue_rq, |
eee417b0 | 1146 | .complete = nvme_complete_rq, |
a4aea562 | 1147 | .init_hctx = nvme_admin_init_hctx, |
4af0e21c | 1148 | .exit_hctx = nvme_admin_exit_hctx, |
a4aea562 MB |
1149 | .init_request = nvme_admin_init_request, |
1150 | .timeout = nvme_timeout, | |
1151 | }; | |
1152 | ||
1153 | static struct blk_mq_ops nvme_mq_ops = { | |
1154 | .queue_rq = nvme_queue_rq, | |
eee417b0 | 1155 | .complete = nvme_complete_rq, |
a4aea562 MB |
1156 | .init_hctx = nvme_init_hctx, |
1157 | .init_request = nvme_init_request, | |
dca51e78 | 1158 | .map_queues = nvme_pci_map_queues, |
a4aea562 | 1159 | .timeout = nvme_timeout, |
a0fa9647 | 1160 | .poll = nvme_poll, |
a4aea562 MB |
1161 | }; |
1162 | ||
ea191d2f KB |
1163 | static void nvme_dev_remove_admin(struct nvme_dev *dev) |
1164 | { | |
1c63dc66 | 1165 | if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) { |
69d9a99c KB |
1166 | /* |
1167 | * If the controller was reset during removal, it's possible | |
1168 | * user requests may be waiting on a stopped queue. Start the | |
1169 | * queue to flush these to completion. | |
1170 | */ | |
1171 | blk_mq_start_stopped_hw_queues(dev->ctrl.admin_q, true); | |
1c63dc66 | 1172 | blk_cleanup_queue(dev->ctrl.admin_q); |
ea191d2f KB |
1173 | blk_mq_free_tag_set(&dev->admin_tagset); |
1174 | } | |
1175 | } | |
1176 | ||
a4aea562 MB |
1177 | static int nvme_alloc_admin_tags(struct nvme_dev *dev) |
1178 | { | |
1c63dc66 | 1179 | if (!dev->ctrl.admin_q) { |
a4aea562 MB |
1180 | dev->admin_tagset.ops = &nvme_mq_admin_ops; |
1181 | dev->admin_tagset.nr_hw_queues = 1; | |
e3e9d50c KB |
1182 | |
1183 | /* | |
1184 | * Subtract one to leave an empty queue entry for 'Full Queue' | |
1185 | * condition. See NVM-Express 1.2 specification, section 4.1.2. | |
1186 | */ | |
1187 | dev->admin_tagset.queue_depth = NVME_AQ_BLKMQ_DEPTH - 1; | |
a4aea562 | 1188 | dev->admin_tagset.timeout = ADMIN_TIMEOUT; |
e75ec752 | 1189 | dev->admin_tagset.numa_node = dev_to_node(dev->dev); |
ac3dd5bd | 1190 | dev->admin_tagset.cmd_size = nvme_cmd_size(dev); |
a4aea562 MB |
1191 | dev->admin_tagset.driver_data = dev; |
1192 | ||
1193 | if (blk_mq_alloc_tag_set(&dev->admin_tagset)) | |
1194 | return -ENOMEM; | |
1195 | ||
1c63dc66 CH |
1196 | dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset); |
1197 | if (IS_ERR(dev->ctrl.admin_q)) { | |
a4aea562 MB |
1198 | blk_mq_free_tag_set(&dev->admin_tagset); |
1199 | return -ENOMEM; | |
1200 | } | |
1c63dc66 | 1201 | if (!blk_get_queue(dev->ctrl.admin_q)) { |
ea191d2f | 1202 | nvme_dev_remove_admin(dev); |
1c63dc66 | 1203 | dev->ctrl.admin_q = NULL; |
ea191d2f KB |
1204 | return -ENODEV; |
1205 | } | |
0fb59cbc | 1206 | } else |
25646264 | 1207 | blk_mq_start_stopped_hw_queues(dev->ctrl.admin_q, true); |
a4aea562 MB |
1208 | |
1209 | return 0; | |
1210 | } | |
1211 | ||
8d85fce7 | 1212 | static int nvme_configure_admin_queue(struct nvme_dev *dev) |
b60503ba | 1213 | { |
ba47e386 | 1214 | int result; |
b60503ba | 1215 | u32 aqa; |
7a67cbea | 1216 | u64 cap = lo_hi_readq(dev->bar + NVME_REG_CAP); |
b60503ba MW |
1217 | struct nvme_queue *nvmeq; |
1218 | ||
8ef2074d | 1219 | dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ? |
dfbac8c7 KB |
1220 | NVME_CAP_NSSRC(cap) : 0; |
1221 | ||
7a67cbea CH |
1222 | if (dev->subsystem && |
1223 | (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO)) | |
1224 | writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS); | |
dfbac8c7 | 1225 | |
5fd4ce1b | 1226 | result = nvme_disable_ctrl(&dev->ctrl, cap); |
ba47e386 MW |
1227 | if (result < 0) |
1228 | return result; | |
b60503ba | 1229 | |
a4aea562 | 1230 | nvmeq = dev->queues[0]; |
cd638946 | 1231 | if (!nvmeq) { |
2b25d981 | 1232 | nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH); |
cd638946 KB |
1233 | if (!nvmeq) |
1234 | return -ENOMEM; | |
cd638946 | 1235 | } |
b60503ba MW |
1236 | |
1237 | aqa = nvmeq->q_depth - 1; | |
1238 | aqa |= aqa << 16; | |
1239 | ||
7a67cbea CH |
1240 | writel(aqa, dev->bar + NVME_REG_AQA); |
1241 | lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ); | |
1242 | lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ); | |
b60503ba | 1243 | |
5fd4ce1b | 1244 | result = nvme_enable_ctrl(&dev->ctrl, cap); |
025c557a | 1245 | if (result) |
d4875622 | 1246 | return result; |
a4aea562 | 1247 | |
2b25d981 | 1248 | nvmeq->cq_vector = 0; |
dca51e78 | 1249 | result = queue_request_irq(nvmeq); |
758dd7fd JD |
1250 | if (result) { |
1251 | nvmeq->cq_vector = -1; | |
d4875622 | 1252 | return result; |
758dd7fd | 1253 | } |
025c557a | 1254 | |
b60503ba MW |
1255 | return result; |
1256 | } | |
1257 | ||
c875a709 GP |
1258 | static bool nvme_should_reset(struct nvme_dev *dev, u32 csts) |
1259 | { | |
1260 | ||
1261 | /* If true, indicates loss of adapter communication, possibly by a | |
1262 | * NVMe Subsystem reset. | |
1263 | */ | |
1264 | bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO); | |
1265 | ||
1266 | /* If there is a reset ongoing, we shouldn't reset again. */ | |
1267 | if (work_busy(&dev->reset_work)) | |
1268 | return false; | |
1269 | ||
1270 | /* We shouldn't reset unless the controller is on fatal error state | |
1271 | * _or_ if we lost the communication with it. | |
1272 | */ | |
1273 | if (!(csts & NVME_CSTS_CFS) && !nssro) | |
1274 | return false; | |
1275 | ||
1276 | /* If PCI error recovery process is happening, we cannot reset or | |
1277 | * the recovery mechanism will surely fail. | |
1278 | */ | |
1279 | if (pci_channel_offline(to_pci_dev(dev->dev))) | |
1280 | return false; | |
1281 | ||
1282 | return true; | |
1283 | } | |
1284 | ||
d2a61918 AL |
1285 | static void nvme_warn_reset(struct nvme_dev *dev, u32 csts) |
1286 | { | |
1287 | /* Read a config register to help see what died. */ | |
1288 | u16 pci_status; | |
1289 | int result; | |
1290 | ||
1291 | result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS, | |
1292 | &pci_status); | |
1293 | if (result == PCIBIOS_SUCCESSFUL) | |
1294 | dev_warn(dev->dev, | |
1295 | "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n", | |
1296 | csts, pci_status); | |
1297 | else | |
1298 | dev_warn(dev->dev, | |
1299 | "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n", | |
1300 | csts, result); | |
1301 | } | |
1302 | ||
2d55cd5f | 1303 | static void nvme_watchdog_timer(unsigned long data) |
1fa6aead | 1304 | { |
2d55cd5f CH |
1305 | struct nvme_dev *dev = (struct nvme_dev *)data; |
1306 | u32 csts = readl(dev->bar + NVME_REG_CSTS); | |
1fa6aead | 1307 | |
c875a709 GP |
1308 | /* Skip controllers under certain specific conditions. */ |
1309 | if (nvme_should_reset(dev, csts)) { | |
c5f6ce97 | 1310 | if (!nvme_reset(dev)) |
d2a61918 | 1311 | nvme_warn_reset(dev, csts); |
2d55cd5f | 1312 | return; |
1fa6aead | 1313 | } |
2d55cd5f CH |
1314 | |
1315 | mod_timer(&dev->watchdog_timer, round_jiffies(jiffies + HZ)); | |
1fa6aead MW |
1316 | } |
1317 | ||
749941f2 | 1318 | static int nvme_create_io_queues(struct nvme_dev *dev) |
42f61420 | 1319 | { |
949928c1 | 1320 | unsigned i, max; |
749941f2 | 1321 | int ret = 0; |
42f61420 | 1322 | |
749941f2 CH |
1323 | for (i = dev->queue_count; i <= dev->max_qid; i++) { |
1324 | if (!nvme_alloc_queue(dev, i, dev->q_depth)) { | |
1325 | ret = -ENOMEM; | |
42f61420 | 1326 | break; |
749941f2 CH |
1327 | } |
1328 | } | |
42f61420 | 1329 | |
949928c1 KB |
1330 | max = min(dev->max_qid, dev->queue_count - 1); |
1331 | for (i = dev->online_queues; i <= max; i++) { | |
749941f2 | 1332 | ret = nvme_create_queue(dev->queues[i], i); |
d4875622 | 1333 | if (ret) |
42f61420 | 1334 | break; |
27e8166c | 1335 | } |
749941f2 CH |
1336 | |
1337 | /* | |
1338 | * Ignore failing Create SQ/CQ commands, we can continue with less | |
1339 | * than the desired aount of queues, and even a controller without | |
1340 | * I/O queues an still be used to issue admin commands. This might | |
1341 | * be useful to upgrade a buggy firmware for example. | |
1342 | */ | |
1343 | return ret >= 0 ? 0 : ret; | |
b60503ba MW |
1344 | } |
1345 | ||
202021c1 SB |
1346 | static ssize_t nvme_cmb_show(struct device *dev, |
1347 | struct device_attribute *attr, | |
1348 | char *buf) | |
1349 | { | |
1350 | struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); | |
1351 | ||
1352 | return snprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n", | |
1353 | ndev->cmbloc, ndev->cmbsz); | |
1354 | } | |
1355 | static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL); | |
1356 | ||
8ffaadf7 JD |
1357 | static void __iomem *nvme_map_cmb(struct nvme_dev *dev) |
1358 | { | |
1359 | u64 szu, size, offset; | |
8ffaadf7 JD |
1360 | resource_size_t bar_size; |
1361 | struct pci_dev *pdev = to_pci_dev(dev->dev); | |
1362 | void __iomem *cmb; | |
1363 | dma_addr_t dma_addr; | |
1364 | ||
7a67cbea | 1365 | dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ); |
8ffaadf7 JD |
1366 | if (!(NVME_CMB_SZ(dev->cmbsz))) |
1367 | return NULL; | |
202021c1 | 1368 | dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC); |
8ffaadf7 | 1369 | |
202021c1 SB |
1370 | if (!use_cmb_sqes) |
1371 | return NULL; | |
8ffaadf7 JD |
1372 | |
1373 | szu = (u64)1 << (12 + 4 * NVME_CMB_SZU(dev->cmbsz)); | |
1374 | size = szu * NVME_CMB_SZ(dev->cmbsz); | |
202021c1 SB |
1375 | offset = szu * NVME_CMB_OFST(dev->cmbloc); |
1376 | bar_size = pci_resource_len(pdev, NVME_CMB_BIR(dev->cmbloc)); | |
8ffaadf7 JD |
1377 | |
1378 | if (offset > bar_size) | |
1379 | return NULL; | |
1380 | ||
1381 | /* | |
1382 | * Controllers may support a CMB size larger than their BAR, | |
1383 | * for example, due to being behind a bridge. Reduce the CMB to | |
1384 | * the reported size of the BAR | |
1385 | */ | |
1386 | if (size > bar_size - offset) | |
1387 | size = bar_size - offset; | |
1388 | ||
202021c1 | 1389 | dma_addr = pci_resource_start(pdev, NVME_CMB_BIR(dev->cmbloc)) + offset; |
8ffaadf7 JD |
1390 | cmb = ioremap_wc(dma_addr, size); |
1391 | if (!cmb) | |
1392 | return NULL; | |
1393 | ||
1394 | dev->cmb_dma_addr = dma_addr; | |
1395 | dev->cmb_size = size; | |
1396 | return cmb; | |
1397 | } | |
1398 | ||
1399 | static inline void nvme_release_cmb(struct nvme_dev *dev) | |
1400 | { | |
1401 | if (dev->cmb) { | |
1402 | iounmap(dev->cmb); | |
1403 | dev->cmb = NULL; | |
1404 | } | |
1405 | } | |
1406 | ||
9d713c2b KB |
1407 | static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) |
1408 | { | |
b80d5ccc | 1409 | return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride); |
9d713c2b KB |
1410 | } |
1411 | ||
8d85fce7 | 1412 | static int nvme_setup_io_queues(struct nvme_dev *dev) |
b60503ba | 1413 | { |
a4aea562 | 1414 | struct nvme_queue *adminq = dev->queues[0]; |
e75ec752 | 1415 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
dca51e78 | 1416 | int result, nr_io_queues, size; |
b60503ba | 1417 | |
2800b8e7 | 1418 | nr_io_queues = num_online_cpus(); |
9a0be7ab CH |
1419 | result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues); |
1420 | if (result < 0) | |
1b23484b | 1421 | return result; |
9a0be7ab | 1422 | |
f5fa90dc | 1423 | if (nr_io_queues == 0) |
a5229050 | 1424 | return 0; |
b60503ba | 1425 | |
8ffaadf7 JD |
1426 | if (dev->cmb && NVME_CMB_SQS(dev->cmbsz)) { |
1427 | result = nvme_cmb_qdepth(dev, nr_io_queues, | |
1428 | sizeof(struct nvme_command)); | |
1429 | if (result > 0) | |
1430 | dev->q_depth = result; | |
1431 | else | |
1432 | nvme_release_cmb(dev); | |
1433 | } | |
1434 | ||
9d713c2b KB |
1435 | size = db_bar_size(dev, nr_io_queues); |
1436 | if (size > 8192) { | |
f1938f6e | 1437 | iounmap(dev->bar); |
9d713c2b KB |
1438 | do { |
1439 | dev->bar = ioremap(pci_resource_start(pdev, 0), size); | |
1440 | if (dev->bar) | |
1441 | break; | |
1442 | if (!--nr_io_queues) | |
1443 | return -ENOMEM; | |
1444 | size = db_bar_size(dev, nr_io_queues); | |
1445 | } while (1); | |
7a67cbea | 1446 | dev->dbs = dev->bar + 4096; |
5a92e700 | 1447 | adminq->q_db = dev->dbs; |
f1938f6e MW |
1448 | } |
1449 | ||
9d713c2b | 1450 | /* Deregister the admin queue's interrupt */ |
dca51e78 | 1451 | free_irq(pci_irq_vector(pdev, 0), adminq); |
9d713c2b | 1452 | |
e32efbfc JA |
1453 | /* |
1454 | * If we enable msix early due to not intx, disable it again before | |
1455 | * setting up the full range we need. | |
1456 | */ | |
dca51e78 CH |
1457 | pci_free_irq_vectors(pdev); |
1458 | nr_io_queues = pci_alloc_irq_vectors(pdev, 1, nr_io_queues, | |
1459 | PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY); | |
1460 | if (nr_io_queues <= 0) | |
1461 | return -EIO; | |
1462 | dev->max_qid = nr_io_queues; | |
fa08a396 | 1463 | |
063a8096 MW |
1464 | /* |
1465 | * Should investigate if there's a performance win from allocating | |
1466 | * more queues than interrupt vectors; it might allow the submission | |
1467 | * path to scale better, even if the receive path is limited by the | |
1468 | * number of interrupts. | |
1469 | */ | |
063a8096 | 1470 | |
dca51e78 | 1471 | result = queue_request_irq(adminq); |
758dd7fd JD |
1472 | if (result) { |
1473 | adminq->cq_vector = -1; | |
d4875622 | 1474 | return result; |
758dd7fd | 1475 | } |
749941f2 | 1476 | return nvme_create_io_queues(dev); |
b60503ba MW |
1477 | } |
1478 | ||
db3cbfff | 1479 | static void nvme_del_queue_end(struct request *req, int error) |
a5768aa8 | 1480 | { |
db3cbfff | 1481 | struct nvme_queue *nvmeq = req->end_io_data; |
b5875222 | 1482 | |
db3cbfff KB |
1483 | blk_mq_free_request(req); |
1484 | complete(&nvmeq->dev->ioq_wait); | |
a5768aa8 KB |
1485 | } |
1486 | ||
db3cbfff | 1487 | static void nvme_del_cq_end(struct request *req, int error) |
a5768aa8 | 1488 | { |
db3cbfff | 1489 | struct nvme_queue *nvmeq = req->end_io_data; |
a5768aa8 | 1490 | |
db3cbfff KB |
1491 | if (!error) { |
1492 | unsigned long flags; | |
1493 | ||
2e39e0f6 ML |
1494 | /* |
1495 | * We might be called with the AQ q_lock held | |
1496 | * and the I/O queue q_lock should always | |
1497 | * nest inside the AQ one. | |
1498 | */ | |
1499 | spin_lock_irqsave_nested(&nvmeq->q_lock, flags, | |
1500 | SINGLE_DEPTH_NESTING); | |
db3cbfff KB |
1501 | nvme_process_cq(nvmeq); |
1502 | spin_unlock_irqrestore(&nvmeq->q_lock, flags); | |
a5768aa8 | 1503 | } |
db3cbfff KB |
1504 | |
1505 | nvme_del_queue_end(req, error); | |
a5768aa8 KB |
1506 | } |
1507 | ||
db3cbfff | 1508 | static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode) |
bda4e0fb | 1509 | { |
db3cbfff KB |
1510 | struct request_queue *q = nvmeq->dev->ctrl.admin_q; |
1511 | struct request *req; | |
1512 | struct nvme_command cmd; | |
bda4e0fb | 1513 | |
db3cbfff KB |
1514 | memset(&cmd, 0, sizeof(cmd)); |
1515 | cmd.delete_queue.opcode = opcode; | |
1516 | cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid); | |
bda4e0fb | 1517 | |
eb71f435 | 1518 | req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); |
db3cbfff KB |
1519 | if (IS_ERR(req)) |
1520 | return PTR_ERR(req); | |
bda4e0fb | 1521 | |
db3cbfff KB |
1522 | req->timeout = ADMIN_TIMEOUT; |
1523 | req->end_io_data = nvmeq; | |
1524 | ||
1525 | blk_execute_rq_nowait(q, NULL, req, false, | |
1526 | opcode == nvme_admin_delete_cq ? | |
1527 | nvme_del_cq_end : nvme_del_queue_end); | |
1528 | return 0; | |
bda4e0fb KB |
1529 | } |
1530 | ||
70659060 | 1531 | static void nvme_disable_io_queues(struct nvme_dev *dev, int queues) |
a5768aa8 | 1532 | { |
70659060 | 1533 | int pass; |
db3cbfff KB |
1534 | unsigned long timeout; |
1535 | u8 opcode = nvme_admin_delete_sq; | |
a5768aa8 | 1536 | |
db3cbfff | 1537 | for (pass = 0; pass < 2; pass++) { |
014a0d60 | 1538 | int sent = 0, i = queues; |
db3cbfff KB |
1539 | |
1540 | reinit_completion(&dev->ioq_wait); | |
1541 | retry: | |
1542 | timeout = ADMIN_TIMEOUT; | |
c21377f8 GKB |
1543 | for (; i > 0; i--, sent++) |
1544 | if (nvme_delete_queue(dev->queues[i], opcode)) | |
db3cbfff | 1545 | break; |
c21377f8 | 1546 | |
db3cbfff KB |
1547 | while (sent--) { |
1548 | timeout = wait_for_completion_io_timeout(&dev->ioq_wait, timeout); | |
1549 | if (timeout == 0) | |
1550 | return; | |
1551 | if (i) | |
1552 | goto retry; | |
1553 | } | |
1554 | opcode = nvme_admin_delete_cq; | |
1555 | } | |
a5768aa8 KB |
1556 | } |
1557 | ||
422ef0c7 MW |
1558 | /* |
1559 | * Return: error value if an error occurred setting up the queues or calling | |
1560 | * Identify Device. 0 if these succeeded, even if adding some of the | |
1561 | * namespaces failed. At the moment, these failures are silent. TBD which | |
1562 | * failures should be reported. | |
1563 | */ | |
8d85fce7 | 1564 | static int nvme_dev_add(struct nvme_dev *dev) |
b60503ba | 1565 | { |
5bae7f73 | 1566 | if (!dev->ctrl.tagset) { |
ffe7704d KB |
1567 | dev->tagset.ops = &nvme_mq_ops; |
1568 | dev->tagset.nr_hw_queues = dev->online_queues - 1; | |
1569 | dev->tagset.timeout = NVME_IO_TIMEOUT; | |
1570 | dev->tagset.numa_node = dev_to_node(dev->dev); | |
1571 | dev->tagset.queue_depth = | |
a4aea562 | 1572 | min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1; |
ffe7704d KB |
1573 | dev->tagset.cmd_size = nvme_cmd_size(dev); |
1574 | dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE; | |
1575 | dev->tagset.driver_data = dev; | |
b60503ba | 1576 | |
ffe7704d KB |
1577 | if (blk_mq_alloc_tag_set(&dev->tagset)) |
1578 | return 0; | |
5bae7f73 | 1579 | dev->ctrl.tagset = &dev->tagset; |
949928c1 KB |
1580 | } else { |
1581 | blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1); | |
1582 | ||
1583 | /* Free previously allocated queues that are no longer usable */ | |
1584 | nvme_free_queues(dev, dev->online_queues); | |
ffe7704d | 1585 | } |
949928c1 | 1586 | |
e1e5e564 | 1587 | return 0; |
b60503ba MW |
1588 | } |
1589 | ||
b00a726a | 1590 | static int nvme_pci_enable(struct nvme_dev *dev) |
0877cb0d | 1591 | { |
42f61420 | 1592 | u64 cap; |
b00a726a | 1593 | int result = -ENOMEM; |
e75ec752 | 1594 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
0877cb0d KB |
1595 | |
1596 | if (pci_enable_device_mem(pdev)) | |
1597 | return result; | |
1598 | ||
0877cb0d | 1599 | pci_set_master(pdev); |
0877cb0d | 1600 | |
e75ec752 CH |
1601 | if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) && |
1602 | dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32))) | |
052d0efa | 1603 | goto disable; |
0877cb0d | 1604 | |
7a67cbea | 1605 | if (readl(dev->bar + NVME_REG_CSTS) == -1) { |
0e53d180 | 1606 | result = -ENODEV; |
b00a726a | 1607 | goto disable; |
0e53d180 | 1608 | } |
e32efbfc JA |
1609 | |
1610 | /* | |
a5229050 KB |
1611 | * Some devices and/or platforms don't advertise or work with INTx |
1612 | * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll | |
1613 | * adjust this later. | |
e32efbfc | 1614 | */ |
dca51e78 CH |
1615 | result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); |
1616 | if (result < 0) | |
1617 | return result; | |
e32efbfc | 1618 | |
7a67cbea CH |
1619 | cap = lo_hi_readq(dev->bar + NVME_REG_CAP); |
1620 | ||
42f61420 KB |
1621 | dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH); |
1622 | dev->db_stride = 1 << NVME_CAP_STRIDE(cap); | |
7a67cbea | 1623 | dev->dbs = dev->bar + 4096; |
1f390c1f SG |
1624 | |
1625 | /* | |
1626 | * Temporary fix for the Apple controller found in the MacBook8,1 and | |
1627 | * some MacBook7,1 to avoid controller resets and data loss. | |
1628 | */ | |
1629 | if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) { | |
1630 | dev->q_depth = 2; | |
1631 | dev_warn(dev->dev, "detected Apple NVMe controller, set " | |
1632 | "queue depth=%u to work around controller resets\n", | |
1633 | dev->q_depth); | |
1634 | } | |
1635 | ||
202021c1 SB |
1636 | /* |
1637 | * CMBs can currently only exist on >=1.2 PCIe devices. We only | |
1638 | * populate sysfs if a CMB is implemented. Note that we add the | |
1639 | * CMB attribute to the nvme_ctrl kobj which removes the need to remove | |
1640 | * it on exit. Since nvme_dev_attrs_group has no name we can pass | |
1641 | * NULL as final argument to sysfs_add_file_to_group. | |
1642 | */ | |
1643 | ||
8ef2074d | 1644 | if (readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 2, 0)) { |
8ffaadf7 | 1645 | dev->cmb = nvme_map_cmb(dev); |
0877cb0d | 1646 | |
202021c1 SB |
1647 | if (dev->cmbsz) { |
1648 | if (sysfs_add_file_to_group(&dev->ctrl.device->kobj, | |
1649 | &dev_attr_cmb.attr, NULL)) | |
1650 | dev_warn(dev->dev, | |
1651 | "failed to add sysfs attribute for CMB\n"); | |
1652 | } | |
1653 | } | |
1654 | ||
a0a3408e KB |
1655 | pci_enable_pcie_error_reporting(pdev); |
1656 | pci_save_state(pdev); | |
0877cb0d KB |
1657 | return 0; |
1658 | ||
1659 | disable: | |
0877cb0d KB |
1660 | pci_disable_device(pdev); |
1661 | return result; | |
1662 | } | |
1663 | ||
1664 | static void nvme_dev_unmap(struct nvme_dev *dev) | |
b00a726a KB |
1665 | { |
1666 | if (dev->bar) | |
1667 | iounmap(dev->bar); | |
a1f447b3 | 1668 | pci_release_mem_regions(to_pci_dev(dev->dev)); |
b00a726a KB |
1669 | } |
1670 | ||
1671 | static void nvme_pci_disable(struct nvme_dev *dev) | |
0877cb0d | 1672 | { |
e75ec752 CH |
1673 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
1674 | ||
dca51e78 | 1675 | pci_free_irq_vectors(pdev); |
0877cb0d | 1676 | |
a0a3408e KB |
1677 | if (pci_is_enabled(pdev)) { |
1678 | pci_disable_pcie_error_reporting(pdev); | |
e75ec752 | 1679 | pci_disable_device(pdev); |
4d115420 | 1680 | } |
4d115420 KB |
1681 | } |
1682 | ||
a5cdb68c | 1683 | static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown) |
b60503ba | 1684 | { |
70659060 | 1685 | int i, queues; |
7c1b2450 | 1686 | u32 csts = -1; |
22404274 | 1687 | |
2d55cd5f | 1688 | del_timer_sync(&dev->watchdog_timer); |
1fa6aead | 1689 | |
77bf25ea | 1690 | mutex_lock(&dev->shutdown_lock); |
b00a726a | 1691 | if (pci_is_enabled(to_pci_dev(dev->dev))) { |
25646264 | 1692 | nvme_stop_queues(&dev->ctrl); |
7a67cbea | 1693 | csts = readl(dev->bar + NVME_REG_CSTS); |
c9d3bf88 | 1694 | } |
c21377f8 | 1695 | |
70659060 | 1696 | queues = dev->online_queues - 1; |
c21377f8 GKB |
1697 | for (i = dev->queue_count - 1; i > 0; i--) |
1698 | nvme_suspend_queue(dev->queues[i]); | |
1699 | ||
7c1b2450 | 1700 | if (csts & NVME_CSTS_CFS || !(csts & NVME_CSTS_RDY)) { |
82469c59 GKB |
1701 | /* A device might become IO incapable very soon during |
1702 | * probe, before the admin queue is configured. Thus, | |
1703 | * queue_count can be 0 here. | |
1704 | */ | |
1705 | if (dev->queue_count) | |
1706 | nvme_suspend_queue(dev->queues[0]); | |
4d115420 | 1707 | } else { |
70659060 | 1708 | nvme_disable_io_queues(dev, queues); |
a5cdb68c | 1709 | nvme_disable_admin_queue(dev, shutdown); |
4d115420 | 1710 | } |
b00a726a | 1711 | nvme_pci_disable(dev); |
07836e65 | 1712 | |
e1958e65 ML |
1713 | blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl); |
1714 | blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl); | |
77bf25ea | 1715 | mutex_unlock(&dev->shutdown_lock); |
b60503ba MW |
1716 | } |
1717 | ||
091b6092 MW |
1718 | static int nvme_setup_prp_pools(struct nvme_dev *dev) |
1719 | { | |
e75ec752 | 1720 | dev->prp_page_pool = dma_pool_create("prp list page", dev->dev, |
091b6092 MW |
1721 | PAGE_SIZE, PAGE_SIZE, 0); |
1722 | if (!dev->prp_page_pool) | |
1723 | return -ENOMEM; | |
1724 | ||
99802a7a | 1725 | /* Optimisation for I/Os between 4k and 128k */ |
e75ec752 | 1726 | dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev, |
99802a7a MW |
1727 | 256, 256, 0); |
1728 | if (!dev->prp_small_pool) { | |
1729 | dma_pool_destroy(dev->prp_page_pool); | |
1730 | return -ENOMEM; | |
1731 | } | |
091b6092 MW |
1732 | return 0; |
1733 | } | |
1734 | ||
1735 | static void nvme_release_prp_pools(struct nvme_dev *dev) | |
1736 | { | |
1737 | dma_pool_destroy(dev->prp_page_pool); | |
99802a7a | 1738 | dma_pool_destroy(dev->prp_small_pool); |
091b6092 MW |
1739 | } |
1740 | ||
1673f1f0 | 1741 | static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl) |
5e82e952 | 1742 | { |
1673f1f0 | 1743 | struct nvme_dev *dev = to_nvme_dev(ctrl); |
9ac27090 | 1744 | |
e75ec752 | 1745 | put_device(dev->dev); |
4af0e21c KB |
1746 | if (dev->tagset.tags) |
1747 | blk_mq_free_tag_set(&dev->tagset); | |
1c63dc66 CH |
1748 | if (dev->ctrl.admin_q) |
1749 | blk_put_queue(dev->ctrl.admin_q); | |
5e82e952 | 1750 | kfree(dev->queues); |
5e82e952 KB |
1751 | kfree(dev); |
1752 | } | |
1753 | ||
f58944e2 KB |
1754 | static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status) |
1755 | { | |
237045fc | 1756 | dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status); |
f58944e2 KB |
1757 | |
1758 | kref_get(&dev->ctrl.kref); | |
69d9a99c | 1759 | nvme_dev_disable(dev, false); |
f58944e2 KB |
1760 | if (!schedule_work(&dev->remove_work)) |
1761 | nvme_put_ctrl(&dev->ctrl); | |
1762 | } | |
1763 | ||
fd634f41 | 1764 | static void nvme_reset_work(struct work_struct *work) |
5e82e952 | 1765 | { |
fd634f41 | 1766 | struct nvme_dev *dev = container_of(work, struct nvme_dev, reset_work); |
f58944e2 | 1767 | int result = -ENODEV; |
5e82e952 | 1768 | |
bb8d261e | 1769 | if (WARN_ON(dev->ctrl.state == NVME_CTRL_RESETTING)) |
fd634f41 | 1770 | goto out; |
5e82e952 | 1771 | |
fd634f41 CH |
1772 | /* |
1773 | * If we're called to reset a live controller first shut it down before | |
1774 | * moving on. | |
1775 | */ | |
b00a726a | 1776 | if (dev->ctrl.ctrl_config & NVME_CC_ENABLE) |
a5cdb68c | 1777 | nvme_dev_disable(dev, false); |
5e82e952 | 1778 | |
bb8d261e | 1779 | if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_RESETTING)) |
9bf2b972 KB |
1780 | goto out; |
1781 | ||
b00a726a | 1782 | result = nvme_pci_enable(dev); |
f0b50732 | 1783 | if (result) |
3cf519b5 | 1784 | goto out; |
f0b50732 KB |
1785 | |
1786 | result = nvme_configure_admin_queue(dev); | |
1787 | if (result) | |
f58944e2 | 1788 | goto out; |
f0b50732 | 1789 | |
a4aea562 | 1790 | nvme_init_queue(dev->queues[0], 0); |
0fb59cbc KB |
1791 | result = nvme_alloc_admin_tags(dev); |
1792 | if (result) | |
f58944e2 | 1793 | goto out; |
b9afca3e | 1794 | |
ce4541f4 CH |
1795 | result = nvme_init_identify(&dev->ctrl); |
1796 | if (result) | |
f58944e2 | 1797 | goto out; |
ce4541f4 | 1798 | |
f0b50732 | 1799 | result = nvme_setup_io_queues(dev); |
badc34d4 | 1800 | if (result) |
f58944e2 | 1801 | goto out; |
f0b50732 | 1802 | |
21f033f7 KB |
1803 | /* |
1804 | * A controller that can not execute IO typically requires user | |
1805 | * intervention to correct. For such degraded controllers, the driver | |
1806 | * should not submit commands the user did not request, so skip | |
1807 | * registering for asynchronous event notification on this condition. | |
1808 | */ | |
f866fc42 CH |
1809 | if (dev->online_queues > 1) |
1810 | nvme_queue_async_events(&dev->ctrl); | |
3cf519b5 | 1811 | |
2d55cd5f | 1812 | mod_timer(&dev->watchdog_timer, round_jiffies(jiffies + HZ)); |
3cf519b5 | 1813 | |
2659e57b CH |
1814 | /* |
1815 | * Keep the controller around but remove all namespaces if we don't have | |
1816 | * any working I/O queue. | |
1817 | */ | |
3cf519b5 | 1818 | if (dev->online_queues < 2) { |
1b3c47c1 | 1819 | dev_warn(dev->ctrl.device, "IO queues not created\n"); |
3b24774e | 1820 | nvme_kill_queues(&dev->ctrl); |
5bae7f73 | 1821 | nvme_remove_namespaces(&dev->ctrl); |
3cf519b5 | 1822 | } else { |
25646264 | 1823 | nvme_start_queues(&dev->ctrl); |
3cf519b5 CH |
1824 | nvme_dev_add(dev); |
1825 | } | |
1826 | ||
bb8d261e CH |
1827 | if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) { |
1828 | dev_warn(dev->ctrl.device, "failed to mark controller live\n"); | |
1829 | goto out; | |
1830 | } | |
92911a55 CH |
1831 | |
1832 | if (dev->online_queues > 1) | |
5955be21 | 1833 | nvme_queue_scan(&dev->ctrl); |
3cf519b5 | 1834 | return; |
f0b50732 | 1835 | |
3cf519b5 | 1836 | out: |
f58944e2 | 1837 | nvme_remove_dead_ctrl(dev, result); |
f0b50732 KB |
1838 | } |
1839 | ||
5c8809e6 | 1840 | static void nvme_remove_dead_ctrl_work(struct work_struct *work) |
9a6b9458 | 1841 | { |
5c8809e6 | 1842 | struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work); |
e75ec752 | 1843 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
9a6b9458 | 1844 | |
69d9a99c | 1845 | nvme_kill_queues(&dev->ctrl); |
9a6b9458 | 1846 | if (pci_get_drvdata(pdev)) |
921920ab | 1847 | device_release_driver(&pdev->dev); |
1673f1f0 | 1848 | nvme_put_ctrl(&dev->ctrl); |
9a6b9458 KB |
1849 | } |
1850 | ||
4cc06521 | 1851 | static int nvme_reset(struct nvme_dev *dev) |
9a6b9458 | 1852 | { |
1c63dc66 | 1853 | if (!dev->ctrl.admin_q || blk_queue_dying(dev->ctrl.admin_q)) |
4cc06521 | 1854 | return -ENODEV; |
c5f6ce97 KB |
1855 | if (work_busy(&dev->reset_work)) |
1856 | return -ENODEV; | |
846cc05f CH |
1857 | if (!queue_work(nvme_workq, &dev->reset_work)) |
1858 | return -EBUSY; | |
846cc05f | 1859 | return 0; |
9a6b9458 KB |
1860 | } |
1861 | ||
1c63dc66 | 1862 | static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val) |
9ca97374 | 1863 | { |
1c63dc66 | 1864 | *val = readl(to_nvme_dev(ctrl)->bar + off); |
90667892 | 1865 | return 0; |
9ca97374 TH |
1866 | } |
1867 | ||
5fd4ce1b | 1868 | static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val) |
4cc06521 | 1869 | { |
5fd4ce1b CH |
1870 | writel(val, to_nvme_dev(ctrl)->bar + off); |
1871 | return 0; | |
1872 | } | |
4cc06521 | 1873 | |
7fd8930f CH |
1874 | static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val) |
1875 | { | |
1876 | *val = readq(to_nvme_dev(ctrl)->bar + off); | |
1877 | return 0; | |
4cc06521 KB |
1878 | } |
1879 | ||
f3ca80fc CH |
1880 | static int nvme_pci_reset_ctrl(struct nvme_ctrl *ctrl) |
1881 | { | |
c5f6ce97 KB |
1882 | struct nvme_dev *dev = to_nvme_dev(ctrl); |
1883 | int ret = nvme_reset(dev); | |
1884 | ||
1885 | if (!ret) | |
1886 | flush_work(&dev->reset_work); | |
1887 | return ret; | |
4cc06521 | 1888 | } |
f3ca80fc | 1889 | |
1c63dc66 | 1890 | static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = { |
1a353d85 | 1891 | .name = "pcie", |
e439bb12 | 1892 | .module = THIS_MODULE, |
1c63dc66 | 1893 | .reg_read32 = nvme_pci_reg_read32, |
5fd4ce1b | 1894 | .reg_write32 = nvme_pci_reg_write32, |
7fd8930f | 1895 | .reg_read64 = nvme_pci_reg_read64, |
f3ca80fc | 1896 | .reset_ctrl = nvme_pci_reset_ctrl, |
1673f1f0 | 1897 | .free_ctrl = nvme_pci_free_ctrl, |
f866fc42 | 1898 | .submit_async_event = nvme_pci_submit_async_event, |
1c63dc66 | 1899 | }; |
4cc06521 | 1900 | |
b00a726a KB |
1901 | static int nvme_dev_map(struct nvme_dev *dev) |
1902 | { | |
b00a726a KB |
1903 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
1904 | ||
a1f447b3 | 1905 | if (pci_request_mem_regions(pdev, "nvme")) |
b00a726a KB |
1906 | return -ENODEV; |
1907 | ||
1908 | dev->bar = ioremap(pci_resource_start(pdev, 0), 8192); | |
1909 | if (!dev->bar) | |
1910 | goto release; | |
1911 | ||
1912 | return 0; | |
1913 | release: | |
a1f447b3 | 1914 | pci_release_mem_regions(pdev); |
b00a726a KB |
1915 | return -ENODEV; |
1916 | } | |
1917 | ||
8d85fce7 | 1918 | static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) |
b60503ba | 1919 | { |
a4aea562 | 1920 | int node, result = -ENOMEM; |
b60503ba MW |
1921 | struct nvme_dev *dev; |
1922 | ||
a4aea562 MB |
1923 | node = dev_to_node(&pdev->dev); |
1924 | if (node == NUMA_NO_NODE) | |
2fa84351 | 1925 | set_dev_node(&pdev->dev, first_memory_node); |
a4aea562 MB |
1926 | |
1927 | dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); | |
b60503ba MW |
1928 | if (!dev) |
1929 | return -ENOMEM; | |
a4aea562 MB |
1930 | dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *), |
1931 | GFP_KERNEL, node); | |
b60503ba MW |
1932 | if (!dev->queues) |
1933 | goto free; | |
1934 | ||
e75ec752 | 1935 | dev->dev = get_device(&pdev->dev); |
9a6b9458 | 1936 | pci_set_drvdata(pdev, dev); |
1c63dc66 | 1937 | |
b00a726a KB |
1938 | result = nvme_dev_map(dev); |
1939 | if (result) | |
1940 | goto free; | |
1941 | ||
f3ca80fc | 1942 | INIT_WORK(&dev->reset_work, nvme_reset_work); |
5c8809e6 | 1943 | INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work); |
2d55cd5f CH |
1944 | setup_timer(&dev->watchdog_timer, nvme_watchdog_timer, |
1945 | (unsigned long)dev); | |
77bf25ea | 1946 | mutex_init(&dev->shutdown_lock); |
db3cbfff | 1947 | init_completion(&dev->ioq_wait); |
b60503ba | 1948 | |
091b6092 MW |
1949 | result = nvme_setup_prp_pools(dev); |
1950 | if (result) | |
a96d4f5c | 1951 | goto put_pci; |
4cc06521 | 1952 | |
f3ca80fc CH |
1953 | result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops, |
1954 | id->driver_data); | |
4cc06521 | 1955 | if (result) |
2e1d8448 | 1956 | goto release_pools; |
740216fc | 1957 | |
1b3c47c1 SG |
1958 | dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev)); |
1959 | ||
92f7a162 | 1960 | queue_work(nvme_workq, &dev->reset_work); |
b60503ba MW |
1961 | return 0; |
1962 | ||
0877cb0d | 1963 | release_pools: |
091b6092 | 1964 | nvme_release_prp_pools(dev); |
a96d4f5c | 1965 | put_pci: |
e75ec752 | 1966 | put_device(dev->dev); |
b00a726a | 1967 | nvme_dev_unmap(dev); |
b60503ba MW |
1968 | free: |
1969 | kfree(dev->queues); | |
b60503ba MW |
1970 | kfree(dev); |
1971 | return result; | |
1972 | } | |
1973 | ||
f0d54a54 KB |
1974 | static void nvme_reset_notify(struct pci_dev *pdev, bool prepare) |
1975 | { | |
a6739479 | 1976 | struct nvme_dev *dev = pci_get_drvdata(pdev); |
f0d54a54 | 1977 | |
a6739479 | 1978 | if (prepare) |
a5cdb68c | 1979 | nvme_dev_disable(dev, false); |
a6739479 | 1980 | else |
c5f6ce97 | 1981 | nvme_reset(dev); |
f0d54a54 KB |
1982 | } |
1983 | ||
09ece142 KB |
1984 | static void nvme_shutdown(struct pci_dev *pdev) |
1985 | { | |
1986 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
a5cdb68c | 1987 | nvme_dev_disable(dev, true); |
09ece142 KB |
1988 | } |
1989 | ||
f58944e2 KB |
1990 | /* |
1991 | * The driver's remove may be called on a device in a partially initialized | |
1992 | * state. This function must not have any dependencies on the device state in | |
1993 | * order to proceed. | |
1994 | */ | |
8d85fce7 | 1995 | static void nvme_remove(struct pci_dev *pdev) |
b60503ba MW |
1996 | { |
1997 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
9a6b9458 | 1998 | |
bb8d261e CH |
1999 | nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); |
2000 | ||
9a6b9458 | 2001 | pci_set_drvdata(pdev, NULL); |
0ff9d4e1 KB |
2002 | |
2003 | if (!pci_device_is_present(pdev)) | |
2004 | nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD); | |
2005 | ||
9bf2b972 | 2006 | flush_work(&dev->reset_work); |
53029b04 | 2007 | nvme_uninit_ctrl(&dev->ctrl); |
a5cdb68c | 2008 | nvme_dev_disable(dev, true); |
a4aea562 | 2009 | nvme_dev_remove_admin(dev); |
a1a5ef99 | 2010 | nvme_free_queues(dev, 0); |
8ffaadf7 | 2011 | nvme_release_cmb(dev); |
9a6b9458 | 2012 | nvme_release_prp_pools(dev); |
b00a726a | 2013 | nvme_dev_unmap(dev); |
1673f1f0 | 2014 | nvme_put_ctrl(&dev->ctrl); |
b60503ba MW |
2015 | } |
2016 | ||
13880f5b KB |
2017 | static int nvme_pci_sriov_configure(struct pci_dev *pdev, int numvfs) |
2018 | { | |
2019 | int ret = 0; | |
2020 | ||
2021 | if (numvfs == 0) { | |
2022 | if (pci_vfs_assigned(pdev)) { | |
2023 | dev_warn(&pdev->dev, | |
2024 | "Cannot disable SR-IOV VFs while assigned\n"); | |
2025 | return -EPERM; | |
2026 | } | |
2027 | pci_disable_sriov(pdev); | |
2028 | return 0; | |
2029 | } | |
2030 | ||
2031 | ret = pci_enable_sriov(pdev, numvfs); | |
2032 | return ret ? ret : numvfs; | |
2033 | } | |
2034 | ||
671a6018 | 2035 | #ifdef CONFIG_PM_SLEEP |
cd638946 KB |
2036 | static int nvme_suspend(struct device *dev) |
2037 | { | |
2038 | struct pci_dev *pdev = to_pci_dev(dev); | |
2039 | struct nvme_dev *ndev = pci_get_drvdata(pdev); | |
2040 | ||
a5cdb68c | 2041 | nvme_dev_disable(ndev, true); |
cd638946 KB |
2042 | return 0; |
2043 | } | |
2044 | ||
2045 | static int nvme_resume(struct device *dev) | |
2046 | { | |
2047 | struct pci_dev *pdev = to_pci_dev(dev); | |
2048 | struct nvme_dev *ndev = pci_get_drvdata(pdev); | |
cd638946 | 2049 | |
c5f6ce97 | 2050 | nvme_reset(ndev); |
9a6b9458 | 2051 | return 0; |
cd638946 | 2052 | } |
671a6018 | 2053 | #endif |
cd638946 KB |
2054 | |
2055 | static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume); | |
b60503ba | 2056 | |
a0a3408e KB |
2057 | static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev, |
2058 | pci_channel_state_t state) | |
2059 | { | |
2060 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
2061 | ||
2062 | /* | |
2063 | * A frozen channel requires a reset. When detected, this method will | |
2064 | * shutdown the controller to quiesce. The controller will be restarted | |
2065 | * after the slot reset through driver's slot_reset callback. | |
2066 | */ | |
a0a3408e KB |
2067 | switch (state) { |
2068 | case pci_channel_io_normal: | |
2069 | return PCI_ERS_RESULT_CAN_RECOVER; | |
2070 | case pci_channel_io_frozen: | |
d011fb31 KB |
2071 | dev_warn(dev->ctrl.device, |
2072 | "frozen state error detected, reset controller\n"); | |
a5cdb68c | 2073 | nvme_dev_disable(dev, false); |
a0a3408e KB |
2074 | return PCI_ERS_RESULT_NEED_RESET; |
2075 | case pci_channel_io_perm_failure: | |
d011fb31 KB |
2076 | dev_warn(dev->ctrl.device, |
2077 | "failure state error detected, request disconnect\n"); | |
a0a3408e KB |
2078 | return PCI_ERS_RESULT_DISCONNECT; |
2079 | } | |
2080 | return PCI_ERS_RESULT_NEED_RESET; | |
2081 | } | |
2082 | ||
2083 | static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev) | |
2084 | { | |
2085 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
2086 | ||
1b3c47c1 | 2087 | dev_info(dev->ctrl.device, "restart after slot reset\n"); |
a0a3408e | 2088 | pci_restore_state(pdev); |
c5f6ce97 | 2089 | nvme_reset(dev); |
a0a3408e KB |
2090 | return PCI_ERS_RESULT_RECOVERED; |
2091 | } | |
2092 | ||
2093 | static void nvme_error_resume(struct pci_dev *pdev) | |
2094 | { | |
2095 | pci_cleanup_aer_uncorrect_error_status(pdev); | |
2096 | } | |
2097 | ||
1d352035 | 2098 | static const struct pci_error_handlers nvme_err_handler = { |
b60503ba | 2099 | .error_detected = nvme_error_detected, |
b60503ba MW |
2100 | .slot_reset = nvme_slot_reset, |
2101 | .resume = nvme_error_resume, | |
f0d54a54 | 2102 | .reset_notify = nvme_reset_notify, |
b60503ba MW |
2103 | }; |
2104 | ||
6eb0d698 | 2105 | static const struct pci_device_id nvme_id_table[] = { |
106198ed | 2106 | { PCI_VDEVICE(INTEL, 0x0953), |
08095e70 KB |
2107 | .driver_data = NVME_QUIRK_STRIPE_SIZE | |
2108 | NVME_QUIRK_DISCARD_ZEROES, }, | |
99466e70 KB |
2109 | { PCI_VDEVICE(INTEL, 0x0a53), |
2110 | .driver_data = NVME_QUIRK_STRIPE_SIZE | | |
2111 | NVME_QUIRK_DISCARD_ZEROES, }, | |
2112 | { PCI_VDEVICE(INTEL, 0x0a54), | |
2113 | .driver_data = NVME_QUIRK_STRIPE_SIZE | | |
2114 | NVME_QUIRK_DISCARD_ZEROES, }, | |
540c801c KB |
2115 | { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */ |
2116 | .driver_data = NVME_QUIRK_IDENTIFY_CNS, }, | |
54adc010 GP |
2117 | { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */ |
2118 | .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, | |
015282c9 WW |
2119 | { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */ |
2120 | .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, | |
b60503ba | 2121 | { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, |
c74dc780 | 2122 | { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) }, |
b60503ba MW |
2123 | { 0, } |
2124 | }; | |
2125 | MODULE_DEVICE_TABLE(pci, nvme_id_table); | |
2126 | ||
2127 | static struct pci_driver nvme_driver = { | |
2128 | .name = "nvme", | |
2129 | .id_table = nvme_id_table, | |
2130 | .probe = nvme_probe, | |
8d85fce7 | 2131 | .remove = nvme_remove, |
09ece142 | 2132 | .shutdown = nvme_shutdown, |
cd638946 KB |
2133 | .driver = { |
2134 | .pm = &nvme_dev_pm_ops, | |
2135 | }, | |
13880f5b | 2136 | .sriov_configure = nvme_pci_sriov_configure, |
b60503ba MW |
2137 | .err_handler = &nvme_err_handler, |
2138 | }; | |
2139 | ||
2140 | static int __init nvme_init(void) | |
2141 | { | |
0ac13140 | 2142 | int result; |
1fa6aead | 2143 | |
92f7a162 | 2144 | nvme_workq = alloc_workqueue("nvme", WQ_UNBOUND | WQ_MEM_RECLAIM, 0); |
9a6b9458 | 2145 | if (!nvme_workq) |
b9afca3e | 2146 | return -ENOMEM; |
9a6b9458 | 2147 | |
f3db22fe KB |
2148 | result = pci_register_driver(&nvme_driver); |
2149 | if (result) | |
576d55d6 | 2150 | destroy_workqueue(nvme_workq); |
b60503ba MW |
2151 | return result; |
2152 | } | |
2153 | ||
2154 | static void __exit nvme_exit(void) | |
2155 | { | |
2156 | pci_unregister_driver(&nvme_driver); | |
9a6b9458 | 2157 | destroy_workqueue(nvme_workq); |
21bd78bc | 2158 | _nvme_check_size(); |
b60503ba MW |
2159 | } |
2160 | ||
2161 | MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); | |
2162 | MODULE_LICENSE("GPL"); | |
c78b4713 | 2163 | MODULE_VERSION("1.0"); |
b60503ba MW |
2164 | module_init(nvme_init); |
2165 | module_exit(nvme_exit); |