Commit | Line | Data |
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b60503ba MW |
1 | /* |
2 | * NVM Express device driver | |
6eb0d698 | 3 | * Copyright (c) 2011-2014, Intel Corporation. |
b60503ba MW |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
b60503ba MW |
13 | */ |
14 | ||
a0a3408e | 15 | #include <linux/aer.h> |
8de05535 | 16 | #include <linux/bitops.h> |
b60503ba | 17 | #include <linux/blkdev.h> |
a4aea562 | 18 | #include <linux/blk-mq.h> |
42f61420 | 19 | #include <linux/cpu.h> |
fd63e9ce | 20 | #include <linux/delay.h> |
b60503ba MW |
21 | #include <linux/errno.h> |
22 | #include <linux/fs.h> | |
23 | #include <linux/genhd.h> | |
4cc09e2d | 24 | #include <linux/hdreg.h> |
5aff9382 | 25 | #include <linux/idr.h> |
b60503ba MW |
26 | #include <linux/init.h> |
27 | #include <linux/interrupt.h> | |
28 | #include <linux/io.h> | |
29 | #include <linux/kdev_t.h> | |
1fa6aead | 30 | #include <linux/kthread.h> |
b60503ba MW |
31 | #include <linux/kernel.h> |
32 | #include <linux/mm.h> | |
33 | #include <linux/module.h> | |
34 | #include <linux/moduleparam.h> | |
77bf25ea | 35 | #include <linux/mutex.h> |
b60503ba | 36 | #include <linux/pci.h> |
be7b6275 | 37 | #include <linux/poison.h> |
c3bfe717 | 38 | #include <linux/ptrace.h> |
b60503ba MW |
39 | #include <linux/sched.h> |
40 | #include <linux/slab.h> | |
e1e5e564 | 41 | #include <linux/t10-pi.h> |
b60503ba | 42 | #include <linux/types.h> |
2f8e2c87 | 43 | #include <linux/io-64-nonatomic-lo-hi.h> |
1d277a63 | 44 | #include <asm/unaligned.h> |
797a796a | 45 | |
f11bb3e2 CH |
46 | #include "nvme.h" |
47 | ||
9d43cf64 | 48 | #define NVME_Q_DEPTH 1024 |
d31af0a3 | 49 | #define NVME_AQ_DEPTH 256 |
b60503ba MW |
50 | #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command)) |
51 | #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion)) | |
adf68f21 CH |
52 | |
53 | /* | |
54 | * We handle AEN commands ourselves and don't even let the | |
55 | * block layer know about them. | |
56 | */ | |
57 | #define NVME_NR_AEN_COMMANDS 1 | |
58 | #define NVME_AQ_BLKMQ_DEPTH (NVME_AQ_DEPTH - NVME_NR_AEN_COMMANDS) | |
9d43cf64 | 59 | |
21d34711 | 60 | unsigned char admin_timeout = 60; |
9d43cf64 KB |
61 | module_param(admin_timeout, byte, 0644); |
62 | MODULE_PARM_DESC(admin_timeout, "timeout in seconds for admin commands"); | |
b60503ba | 63 | |
bd67608a MW |
64 | unsigned char nvme_io_timeout = 30; |
65 | module_param_named(io_timeout, nvme_io_timeout, byte, 0644); | |
b355084a | 66 | MODULE_PARM_DESC(io_timeout, "timeout in seconds for I/O"); |
b60503ba | 67 | |
5fd4ce1b | 68 | unsigned char shutdown_timeout = 5; |
2484f407 DM |
69 | module_param(shutdown_timeout, byte, 0644); |
70 | MODULE_PARM_DESC(shutdown_timeout, "timeout in seconds for controller shutdown"); | |
71 | ||
58ffacb5 MW |
72 | static int use_threaded_interrupts; |
73 | module_param(use_threaded_interrupts, int, 0); | |
74 | ||
8ffaadf7 JD |
75 | static bool use_cmb_sqes = true; |
76 | module_param(use_cmb_sqes, bool, 0644); | |
77 | MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes"); | |
78 | ||
1fa6aead MW |
79 | static LIST_HEAD(dev_list); |
80 | static struct task_struct *nvme_thread; | |
9a6b9458 | 81 | static struct workqueue_struct *nvme_workq; |
b9afca3e | 82 | static wait_queue_head_t nvme_kthread_wait; |
1fa6aead | 83 | |
1c63dc66 CH |
84 | struct nvme_dev; |
85 | struct nvme_queue; | |
86 | ||
4cc06521 | 87 | static int nvme_reset(struct nvme_dev *dev); |
a0fa9647 | 88 | static void nvme_process_cq(struct nvme_queue *nvmeq); |
5c8809e6 | 89 | static void nvme_remove_dead_ctrl(struct nvme_dev *dev); |
e1569a16 | 90 | static void nvme_dev_shutdown(struct nvme_dev *dev); |
d4b4ff8e | 91 | |
1c63dc66 CH |
92 | /* |
93 | * Represents an NVM Express device. Each nvme_dev is a PCI function. | |
94 | */ | |
95 | struct nvme_dev { | |
96 | struct list_head node; | |
97 | struct nvme_queue **queues; | |
98 | struct blk_mq_tag_set tagset; | |
99 | struct blk_mq_tag_set admin_tagset; | |
100 | u32 __iomem *dbs; | |
101 | struct device *dev; | |
102 | struct dma_pool *prp_page_pool; | |
103 | struct dma_pool *prp_small_pool; | |
104 | unsigned queue_count; | |
105 | unsigned online_queues; | |
106 | unsigned max_qid; | |
107 | int q_depth; | |
108 | u32 db_stride; | |
1c63dc66 CH |
109 | struct msix_entry *entry; |
110 | void __iomem *bar; | |
1c63dc66 | 111 | struct work_struct reset_work; |
1c63dc66 | 112 | struct work_struct scan_work; |
5c8809e6 | 113 | struct work_struct remove_work; |
77bf25ea | 114 | struct mutex shutdown_lock; |
1c63dc66 | 115 | bool subsystem; |
1c63dc66 CH |
116 | void __iomem *cmb; |
117 | dma_addr_t cmb_dma_addr; | |
118 | u64 cmb_size; | |
119 | u32 cmbsz; | |
fd634f41 | 120 | unsigned long flags; |
db3cbfff | 121 | |
fd634f41 | 122 | #define NVME_CTRL_RESETTING 0 |
1c63dc66 CH |
123 | |
124 | struct nvme_ctrl ctrl; | |
db3cbfff | 125 | struct completion ioq_wait; |
1c63dc66 CH |
126 | }; |
127 | ||
128 | static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl) | |
129 | { | |
130 | return container_of(ctrl, struct nvme_dev, ctrl); | |
131 | } | |
132 | ||
b60503ba MW |
133 | /* |
134 | * An NVM Express queue. Each device has at least two (one for admin | |
135 | * commands and one for I/O commands). | |
136 | */ | |
137 | struct nvme_queue { | |
138 | struct device *q_dmadev; | |
091b6092 | 139 | struct nvme_dev *dev; |
3193f07b | 140 | char irqname[24]; /* nvme4294967295-65535\0 */ |
b60503ba MW |
141 | spinlock_t q_lock; |
142 | struct nvme_command *sq_cmds; | |
8ffaadf7 | 143 | struct nvme_command __iomem *sq_cmds_io; |
b60503ba | 144 | volatile struct nvme_completion *cqes; |
42483228 | 145 | struct blk_mq_tags **tags; |
b60503ba MW |
146 | dma_addr_t sq_dma_addr; |
147 | dma_addr_t cq_dma_addr; | |
b60503ba MW |
148 | u32 __iomem *q_db; |
149 | u16 q_depth; | |
6222d172 | 150 | s16 cq_vector; |
b60503ba MW |
151 | u16 sq_head; |
152 | u16 sq_tail; | |
153 | u16 cq_head; | |
c30341dc | 154 | u16 qid; |
e9539f47 MW |
155 | u8 cq_phase; |
156 | u8 cqe_seen; | |
b60503ba MW |
157 | }; |
158 | ||
71bd150c CH |
159 | /* |
160 | * The nvme_iod describes the data in an I/O, including the list of PRP | |
161 | * entries. You can't see it in this data structure because C doesn't let | |
f4800d6d | 162 | * me express that. Use nvme_init_iod to ensure there's enough space |
71bd150c CH |
163 | * allocated to store the PRP list. |
164 | */ | |
165 | struct nvme_iod { | |
f4800d6d CH |
166 | struct nvme_queue *nvmeq; |
167 | int aborted; | |
71bd150c | 168 | int npages; /* In the PRP list. 0 means small pool in use */ |
71bd150c CH |
169 | int nents; /* Used in scatterlist */ |
170 | int length; /* Of data, in bytes */ | |
171 | dma_addr_t first_dma; | |
bf684057 | 172 | struct scatterlist meta_sg; /* metadata requires single contiguous buffer */ |
f4800d6d CH |
173 | struct scatterlist *sg; |
174 | struct scatterlist inline_sg[0]; | |
71bd150c CH |
175 | }; |
176 | ||
b60503ba MW |
177 | /* |
178 | * Check we didin't inadvertently grow the command struct | |
179 | */ | |
180 | static inline void _nvme_check_size(void) | |
181 | { | |
182 | BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64); | |
183 | BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); | |
184 | BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); | |
185 | BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); | |
186 | BUILD_BUG_ON(sizeof(struct nvme_features) != 64); | |
f8ebf840 | 187 | BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64); |
c30341dc | 188 | BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64); |
b60503ba MW |
189 | BUILD_BUG_ON(sizeof(struct nvme_command) != 64); |
190 | BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096); | |
191 | BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096); | |
192 | BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64); | |
6ecec745 | 193 | BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512); |
b60503ba MW |
194 | } |
195 | ||
ac3dd5bd JA |
196 | /* |
197 | * Max size of iod being embedded in the request payload | |
198 | */ | |
199 | #define NVME_INT_PAGES 2 | |
5fd4ce1b | 200 | #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size) |
ac3dd5bd JA |
201 | |
202 | /* | |
203 | * Will slightly overestimate the number of pages needed. This is OK | |
204 | * as it only leads to a small amount of wasted memory for the lifetime of | |
205 | * the I/O. | |
206 | */ | |
207 | static int nvme_npages(unsigned size, struct nvme_dev *dev) | |
208 | { | |
5fd4ce1b CH |
209 | unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size, |
210 | dev->ctrl.page_size); | |
ac3dd5bd JA |
211 | return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); |
212 | } | |
213 | ||
f4800d6d CH |
214 | static unsigned int nvme_iod_alloc_size(struct nvme_dev *dev, |
215 | unsigned int size, unsigned int nseg) | |
ac3dd5bd | 216 | { |
f4800d6d CH |
217 | return sizeof(__le64 *) * nvme_npages(size, dev) + |
218 | sizeof(struct scatterlist) * nseg; | |
219 | } | |
ac3dd5bd | 220 | |
f4800d6d CH |
221 | static unsigned int nvme_cmd_size(struct nvme_dev *dev) |
222 | { | |
223 | return sizeof(struct nvme_iod) + | |
224 | nvme_iod_alloc_size(dev, NVME_INT_BYTES(dev), NVME_INT_PAGES); | |
ac3dd5bd JA |
225 | } |
226 | ||
a4aea562 MB |
227 | static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, |
228 | unsigned int hctx_idx) | |
e85248e5 | 229 | { |
a4aea562 MB |
230 | struct nvme_dev *dev = data; |
231 | struct nvme_queue *nvmeq = dev->queues[0]; | |
232 | ||
42483228 KB |
233 | WARN_ON(hctx_idx != 0); |
234 | WARN_ON(dev->admin_tagset.tags[0] != hctx->tags); | |
235 | WARN_ON(nvmeq->tags); | |
236 | ||
a4aea562 | 237 | hctx->driver_data = nvmeq; |
42483228 | 238 | nvmeq->tags = &dev->admin_tagset.tags[0]; |
a4aea562 | 239 | return 0; |
e85248e5 MW |
240 | } |
241 | ||
4af0e21c KB |
242 | static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx) |
243 | { | |
244 | struct nvme_queue *nvmeq = hctx->driver_data; | |
245 | ||
246 | nvmeq->tags = NULL; | |
247 | } | |
248 | ||
a4aea562 MB |
249 | static int nvme_admin_init_request(void *data, struct request *req, |
250 | unsigned int hctx_idx, unsigned int rq_idx, | |
251 | unsigned int numa_node) | |
22404274 | 252 | { |
a4aea562 | 253 | struct nvme_dev *dev = data; |
f4800d6d | 254 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
a4aea562 MB |
255 | struct nvme_queue *nvmeq = dev->queues[0]; |
256 | ||
257 | BUG_ON(!nvmeq); | |
f4800d6d | 258 | iod->nvmeq = nvmeq; |
a4aea562 | 259 | return 0; |
22404274 KB |
260 | } |
261 | ||
a4aea562 MB |
262 | static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, |
263 | unsigned int hctx_idx) | |
b60503ba | 264 | { |
a4aea562 | 265 | struct nvme_dev *dev = data; |
42483228 | 266 | struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1]; |
a4aea562 | 267 | |
42483228 KB |
268 | if (!nvmeq->tags) |
269 | nvmeq->tags = &dev->tagset.tags[hctx_idx]; | |
b60503ba | 270 | |
42483228 | 271 | WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags); |
a4aea562 MB |
272 | hctx->driver_data = nvmeq; |
273 | return 0; | |
b60503ba MW |
274 | } |
275 | ||
a4aea562 MB |
276 | static int nvme_init_request(void *data, struct request *req, |
277 | unsigned int hctx_idx, unsigned int rq_idx, | |
278 | unsigned int numa_node) | |
b60503ba | 279 | { |
a4aea562 | 280 | struct nvme_dev *dev = data; |
f4800d6d | 281 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
a4aea562 MB |
282 | struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1]; |
283 | ||
284 | BUG_ON(!nvmeq); | |
f4800d6d | 285 | iod->nvmeq = nvmeq; |
a4aea562 MB |
286 | return 0; |
287 | } | |
288 | ||
adf68f21 CH |
289 | static void nvme_complete_async_event(struct nvme_dev *dev, |
290 | struct nvme_completion *cqe) | |
3c0cf138 | 291 | { |
adf68f21 CH |
292 | u16 status = le16_to_cpu(cqe->status) >> 1; |
293 | u32 result = le32_to_cpu(cqe->result); | |
a4aea562 MB |
294 | |
295 | if (status == NVME_SC_SUCCESS || status == NVME_SC_ABORT_REQ) | |
adf68f21 | 296 | ++dev->ctrl.event_limit; |
a5768aa8 KB |
297 | if (status != NVME_SC_SUCCESS) |
298 | return; | |
299 | ||
300 | switch (result & 0xff07) { | |
301 | case NVME_AER_NOTICE_NS_CHANGED: | |
adf68f21 CH |
302 | dev_info(dev->dev, "rescanning\n"); |
303 | queue_work(nvme_workq, &dev->scan_work); | |
a5768aa8 | 304 | default: |
adf68f21 | 305 | dev_warn(dev->dev, "async event result %08x\n", result); |
a5768aa8 | 306 | } |
b60503ba MW |
307 | } |
308 | ||
b60503ba | 309 | /** |
adf68f21 | 310 | * __nvme_submit_cmd() - Copy a command into a queue and ring the doorbell |
b60503ba MW |
311 | * @nvmeq: The queue to use |
312 | * @cmd: The command to send | |
313 | * | |
314 | * Safe to use from interrupt context | |
315 | */ | |
e3f879bf SB |
316 | static void __nvme_submit_cmd(struct nvme_queue *nvmeq, |
317 | struct nvme_command *cmd) | |
b60503ba | 318 | { |
a4aea562 MB |
319 | u16 tail = nvmeq->sq_tail; |
320 | ||
8ffaadf7 JD |
321 | if (nvmeq->sq_cmds_io) |
322 | memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd)); | |
323 | else | |
324 | memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd)); | |
325 | ||
b60503ba MW |
326 | if (++tail == nvmeq->q_depth) |
327 | tail = 0; | |
7547881d | 328 | writel(tail, nvmeq->q_db); |
b60503ba | 329 | nvmeq->sq_tail = tail; |
b60503ba MW |
330 | } |
331 | ||
f4800d6d | 332 | static __le64 **iod_list(struct request *req) |
b60503ba | 333 | { |
f4800d6d CH |
334 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
335 | return (__le64 **)(iod->sg + req->nr_phys_segments); | |
b60503ba MW |
336 | } |
337 | ||
f4800d6d | 338 | static int nvme_init_iod(struct request *rq, struct nvme_dev *dev) |
ac3dd5bd | 339 | { |
f4800d6d CH |
340 | struct nvme_iod *iod = blk_mq_rq_to_pdu(rq); |
341 | int nseg = rq->nr_phys_segments; | |
342 | unsigned size; | |
ac3dd5bd | 343 | |
f4800d6d CH |
344 | if (rq->cmd_flags & REQ_DISCARD) |
345 | size = sizeof(struct nvme_dsm_range); | |
346 | else | |
347 | size = blk_rq_bytes(rq); | |
ac3dd5bd | 348 | |
f4800d6d CH |
349 | if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) { |
350 | iod->sg = kmalloc(nvme_iod_alloc_size(dev, size, nseg), GFP_ATOMIC); | |
351 | if (!iod->sg) | |
352 | return BLK_MQ_RQ_QUEUE_BUSY; | |
353 | } else { | |
354 | iod->sg = iod->inline_sg; | |
ac3dd5bd JA |
355 | } |
356 | ||
f4800d6d CH |
357 | iod->aborted = 0; |
358 | iod->npages = -1; | |
359 | iod->nents = 0; | |
360 | iod->length = size; | |
361 | return 0; | |
ac3dd5bd JA |
362 | } |
363 | ||
f4800d6d | 364 | static void nvme_free_iod(struct nvme_dev *dev, struct request *req) |
b60503ba | 365 | { |
f4800d6d | 366 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
5fd4ce1b | 367 | const int last_prp = dev->ctrl.page_size / 8 - 1; |
eca18b23 | 368 | int i; |
f4800d6d | 369 | __le64 **list = iod_list(req); |
eca18b23 MW |
370 | dma_addr_t prp_dma = iod->first_dma; |
371 | ||
372 | if (iod->npages == 0) | |
373 | dma_pool_free(dev->prp_small_pool, list[0], prp_dma); | |
374 | for (i = 0; i < iod->npages; i++) { | |
375 | __le64 *prp_list = list[i]; | |
376 | dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]); | |
377 | dma_pool_free(dev->prp_page_pool, prp_list, prp_dma); | |
378 | prp_dma = next_prp_dma; | |
379 | } | |
ac3dd5bd | 380 | |
f4800d6d CH |
381 | if (iod->sg != iod->inline_sg) |
382 | kfree(iod->sg); | |
b60503ba MW |
383 | } |
384 | ||
52b68d7e | 385 | #ifdef CONFIG_BLK_DEV_INTEGRITY |
e1e5e564 KB |
386 | static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi) |
387 | { | |
388 | if (be32_to_cpu(pi->ref_tag) == v) | |
389 | pi->ref_tag = cpu_to_be32(p); | |
390 | } | |
391 | ||
392 | static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi) | |
393 | { | |
394 | if (be32_to_cpu(pi->ref_tag) == p) | |
395 | pi->ref_tag = cpu_to_be32(v); | |
396 | } | |
397 | ||
398 | /** | |
399 | * nvme_dif_remap - remaps ref tags to bip seed and physical lba | |
400 | * | |
401 | * The virtual start sector is the one that was originally submitted by the | |
402 | * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical | |
403 | * start sector may be different. Remap protection information to match the | |
404 | * physical LBA on writes, and back to the original seed on reads. | |
405 | * | |
406 | * Type 0 and 3 do not have a ref tag, so no remapping required. | |
407 | */ | |
408 | static void nvme_dif_remap(struct request *req, | |
409 | void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi)) | |
410 | { | |
411 | struct nvme_ns *ns = req->rq_disk->private_data; | |
412 | struct bio_integrity_payload *bip; | |
413 | struct t10_pi_tuple *pi; | |
414 | void *p, *pmap; | |
415 | u32 i, nlb, ts, phys, virt; | |
416 | ||
417 | if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3) | |
418 | return; | |
419 | ||
420 | bip = bio_integrity(req->bio); | |
421 | if (!bip) | |
422 | return; | |
423 | ||
424 | pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset; | |
e1e5e564 KB |
425 | |
426 | p = pmap; | |
427 | virt = bip_get_seed(bip); | |
428 | phys = nvme_block_nr(ns, blk_rq_pos(req)); | |
429 | nlb = (blk_rq_bytes(req) >> ns->lba_shift); | |
ac6fc48c | 430 | ts = ns->disk->queue->integrity.tuple_size; |
e1e5e564 KB |
431 | |
432 | for (i = 0; i < nlb; i++, virt++, phys++) { | |
433 | pi = (struct t10_pi_tuple *)p; | |
434 | dif_swap(phys, virt, pi); | |
435 | p += ts; | |
436 | } | |
437 | kunmap_atomic(pmap); | |
438 | } | |
52b68d7e KB |
439 | #else /* CONFIG_BLK_DEV_INTEGRITY */ |
440 | static void nvme_dif_remap(struct request *req, | |
441 | void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi)) | |
442 | { | |
443 | } | |
444 | static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi) | |
445 | { | |
446 | } | |
447 | static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi) | |
448 | { | |
449 | } | |
52b68d7e KB |
450 | #endif |
451 | ||
f4800d6d | 452 | static bool nvme_setup_prps(struct nvme_dev *dev, struct request *req, |
69d2b571 | 453 | int total_len) |
ff22b54f | 454 | { |
f4800d6d | 455 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
99802a7a | 456 | struct dma_pool *pool; |
eca18b23 MW |
457 | int length = total_len; |
458 | struct scatterlist *sg = iod->sg; | |
ff22b54f MW |
459 | int dma_len = sg_dma_len(sg); |
460 | u64 dma_addr = sg_dma_address(sg); | |
5fd4ce1b | 461 | u32 page_size = dev->ctrl.page_size; |
f137e0f1 | 462 | int offset = dma_addr & (page_size - 1); |
e025344c | 463 | __le64 *prp_list; |
f4800d6d | 464 | __le64 **list = iod_list(req); |
e025344c | 465 | dma_addr_t prp_dma; |
eca18b23 | 466 | int nprps, i; |
ff22b54f | 467 | |
1d090624 | 468 | length -= (page_size - offset); |
ff22b54f | 469 | if (length <= 0) |
69d2b571 | 470 | return true; |
ff22b54f | 471 | |
1d090624 | 472 | dma_len -= (page_size - offset); |
ff22b54f | 473 | if (dma_len) { |
1d090624 | 474 | dma_addr += (page_size - offset); |
ff22b54f MW |
475 | } else { |
476 | sg = sg_next(sg); | |
477 | dma_addr = sg_dma_address(sg); | |
478 | dma_len = sg_dma_len(sg); | |
479 | } | |
480 | ||
1d090624 | 481 | if (length <= page_size) { |
edd10d33 | 482 | iod->first_dma = dma_addr; |
69d2b571 | 483 | return true; |
e025344c SMM |
484 | } |
485 | ||
1d090624 | 486 | nprps = DIV_ROUND_UP(length, page_size); |
99802a7a MW |
487 | if (nprps <= (256 / 8)) { |
488 | pool = dev->prp_small_pool; | |
eca18b23 | 489 | iod->npages = 0; |
99802a7a MW |
490 | } else { |
491 | pool = dev->prp_page_pool; | |
eca18b23 | 492 | iod->npages = 1; |
99802a7a MW |
493 | } |
494 | ||
69d2b571 | 495 | prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); |
b77954cb | 496 | if (!prp_list) { |
edd10d33 | 497 | iod->first_dma = dma_addr; |
eca18b23 | 498 | iod->npages = -1; |
69d2b571 | 499 | return false; |
b77954cb | 500 | } |
eca18b23 MW |
501 | list[0] = prp_list; |
502 | iod->first_dma = prp_dma; | |
e025344c SMM |
503 | i = 0; |
504 | for (;;) { | |
1d090624 | 505 | if (i == page_size >> 3) { |
e025344c | 506 | __le64 *old_prp_list = prp_list; |
69d2b571 | 507 | prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); |
eca18b23 | 508 | if (!prp_list) |
69d2b571 | 509 | return false; |
eca18b23 | 510 | list[iod->npages++] = prp_list; |
7523d834 MW |
511 | prp_list[0] = old_prp_list[i - 1]; |
512 | old_prp_list[i - 1] = cpu_to_le64(prp_dma); | |
513 | i = 1; | |
e025344c SMM |
514 | } |
515 | prp_list[i++] = cpu_to_le64(dma_addr); | |
1d090624 KB |
516 | dma_len -= page_size; |
517 | dma_addr += page_size; | |
518 | length -= page_size; | |
e025344c SMM |
519 | if (length <= 0) |
520 | break; | |
521 | if (dma_len > 0) | |
522 | continue; | |
523 | BUG_ON(dma_len < 0); | |
524 | sg = sg_next(sg); | |
525 | dma_addr = sg_dma_address(sg); | |
526 | dma_len = sg_dma_len(sg); | |
ff22b54f MW |
527 | } |
528 | ||
69d2b571 | 529 | return true; |
ff22b54f MW |
530 | } |
531 | ||
f4800d6d | 532 | static int nvme_map_data(struct nvme_dev *dev, struct request *req, |
ba1ca37e | 533 | struct nvme_command *cmnd) |
d29ec824 | 534 | { |
f4800d6d | 535 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
ba1ca37e CH |
536 | struct request_queue *q = req->q; |
537 | enum dma_data_direction dma_dir = rq_data_dir(req) ? | |
538 | DMA_TO_DEVICE : DMA_FROM_DEVICE; | |
539 | int ret = BLK_MQ_RQ_QUEUE_ERROR; | |
540 | ||
541 | sg_init_table(iod->sg, req->nr_phys_segments); | |
542 | iod->nents = blk_rq_map_sg(q, req, iod->sg); | |
543 | if (!iod->nents) | |
544 | goto out; | |
545 | ||
546 | ret = BLK_MQ_RQ_QUEUE_BUSY; | |
547 | if (!dma_map_sg(dev->dev, iod->sg, iod->nents, dma_dir)) | |
548 | goto out; | |
549 | ||
f4800d6d | 550 | if (!nvme_setup_prps(dev, req, blk_rq_bytes(req))) |
ba1ca37e CH |
551 | goto out_unmap; |
552 | ||
553 | ret = BLK_MQ_RQ_QUEUE_ERROR; | |
554 | if (blk_integrity_rq(req)) { | |
555 | if (blk_rq_count_integrity_sg(q, req->bio) != 1) | |
556 | goto out_unmap; | |
557 | ||
bf684057 CH |
558 | sg_init_table(&iod->meta_sg, 1); |
559 | if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1) | |
ba1ca37e | 560 | goto out_unmap; |
d29ec824 | 561 | |
ba1ca37e CH |
562 | if (rq_data_dir(req)) |
563 | nvme_dif_remap(req, nvme_dif_prep); | |
564 | ||
bf684057 | 565 | if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir)) |
ba1ca37e | 566 | goto out_unmap; |
d29ec824 CH |
567 | } |
568 | ||
ba1ca37e CH |
569 | cmnd->rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg)); |
570 | cmnd->rw.prp2 = cpu_to_le64(iod->first_dma); | |
571 | if (blk_integrity_rq(req)) | |
bf684057 | 572 | cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg)); |
ba1ca37e CH |
573 | return BLK_MQ_RQ_QUEUE_OK; |
574 | ||
575 | out_unmap: | |
576 | dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); | |
577 | out: | |
578 | return ret; | |
d29ec824 CH |
579 | } |
580 | ||
f4800d6d | 581 | static void nvme_unmap_data(struct nvme_dev *dev, struct request *req) |
d4f6c3ab | 582 | { |
f4800d6d | 583 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
d4f6c3ab CH |
584 | enum dma_data_direction dma_dir = rq_data_dir(req) ? |
585 | DMA_TO_DEVICE : DMA_FROM_DEVICE; | |
586 | ||
587 | if (iod->nents) { | |
588 | dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); | |
589 | if (blk_integrity_rq(req)) { | |
590 | if (!rq_data_dir(req)) | |
591 | nvme_dif_remap(req, nvme_dif_complete); | |
bf684057 | 592 | dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir); |
d4f6c3ab CH |
593 | } |
594 | } | |
595 | ||
f4800d6d | 596 | nvme_free_iod(dev, req); |
d4f6c3ab CH |
597 | } |
598 | ||
a4aea562 MB |
599 | /* |
600 | * We reuse the small pool to allocate the 16-byte range here as it is not | |
601 | * worth having a special pool for these or additional cases to handle freeing | |
602 | * the iod. | |
603 | */ | |
ba1ca37e | 604 | static int nvme_setup_discard(struct nvme_queue *nvmeq, struct nvme_ns *ns, |
f4800d6d | 605 | struct request *req, struct nvme_command *cmnd) |
0e5e4f0e | 606 | { |
f4800d6d | 607 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
ba1ca37e CH |
608 | struct nvme_dsm_range *range; |
609 | ||
610 | range = dma_pool_alloc(nvmeq->dev->prp_small_pool, GFP_ATOMIC, | |
611 | &iod->first_dma); | |
612 | if (!range) | |
613 | return BLK_MQ_RQ_QUEUE_BUSY; | |
f4800d6d | 614 | iod_list(req)[0] = (__le64 *)range; |
ba1ca37e | 615 | iod->npages = 0; |
0e5e4f0e | 616 | |
0e5e4f0e | 617 | range->cattr = cpu_to_le32(0); |
a4aea562 MB |
618 | range->nlb = cpu_to_le32(blk_rq_bytes(req) >> ns->lba_shift); |
619 | range->slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req))); | |
0e5e4f0e | 620 | |
ba1ca37e CH |
621 | memset(cmnd, 0, sizeof(*cmnd)); |
622 | cmnd->dsm.opcode = nvme_cmd_dsm; | |
623 | cmnd->dsm.nsid = cpu_to_le32(ns->ns_id); | |
624 | cmnd->dsm.prp1 = cpu_to_le64(iod->first_dma); | |
625 | cmnd->dsm.nr = 0; | |
626 | cmnd->dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD); | |
627 | return BLK_MQ_RQ_QUEUE_OK; | |
0e5e4f0e KB |
628 | } |
629 | ||
d29ec824 CH |
630 | /* |
631 | * NOTE: ns is NULL when called on the admin queue. | |
632 | */ | |
a4aea562 MB |
633 | static int nvme_queue_rq(struct blk_mq_hw_ctx *hctx, |
634 | const struct blk_mq_queue_data *bd) | |
edd10d33 | 635 | { |
a4aea562 MB |
636 | struct nvme_ns *ns = hctx->queue->queuedata; |
637 | struct nvme_queue *nvmeq = hctx->driver_data; | |
d29ec824 | 638 | struct nvme_dev *dev = nvmeq->dev; |
a4aea562 | 639 | struct request *req = bd->rq; |
ba1ca37e CH |
640 | struct nvme_command cmnd; |
641 | int ret = BLK_MQ_RQ_QUEUE_OK; | |
edd10d33 | 642 | |
e1e5e564 KB |
643 | /* |
644 | * If formated with metadata, require the block layer provide a buffer | |
645 | * unless this namespace is formated such that the metadata can be | |
646 | * stripped/generated by the controller with PRACT=1. | |
647 | */ | |
d29ec824 | 648 | if (ns && ns->ms && !blk_integrity_rq(req)) { |
71feb364 KB |
649 | if (!(ns->pi_type && ns->ms == 8) && |
650 | req->cmd_type != REQ_TYPE_DRV_PRIV) { | |
eee417b0 | 651 | blk_mq_end_request(req, -EFAULT); |
e1e5e564 KB |
652 | return BLK_MQ_RQ_QUEUE_OK; |
653 | } | |
654 | } | |
655 | ||
f4800d6d CH |
656 | ret = nvme_init_iod(req, dev); |
657 | if (ret) | |
658 | return ret; | |
a4aea562 | 659 | |
a4aea562 | 660 | if (req->cmd_flags & REQ_DISCARD) { |
f4800d6d | 661 | ret = nvme_setup_discard(nvmeq, ns, req, &cmnd); |
ba1ca37e CH |
662 | } else { |
663 | if (req->cmd_type == REQ_TYPE_DRV_PRIV) | |
664 | memcpy(&cmnd, req->cmd, sizeof(cmnd)); | |
665 | else if (req->cmd_flags & REQ_FLUSH) | |
666 | nvme_setup_flush(ns, &cmnd); | |
667 | else | |
668 | nvme_setup_rw(ns, req, &cmnd); | |
a4aea562 | 669 | |
ba1ca37e | 670 | if (req->nr_phys_segments) |
f4800d6d | 671 | ret = nvme_map_data(dev, req, &cmnd); |
edd10d33 | 672 | } |
1974b1ae | 673 | |
ba1ca37e CH |
674 | if (ret) |
675 | goto out; | |
676 | ||
677 | cmnd.common.command_id = req->tag; | |
aae239e1 | 678 | blk_mq_start_request(req); |
a4aea562 | 679 | |
ba1ca37e CH |
680 | spin_lock_irq(&nvmeq->q_lock); |
681 | __nvme_submit_cmd(nvmeq, &cmnd); | |
a4aea562 MB |
682 | nvme_process_cq(nvmeq); |
683 | spin_unlock_irq(&nvmeq->q_lock); | |
684 | return BLK_MQ_RQ_QUEUE_OK; | |
ba1ca37e | 685 | out: |
f4800d6d | 686 | nvme_free_iod(dev, req); |
ba1ca37e | 687 | return ret; |
b60503ba MW |
688 | } |
689 | ||
eee417b0 CH |
690 | static void nvme_complete_rq(struct request *req) |
691 | { | |
f4800d6d CH |
692 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
693 | struct nvme_dev *dev = iod->nvmeq->dev; | |
eee417b0 CH |
694 | int error = 0; |
695 | ||
f4800d6d | 696 | nvme_unmap_data(dev, req); |
eee417b0 CH |
697 | |
698 | if (unlikely(req->errors)) { | |
699 | if (nvme_req_needs_retry(req, req->errors)) { | |
700 | nvme_requeue_req(req); | |
701 | return; | |
702 | } | |
703 | ||
704 | if (req->cmd_type == REQ_TYPE_DRV_PRIV) | |
705 | error = req->errors; | |
706 | else | |
707 | error = nvme_error_status(req->errors); | |
708 | } | |
709 | ||
f4800d6d | 710 | if (unlikely(iod->aborted)) { |
eee417b0 CH |
711 | dev_warn(dev->dev, |
712 | "completing aborted command with status: %04x\n", | |
713 | req->errors); | |
714 | } | |
715 | ||
716 | blk_mq_end_request(req, error); | |
717 | } | |
718 | ||
a0fa9647 | 719 | static void __nvme_process_cq(struct nvme_queue *nvmeq, unsigned int *tag) |
b60503ba | 720 | { |
82123460 | 721 | u16 head, phase; |
b60503ba | 722 | |
b60503ba | 723 | head = nvmeq->cq_head; |
82123460 | 724 | phase = nvmeq->cq_phase; |
b60503ba MW |
725 | |
726 | for (;;) { | |
b60503ba | 727 | struct nvme_completion cqe = nvmeq->cqes[head]; |
adf68f21 | 728 | u16 status = le16_to_cpu(cqe.status); |
eee417b0 | 729 | struct request *req; |
adf68f21 CH |
730 | |
731 | if ((status & 1) != phase) | |
b60503ba MW |
732 | break; |
733 | nvmeq->sq_head = le16_to_cpu(cqe.sq_head); | |
734 | if (++head == nvmeq->q_depth) { | |
735 | head = 0; | |
82123460 | 736 | phase = !phase; |
b60503ba | 737 | } |
adf68f21 | 738 | |
a0fa9647 JA |
739 | if (tag && *tag == cqe.command_id) |
740 | *tag = -1; | |
adf68f21 | 741 | |
aae239e1 CH |
742 | if (unlikely(cqe.command_id >= nvmeq->q_depth)) { |
743 | dev_warn(nvmeq->q_dmadev, | |
744 | "invalid id %d completed on queue %d\n", | |
745 | cqe.command_id, le16_to_cpu(cqe.sq_id)); | |
746 | continue; | |
747 | } | |
748 | ||
adf68f21 CH |
749 | /* |
750 | * AEN requests are special as they don't time out and can | |
751 | * survive any kind of queue freeze and often don't respond to | |
752 | * aborts. We don't even bother to allocate a struct request | |
753 | * for them but rather special case them here. | |
754 | */ | |
755 | if (unlikely(nvmeq->qid == 0 && | |
756 | cqe.command_id >= NVME_AQ_BLKMQ_DEPTH)) { | |
757 | nvme_complete_async_event(nvmeq->dev, &cqe); | |
758 | continue; | |
759 | } | |
760 | ||
eee417b0 CH |
761 | req = blk_mq_tag_to_rq(*nvmeq->tags, cqe.command_id); |
762 | if (req->cmd_type == REQ_TYPE_DRV_PRIV) { | |
763 | u32 result = le32_to_cpu(cqe.result); | |
764 | req->special = (void *)(uintptr_t)result; | |
765 | } | |
766 | blk_mq_complete_request(req, status >> 1); | |
767 | ||
b60503ba MW |
768 | } |
769 | ||
770 | /* If the controller ignores the cq head doorbell and continuously | |
771 | * writes to the queue, it is theoretically possible to wrap around | |
772 | * the queue twice and mistakenly return IRQ_NONE. Linux only | |
773 | * requires that 0.1% of your interrupts are handled, so this isn't | |
774 | * a big problem. | |
775 | */ | |
82123460 | 776 | if (head == nvmeq->cq_head && phase == nvmeq->cq_phase) |
a0fa9647 | 777 | return; |
b60503ba | 778 | |
604e8c8d KB |
779 | if (likely(nvmeq->cq_vector >= 0)) |
780 | writel(head, nvmeq->q_db + nvmeq->dev->db_stride); | |
b60503ba | 781 | nvmeq->cq_head = head; |
82123460 | 782 | nvmeq->cq_phase = phase; |
b60503ba | 783 | |
e9539f47 | 784 | nvmeq->cqe_seen = 1; |
a0fa9647 JA |
785 | } |
786 | ||
787 | static void nvme_process_cq(struct nvme_queue *nvmeq) | |
788 | { | |
789 | __nvme_process_cq(nvmeq, NULL); | |
b60503ba MW |
790 | } |
791 | ||
792 | static irqreturn_t nvme_irq(int irq, void *data) | |
58ffacb5 MW |
793 | { |
794 | irqreturn_t result; | |
795 | struct nvme_queue *nvmeq = data; | |
796 | spin_lock(&nvmeq->q_lock); | |
e9539f47 MW |
797 | nvme_process_cq(nvmeq); |
798 | result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE; | |
799 | nvmeq->cqe_seen = 0; | |
58ffacb5 MW |
800 | spin_unlock(&nvmeq->q_lock); |
801 | return result; | |
802 | } | |
803 | ||
804 | static irqreturn_t nvme_irq_check(int irq, void *data) | |
805 | { | |
806 | struct nvme_queue *nvmeq = data; | |
807 | struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head]; | |
808 | if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase) | |
809 | return IRQ_NONE; | |
810 | return IRQ_WAKE_THREAD; | |
811 | } | |
812 | ||
a0fa9647 JA |
813 | static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag) |
814 | { | |
815 | struct nvme_queue *nvmeq = hctx->driver_data; | |
816 | ||
817 | if ((le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) == | |
818 | nvmeq->cq_phase) { | |
819 | spin_lock_irq(&nvmeq->q_lock); | |
820 | __nvme_process_cq(nvmeq, &tag); | |
821 | spin_unlock_irq(&nvmeq->q_lock); | |
822 | ||
823 | if (tag == -1) | |
824 | return 1; | |
825 | } | |
826 | ||
827 | return 0; | |
828 | } | |
829 | ||
adf68f21 | 830 | static void nvme_submit_async_event(struct nvme_dev *dev) |
a4aea562 | 831 | { |
a4aea562 | 832 | struct nvme_command c; |
a4aea562 MB |
833 | |
834 | memset(&c, 0, sizeof(c)); | |
835 | c.common.opcode = nvme_admin_async_event; | |
adf68f21 | 836 | c.common.command_id = NVME_AQ_BLKMQ_DEPTH + --dev->ctrl.event_limit; |
a4aea562 | 837 | |
adf68f21 | 838 | __nvme_submit_cmd(dev->queues[0], &c); |
a4aea562 MB |
839 | } |
840 | ||
b60503ba MW |
841 | static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) |
842 | { | |
b60503ba MW |
843 | struct nvme_command c; |
844 | ||
845 | memset(&c, 0, sizeof(c)); | |
846 | c.delete_queue.opcode = opcode; | |
847 | c.delete_queue.qid = cpu_to_le16(id); | |
848 | ||
1c63dc66 | 849 | return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); |
b60503ba MW |
850 | } |
851 | ||
852 | static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, | |
853 | struct nvme_queue *nvmeq) | |
854 | { | |
b60503ba MW |
855 | struct nvme_command c; |
856 | int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED; | |
857 | ||
d29ec824 CH |
858 | /* |
859 | * Note: we (ab)use the fact the the prp fields survive if no data | |
860 | * is attached to the request. | |
861 | */ | |
b60503ba MW |
862 | memset(&c, 0, sizeof(c)); |
863 | c.create_cq.opcode = nvme_admin_create_cq; | |
864 | c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); | |
865 | c.create_cq.cqid = cpu_to_le16(qid); | |
866 | c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); | |
867 | c.create_cq.cq_flags = cpu_to_le16(flags); | |
868 | c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector); | |
869 | ||
1c63dc66 | 870 | return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); |
b60503ba MW |
871 | } |
872 | ||
873 | static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, | |
874 | struct nvme_queue *nvmeq) | |
875 | { | |
b60503ba MW |
876 | struct nvme_command c; |
877 | int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM; | |
878 | ||
d29ec824 CH |
879 | /* |
880 | * Note: we (ab)use the fact the the prp fields survive if no data | |
881 | * is attached to the request. | |
882 | */ | |
b60503ba MW |
883 | memset(&c, 0, sizeof(c)); |
884 | c.create_sq.opcode = nvme_admin_create_sq; | |
885 | c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); | |
886 | c.create_sq.sqid = cpu_to_le16(qid); | |
887 | c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); | |
888 | c.create_sq.sq_flags = cpu_to_le16(flags); | |
889 | c.create_sq.cqid = cpu_to_le16(qid); | |
890 | ||
1c63dc66 | 891 | return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); |
b60503ba MW |
892 | } |
893 | ||
894 | static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) | |
895 | { | |
896 | return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); | |
897 | } | |
898 | ||
899 | static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) | |
900 | { | |
901 | return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); | |
902 | } | |
903 | ||
e7a2a87d CH |
904 | static void abort_endio(struct request *req, int error) |
905 | { | |
f4800d6d CH |
906 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
907 | struct nvme_queue *nvmeq = iod->nvmeq; | |
e7a2a87d CH |
908 | u32 result = (u32)(uintptr_t)req->special; |
909 | u16 status = req->errors; | |
910 | ||
911 | dev_warn(nvmeq->q_dmadev, "Abort status:%x result:%x", status, result); | |
912 | atomic_inc(&nvmeq->dev->ctrl.abort_limit); | |
913 | ||
914 | blk_mq_free_request(req); | |
915 | } | |
916 | ||
31c7c7d2 | 917 | static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved) |
c30341dc | 918 | { |
f4800d6d CH |
919 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
920 | struct nvme_queue *nvmeq = iod->nvmeq; | |
c30341dc | 921 | struct nvme_dev *dev = nvmeq->dev; |
a4aea562 | 922 | struct request *abort_req; |
a4aea562 | 923 | struct nvme_command cmd; |
c30341dc | 924 | |
31c7c7d2 | 925 | /* |
fd634f41 CH |
926 | * Shutdown immediately if controller times out while starting. The |
927 | * reset work will see the pci device disabled when it gets the forced | |
928 | * cancellation error. All outstanding requests are completed on | |
929 | * shutdown, so we return BLK_EH_HANDLED. | |
930 | */ | |
931 | if (test_bit(NVME_CTRL_RESETTING, &dev->flags)) { | |
932 | dev_warn(dev->dev, | |
933 | "I/O %d QID %d timeout, disable controller\n", | |
934 | req->tag, nvmeq->qid); | |
935 | nvme_dev_shutdown(dev); | |
936 | req->errors = NVME_SC_CANCELLED; | |
937 | return BLK_EH_HANDLED; | |
938 | } | |
939 | ||
940 | /* | |
941 | * Shutdown the controller immediately and schedule a reset if the | |
942 | * command was already aborted once before and still hasn't been | |
943 | * returned to the driver, or if this is the admin queue. | |
31c7c7d2 | 944 | */ |
f4800d6d | 945 | if (!nvmeq->qid || iod->aborted) { |
e1569a16 KB |
946 | dev_warn(dev->dev, |
947 | "I/O %d QID %d timeout, reset controller\n", | |
948 | req->tag, nvmeq->qid); | |
949 | nvme_dev_shutdown(dev); | |
950 | queue_work(nvme_workq, &dev->reset_work); | |
951 | ||
952 | /* | |
953 | * Mark the request as handled, since the inline shutdown | |
954 | * forces all outstanding requests to complete. | |
955 | */ | |
956 | req->errors = NVME_SC_CANCELLED; | |
957 | return BLK_EH_HANDLED; | |
c30341dc KB |
958 | } |
959 | ||
f4800d6d | 960 | iod->aborted = 1; |
c30341dc | 961 | |
e7a2a87d | 962 | if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) { |
6bf25d16 | 963 | atomic_inc(&dev->ctrl.abort_limit); |
31c7c7d2 | 964 | return BLK_EH_RESET_TIMER; |
6bf25d16 | 965 | } |
c30341dc KB |
966 | |
967 | memset(&cmd, 0, sizeof(cmd)); | |
968 | cmd.abort.opcode = nvme_admin_abort_cmd; | |
a4aea562 | 969 | cmd.abort.cid = req->tag; |
c30341dc | 970 | cmd.abort.sqid = cpu_to_le16(nvmeq->qid); |
c30341dc | 971 | |
31c7c7d2 CH |
972 | dev_warn(nvmeq->q_dmadev, "I/O %d QID %d timeout, aborting\n", |
973 | req->tag, nvmeq->qid); | |
e7a2a87d CH |
974 | |
975 | abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd, | |
976 | BLK_MQ_REQ_NOWAIT); | |
977 | if (IS_ERR(abort_req)) { | |
978 | atomic_inc(&dev->ctrl.abort_limit); | |
979 | return BLK_EH_RESET_TIMER; | |
980 | } | |
981 | ||
982 | abort_req->timeout = ADMIN_TIMEOUT; | |
983 | abort_req->end_io_data = NULL; | |
984 | blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio); | |
31c7c7d2 CH |
985 | |
986 | /* | |
987 | * The aborted req will be completed on receiving the abort req. | |
988 | * We enable the timer again. If hit twice, it'll cause a device reset, | |
989 | * as the device then is in a faulty state. | |
990 | */ | |
991 | return BLK_EH_RESET_TIMER; | |
c30341dc KB |
992 | } |
993 | ||
42483228 | 994 | static void nvme_cancel_queue_ios(struct request *req, void *data, bool reserved) |
a09115b2 | 995 | { |
a4aea562 | 996 | struct nvme_queue *nvmeq = data; |
aae239e1 | 997 | int status; |
cef6a948 KB |
998 | |
999 | if (!blk_mq_request_started(req)) | |
1000 | return; | |
a09115b2 | 1001 | |
aae239e1 CH |
1002 | dev_warn(nvmeq->q_dmadev, |
1003 | "Cancelling I/O %d QID %d\n", req->tag, nvmeq->qid); | |
a4aea562 | 1004 | |
1d49c38c | 1005 | status = NVME_SC_ABORT_REQ; |
cef6a948 | 1006 | if (blk_queue_dying(req->q)) |
aae239e1 CH |
1007 | status |= NVME_SC_DNR; |
1008 | blk_mq_complete_request(req, status); | |
a09115b2 MW |
1009 | } |
1010 | ||
a4aea562 MB |
1011 | static void nvme_free_queue(struct nvme_queue *nvmeq) |
1012 | { | |
9e866774 MW |
1013 | dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth), |
1014 | (void *)nvmeq->cqes, nvmeq->cq_dma_addr); | |
8ffaadf7 JD |
1015 | if (nvmeq->sq_cmds) |
1016 | dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth), | |
9e866774 MW |
1017 | nvmeq->sq_cmds, nvmeq->sq_dma_addr); |
1018 | kfree(nvmeq); | |
1019 | } | |
1020 | ||
a1a5ef99 | 1021 | static void nvme_free_queues(struct nvme_dev *dev, int lowest) |
22404274 KB |
1022 | { |
1023 | int i; | |
1024 | ||
a1a5ef99 | 1025 | for (i = dev->queue_count - 1; i >= lowest; i--) { |
a4aea562 | 1026 | struct nvme_queue *nvmeq = dev->queues[i]; |
22404274 | 1027 | dev->queue_count--; |
a4aea562 | 1028 | dev->queues[i] = NULL; |
f435c282 | 1029 | nvme_free_queue(nvmeq); |
121c7ad4 | 1030 | } |
22404274 KB |
1031 | } |
1032 | ||
4d115420 KB |
1033 | /** |
1034 | * nvme_suspend_queue - put queue into suspended state | |
1035 | * @nvmeq - queue to suspend | |
4d115420 KB |
1036 | */ |
1037 | static int nvme_suspend_queue(struct nvme_queue *nvmeq) | |
b60503ba | 1038 | { |
2b25d981 | 1039 | int vector; |
b60503ba | 1040 | |
a09115b2 | 1041 | spin_lock_irq(&nvmeq->q_lock); |
2b25d981 KB |
1042 | if (nvmeq->cq_vector == -1) { |
1043 | spin_unlock_irq(&nvmeq->q_lock); | |
1044 | return 1; | |
1045 | } | |
1046 | vector = nvmeq->dev->entry[nvmeq->cq_vector].vector; | |
42f61420 | 1047 | nvmeq->dev->online_queues--; |
2b25d981 | 1048 | nvmeq->cq_vector = -1; |
a09115b2 MW |
1049 | spin_unlock_irq(&nvmeq->q_lock); |
1050 | ||
1c63dc66 | 1051 | if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q) |
25646264 | 1052 | blk_mq_stop_hw_queues(nvmeq->dev->ctrl.admin_q); |
6df3dbc8 | 1053 | |
aba2080f MW |
1054 | irq_set_affinity_hint(vector, NULL); |
1055 | free_irq(vector, nvmeq); | |
b60503ba | 1056 | |
4d115420 KB |
1057 | return 0; |
1058 | } | |
b60503ba | 1059 | |
4d115420 KB |
1060 | static void nvme_clear_queue(struct nvme_queue *nvmeq) |
1061 | { | |
22404274 | 1062 | spin_lock_irq(&nvmeq->q_lock); |
42483228 KB |
1063 | if (nvmeq->tags && *nvmeq->tags) |
1064 | blk_mq_all_tag_busy_iter(*nvmeq->tags, nvme_cancel_queue_ios, nvmeq); | |
22404274 | 1065 | spin_unlock_irq(&nvmeq->q_lock); |
b60503ba MW |
1066 | } |
1067 | ||
4d115420 KB |
1068 | static void nvme_disable_queue(struct nvme_dev *dev, int qid) |
1069 | { | |
a4aea562 | 1070 | struct nvme_queue *nvmeq = dev->queues[qid]; |
4d115420 KB |
1071 | |
1072 | if (!nvmeq) | |
1073 | return; | |
1074 | if (nvme_suspend_queue(nvmeq)) | |
1075 | return; | |
1076 | ||
0e53d180 KB |
1077 | /* Don't tell the adapter to delete the admin queue. |
1078 | * Don't tell a removed adapter to delete IO queues. */ | |
7a67cbea | 1079 | if (qid && readl(dev->bar + NVME_REG_CSTS) != -1) { |
b60503ba MW |
1080 | adapter_delete_sq(dev, qid); |
1081 | adapter_delete_cq(dev, qid); | |
1082 | } | |
07836e65 KB |
1083 | |
1084 | spin_lock_irq(&nvmeq->q_lock); | |
1085 | nvme_process_cq(nvmeq); | |
1086 | spin_unlock_irq(&nvmeq->q_lock); | |
b60503ba MW |
1087 | } |
1088 | ||
8ffaadf7 JD |
1089 | static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues, |
1090 | int entry_size) | |
1091 | { | |
1092 | int q_depth = dev->q_depth; | |
5fd4ce1b CH |
1093 | unsigned q_size_aligned = roundup(q_depth * entry_size, |
1094 | dev->ctrl.page_size); | |
8ffaadf7 JD |
1095 | |
1096 | if (q_size_aligned * nr_io_queues > dev->cmb_size) { | |
c45f5c99 | 1097 | u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues); |
5fd4ce1b | 1098 | mem_per_q = round_down(mem_per_q, dev->ctrl.page_size); |
c45f5c99 | 1099 | q_depth = div_u64(mem_per_q, entry_size); |
8ffaadf7 JD |
1100 | |
1101 | /* | |
1102 | * Ensure the reduced q_depth is above some threshold where it | |
1103 | * would be better to map queues in system memory with the | |
1104 | * original depth | |
1105 | */ | |
1106 | if (q_depth < 64) | |
1107 | return -ENOMEM; | |
1108 | } | |
1109 | ||
1110 | return q_depth; | |
1111 | } | |
1112 | ||
1113 | static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq, | |
1114 | int qid, int depth) | |
1115 | { | |
1116 | if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz)) { | |
5fd4ce1b CH |
1117 | unsigned offset = (qid - 1) * roundup(SQ_SIZE(depth), |
1118 | dev->ctrl.page_size); | |
8ffaadf7 JD |
1119 | nvmeq->sq_dma_addr = dev->cmb_dma_addr + offset; |
1120 | nvmeq->sq_cmds_io = dev->cmb + offset; | |
1121 | } else { | |
1122 | nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth), | |
1123 | &nvmeq->sq_dma_addr, GFP_KERNEL); | |
1124 | if (!nvmeq->sq_cmds) | |
1125 | return -ENOMEM; | |
1126 | } | |
1127 | ||
1128 | return 0; | |
1129 | } | |
1130 | ||
b60503ba | 1131 | static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid, |
2b25d981 | 1132 | int depth) |
b60503ba | 1133 | { |
a4aea562 | 1134 | struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq), GFP_KERNEL); |
b60503ba MW |
1135 | if (!nvmeq) |
1136 | return NULL; | |
1137 | ||
e75ec752 | 1138 | nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth), |
4d51abf9 | 1139 | &nvmeq->cq_dma_addr, GFP_KERNEL); |
b60503ba MW |
1140 | if (!nvmeq->cqes) |
1141 | goto free_nvmeq; | |
b60503ba | 1142 | |
8ffaadf7 | 1143 | if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth)) |
b60503ba MW |
1144 | goto free_cqdma; |
1145 | ||
e75ec752 | 1146 | nvmeq->q_dmadev = dev->dev; |
091b6092 | 1147 | nvmeq->dev = dev; |
3193f07b | 1148 | snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d", |
1c63dc66 | 1149 | dev->ctrl.instance, qid); |
b60503ba MW |
1150 | spin_lock_init(&nvmeq->q_lock); |
1151 | nvmeq->cq_head = 0; | |
82123460 | 1152 | nvmeq->cq_phase = 1; |
b80d5ccc | 1153 | nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; |
b60503ba | 1154 | nvmeq->q_depth = depth; |
c30341dc | 1155 | nvmeq->qid = qid; |
758dd7fd | 1156 | nvmeq->cq_vector = -1; |
a4aea562 | 1157 | dev->queues[qid] = nvmeq; |
b60503ba | 1158 | |
36a7e993 JD |
1159 | /* make sure queue descriptor is set before queue count, for kthread */ |
1160 | mb(); | |
1161 | dev->queue_count++; | |
1162 | ||
b60503ba MW |
1163 | return nvmeq; |
1164 | ||
1165 | free_cqdma: | |
e75ec752 | 1166 | dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes, |
b60503ba MW |
1167 | nvmeq->cq_dma_addr); |
1168 | free_nvmeq: | |
1169 | kfree(nvmeq); | |
1170 | return NULL; | |
1171 | } | |
1172 | ||
3001082c MW |
1173 | static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq, |
1174 | const char *name) | |
1175 | { | |
58ffacb5 MW |
1176 | if (use_threaded_interrupts) |
1177 | return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector, | |
481e5bad | 1178 | nvme_irq_check, nvme_irq, IRQF_SHARED, |
58ffacb5 | 1179 | name, nvmeq); |
3001082c | 1180 | return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq, |
481e5bad | 1181 | IRQF_SHARED, name, nvmeq); |
3001082c MW |
1182 | } |
1183 | ||
22404274 | 1184 | static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) |
b60503ba | 1185 | { |
22404274 | 1186 | struct nvme_dev *dev = nvmeq->dev; |
b60503ba | 1187 | |
7be50e93 | 1188 | spin_lock_irq(&nvmeq->q_lock); |
22404274 KB |
1189 | nvmeq->sq_tail = 0; |
1190 | nvmeq->cq_head = 0; | |
1191 | nvmeq->cq_phase = 1; | |
b80d5ccc | 1192 | nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; |
22404274 | 1193 | memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth)); |
42f61420 | 1194 | dev->online_queues++; |
7be50e93 | 1195 | spin_unlock_irq(&nvmeq->q_lock); |
22404274 KB |
1196 | } |
1197 | ||
1198 | static int nvme_create_queue(struct nvme_queue *nvmeq, int qid) | |
1199 | { | |
1200 | struct nvme_dev *dev = nvmeq->dev; | |
1201 | int result; | |
3f85d50b | 1202 | |
2b25d981 | 1203 | nvmeq->cq_vector = qid - 1; |
b60503ba MW |
1204 | result = adapter_alloc_cq(dev, qid, nvmeq); |
1205 | if (result < 0) | |
22404274 | 1206 | return result; |
b60503ba MW |
1207 | |
1208 | result = adapter_alloc_sq(dev, qid, nvmeq); | |
1209 | if (result < 0) | |
1210 | goto release_cq; | |
1211 | ||
3193f07b | 1212 | result = queue_request_irq(dev, nvmeq, nvmeq->irqname); |
b60503ba MW |
1213 | if (result < 0) |
1214 | goto release_sq; | |
1215 | ||
22404274 | 1216 | nvme_init_queue(nvmeq, qid); |
22404274 | 1217 | return result; |
b60503ba MW |
1218 | |
1219 | release_sq: | |
1220 | adapter_delete_sq(dev, qid); | |
1221 | release_cq: | |
1222 | adapter_delete_cq(dev, qid); | |
22404274 | 1223 | return result; |
b60503ba MW |
1224 | } |
1225 | ||
a4aea562 | 1226 | static struct blk_mq_ops nvme_mq_admin_ops = { |
d29ec824 | 1227 | .queue_rq = nvme_queue_rq, |
eee417b0 | 1228 | .complete = nvme_complete_rq, |
a4aea562 MB |
1229 | .map_queue = blk_mq_map_queue, |
1230 | .init_hctx = nvme_admin_init_hctx, | |
4af0e21c | 1231 | .exit_hctx = nvme_admin_exit_hctx, |
a4aea562 MB |
1232 | .init_request = nvme_admin_init_request, |
1233 | .timeout = nvme_timeout, | |
1234 | }; | |
1235 | ||
1236 | static struct blk_mq_ops nvme_mq_ops = { | |
1237 | .queue_rq = nvme_queue_rq, | |
eee417b0 | 1238 | .complete = nvme_complete_rq, |
a4aea562 MB |
1239 | .map_queue = blk_mq_map_queue, |
1240 | .init_hctx = nvme_init_hctx, | |
1241 | .init_request = nvme_init_request, | |
1242 | .timeout = nvme_timeout, | |
a0fa9647 | 1243 | .poll = nvme_poll, |
a4aea562 MB |
1244 | }; |
1245 | ||
ea191d2f KB |
1246 | static void nvme_dev_remove_admin(struct nvme_dev *dev) |
1247 | { | |
1c63dc66 CH |
1248 | if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) { |
1249 | blk_cleanup_queue(dev->ctrl.admin_q); | |
ea191d2f KB |
1250 | blk_mq_free_tag_set(&dev->admin_tagset); |
1251 | } | |
1252 | } | |
1253 | ||
a4aea562 MB |
1254 | static int nvme_alloc_admin_tags(struct nvme_dev *dev) |
1255 | { | |
1c63dc66 | 1256 | if (!dev->ctrl.admin_q) { |
a4aea562 MB |
1257 | dev->admin_tagset.ops = &nvme_mq_admin_ops; |
1258 | dev->admin_tagset.nr_hw_queues = 1; | |
e3e9d50c KB |
1259 | |
1260 | /* | |
1261 | * Subtract one to leave an empty queue entry for 'Full Queue' | |
1262 | * condition. See NVM-Express 1.2 specification, section 4.1.2. | |
1263 | */ | |
1264 | dev->admin_tagset.queue_depth = NVME_AQ_BLKMQ_DEPTH - 1; | |
a4aea562 | 1265 | dev->admin_tagset.timeout = ADMIN_TIMEOUT; |
e75ec752 | 1266 | dev->admin_tagset.numa_node = dev_to_node(dev->dev); |
ac3dd5bd | 1267 | dev->admin_tagset.cmd_size = nvme_cmd_size(dev); |
a4aea562 MB |
1268 | dev->admin_tagset.driver_data = dev; |
1269 | ||
1270 | if (blk_mq_alloc_tag_set(&dev->admin_tagset)) | |
1271 | return -ENOMEM; | |
1272 | ||
1c63dc66 CH |
1273 | dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset); |
1274 | if (IS_ERR(dev->ctrl.admin_q)) { | |
a4aea562 MB |
1275 | blk_mq_free_tag_set(&dev->admin_tagset); |
1276 | return -ENOMEM; | |
1277 | } | |
1c63dc66 | 1278 | if (!blk_get_queue(dev->ctrl.admin_q)) { |
ea191d2f | 1279 | nvme_dev_remove_admin(dev); |
1c63dc66 | 1280 | dev->ctrl.admin_q = NULL; |
ea191d2f KB |
1281 | return -ENODEV; |
1282 | } | |
0fb59cbc | 1283 | } else |
25646264 | 1284 | blk_mq_start_stopped_hw_queues(dev->ctrl.admin_q, true); |
a4aea562 MB |
1285 | |
1286 | return 0; | |
1287 | } | |
1288 | ||
8d85fce7 | 1289 | static int nvme_configure_admin_queue(struct nvme_dev *dev) |
b60503ba | 1290 | { |
ba47e386 | 1291 | int result; |
b60503ba | 1292 | u32 aqa; |
7a67cbea | 1293 | u64 cap = lo_hi_readq(dev->bar + NVME_REG_CAP); |
b60503ba MW |
1294 | struct nvme_queue *nvmeq; |
1295 | ||
7a67cbea | 1296 | dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1) ? |
dfbac8c7 KB |
1297 | NVME_CAP_NSSRC(cap) : 0; |
1298 | ||
7a67cbea CH |
1299 | if (dev->subsystem && |
1300 | (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO)) | |
1301 | writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS); | |
dfbac8c7 | 1302 | |
5fd4ce1b | 1303 | result = nvme_disable_ctrl(&dev->ctrl, cap); |
ba47e386 MW |
1304 | if (result < 0) |
1305 | return result; | |
b60503ba | 1306 | |
a4aea562 | 1307 | nvmeq = dev->queues[0]; |
cd638946 | 1308 | if (!nvmeq) { |
2b25d981 | 1309 | nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH); |
cd638946 KB |
1310 | if (!nvmeq) |
1311 | return -ENOMEM; | |
cd638946 | 1312 | } |
b60503ba MW |
1313 | |
1314 | aqa = nvmeq->q_depth - 1; | |
1315 | aqa |= aqa << 16; | |
1316 | ||
7a67cbea CH |
1317 | writel(aqa, dev->bar + NVME_REG_AQA); |
1318 | lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ); | |
1319 | lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ); | |
b60503ba | 1320 | |
5fd4ce1b | 1321 | result = nvme_enable_ctrl(&dev->ctrl, cap); |
025c557a | 1322 | if (result) |
a4aea562 MB |
1323 | goto free_nvmeq; |
1324 | ||
2b25d981 | 1325 | nvmeq->cq_vector = 0; |
3193f07b | 1326 | result = queue_request_irq(dev, nvmeq, nvmeq->irqname); |
758dd7fd JD |
1327 | if (result) { |
1328 | nvmeq->cq_vector = -1; | |
0fb59cbc | 1329 | goto free_nvmeq; |
758dd7fd | 1330 | } |
025c557a | 1331 | |
b60503ba | 1332 | return result; |
a4aea562 | 1333 | |
a4aea562 MB |
1334 | free_nvmeq: |
1335 | nvme_free_queues(dev, 0); | |
1336 | return result; | |
b60503ba MW |
1337 | } |
1338 | ||
1fa6aead MW |
1339 | static int nvme_kthread(void *data) |
1340 | { | |
d4b4ff8e | 1341 | struct nvme_dev *dev, *next; |
1fa6aead MW |
1342 | |
1343 | while (!kthread_should_stop()) { | |
564a232c | 1344 | set_current_state(TASK_INTERRUPTIBLE); |
1fa6aead | 1345 | spin_lock(&dev_list_lock); |
d4b4ff8e | 1346 | list_for_each_entry_safe(dev, next, &dev_list, node) { |
1fa6aead | 1347 | int i; |
7a67cbea | 1348 | u32 csts = readl(dev->bar + NVME_REG_CSTS); |
dfbac8c7 | 1349 | |
846cc05f CH |
1350 | /* |
1351 | * Skip controllers currently under reset. | |
1352 | */ | |
1353 | if (work_pending(&dev->reset_work) || work_busy(&dev->reset_work)) | |
1354 | continue; | |
1355 | ||
dfbac8c7 KB |
1356 | if ((dev->subsystem && (csts & NVME_CSTS_NSSRO)) || |
1357 | csts & NVME_CSTS_CFS) { | |
846cc05f | 1358 | if (queue_work(nvme_workq, &dev->reset_work)) { |
90667892 CH |
1359 | dev_warn(dev->dev, |
1360 | "Failed status: %x, reset controller\n", | |
7a67cbea | 1361 | readl(dev->bar + NVME_REG_CSTS)); |
90667892 | 1362 | } |
d4b4ff8e KB |
1363 | continue; |
1364 | } | |
1fa6aead | 1365 | for (i = 0; i < dev->queue_count; i++) { |
a4aea562 | 1366 | struct nvme_queue *nvmeq = dev->queues[i]; |
740216fc MW |
1367 | if (!nvmeq) |
1368 | continue; | |
1fa6aead | 1369 | spin_lock_irq(&nvmeq->q_lock); |
bc57a0f7 | 1370 | nvme_process_cq(nvmeq); |
6fccf938 | 1371 | |
adf68f21 CH |
1372 | while (i == 0 && dev->ctrl.event_limit > 0) |
1373 | nvme_submit_async_event(dev); | |
1fa6aead MW |
1374 | spin_unlock_irq(&nvmeq->q_lock); |
1375 | } | |
1376 | } | |
1377 | spin_unlock(&dev_list_lock); | |
acb7aa0d | 1378 | schedule_timeout(round_jiffies_relative(HZ)); |
1fa6aead MW |
1379 | } |
1380 | return 0; | |
1381 | } | |
1382 | ||
749941f2 | 1383 | static int nvme_create_io_queues(struct nvme_dev *dev) |
42f61420 | 1384 | { |
a4aea562 | 1385 | unsigned i; |
749941f2 | 1386 | int ret = 0; |
42f61420 | 1387 | |
749941f2 CH |
1388 | for (i = dev->queue_count; i <= dev->max_qid; i++) { |
1389 | if (!nvme_alloc_queue(dev, i, dev->q_depth)) { | |
1390 | ret = -ENOMEM; | |
42f61420 | 1391 | break; |
749941f2 CH |
1392 | } |
1393 | } | |
42f61420 | 1394 | |
749941f2 CH |
1395 | for (i = dev->online_queues; i <= dev->queue_count - 1; i++) { |
1396 | ret = nvme_create_queue(dev->queues[i], i); | |
1397 | if (ret) { | |
2659e57b | 1398 | nvme_free_queues(dev, i); |
42f61420 | 1399 | break; |
2659e57b | 1400 | } |
749941f2 CH |
1401 | } |
1402 | ||
1403 | /* | |
1404 | * Ignore failing Create SQ/CQ commands, we can continue with less | |
1405 | * than the desired aount of queues, and even a controller without | |
1406 | * I/O queues an still be used to issue admin commands. This might | |
1407 | * be useful to upgrade a buggy firmware for example. | |
1408 | */ | |
1409 | return ret >= 0 ? 0 : ret; | |
42f61420 KB |
1410 | } |
1411 | ||
8ffaadf7 JD |
1412 | static void __iomem *nvme_map_cmb(struct nvme_dev *dev) |
1413 | { | |
1414 | u64 szu, size, offset; | |
1415 | u32 cmbloc; | |
1416 | resource_size_t bar_size; | |
1417 | struct pci_dev *pdev = to_pci_dev(dev->dev); | |
1418 | void __iomem *cmb; | |
1419 | dma_addr_t dma_addr; | |
1420 | ||
1421 | if (!use_cmb_sqes) | |
1422 | return NULL; | |
1423 | ||
7a67cbea | 1424 | dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ); |
8ffaadf7 JD |
1425 | if (!(NVME_CMB_SZ(dev->cmbsz))) |
1426 | return NULL; | |
1427 | ||
7a67cbea | 1428 | cmbloc = readl(dev->bar + NVME_REG_CMBLOC); |
8ffaadf7 JD |
1429 | |
1430 | szu = (u64)1 << (12 + 4 * NVME_CMB_SZU(dev->cmbsz)); | |
1431 | size = szu * NVME_CMB_SZ(dev->cmbsz); | |
1432 | offset = szu * NVME_CMB_OFST(cmbloc); | |
1433 | bar_size = pci_resource_len(pdev, NVME_CMB_BIR(cmbloc)); | |
1434 | ||
1435 | if (offset > bar_size) | |
1436 | return NULL; | |
1437 | ||
1438 | /* | |
1439 | * Controllers may support a CMB size larger than their BAR, | |
1440 | * for example, due to being behind a bridge. Reduce the CMB to | |
1441 | * the reported size of the BAR | |
1442 | */ | |
1443 | if (size > bar_size - offset) | |
1444 | size = bar_size - offset; | |
1445 | ||
1446 | dma_addr = pci_resource_start(pdev, NVME_CMB_BIR(cmbloc)) + offset; | |
1447 | cmb = ioremap_wc(dma_addr, size); | |
1448 | if (!cmb) | |
1449 | return NULL; | |
1450 | ||
1451 | dev->cmb_dma_addr = dma_addr; | |
1452 | dev->cmb_size = size; | |
1453 | return cmb; | |
1454 | } | |
1455 | ||
1456 | static inline void nvme_release_cmb(struct nvme_dev *dev) | |
1457 | { | |
1458 | if (dev->cmb) { | |
1459 | iounmap(dev->cmb); | |
1460 | dev->cmb = NULL; | |
1461 | } | |
1462 | } | |
1463 | ||
9d713c2b KB |
1464 | static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) |
1465 | { | |
b80d5ccc | 1466 | return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride); |
9d713c2b KB |
1467 | } |
1468 | ||
8d85fce7 | 1469 | static int nvme_setup_io_queues(struct nvme_dev *dev) |
b60503ba | 1470 | { |
a4aea562 | 1471 | struct nvme_queue *adminq = dev->queues[0]; |
e75ec752 | 1472 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
42f61420 | 1473 | int result, i, vecs, nr_io_queues, size; |
b60503ba | 1474 | |
42f61420 | 1475 | nr_io_queues = num_possible_cpus(); |
9a0be7ab CH |
1476 | result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues); |
1477 | if (result < 0) | |
1b23484b | 1478 | return result; |
9a0be7ab CH |
1479 | |
1480 | /* | |
1481 | * Degraded controllers might return an error when setting the queue | |
1482 | * count. We still want to be able to bring them online and offer | |
1483 | * access to the admin queue, as that might be only way to fix them up. | |
1484 | */ | |
1485 | if (result > 0) { | |
1486 | dev_err(dev->dev, "Could not set queue count (%d)\n", result); | |
1487 | nr_io_queues = 0; | |
1488 | result = 0; | |
1489 | } | |
b60503ba | 1490 | |
8ffaadf7 JD |
1491 | if (dev->cmb && NVME_CMB_SQS(dev->cmbsz)) { |
1492 | result = nvme_cmb_qdepth(dev, nr_io_queues, | |
1493 | sizeof(struct nvme_command)); | |
1494 | if (result > 0) | |
1495 | dev->q_depth = result; | |
1496 | else | |
1497 | nvme_release_cmb(dev); | |
1498 | } | |
1499 | ||
9d713c2b KB |
1500 | size = db_bar_size(dev, nr_io_queues); |
1501 | if (size > 8192) { | |
f1938f6e | 1502 | iounmap(dev->bar); |
9d713c2b KB |
1503 | do { |
1504 | dev->bar = ioremap(pci_resource_start(pdev, 0), size); | |
1505 | if (dev->bar) | |
1506 | break; | |
1507 | if (!--nr_io_queues) | |
1508 | return -ENOMEM; | |
1509 | size = db_bar_size(dev, nr_io_queues); | |
1510 | } while (1); | |
7a67cbea | 1511 | dev->dbs = dev->bar + 4096; |
5a92e700 | 1512 | adminq->q_db = dev->dbs; |
f1938f6e MW |
1513 | } |
1514 | ||
9d713c2b | 1515 | /* Deregister the admin queue's interrupt */ |
3193f07b | 1516 | free_irq(dev->entry[0].vector, adminq); |
9d713c2b | 1517 | |
e32efbfc JA |
1518 | /* |
1519 | * If we enable msix early due to not intx, disable it again before | |
1520 | * setting up the full range we need. | |
1521 | */ | |
1522 | if (!pdev->irq) | |
1523 | pci_disable_msix(pdev); | |
1524 | ||
be577fab | 1525 | for (i = 0; i < nr_io_queues; i++) |
1b23484b | 1526 | dev->entry[i].entry = i; |
be577fab AG |
1527 | vecs = pci_enable_msix_range(pdev, dev->entry, 1, nr_io_queues); |
1528 | if (vecs < 0) { | |
1529 | vecs = pci_enable_msi_range(pdev, 1, min(nr_io_queues, 32)); | |
1530 | if (vecs < 0) { | |
1531 | vecs = 1; | |
1532 | } else { | |
1533 | for (i = 0; i < vecs; i++) | |
1534 | dev->entry[i].vector = i + pdev->irq; | |
fa08a396 RRG |
1535 | } |
1536 | } | |
1537 | ||
063a8096 MW |
1538 | /* |
1539 | * Should investigate if there's a performance win from allocating | |
1540 | * more queues than interrupt vectors; it might allow the submission | |
1541 | * path to scale better, even if the receive path is limited by the | |
1542 | * number of interrupts. | |
1543 | */ | |
1544 | nr_io_queues = vecs; | |
42f61420 | 1545 | dev->max_qid = nr_io_queues; |
063a8096 | 1546 | |
3193f07b | 1547 | result = queue_request_irq(dev, adminq, adminq->irqname); |
758dd7fd JD |
1548 | if (result) { |
1549 | adminq->cq_vector = -1; | |
22404274 | 1550 | goto free_queues; |
758dd7fd | 1551 | } |
1b23484b | 1552 | |
cd638946 | 1553 | /* Free previously allocated queues that are no longer usable */ |
42f61420 | 1554 | nvme_free_queues(dev, nr_io_queues + 1); |
749941f2 | 1555 | return nvme_create_io_queues(dev); |
b60503ba | 1556 | |
22404274 | 1557 | free_queues: |
a1a5ef99 | 1558 | nvme_free_queues(dev, 1); |
22404274 | 1559 | return result; |
b60503ba MW |
1560 | } |
1561 | ||
bda4e0fb KB |
1562 | static void nvme_set_irq_hints(struct nvme_dev *dev) |
1563 | { | |
1564 | struct nvme_queue *nvmeq; | |
1565 | int i; | |
1566 | ||
1567 | for (i = 0; i < dev->online_queues; i++) { | |
1568 | nvmeq = dev->queues[i]; | |
1569 | ||
1570 | if (!nvmeq->tags || !(*nvmeq->tags)) | |
1571 | continue; | |
1572 | ||
1573 | irq_set_affinity_hint(dev->entry[nvmeq->cq_vector].vector, | |
1574 | blk_mq_tags_cpumask(*nvmeq->tags)); | |
1575 | } | |
1576 | } | |
1577 | ||
a5768aa8 KB |
1578 | static void nvme_dev_scan(struct work_struct *work) |
1579 | { | |
1580 | struct nvme_dev *dev = container_of(work, struct nvme_dev, scan_work); | |
a5768aa8 KB |
1581 | |
1582 | if (!dev->tagset.tags) | |
1583 | return; | |
5bae7f73 | 1584 | nvme_scan_namespaces(&dev->ctrl); |
bda4e0fb | 1585 | nvme_set_irq_hints(dev); |
a5768aa8 KB |
1586 | } |
1587 | ||
db3cbfff KB |
1588 | static void nvme_del_queue_end(struct request *req, int error) |
1589 | { | |
1590 | struct nvme_queue *nvmeq = req->end_io_data; | |
1591 | ||
1592 | blk_mq_free_request(req); | |
1593 | complete(&nvmeq->dev->ioq_wait); | |
1594 | } | |
1595 | ||
1596 | static void nvme_del_cq_end(struct request *req, int error) | |
1597 | { | |
1598 | struct nvme_queue *nvmeq = req->end_io_data; | |
1599 | ||
1600 | if (!error) { | |
1601 | unsigned long flags; | |
1602 | ||
1603 | spin_lock_irqsave(&nvmeq->q_lock, flags); | |
1604 | nvme_process_cq(nvmeq); | |
1605 | spin_unlock_irqrestore(&nvmeq->q_lock, flags); | |
1606 | } | |
1607 | ||
1608 | nvme_del_queue_end(req, error); | |
1609 | } | |
1610 | ||
1611 | static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode) | |
1612 | { | |
1613 | struct request_queue *q = nvmeq->dev->ctrl.admin_q; | |
1614 | struct request *req; | |
1615 | struct nvme_command cmd; | |
1616 | ||
1617 | memset(&cmd, 0, sizeof(cmd)); | |
1618 | cmd.delete_queue.opcode = opcode; | |
1619 | cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid); | |
1620 | ||
1621 | req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT); | |
1622 | if (IS_ERR(req)) | |
1623 | return PTR_ERR(req); | |
1624 | ||
1625 | req->timeout = ADMIN_TIMEOUT; | |
1626 | req->end_io_data = nvmeq; | |
1627 | ||
1628 | blk_execute_rq_nowait(q, NULL, req, false, | |
1629 | opcode == nvme_admin_delete_cq ? | |
1630 | nvme_del_cq_end : nvme_del_queue_end); | |
1631 | return 0; | |
1632 | } | |
1633 | ||
1634 | static void nvme_disable_io_queues(struct nvme_dev *dev) | |
1635 | { | |
1636 | int pass; | |
1637 | unsigned long timeout; | |
1638 | u8 opcode = nvme_admin_delete_sq; | |
1639 | ||
1640 | for (pass = 0; pass < 2; pass++) { | |
1641 | int sent = 0, i = dev->queue_count - 1; | |
1642 | ||
1643 | reinit_completion(&dev->ioq_wait); | |
1644 | retry: | |
1645 | timeout = ADMIN_TIMEOUT; | |
1646 | for (; i > 0; i--) { | |
1647 | struct nvme_queue *nvmeq = dev->queues[i]; | |
1648 | ||
1649 | if (!pass) | |
1650 | nvme_suspend_queue(nvmeq); | |
1651 | if (nvme_delete_queue(nvmeq, opcode)) | |
1652 | break; | |
1653 | ++sent; | |
1654 | } | |
1655 | while (sent--) { | |
1656 | timeout = wait_for_completion_io_timeout(&dev->ioq_wait, timeout); | |
1657 | if (timeout == 0) | |
1658 | return; | |
1659 | if (i) | |
1660 | goto retry; | |
1661 | } | |
1662 | opcode = nvme_admin_delete_cq; | |
1663 | } | |
1664 | } | |
1665 | ||
422ef0c7 MW |
1666 | /* |
1667 | * Return: error value if an error occurred setting up the queues or calling | |
1668 | * Identify Device. 0 if these succeeded, even if adding some of the | |
1669 | * namespaces failed. At the moment, these failures are silent. TBD which | |
1670 | * failures should be reported. | |
1671 | */ | |
8d85fce7 | 1672 | static int nvme_dev_add(struct nvme_dev *dev) |
b60503ba | 1673 | { |
5bae7f73 | 1674 | if (!dev->ctrl.tagset) { |
ffe7704d KB |
1675 | dev->tagset.ops = &nvme_mq_ops; |
1676 | dev->tagset.nr_hw_queues = dev->online_queues - 1; | |
1677 | dev->tagset.timeout = NVME_IO_TIMEOUT; | |
1678 | dev->tagset.numa_node = dev_to_node(dev->dev); | |
1679 | dev->tagset.queue_depth = | |
a4aea562 | 1680 | min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1; |
ffe7704d KB |
1681 | dev->tagset.cmd_size = nvme_cmd_size(dev); |
1682 | dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE; | |
1683 | dev->tagset.driver_data = dev; | |
b60503ba | 1684 | |
ffe7704d KB |
1685 | if (blk_mq_alloc_tag_set(&dev->tagset)) |
1686 | return 0; | |
5bae7f73 | 1687 | dev->ctrl.tagset = &dev->tagset; |
ffe7704d | 1688 | } |
92f7a162 | 1689 | queue_work(nvme_workq, &dev->scan_work); |
e1e5e564 | 1690 | return 0; |
b60503ba MW |
1691 | } |
1692 | ||
0877cb0d KB |
1693 | static int nvme_dev_map(struct nvme_dev *dev) |
1694 | { | |
42f61420 | 1695 | u64 cap; |
0877cb0d | 1696 | int bars, result = -ENOMEM; |
e75ec752 | 1697 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
0877cb0d KB |
1698 | |
1699 | if (pci_enable_device_mem(pdev)) | |
1700 | return result; | |
1701 | ||
1702 | dev->entry[0].vector = pdev->irq; | |
1703 | pci_set_master(pdev); | |
1704 | bars = pci_select_bars(pdev, IORESOURCE_MEM); | |
be7837e8 JA |
1705 | if (!bars) |
1706 | goto disable_pci; | |
1707 | ||
0877cb0d KB |
1708 | if (pci_request_selected_regions(pdev, bars, "nvme")) |
1709 | goto disable_pci; | |
1710 | ||
e75ec752 CH |
1711 | if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) && |
1712 | dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32))) | |
052d0efa | 1713 | goto disable; |
0877cb0d | 1714 | |
0877cb0d KB |
1715 | dev->bar = ioremap(pci_resource_start(pdev, 0), 8192); |
1716 | if (!dev->bar) | |
1717 | goto disable; | |
e32efbfc | 1718 | |
7a67cbea | 1719 | if (readl(dev->bar + NVME_REG_CSTS) == -1) { |
0e53d180 KB |
1720 | result = -ENODEV; |
1721 | goto unmap; | |
1722 | } | |
e32efbfc JA |
1723 | |
1724 | /* | |
1725 | * Some devices don't advertse INTx interrupts, pre-enable a single | |
1726 | * MSIX vec for setup. We'll adjust this later. | |
1727 | */ | |
1728 | if (!pdev->irq) { | |
1729 | result = pci_enable_msix(pdev, dev->entry, 1); | |
1730 | if (result < 0) | |
1731 | goto unmap; | |
1732 | } | |
1733 | ||
7a67cbea CH |
1734 | cap = lo_hi_readq(dev->bar + NVME_REG_CAP); |
1735 | ||
42f61420 KB |
1736 | dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH); |
1737 | dev->db_stride = 1 << NVME_CAP_STRIDE(cap); | |
7a67cbea CH |
1738 | dev->dbs = dev->bar + 4096; |
1739 | if (readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 2)) | |
8ffaadf7 | 1740 | dev->cmb = nvme_map_cmb(dev); |
0877cb0d | 1741 | |
a0a3408e KB |
1742 | pci_enable_pcie_error_reporting(pdev); |
1743 | pci_save_state(pdev); | |
0877cb0d KB |
1744 | return 0; |
1745 | ||
0e53d180 KB |
1746 | unmap: |
1747 | iounmap(dev->bar); | |
1748 | dev->bar = NULL; | |
0877cb0d KB |
1749 | disable: |
1750 | pci_release_regions(pdev); | |
1751 | disable_pci: | |
1752 | pci_disable_device(pdev); | |
1753 | return result; | |
1754 | } | |
1755 | ||
1756 | static void nvme_dev_unmap(struct nvme_dev *dev) | |
1757 | { | |
e75ec752 CH |
1758 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
1759 | ||
1760 | if (pdev->msi_enabled) | |
1761 | pci_disable_msi(pdev); | |
1762 | else if (pdev->msix_enabled) | |
1763 | pci_disable_msix(pdev); | |
0877cb0d KB |
1764 | |
1765 | if (dev->bar) { | |
1766 | iounmap(dev->bar); | |
1767 | dev->bar = NULL; | |
e75ec752 | 1768 | pci_release_regions(pdev); |
0877cb0d KB |
1769 | } |
1770 | ||
a0a3408e KB |
1771 | if (pci_is_enabled(pdev)) { |
1772 | pci_disable_pcie_error_reporting(pdev); | |
e75ec752 | 1773 | pci_disable_device(pdev); |
a0a3408e | 1774 | } |
0877cb0d KB |
1775 | } |
1776 | ||
7385014c CH |
1777 | static int nvme_dev_list_add(struct nvme_dev *dev) |
1778 | { | |
1779 | bool start_thread = false; | |
1780 | ||
1781 | spin_lock(&dev_list_lock); | |
1782 | if (list_empty(&dev_list) && IS_ERR_OR_NULL(nvme_thread)) { | |
1783 | start_thread = true; | |
1784 | nvme_thread = NULL; | |
1785 | } | |
1786 | list_add(&dev->node, &dev_list); | |
1787 | spin_unlock(&dev_list_lock); | |
1788 | ||
1789 | if (start_thread) { | |
1790 | nvme_thread = kthread_run(nvme_kthread, NULL, "nvme"); | |
1791 | wake_up_all(&nvme_kthread_wait); | |
1792 | } else | |
1793 | wait_event_killable(nvme_kthread_wait, nvme_thread); | |
1794 | ||
1795 | if (IS_ERR_OR_NULL(nvme_thread)) | |
1796 | return nvme_thread ? PTR_ERR(nvme_thread) : -EINTR; | |
1797 | ||
1798 | return 0; | |
1799 | } | |
1800 | ||
b9afca3e DM |
1801 | /* |
1802 | * Remove the node from the device list and check | |
1803 | * for whether or not we need to stop the nvme_thread. | |
1804 | */ | |
1805 | static void nvme_dev_list_remove(struct nvme_dev *dev) | |
1806 | { | |
1807 | struct task_struct *tmp = NULL; | |
1808 | ||
1809 | spin_lock(&dev_list_lock); | |
1810 | list_del_init(&dev->node); | |
1811 | if (list_empty(&dev_list) && !IS_ERR_OR_NULL(nvme_thread)) { | |
1812 | tmp = nvme_thread; | |
1813 | nvme_thread = NULL; | |
1814 | } | |
1815 | spin_unlock(&dev_list_lock); | |
1816 | ||
1817 | if (tmp) | |
1818 | kthread_stop(tmp); | |
1819 | } | |
1820 | ||
f0b50732 | 1821 | static void nvme_dev_shutdown(struct nvme_dev *dev) |
b60503ba | 1822 | { |
22404274 | 1823 | int i; |
7c1b2450 | 1824 | u32 csts = -1; |
22404274 | 1825 | |
b9afca3e | 1826 | nvme_dev_list_remove(dev); |
1fa6aead | 1827 | |
77bf25ea | 1828 | mutex_lock(&dev->shutdown_lock); |
c9d3bf88 | 1829 | if (dev->bar) { |
25646264 | 1830 | nvme_stop_queues(&dev->ctrl); |
7a67cbea | 1831 | csts = readl(dev->bar + NVME_REG_CSTS); |
c9d3bf88 | 1832 | } |
7c1b2450 | 1833 | if (csts & NVME_CSTS_CFS || !(csts & NVME_CSTS_RDY)) { |
4d115420 | 1834 | for (i = dev->queue_count - 1; i >= 0; i--) { |
a4aea562 | 1835 | struct nvme_queue *nvmeq = dev->queues[i]; |
4d115420 | 1836 | nvme_suspend_queue(nvmeq); |
4d115420 KB |
1837 | } |
1838 | } else { | |
1839 | nvme_disable_io_queues(dev); | |
5fd4ce1b | 1840 | nvme_shutdown_ctrl(&dev->ctrl); |
4d115420 KB |
1841 | nvme_disable_queue(dev, 0); |
1842 | } | |
f0b50732 | 1843 | nvme_dev_unmap(dev); |
07836e65 KB |
1844 | |
1845 | for (i = dev->queue_count - 1; i >= 0; i--) | |
1846 | nvme_clear_queue(dev->queues[i]); | |
77bf25ea | 1847 | mutex_unlock(&dev->shutdown_lock); |
f0b50732 KB |
1848 | } |
1849 | ||
091b6092 MW |
1850 | static int nvme_setup_prp_pools(struct nvme_dev *dev) |
1851 | { | |
e75ec752 | 1852 | dev->prp_page_pool = dma_pool_create("prp list page", dev->dev, |
091b6092 MW |
1853 | PAGE_SIZE, PAGE_SIZE, 0); |
1854 | if (!dev->prp_page_pool) | |
1855 | return -ENOMEM; | |
1856 | ||
99802a7a | 1857 | /* Optimisation for I/Os between 4k and 128k */ |
e75ec752 | 1858 | dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev, |
99802a7a MW |
1859 | 256, 256, 0); |
1860 | if (!dev->prp_small_pool) { | |
1861 | dma_pool_destroy(dev->prp_page_pool); | |
1862 | return -ENOMEM; | |
1863 | } | |
091b6092 MW |
1864 | return 0; |
1865 | } | |
1866 | ||
1867 | static void nvme_release_prp_pools(struct nvme_dev *dev) | |
1868 | { | |
1869 | dma_pool_destroy(dev->prp_page_pool); | |
99802a7a | 1870 | dma_pool_destroy(dev->prp_small_pool); |
091b6092 MW |
1871 | } |
1872 | ||
1673f1f0 | 1873 | static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl) |
5e82e952 | 1874 | { |
1673f1f0 | 1875 | struct nvme_dev *dev = to_nvme_dev(ctrl); |
9ac27090 | 1876 | |
e75ec752 | 1877 | put_device(dev->dev); |
4af0e21c KB |
1878 | if (dev->tagset.tags) |
1879 | blk_mq_free_tag_set(&dev->tagset); | |
1c63dc66 CH |
1880 | if (dev->ctrl.admin_q) |
1881 | blk_put_queue(dev->ctrl.admin_q); | |
5e82e952 KB |
1882 | kfree(dev->queues); |
1883 | kfree(dev->entry); | |
1884 | kfree(dev); | |
1885 | } | |
1886 | ||
fd634f41 | 1887 | static void nvme_reset_work(struct work_struct *work) |
f0b50732 | 1888 | { |
fd634f41 | 1889 | struct nvme_dev *dev = container_of(work, struct nvme_dev, reset_work); |
3cf519b5 | 1890 | int result; |
f0b50732 | 1891 | |
fd634f41 CH |
1892 | if (WARN_ON(test_bit(NVME_CTRL_RESETTING, &dev->flags))) |
1893 | goto out; | |
1894 | ||
1895 | /* | |
1896 | * If we're called to reset a live controller first shut it down before | |
1897 | * moving on. | |
1898 | */ | |
1899 | if (dev->bar) | |
1900 | nvme_dev_shutdown(dev); | |
1901 | ||
1902 | set_bit(NVME_CTRL_RESETTING, &dev->flags); | |
1903 | ||
f0b50732 KB |
1904 | result = nvme_dev_map(dev); |
1905 | if (result) | |
3cf519b5 | 1906 | goto out; |
f0b50732 KB |
1907 | |
1908 | result = nvme_configure_admin_queue(dev); | |
1909 | if (result) | |
1910 | goto unmap; | |
1911 | ||
a4aea562 | 1912 | nvme_init_queue(dev->queues[0], 0); |
0fb59cbc KB |
1913 | result = nvme_alloc_admin_tags(dev); |
1914 | if (result) | |
1915 | goto disable; | |
b9afca3e | 1916 | |
ce4541f4 CH |
1917 | result = nvme_init_identify(&dev->ctrl); |
1918 | if (result) | |
1919 | goto free_tags; | |
1920 | ||
f0b50732 | 1921 | result = nvme_setup_io_queues(dev); |
badc34d4 | 1922 | if (result) |
0fb59cbc | 1923 | goto free_tags; |
f0b50732 | 1924 | |
adf68f21 | 1925 | dev->ctrl.event_limit = NVME_NR_AEN_COMMANDS; |
3cf519b5 | 1926 | |
7385014c CH |
1927 | result = nvme_dev_list_add(dev); |
1928 | if (result) | |
1929 | goto remove; | |
1930 | ||
2659e57b CH |
1931 | /* |
1932 | * Keep the controller around but remove all namespaces if we don't have | |
1933 | * any working I/O queue. | |
1934 | */ | |
3cf519b5 CH |
1935 | if (dev->online_queues < 2) { |
1936 | dev_warn(dev->dev, "IO queues not created\n"); | |
5bae7f73 | 1937 | nvme_remove_namespaces(&dev->ctrl); |
3cf519b5 | 1938 | } else { |
25646264 | 1939 | nvme_start_queues(&dev->ctrl); |
3cf519b5 CH |
1940 | nvme_dev_add(dev); |
1941 | } | |
1942 | ||
fd634f41 | 1943 | clear_bit(NVME_CTRL_RESETTING, &dev->flags); |
3cf519b5 | 1944 | return; |
f0b50732 | 1945 | |
7385014c CH |
1946 | remove: |
1947 | nvme_dev_list_remove(dev); | |
0fb59cbc KB |
1948 | free_tags: |
1949 | nvme_dev_remove_admin(dev); | |
1c63dc66 CH |
1950 | blk_put_queue(dev->ctrl.admin_q); |
1951 | dev->ctrl.admin_q = NULL; | |
4af0e21c | 1952 | dev->queues[0]->tags = NULL; |
f0b50732 | 1953 | disable: |
a1a5ef99 | 1954 | nvme_disable_queue(dev, 0); |
f0b50732 KB |
1955 | unmap: |
1956 | nvme_dev_unmap(dev); | |
3cf519b5 | 1957 | out: |
5c8809e6 | 1958 | nvme_remove_dead_ctrl(dev); |
f0b50732 KB |
1959 | } |
1960 | ||
5c8809e6 | 1961 | static void nvme_remove_dead_ctrl_work(struct work_struct *work) |
9a6b9458 | 1962 | { |
5c8809e6 | 1963 | struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work); |
e75ec752 | 1964 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
9a6b9458 KB |
1965 | |
1966 | if (pci_get_drvdata(pdev)) | |
c81f4975 | 1967 | pci_stop_and_remove_bus_device_locked(pdev); |
1673f1f0 | 1968 | nvme_put_ctrl(&dev->ctrl); |
9a6b9458 KB |
1969 | } |
1970 | ||
5c8809e6 | 1971 | static void nvme_remove_dead_ctrl(struct nvme_dev *dev) |
de3eff2b | 1972 | { |
5c8809e6 | 1973 | dev_warn(dev->dev, "Removing after probe failure\n"); |
1673f1f0 | 1974 | kref_get(&dev->ctrl.kref); |
5c8809e6 | 1975 | if (!schedule_work(&dev->remove_work)) |
1673f1f0 | 1976 | nvme_put_ctrl(&dev->ctrl); |
de3eff2b KB |
1977 | } |
1978 | ||
4cc06521 KB |
1979 | static int nvme_reset(struct nvme_dev *dev) |
1980 | { | |
1c63dc66 | 1981 | if (!dev->ctrl.admin_q || blk_queue_dying(dev->ctrl.admin_q)) |
4cc06521 KB |
1982 | return -ENODEV; |
1983 | ||
846cc05f CH |
1984 | if (!queue_work(nvme_workq, &dev->reset_work)) |
1985 | return -EBUSY; | |
4cc06521 | 1986 | |
846cc05f | 1987 | flush_work(&dev->reset_work); |
846cc05f | 1988 | return 0; |
4cc06521 KB |
1989 | } |
1990 | ||
1c63dc66 CH |
1991 | static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val) |
1992 | { | |
1993 | *val = readl(to_nvme_dev(ctrl)->bar + off); | |
1994 | return 0; | |
1995 | } | |
1996 | ||
5fd4ce1b CH |
1997 | static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val) |
1998 | { | |
1999 | writel(val, to_nvme_dev(ctrl)->bar + off); | |
2000 | return 0; | |
2001 | } | |
2002 | ||
7fd8930f CH |
2003 | static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val) |
2004 | { | |
2005 | *val = readq(to_nvme_dev(ctrl)->bar + off); | |
2006 | return 0; | |
2007 | } | |
2008 | ||
5bae7f73 CH |
2009 | static bool nvme_pci_io_incapable(struct nvme_ctrl *ctrl) |
2010 | { | |
2011 | struct nvme_dev *dev = to_nvme_dev(ctrl); | |
2012 | ||
2013 | return !dev->bar || dev->online_queues < 2; | |
2014 | } | |
2015 | ||
f3ca80fc CH |
2016 | static int nvme_pci_reset_ctrl(struct nvme_ctrl *ctrl) |
2017 | { | |
2018 | return nvme_reset(to_nvme_dev(ctrl)); | |
2019 | } | |
2020 | ||
1c63dc66 CH |
2021 | static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = { |
2022 | .reg_read32 = nvme_pci_reg_read32, | |
5fd4ce1b | 2023 | .reg_write32 = nvme_pci_reg_write32, |
7fd8930f | 2024 | .reg_read64 = nvme_pci_reg_read64, |
5bae7f73 | 2025 | .io_incapable = nvme_pci_io_incapable, |
f3ca80fc | 2026 | .reset_ctrl = nvme_pci_reset_ctrl, |
1673f1f0 | 2027 | .free_ctrl = nvme_pci_free_ctrl, |
1c63dc66 CH |
2028 | }; |
2029 | ||
8d85fce7 | 2030 | static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) |
b60503ba | 2031 | { |
a4aea562 | 2032 | int node, result = -ENOMEM; |
b60503ba MW |
2033 | struct nvme_dev *dev; |
2034 | ||
a4aea562 MB |
2035 | node = dev_to_node(&pdev->dev); |
2036 | if (node == NUMA_NO_NODE) | |
2037 | set_dev_node(&pdev->dev, 0); | |
2038 | ||
2039 | dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); | |
b60503ba MW |
2040 | if (!dev) |
2041 | return -ENOMEM; | |
a4aea562 MB |
2042 | dev->entry = kzalloc_node(num_possible_cpus() * sizeof(*dev->entry), |
2043 | GFP_KERNEL, node); | |
b60503ba MW |
2044 | if (!dev->entry) |
2045 | goto free; | |
a4aea562 MB |
2046 | dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *), |
2047 | GFP_KERNEL, node); | |
b60503ba MW |
2048 | if (!dev->queues) |
2049 | goto free; | |
2050 | ||
e75ec752 | 2051 | dev->dev = get_device(&pdev->dev); |
9a6b9458 | 2052 | pci_set_drvdata(pdev, dev); |
1c63dc66 | 2053 | |
f3ca80fc CH |
2054 | INIT_LIST_HEAD(&dev->node); |
2055 | INIT_WORK(&dev->scan_work, nvme_dev_scan); | |
f3ca80fc | 2056 | INIT_WORK(&dev->reset_work, nvme_reset_work); |
5c8809e6 | 2057 | INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work); |
77bf25ea | 2058 | mutex_init(&dev->shutdown_lock); |
db3cbfff | 2059 | init_completion(&dev->ioq_wait); |
1c63dc66 | 2060 | |
f3ca80fc | 2061 | result = nvme_setup_prp_pools(dev); |
cd58ad7d | 2062 | if (result) |
a96d4f5c | 2063 | goto put_pci; |
b60503ba | 2064 | |
f3ca80fc CH |
2065 | result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops, |
2066 | id->driver_data); | |
091b6092 | 2067 | if (result) |
2e1d8448 | 2068 | goto release_pools; |
740216fc | 2069 | |
92f7a162 | 2070 | queue_work(nvme_workq, &dev->reset_work); |
b60503ba MW |
2071 | return 0; |
2072 | ||
0877cb0d | 2073 | release_pools: |
091b6092 | 2074 | nvme_release_prp_pools(dev); |
a96d4f5c | 2075 | put_pci: |
e75ec752 | 2076 | put_device(dev->dev); |
b60503ba MW |
2077 | free: |
2078 | kfree(dev->queues); | |
2079 | kfree(dev->entry); | |
2080 | kfree(dev); | |
2081 | return result; | |
2082 | } | |
2083 | ||
f0d54a54 KB |
2084 | static void nvme_reset_notify(struct pci_dev *pdev, bool prepare) |
2085 | { | |
a6739479 | 2086 | struct nvme_dev *dev = pci_get_drvdata(pdev); |
f0d54a54 | 2087 | |
a6739479 KB |
2088 | if (prepare) |
2089 | nvme_dev_shutdown(dev); | |
2090 | else | |
92f7a162 | 2091 | queue_work(nvme_workq, &dev->reset_work); |
f0d54a54 KB |
2092 | } |
2093 | ||
09ece142 KB |
2094 | static void nvme_shutdown(struct pci_dev *pdev) |
2095 | { | |
2096 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
2097 | nvme_dev_shutdown(dev); | |
2098 | } | |
2099 | ||
8d85fce7 | 2100 | static void nvme_remove(struct pci_dev *pdev) |
b60503ba MW |
2101 | { |
2102 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
9a6b9458 KB |
2103 | |
2104 | spin_lock(&dev_list_lock); | |
2105 | list_del_init(&dev->node); | |
2106 | spin_unlock(&dev_list_lock); | |
2107 | ||
2108 | pci_set_drvdata(pdev, NULL); | |
2109 | flush_work(&dev->reset_work); | |
a5768aa8 | 2110 | flush_work(&dev->scan_work); |
5bae7f73 | 2111 | nvme_remove_namespaces(&dev->ctrl); |
53029b04 | 2112 | nvme_uninit_ctrl(&dev->ctrl); |
3399a3f7 | 2113 | nvme_dev_shutdown(dev); |
a4aea562 | 2114 | nvme_dev_remove_admin(dev); |
a1a5ef99 | 2115 | nvme_free_queues(dev, 0); |
8ffaadf7 | 2116 | nvme_release_cmb(dev); |
9a6b9458 | 2117 | nvme_release_prp_pools(dev); |
1673f1f0 | 2118 | nvme_put_ctrl(&dev->ctrl); |
b60503ba MW |
2119 | } |
2120 | ||
671a6018 | 2121 | #ifdef CONFIG_PM_SLEEP |
cd638946 KB |
2122 | static int nvme_suspend(struct device *dev) |
2123 | { | |
2124 | struct pci_dev *pdev = to_pci_dev(dev); | |
2125 | struct nvme_dev *ndev = pci_get_drvdata(pdev); | |
2126 | ||
2127 | nvme_dev_shutdown(ndev); | |
2128 | return 0; | |
2129 | } | |
2130 | ||
2131 | static int nvme_resume(struct device *dev) | |
2132 | { | |
2133 | struct pci_dev *pdev = to_pci_dev(dev); | |
2134 | struct nvme_dev *ndev = pci_get_drvdata(pdev); | |
cd638946 | 2135 | |
92f7a162 | 2136 | queue_work(nvme_workq, &ndev->reset_work); |
9a6b9458 | 2137 | return 0; |
cd638946 | 2138 | } |
671a6018 | 2139 | #endif |
cd638946 KB |
2140 | |
2141 | static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume); | |
b60503ba | 2142 | |
a0a3408e KB |
2143 | static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev, |
2144 | pci_channel_state_t state) | |
2145 | { | |
2146 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
2147 | ||
2148 | /* | |
2149 | * A frozen channel requires a reset. When detected, this method will | |
2150 | * shutdown the controller to quiesce. The controller will be restarted | |
2151 | * after the slot reset through driver's slot_reset callback. | |
2152 | */ | |
2153 | dev_warn(&pdev->dev, "error detected: state:%d\n", state); | |
2154 | switch (state) { | |
2155 | case pci_channel_io_normal: | |
2156 | return PCI_ERS_RESULT_CAN_RECOVER; | |
2157 | case pci_channel_io_frozen: | |
2158 | nvme_dev_shutdown(dev); | |
2159 | return PCI_ERS_RESULT_NEED_RESET; | |
2160 | case pci_channel_io_perm_failure: | |
2161 | return PCI_ERS_RESULT_DISCONNECT; | |
2162 | } | |
2163 | return PCI_ERS_RESULT_NEED_RESET; | |
2164 | } | |
2165 | ||
2166 | static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev) | |
2167 | { | |
2168 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
2169 | ||
2170 | dev_info(&pdev->dev, "restart after slot reset\n"); | |
2171 | pci_restore_state(pdev); | |
2172 | queue_work(nvme_workq, &dev->reset_work); | |
2173 | return PCI_ERS_RESULT_RECOVERED; | |
2174 | } | |
2175 | ||
2176 | static void nvme_error_resume(struct pci_dev *pdev) | |
2177 | { | |
2178 | pci_cleanup_aer_uncorrect_error_status(pdev); | |
2179 | } | |
2180 | ||
1d352035 | 2181 | static const struct pci_error_handlers nvme_err_handler = { |
b60503ba | 2182 | .error_detected = nvme_error_detected, |
b60503ba MW |
2183 | .slot_reset = nvme_slot_reset, |
2184 | .resume = nvme_error_resume, | |
f0d54a54 | 2185 | .reset_notify = nvme_reset_notify, |
b60503ba MW |
2186 | }; |
2187 | ||
2188 | /* Move to pci_ids.h later */ | |
2189 | #define PCI_CLASS_STORAGE_EXPRESS 0x010802 | |
2190 | ||
6eb0d698 | 2191 | static const struct pci_device_id nvme_id_table[] = { |
106198ed CH |
2192 | { PCI_VDEVICE(INTEL, 0x0953), |
2193 | .driver_data = NVME_QUIRK_STRIPE_SIZE, }, | |
540c801c KB |
2194 | { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */ |
2195 | .driver_data = NVME_QUIRK_IDENTIFY_CNS, }, | |
b60503ba | 2196 | { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, |
c74dc780 | 2197 | { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) }, |
b60503ba MW |
2198 | { 0, } |
2199 | }; | |
2200 | MODULE_DEVICE_TABLE(pci, nvme_id_table); | |
2201 | ||
2202 | static struct pci_driver nvme_driver = { | |
2203 | .name = "nvme", | |
2204 | .id_table = nvme_id_table, | |
2205 | .probe = nvme_probe, | |
8d85fce7 | 2206 | .remove = nvme_remove, |
09ece142 | 2207 | .shutdown = nvme_shutdown, |
cd638946 KB |
2208 | .driver = { |
2209 | .pm = &nvme_dev_pm_ops, | |
2210 | }, | |
b60503ba MW |
2211 | .err_handler = &nvme_err_handler, |
2212 | }; | |
2213 | ||
2214 | static int __init nvme_init(void) | |
2215 | { | |
0ac13140 | 2216 | int result; |
1fa6aead | 2217 | |
b9afca3e | 2218 | init_waitqueue_head(&nvme_kthread_wait); |
b60503ba | 2219 | |
92f7a162 | 2220 | nvme_workq = alloc_workqueue("nvme", WQ_UNBOUND | WQ_MEM_RECLAIM, 0); |
9a6b9458 | 2221 | if (!nvme_workq) |
b9afca3e | 2222 | return -ENOMEM; |
9a6b9458 | 2223 | |
5bae7f73 | 2224 | result = nvme_core_init(); |
5c42ea16 | 2225 | if (result < 0) |
9a6b9458 | 2226 | goto kill_workq; |
b60503ba | 2227 | |
f3db22fe KB |
2228 | result = pci_register_driver(&nvme_driver); |
2229 | if (result) | |
f3ca80fc | 2230 | goto core_exit; |
1fa6aead | 2231 | return 0; |
b60503ba | 2232 | |
f3ca80fc | 2233 | core_exit: |
5bae7f73 | 2234 | nvme_core_exit(); |
9a6b9458 KB |
2235 | kill_workq: |
2236 | destroy_workqueue(nvme_workq); | |
b60503ba MW |
2237 | return result; |
2238 | } | |
2239 | ||
2240 | static void __exit nvme_exit(void) | |
2241 | { | |
2242 | pci_unregister_driver(&nvme_driver); | |
5bae7f73 | 2243 | nvme_core_exit(); |
9a6b9458 | 2244 | destroy_workqueue(nvme_workq); |
b9afca3e | 2245 | BUG_ON(nvme_thread && !IS_ERR(nvme_thread)); |
21bd78bc | 2246 | _nvme_check_size(); |
b60503ba MW |
2247 | } |
2248 | ||
2249 | MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); | |
2250 | MODULE_LICENSE("GPL"); | |
c78b4713 | 2251 | MODULE_VERSION("1.0"); |
b60503ba MW |
2252 | module_init(nvme_init); |
2253 | module_exit(nvme_exit); |