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nvme-core: use u16 type for ctrl->sqsize
[linux-2.6-block.git] / drivers / nvme / host / pci.c
CommitLineData
5f37396d 1// SPDX-License-Identifier: GPL-2.0
b60503ba
MW		 2/*
3 * NVM Express device driver
6eb0d698 4 * Copyright (c) 2011-2014, Intel Corporation.
b60503ba
MW		 5 */
6
a0a3408e 7#include <linux/aer.h>
18119775 8#include <linux/async.h>
b60503ba 9#include <linux/blkdev.h>
a4aea562 10#include <linux/blk-mq.h>
dca51e78 11#include <linux/blk-mq-pci.h>
ff5350a8 12#include <linux/dmi.h>
b60503ba
MW		 13#include <linux/init.h>
14#include <linux/interrupt.h>
15#include <linux/io.h>
b60503ba
MW		 16#include <linux/mm.h>
17#include <linux/module.h>
77bf25ea 18#include <linux/mutex.h>
d0877473 19#include <linux/once.h>
b60503ba 20#include <linux/pci.h>
d916b1be 21#include <linux/suspend.h>
e1e5e564 22#include <linux/t10-pi.h>
b60503ba 23#include <linux/types.h>
2f8e2c87 24#include <linux/io-64-nonatomic-lo-hi.h>
a98e58e5 25#include <linux/sed-opal.h>
0f238ff5 26#include <linux/pci-p2pdma.h>
797a796a 27
604c01d5 28#include "trace.h"
f11bb3e2
CH		 29#include "nvme.h"
30
c1e0cc7e 31#define SQ_SIZE(q) ((q)->q_depth << (q)->sqes)
8a1d09a6 32#define CQ_SIZE(q) ((q)->q_depth * sizeof(struct nvme_completion))
c965809c 33
a7a7cbe3 34#define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc))
9d43cf64 35
943e942e
JA		 36/*
37 * These can be higher, but we need to ensure that any command doesn't
38 * require an sg allocation that needs more than a page of data.
39 */
40#define NVME_MAX_KB_SZ 4096
41#define NVME_MAX_SEGS 127
42
58ffacb5
MW		 43static int use_threaded_interrupts;
44module_param(use_threaded_interrupts, int, 0);
45
8ffaadf7 46static bool use_cmb_sqes = true;
69f4eb9f 47module_param(use_cmb_sqes, bool, 0444);
8ffaadf7
JD		 48MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
49
87ad72a5
CH		 50static unsigned int max_host_mem_size_mb = 128;
51module_param(max_host_mem_size_mb, uint, 0444);
52MODULE_PARM_DESC(max_host_mem_size_mb,
53 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
1fa6aead 54
a7a7cbe3
CK		 55static unsigned int sgl_threshold = SZ_32K;
56module_param(sgl_threshold, uint, 0644);
57MODULE_PARM_DESC(sgl_threshold,
58 "Use SGLs when average request segment size is larger or equal to "
59 "this size. Use 0 to disable SGLs.");
60
b27c1e68 61static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
62static const struct kernel_param_ops io_queue_depth_ops = {
63 .set = io_queue_depth_set,
64 .get = param_get_int,
65};
66
67static int io_queue_depth = 1024;
68module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
69MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2");
70
9c9e76d5
WZ		 71static int io_queue_count_set(const char *val, const struct kernel_param *kp)
72{
73 unsigned int n;
74 int ret;
75
76 ret = kstrtouint(val, 10, &n);
77 if (ret != 0 || n > num_possible_cpus())
78 return -EINVAL;
79 return param_set_uint(val, kp);
80}
81
82static const struct kernel_param_ops io_queue_count_ops = {
83 .set = io_queue_count_set,
84 .get = param_get_uint,
85};
86
3f68baf7 87static unsigned int write_queues;
9c9e76d5 88module_param_cb(write_queues, &io_queue_count_ops, &write_queues, 0644);
3b6592f7
JA		 89MODULE_PARM_DESC(write_queues,
90 "Number of queues to use for writes. If not set, reads and writes "
91 "will share a queue set.");
92
3f68baf7 93static unsigned int poll_queues;
9c9e76d5 94module_param_cb(poll_queues, &io_queue_count_ops, &poll_queues, 0644);
4b04cc6a
JA		 95MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO.");
96
1c63dc66
CH		 97struct nvme_dev;
98struct nvme_queue;
b3fffdef 99
a5cdb68c 100static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
8fae268b 101static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode);
d4b4ff8e 102
1c63dc66
CH		 103/*
104 * Represents an NVM Express device. Each nvme_dev is a PCI function.
105 */
106struct nvme_dev {
147b27e4 107 struct nvme_queue *queues;
1c63dc66
CH		 108 struct blk_mq_tag_set tagset;
109 struct blk_mq_tag_set admin_tagset;
110 u32 __iomem *dbs;
111 struct device *dev;
112 struct dma_pool *prp_page_pool;
113 struct dma_pool *prp_small_pool;
1c63dc66
CH		 114 unsigned online_queues;
115 unsigned max_qid;
e20ba6e1 116 unsigned io_queues[HCTX_MAX_TYPES];
22b55601 117 unsigned int num_vecs;
1c63dc66 118 int q_depth;
c1e0cc7e 119 int io_sqes;
1c63dc66 120 u32 db_stride;
1c63dc66 121 void __iomem *bar;
97f6ef64 122 unsigned long bar_mapped_size;
5c8809e6 123 struct work_struct remove_work;
77bf25ea 124 struct mutex shutdown_lock;
1c63dc66 125 bool subsystem;
1c63dc66 126 u64 cmb_size;
0f238ff5 127 bool cmb_use_sqes;
1c63dc66 128 u32 cmbsz;
202021c1 129 u32 cmbloc;
1c63dc66 130 struct nvme_ctrl ctrl;
d916b1be 131 u32 last_ps;
87ad72a5 132
943e942e
JA		 133 mempool_t *iod_mempool;
134
87ad72a5 135 /* shadow doorbell buffer support: */
f9f38e33
HK		 136 u32 *dbbuf_dbs;
137 dma_addr_t dbbuf_dbs_dma_addr;
138 u32 *dbbuf_eis;
139 dma_addr_t dbbuf_eis_dma_addr;
87ad72a5
CH		 140
141 /* host memory buffer support: */
142 u64 host_mem_size;
143 u32 nr_host_mem_descs;
4033f35d 144 dma_addr_t host_mem_descs_dma;
87ad72a5
CH		 145 struct nvme_host_mem_buf_desc *host_mem_descs;
146 void **host_mem_desc_bufs;
2a5bcfdd
WZ		 147 unsigned int nr_allocated_queues;
148 unsigned int nr_write_queues;
149 unsigned int nr_poll_queues;
4d115420 150};
1fa6aead 151
b27c1e68 152static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
153{
154 int n = 0, ret;
155
156 ret = kstrtoint(val, 10, &n);
157 if (ret != 0 || n < 2)
158 return -EINVAL;
159
160 return param_set_int(val, kp);
161}
162
f9f38e33
HK		 163static inline unsigned int sq_idx(unsigned int qid, u32 stride)
164{
165 return qid * 2 * stride;
166}
167
168static inline unsigned int cq_idx(unsigned int qid, u32 stride)
169{
170 return (qid * 2 + 1) * stride;
171}
172
1c63dc66
CH		 173static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
174{
175 return container_of(ctrl, struct nvme_dev, ctrl);
176}
177
b60503ba
MW		 178/*
179 * An NVM Express queue. Each device has at least two (one for admin
180 * commands and one for I/O commands).
181 */
182struct nvme_queue {
091b6092 183 struct nvme_dev *dev;
1ab0cd69 184 spinlock_t sq_lock;
c1e0cc7e 185 void *sq_cmds;
3a7afd8e
CH		 186 /* only used for poll queues: */
187 spinlock_t cq_poll_lock ____cacheline_aligned_in_smp;
74943d45 188 struct nvme_completion *cqes;
b60503ba
MW		 189 dma_addr_t sq_dma_addr;
190 dma_addr_t cq_dma_addr;
b60503ba
MW		 191 u32 __iomem *q_db;
192 u16 q_depth;
7c349dde 193 u16 cq_vector;
b60503ba
MW		 194 u16 sq_tail;
195 u16 cq_head;
c30341dc 196 u16 qid;
e9539f47 197 u8 cq_phase;
c1e0cc7e 198 u8 sqes;
4e224106
CH		 199 unsigned long flags;
200#define NVMEQ_ENABLED 0
63223078 201#define NVMEQ_SQ_CMB 1
d1ed6aa1 202#define NVMEQ_DELETE_ERROR 2
7c349dde 203#define NVMEQ_POLLED 3
f9f38e33
HK		 204 u32 *dbbuf_sq_db;
205 u32 *dbbuf_cq_db;
206 u32 *dbbuf_sq_ei;
207 u32 *dbbuf_cq_ei;
d1ed6aa1 208 struct completion delete_done;
b60503ba
MW		 209};
210
71bd150c 211/*
9b048119
CH		 212 * The nvme_iod describes the data in an I/O.
213 *
214 * The sg pointer contains the list of PRP/SGL chunk allocations in addition
215 * to the actual struct scatterlist.
71bd150c
CH		 216 */
217struct nvme_iod {
d49187e9 218 struct nvme_request req;
f4800d6d 219 struct nvme_queue *nvmeq;
a7a7cbe3 220 bool use_sgl;
f4800d6d 221 int aborted;
71bd150c 222 int npages; /* In the PRP list. 0 means small pool in use */
71bd150c 223 int nents; /* Used in scatterlist */
71bd150c 224 dma_addr_t first_dma;
dff824b2 225 unsigned int dma_len; /* length of single DMA segment mapping */
783b94bd 226 dma_addr_t meta_dma;
f4800d6d 227 struct scatterlist *sg;
b60503ba
MW		 228};
229
2a5bcfdd 230static inline unsigned int nvme_dbbuf_size(struct nvme_dev *dev)
3b6592f7 231{
2a5bcfdd 232 return dev->nr_allocated_queues * 8 * dev->db_stride;
f9f38e33
HK		 233}
234
235static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
236{
2a5bcfdd 237 unsigned int mem_size = nvme_dbbuf_size(dev);
f9f38e33
HK		 238
239 if (dev->dbbuf_dbs)
240 return 0;
241
242 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
243 &dev->dbbuf_dbs_dma_addr,
244 GFP_KERNEL);
245 if (!dev->dbbuf_dbs)
246 return -ENOMEM;
247 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
248 &dev->dbbuf_eis_dma_addr,
249 GFP_KERNEL);
250 if (!dev->dbbuf_eis) {
251 dma_free_coherent(dev->dev, mem_size,
252 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
253 dev->dbbuf_dbs = NULL;
254 return -ENOMEM;
255 }
256
257 return 0;
258}
259
260static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
261{
2a5bcfdd 262 unsigned int mem_size = nvme_dbbuf_size(dev);
f9f38e33
HK		 263
264 if (dev->dbbuf_dbs) {
265 dma_free_coherent(dev->dev, mem_size,
266 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
267 dev->dbbuf_dbs = NULL;
268 }
269 if (dev->dbbuf_eis) {
270 dma_free_coherent(dev->dev, mem_size,
271 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
272 dev->dbbuf_eis = NULL;
273 }
274}
275
276static void nvme_dbbuf_init(struct nvme_dev *dev,
277 struct nvme_queue *nvmeq, int qid)
278{
279 if (!dev->dbbuf_dbs || !qid)
280 return;
281
282 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
283 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
284 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
285 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
286}
287
288static void nvme_dbbuf_set(struct nvme_dev *dev)
289{
290 struct nvme_command c;
291
292 if (!dev->dbbuf_dbs)
293 return;
294
295 memset(&c, 0, sizeof(c));
296 c.dbbuf.opcode = nvme_admin_dbbuf;
297 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
298 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
299
300 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
9bdcfb10 301 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
f9f38e33
HK		 302 /* Free memory and continue on */
303 nvme_dbbuf_dma_free(dev);
304 }
305}
306
307static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
308{
309 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
310}
311
312/* Update dbbuf and return true if an MMIO is required */
313static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
314 volatile u32 *dbbuf_ei)
315{
316 if (dbbuf_db) {
317 u16 old_value;
318
319 /*
320 * Ensure that the queue is written before updating
321 * the doorbell in memory
322 */
323 wmb();
324
325 old_value = *dbbuf_db;
326 *dbbuf_db = value;
327
f1ed3df2
MW		 328 /*
329 * Ensure that the doorbell is updated before reading the event
330 * index from memory. The controller needs to provide similar
331 * ordering to ensure the envent index is updated before reading
332 * the doorbell.
333 */
334 mb();
335
f9f38e33
HK		 336 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value))
337 return false;
338 }
339
340 return true;
b60503ba
MW		 341}
342
ac3dd5bd
JA		 343/*
344 * Will slightly overestimate the number of pages needed. This is OK
345 * as it only leads to a small amount of wasted memory for the lifetime of
346 * the I/O.
347 */
348static int nvme_npages(unsigned size, struct nvme_dev *dev)
349{
5fd4ce1b
CH		 350 unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size,
351 dev->ctrl.page_size);
ac3dd5bd
JA		 352 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
353}
354
a7a7cbe3
CK		 355/*
356 * Calculates the number of pages needed for the SGL segments. For example a 4k
357 * page can accommodate 256 SGL descriptors.
358 */
359static int nvme_pci_npages_sgl(unsigned int num_seg)
ac3dd5bd 360{
a7a7cbe3 361 return DIV_ROUND_UP(num_seg * sizeof(struct nvme_sgl_desc), PAGE_SIZE);
f4800d6d 362}
ac3dd5bd 363
a7a7cbe3
CK		 364static unsigned int nvme_pci_iod_alloc_size(struct nvme_dev *dev,
365 unsigned int size, unsigned int nseg, bool use_sgl)
f4800d6d 366{
a7a7cbe3
CK		 367 size_t alloc_size;
368
369 if (use_sgl)
370 alloc_size = sizeof(__le64 *) * nvme_pci_npages_sgl(nseg);
371 else
372 alloc_size = sizeof(__le64 *) * nvme_npages(size, dev);
373
374 return alloc_size + sizeof(struct scatterlist) * nseg;
f4800d6d 375}
ac3dd5bd 376
a4aea562
MB		 377static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
378 unsigned int hctx_idx)
e85248e5 379{
a4aea562 380 struct nvme_dev *dev = data;
147b27e4 381 struct nvme_queue *nvmeq = &dev->queues[0];
a4aea562 382
42483228
KB		 383 WARN_ON(hctx_idx != 0);
384 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
42483228 385
a4aea562
MB		 386 hctx->driver_data = nvmeq;
387 return 0;
e85248e5
MW		 388}
389
a4aea562
MB		 390static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
391 unsigned int hctx_idx)
b60503ba 392{
a4aea562 393 struct nvme_dev *dev = data;
147b27e4 394 struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
a4aea562 395
42483228 396 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
a4aea562
MB		 397 hctx->driver_data = nvmeq;
398 return 0;
b60503ba
MW		 399}
400
d6296d39
CH		 401static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req,
402 unsigned int hctx_idx, unsigned int numa_node)
b60503ba 403{
d6296d39 404 struct nvme_dev *dev = set->driver_data;
f4800d6d 405 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
0350815a 406 int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0;
147b27e4 407 struct nvme_queue *nvmeq = &dev->queues[queue_idx];
a4aea562
MB		 408
409 BUG_ON(!nvmeq);
f4800d6d 410 iod->nvmeq = nvmeq;
59e29ce6
SG		 411
412 nvme_req(req)->ctrl = &dev->ctrl;
a4aea562
MB		 413 return 0;
414}
415
3b6592f7
JA		 416static int queue_irq_offset(struct nvme_dev *dev)
417{
418 /* if we have more than 1 vec, admin queue offsets us by 1 */
419 if (dev->num_vecs > 1)
420 return 1;
421
422 return 0;
423}
424
dca51e78
CH		 425static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
426{
427 struct nvme_dev *dev = set->driver_data;
3b6592f7
JA		 428 int i, qoff, offset;
429
430 offset = queue_irq_offset(dev);
431 for (i = 0, qoff = 0; i < set->nr_maps; i++) {
432 struct blk_mq_queue_map *map = &set->map[i];
433
434 map->nr_queues = dev->io_queues[i];
435 if (!map->nr_queues) {
e20ba6e1 436 BUG_ON(i == HCTX_TYPE_DEFAULT);
7e849dd9 437 continue;
3b6592f7
JA		 438 }
439
4b04cc6a
JA		 440 /*
441 * The poll queue(s) doesn't have an IRQ (and hence IRQ
442 * affinity), so use the regular blk-mq cpu mapping
443 */
3b6592f7 444 map->queue_offset = qoff;
cb9e0e50 445 if (i != HCTX_TYPE_POLL && offset)
4b04cc6a
JA		 446 blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset);
447 else
448 blk_mq_map_queues(map);
3b6592f7
JA		 449 qoff += map->nr_queues;
450 offset += map->nr_queues;
451 }
452
453 return 0;
dca51e78
CH		 454}
455
54b2fcee 456static inline void nvme_write_sq_db(struct nvme_queue *nvmeq)
04f3eafd 457{
04f3eafd
JA		 458 if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail,
459 nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei))
460 writel(nvmeq->sq_tail, nvmeq->q_db);
04f3eafd
JA		 461}
462
b60503ba 463/**
90ea5ca4 464 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
b60503ba
MW		 465 * @nvmeq: The queue to use
466 * @cmd: The command to send
04f3eafd 467 * @write_sq: whether to write to the SQ doorbell
b60503ba 468 */
04f3eafd
JA		 469static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd,
470 bool write_sq)
b60503ba 471{
90ea5ca4 472 spin_lock(&nvmeq->sq_lock);
c1e0cc7e
BH		 473 memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes),
474 cmd, sizeof(*cmd));
90ea5ca4
CH		 475 if (++nvmeq->sq_tail == nvmeq->q_depth)
476 nvmeq->sq_tail = 0;
54b2fcee
KB		 477 if (write_sq)
478 nvme_write_sq_db(nvmeq);
04f3eafd
JA		 479 spin_unlock(&nvmeq->sq_lock);
480}
481
482static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx)
483{
484 struct nvme_queue *nvmeq = hctx->driver_data;
485
486 spin_lock(&nvmeq->sq_lock);
54b2fcee 487 nvme_write_sq_db(nvmeq);
90ea5ca4 488 spin_unlock(&nvmeq->sq_lock);
b60503ba
MW		 489}
490
a7a7cbe3 491static void **nvme_pci_iod_list(struct request *req)
b60503ba 492{
f4800d6d 493 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3 494 return (void **)(iod->sg + blk_rq_nr_phys_segments(req));
b60503ba
MW		 495}
496
955b1b5a
MI		 497static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req)
498{
499 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
20469a37 500 int nseg = blk_rq_nr_phys_segments(req);
955b1b5a
MI		 501 unsigned int avg_seg_size;
502
20469a37
KB		 503 if (nseg == 0)
504 return false;
505
506 avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
955b1b5a
MI		 507
508 if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1))))
509 return false;
510 if (!iod->nvmeq->qid)
511 return false;
512 if (!sgl_threshold || avg_seg_size < sgl_threshold)
513 return false;
514 return true;
515}
516
7fe07d14 517static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
b60503ba 518{
f4800d6d 519 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3
CK		 520 const int last_prp = dev->ctrl.page_size / sizeof(__le64) - 1;
521 dma_addr_t dma_addr = iod->first_dma, next_dma_addr;
eca18b23 522 int i;
eca18b23 523
dff824b2 524 if (iod->dma_len) {
f2fa006f
IR		 525 dma_unmap_page(dev->dev, dma_addr, iod->dma_len,
526 rq_dma_dir(req));
dff824b2 527 return;
7fe07d14
CH		 528 }
529
dff824b2
CH		 530 WARN_ON_ONCE(!iod->nents);
531
7f73eac3
LG		 532 if (is_pci_p2pdma_page(sg_page(iod->sg)))
533 pci_p2pdma_unmap_sg(dev->dev, iod->sg, iod->nents,
534 rq_dma_dir(req));
535 else
dff824b2
CH		 536 dma_unmap_sg(dev->dev, iod->sg, iod->nents, rq_dma_dir(req));
537
538
eca18b23 539 if (iod->npages == 0)
a7a7cbe3
CK		 540 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0],
541 dma_addr);
542
eca18b23 543 for (i = 0; i < iod->npages; i++) {
a7a7cbe3
CK		 544 void *addr = nvme_pci_iod_list(req)[i];
545
546 if (iod->use_sgl) {
547 struct nvme_sgl_desc *sg_list = addr;
548
549 next_dma_addr =
550 le64_to_cpu((sg_list[SGES_PER_PAGE - 1]).addr);
551 } else {
552 __le64 *prp_list = addr;
553
554 next_dma_addr = le64_to_cpu(prp_list[last_prp]);
555 }
556
557 dma_pool_free(dev->prp_page_pool, addr, dma_addr);
558 dma_addr = next_dma_addr;
eca18b23 559 }
ac3dd5bd 560
d43f1ccf 561 mempool_free(iod->sg, dev->iod_mempool);
b4ff9c8d
KB		 562}
563
d0877473
KB		 564static void nvme_print_sgl(struct scatterlist *sgl, int nents)
565{
566 int i;
567 struct scatterlist *sg;
568
569 for_each_sg(sgl, sg, nents, i) {
570 dma_addr_t phys = sg_phys(sg);
571 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
572 "dma_address:%pad dma_length:%d\n",
573 i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
574 sg_dma_len(sg));
575 }
576}
577
a7a7cbe3
CK		 578static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
579 struct request *req, struct nvme_rw_command *cmnd)
ff22b54f 580{
f4800d6d 581 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
99802a7a 582 struct dma_pool *pool;
b131c61d 583 int length = blk_rq_payload_bytes(req);
eca18b23 584 struct scatterlist *sg = iod->sg;
ff22b54f
MW		 585 int dma_len = sg_dma_len(sg);
586 u64 dma_addr = sg_dma_address(sg);
5fd4ce1b 587 u32 page_size = dev->ctrl.page_size;
f137e0f1 588 int offset = dma_addr & (page_size - 1);
e025344c 589 __le64 *prp_list;
a7a7cbe3 590 void **list = nvme_pci_iod_list(req);
e025344c 591 dma_addr_t prp_dma;
eca18b23 592 int nprps, i;
ff22b54f 593
1d090624 594 length -= (page_size - offset);
5228b328
JS		 595 if (length <= 0) {
596 iod->first_dma = 0;
a7a7cbe3 597 goto done;
5228b328 598 }
ff22b54f 599
1d090624 600 dma_len -= (page_size - offset);
ff22b54f 601 if (dma_len) {
1d090624 602 dma_addr += (page_size - offset);
ff22b54f
MW		 603 } else {
604 sg = sg_next(sg);
605 dma_addr = sg_dma_address(sg);
606 dma_len = sg_dma_len(sg);
607 }
608
1d090624 609 if (length <= page_size) {
edd10d33 610 iod->first_dma = dma_addr;
a7a7cbe3 611 goto done;
e025344c
SMM		 612 }
613
1d090624 614 nprps = DIV_ROUND_UP(length, page_size);
99802a7a
MW		 615 if (nprps <= (256 / 8)) {
616 pool = dev->prp_small_pool;
eca18b23 617 iod->npages = 0;
99802a7a
MW		 618 } else {
619 pool = dev->prp_page_pool;
eca18b23 620 iod->npages = 1;
99802a7a
MW		 621 }
622
69d2b571 623 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
b77954cb 624 if (!prp_list) {
edd10d33 625 iod->first_dma = dma_addr;
eca18b23 626 iod->npages = -1;
86eea289 627 return BLK_STS_RESOURCE;
b77954cb 628 }
eca18b23
MW		 629 list[0] = prp_list;
630 iod->first_dma = prp_dma;
e025344c
SMM		 631 i = 0;
632 for (;;) {
1d090624 633 if (i == page_size >> 3) {
e025344c 634 __le64 *old_prp_list = prp_list;
69d2b571 635 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
eca18b23 636 if (!prp_list)
86eea289 637 return BLK_STS_RESOURCE;
eca18b23 638 list[iod->npages++] = prp_list;
7523d834
MW		 639 prp_list[0] = old_prp_list[i - 1];
640 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
641 i = 1;
e025344c
SMM		 642 }
643 prp_list[i++] = cpu_to_le64(dma_addr);
1d090624
KB		 644 dma_len -= page_size;
645 dma_addr += page_size;
646 length -= page_size;
e025344c
SMM		 647 if (length <= 0)
648 break;
649 if (dma_len > 0)
650 continue;
86eea289
KB		 651 if (unlikely(dma_len < 0))
652 goto bad_sgl;
e025344c
SMM		 653 sg = sg_next(sg);
654 dma_addr = sg_dma_address(sg);
655 dma_len = sg_dma_len(sg);
ff22b54f
MW		 656 }
657
a7a7cbe3
CK		 658done:
659 cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
660 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
661
86eea289
KB		 662 return BLK_STS_OK;
663
664 bad_sgl:
d0877473
KB		 665 WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents),
666 "Invalid SGL for payload:%d nents:%d\n",
667 blk_rq_payload_bytes(req), iod->nents);
86eea289 668 return BLK_STS_IOERR;
ff22b54f
MW		 669}
670
a7a7cbe3
CK		 671static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
672 struct scatterlist *sg)
673{
674 sge->addr = cpu_to_le64(sg_dma_address(sg));
675 sge->length = cpu_to_le32(sg_dma_len(sg));
676 sge->type = NVME_SGL_FMT_DATA_DESC << 4;
677}
678
679static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
680 dma_addr_t dma_addr, int entries)
681{
682 sge->addr = cpu_to_le64(dma_addr);
683 if (entries < SGES_PER_PAGE) {
684 sge->length = cpu_to_le32(entries * sizeof(*sge));
685 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
686 } else {
687 sge->length = cpu_to_le32(PAGE_SIZE);
688 sge->type = NVME_SGL_FMT_SEG_DESC << 4;
689 }
690}
691
692static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
b0f2853b 693 struct request *req, struct nvme_rw_command *cmd, int entries)
a7a7cbe3
CK		 694{
695 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3
CK		 696 struct dma_pool *pool;
697 struct nvme_sgl_desc *sg_list;
698 struct scatterlist *sg = iod->sg;
a7a7cbe3 699 dma_addr_t sgl_dma;
b0f2853b 700 int i = 0;
a7a7cbe3 701
a7a7cbe3
CK		 702 /* setting the transfer type as SGL */
703 cmd->flags = NVME_CMD_SGL_METABUF;
704
b0f2853b 705 if (entries == 1) {
a7a7cbe3
CK		 706 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
707 return BLK_STS_OK;
708 }
709
710 if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
711 pool = dev->prp_small_pool;
712 iod->npages = 0;
713 } else {
714 pool = dev->prp_page_pool;
715 iod->npages = 1;
716 }
717
718 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
719 if (!sg_list) {
720 iod->npages = -1;
721 return BLK_STS_RESOURCE;
722 }
723
724 nvme_pci_iod_list(req)[0] = sg_list;
725 iod->first_dma = sgl_dma;
726
727 nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
728
729 do {
730 if (i == SGES_PER_PAGE) {
731 struct nvme_sgl_desc *old_sg_desc = sg_list;
732 struct nvme_sgl_desc *link = &old_sg_desc[i - 1];
733
734 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
735 if (!sg_list)
736 return BLK_STS_RESOURCE;
737
738 i = 0;
739 nvme_pci_iod_list(req)[iod->npages++] = sg_list;
740 sg_list[i++] = *link;
741 nvme_pci_sgl_set_seg(link, sgl_dma, entries);
742 }
743
744 nvme_pci_sgl_set_data(&sg_list[i++], sg);
a7a7cbe3 745 sg = sg_next(sg);
b0f2853b 746 } while (--entries > 0);
a7a7cbe3 747
a7a7cbe3
CK		 748 return BLK_STS_OK;
749}
750
dff824b2
CH		 751static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev,
752 struct request *req, struct nvme_rw_command *cmnd,
753 struct bio_vec *bv)
754{
755 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a4f40484
KH		 756 unsigned int offset = bv->bv_offset & (dev->ctrl.page_size - 1);
757 unsigned int first_prp_len = dev->ctrl.page_size - offset;
dff824b2
CH		 758
759 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
760 if (dma_mapping_error(dev->dev, iod->first_dma))
761 return BLK_STS_RESOURCE;
762 iod->dma_len = bv->bv_len;
763
764 cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma);
765 if (bv->bv_len > first_prp_len)
766 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len);
767 return 0;
768}
769
29791057
CH		 770static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev,
771 struct request *req, struct nvme_rw_command *cmnd,
772 struct bio_vec *bv)
773{
774 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
775
776 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
777 if (dma_mapping_error(dev->dev, iod->first_dma))
778 return BLK_STS_RESOURCE;
779 iod->dma_len = bv->bv_len;
780
049bf372 781 cmnd->flags = NVME_CMD_SGL_METABUF;
29791057
CH		 782 cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma);
783 cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len);
784 cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4;
785 return 0;
786}
787
fc17b653 788static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
b131c61d 789 struct nvme_command *cmnd)
d29ec824 790{
f4800d6d 791 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
70479b71 792 blk_status_t ret = BLK_STS_RESOURCE;
b0f2853b 793 int nr_mapped;
d29ec824 794
dff824b2
CH		 795 if (blk_rq_nr_phys_segments(req) == 1) {
796 struct bio_vec bv = req_bvec(req);
797
798 if (!is_pci_p2pdma_page(bv.bv_page)) {
799 if (bv.bv_offset + bv.bv_len <= dev->ctrl.page_size * 2)
800 return nvme_setup_prp_simple(dev, req,
801 &cmnd->rw, &bv);
29791057
CH		 802
803 if (iod->nvmeq->qid &&
804 dev->ctrl.sgls & ((1 << 0) | (1 << 1)))
805 return nvme_setup_sgl_simple(dev, req,
806 &cmnd->rw, &bv);
dff824b2
CH		 807 }
808 }
809
810 iod->dma_len = 0;
d43f1ccf
CH		 811 iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC);
812 if (!iod->sg)
813 return BLK_STS_RESOURCE;
f9d03f96 814 sg_init_table(iod->sg, blk_rq_nr_phys_segments(req));
70479b71 815 iod->nents = blk_rq_map_sg(req->q, req, iod->sg);
ba1ca37e
CH		 816 if (!iod->nents)
817 goto out;
d29ec824 818
e0596ab2 819 if (is_pci_p2pdma_page(sg_page(iod->sg)))
2b9f4bb2
LG		 820 nr_mapped = pci_p2pdma_map_sg_attrs(dev->dev, iod->sg,
821 iod->nents, rq_dma_dir(req), DMA_ATTR_NO_WARN);
e0596ab2
LG		 822 else
823 nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents,
70479b71 824 rq_dma_dir(req), DMA_ATTR_NO_WARN);
b0f2853b 825 if (!nr_mapped)
ba1ca37e 826 goto out;
d29ec824 827
70479b71 828 iod->use_sgl = nvme_pci_use_sgls(dev, req);
955b1b5a 829 if (iod->use_sgl)
b0f2853b 830 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped);
a7a7cbe3
CK		 831 else
832 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
4aedb705 833out:
86eea289 834 if (ret != BLK_STS_OK)
4aedb705
CH		 835 nvme_unmap_data(dev, req);
836 return ret;
837}
3045c0d0 838
4aedb705
CH		 839static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req,
840 struct nvme_command *cmnd)
841{
842 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
00df5cb4 843
4aedb705
CH		 844 iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req),
845 rq_dma_dir(req), 0);
846 if (dma_mapping_error(dev->dev, iod->meta_dma))
847 return BLK_STS_IOERR;
848 cmnd->rw.metadata = cpu_to_le64(iod->meta_dma);
849 return 0;
00df5cb4
MW		 850}
851
d29ec824
CH		 852/*
853 * NOTE: ns is NULL when called on the admin queue.
854 */
fc17b653 855static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
a4aea562 856 const struct blk_mq_queue_data *bd)
edd10d33 857{
a4aea562
MB		 858 struct nvme_ns *ns = hctx->queue->queuedata;
859 struct nvme_queue *nvmeq = hctx->driver_data;
d29ec824 860 struct nvme_dev *dev = nvmeq->dev;
a4aea562 861 struct request *req = bd->rq;
9b048119 862 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
ba1ca37e 863 struct nvme_command cmnd;
ebe6d874 864 blk_status_t ret;
e1e5e564 865
9b048119
CH		 866 iod->aborted = 0;
867 iod->npages = -1;
868 iod->nents = 0;
869
d1f06f4a
JA		 870 /*
871 * We should not need to do this, but we're still using this to
872 * ensure we can drain requests on a dying queue.
873 */
4e224106 874 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
d1f06f4a
JA		 875 return BLK_STS_IOERR;
876
f9d03f96 877 ret = nvme_setup_cmd(ns, req, &cmnd);
fc17b653 878 if (ret)
f4800d6d 879 return ret;
a4aea562 880
fc17b653 881 if (blk_rq_nr_phys_segments(req)) {
b131c61d 882 ret = nvme_map_data(dev, req, &cmnd);
fc17b653 883 if (ret)
9b048119 884 goto out_free_cmd;
fc17b653 885 }
a4aea562 886
4aedb705
CH		 887 if (blk_integrity_rq(req)) {
888 ret = nvme_map_metadata(dev, req, &cmnd);
889 if (ret)
890 goto out_unmap_data;
891 }
892
aae239e1 893 blk_mq_start_request(req);
04f3eafd 894 nvme_submit_cmd(nvmeq, &cmnd, bd->last);
fc17b653 895 return BLK_STS_OK;
4aedb705
CH		 896out_unmap_data:
897 nvme_unmap_data(dev, req);
f9d03f96
CH		 898out_free_cmd:
899 nvme_cleanup_cmd(req);
ba1ca37e 900 return ret;
b60503ba 901}
e1e5e564 902
77f02a7a 903static void nvme_pci_complete_rq(struct request *req)
eee417b0 904{
f4800d6d 905 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
4aedb705 906 struct nvme_dev *dev = iod->nvmeq->dev;
a4aea562 907
4aedb705
CH		 908 if (blk_integrity_rq(req))
909 dma_unmap_page(dev->dev, iod->meta_dma,
910 rq_integrity_vec(req)->bv_len, rq_data_dir(req));
b15c592d 911 if (blk_rq_nr_phys_segments(req))
4aedb705 912 nvme_unmap_data(dev, req);
77f02a7a 913 nvme_complete_rq(req);
b60503ba
MW		 914}
915
d783e0bd 916/* We read the CQE phase first to check if the rest of the entry is valid */
750dde44 917static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq)
d783e0bd 918{
74943d45
KB		 919 struct nvme_completion *hcqe = &nvmeq->cqes[nvmeq->cq_head];
920
921 return (le16_to_cpu(READ_ONCE(hcqe->status)) & 1) == nvmeq->cq_phase;
d783e0bd
MR		 922}
923
eb281c82 924static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
b60503ba 925{
eb281c82 926 u16 head = nvmeq->cq_head;
adf68f21 927
397c699f
KB		 928 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
929 nvmeq->dbbuf_cq_ei))
930 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
eb281c82 931}
aae239e1 932
cfa27356
CH		 933static inline struct blk_mq_tags *nvme_queue_tagset(struct nvme_queue *nvmeq)
934{
935 if (!nvmeq->qid)
936 return nvmeq->dev->admin_tagset.tags[0];
937 return nvmeq->dev->tagset.tags[nvmeq->qid - 1];
938}
939
5cb525c8 940static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx)
83a12fb7 941{
74943d45 942 struct nvme_completion *cqe = &nvmeq->cqes[idx];
83a12fb7 943 struct request *req;
adf68f21 944
83a12fb7
SG		 945 if (unlikely(cqe->command_id >= nvmeq->q_depth)) {
946 dev_warn(nvmeq->dev->ctrl.device,
947 "invalid id %d completed on queue %d\n",
948 cqe->command_id, le16_to_cpu(cqe->sq_id));
949 return;
b60503ba
MW		 950 }
951
83a12fb7
SG		 952 /*
953 * AEN requests are special as they don't time out and can
954 * survive any kind of queue freeze and often don't respond to
955 * aborts. We don't even bother to allocate a struct request
956 * for them but rather special case them here.
957 */
58a8df67 958 if (unlikely(nvme_is_aen_req(nvmeq->qid, cqe->command_id))) {
83a12fb7
SG		 959 nvme_complete_async_event(&nvmeq->dev->ctrl,
960 cqe->status, &cqe->result);
a0fa9647 961 return;
83a12fb7 962 }
b60503ba 963
cfa27356 964 req = blk_mq_tag_to_rq(nvme_queue_tagset(nvmeq), cqe->command_id);
604c01d5 965 trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail);
ff029451
CH		 966 if (!nvme_end_request(req, cqe->status, cqe->result))
967 nvme_pci_complete_rq(req);
83a12fb7 968}
b60503ba 969
5cb525c8
JA		 970static inline void nvme_update_cq_head(struct nvme_queue *nvmeq)
971{
a8de6639
AD		 972 u16 tmp = nvmeq->cq_head + 1;
973
974 if (tmp == nvmeq->q_depth) {
5cb525c8 975 nvmeq->cq_head = 0;
e2a366a4 976 nvmeq->cq_phase ^= 1;
a8de6639
AD		 977 } else {
978 nvmeq->cq_head = tmp;
b60503ba 979 }
a0fa9647
JA		 980}
981
324b494c 982static inline int nvme_process_cq(struct nvme_queue *nvmeq)
a0fa9647 983{
1052b8ac 984 int found = 0;
b60503ba 985
1052b8ac 986 while (nvme_cqe_pending(nvmeq)) {
bf392a5d 987 found++;
b69e2ef2
KB		 988 /*
989 * load-load control dependency between phase and the rest of
990 * the cqe requires a full read memory barrier
991 */
992 dma_rmb();
324b494c 993 nvme_handle_cqe(nvmeq, nvmeq->cq_head);
5cb525c8 994 nvme_update_cq_head(nvmeq);
920d13a8 995 }
eb281c82 996
324b494c 997 if (found)
920d13a8 998 nvme_ring_cq_doorbell(nvmeq);
5cb525c8 999 return found;
b60503ba
MW		 1000}
1001
1002static irqreturn_t nvme_irq(int irq, void *data)
58ffacb5 1003{
58ffacb5 1004 struct nvme_queue *nvmeq = data;
68fa9dbe 1005 irqreturn_t ret = IRQ_NONE;
5cb525c8 1006
3a7afd8e
CH		 1007 /*
1008 * The rmb/wmb pair ensures we see all updates from a previous run of
1009 * the irq handler, even if that was on another CPU.
1010 */
1011 rmb();
324b494c
KB		 1012 if (nvme_process_cq(nvmeq))
1013 ret = IRQ_HANDLED;
3a7afd8e 1014 wmb();
5cb525c8 1015
68fa9dbe 1016 return ret;
58ffacb5
MW		 1017}
1018
1019static irqreturn_t nvme_irq_check(int irq, void *data)
1020{
1021 struct nvme_queue *nvmeq = data;
750dde44 1022 if (nvme_cqe_pending(nvmeq))
d783e0bd
MR		 1023 return IRQ_WAKE_THREAD;
1024 return IRQ_NONE;
58ffacb5
MW		 1025}
1026
0b2a8a9f 1027/*
fa059b85 1028 * Poll for completions for any interrupt driven queue
0b2a8a9f
CH		 1029 * Can be called from any context.
1030 */
fa059b85 1031static void nvme_poll_irqdisable(struct nvme_queue *nvmeq)
a0fa9647 1032{
3a7afd8e 1033 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
a0fa9647 1034
fa059b85 1035 WARN_ON_ONCE(test_bit(NVMEQ_POLLED, &nvmeq->flags));
442e19b7 1036
fa059b85
KB		 1037 disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1038 nvme_process_cq(nvmeq);
1039 enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
a0fa9647
JA		 1040}
1041
9743139c 1042static int nvme_poll(struct blk_mq_hw_ctx *hctx)
dabcefab
JA		 1043{
1044 struct nvme_queue *nvmeq = hctx->driver_data;
dabcefab
JA		 1045 bool found;
1046
1047 if (!nvme_cqe_pending(nvmeq))
1048 return 0;
1049
3a7afd8e 1050 spin_lock(&nvmeq->cq_poll_lock);
324b494c 1051 found = nvme_process_cq(nvmeq);
3a7afd8e 1052 spin_unlock(&nvmeq->cq_poll_lock);
dabcefab 1053
dabcefab
JA		 1054 return found;
1055}
1056
ad22c355 1057static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
b60503ba 1058{
f866fc42 1059 struct nvme_dev *dev = to_nvme_dev(ctrl);
147b27e4 1060 struct nvme_queue *nvmeq = &dev->queues[0];
a4aea562 1061 struct nvme_command c;
b60503ba 1062
a4aea562
MB		 1063 memset(&c, 0, sizeof(c));
1064 c.common.opcode = nvme_admin_async_event;
ad22c355 1065 c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
04f3eafd 1066 nvme_submit_cmd(nvmeq, &c, true);
f705f837
CH		 1067}
1068
b60503ba 1069static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
f705f837 1070{
b60503ba
MW		 1071 struct nvme_command c;
1072
1073 memset(&c, 0, sizeof(c));
1074 c.delete_queue.opcode = opcode;
1075 c.delete_queue.qid = cpu_to_le16(id);
1076
1c63dc66 1077 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1078}
1079
b60503ba 1080static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
a8e3e0bb 1081 struct nvme_queue *nvmeq, s16 vector)
b60503ba 1082{
b60503ba 1083 struct nvme_command c;
4b04cc6a
JA		 1084 int flags = NVME_QUEUE_PHYS_CONTIG;
1085
7c349dde 1086 if (!test_bit(NVMEQ_POLLED, &nvmeq->flags))
4b04cc6a 1087 flags |= NVME_CQ_IRQ_ENABLED;
b60503ba 1088
d29ec824 1089 /*
16772ae6 1090 * Note: we (ab)use the fact that the prp fields survive if no data
d29ec824
CH		 1091 * is attached to the request.
1092 */
b60503ba
MW		 1093 memset(&c, 0, sizeof(c));
1094 c.create_cq.opcode = nvme_admin_create_cq;
1095 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1096 c.create_cq.cqid = cpu_to_le16(qid);
1097 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1098 c.create_cq.cq_flags = cpu_to_le16(flags);
7c349dde 1099 c.create_cq.irq_vector = cpu_to_le16(vector);
b60503ba 1100
1c63dc66 1101 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1102}
1103
1104static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1105 struct nvme_queue *nvmeq)
1106{
9abd68ef 1107 struct nvme_ctrl *ctrl = &dev->ctrl;
b60503ba 1108 struct nvme_command c;
81c1cd98 1109 int flags = NVME_QUEUE_PHYS_CONTIG;
b60503ba 1110
9abd68ef
JA		 1111 /*
1112 * Some drives have a bug that auto-enables WRRU if MEDIUM isn't
1113 * set. Since URGENT priority is zeroes, it makes all queues
1114 * URGENT.
1115 */
1116 if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ)
1117 flags |= NVME_SQ_PRIO_MEDIUM;
1118
d29ec824 1119 /*
16772ae6 1120 * Note: we (ab)use the fact that the prp fields survive if no data
d29ec824
CH		 1121 * is attached to the request.
1122 */
b60503ba
MW		 1123 memset(&c, 0, sizeof(c));
1124 c.create_sq.opcode = nvme_admin_create_sq;
1125 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1126 c.create_sq.sqid = cpu_to_le16(qid);
1127 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1128 c.create_sq.sq_flags = cpu_to_le16(flags);
1129 c.create_sq.cqid = cpu_to_le16(qid);
1130
1c63dc66 1131 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1132}
1133
1134static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1135{
1136 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1137}
1138
1139static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1140{
1141 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1142}
1143
2a842aca 1144static void abort_endio(struct request *req, blk_status_t error)
bc5fc7e4 1145{
f4800d6d
CH		 1146 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1147 struct nvme_queue *nvmeq = iod->nvmeq;
e44ac588 1148
27fa9bc5
CH		 1149 dev_warn(nvmeq->dev->ctrl.device,
1150 "Abort status: 0x%x", nvme_req(req)->status);
e7a2a87d 1151 atomic_inc(&nvmeq->dev->ctrl.abort_limit);
e7a2a87d 1152 blk_mq_free_request(req);
bc5fc7e4
MW		 1153}
1154
b2a0eb1a
KB		 1155static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1156{
1157
1158 /* If true, indicates loss of adapter communication, possibly by a
1159 * NVMe Subsystem reset.
1160 */
1161 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1162
ad70062c
JW		 1163 /* If there is a reset/reinit ongoing, we shouldn't reset again. */
1164 switch (dev->ctrl.state) {
1165 case NVME_CTRL_RESETTING:
ad6a0a52 1166 case NVME_CTRL_CONNECTING:
b2a0eb1a 1167 return false;
ad70062c
JW		 1168 default:
1169 break;
1170 }
b2a0eb1a
KB		 1171
1172 /* We shouldn't reset unless the controller is on fatal error state
1173 * _or_ if we lost the communication with it.
1174 */
1175 if (!(csts & NVME_CSTS_CFS) && !nssro)
1176 return false;
1177
b2a0eb1a
KB		 1178 return true;
1179}
1180
1181static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1182{
1183 /* Read a config register to help see what died. */
1184 u16 pci_status;
1185 int result;
1186
1187 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1188 &pci_status);
1189 if (result == PCIBIOS_SUCCESSFUL)
1190 dev_warn(dev->ctrl.device,
1191 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1192 csts, pci_status);
1193 else
1194 dev_warn(dev->ctrl.device,
1195 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1196 csts, result);
1197}
1198
31c7c7d2 1199static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
c30341dc 1200{
f4800d6d
CH		 1201 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1202 struct nvme_queue *nvmeq = iod->nvmeq;
c30341dc 1203 struct nvme_dev *dev = nvmeq->dev;
a4aea562 1204 struct request *abort_req;
a4aea562 1205 struct nvme_command cmd;
b2a0eb1a
KB		 1206 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1207
651438bb
WX		 1208 /* If PCI error recovery process is happening, we cannot reset or
1209 * the recovery mechanism will surely fail.
1210 */
1211 mb();
1212 if (pci_channel_offline(to_pci_dev(dev->dev)))
1213 return BLK_EH_RESET_TIMER;
1214
b2a0eb1a
KB		 1215 /*
1216 * Reset immediately if the controller is failed
1217 */
1218 if (nvme_should_reset(dev, csts)) {
1219 nvme_warn_reset(dev, csts);
1220 nvme_dev_disable(dev, false);
d86c4d8e 1221 nvme_reset_ctrl(&dev->ctrl);
db8c48e4 1222 return BLK_EH_DONE;
b2a0eb1a 1223 }
c30341dc 1224
7776db1c
KB		 1225 /*
1226 * Did we miss an interrupt?
1227 */
fa059b85
KB		 1228 if (test_bit(NVMEQ_POLLED, &nvmeq->flags))
1229 nvme_poll(req->mq_hctx);
1230 else
1231 nvme_poll_irqdisable(nvmeq);
1232
bf392a5d 1233 if (blk_mq_request_completed(req)) {
7776db1c
KB		 1234 dev_warn(dev->ctrl.device,
1235 "I/O %d QID %d timeout, completion polled\n",
1236 req->tag, nvmeq->qid);
db8c48e4 1237 return BLK_EH_DONE;
7776db1c
KB		 1238 }
1239
31c7c7d2 1240 /*
fd634f41
CH		 1241 * Shutdown immediately if controller times out while starting. The
1242 * reset work will see the pci device disabled when it gets the forced
1243 * cancellation error. All outstanding requests are completed on
db8c48e4 1244 * shutdown, so we return BLK_EH_DONE.
fd634f41 1245 */
4244140d
KB		 1246 switch (dev->ctrl.state) {
1247 case NVME_CTRL_CONNECTING:
2036f726
KB		 1248 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
1249 /* fall through */
1250 case NVME_CTRL_DELETING:
b9cac43c 1251 dev_warn_ratelimited(dev->ctrl.device,
fd634f41
CH		 1252 "I/O %d QID %d timeout, disable controller\n",
1253 req->tag, nvmeq->qid);
2036f726 1254 nvme_dev_disable(dev, true);
27fa9bc5 1255 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
db8c48e4 1256 return BLK_EH_DONE;
39a9dd81
KB		 1257 case NVME_CTRL_RESETTING:
1258 return BLK_EH_RESET_TIMER;
4244140d
KB		 1259 default:
1260 break;
c30341dc
KB		 1261 }
1262
fd634f41
CH		 1263 /*
1264 * Shutdown the controller immediately and schedule a reset if the
1265 * command was already aborted once before and still hasn't been
1266 * returned to the driver, or if this is the admin queue.
31c7c7d2 1267 */
f4800d6d 1268 if (!nvmeq->qid || iod->aborted) {
1b3c47c1 1269 dev_warn(dev->ctrl.device,
e1569a16
KB		 1270 "I/O %d QID %d timeout, reset controller\n",
1271 req->tag, nvmeq->qid);
a5cdb68c 1272 nvme_dev_disable(dev, false);
d86c4d8e 1273 nvme_reset_ctrl(&dev->ctrl);
c30341dc 1274
27fa9bc5 1275 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
db8c48e4 1276 return BLK_EH_DONE;
c30341dc 1277 }
c30341dc 1278
e7a2a87d 1279 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
6bf25d16 1280 atomic_inc(&dev->ctrl.abort_limit);
31c7c7d2 1281 return BLK_EH_RESET_TIMER;
6bf25d16 1282 }
7bf7d778 1283 iod->aborted = 1;
a4aea562 1284
c30341dc
KB		 1285 memset(&cmd, 0, sizeof(cmd));
1286 cmd.abort.opcode = nvme_admin_abort_cmd;
a4aea562 1287 cmd.abort.cid = req->tag;
c30341dc 1288 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
c30341dc 1289
1b3c47c1
SG		 1290 dev_warn(nvmeq->dev->ctrl.device,
1291 "I/O %d QID %d timeout, aborting\n",
1292 req->tag, nvmeq->qid);
e7a2a87d
CH		 1293
1294 abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
eb71f435 1295 BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
e7a2a87d
CH		 1296 if (IS_ERR(abort_req)) {
1297 atomic_inc(&dev->ctrl.abort_limit);
1298 return BLK_EH_RESET_TIMER;
1299 }
1300
1301 abort_req->timeout = ADMIN_TIMEOUT;
1302 abort_req->end_io_data = NULL;
1303 blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio);
c30341dc 1304
31c7c7d2
CH		 1305 /*
1306 * The aborted req will be completed on receiving the abort req.
1307 * We enable the timer again. If hit twice, it'll cause a device reset,
1308 * as the device then is in a faulty state.
1309 */
1310 return BLK_EH_RESET_TIMER;
c30341dc
KB		 1311}
1312
a4aea562
MB		 1313static void nvme_free_queue(struct nvme_queue *nvmeq)
1314{
8a1d09a6 1315 dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq),
9e866774 1316 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
63223078
CH		 1317 if (!nvmeq->sq_cmds)
1318 return;
0f238ff5 1319
63223078 1320 if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) {
88a041f4 1321 pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev),
8a1d09a6 1322 nvmeq->sq_cmds, SQ_SIZE(nvmeq));
63223078 1323 } else {
8a1d09a6 1324 dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq),
63223078 1325 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
0f238ff5 1326 }
9e866774
MW		 1327}
1328
a1a5ef99 1329static void nvme_free_queues(struct nvme_dev *dev, int lowest)
22404274
KB		 1330{
1331 int i;
1332
d858e5f0 1333 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
d858e5f0 1334 dev->ctrl.queue_count--;
147b27e4 1335 nvme_free_queue(&dev->queues[i]);
121c7ad4 1336 }
22404274
KB		 1337}
1338
4d115420
KB		 1339/**
1340 * nvme_suspend_queue - put queue into suspended state
40581d1a 1341 * @nvmeq: queue to suspend
4d115420
KB		 1342 */
1343static int nvme_suspend_queue(struct nvme_queue *nvmeq)
b60503ba 1344{
4e224106 1345 if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags))
2b25d981 1346 return 1;
a09115b2 1347
4e224106 1348 /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */
d1f06f4a 1349 mb();
a09115b2 1350
4e224106 1351 nvmeq->dev->online_queues--;
1c63dc66 1352 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
c81545f9 1353 blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q);
7c349dde
KB		 1354 if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags))
1355 pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq);
4d115420
KB		 1356 return 0;
1357}
b60503ba 1358
8fae268b
KB		 1359static void nvme_suspend_io_queues(struct nvme_dev *dev)
1360{
1361 int i;
1362
1363 for (i = dev->ctrl.queue_count - 1; i > 0; i--)
1364 nvme_suspend_queue(&dev->queues[i]);
1365}
1366
a5cdb68c 1367static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
4d115420 1368{
147b27e4 1369 struct nvme_queue *nvmeq = &dev->queues[0];
4d115420 1370
a5cdb68c
KB		 1371 if (shutdown)
1372 nvme_shutdown_ctrl(&dev->ctrl);
1373 else
b5b05048 1374 nvme_disable_ctrl(&dev->ctrl);
07836e65 1375
bf392a5d 1376 nvme_poll_irqdisable(nvmeq);
b60503ba
MW		 1377}
1378
fa46c6fb
KB		 1379/*
1380 * Called only on a device that has been disabled and after all other threads
9210c075
DZ		 1381 * that can check this device's completion queues have synced, except
1382 * nvme_poll(). This is the last chance for the driver to see a natural
1383 * completion before nvme_cancel_request() terminates all incomplete requests.
fa46c6fb
KB		 1384 */
1385static void nvme_reap_pending_cqes(struct nvme_dev *dev)
1386{
fa46c6fb
KB		 1387 int i;
1388
9210c075
DZ		 1389 for (i = dev->ctrl.queue_count - 1; i > 0; i--) {
1390 spin_lock(&dev->queues[i].cq_poll_lock);
324b494c 1391 nvme_process_cq(&dev->queues[i]);
9210c075
DZ		 1392 spin_unlock(&dev->queues[i].cq_poll_lock);
1393 }
fa46c6fb
KB		 1394}
1395
8ffaadf7
JD		 1396static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1397 int entry_size)
1398{
1399 int q_depth = dev->q_depth;
5fd4ce1b
CH		 1400 unsigned q_size_aligned = roundup(q_depth * entry_size,
1401 dev->ctrl.page_size);
8ffaadf7
JD		 1402
1403 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
c45f5c99 1404 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
5fd4ce1b 1405 mem_per_q = round_down(mem_per_q, dev->ctrl.page_size);
c45f5c99 1406 q_depth = div_u64(mem_per_q, entry_size);
8ffaadf7
JD		 1407
1408 /*
1409 * Ensure the reduced q_depth is above some threshold where it
1410 * would be better to map queues in system memory with the
1411 * original depth
1412 */
1413 if (q_depth < 64)
1414 return -ENOMEM;
1415 }
1416
1417 return q_depth;
1418}
1419
1420static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
8a1d09a6 1421 int qid)
8ffaadf7 1422{
0f238ff5
LG		 1423 struct pci_dev *pdev = to_pci_dev(dev->dev);
1424
1425 if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
8a1d09a6 1426 nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq));
bfac8e9f
AM		 1427 if (nvmeq->sq_cmds) {
1428 nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev,
1429 nvmeq->sq_cmds);
1430 if (nvmeq->sq_dma_addr) {
1431 set_bit(NVMEQ_SQ_CMB, &nvmeq->flags);
1432 return 0;
1433 }
1434
8a1d09a6 1435 pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq));
63223078 1436 }
0f238ff5 1437 }
8ffaadf7 1438
8a1d09a6 1439 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq),
63223078 1440 &nvmeq->sq_dma_addr, GFP_KERNEL);
815c6704
KB		 1441 if (!nvmeq->sq_cmds)
1442 return -ENOMEM;
8ffaadf7
JD		 1443 return 0;
1444}
1445
a6ff7262 1446static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
b60503ba 1447{
147b27e4 1448 struct nvme_queue *nvmeq = &dev->queues[qid];
b60503ba 1449
62314e40
KB		 1450 if (dev->ctrl.queue_count > qid)
1451 return 0;
b60503ba 1452
c1e0cc7e 1453 nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES;
8a1d09a6
BH		 1454 nvmeq->q_depth = depth;
1455 nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq),
750afb08 1456 &nvmeq->cq_dma_addr, GFP_KERNEL);
b60503ba
MW		 1457 if (!nvmeq->cqes)
1458 goto free_nvmeq;
b60503ba 1459
8a1d09a6 1460 if (nvme_alloc_sq_cmds(dev, nvmeq, qid))
b60503ba
MW		 1461 goto free_cqdma;
1462
091b6092 1463 nvmeq->dev = dev;
1ab0cd69 1464 spin_lock_init(&nvmeq->sq_lock);
3a7afd8e 1465 spin_lock_init(&nvmeq->cq_poll_lock);
b60503ba 1466 nvmeq->cq_head = 0;
82123460 1467 nvmeq->cq_phase = 1;
b80d5ccc 1468 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
c30341dc 1469 nvmeq->qid = qid;
d858e5f0 1470 dev->ctrl.queue_count++;
36a7e993 1471
147b27e4 1472 return 0;
b60503ba
MW		 1473
1474 free_cqdma:
8a1d09a6
BH		 1475 dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes,
1476 nvmeq->cq_dma_addr);
b60503ba 1477 free_nvmeq:
147b27e4 1478 return -ENOMEM;
b60503ba
MW		 1479}
1480
dca51e78 1481static int queue_request_irq(struct nvme_queue *nvmeq)
3001082c 1482{
0ff199cb
CH		 1483 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1484 int nr = nvmeq->dev->ctrl.instance;
1485
1486 if (use_threaded_interrupts) {
1487 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1488 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1489 } else {
1490 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1491 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1492 }
3001082c
MW		 1493}
1494
22404274 1495static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
b60503ba 1496{
22404274 1497 struct nvme_dev *dev = nvmeq->dev;
b60503ba 1498
22404274
KB		 1499 nvmeq->sq_tail = 0;
1500 nvmeq->cq_head = 0;
1501 nvmeq->cq_phase = 1;
b80d5ccc 1502 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
8a1d09a6 1503 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq));
f9f38e33 1504 nvme_dbbuf_init(dev, nvmeq, qid);
42f61420 1505 dev->online_queues++;
3a7afd8e 1506 wmb(); /* ensure the first interrupt sees the initialization */
22404274
KB		 1507}
1508
4b04cc6a 1509static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled)
22404274
KB		 1510{
1511 struct nvme_dev *dev = nvmeq->dev;
1512 int result;
7c349dde 1513 u16 vector = 0;
3f85d50b 1514
d1ed6aa1
CH		 1515 clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
1516
22b55601
KB		 1517 /*
1518 * A queue's vector matches the queue identifier unless the controller
1519 * has only one vector available.
1520 */
4b04cc6a
JA		 1521 if (!polled)
1522 vector = dev->num_vecs == 1 ? 0 : qid;
1523 else
7c349dde 1524 set_bit(NVMEQ_POLLED, &nvmeq->flags);
4b04cc6a 1525
a8e3e0bb 1526 result = adapter_alloc_cq(dev, qid, nvmeq, vector);
ded45505
KB		 1527 if (result)
1528 return result;
b60503ba
MW		 1529
1530 result = adapter_alloc_sq(dev, qid, nvmeq);
1531 if (result < 0)
ded45505 1532 return result;
c80b36cd 1533 if (result)
b60503ba
MW		 1534 goto release_cq;
1535
a8e3e0bb 1536 nvmeq->cq_vector = vector;
161b8be2 1537 nvme_init_queue(nvmeq, qid);
4b04cc6a 1538
7c349dde 1539 if (!polled) {
4b04cc6a
JA		 1540 result = queue_request_irq(nvmeq);
1541 if (result < 0)
1542 goto release_sq;
1543 }
b60503ba 1544
4e224106 1545 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
22404274 1546 return result;
b60503ba 1547
a8e3e0bb 1548release_sq:
f25a2dfc 1549 dev->online_queues--;
b60503ba 1550 adapter_delete_sq(dev, qid);
a8e3e0bb 1551release_cq:
b60503ba 1552 adapter_delete_cq(dev, qid);
22404274 1553 return result;
b60503ba
MW		 1554}
1555
f363b089 1556static const struct blk_mq_ops nvme_mq_admin_ops = {
d29ec824 1557 .queue_rq = nvme_queue_rq,
77f02a7a 1558 .complete = nvme_pci_complete_rq,
a4aea562 1559 .init_hctx = nvme_admin_init_hctx,
0350815a 1560 .init_request = nvme_init_request,
a4aea562
MB		 1561 .timeout = nvme_timeout,
1562};
1563
f363b089 1564static const struct blk_mq_ops nvme_mq_ops = {
376f7ef8
CH		 1565 .queue_rq = nvme_queue_rq,
1566 .complete = nvme_pci_complete_rq,
1567 .commit_rqs = nvme_commit_rqs,
1568 .init_hctx = nvme_init_hctx,
1569 .init_request = nvme_init_request,
1570 .map_queues = nvme_pci_map_queues,
1571 .timeout = nvme_timeout,
1572 .poll = nvme_poll,
dabcefab
JA		 1573};
1574
ea191d2f
KB		 1575static void nvme_dev_remove_admin(struct nvme_dev *dev)
1576{
1c63dc66 1577 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
69d9a99c
KB		 1578 /*
1579 * If the controller was reset during removal, it's possible
1580 * user requests may be waiting on a stopped queue. Start the
1581 * queue to flush these to completion.
1582 */
c81545f9 1583 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1c63dc66 1584 blk_cleanup_queue(dev->ctrl.admin_q);
ea191d2f
KB		 1585 blk_mq_free_tag_set(&dev->admin_tagset);
1586 }
1587}
1588
a4aea562
MB		 1589static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1590{
1c63dc66 1591 if (!dev->ctrl.admin_q) {
a4aea562
MB		 1592 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1593 dev->admin_tagset.nr_hw_queues = 1;
e3e9d50c 1594
38dabe21 1595 dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH;
a4aea562 1596 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
d4ec47f1 1597 dev->admin_tagset.numa_node = dev->ctrl.numa_node;
d43f1ccf 1598 dev->admin_tagset.cmd_size = sizeof(struct nvme_iod);
d3484991 1599 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED;
a4aea562
MB		 1600 dev->admin_tagset.driver_data = dev;
1601
1602 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1603 return -ENOMEM;
34b6c231 1604 dev->ctrl.admin_tagset = &dev->admin_tagset;
a4aea562 1605
1c63dc66
CH		 1606 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1607 if (IS_ERR(dev->ctrl.admin_q)) {
a4aea562
MB		 1608 blk_mq_free_tag_set(&dev->admin_tagset);
1609 return -ENOMEM;
1610 }
1c63dc66 1611 if (!blk_get_queue(dev->ctrl.admin_q)) {
ea191d2f 1612 nvme_dev_remove_admin(dev);
1c63dc66 1613 dev->ctrl.admin_q = NULL;
ea191d2f
KB		 1614 return -ENODEV;
1615 }
0fb59cbc 1616 } else
c81545f9 1617 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
a4aea562
MB		 1618
1619 return 0;
1620}
1621
97f6ef64
XY		 1622static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1623{
1624 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1625}
1626
1627static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1628{
1629 struct pci_dev *pdev = to_pci_dev(dev->dev);
1630
1631 if (size <= dev->bar_mapped_size)
1632 return 0;
1633 if (size > pci_resource_len(pdev, 0))
1634 return -ENOMEM;
1635 if (dev->bar)
1636 iounmap(dev->bar);
1637 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1638 if (!dev->bar) {
1639 dev->bar_mapped_size = 0;
1640 return -ENOMEM;
1641 }
1642 dev->bar_mapped_size = size;
1643 dev->dbs = dev->bar + NVME_REG_DBS;
1644
1645 return 0;
1646}
1647
01ad0990 1648static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
b60503ba 1649{
ba47e386 1650 int result;
b60503ba
MW		 1651 u32 aqa;
1652 struct nvme_queue *nvmeq;
1653
97f6ef64
XY		 1654 result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1655 if (result < 0)
1656 return result;
1657
8ef2074d 1658 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
20d0dfe6 1659 NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
dfbac8c7 1660
7a67cbea
CH		 1661 if (dev->subsystem &&
1662 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1663 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
dfbac8c7 1664
b5b05048 1665 result = nvme_disable_ctrl(&dev->ctrl);
ba47e386
MW		 1666 if (result < 0)
1667 return result;
b60503ba 1668
a6ff7262 1669 result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
147b27e4
SG		 1670 if (result)
1671 return result;
b60503ba 1672
635333e4
MG		 1673 dev->ctrl.numa_node = dev_to_node(dev->dev);
1674
147b27e4 1675 nvmeq = &dev->queues[0];
b60503ba
MW		 1676 aqa = nvmeq->q_depth - 1;
1677 aqa |= aqa << 16;
1678
7a67cbea
CH		 1679 writel(aqa, dev->bar + NVME_REG_AQA);
1680 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1681 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
b60503ba 1682
c0f2f45b 1683 result = nvme_enable_ctrl(&dev->ctrl);
025c557a 1684 if (result)
d4875622 1685 return result;
a4aea562 1686
2b25d981 1687 nvmeq->cq_vector = 0;
161b8be2 1688 nvme_init_queue(nvmeq, 0);
dca51e78 1689 result = queue_request_irq(nvmeq);
758dd7fd 1690 if (result) {
7c349dde 1691 dev->online_queues--;
d4875622 1692 return result;
758dd7fd 1693 }
025c557a 1694
4e224106 1695 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
b60503ba
MW		 1696 return result;
1697}
1698
749941f2 1699static int nvme_create_io_queues(struct nvme_dev *dev)
42f61420 1700{
4b04cc6a 1701 unsigned i, max, rw_queues;
749941f2 1702 int ret = 0;
42f61420 1703
d858e5f0 1704 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
a6ff7262 1705 if (nvme_alloc_queue(dev, i, dev->q_depth)) {
749941f2 1706 ret = -ENOMEM;
42f61420 1707 break;
749941f2
CH		 1708 }
1709 }
42f61420 1710
d858e5f0 1711 max = min(dev->max_qid, dev->ctrl.queue_count - 1);
e20ba6e1
CH		 1712 if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) {
1713 rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] +
1714 dev->io_queues[HCTX_TYPE_READ];
4b04cc6a
JA		 1715 } else {
1716 rw_queues = max;
1717 }
1718
949928c1 1719 for (i = dev->online_queues; i <= max; i++) {
4b04cc6a
JA		 1720 bool polled = i > rw_queues;
1721
1722 ret = nvme_create_queue(&dev->queues[i], i, polled);
d4875622 1723 if (ret)
42f61420 1724 break;
27e8166c 1725 }
749941f2
CH		 1726
1727 /*
1728 * Ignore failing Create SQ/CQ commands, we can continue with less
8adb8c14
MI		 1729 * than the desired amount of queues, and even a controller without
1730 * I/O queues can still be used to issue admin commands. This might
749941f2
CH		 1731 * be useful to upgrade a buggy firmware for example.
1732 */
1733 return ret >= 0 ? 0 : ret;
b60503ba
MW		 1734}
1735
202021c1
SB		 1736static ssize_t nvme_cmb_show(struct device *dev,
1737 struct device_attribute *attr,
1738 char *buf)
1739{
1740 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
1741
c965809c 1742 return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n",
202021c1
SB		 1743 ndev->cmbloc, ndev->cmbsz);
1744}
1745static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL);
1746
88de4598 1747static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
8ffaadf7 1748{
88de4598
CH		 1749 u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
1750
1751 return 1ULL << (12 + 4 * szu);
1752}
1753
1754static u32 nvme_cmb_size(struct nvme_dev *dev)
1755{
1756 return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
1757}
1758
f65efd6d 1759static void nvme_map_cmb(struct nvme_dev *dev)
8ffaadf7 1760{
88de4598 1761 u64 size, offset;
8ffaadf7
JD		 1762 resource_size_t bar_size;
1763 struct pci_dev *pdev = to_pci_dev(dev->dev);
8969f1f8 1764 int bar;
8ffaadf7 1765
9fe5c59f
KB		 1766 if (dev->cmb_size)
1767 return;
1768
7a67cbea 1769 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
f65efd6d
CH		 1770 if (!dev->cmbsz)
1771 return;
202021c1 1772 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
8ffaadf7 1773
88de4598
CH		 1774 size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
1775 offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
8969f1f8
CH		 1776 bar = NVME_CMB_BIR(dev->cmbloc);
1777 bar_size = pci_resource_len(pdev, bar);
8ffaadf7
JD		 1778
1779 if (offset > bar_size)
f65efd6d 1780 return;
8ffaadf7
JD		 1781
1782 /*
1783 * Controllers may support a CMB size larger than their BAR,
1784 * for example, due to being behind a bridge. Reduce the CMB to
1785 * the reported size of the BAR
1786 */
1787 if (size > bar_size - offset)
1788 size = bar_size - offset;
1789
0f238ff5
LG		 1790 if (pci_p2pdma_add_resource(pdev, bar, size, offset)) {
1791 dev_warn(dev->ctrl.device,
1792 "failed to register the CMB\n");
f65efd6d 1793 return;
0f238ff5
LG		 1794 }
1795
8ffaadf7 1796 dev->cmb_size = size;
0f238ff5
LG		 1797 dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS);
1798
1799 if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) ==
1800 (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS))
1801 pci_p2pmem_publish(pdev, true);
f65efd6d
CH		 1802
1803 if (sysfs_add_file_to_group(&dev->ctrl.device->kobj,
1804 &dev_attr_cmb.attr, NULL))
1805 dev_warn(dev->ctrl.device,
1806 "failed to add sysfs attribute for CMB\n");
8ffaadf7
JD		 1807}
1808
1809static inline void nvme_release_cmb(struct nvme_dev *dev)
1810{
0f238ff5 1811 if (dev->cmb_size) {
1c78f773
MG		 1812 sysfs_remove_file_from_group(&dev->ctrl.device->kobj,
1813 &dev_attr_cmb.attr, NULL);
0f238ff5 1814 dev->cmb_size = 0;
8ffaadf7
JD		 1815 }
1816}
1817
87ad72a5
CH		 1818static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1819{
4033f35d 1820 u64 dma_addr = dev->host_mem_descs_dma;
87ad72a5 1821 struct nvme_command c;
87ad72a5
CH		 1822 int ret;
1823
87ad72a5
CH		 1824 memset(&c, 0, sizeof(c));
1825 c.features.opcode = nvme_admin_set_features;
1826 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1827 c.features.dword11 = cpu_to_le32(bits);
1828 c.features.dword12 = cpu_to_le32(dev->host_mem_size >>
1829 ilog2(dev->ctrl.page_size));
1830 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr));
1831 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr));
1832 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs);
1833
1834 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1835 if (ret) {
1836 dev_warn(dev->ctrl.device,
1837 "failed to set host mem (err %d, flags %#x).\n",
1838 ret, bits);
1839 }
87ad72a5
CH		 1840 return ret;
1841}
1842
1843static void nvme_free_host_mem(struct nvme_dev *dev)
1844{
1845 int i;
1846
1847 for (i = 0; i < dev->nr_host_mem_descs; i++) {
1848 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
1849 size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size;
1850
cc667f6d
LD		 1851 dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i],
1852 le64_to_cpu(desc->addr),
1853 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
87ad72a5
CH		 1854 }
1855
1856 kfree(dev->host_mem_desc_bufs);
1857 dev->host_mem_desc_bufs = NULL;
4033f35d
CH		 1858 dma_free_coherent(dev->dev,
1859 dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
1860 dev->host_mem_descs, dev->host_mem_descs_dma);
87ad72a5 1861 dev->host_mem_descs = NULL;
7e5dd57e 1862 dev->nr_host_mem_descs = 0;
87ad72a5
CH		 1863}
1864
92dc6895
CH		 1865static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
1866 u32 chunk_size)
9d713c2b 1867{
87ad72a5 1868 struct nvme_host_mem_buf_desc *descs;
92dc6895 1869 u32 max_entries, len;
4033f35d 1870 dma_addr_t descs_dma;
2ee0e4ed 1871 int i = 0;
87ad72a5 1872 void **bufs;
6fbcde66 1873 u64 size, tmp;
87ad72a5 1874
87ad72a5
CH		 1875 tmp = (preferred + chunk_size - 1);
1876 do_div(tmp, chunk_size);
1877 max_entries = tmp;
044a9df1
CH		 1878
1879 if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
1880 max_entries = dev->ctrl.hmmaxd;
1881
750afb08
LC		 1882 descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs),
1883 &descs_dma, GFP_KERNEL);
87ad72a5
CH		 1884 if (!descs)
1885 goto out;
1886
1887 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
1888 if (!bufs)
1889 goto out_free_descs;
1890
244a8fe4 1891 for (size = 0; size < preferred && i < max_entries; size += len) {
87ad72a5
CH		 1892 dma_addr_t dma_addr;
1893
50cdb7c6 1894 len = min_t(u64, chunk_size, preferred - size);
87ad72a5
CH		 1895 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
1896 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1897 if (!bufs[i])
1898 break;
1899
1900 descs[i].addr = cpu_to_le64(dma_addr);
1901 descs[i].size = cpu_to_le32(len / dev->ctrl.page_size);
1902 i++;
1903 }
1904
92dc6895 1905 if (!size)
87ad72a5 1906 goto out_free_bufs;
87ad72a5 1907
87ad72a5
CH		 1908 dev->nr_host_mem_descs = i;
1909 dev->host_mem_size = size;
1910 dev->host_mem_descs = descs;
4033f35d 1911 dev->host_mem_descs_dma = descs_dma;
87ad72a5
CH		 1912 dev->host_mem_desc_bufs = bufs;
1913 return 0;
1914
1915out_free_bufs:
1916 while (--i >= 0) {
1917 size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size;
1918
cc667f6d
LD		 1919 dma_free_attrs(dev->dev, size, bufs[i],
1920 le64_to_cpu(descs[i].addr),
1921 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
87ad72a5
CH		 1922 }
1923
1924 kfree(bufs);
1925out_free_descs:
4033f35d
CH		 1926 dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
1927 descs_dma);
87ad72a5 1928out:
87ad72a5
CH		 1929 dev->host_mem_descs = NULL;
1930 return -ENOMEM;
1931}
1932
92dc6895
CH		 1933static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
1934{
1935 u32 chunk_size;
1936
1937 /* start big and work our way down */
30f92d62 1938 for (chunk_size = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
044a9df1 1939 chunk_size >= max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
92dc6895
CH		 1940 chunk_size /= 2) {
1941 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
1942 if (!min || dev->host_mem_size >= min)
1943 return 0;
1944 nvme_free_host_mem(dev);
1945 }
1946 }
1947
1948 return -ENOMEM;
1949}
1950
9620cfba 1951static int nvme_setup_host_mem(struct nvme_dev *dev)
87ad72a5
CH		 1952{
1953 u64 max = (u64)max_host_mem_size_mb * SZ_1M;
1954 u64 preferred = (u64)dev->ctrl.hmpre * 4096;
1955 u64 min = (u64)dev->ctrl.hmmin * 4096;
1956 u32 enable_bits = NVME_HOST_MEM_ENABLE;
6fbcde66 1957 int ret;
87ad72a5
CH		 1958
1959 preferred = min(preferred, max);
1960 if (min > max) {
1961 dev_warn(dev->ctrl.device,
1962 "min host memory (%lld MiB) above limit (%d MiB).\n",
1963 min >> ilog2(SZ_1M), max_host_mem_size_mb);
1964 nvme_free_host_mem(dev);
9620cfba 1965 return 0;
87ad72a5
CH		 1966 }
1967
1968 /*
1969 * If we already have a buffer allocated check if we can reuse it.
1970 */
1971 if (dev->host_mem_descs) {
1972 if (dev->host_mem_size >= min)
1973 enable_bits |= NVME_HOST_MEM_RETURN;
1974 else
1975 nvme_free_host_mem(dev);
1976 }
1977
1978 if (!dev->host_mem_descs) {
92dc6895
CH		 1979 if (nvme_alloc_host_mem(dev, min, preferred)) {
1980 dev_warn(dev->ctrl.device,
1981 "failed to allocate host memory buffer.\n");
9620cfba 1982 return 0; /* controller must work without HMB */
92dc6895
CH		 1983 }
1984
1985 dev_info(dev->ctrl.device,
1986 "allocated %lld MiB host memory buffer.\n",
1987 dev->host_mem_size >> ilog2(SZ_1M));
87ad72a5
CH		 1988 }
1989
9620cfba
CH		 1990 ret = nvme_set_host_mem(dev, enable_bits);
1991 if (ret)
87ad72a5 1992 nvme_free_host_mem(dev);
9620cfba 1993 return ret;
9d713c2b
KB		 1994}
1995
612b7286
ML		 1996/*
1997 * nirqs is the number of interrupts available for write and read
1998 * queues. The core already reserved an interrupt for the admin queue.
1999 */
2000static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs)
3b6592f7 2001{
612b7286 2002 struct nvme_dev *dev = affd->priv;
2a5bcfdd 2003 unsigned int nr_read_queues, nr_write_queues = dev->nr_write_queues;
3b6592f7
JA		 2004
2005 /*
612b7286
ML		 2006 * If there is no interupt available for queues, ensure that
2007 * the default queue is set to 1. The affinity set size is
2008 * also set to one, but the irq core ignores it for this case.
2009 *
2010 * If only one interrupt is available or 'write_queue' == 0, combine
2011 * write and read queues.
2012 *
2013 * If 'write_queues' > 0, ensure it leaves room for at least one read
2014 * queue.
3b6592f7 2015 */
612b7286
ML		 2016 if (!nrirqs) {
2017 nrirqs = 1;
2018 nr_read_queues = 0;
2a5bcfdd 2019 } else if (nrirqs == 1 || !nr_write_queues) {
612b7286 2020 nr_read_queues = 0;
2a5bcfdd 2021 } else if (nr_write_queues >= nrirqs) {
612b7286 2022 nr_read_queues = 1;
3b6592f7 2023 } else {
2a5bcfdd 2024 nr_read_queues = nrirqs - nr_write_queues;
3b6592f7 2025 }
612b7286
ML		 2026
2027 dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2028 affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2029 dev->io_queues[HCTX_TYPE_READ] = nr_read_queues;
2030 affd->set_size[HCTX_TYPE_READ] = nr_read_queues;
2031 affd->nr_sets = nr_read_queues ? 2 : 1;
3b6592f7
JA		 2032}
2033
6451fe73 2034static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues)
3b6592f7
JA		 2035{
2036 struct pci_dev *pdev = to_pci_dev(dev->dev);
3b6592f7 2037 struct irq_affinity affd = {
9cfef55b 2038 .pre_vectors = 1,
612b7286
ML		 2039 .calc_sets = nvme_calc_irq_sets,
2040 .priv = dev,
3b6592f7 2041 };
6451fe73
JA		 2042 unsigned int irq_queues, this_p_queues;
2043
2044 /*
2045 * Poll queues don't need interrupts, but we need at least one IO
2046 * queue left over for non-polled IO.
2047 */
2a5bcfdd 2048 this_p_queues = dev->nr_poll_queues;
6451fe73
JA		 2049 if (this_p_queues >= nr_io_queues) {
2050 this_p_queues = nr_io_queues - 1;
2051 irq_queues = 1;
2052 } else {
7e4c6b9a 2053 irq_queues = nr_io_queues - this_p_queues + 1;
6451fe73
JA		 2054 }
2055 dev->io_queues[HCTX_TYPE_POLL] = this_p_queues;
3b6592f7 2056
612b7286
ML		 2057 /* Initialize for the single interrupt case */
2058 dev->io_queues[HCTX_TYPE_DEFAULT] = 1;
2059 dev->io_queues[HCTX_TYPE_READ] = 0;
3b6592f7 2060
66341331
BH		 2061 /*
2062 * Some Apple controllers require all queues to use the
2063 * first vector.
2064 */
2065 if (dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR)
2066 irq_queues = 1;
2067
612b7286
ML		 2068 return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues,
2069 PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd);
3b6592f7
JA		 2070}
2071
8fae268b
KB		 2072static void nvme_disable_io_queues(struct nvme_dev *dev)
2073{
2074 if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq))
2075 __nvme_disable_io_queues(dev, nvme_admin_delete_cq);
2076}
2077
2a5bcfdd
WZ		 2078static unsigned int nvme_max_io_queues(struct nvme_dev *dev)
2079{
2080 return num_possible_cpus() + dev->nr_write_queues + dev->nr_poll_queues;
2081}
2082
8d85fce7 2083static int nvme_setup_io_queues(struct nvme_dev *dev)
b60503ba 2084{
147b27e4 2085 struct nvme_queue *adminq = &dev->queues[0];
e75ec752 2086 struct pci_dev *pdev = to_pci_dev(dev->dev);
2a5bcfdd 2087 unsigned int nr_io_queues;
97f6ef64 2088 unsigned long size;
2a5bcfdd 2089 int result;
b60503ba 2090
2a5bcfdd
WZ		 2091 /*
2092 * Sample the module parameters once at reset time so that we have
2093 * stable values to work with.
2094 */
2095 dev->nr_write_queues = write_queues;
2096 dev->nr_poll_queues = poll_queues;
d38e9f04
BH		 2097
2098 /*
2099 * If tags are shared with admin queue (Apple bug), then
2100 * make sure we only use one IO queue.
2101 */
2102 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2103 nr_io_queues = 1;
2a5bcfdd
WZ		 2104 else
2105 nr_io_queues = min(nvme_max_io_queues(dev),
2106 dev->nr_allocated_queues - 1);
d38e9f04 2107
9a0be7ab
CH		 2108 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
2109 if (result < 0)
1b23484b 2110 return result;
9a0be7ab 2111
f5fa90dc 2112 if (nr_io_queues == 0)
a5229050 2113 return 0;
4e224106
CH		 2114
2115 clear_bit(NVMEQ_ENABLED, &adminq->flags);
b60503ba 2116
0f238ff5 2117 if (dev->cmb_use_sqes) {
8ffaadf7
JD		 2118 result = nvme_cmb_qdepth(dev, nr_io_queues,
2119 sizeof(struct nvme_command));
2120 if (result > 0)
2121 dev->q_depth = result;
2122 else
0f238ff5 2123 dev->cmb_use_sqes = false;
8ffaadf7
JD		 2124 }
2125
97f6ef64
XY		 2126 do {
2127 size = db_bar_size(dev, nr_io_queues);
2128 result = nvme_remap_bar(dev, size);
2129 if (!result)
2130 break;
2131 if (!--nr_io_queues)
2132 return -ENOMEM;
2133 } while (1);
2134 adminq->q_db = dev->dbs;
f1938f6e 2135
8fae268b 2136 retry:
9d713c2b 2137 /* Deregister the admin queue's interrupt */
0ff199cb 2138 pci_free_irq(pdev, 0, adminq);
9d713c2b 2139
e32efbfc
JA		 2140 /*
2141 * If we enable msix early due to not intx, disable it again before
2142 * setting up the full range we need.
2143 */
dca51e78 2144 pci_free_irq_vectors(pdev);
3b6592f7
JA		 2145
2146 result = nvme_setup_irqs(dev, nr_io_queues);
22b55601 2147 if (result <= 0)
dca51e78 2148 return -EIO;
3b6592f7 2149
22b55601 2150 dev->num_vecs = result;
4b04cc6a 2151 result = max(result - 1, 1);
e20ba6e1 2152 dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL];
fa08a396 2153
063a8096
MW		 2154 /*
2155 * Should investigate if there's a performance win from allocating
2156 * more queues than interrupt vectors; it might allow the submission
2157 * path to scale better, even if the receive path is limited by the
2158 * number of interrupts.
2159 */
dca51e78 2160 result = queue_request_irq(adminq);
7c349dde 2161 if (result)
d4875622 2162 return result;
4e224106 2163 set_bit(NVMEQ_ENABLED, &adminq->flags);
8fae268b
KB		 2164
2165 result = nvme_create_io_queues(dev);
2166 if (result || dev->online_queues < 2)
2167 return result;
2168
2169 if (dev->online_queues - 1 < dev->max_qid) {
2170 nr_io_queues = dev->online_queues - 1;
2171 nvme_disable_io_queues(dev);
2172 nvme_suspend_io_queues(dev);
2173 goto retry;
2174 }
2175 dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n",
2176 dev->io_queues[HCTX_TYPE_DEFAULT],
2177 dev->io_queues[HCTX_TYPE_READ],
2178 dev->io_queues[HCTX_TYPE_POLL]);
2179 return 0;
b60503ba
MW		 2180}
2181
2a842aca 2182static void nvme_del_queue_end(struct request *req, blk_status_t error)
a5768aa8 2183{
db3cbfff 2184 struct nvme_queue *nvmeq = req->end_io_data;
b5875222 2185
db3cbfff 2186 blk_mq_free_request(req);
d1ed6aa1 2187 complete(&nvmeq->delete_done);
a5768aa8
KB		 2188}
2189
2a842aca 2190static void nvme_del_cq_end(struct request *req, blk_status_t error)
a5768aa8 2191{
db3cbfff 2192 struct nvme_queue *nvmeq = req->end_io_data;
a5768aa8 2193
d1ed6aa1
CH		 2194 if (error)
2195 set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
db3cbfff
KB		 2196
2197 nvme_del_queue_end(req, error);
a5768aa8
KB		 2198}
2199
db3cbfff 2200static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
bda4e0fb 2201{
db3cbfff
KB		 2202 struct request_queue *q = nvmeq->dev->ctrl.admin_q;
2203 struct request *req;
2204 struct nvme_command cmd;
bda4e0fb 2205
db3cbfff
KB		 2206 memset(&cmd, 0, sizeof(cmd));
2207 cmd.delete_queue.opcode = opcode;
2208 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
bda4e0fb 2209
eb71f435 2210 req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
db3cbfff
KB		 2211 if (IS_ERR(req))
2212 return PTR_ERR(req);
bda4e0fb 2213
db3cbfff
KB		 2214 req->timeout = ADMIN_TIMEOUT;
2215 req->end_io_data = nvmeq;
2216
d1ed6aa1 2217 init_completion(&nvmeq->delete_done);
db3cbfff
KB		 2218 blk_execute_rq_nowait(q, NULL, req, false,
2219 opcode == nvme_admin_delete_cq ?
2220 nvme_del_cq_end : nvme_del_queue_end);
2221 return 0;
bda4e0fb
KB		 2222}
2223
8fae268b 2224static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode)
a5768aa8 2225{
5271edd4 2226 int nr_queues = dev->online_queues - 1, sent = 0;
db3cbfff 2227 unsigned long timeout;
a5768aa8 2228
db3cbfff 2229 retry:
5271edd4
CH		 2230 timeout = ADMIN_TIMEOUT;
2231 while (nr_queues > 0) {
2232 if (nvme_delete_queue(&dev->queues[nr_queues], opcode))
2233 break;
2234 nr_queues--;
2235 sent++;
db3cbfff 2236 }
d1ed6aa1
CH		 2237 while (sent) {
2238 struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent];
2239
2240 timeout = wait_for_completion_io_timeout(&nvmeq->delete_done,
5271edd4
CH		 2241 timeout);
2242 if (timeout == 0)
2243 return false;
d1ed6aa1 2244
d1ed6aa1 2245 sent--;
5271edd4
CH		 2246 if (nr_queues)
2247 goto retry;
2248 }
2249 return true;
a5768aa8
KB		 2250}
2251
5d02a5c1 2252static void nvme_dev_add(struct nvme_dev *dev)
b60503ba 2253{
2b1b7e78
JW		 2254 int ret;
2255
5bae7f73 2256 if (!dev->ctrl.tagset) {
376f7ef8 2257 dev->tagset.ops = &nvme_mq_ops;
ffe7704d 2258 dev->tagset.nr_hw_queues = dev->online_queues - 1;
8fe34be1 2259 dev->tagset.nr_maps = 2; /* default + read */
ed92ad37
CH		 2260 if (dev->io_queues[HCTX_TYPE_POLL])
2261 dev->tagset.nr_maps++;
ffe7704d 2262 dev->tagset.timeout = NVME_IO_TIMEOUT;
d4ec47f1 2263 dev->tagset.numa_node = dev->ctrl.numa_node;
ffe7704d 2264 dev->tagset.queue_depth =
a4aea562 2265 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
d43f1ccf 2266 dev->tagset.cmd_size = sizeof(struct nvme_iod);
ffe7704d
KB		 2267 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2268 dev->tagset.driver_data = dev;
b60503ba 2269
d38e9f04
BH		 2270 /*
2271 * Some Apple controllers requires tags to be unique
2272 * across admin and IO queue, so reserve the first 32
2273 * tags of the IO queue.
2274 */
2275 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2276 dev->tagset.reserved_tags = NVME_AQ_DEPTH;
2277
2b1b7e78
JW		 2278 ret = blk_mq_alloc_tag_set(&dev->tagset);
2279 if (ret) {
2280 dev_warn(dev->ctrl.device,
2281 "IO queues tagset allocation failed %d\n", ret);
5d02a5c1 2282 return;
2b1b7e78 2283 }
5bae7f73 2284 dev->ctrl.tagset = &dev->tagset;
949928c1
KB		 2285 } else {
2286 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2287
2288 /* Free previously allocated queues that are no longer usable */
2289 nvme_free_queues(dev, dev->online_queues);
ffe7704d 2290 }
949928c1 2291
e8fd41bb 2292 nvme_dbbuf_set(dev);
b60503ba
MW		 2293}
2294
b00a726a 2295static int nvme_pci_enable(struct nvme_dev *dev)
0877cb0d 2296{
b00a726a 2297 int result = -ENOMEM;
e75ec752 2298 struct pci_dev *pdev = to_pci_dev(dev->dev);
0877cb0d
KB		 2299
2300 if (pci_enable_device_mem(pdev))
2301 return result;
2302
0877cb0d 2303 pci_set_master(pdev);
0877cb0d 2304
4fe06923 2305 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)))
052d0efa 2306 goto disable;
0877cb0d 2307
7a67cbea 2308 if (readl(dev->bar + NVME_REG_CSTS) == -1) {
0e53d180 2309 result = -ENODEV;
b00a726a 2310 goto disable;
0e53d180 2311 }
e32efbfc
JA		 2312
2313 /*
a5229050
KB		 2314 * Some devices and/or platforms don't advertise or work with INTx
2315 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2316 * adjust this later.
e32efbfc 2317 */
dca51e78
CH		 2318 result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
2319 if (result < 0)
2320 return result;
e32efbfc 2321
20d0dfe6 2322 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
7a67cbea 2323
20d0dfe6 2324 dev->q_depth = min_t(int, NVME_CAP_MQES(dev->ctrl.cap) + 1,
b27c1e68 2325 io_queue_depth);
aa22c8e6 2326 dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */
20d0dfe6 2327 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
7a67cbea 2328 dev->dbs = dev->bar + 4096;
1f390c1f 2329
66341331
BH		 2330 /*
2331 * Some Apple controllers require a non-standard SQE size.
2332 * Interestingly they also seem to ignore the CC:IOSQES register
2333 * so we don't bother updating it here.
2334 */
2335 if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES)
2336 dev->io_sqes = 7;
2337 else
2338 dev->io_sqes = NVME_NVM_IOSQES;
1f390c1f
SG		 2339
2340 /*
2341 * Temporary fix for the Apple controller found in the MacBook8,1 and
2342 * some MacBook7,1 to avoid controller resets and data loss.
2343 */
2344 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
2345 dev->q_depth = 2;
9bdcfb10
CH		 2346 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
2347 "set queue depth=%u to work around controller resets\n",
1f390c1f 2348 dev->q_depth);
d554b5e1
MP		 2349 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2350 (pdev->device == 0xa821 || pdev->device == 0xa822) &&
20d0dfe6 2351 NVME_CAP_MQES(dev->ctrl.cap) == 0) {
d554b5e1
MP		 2352 dev->q_depth = 64;
2353 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2354 "set queue depth=%u\n", dev->q_depth);
1f390c1f
SG		 2355 }
2356
d38e9f04
BH		 2357 /*
2358 * Controllers with the shared tags quirk need the IO queue to be
2359 * big enough so that we get 32 tags for the admin queue
2360 */
2361 if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) &&
2362 (dev->q_depth < (NVME_AQ_DEPTH + 2))) {
2363 dev->q_depth = NVME_AQ_DEPTH + 2;
2364 dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n",
2365 dev->q_depth);
2366 }
2367
2368
f65efd6d 2369 nvme_map_cmb(dev);
202021c1 2370
a0a3408e
KB		 2371 pci_enable_pcie_error_reporting(pdev);
2372 pci_save_state(pdev);
0877cb0d
KB		 2373 return 0;
2374
2375 disable:
0877cb0d
KB		 2376 pci_disable_device(pdev);
2377 return result;
2378}
2379
2380static void nvme_dev_unmap(struct nvme_dev *dev)
b00a726a
KB		 2381{
2382 if (dev->bar)
2383 iounmap(dev->bar);
a1f447b3 2384 pci_release_mem_regions(to_pci_dev(dev->dev));
b00a726a
KB		 2385}
2386
2387static void nvme_pci_disable(struct nvme_dev *dev)
0877cb0d 2388{
e75ec752
CH		 2389 struct pci_dev *pdev = to_pci_dev(dev->dev);
2390
dca51e78 2391 pci_free_irq_vectors(pdev);
0877cb0d 2392
a0a3408e
KB		 2393 if (pci_is_enabled(pdev)) {
2394 pci_disable_pcie_error_reporting(pdev);
e75ec752 2395 pci_disable_device(pdev);
4d115420 2396 }
4d115420
KB		 2397}
2398
a5cdb68c 2399static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
b60503ba 2400{
e43269e6 2401 bool dead = true, freeze = false;
302ad8cc 2402 struct pci_dev *pdev = to_pci_dev(dev->dev);
22404274 2403
77bf25ea 2404 mutex_lock(&dev->shutdown_lock);
302ad8cc
KB		 2405 if (pci_is_enabled(pdev)) {
2406 u32 csts = readl(dev->bar + NVME_REG_CSTS);
2407
ebef7368 2408 if (dev->ctrl.state == NVME_CTRL_LIVE ||
e43269e6
KB		 2409 dev->ctrl.state == NVME_CTRL_RESETTING) {
2410 freeze = true;
302ad8cc 2411 nvme_start_freeze(&dev->ctrl);
e43269e6 2412 }
302ad8cc
KB		 2413 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
2414 pdev->error_state != pci_channel_io_normal);
c9d3bf88 2415 }
c21377f8 2416
302ad8cc
KB		 2417 /*
2418 * Give the controller a chance to complete all entered requests if
2419 * doing a safe shutdown.
2420 */
e43269e6
KB		 2421 if (!dead && shutdown && freeze)
2422 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
9a915a5b
JW		 2423
2424 nvme_stop_queues(&dev->ctrl);
87ad72a5 2425
64ee0ac0 2426 if (!dead && dev->ctrl.queue_count > 0) {
8fae268b 2427 nvme_disable_io_queues(dev);
a5cdb68c 2428 nvme_disable_admin_queue(dev, shutdown);
4d115420 2429 }
8fae268b
KB		 2430 nvme_suspend_io_queues(dev);
2431 nvme_suspend_queue(&dev->queues[0]);
b00a726a 2432 nvme_pci_disable(dev);
fa46c6fb 2433 nvme_reap_pending_cqes(dev);
07836e65 2434
e1958e65
ML		 2435 blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
2436 blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
622b8b68
ML		 2437 blk_mq_tagset_wait_completed_request(&dev->tagset);
2438 blk_mq_tagset_wait_completed_request(&dev->admin_tagset);
302ad8cc
KB		 2439
2440 /*
2441 * The driver will not be starting up queues again if shutting down so
2442 * must flush all entered requests to their failed completion to avoid
2443 * deadlocking blk-mq hot-cpu notifier.
2444 */
c8e9e9b7 2445 if (shutdown) {
302ad8cc 2446 nvme_start_queues(&dev->ctrl);
c8e9e9b7
KB		 2447 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q))
2448 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
2449 }
77bf25ea 2450 mutex_unlock(&dev->shutdown_lock);
b60503ba
MW		 2451}
2452
c1ac9a4b
KB		 2453static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown)
2454{
2455 if (!nvme_wait_reset(&dev->ctrl))
2456 return -EBUSY;
2457 nvme_dev_disable(dev, shutdown);
2458 return 0;
2459}
2460
091b6092
MW		 2461static int nvme_setup_prp_pools(struct nvme_dev *dev)
2462{
e75ec752 2463 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
091b6092
MW		 2464 PAGE_SIZE, PAGE_SIZE, 0);
2465 if (!dev->prp_page_pool)
2466 return -ENOMEM;
2467
99802a7a 2468 /* Optimisation for I/Os between 4k and 128k */
e75ec752 2469 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
99802a7a
MW		 2470 256, 256, 0);
2471 if (!dev->prp_small_pool) {
2472 dma_pool_destroy(dev->prp_page_pool);
2473 return -ENOMEM;
2474 }
091b6092
MW		 2475 return 0;
2476}
2477
2478static void nvme_release_prp_pools(struct nvme_dev *dev)
2479{
2480 dma_pool_destroy(dev->prp_page_pool);
99802a7a 2481 dma_pool_destroy(dev->prp_small_pool);
091b6092
MW		 2482}
2483
770597ec
KB		 2484static void nvme_free_tagset(struct nvme_dev *dev)
2485{
2486 if (dev->tagset.tags)
2487 blk_mq_free_tag_set(&dev->tagset);
2488 dev->ctrl.tagset = NULL;
2489}
2490
1673f1f0 2491static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
5e82e952 2492{
1673f1f0 2493 struct nvme_dev *dev = to_nvme_dev(ctrl);
9ac27090 2494
f9f38e33 2495 nvme_dbbuf_dma_free(dev);
770597ec 2496 nvme_free_tagset(dev);
1c63dc66
CH		 2497 if (dev->ctrl.admin_q)
2498 blk_put_queue(dev->ctrl.admin_q);
e286bcfc 2499 free_opal_dev(dev->ctrl.opal_dev);
943e942e 2500 mempool_destroy(dev->iod_mempool);
253fd4ac
IR		 2501 put_device(dev->dev);
2502 kfree(dev->queues);
5e82e952
KB		 2503 kfree(dev);
2504}
2505
7c1ce408 2506static void nvme_remove_dead_ctrl(struct nvme_dev *dev)
f58944e2 2507{
c1ac9a4b
KB		 2508 /*
2509 * Set state to deleting now to avoid blocking nvme_wait_reset(), which
2510 * may be holding this pci_dev's device lock.
2511 */
2512 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
d22524a4 2513 nvme_get_ctrl(&dev->ctrl);
69d9a99c 2514 nvme_dev_disable(dev, false);
9f9cafc1 2515 nvme_kill_queues(&dev->ctrl);
03e0f3a6 2516 if (!queue_work(nvme_wq, &dev->remove_work))
f58944e2
KB		 2517 nvme_put_ctrl(&dev->ctrl);
2518}
2519
fd634f41 2520static void nvme_reset_work(struct work_struct *work)
5e82e952 2521{
d86c4d8e
CH		 2522 struct nvme_dev *dev =
2523 container_of(work, struct nvme_dev, ctrl.reset_work);
a98e58e5 2524 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
e71afda4 2525 int result;
5e82e952 2526
e71afda4
CK		 2527 if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING)) {
2528 result = -ENODEV;
fd634f41 2529 goto out;
e71afda4 2530 }
5e82e952 2531
fd634f41
CH		 2532 /*
2533 * If we're called to reset a live controller first shut it down before
2534 * moving on.
2535 */
b00a726a 2536 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
a5cdb68c 2537 nvme_dev_disable(dev, false);
d6135c3a 2538 nvme_sync_queues(&dev->ctrl);
5e82e952 2539
5c959d73 2540 mutex_lock(&dev->shutdown_lock);
b00a726a 2541 result = nvme_pci_enable(dev);
f0b50732 2542 if (result)
4726bcf3 2543 goto out_unlock;
f0b50732 2544
01ad0990 2545 result = nvme_pci_configure_admin_queue(dev);
f0b50732 2546 if (result)
4726bcf3 2547 goto out_unlock;
f0b50732 2548
0fb59cbc
KB		 2549 result = nvme_alloc_admin_tags(dev);
2550 if (result)
4726bcf3 2551 goto out_unlock;
b9afca3e 2552
943e942e
JA		 2553 /*
2554 * Limit the max command size to prevent iod->sg allocations going
2555 * over a single page.
2556 */
7637de31
CH		 2557 dev->ctrl.max_hw_sectors = min_t(u32,
2558 NVME_MAX_KB_SZ << 1, dma_max_mapping_size(dev->dev) >> 9);
943e942e 2559 dev->ctrl.max_segments = NVME_MAX_SEGS;
a48bc520
CH		 2560
2561 /*
2562 * Don't limit the IOMMU merged segment size.
2563 */
2564 dma_set_max_seg_size(dev->dev, 0xffffffff);
2565
5c959d73
KB		 2566 mutex_unlock(&dev->shutdown_lock);
2567
2568 /*
2569 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
2570 * initializing procedure here.
2571 */
2572 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
2573 dev_warn(dev->ctrl.device,
2574 "failed to mark controller CONNECTING\n");
cee6c269 2575 result = -EBUSY;
5c959d73
KB		 2576 goto out;
2577 }
943e942e 2578
95093350
MG		 2579 /*
2580 * We do not support an SGL for metadata (yet), so we are limited to a
2581 * single integrity segment for the separate metadata pointer.
2582 */
2583 dev->ctrl.max_integrity_segments = 1;
2584
ce4541f4
CH		 2585 result = nvme_init_identify(&dev->ctrl);
2586 if (result)
f58944e2 2587 goto out;
ce4541f4 2588
e286bcfc
SB		 2589 if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
2590 if (!dev->ctrl.opal_dev)
2591 dev->ctrl.opal_dev =
2592 init_opal_dev(&dev->ctrl, &nvme_sec_submit);
2593 else if (was_suspend)
2594 opal_unlock_from_suspend(dev->ctrl.opal_dev);
2595 } else {
2596 free_opal_dev(dev->ctrl.opal_dev);
2597 dev->ctrl.opal_dev = NULL;
4f1244c8 2598 }
a98e58e5 2599
f9f38e33
HK		 2600 if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) {
2601 result = nvme_dbbuf_dma_alloc(dev);
2602 if (result)
2603 dev_warn(dev->dev,
2604 "unable to allocate dma for dbbuf\n");
2605 }
2606
9620cfba
CH		 2607 if (dev->ctrl.hmpre) {
2608 result = nvme_setup_host_mem(dev);
2609 if (result < 0)
2610 goto out;
2611 }
87ad72a5 2612
f0b50732 2613 result = nvme_setup_io_queues(dev);
badc34d4 2614 if (result)
f58944e2 2615 goto out;
f0b50732 2616
2659e57b
CH		 2617 /*
2618 * Keep the controller around but remove all namespaces if we don't have
2619 * any working I/O queue.
2620 */
3cf519b5 2621 if (dev->online_queues < 2) {
1b3c47c1 2622 dev_warn(dev->ctrl.device, "IO queues not created\n");
3b24774e 2623 nvme_kill_queues(&dev->ctrl);
5bae7f73 2624 nvme_remove_namespaces(&dev->ctrl);
770597ec 2625 nvme_free_tagset(dev);
3cf519b5 2626 } else {
25646264 2627 nvme_start_queues(&dev->ctrl);
302ad8cc 2628 nvme_wait_freeze(&dev->ctrl);
5d02a5c1 2629 nvme_dev_add(dev);
302ad8cc 2630 nvme_unfreeze(&dev->ctrl);
3cf519b5
CH		 2631 }
2632
2b1b7e78
JW		 2633 /*
2634 * If only admin queue live, keep it to do further investigation or
2635 * recovery.
2636 */
5d02a5c1 2637 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
2b1b7e78 2638 dev_warn(dev->ctrl.device,
5d02a5c1 2639 "failed to mark controller live state\n");
e71afda4 2640 result = -ENODEV;
bb8d261e
CH		 2641 goto out;
2642 }
92911a55 2643
d09f2b45 2644 nvme_start_ctrl(&dev->ctrl);
3cf519b5 2645 return;
f0b50732 2646
4726bcf3
KB		 2647 out_unlock:
2648 mutex_unlock(&dev->shutdown_lock);
3cf519b5 2649 out:
7c1ce408
CK		 2650 if (result)
2651 dev_warn(dev->ctrl.device,
2652 "Removing after probe failure status: %d\n", result);
2653 nvme_remove_dead_ctrl(dev);
f0b50732
KB		 2654}
2655
5c8809e6 2656static void nvme_remove_dead_ctrl_work(struct work_struct *work)
9a6b9458 2657{
5c8809e6 2658 struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
e75ec752 2659 struct pci_dev *pdev = to_pci_dev(dev->dev);
9a6b9458
KB		 2660
2661 if (pci_get_drvdata(pdev))
921920ab 2662 device_release_driver(&pdev->dev);
1673f1f0 2663 nvme_put_ctrl(&dev->ctrl);
9a6b9458
KB		 2664}
2665
1c63dc66 2666static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
9ca97374 2667{
1c63dc66 2668 *val = readl(to_nvme_dev(ctrl)->bar + off);
90667892 2669 return 0;
9ca97374
TH		 2670}
2671
5fd4ce1b 2672static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
4cc06521 2673{
5fd4ce1b
CH		 2674 writel(val, to_nvme_dev(ctrl)->bar + off);
2675 return 0;
2676}
4cc06521 2677
7fd8930f
CH		 2678static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2679{
3a8ecc93 2680 *val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off);
7fd8930f 2681 return 0;
4cc06521
KB		 2682}
2683
97c12223
KB		 2684static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
2685{
2686 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2687
2db24e4a 2688 return snprintf(buf, size, "%s\n", dev_name(&pdev->dev));
97c12223
KB		 2689}
2690
1c63dc66 2691static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
1a353d85 2692 .name = "pcie",
e439bb12 2693 .module = THIS_MODULE,
e0596ab2
LG		 2694 .flags = NVME_F_METADATA_SUPPORTED |
2695 NVME_F_PCI_P2PDMA,
1c63dc66 2696 .reg_read32 = nvme_pci_reg_read32,
5fd4ce1b 2697 .reg_write32 = nvme_pci_reg_write32,
7fd8930f 2698 .reg_read64 = nvme_pci_reg_read64,
1673f1f0 2699 .free_ctrl = nvme_pci_free_ctrl,
f866fc42 2700 .submit_async_event = nvme_pci_submit_async_event,
97c12223 2701 .get_address = nvme_pci_get_address,
1c63dc66 2702};
4cc06521 2703
b00a726a
KB		 2704static int nvme_dev_map(struct nvme_dev *dev)
2705{
b00a726a
KB		 2706 struct pci_dev *pdev = to_pci_dev(dev->dev);
2707
a1f447b3 2708 if (pci_request_mem_regions(pdev, "nvme"))
b00a726a
KB		 2709 return -ENODEV;
2710
97f6ef64 2711 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
b00a726a
KB		 2712 goto release;
2713
9fa196e7 2714 return 0;
b00a726a 2715 release:
9fa196e7
MG		 2716 pci_release_mem_regions(pdev);
2717 return -ENODEV;
b00a726a
KB		 2718}
2719
8427bbc2 2720static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
ff5350a8
AL		 2721{
2722 if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
2723 /*
2724 * Several Samsung devices seem to drop off the PCIe bus
2725 * randomly when APST is on and uses the deepest sleep state.
2726 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2727 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2728 * 950 PRO 256GB", but it seems to be restricted to two Dell
2729 * laptops.
2730 */
2731 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
2732 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
2733 dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
2734 return NVME_QUIRK_NO_DEEPEST_PS;
8427bbc2
KHF		 2735 } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
2736 /*
2737 * Samsung SSD 960 EVO drops off the PCIe bus after system
467c77d4
JJ		 2738 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
2739 * within few minutes after bootup on a Coffee Lake board -
2740 * ASUS PRIME Z370-A
8427bbc2
KHF		 2741 */
2742 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
467c77d4
JJ		 2743 (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") ||
2744 dmi_match(DMI_BOARD_NAME, "PRIME Z370-A")))
8427bbc2 2745 return NVME_QUIRK_NO_APST;
1fae37ac
S		 2746 } else if ((pdev->vendor == 0x144d && (pdev->device == 0xa801 ||
2747 pdev->device == 0xa808 || pdev->device == 0xa809)) ||
2748 (pdev->vendor == 0x1e0f && pdev->device == 0x0001)) {
2749 /*
2750 * Forcing to use host managed nvme power settings for
2751 * lowest idle power with quick resume latency on
2752 * Samsung and Toshiba SSDs based on suspend behavior
2753 * on Coffee Lake board for LENOVO C640
2754 */
2755 if ((dmi_match(DMI_BOARD_VENDOR, "LENOVO")) &&
2756 dmi_match(DMI_BOARD_NAME, "LNVNB161216"))
2757 return NVME_QUIRK_SIMPLE_SUSPEND;
ff5350a8
AL		 2758 }
2759
2760 return 0;
2761}
2762
18119775
KB		 2763static void nvme_async_probe(void *data, async_cookie_t cookie)
2764{
2765 struct nvme_dev *dev = data;
80f513b5 2766
bd46a906 2767 flush_work(&dev->ctrl.reset_work);
18119775 2768 flush_work(&dev->ctrl.scan_work);
80f513b5 2769 nvme_put_ctrl(&dev->ctrl);
18119775
KB		 2770}
2771
8d85fce7 2772static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
b60503ba 2773{
a4aea562 2774 int node, result = -ENOMEM;
b60503ba 2775 struct nvme_dev *dev;
ff5350a8 2776 unsigned long quirks = id->driver_data;
943e942e 2777 size_t alloc_size;
b60503ba 2778
a4aea562
MB		 2779 node = dev_to_node(&pdev->dev);
2780 if (node == NUMA_NO_NODE)
2fa84351 2781 set_dev_node(&pdev->dev, first_memory_node);
a4aea562
MB		 2782
2783 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
b60503ba
MW		 2784 if (!dev)
2785 return -ENOMEM;
147b27e4 2786
2a5bcfdd
WZ		 2787 dev->nr_write_queues = write_queues;
2788 dev->nr_poll_queues = poll_queues;
2789 dev->nr_allocated_queues = nvme_max_io_queues(dev) + 1;
2790 dev->queues = kcalloc_node(dev->nr_allocated_queues,
2791 sizeof(struct nvme_queue), GFP_KERNEL, node);
b60503ba
MW		 2792 if (!dev->queues)
2793 goto free;
2794
e75ec752 2795 dev->dev = get_device(&pdev->dev);
9a6b9458 2796 pci_set_drvdata(pdev, dev);
1c63dc66 2797
b00a726a
KB		 2798 result = nvme_dev_map(dev);
2799 if (result)
b00c9b7a 2800 goto put_pci;
b00a726a 2801
d86c4d8e 2802 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
5c8809e6 2803 INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
77bf25ea 2804 mutex_init(&dev->shutdown_lock);
b60503ba 2805
091b6092
MW		 2806 result = nvme_setup_prp_pools(dev);
2807 if (result)
b00c9b7a 2808 goto unmap;
4cc06521 2809
8427bbc2 2810 quirks |= check_vendor_combination_bug(pdev);
ff5350a8 2811
943e942e
JA		 2812 /*
2813 * Double check that our mempool alloc size will cover the biggest
2814 * command we support.
2815 */
2816 alloc_size = nvme_pci_iod_alloc_size(dev, NVME_MAX_KB_SZ,
2817 NVME_MAX_SEGS, true);
2818 WARN_ON_ONCE(alloc_size > PAGE_SIZE);
2819
2820 dev->iod_mempool = mempool_create_node(1, mempool_kmalloc,
2821 mempool_kfree,
2822 (void *) alloc_size,
2823 GFP_KERNEL, node);
2824 if (!dev->iod_mempool) {
2825 result = -ENOMEM;
2826 goto release_pools;
2827 }
2828
b6e44b4c
KB		 2829 result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
2830 quirks);
2831 if (result)
2832 goto release_mempool;
2833
1b3c47c1
SG		 2834 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
2835
bd46a906 2836 nvme_reset_ctrl(&dev->ctrl);
18119775 2837 async_schedule(nvme_async_probe, dev);
4caff8fc 2838
b60503ba
MW		 2839 return 0;
2840
b6e44b4c
KB		 2841 release_mempool:
2842 mempool_destroy(dev->iod_mempool);
0877cb0d 2843 release_pools:
091b6092 2844 nvme_release_prp_pools(dev);
b00c9b7a
CJ		 2845 unmap:
2846 nvme_dev_unmap(dev);
a96d4f5c 2847 put_pci:
e75ec752 2848 put_device(dev->dev);
b60503ba
MW		 2849 free:
2850 kfree(dev->queues);
b60503ba
MW		 2851 kfree(dev);
2852 return result;
2853}
2854
775755ed 2855static void nvme_reset_prepare(struct pci_dev *pdev)
f0d54a54 2856{
a6739479 2857 struct nvme_dev *dev = pci_get_drvdata(pdev);
c1ac9a4b
KB		 2858
2859 /*
2860 * We don't need to check the return value from waiting for the reset
2861 * state as pci_dev device lock is held, making it impossible to race
2862 * with ->remove().
2863 */
2864 nvme_disable_prepare_reset(dev, false);
2865 nvme_sync_queues(&dev->ctrl);
775755ed 2866}
f0d54a54 2867
775755ed
CH		 2868static void nvme_reset_done(struct pci_dev *pdev)
2869{
f263fbb8 2870 struct nvme_dev *dev = pci_get_drvdata(pdev);
c1ac9a4b
KB		 2871
2872 if (!nvme_try_sched_reset(&dev->ctrl))
2873 flush_work(&dev->ctrl.reset_work);
f0d54a54
KB		 2874}
2875
09ece142
KB		 2876static void nvme_shutdown(struct pci_dev *pdev)
2877{
2878 struct nvme_dev *dev = pci_get_drvdata(pdev);
c1ac9a4b 2879 nvme_disable_prepare_reset(dev, true);
09ece142
KB		 2880}
2881
f58944e2
KB		 2882/*
2883 * The driver's remove may be called on a device in a partially initialized
2884 * state. This function must not have any dependencies on the device state in
2885 * order to proceed.
2886 */
8d85fce7 2887static void nvme_remove(struct pci_dev *pdev)
b60503ba
MW		 2888{
2889 struct nvme_dev *dev = pci_get_drvdata(pdev);
9a6b9458 2890
bb8d261e 2891 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
9a6b9458 2892 pci_set_drvdata(pdev, NULL);
0ff9d4e1 2893
6db28eda 2894 if (!pci_device_is_present(pdev)) {
0ff9d4e1 2895 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
1d39e692 2896 nvme_dev_disable(dev, true);
cb4bfda6 2897 nvme_dev_remove_admin(dev);
6db28eda 2898 }
0ff9d4e1 2899
d86c4d8e 2900 flush_work(&dev->ctrl.reset_work);
d09f2b45
SG		 2901 nvme_stop_ctrl(&dev->ctrl);
2902 nvme_remove_namespaces(&dev->ctrl);
a5cdb68c 2903 nvme_dev_disable(dev, true);
9fe5c59f 2904 nvme_release_cmb(dev);
87ad72a5 2905 nvme_free_host_mem(dev);
a4aea562 2906 nvme_dev_remove_admin(dev);
a1a5ef99 2907 nvme_free_queues(dev, 0);
9a6b9458 2908 nvme_release_prp_pools(dev);
b00a726a 2909 nvme_dev_unmap(dev);
726612b6 2910 nvme_uninit_ctrl(&dev->ctrl);
b60503ba
MW		 2911}
2912
671a6018 2913#ifdef CONFIG_PM_SLEEP
d916b1be
KB		 2914static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps)
2915{
2916 return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps);
2917}
2918
2919static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps)
2920{
2921 return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL);
2922}
2923
2924static int nvme_resume(struct device *dev)
2925{
2926 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
2927 struct nvme_ctrl *ctrl = &ndev->ctrl;
2928
4eaefe8c 2929 if (ndev->last_ps == U32_MAX ||
d916b1be 2930 nvme_set_power_state(ctrl, ndev->last_ps) != 0)
c1ac9a4b 2931 return nvme_try_sched_reset(&ndev->ctrl);
d916b1be
KB		 2932 return 0;
2933}
2934
cd638946
KB		 2935static int nvme_suspend(struct device *dev)
2936{
2937 struct pci_dev *pdev = to_pci_dev(dev);
2938 struct nvme_dev *ndev = pci_get_drvdata(pdev);
d916b1be
KB		 2939 struct nvme_ctrl *ctrl = &ndev->ctrl;
2940 int ret = -EBUSY;
2941
4eaefe8c
RW		 2942 ndev->last_ps = U32_MAX;
2943
d916b1be
KB		 2944 /*
2945 * The platform does not remove power for a kernel managed suspend so
2946 * use host managed nvme power settings for lowest idle power if
2947 * possible. This should have quicker resume latency than a full device
2948 * shutdown. But if the firmware is involved after the suspend or the
2949 * device does not support any non-default power states, shut down the
2950 * device fully.
4eaefe8c
RW		 2951 *
2952 * If ASPM is not enabled for the device, shut down the device and allow
2953 * the PCI bus layer to put it into D3 in order to take the PCIe link
2954 * down, so as to allow the platform to achieve its minimum low-power
2955 * state (which may not be possible if the link is up).
b97120b1
CH		 2956 *
2957 * If a host memory buffer is enabled, shut down the device as the NVMe
2958 * specification allows the device to access the host memory buffer in
2959 * host DRAM from all power states, but hosts will fail access to DRAM
2960 * during S3.
d916b1be 2961 */
4eaefe8c 2962 if (pm_suspend_via_firmware() || !ctrl->npss ||
cb32de1b 2963 !pcie_aspm_enabled(pdev) ||
b97120b1 2964 ndev->nr_host_mem_descs ||
c1ac9a4b
KB		 2965 (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND))
2966 return nvme_disable_prepare_reset(ndev, true);
d916b1be
KB		 2967
2968 nvme_start_freeze(ctrl);
2969 nvme_wait_freeze(ctrl);
2970 nvme_sync_queues(ctrl);
2971
5d02a5c1 2972 if (ctrl->state != NVME_CTRL_LIVE)
d916b1be
KB		 2973 goto unfreeze;
2974
d916b1be
KB		 2975 ret = nvme_get_power_state(ctrl, &ndev->last_ps);
2976 if (ret < 0)
2977 goto unfreeze;
2978
7cbb5c6f
ML		 2979 /*
2980 * A saved state prevents pci pm from generically controlling the
2981 * device's power. If we're using protocol specific settings, we don't
2982 * want pci interfering.
2983 */
2984 pci_save_state(pdev);
2985
d916b1be
KB		 2986 ret = nvme_set_power_state(ctrl, ctrl->npss);
2987 if (ret < 0)
2988 goto unfreeze;
2989
2990 if (ret) {
7cbb5c6f
ML		 2991 /* discard the saved state */
2992 pci_load_saved_state(pdev, NULL);
2993
d916b1be
KB		 2994 /*
2995 * Clearing npss forces a controller reset on resume. The
05d3046f 2996 * correct value will be rediscovered then.
d916b1be 2997 */
c1ac9a4b 2998 ret = nvme_disable_prepare_reset(ndev, true);
d916b1be 2999 ctrl->npss = 0;
d916b1be 3000 }
d916b1be
KB		 3001unfreeze:
3002 nvme_unfreeze(ctrl);
3003 return ret;
3004}
3005
3006static int nvme_simple_suspend(struct device *dev)
3007{
3008 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
c1ac9a4b 3009 return nvme_disable_prepare_reset(ndev, true);
cd638946
KB		 3010}
3011
d916b1be 3012static int nvme_simple_resume(struct device *dev)
cd638946
KB		 3013{
3014 struct pci_dev *pdev = to_pci_dev(dev);
3015 struct nvme_dev *ndev = pci_get_drvdata(pdev);
cd638946 3016
c1ac9a4b 3017 return nvme_try_sched_reset(&ndev->ctrl);
cd638946
KB		 3018}
3019
21774222 3020static const struct dev_pm_ops nvme_dev_pm_ops = {
d916b1be
KB		 3021 .suspend = nvme_suspend,
3022 .resume = nvme_resume,
3023 .freeze = nvme_simple_suspend,
3024 .thaw = nvme_simple_resume,
3025 .poweroff = nvme_simple_suspend,
3026 .restore = nvme_simple_resume,
3027};
3028#endif /* CONFIG_PM_SLEEP */
b60503ba 3029
a0a3408e
KB		 3030static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
3031 pci_channel_state_t state)
3032{
3033 struct nvme_dev *dev = pci_get_drvdata(pdev);
3034
3035 /*
3036 * A frozen channel requires a reset. When detected, this method will
3037 * shutdown the controller to quiesce. The controller will be restarted
3038 * after the slot reset through driver's slot_reset callback.
3039 */
a0a3408e
KB		 3040 switch (state) {
3041 case pci_channel_io_normal:
3042 return PCI_ERS_RESULT_CAN_RECOVER;
3043 case pci_channel_io_frozen:
d011fb31
KB		 3044 dev_warn(dev->ctrl.device,
3045 "frozen state error detected, reset controller\n");
a5cdb68c 3046 nvme_dev_disable(dev, false);
a0a3408e
KB		 3047 return PCI_ERS_RESULT_NEED_RESET;
3048 case pci_channel_io_perm_failure:
d011fb31
KB		 3049 dev_warn(dev->ctrl.device,
3050 "failure state error detected, request disconnect\n");
a0a3408e
KB		 3051 return PCI_ERS_RESULT_DISCONNECT;
3052 }
3053 return PCI_ERS_RESULT_NEED_RESET;
3054}
3055
3056static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
3057{
3058 struct nvme_dev *dev = pci_get_drvdata(pdev);
3059
1b3c47c1 3060 dev_info(dev->ctrl.device, "restart after slot reset\n");
a0a3408e 3061 pci_restore_state(pdev);
d86c4d8e 3062 nvme_reset_ctrl(&dev->ctrl);
a0a3408e
KB		 3063 return PCI_ERS_RESULT_RECOVERED;
3064}
3065
3066static void nvme_error_resume(struct pci_dev *pdev)
3067{
72cd4cc2
KB		 3068 struct nvme_dev *dev = pci_get_drvdata(pdev);
3069
3070 flush_work(&dev->ctrl.reset_work);
a0a3408e
KB		 3071}
3072
1d352035 3073static const struct pci_error_handlers nvme_err_handler = {
b60503ba 3074 .error_detected = nvme_error_detected,
b60503ba
MW		 3075 .slot_reset = nvme_slot_reset,
3076 .resume = nvme_error_resume,
775755ed
CH		 3077 .reset_prepare = nvme_reset_prepare,
3078 .reset_done = nvme_reset_done,
b60503ba
MW		 3079};
3080
6eb0d698 3081static const struct pci_device_id nvme_id_table[] = {
106198ed 3082 { PCI_VDEVICE(INTEL, 0x0953),
08095e70 3083 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 3084 NVME_QUIRK_DEALLOCATE_ZEROES, },
99466e70
KB		 3085 { PCI_VDEVICE(INTEL, 0x0a53),
3086 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 3087 NVME_QUIRK_DEALLOCATE_ZEROES, },
99466e70
KB		 3088 { PCI_VDEVICE(INTEL, 0x0a54),
3089 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 3090 NVME_QUIRK_DEALLOCATE_ZEROES, },
f99cb7af
DWF		 3091 { PCI_VDEVICE(INTEL, 0x0a55),
3092 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3093 NVME_QUIRK_DEALLOCATE_ZEROES, },
50af47d0 3094 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */
9abd68ef 3095 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
6c6aa2f2
AM		 3096 NVME_QUIRK_MEDIUM_PRIO_SQ |
3097 NVME_QUIRK_NO_TEMP_THRESH_CHANGE },
6299358d
JD		 3098 { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */
3099 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
540c801c 3100 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */
7b210e4e
CH		 3101 .driver_data = NVME_QUIRK_IDENTIFY_CNS |
3102 NVME_QUIRK_DISABLE_WRITE_ZEROES, },
0302ae60
MP		 3103 { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */
3104 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
54adc010
GP		 3105 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
3106 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
8c97eecc
JL		 3107 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */
3108 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
015282c9
WW		 3109 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
3110 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
d554b5e1
MP		 3111 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */
3112 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3113 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */
3114 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
608cc4b1
CH		 3115 { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */
3116 .driver_data = NVME_QUIRK_LIGHTNVM, },
3117 { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */
3118 .driver_data = NVME_QUIRK_LIGHTNVM, },
ea48e877
WX		 3119 { PCI_DEVICE(0x1d1d, 0x2601), /* CNEX Granby */
3120 .driver_data = NVME_QUIRK_LIGHTNVM, },
08b903b5
MN		 3121 { PCI_DEVICE(0x10ec, 0x5762), /* ADATA SX6000LNP */
3122 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
f03e42c6
GC		 3123 { PCI_DEVICE(0x1cc1, 0x8201), /* ADATA SX8200PNP 512GB */
3124 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3125 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
b60503ba 3126 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
98f7b86a
AS		 3127 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001),
3128 .driver_data = NVME_QUIRK_SINGLE_VECTOR },
124298bd 3129 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
66341331
BH		 3130 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005),
3131 .driver_data = NVME_QUIRK_SINGLE_VECTOR |
d38e9f04
BH		 3132 NVME_QUIRK_128_BYTES_SQES |
3133 NVME_QUIRK_SHARED_TAGS },
b60503ba
MW		 3134 { 0, }
3135};
3136MODULE_DEVICE_TABLE(pci, nvme_id_table);
3137
3138static struct pci_driver nvme_driver = {
3139 .name = "nvme",
3140 .id_table = nvme_id_table,
3141 .probe = nvme_probe,
8d85fce7 3142 .remove = nvme_remove,
09ece142 3143 .shutdown = nvme_shutdown,
d916b1be 3144#ifdef CONFIG_PM_SLEEP
cd638946
KB		 3145 .driver = {
3146 .pm = &nvme_dev_pm_ops,
3147 },
d916b1be 3148#endif
74d986ab 3149 .sriov_configure = pci_sriov_configure_simple,
b60503ba
MW		 3150 .err_handler = &nvme_err_handler,
3151};
3152
3153static int __init nvme_init(void)
3154{
81101540
CH		 3155 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
3156 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
3157 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
612b7286 3158 BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2);
17c33167 3159
9a6327d2 3160 return pci_register_driver(&nvme_driver);
b60503ba
MW		 3161}
3162
3163static void __exit nvme_exit(void)
3164{
3165 pci_unregister_driver(&nvme_driver);
03e0f3a6 3166 flush_workqueue(nvme_wq);
b60503ba
MW		 3167}
3168
3169MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3170MODULE_LICENSE("GPL");
c78b4713 3171MODULE_VERSION("1.0");
b60503ba
MW		 3172module_init(nvme_init);
3173module_exit(nvme_exit);
Linux 6.x block layer and io_uring tree(s)