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nvme-pci: move ->cq_vector == -1 check outside of ->q_lock
[linux-2.6-block.git] / drivers / nvme / host / pci.c
CommitLineData
b60503ba
MW		 1/*
2 * NVM Express device driver
6eb0d698 3 * Copyright (c) 2011-2014, Intel Corporation.
b60503ba
MW		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
b60503ba
MW		 13 */
14
a0a3408e 15#include <linux/aer.h>
18119775 16#include <linux/async.h>
b60503ba 17#include <linux/blkdev.h>
a4aea562 18#include <linux/blk-mq.h>
dca51e78 19#include <linux/blk-mq-pci.h>
ff5350a8 20#include <linux/dmi.h>
b60503ba
MW		 21#include <linux/init.h>
22#include <linux/interrupt.h>
23#include <linux/io.h>
b60503ba
MW		 24#include <linux/mm.h>
25#include <linux/module.h>
77bf25ea 26#include <linux/mutex.h>
d0877473 27#include <linux/once.h>
b60503ba 28#include <linux/pci.h>
e1e5e564 29#include <linux/t10-pi.h>
b60503ba 30#include <linux/types.h>
2f8e2c87 31#include <linux/io-64-nonatomic-lo-hi.h>
a98e58e5 32#include <linux/sed-opal.h>
797a796a 33
f11bb3e2
CH		 34#include "nvme.h"
35
b60503ba
MW		 36#define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
37#define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
c965809c 38
a7a7cbe3 39#define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc))
9d43cf64 40
58ffacb5
MW		 41static int use_threaded_interrupts;
42module_param(use_threaded_interrupts, int, 0);
43
8ffaadf7
JD		 44static bool use_cmb_sqes = true;
45module_param(use_cmb_sqes, bool, 0644);
46MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
47
87ad72a5
CH		 48static unsigned int max_host_mem_size_mb = 128;
49module_param(max_host_mem_size_mb, uint, 0444);
50MODULE_PARM_DESC(max_host_mem_size_mb,
51 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
1fa6aead 52
a7a7cbe3
CK		 53static unsigned int sgl_threshold = SZ_32K;
54module_param(sgl_threshold, uint, 0644);
55MODULE_PARM_DESC(sgl_threshold,
56 "Use SGLs when average request segment size is larger or equal to "
57 "this size. Use 0 to disable SGLs.");
58
b27c1e68 59static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
60static const struct kernel_param_ops io_queue_depth_ops = {
61 .set = io_queue_depth_set,
62 .get = param_get_int,
63};
64
65static int io_queue_depth = 1024;
66module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
67MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2");
68
1c63dc66
CH		 69struct nvme_dev;
70struct nvme_queue;
b3fffdef 71
a5cdb68c 72static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
d4b4ff8e 73
1c63dc66
CH		 74/*
75 * Represents an NVM Express device. Each nvme_dev is a PCI function.
76 */
77struct nvme_dev {
147b27e4 78 struct nvme_queue *queues;
1c63dc66
CH		 79 struct blk_mq_tag_set tagset;
80 struct blk_mq_tag_set admin_tagset;
81 u32 __iomem *dbs;
82 struct device *dev;
83 struct dma_pool *prp_page_pool;
84 struct dma_pool *prp_small_pool;
1c63dc66
CH		 85 unsigned online_queues;
86 unsigned max_qid;
22b55601 87 unsigned int num_vecs;
1c63dc66
CH		 88 int q_depth;
89 u32 db_stride;
1c63dc66 90 void __iomem *bar;
97f6ef64 91 unsigned long bar_mapped_size;
5c8809e6 92 struct work_struct remove_work;
77bf25ea 93 struct mutex shutdown_lock;
1c63dc66 94 bool subsystem;
1c63dc66 95 void __iomem *cmb;
8969f1f8 96 pci_bus_addr_t cmb_bus_addr;
1c63dc66
CH		 97 u64 cmb_size;
98 u32 cmbsz;
202021c1 99 u32 cmbloc;
1c63dc66 100 struct nvme_ctrl ctrl;
db3cbfff 101 struct completion ioq_wait;
87ad72a5
CH		 102
103 /* shadow doorbell buffer support: */
f9f38e33
HK		 104 u32 *dbbuf_dbs;
105 dma_addr_t dbbuf_dbs_dma_addr;
106 u32 *dbbuf_eis;
107 dma_addr_t dbbuf_eis_dma_addr;
87ad72a5
CH		 108
109 /* host memory buffer support: */
110 u64 host_mem_size;
111 u32 nr_host_mem_descs;
4033f35d 112 dma_addr_t host_mem_descs_dma;
87ad72a5
CH		 113 struct nvme_host_mem_buf_desc *host_mem_descs;
114 void **host_mem_desc_bufs;
4d115420 115};
1fa6aead 116
b27c1e68 117static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
118{
119 int n = 0, ret;
120
121 ret = kstrtoint(val, 10, &n);
122 if (ret != 0 || n < 2)
123 return -EINVAL;
124
125 return param_set_int(val, kp);
126}
127
f9f38e33
HK		 128static inline unsigned int sq_idx(unsigned int qid, u32 stride)
129{
130 return qid * 2 * stride;
131}
132
133static inline unsigned int cq_idx(unsigned int qid, u32 stride)
134{
135 return (qid * 2 + 1) * stride;
136}
137
1c63dc66
CH		 138static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
139{
140 return container_of(ctrl, struct nvme_dev, ctrl);
141}
142
b60503ba
MW		 143/*
144 * An NVM Express queue. Each device has at least two (one for admin
145 * commands and one for I/O commands).
146 */
147struct nvme_queue {
148 struct device *q_dmadev;
091b6092 149 struct nvme_dev *dev;
b60503ba
MW		 150 spinlock_t q_lock;
151 struct nvme_command *sq_cmds;
8ffaadf7 152 struct nvme_command __iomem *sq_cmds_io;
b60503ba 153 volatile struct nvme_completion *cqes;
42483228 154 struct blk_mq_tags **tags;
b60503ba
MW		 155 dma_addr_t sq_dma_addr;
156 dma_addr_t cq_dma_addr;
b60503ba
MW		 157 u32 __iomem *q_db;
158 u16 q_depth;
6222d172 159 s16 cq_vector;
b60503ba
MW		 160 u16 sq_tail;
161 u16 cq_head;
c30341dc 162 u16 qid;
e9539f47
MW		 163 u8 cq_phase;
164 u8 cqe_seen;
f9f38e33
HK		 165 u32 *dbbuf_sq_db;
166 u32 *dbbuf_cq_db;
167 u32 *dbbuf_sq_ei;
168 u32 *dbbuf_cq_ei;
b60503ba
MW		 169};
170
71bd150c
CH		 171/*
172 * The nvme_iod describes the data in an I/O, including the list of PRP
173 * entries. You can't see it in this data structure because C doesn't let
f4800d6d 174 * me express that. Use nvme_init_iod to ensure there's enough space
71bd150c
CH		 175 * allocated to store the PRP list.
176 */
177struct nvme_iod {
d49187e9 178 struct nvme_request req;
f4800d6d 179 struct nvme_queue *nvmeq;
a7a7cbe3 180 bool use_sgl;
f4800d6d 181 int aborted;
71bd150c 182 int npages; /* In the PRP list. 0 means small pool in use */
71bd150c
CH		 183 int nents; /* Used in scatterlist */
184 int length; /* Of data, in bytes */
185 dma_addr_t first_dma;
bf684057 186 struct scatterlist meta_sg; /* metadata requires single contiguous buffer */
f4800d6d
CH		 187 struct scatterlist *sg;
188 struct scatterlist inline_sg[0];
b60503ba
MW		 189};
190
191/*
192 * Check we didin't inadvertently grow the command struct
193 */
194static inline void _nvme_check_size(void)
195{
196 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
197 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
198 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
199 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
200 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
f8ebf840 201 BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
c30341dc 202 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
b60503ba 203 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
0add5e8e
JT		 204 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != NVME_IDENTIFY_DATA_SIZE);
205 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != NVME_IDENTIFY_DATA_SIZE);
b60503ba 206 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
6ecec745 207 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
f9f38e33
HK		 208 BUILD_BUG_ON(sizeof(struct nvme_dbbuf) != 64);
209}
210
211static inline unsigned int nvme_dbbuf_size(u32 stride)
212{
213 return ((num_possible_cpus() + 1) * 8 * stride);
214}
215
216static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
217{
218 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
219
220 if (dev->dbbuf_dbs)
221 return 0;
222
223 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
224 &dev->dbbuf_dbs_dma_addr,
225 GFP_KERNEL);
226 if (!dev->dbbuf_dbs)
227 return -ENOMEM;
228 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
229 &dev->dbbuf_eis_dma_addr,
230 GFP_KERNEL);
231 if (!dev->dbbuf_eis) {
232 dma_free_coherent(dev->dev, mem_size,
233 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
234 dev->dbbuf_dbs = NULL;
235 return -ENOMEM;
236 }
237
238 return 0;
239}
240
241static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
242{
243 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
244
245 if (dev->dbbuf_dbs) {
246 dma_free_coherent(dev->dev, mem_size,
247 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
248 dev->dbbuf_dbs = NULL;
249 }
250 if (dev->dbbuf_eis) {
251 dma_free_coherent(dev->dev, mem_size,
252 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
253 dev->dbbuf_eis = NULL;
254 }
255}
256
257static void nvme_dbbuf_init(struct nvme_dev *dev,
258 struct nvme_queue *nvmeq, int qid)
259{
260 if (!dev->dbbuf_dbs || !qid)
261 return;
262
263 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
264 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
265 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
266 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
267}
268
269static void nvme_dbbuf_set(struct nvme_dev *dev)
270{
271 struct nvme_command c;
272
273 if (!dev->dbbuf_dbs)
274 return;
275
276 memset(&c, 0, sizeof(c));
277 c.dbbuf.opcode = nvme_admin_dbbuf;
278 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
279 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
280
281 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
9bdcfb10 282 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
f9f38e33
HK		 283 /* Free memory and continue on */
284 nvme_dbbuf_dma_free(dev);
285 }
286}
287
288static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
289{
290 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
291}
292
293/* Update dbbuf and return true if an MMIO is required */
294static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
295 volatile u32 *dbbuf_ei)
296{
297 if (dbbuf_db) {
298 u16 old_value;
299
300 /*
301 * Ensure that the queue is written before updating
302 * the doorbell in memory
303 */
304 wmb();
305
306 old_value = *dbbuf_db;
307 *dbbuf_db = value;
308
309 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value))
310 return false;
311 }
312
313 return true;
b60503ba
MW		 314}
315
ac3dd5bd
JA		 316/*
317 * Max size of iod being embedded in the request payload
318 */
319#define NVME_INT_PAGES 2
5fd4ce1b 320#define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size)
ac3dd5bd
JA		 321
322/*
323 * Will slightly overestimate the number of pages needed. This is OK
324 * as it only leads to a small amount of wasted memory for the lifetime of
325 * the I/O.
326 */
327static int nvme_npages(unsigned size, struct nvme_dev *dev)
328{
5fd4ce1b
CH		 329 unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size,
330 dev->ctrl.page_size);
ac3dd5bd
JA		 331 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
332}
333
a7a7cbe3
CK		 334/*
335 * Calculates the number of pages needed for the SGL segments. For example a 4k
336 * page can accommodate 256 SGL descriptors.
337 */
338static int nvme_pci_npages_sgl(unsigned int num_seg)
ac3dd5bd 339{
a7a7cbe3 340 return DIV_ROUND_UP(num_seg * sizeof(struct nvme_sgl_desc), PAGE_SIZE);
f4800d6d 341}
ac3dd5bd 342
a7a7cbe3
CK		 343static unsigned int nvme_pci_iod_alloc_size(struct nvme_dev *dev,
344 unsigned int size, unsigned int nseg, bool use_sgl)
f4800d6d 345{
a7a7cbe3
CK		 346 size_t alloc_size;
347
348 if (use_sgl)
349 alloc_size = sizeof(__le64 *) * nvme_pci_npages_sgl(nseg);
350 else
351 alloc_size = sizeof(__le64 *) * nvme_npages(size, dev);
352
353 return alloc_size + sizeof(struct scatterlist) * nseg;
f4800d6d 354}
ac3dd5bd 355
a7a7cbe3 356static unsigned int nvme_pci_cmd_size(struct nvme_dev *dev, bool use_sgl)
f4800d6d 357{
a7a7cbe3
CK		 358 unsigned int alloc_size = nvme_pci_iod_alloc_size(dev,
359 NVME_INT_BYTES(dev), NVME_INT_PAGES,
360 use_sgl);
361
362 return sizeof(struct nvme_iod) + alloc_size;
ac3dd5bd
JA		 363}
364
a4aea562
MB		 365static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
366 unsigned int hctx_idx)
e85248e5 367{
a4aea562 368 struct nvme_dev *dev = data;
147b27e4 369 struct nvme_queue *nvmeq = &dev->queues[0];
a4aea562 370
42483228
KB		 371 WARN_ON(hctx_idx != 0);
372 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
373 WARN_ON(nvmeq->tags);
374
a4aea562 375 hctx->driver_data = nvmeq;
42483228 376 nvmeq->tags = &dev->admin_tagset.tags[0];
a4aea562 377 return 0;
e85248e5
MW		 378}
379
4af0e21c
KB		 380static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
381{
382 struct nvme_queue *nvmeq = hctx->driver_data;
383
384 nvmeq->tags = NULL;
385}
386
a4aea562
MB		 387static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
388 unsigned int hctx_idx)
b60503ba 389{
a4aea562 390 struct nvme_dev *dev = data;
147b27e4 391 struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
a4aea562 392
42483228
KB		 393 if (!nvmeq->tags)
394 nvmeq->tags = &dev->tagset.tags[hctx_idx];
b60503ba 395
42483228 396 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
a4aea562
MB		 397 hctx->driver_data = nvmeq;
398 return 0;
b60503ba
MW		 399}
400
d6296d39
CH		 401static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req,
402 unsigned int hctx_idx, unsigned int numa_node)
b60503ba 403{
d6296d39 404 struct nvme_dev *dev = set->driver_data;
f4800d6d 405 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
0350815a 406 int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0;
147b27e4 407 struct nvme_queue *nvmeq = &dev->queues[queue_idx];
a4aea562
MB		 408
409 BUG_ON(!nvmeq);
f4800d6d 410 iod->nvmeq = nvmeq;
a4aea562
MB		 411 return 0;
412}
413
dca51e78
CH		 414static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
415{
416 struct nvme_dev *dev = set->driver_data;
417
22b55601
KB		 418 return blk_mq_pci_map_queues(set, to_pci_dev(dev->dev),
419 dev->num_vecs > 1 ? 1 /* admin queue */ : 0);
dca51e78
CH		 420}
421
b60503ba 422/**
adf68f21 423 * __nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
b60503ba
MW		 424 * @nvmeq: The queue to use
425 * @cmd: The command to send
426 *
427 * Safe to use from interrupt context
428 */
e3f879bf
SB		 429static void __nvme_submit_cmd(struct nvme_queue *nvmeq,
430 struct nvme_command *cmd)
b60503ba 431{
a4aea562
MB		 432 u16 tail = nvmeq->sq_tail;
433
8ffaadf7
JD		 434 if (nvmeq->sq_cmds_io)
435 memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd));
436 else
437 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
438
b60503ba
MW		 439 if (++tail == nvmeq->q_depth)
440 tail = 0;
f9f38e33
HK		 441 if (nvme_dbbuf_update_and_check_event(tail, nvmeq->dbbuf_sq_db,
442 nvmeq->dbbuf_sq_ei))
443 writel(tail, nvmeq->q_db);
b60503ba 444 nvmeq->sq_tail = tail;
b60503ba
MW		 445}
446
a7a7cbe3 447static void **nvme_pci_iod_list(struct request *req)
b60503ba 448{
f4800d6d 449 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3 450 return (void **)(iod->sg + blk_rq_nr_phys_segments(req));
b60503ba
MW		 451}
452
955b1b5a
MI		 453static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req)
454{
455 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
20469a37 456 int nseg = blk_rq_nr_phys_segments(req);
955b1b5a
MI		 457 unsigned int avg_seg_size;
458
20469a37
KB		 459 if (nseg == 0)
460 return false;
461
462 avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
955b1b5a
MI		 463
464 if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1))))
465 return false;
466 if (!iod->nvmeq->qid)
467 return false;
468 if (!sgl_threshold || avg_seg_size < sgl_threshold)
469 return false;
470 return true;
471}
472
fc17b653 473static blk_status_t nvme_init_iod(struct request *rq, struct nvme_dev *dev)
ac3dd5bd 474{
f4800d6d 475 struct nvme_iod *iod = blk_mq_rq_to_pdu(rq);
f9d03f96 476 int nseg = blk_rq_nr_phys_segments(rq);
b131c61d 477 unsigned int size = blk_rq_payload_bytes(rq);
ac3dd5bd 478
955b1b5a
MI		 479 iod->use_sgl = nvme_pci_use_sgls(dev, rq);
480
f4800d6d 481 if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) {
a7a7cbe3
CK		 482 size_t alloc_size = nvme_pci_iod_alloc_size(dev, size, nseg,
483 iod->use_sgl);
484
485 iod->sg = kmalloc(alloc_size, GFP_ATOMIC);
f4800d6d 486 if (!iod->sg)
fc17b653 487 return BLK_STS_RESOURCE;
f4800d6d
CH		 488 } else {
489 iod->sg = iod->inline_sg;
ac3dd5bd
JA		 490 }
491
f4800d6d
CH		 492 iod->aborted = 0;
493 iod->npages = -1;
494 iod->nents = 0;
495 iod->length = size;
f80ec966 496
fc17b653 497 return BLK_STS_OK;
ac3dd5bd
JA		 498}
499
f4800d6d 500static void nvme_free_iod(struct nvme_dev *dev, struct request *req)
b60503ba 501{
f4800d6d 502 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3
CK		 503 const int last_prp = dev->ctrl.page_size / sizeof(__le64) - 1;
504 dma_addr_t dma_addr = iod->first_dma, next_dma_addr;
505
eca18b23 506 int i;
eca18b23
MW		 507
508 if (iod->npages == 0)
a7a7cbe3
CK		 509 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0],
510 dma_addr);
511
eca18b23 512 for (i = 0; i < iod->npages; i++) {
a7a7cbe3
CK		 513 void *addr = nvme_pci_iod_list(req)[i];
514
515 if (iod->use_sgl) {
516 struct nvme_sgl_desc *sg_list = addr;
517
518 next_dma_addr =
519 le64_to_cpu((sg_list[SGES_PER_PAGE - 1]).addr);
520 } else {
521 __le64 *prp_list = addr;
522
523 next_dma_addr = le64_to_cpu(prp_list[last_prp]);
524 }
525
526 dma_pool_free(dev->prp_page_pool, addr, dma_addr);
527 dma_addr = next_dma_addr;
eca18b23 528 }
ac3dd5bd 529
f4800d6d
CH		 530 if (iod->sg != iod->inline_sg)
531 kfree(iod->sg);
b4ff9c8d
KB		 532}
533
52b68d7e 534#ifdef CONFIG_BLK_DEV_INTEGRITY
e1e5e564
KB		 535static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
536{
537 if (be32_to_cpu(pi->ref_tag) == v)
538 pi->ref_tag = cpu_to_be32(p);
539}
540
541static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
542{
543 if (be32_to_cpu(pi->ref_tag) == p)
544 pi->ref_tag = cpu_to_be32(v);
545}
546
547/**
548 * nvme_dif_remap - remaps ref tags to bip seed and physical lba
549 *
550 * The virtual start sector is the one that was originally submitted by the
551 * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical
552 * start sector may be different. Remap protection information to match the
553 * physical LBA on writes, and back to the original seed on reads.
554 *
555 * Type 0 and 3 do not have a ref tag, so no remapping required.
556 */
557static void nvme_dif_remap(struct request *req,
558 void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
559{
560 struct nvme_ns *ns = req->rq_disk->private_data;
561 struct bio_integrity_payload *bip;
562 struct t10_pi_tuple *pi;
563 void *p, *pmap;
564 u32 i, nlb, ts, phys, virt;
565
566 if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3)
567 return;
568
569 bip = bio_integrity(req->bio);
570 if (!bip)
571 return;
572
573 pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset;
e1e5e564
KB		 574
575 p = pmap;
576 virt = bip_get_seed(bip);
577 phys = nvme_block_nr(ns, blk_rq_pos(req));
578 nlb = (blk_rq_bytes(req) >> ns->lba_shift);
ac6fc48c 579 ts = ns->disk->queue->integrity.tuple_size;
e1e5e564
KB		 580
581 for (i = 0; i < nlb; i++, virt++, phys++) {
582 pi = (struct t10_pi_tuple *)p;
583 dif_swap(phys, virt, pi);
584 p += ts;
585 }
586 kunmap_atomic(pmap);
587}
52b68d7e
KB		 588#else /* CONFIG_BLK_DEV_INTEGRITY */
589static void nvme_dif_remap(struct request *req,
590 void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
591{
592}
593static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
594{
595}
596static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
597{
598}
52b68d7e
KB		 599#endif
600
d0877473
KB		 601static void nvme_print_sgl(struct scatterlist *sgl, int nents)
602{
603 int i;
604 struct scatterlist *sg;
605
606 for_each_sg(sgl, sg, nents, i) {
607 dma_addr_t phys = sg_phys(sg);
608 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
609 "dma_address:%pad dma_length:%d\n",
610 i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
611 sg_dma_len(sg));
612 }
613}
614
a7a7cbe3
CK		 615static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
616 struct request *req, struct nvme_rw_command *cmnd)
ff22b54f 617{
f4800d6d 618 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
99802a7a 619 struct dma_pool *pool;
b131c61d 620 int length = blk_rq_payload_bytes(req);
eca18b23 621 struct scatterlist *sg = iod->sg;
ff22b54f
MW		 622 int dma_len = sg_dma_len(sg);
623 u64 dma_addr = sg_dma_address(sg);
5fd4ce1b 624 u32 page_size = dev->ctrl.page_size;
f137e0f1 625 int offset = dma_addr & (page_size - 1);
e025344c 626 __le64 *prp_list;
a7a7cbe3 627 void **list = nvme_pci_iod_list(req);
e025344c 628 dma_addr_t prp_dma;
eca18b23 629 int nprps, i;
ff22b54f 630
1d090624 631 length -= (page_size - offset);
5228b328
JS		 632 if (length <= 0) {
633 iod->first_dma = 0;
a7a7cbe3 634 goto done;
5228b328 635 }
ff22b54f 636
1d090624 637 dma_len -= (page_size - offset);
ff22b54f 638 if (dma_len) {
1d090624 639 dma_addr += (page_size - offset);
ff22b54f
MW		 640 } else {
641 sg = sg_next(sg);
642 dma_addr = sg_dma_address(sg);
643 dma_len = sg_dma_len(sg);
644 }
645
1d090624 646 if (length <= page_size) {
edd10d33 647 iod->first_dma = dma_addr;
a7a7cbe3 648 goto done;
e025344c
SMM		 649 }
650
1d090624 651 nprps = DIV_ROUND_UP(length, page_size);
99802a7a
MW		 652 if (nprps <= (256 / 8)) {
653 pool = dev->prp_small_pool;
eca18b23 654 iod->npages = 0;
99802a7a
MW		 655 } else {
656 pool = dev->prp_page_pool;
eca18b23 657 iod->npages = 1;
99802a7a
MW		 658 }
659
69d2b571 660 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
b77954cb 661 if (!prp_list) {
edd10d33 662 iod->first_dma = dma_addr;
eca18b23 663 iod->npages = -1;
86eea289 664 return BLK_STS_RESOURCE;
b77954cb 665 }
eca18b23
MW		 666 list[0] = prp_list;
667 iod->first_dma = prp_dma;
e025344c
SMM		 668 i = 0;
669 for (;;) {
1d090624 670 if (i == page_size >> 3) {
e025344c 671 __le64 *old_prp_list = prp_list;
69d2b571 672 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
eca18b23 673 if (!prp_list)
86eea289 674 return BLK_STS_RESOURCE;
eca18b23 675 list[iod->npages++] = prp_list;
7523d834
MW		 676 prp_list[0] = old_prp_list[i - 1];
677 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
678 i = 1;
e025344c
SMM		 679 }
680 prp_list[i++] = cpu_to_le64(dma_addr);
1d090624
KB		 681 dma_len -= page_size;
682 dma_addr += page_size;
683 length -= page_size;
e025344c
SMM		 684 if (length <= 0)
685 break;
686 if (dma_len > 0)
687 continue;
86eea289
KB		 688 if (unlikely(dma_len < 0))
689 goto bad_sgl;
e025344c
SMM		 690 sg = sg_next(sg);
691 dma_addr = sg_dma_address(sg);
692 dma_len = sg_dma_len(sg);
ff22b54f
MW		 693 }
694
a7a7cbe3
CK		 695done:
696 cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
697 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
698
86eea289
KB		 699 return BLK_STS_OK;
700
701 bad_sgl:
d0877473
KB		 702 WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents),
703 "Invalid SGL for payload:%d nents:%d\n",
704 blk_rq_payload_bytes(req), iod->nents);
86eea289 705 return BLK_STS_IOERR;
ff22b54f
MW		 706}
707
a7a7cbe3
CK		 708static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
709 struct scatterlist *sg)
710{
711 sge->addr = cpu_to_le64(sg_dma_address(sg));
712 sge->length = cpu_to_le32(sg_dma_len(sg));
713 sge->type = NVME_SGL_FMT_DATA_DESC << 4;
714}
715
716static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
717 dma_addr_t dma_addr, int entries)
718{
719 sge->addr = cpu_to_le64(dma_addr);
720 if (entries < SGES_PER_PAGE) {
721 sge->length = cpu_to_le32(entries * sizeof(*sge));
722 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
723 } else {
724 sge->length = cpu_to_le32(PAGE_SIZE);
725 sge->type = NVME_SGL_FMT_SEG_DESC << 4;
726 }
727}
728
729static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
b0f2853b 730 struct request *req, struct nvme_rw_command *cmd, int entries)
a7a7cbe3
CK		 731{
732 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3
CK		 733 struct dma_pool *pool;
734 struct nvme_sgl_desc *sg_list;
735 struct scatterlist *sg = iod->sg;
a7a7cbe3 736 dma_addr_t sgl_dma;
b0f2853b 737 int i = 0;
a7a7cbe3 738
a7a7cbe3
CK		 739 /* setting the transfer type as SGL */
740 cmd->flags = NVME_CMD_SGL_METABUF;
741
b0f2853b 742 if (entries == 1) {
a7a7cbe3
CK		 743 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
744 return BLK_STS_OK;
745 }
746
747 if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
748 pool = dev->prp_small_pool;
749 iod->npages = 0;
750 } else {
751 pool = dev->prp_page_pool;
752 iod->npages = 1;
753 }
754
755 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
756 if (!sg_list) {
757 iod->npages = -1;
758 return BLK_STS_RESOURCE;
759 }
760
761 nvme_pci_iod_list(req)[0] = sg_list;
762 iod->first_dma = sgl_dma;
763
764 nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
765
766 do {
767 if (i == SGES_PER_PAGE) {
768 struct nvme_sgl_desc *old_sg_desc = sg_list;
769 struct nvme_sgl_desc *link = &old_sg_desc[i - 1];
770
771 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
772 if (!sg_list)
773 return BLK_STS_RESOURCE;
774
775 i = 0;
776 nvme_pci_iod_list(req)[iod->npages++] = sg_list;
777 sg_list[i++] = *link;
778 nvme_pci_sgl_set_seg(link, sgl_dma, entries);
779 }
780
781 nvme_pci_sgl_set_data(&sg_list[i++], sg);
a7a7cbe3 782 sg = sg_next(sg);
b0f2853b 783 } while (--entries > 0);
a7a7cbe3 784
a7a7cbe3
CK		 785 return BLK_STS_OK;
786}
787
fc17b653 788static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
b131c61d 789 struct nvme_command *cmnd)
d29ec824 790{
f4800d6d 791 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
ba1ca37e
CH		 792 struct request_queue *q = req->q;
793 enum dma_data_direction dma_dir = rq_data_dir(req) ?
794 DMA_TO_DEVICE : DMA_FROM_DEVICE;
fc17b653 795 blk_status_t ret = BLK_STS_IOERR;
b0f2853b 796 int nr_mapped;
d29ec824 797
f9d03f96 798 sg_init_table(iod->sg, blk_rq_nr_phys_segments(req));
ba1ca37e
CH		 799 iod->nents = blk_rq_map_sg(q, req, iod->sg);
800 if (!iod->nents)
801 goto out;
d29ec824 802
fc17b653 803 ret = BLK_STS_RESOURCE;
b0f2853b
CH		 804 nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, dma_dir,
805 DMA_ATTR_NO_WARN);
806 if (!nr_mapped)
ba1ca37e 807 goto out;
d29ec824 808
955b1b5a 809 if (iod->use_sgl)
b0f2853b 810 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped);
a7a7cbe3
CK		 811 else
812 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
813
86eea289 814 if (ret != BLK_STS_OK)
ba1ca37e 815 goto out_unmap;
0e5e4f0e 816
fc17b653 817 ret = BLK_STS_IOERR;
ba1ca37e
CH		 818 if (blk_integrity_rq(req)) {
819 if (blk_rq_count_integrity_sg(q, req->bio) != 1)
820 goto out_unmap;
0e5e4f0e 821
bf684057
CH		 822 sg_init_table(&iod->meta_sg, 1);
823 if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1)
ba1ca37e 824 goto out_unmap;
0e5e4f0e 825
b5d8af5b 826 if (req_op(req) == REQ_OP_WRITE)
ba1ca37e 827 nvme_dif_remap(req, nvme_dif_prep);
0e5e4f0e 828
bf684057 829 if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir))
ba1ca37e 830 goto out_unmap;
d29ec824 831 }
00df5cb4 832
ba1ca37e 833 if (blk_integrity_rq(req))
bf684057 834 cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg));
fc17b653 835 return BLK_STS_OK;
00df5cb4 836
ba1ca37e
CH		 837out_unmap:
838 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
839out:
840 return ret;
00df5cb4
MW		 841}
842
f4800d6d 843static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
b60503ba 844{
f4800d6d 845 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
d4f6c3ab
CH		 846 enum dma_data_direction dma_dir = rq_data_dir(req) ?
847 DMA_TO_DEVICE : DMA_FROM_DEVICE;
848
849 if (iod->nents) {
850 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
851 if (blk_integrity_rq(req)) {
b5d8af5b 852 if (req_op(req) == REQ_OP_READ)
d4f6c3ab 853 nvme_dif_remap(req, nvme_dif_complete);
bf684057 854 dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir);
e1e5e564 855 }
e19b127f 856 }
e1e5e564 857
f9d03f96 858 nvme_cleanup_cmd(req);
f4800d6d 859 nvme_free_iod(dev, req);
d4f6c3ab 860}
b60503ba 861
d29ec824
CH		 862/*
863 * NOTE: ns is NULL when called on the admin queue.
864 */
fc17b653 865static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
a4aea562 866 const struct blk_mq_queue_data *bd)
edd10d33 867{
a4aea562
MB		 868 struct nvme_ns *ns = hctx->queue->queuedata;
869 struct nvme_queue *nvmeq = hctx->driver_data;
d29ec824 870 struct nvme_dev *dev = nvmeq->dev;
a4aea562 871 struct request *req = bd->rq;
ba1ca37e 872 struct nvme_command cmnd;
ebe6d874 873 blk_status_t ret;
e1e5e564 874
d1f06f4a
JA		 875 /*
876 * We should not need to do this, but we're still using this to
877 * ensure we can drain requests on a dying queue.
878 */
879 if (unlikely(nvmeq->cq_vector < 0))
880 return BLK_STS_IOERR;
881
f9d03f96 882 ret = nvme_setup_cmd(ns, req, &cmnd);
fc17b653 883 if (ret)
f4800d6d 884 return ret;
a4aea562 885
b131c61d 886 ret = nvme_init_iod(req, dev);
fc17b653 887 if (ret)
f9d03f96 888 goto out_free_cmd;
a4aea562 889
fc17b653 890 if (blk_rq_nr_phys_segments(req)) {
b131c61d 891 ret = nvme_map_data(dev, req, &cmnd);
fc17b653
CH		 892 if (ret)
893 goto out_cleanup_iod;
894 }
a4aea562 895
aae239e1 896 blk_mq_start_request(req);
a4aea562 897
ba1ca37e
CH		 898 spin_lock_irq(&nvmeq->q_lock);
899 __nvme_submit_cmd(nvmeq, &cmnd);
a4aea562 900 spin_unlock_irq(&nvmeq->q_lock);
fc17b653 901 return BLK_STS_OK;
f9d03f96 902out_cleanup_iod:
f4800d6d 903 nvme_free_iod(dev, req);
f9d03f96
CH		 904out_free_cmd:
905 nvme_cleanup_cmd(req);
ba1ca37e 906 return ret;
b60503ba 907}
e1e5e564 908
77f02a7a 909static void nvme_pci_complete_rq(struct request *req)
eee417b0 910{
f4800d6d 911 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a4aea562 912
77f02a7a
CH		 913 nvme_unmap_data(iod->nvmeq->dev, req);
914 nvme_complete_rq(req);
b60503ba
MW		 915}
916
d783e0bd 917/* We read the CQE phase first to check if the rest of the entry is valid */
750dde44 918static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq)
d783e0bd 919{
750dde44
CH		 920 return (le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) ==
921 nvmeq->cq_phase;
d783e0bd
MR		 922}
923
eb281c82 924static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
b60503ba 925{
eb281c82 926 u16 head = nvmeq->cq_head;
adf68f21 927
eb281c82
SG		 928 if (likely(nvmeq->cq_vector >= 0)) {
929 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
930 nvmeq->dbbuf_cq_ei))
931 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
932 }
933}
aae239e1 934
83a12fb7
SG		 935static inline void nvme_handle_cqe(struct nvme_queue *nvmeq,
936 struct nvme_completion *cqe)
937{
938 struct request *req;
adf68f21 939
83a12fb7
SG		 940 if (unlikely(cqe->command_id >= nvmeq->q_depth)) {
941 dev_warn(nvmeq->dev->ctrl.device,
942 "invalid id %d completed on queue %d\n",
943 cqe->command_id, le16_to_cpu(cqe->sq_id));
944 return;
b60503ba
MW		 945 }
946
83a12fb7
SG		 947 /*
948 * AEN requests are special as they don't time out and can
949 * survive any kind of queue freeze and often don't respond to
950 * aborts. We don't even bother to allocate a struct request
951 * for them but rather special case them here.
952 */
953 if (unlikely(nvmeq->qid == 0 &&
38dabe21 954 cqe->command_id >= NVME_AQ_BLK_MQ_DEPTH)) {
83a12fb7
SG		 955 nvme_complete_async_event(&nvmeq->dev->ctrl,
956 cqe->status, &cqe->result);
a0fa9647 957 return;
83a12fb7 958 }
b60503ba 959
e9d8a0fd 960 nvmeq->cqe_seen = 1;
83a12fb7
SG		 961 req = blk_mq_tag_to_rq(*nvmeq->tags, cqe->command_id);
962 nvme_end_request(req, cqe->status, cqe->result);
963}
b60503ba 964
920d13a8
SG		 965static inline bool nvme_read_cqe(struct nvme_queue *nvmeq,
966 struct nvme_completion *cqe)
b60503ba 967{
750dde44 968 if (nvme_cqe_pending(nvmeq)) {
920d13a8 969 *cqe = nvmeq->cqes[nvmeq->cq_head];
adf68f21 970
920d13a8
SG		 971 if (++nvmeq->cq_head == nvmeq->q_depth) {
972 nvmeq->cq_head = 0;
973 nvmeq->cq_phase = !nvmeq->cq_phase;
b60503ba 974 }
920d13a8 975 return true;
b60503ba 976 }
920d13a8 977 return false;
a0fa9647
JA		 978}
979
980static void nvme_process_cq(struct nvme_queue *nvmeq)
981{
920d13a8
SG		 982 struct nvme_completion cqe;
983 int consumed = 0;
b60503ba 984
920d13a8
SG		 985 while (nvme_read_cqe(nvmeq, &cqe)) {
986 nvme_handle_cqe(nvmeq, &cqe);
987 consumed++;
920d13a8 988 }
eb281c82 989
e9d8a0fd 990 if (consumed)
920d13a8 991 nvme_ring_cq_doorbell(nvmeq);
b60503ba
MW		 992}
993
994static irqreturn_t nvme_irq(int irq, void *data)
58ffacb5
MW		 995{
996 irqreturn_t result;
997 struct nvme_queue *nvmeq = data;
998 spin_lock(&nvmeq->q_lock);
e9539f47
MW		 999 nvme_process_cq(nvmeq);
1000 result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE;
1001 nvmeq->cqe_seen = 0;
58ffacb5
MW		 1002 spin_unlock(&nvmeq->q_lock);
1003 return result;
1004}
1005
1006static irqreturn_t nvme_irq_check(int irq, void *data)
1007{
1008 struct nvme_queue *nvmeq = data;
750dde44 1009 if (nvme_cqe_pending(nvmeq))
d783e0bd
MR		 1010 return IRQ_WAKE_THREAD;
1011 return IRQ_NONE;
58ffacb5
MW		 1012}
1013
7776db1c 1014static int __nvme_poll(struct nvme_queue *nvmeq, unsigned int tag)
a0fa9647 1015{
442e19b7
SG		 1016 struct nvme_completion cqe;
1017 int found = 0, consumed = 0;
a0fa9647 1018
750dde44 1019 if (!nvme_cqe_pending(nvmeq))
442e19b7 1020 return 0;
a0fa9647 1021
442e19b7
SG		 1022 spin_lock_irq(&nvmeq->q_lock);
1023 while (nvme_read_cqe(nvmeq, &cqe)) {
1024 nvme_handle_cqe(nvmeq, &cqe);
1025 consumed++;
1026
1027 if (tag == cqe.command_id) {
1028 found = 1;
1029 break;
1030 }
1031 }
1032
1033 if (consumed)
1034 nvme_ring_cq_doorbell(nvmeq);
1035 spin_unlock_irq(&nvmeq->q_lock);
1036
1037 return found;
a0fa9647
JA		 1038}
1039
7776db1c
KB		 1040static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag)
1041{
1042 struct nvme_queue *nvmeq = hctx->driver_data;
1043
1044 return __nvme_poll(nvmeq, tag);
1045}
1046
ad22c355 1047static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
b60503ba 1048{
f866fc42 1049 struct nvme_dev *dev = to_nvme_dev(ctrl);
147b27e4 1050 struct nvme_queue *nvmeq = &dev->queues[0];
a4aea562 1051 struct nvme_command c;
b60503ba 1052
a4aea562
MB		 1053 memset(&c, 0, sizeof(c));
1054 c.common.opcode = nvme_admin_async_event;
ad22c355 1055 c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
3c0cf138 1056
9396dec9 1057 spin_lock_irq(&nvmeq->q_lock);
f866fc42 1058 __nvme_submit_cmd(nvmeq, &c);
9396dec9 1059 spin_unlock_irq(&nvmeq->q_lock);
f705f837
CH		 1060}
1061
b60503ba 1062static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
f705f837 1063{
b60503ba
MW		 1064 struct nvme_command c;
1065
1066 memset(&c, 0, sizeof(c));
1067 c.delete_queue.opcode = opcode;
1068 c.delete_queue.qid = cpu_to_le16(id);
1069
1c63dc66 1070 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1071}
1072
b60503ba
MW		 1073static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
1074 struct nvme_queue *nvmeq)
1075{
b60503ba
MW		 1076 struct nvme_command c;
1077 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
1078
d29ec824 1079 /*
16772ae6 1080 * Note: we (ab)use the fact that the prp fields survive if no data
d29ec824
CH		 1081 * is attached to the request.
1082 */
b60503ba
MW		 1083 memset(&c, 0, sizeof(c));
1084 c.create_cq.opcode = nvme_admin_create_cq;
1085 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1086 c.create_cq.cqid = cpu_to_le16(qid);
1087 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1088 c.create_cq.cq_flags = cpu_to_le16(flags);
1089 c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
1090
1c63dc66 1091 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1092}
1093
1094static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1095 struct nvme_queue *nvmeq)
1096{
b60503ba 1097 struct nvme_command c;
81c1cd98 1098 int flags = NVME_QUEUE_PHYS_CONTIG;
b60503ba 1099
d29ec824 1100 /*
16772ae6 1101 * Note: we (ab)use the fact that the prp fields survive if no data
d29ec824
CH		 1102 * is attached to the request.
1103 */
b60503ba
MW		 1104 memset(&c, 0, sizeof(c));
1105 c.create_sq.opcode = nvme_admin_create_sq;
1106 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1107 c.create_sq.sqid = cpu_to_le16(qid);
1108 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1109 c.create_sq.sq_flags = cpu_to_le16(flags);
1110 c.create_sq.cqid = cpu_to_le16(qid);
1111
1c63dc66 1112 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1113}
1114
1115static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1116{
1117 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1118}
1119
1120static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1121{
1122 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1123}
1124
2a842aca 1125static void abort_endio(struct request *req, blk_status_t error)
bc5fc7e4 1126{
f4800d6d
CH		 1127 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1128 struct nvme_queue *nvmeq = iod->nvmeq;
e44ac588 1129
27fa9bc5
CH		 1130 dev_warn(nvmeq->dev->ctrl.device,
1131 "Abort status: 0x%x", nvme_req(req)->status);
e7a2a87d 1132 atomic_inc(&nvmeq->dev->ctrl.abort_limit);
e7a2a87d 1133 blk_mq_free_request(req);
bc5fc7e4
MW		 1134}
1135
b2a0eb1a
KB		 1136static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1137{
1138
1139 /* If true, indicates loss of adapter communication, possibly by a
1140 * NVMe Subsystem reset.
1141 */
1142 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1143
ad70062c
JW		 1144 /* If there is a reset/reinit ongoing, we shouldn't reset again. */
1145 switch (dev->ctrl.state) {
1146 case NVME_CTRL_RESETTING:
ad6a0a52 1147 case NVME_CTRL_CONNECTING:
b2a0eb1a 1148 return false;
ad70062c
JW		 1149 default:
1150 break;
1151 }
b2a0eb1a
KB		 1152
1153 /* We shouldn't reset unless the controller is on fatal error state
1154 * _or_ if we lost the communication with it.
1155 */
1156 if (!(csts & NVME_CSTS_CFS) && !nssro)
1157 return false;
1158
b2a0eb1a
KB		 1159 return true;
1160}
1161
1162static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1163{
1164 /* Read a config register to help see what died. */
1165 u16 pci_status;
1166 int result;
1167
1168 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1169 &pci_status);
1170 if (result == PCIBIOS_SUCCESSFUL)
1171 dev_warn(dev->ctrl.device,
1172 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1173 csts, pci_status);
1174 else
1175 dev_warn(dev->ctrl.device,
1176 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1177 csts, result);
1178}
1179
31c7c7d2 1180static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
c30341dc 1181{
f4800d6d
CH		 1182 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1183 struct nvme_queue *nvmeq = iod->nvmeq;
c30341dc 1184 struct nvme_dev *dev = nvmeq->dev;
a4aea562 1185 struct request *abort_req;
a4aea562 1186 struct nvme_command cmd;
b2a0eb1a
KB		 1187 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1188
651438bb
WX		 1189 /* If PCI error recovery process is happening, we cannot reset or
1190 * the recovery mechanism will surely fail.
1191 */
1192 mb();
1193 if (pci_channel_offline(to_pci_dev(dev->dev)))
1194 return BLK_EH_RESET_TIMER;
1195
b2a0eb1a
KB		 1196 /*
1197 * Reset immediately if the controller is failed
1198 */
1199 if (nvme_should_reset(dev, csts)) {
1200 nvme_warn_reset(dev, csts);
1201 nvme_dev_disable(dev, false);
d86c4d8e 1202 nvme_reset_ctrl(&dev->ctrl);
b2a0eb1a
KB		 1203 return BLK_EH_HANDLED;
1204 }
c30341dc 1205
7776db1c
KB		 1206 /*
1207 * Did we miss an interrupt?
1208 */
1209 if (__nvme_poll(nvmeq, req->tag)) {
1210 dev_warn(dev->ctrl.device,
1211 "I/O %d QID %d timeout, completion polled\n",
1212 req->tag, nvmeq->qid);
1213 return BLK_EH_HANDLED;
1214 }
1215
31c7c7d2 1216 /*
fd634f41
CH		 1217 * Shutdown immediately if controller times out while starting. The
1218 * reset work will see the pci device disabled when it gets the forced
1219 * cancellation error. All outstanding requests are completed on
1220 * shutdown, so we return BLK_EH_HANDLED.
1221 */
4244140d
KB		 1222 switch (dev->ctrl.state) {
1223 case NVME_CTRL_CONNECTING:
1224 case NVME_CTRL_RESETTING:
1b3c47c1 1225 dev_warn(dev->ctrl.device,
fd634f41
CH		 1226 "I/O %d QID %d timeout, disable controller\n",
1227 req->tag, nvmeq->qid);
a5cdb68c 1228 nvme_dev_disable(dev, false);
27fa9bc5 1229 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
fd634f41 1230 return BLK_EH_HANDLED;
4244140d
KB		 1231 default:
1232 break;
c30341dc
KB		 1233 }
1234
fd634f41
CH		 1235 /*
1236 * Shutdown the controller immediately and schedule a reset if the
1237 * command was already aborted once before and still hasn't been
1238 * returned to the driver, or if this is the admin queue.
31c7c7d2 1239 */
f4800d6d 1240 if (!nvmeq->qid || iod->aborted) {
1b3c47c1 1241 dev_warn(dev->ctrl.device,
e1569a16
KB		 1242 "I/O %d QID %d timeout, reset controller\n",
1243 req->tag, nvmeq->qid);
a5cdb68c 1244 nvme_dev_disable(dev, false);
d86c4d8e 1245 nvme_reset_ctrl(&dev->ctrl);
c30341dc 1246
e1569a16
KB		 1247 /*
1248 * Mark the request as handled, since the inline shutdown
1249 * forces all outstanding requests to complete.
1250 */
27fa9bc5 1251 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
e1569a16 1252 return BLK_EH_HANDLED;
c30341dc 1253 }
c30341dc 1254
e7a2a87d 1255 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
6bf25d16 1256 atomic_inc(&dev->ctrl.abort_limit);
31c7c7d2 1257 return BLK_EH_RESET_TIMER;
6bf25d16 1258 }
7bf7d778 1259 iod->aborted = 1;
a4aea562 1260
c30341dc
KB		 1261 memset(&cmd, 0, sizeof(cmd));
1262 cmd.abort.opcode = nvme_admin_abort_cmd;
a4aea562 1263 cmd.abort.cid = req->tag;
c30341dc 1264 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
c30341dc 1265
1b3c47c1
SG		 1266 dev_warn(nvmeq->dev->ctrl.device,
1267 "I/O %d QID %d timeout, aborting\n",
1268 req->tag, nvmeq->qid);
e7a2a87d
CH		 1269
1270 abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
eb71f435 1271 BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
e7a2a87d
CH		 1272 if (IS_ERR(abort_req)) {
1273 atomic_inc(&dev->ctrl.abort_limit);
1274 return BLK_EH_RESET_TIMER;
1275 }
1276
1277 abort_req->timeout = ADMIN_TIMEOUT;
1278 abort_req->end_io_data = NULL;
1279 blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio);
c30341dc 1280
31c7c7d2
CH		 1281 /*
1282 * The aborted req will be completed on receiving the abort req.
1283 * We enable the timer again. If hit twice, it'll cause a device reset,
1284 * as the device then is in a faulty state.
1285 */
1286 return BLK_EH_RESET_TIMER;
c30341dc
KB		 1287}
1288
a4aea562
MB		 1289static void nvme_free_queue(struct nvme_queue *nvmeq)
1290{
9e866774
MW		 1291 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1292 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
8ffaadf7
JD		 1293 if (nvmeq->sq_cmds)
1294 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
9e866774 1295 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
9e866774
MW		 1296}
1297
a1a5ef99 1298static void nvme_free_queues(struct nvme_dev *dev, int lowest)
22404274
KB		 1299{
1300 int i;
1301
d858e5f0 1302 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
d858e5f0 1303 dev->ctrl.queue_count--;
147b27e4 1304 nvme_free_queue(&dev->queues[i]);
121c7ad4 1305 }
22404274
KB		 1306}
1307
4d115420
KB		 1308/**
1309 * nvme_suspend_queue - put queue into suspended state
1310 * @nvmeq - queue to suspend
4d115420
KB		 1311 */
1312static int nvme_suspend_queue(struct nvme_queue *nvmeq)
b60503ba 1313{
2b25d981 1314 int vector;
b60503ba 1315
a09115b2 1316 spin_lock_irq(&nvmeq->q_lock);
2b25d981
KB		 1317 if (nvmeq->cq_vector == -1) {
1318 spin_unlock_irq(&nvmeq->q_lock);
1319 return 1;
1320 }
0ff199cb 1321 vector = nvmeq->cq_vector;
42f61420 1322 nvmeq->dev->online_queues--;
2b25d981 1323 nvmeq->cq_vector = -1;
a09115b2
MW		 1324 spin_unlock_irq(&nvmeq->q_lock);
1325
d1f06f4a
JA		 1326 /*
1327 * Ensure that nvme_queue_rq() sees it ->cq_vector == -1 without
1328 * having to grab the lock.
1329 */
1330 mb();
1331
1c63dc66 1332 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
c81545f9 1333 blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q);
6df3dbc8 1334
0ff199cb 1335 pci_free_irq(to_pci_dev(nvmeq->dev->dev), vector, nvmeq);
b60503ba 1336
4d115420
KB		 1337 return 0;
1338}
b60503ba 1339
a5cdb68c 1340static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
4d115420 1341{
147b27e4 1342 struct nvme_queue *nvmeq = &dev->queues[0];
4d115420 1343
a5cdb68c
KB		 1344 if (shutdown)
1345 nvme_shutdown_ctrl(&dev->ctrl);
1346 else
20d0dfe6 1347 nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap);
07836e65
KB		 1348
1349 spin_lock_irq(&nvmeq->q_lock);
1350 nvme_process_cq(nvmeq);
1351 spin_unlock_irq(&nvmeq->q_lock);
b60503ba
MW		 1352}
1353
8ffaadf7
JD		 1354static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1355 int entry_size)
1356{
1357 int q_depth = dev->q_depth;
5fd4ce1b
CH		 1358 unsigned q_size_aligned = roundup(q_depth * entry_size,
1359 dev->ctrl.page_size);
8ffaadf7
JD		 1360
1361 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
c45f5c99 1362 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
5fd4ce1b 1363 mem_per_q = round_down(mem_per_q, dev->ctrl.page_size);
c45f5c99 1364 q_depth = div_u64(mem_per_q, entry_size);
8ffaadf7
JD		 1365
1366 /*
1367 * Ensure the reduced q_depth is above some threshold where it
1368 * would be better to map queues in system memory with the
1369 * original depth
1370 */
1371 if (q_depth < 64)
1372 return -ENOMEM;
1373 }
1374
1375 return q_depth;
1376}
1377
1378static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1379 int qid, int depth)
1380{
815c6704
KB		 1381 /* CMB SQEs will be mapped before creation */
1382 if (qid && dev->cmb && use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS))
1383 return 0;
8ffaadf7 1384
815c6704
KB		 1385 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
1386 &nvmeq->sq_dma_addr, GFP_KERNEL);
1387 if (!nvmeq->sq_cmds)
1388 return -ENOMEM;
8ffaadf7
JD		 1389 return 0;
1390}
1391
a6ff7262 1392static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
b60503ba 1393{
147b27e4 1394 struct nvme_queue *nvmeq = &dev->queues[qid];
b60503ba 1395
62314e40
KB		 1396 if (dev->ctrl.queue_count > qid)
1397 return 0;
b60503ba 1398
e75ec752 1399 nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth),
4d51abf9 1400 &nvmeq->cq_dma_addr, GFP_KERNEL);
b60503ba
MW		 1401 if (!nvmeq->cqes)
1402 goto free_nvmeq;
b60503ba 1403
8ffaadf7 1404 if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth))
b60503ba
MW		 1405 goto free_cqdma;
1406
e75ec752 1407 nvmeq->q_dmadev = dev->dev;
091b6092 1408 nvmeq->dev = dev;
b60503ba
MW		 1409 spin_lock_init(&nvmeq->q_lock);
1410 nvmeq->cq_head = 0;
82123460 1411 nvmeq->cq_phase = 1;
b80d5ccc 1412 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
b60503ba 1413 nvmeq->q_depth = depth;
c30341dc 1414 nvmeq->qid = qid;
758dd7fd 1415 nvmeq->cq_vector = -1;
d858e5f0 1416 dev->ctrl.queue_count++;
36a7e993 1417
147b27e4 1418 return 0;
b60503ba
MW		 1419
1420 free_cqdma:
e75ec752 1421 dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes,
b60503ba
MW		 1422 nvmeq->cq_dma_addr);
1423 free_nvmeq:
147b27e4 1424 return -ENOMEM;
b60503ba
MW		 1425}
1426
dca51e78 1427static int queue_request_irq(struct nvme_queue *nvmeq)
3001082c 1428{
0ff199cb
CH		 1429 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1430 int nr = nvmeq->dev->ctrl.instance;
1431
1432 if (use_threaded_interrupts) {
1433 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1434 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1435 } else {
1436 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1437 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1438 }
3001082c
MW		 1439}
1440
22404274 1441static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
b60503ba 1442{
22404274 1443 struct nvme_dev *dev = nvmeq->dev;
b60503ba 1444
7be50e93 1445 spin_lock_irq(&nvmeq->q_lock);
22404274
KB		 1446 nvmeq->sq_tail = 0;
1447 nvmeq->cq_head = 0;
1448 nvmeq->cq_phase = 1;
b80d5ccc 1449 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
22404274 1450 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
f9f38e33 1451 nvme_dbbuf_init(dev, nvmeq, qid);
42f61420 1452 dev->online_queues++;
7be50e93 1453 spin_unlock_irq(&nvmeq->q_lock);
22404274
KB		 1454}
1455
1456static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1457{
1458 struct nvme_dev *dev = nvmeq->dev;
1459 int result;
3f85d50b 1460
815c6704
KB		 1461 if (dev->cmb && use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
1462 unsigned offset = (qid - 1) * roundup(SQ_SIZE(nvmeq->q_depth),
1463 dev->ctrl.page_size);
1464 nvmeq->sq_dma_addr = dev->cmb_bus_addr + offset;
1465 nvmeq->sq_cmds_io = dev->cmb + offset;
1466 }
1467
22b55601
KB		 1468 /*
1469 * A queue's vector matches the queue identifier unless the controller
1470 * has only one vector available.
1471 */
1472 nvmeq->cq_vector = dev->num_vecs == 1 ? 0 : qid;
b60503ba
MW		 1473 result = adapter_alloc_cq(dev, qid, nvmeq);
1474 if (result < 0)
f25a2dfc 1475 goto release_vector;
b60503ba
MW		 1476
1477 result = adapter_alloc_sq(dev, qid, nvmeq);
1478 if (result < 0)
1479 goto release_cq;
1480
161b8be2 1481 nvme_init_queue(nvmeq, qid);
dca51e78 1482 result = queue_request_irq(nvmeq);
b60503ba
MW		 1483 if (result < 0)
1484 goto release_sq;
1485
22404274 1486 return result;
b60503ba
MW		 1487
1488 release_sq:
f25a2dfc 1489 dev->online_queues--;
b60503ba
MW		 1490 adapter_delete_sq(dev, qid);
1491 release_cq:
1492 adapter_delete_cq(dev, qid);
f25a2dfc
JW		 1493 release_vector:
1494 nvmeq->cq_vector = -1;
22404274 1495 return result;
b60503ba
MW		 1496}
1497
f363b089 1498static const struct blk_mq_ops nvme_mq_admin_ops = {
d29ec824 1499 .queue_rq = nvme_queue_rq,
77f02a7a 1500 .complete = nvme_pci_complete_rq,
a4aea562 1501 .init_hctx = nvme_admin_init_hctx,
4af0e21c 1502 .exit_hctx = nvme_admin_exit_hctx,
0350815a 1503 .init_request = nvme_init_request,
a4aea562
MB		 1504 .timeout = nvme_timeout,
1505};
1506
f363b089 1507static const struct blk_mq_ops nvme_mq_ops = {
a4aea562 1508 .queue_rq = nvme_queue_rq,
77f02a7a 1509 .complete = nvme_pci_complete_rq,
a4aea562
MB		 1510 .init_hctx = nvme_init_hctx,
1511 .init_request = nvme_init_request,
dca51e78 1512 .map_queues = nvme_pci_map_queues,
a4aea562 1513 .timeout = nvme_timeout,
a0fa9647 1514 .poll = nvme_poll,
a4aea562
MB		 1515};
1516
ea191d2f
KB		 1517static void nvme_dev_remove_admin(struct nvme_dev *dev)
1518{
1c63dc66 1519 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
69d9a99c
KB		 1520 /*
1521 * If the controller was reset during removal, it's possible
1522 * user requests may be waiting on a stopped queue. Start the
1523 * queue to flush these to completion.
1524 */
c81545f9 1525 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1c63dc66 1526 blk_cleanup_queue(dev->ctrl.admin_q);
ea191d2f
KB		 1527 blk_mq_free_tag_set(&dev->admin_tagset);
1528 }
1529}
1530
a4aea562
MB		 1531static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1532{
1c63dc66 1533 if (!dev->ctrl.admin_q) {
a4aea562
MB		 1534 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1535 dev->admin_tagset.nr_hw_queues = 1;
e3e9d50c 1536
38dabe21 1537 dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH;
a4aea562 1538 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
e75ec752 1539 dev->admin_tagset.numa_node = dev_to_node(dev->dev);
a7a7cbe3 1540 dev->admin_tagset.cmd_size = nvme_pci_cmd_size(dev, false);
d3484991 1541 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED;
a4aea562
MB		 1542 dev->admin_tagset.driver_data = dev;
1543
1544 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1545 return -ENOMEM;
34b6c231 1546 dev->ctrl.admin_tagset = &dev->admin_tagset;
a4aea562 1547
1c63dc66
CH		 1548 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1549 if (IS_ERR(dev->ctrl.admin_q)) {
a4aea562
MB		 1550 blk_mq_free_tag_set(&dev->admin_tagset);
1551 return -ENOMEM;
1552 }
1c63dc66 1553 if (!blk_get_queue(dev->ctrl.admin_q)) {
ea191d2f 1554 nvme_dev_remove_admin(dev);
1c63dc66 1555 dev->ctrl.admin_q = NULL;
ea191d2f
KB		 1556 return -ENODEV;
1557 }
0fb59cbc 1558 } else
c81545f9 1559 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
a4aea562
MB		 1560
1561 return 0;
1562}
1563
97f6ef64
XY		 1564static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1565{
1566 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1567}
1568
1569static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1570{
1571 struct pci_dev *pdev = to_pci_dev(dev->dev);
1572
1573 if (size <= dev->bar_mapped_size)
1574 return 0;
1575 if (size > pci_resource_len(pdev, 0))
1576 return -ENOMEM;
1577 if (dev->bar)
1578 iounmap(dev->bar);
1579 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1580 if (!dev->bar) {
1581 dev->bar_mapped_size = 0;
1582 return -ENOMEM;
1583 }
1584 dev->bar_mapped_size = size;
1585 dev->dbs = dev->bar + NVME_REG_DBS;
1586
1587 return 0;
1588}
1589
01ad0990 1590static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
b60503ba 1591{
ba47e386 1592 int result;
b60503ba
MW		 1593 u32 aqa;
1594 struct nvme_queue *nvmeq;
1595
97f6ef64
XY		 1596 result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1597 if (result < 0)
1598 return result;
1599
8ef2074d 1600 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
20d0dfe6 1601 NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
dfbac8c7 1602
7a67cbea
CH		 1603 if (dev->subsystem &&
1604 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1605 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
dfbac8c7 1606
20d0dfe6 1607 result = nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap);
ba47e386
MW		 1608 if (result < 0)
1609 return result;
b60503ba 1610
a6ff7262 1611 result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
147b27e4
SG		 1612 if (result)
1613 return result;
b60503ba 1614
147b27e4 1615 nvmeq = &dev->queues[0];
b60503ba
MW		 1616 aqa = nvmeq->q_depth - 1;
1617 aqa |= aqa << 16;
1618
7a67cbea
CH		 1619 writel(aqa, dev->bar + NVME_REG_AQA);
1620 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1621 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
b60503ba 1622
20d0dfe6 1623 result = nvme_enable_ctrl(&dev->ctrl, dev->ctrl.cap);
025c557a 1624 if (result)
d4875622 1625 return result;
a4aea562 1626
2b25d981 1627 nvmeq->cq_vector = 0;
161b8be2 1628 nvme_init_queue(nvmeq, 0);
dca51e78 1629 result = queue_request_irq(nvmeq);
758dd7fd
JD		 1630 if (result) {
1631 nvmeq->cq_vector = -1;
d4875622 1632 return result;
758dd7fd 1633 }
025c557a 1634
b60503ba
MW		 1635 return result;
1636}
1637
749941f2 1638static int nvme_create_io_queues(struct nvme_dev *dev)
42f61420 1639{
949928c1 1640 unsigned i, max;
749941f2 1641 int ret = 0;
42f61420 1642
d858e5f0 1643 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
a6ff7262 1644 if (nvme_alloc_queue(dev, i, dev->q_depth)) {
749941f2 1645 ret = -ENOMEM;
42f61420 1646 break;
749941f2
CH		 1647 }
1648 }
42f61420 1649
d858e5f0 1650 max = min(dev->max_qid, dev->ctrl.queue_count - 1);
949928c1 1651 for (i = dev->online_queues; i <= max; i++) {
147b27e4 1652 ret = nvme_create_queue(&dev->queues[i], i);
d4875622 1653 if (ret)
42f61420 1654 break;
27e8166c 1655 }
749941f2
CH		 1656
1657 /*
1658 * Ignore failing Create SQ/CQ commands, we can continue with less
8adb8c14
MI		 1659 * than the desired amount of queues, and even a controller without
1660 * I/O queues can still be used to issue admin commands. This might
749941f2
CH		 1661 * be useful to upgrade a buggy firmware for example.
1662 */
1663 return ret >= 0 ? 0 : ret;
b60503ba
MW		 1664}
1665
202021c1
SB		 1666static ssize_t nvme_cmb_show(struct device *dev,
1667 struct device_attribute *attr,
1668 char *buf)
1669{
1670 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
1671
c965809c 1672 return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n",
202021c1
SB		 1673 ndev->cmbloc, ndev->cmbsz);
1674}
1675static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL);
1676
88de4598 1677static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
8ffaadf7 1678{
88de4598
CH		 1679 u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
1680
1681 return 1ULL << (12 + 4 * szu);
1682}
1683
1684static u32 nvme_cmb_size(struct nvme_dev *dev)
1685{
1686 return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
1687}
1688
f65efd6d 1689static void nvme_map_cmb(struct nvme_dev *dev)
8ffaadf7 1690{
88de4598 1691 u64 size, offset;
8ffaadf7
JD		 1692 resource_size_t bar_size;
1693 struct pci_dev *pdev = to_pci_dev(dev->dev);
8969f1f8 1694 int bar;
8ffaadf7 1695
7a67cbea 1696 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
f65efd6d
CH		 1697 if (!dev->cmbsz)
1698 return;
202021c1 1699 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
8ffaadf7 1700
202021c1 1701 if (!use_cmb_sqes)
f65efd6d 1702 return;
8ffaadf7 1703
88de4598
CH		 1704 size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
1705 offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
8969f1f8
CH		 1706 bar = NVME_CMB_BIR(dev->cmbloc);
1707 bar_size = pci_resource_len(pdev, bar);
8ffaadf7
JD		 1708
1709 if (offset > bar_size)
f65efd6d 1710 return;
8ffaadf7
JD		 1711
1712 /*
1713 * Controllers may support a CMB size larger than their BAR,
1714 * for example, due to being behind a bridge. Reduce the CMB to
1715 * the reported size of the BAR
1716 */
1717 if (size > bar_size - offset)
1718 size = bar_size - offset;
1719
f65efd6d
CH		 1720 dev->cmb = ioremap_wc(pci_resource_start(pdev, bar) + offset, size);
1721 if (!dev->cmb)
1722 return;
8969f1f8 1723 dev->cmb_bus_addr = pci_bus_address(pdev, bar) + offset;
8ffaadf7 1724 dev->cmb_size = size;
f65efd6d
CH		 1725
1726 if (sysfs_add_file_to_group(&dev->ctrl.device->kobj,
1727 &dev_attr_cmb.attr, NULL))
1728 dev_warn(dev->ctrl.device,
1729 "failed to add sysfs attribute for CMB\n");
8ffaadf7
JD		 1730}
1731
1732static inline void nvme_release_cmb(struct nvme_dev *dev)
1733{
1734 if (dev->cmb) {
1735 iounmap(dev->cmb);
1736 dev->cmb = NULL;
1c78f773
MG		 1737 sysfs_remove_file_from_group(&dev->ctrl.device->kobj,
1738 &dev_attr_cmb.attr, NULL);
1739 dev->cmbsz = 0;
8ffaadf7
JD		 1740 }
1741}
1742
87ad72a5
CH		 1743static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1744{
4033f35d 1745 u64 dma_addr = dev->host_mem_descs_dma;
87ad72a5 1746 struct nvme_command c;
87ad72a5
CH		 1747 int ret;
1748
87ad72a5
CH		 1749 memset(&c, 0, sizeof(c));
1750 c.features.opcode = nvme_admin_set_features;
1751 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1752 c.features.dword11 = cpu_to_le32(bits);
1753 c.features.dword12 = cpu_to_le32(dev->host_mem_size >>
1754 ilog2(dev->ctrl.page_size));
1755 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr));
1756 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr));
1757 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs);
1758
1759 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1760 if (ret) {
1761 dev_warn(dev->ctrl.device,
1762 "failed to set host mem (err %d, flags %#x).\n",
1763 ret, bits);
1764 }
87ad72a5
CH		 1765 return ret;
1766}
1767
1768static void nvme_free_host_mem(struct nvme_dev *dev)
1769{
1770 int i;
1771
1772 for (i = 0; i < dev->nr_host_mem_descs; i++) {
1773 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
1774 size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size;
1775
1776 dma_free_coherent(dev->dev, size, dev->host_mem_desc_bufs[i],
1777 le64_to_cpu(desc->addr));
1778 }
1779
1780 kfree(dev->host_mem_desc_bufs);
1781 dev->host_mem_desc_bufs = NULL;
4033f35d
CH		 1782 dma_free_coherent(dev->dev,
1783 dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
1784 dev->host_mem_descs, dev->host_mem_descs_dma);
87ad72a5 1785 dev->host_mem_descs = NULL;
7e5dd57e 1786 dev->nr_host_mem_descs = 0;
87ad72a5
CH		 1787}
1788
92dc6895
CH		 1789static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
1790 u32 chunk_size)
9d713c2b 1791{
87ad72a5 1792 struct nvme_host_mem_buf_desc *descs;
92dc6895 1793 u32 max_entries, len;
4033f35d 1794 dma_addr_t descs_dma;
2ee0e4ed 1795 int i = 0;
87ad72a5 1796 void **bufs;
6fbcde66 1797 u64 size, tmp;
87ad72a5 1798
87ad72a5
CH		 1799 tmp = (preferred + chunk_size - 1);
1800 do_div(tmp, chunk_size);
1801 max_entries = tmp;
044a9df1
CH		 1802
1803 if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
1804 max_entries = dev->ctrl.hmmaxd;
1805
4033f35d
CH		 1806 descs = dma_zalloc_coherent(dev->dev, max_entries * sizeof(*descs),
1807 &descs_dma, GFP_KERNEL);
87ad72a5
CH		 1808 if (!descs)
1809 goto out;
1810
1811 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
1812 if (!bufs)
1813 goto out_free_descs;
1814
244a8fe4 1815 for (size = 0; size < preferred && i < max_entries; size += len) {
87ad72a5
CH		 1816 dma_addr_t dma_addr;
1817
50cdb7c6 1818 len = min_t(u64, chunk_size, preferred - size);
87ad72a5
CH		 1819 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
1820 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1821 if (!bufs[i])
1822 break;
1823
1824 descs[i].addr = cpu_to_le64(dma_addr);
1825 descs[i].size = cpu_to_le32(len / dev->ctrl.page_size);
1826 i++;
1827 }
1828
92dc6895 1829 if (!size)
87ad72a5 1830 goto out_free_bufs;
87ad72a5 1831
87ad72a5
CH		 1832 dev->nr_host_mem_descs = i;
1833 dev->host_mem_size = size;
1834 dev->host_mem_descs = descs;
4033f35d 1835 dev->host_mem_descs_dma = descs_dma;
87ad72a5
CH		 1836 dev->host_mem_desc_bufs = bufs;
1837 return 0;
1838
1839out_free_bufs:
1840 while (--i >= 0) {
1841 size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size;
1842
1843 dma_free_coherent(dev->dev, size, bufs[i],
1844 le64_to_cpu(descs[i].addr));
1845 }
1846
1847 kfree(bufs);
1848out_free_descs:
4033f35d
CH		 1849 dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
1850 descs_dma);
87ad72a5 1851out:
87ad72a5
CH		 1852 dev->host_mem_descs = NULL;
1853 return -ENOMEM;
1854}
1855
92dc6895
CH		 1856static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
1857{
1858 u32 chunk_size;
1859
1860 /* start big and work our way down */
30f92d62 1861 for (chunk_size = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
044a9df1 1862 chunk_size >= max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
92dc6895
CH		 1863 chunk_size /= 2) {
1864 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
1865 if (!min || dev->host_mem_size >= min)
1866 return 0;
1867 nvme_free_host_mem(dev);
1868 }
1869 }
1870
1871 return -ENOMEM;
1872}
1873
9620cfba 1874static int nvme_setup_host_mem(struct nvme_dev *dev)
87ad72a5
CH		 1875{
1876 u64 max = (u64)max_host_mem_size_mb * SZ_1M;
1877 u64 preferred = (u64)dev->ctrl.hmpre * 4096;
1878 u64 min = (u64)dev->ctrl.hmmin * 4096;
1879 u32 enable_bits = NVME_HOST_MEM_ENABLE;
6fbcde66 1880 int ret;
87ad72a5
CH		 1881
1882 preferred = min(preferred, max);
1883 if (min > max) {
1884 dev_warn(dev->ctrl.device,
1885 "min host memory (%lld MiB) above limit (%d MiB).\n",
1886 min >> ilog2(SZ_1M), max_host_mem_size_mb);
1887 nvme_free_host_mem(dev);
9620cfba 1888 return 0;
87ad72a5
CH		 1889 }
1890
1891 /*
1892 * If we already have a buffer allocated check if we can reuse it.
1893 */
1894 if (dev->host_mem_descs) {
1895 if (dev->host_mem_size >= min)
1896 enable_bits |= NVME_HOST_MEM_RETURN;
1897 else
1898 nvme_free_host_mem(dev);
1899 }
1900
1901 if (!dev->host_mem_descs) {
92dc6895
CH		 1902 if (nvme_alloc_host_mem(dev, min, preferred)) {
1903 dev_warn(dev->ctrl.device,
1904 "failed to allocate host memory buffer.\n");
9620cfba 1905 return 0; /* controller must work without HMB */
92dc6895
CH		 1906 }
1907
1908 dev_info(dev->ctrl.device,
1909 "allocated %lld MiB host memory buffer.\n",
1910 dev->host_mem_size >> ilog2(SZ_1M));
87ad72a5
CH		 1911 }
1912
9620cfba
CH		 1913 ret = nvme_set_host_mem(dev, enable_bits);
1914 if (ret)
87ad72a5 1915 nvme_free_host_mem(dev);
9620cfba 1916 return ret;
9d713c2b
KB		 1917}
1918
8d85fce7 1919static int nvme_setup_io_queues(struct nvme_dev *dev)
b60503ba 1920{
147b27e4 1921 struct nvme_queue *adminq = &dev->queues[0];
e75ec752 1922 struct pci_dev *pdev = to_pci_dev(dev->dev);
97f6ef64
XY		 1923 int result, nr_io_queues;
1924 unsigned long size;
b60503ba 1925
22b55601
KB		 1926 struct irq_affinity affd = {
1927 .pre_vectors = 1
1928 };
1929
16ccfff2 1930 nr_io_queues = num_possible_cpus();
9a0be7ab
CH		 1931 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
1932 if (result < 0)
1b23484b 1933 return result;
9a0be7ab 1934
f5fa90dc 1935 if (nr_io_queues == 0)
a5229050 1936 return 0;
b60503ba 1937
88de4598 1938 if (dev->cmb && (dev->cmbsz & NVME_CMBSZ_SQS)) {
8ffaadf7
JD		 1939 result = nvme_cmb_qdepth(dev, nr_io_queues,
1940 sizeof(struct nvme_command));
1941 if (result > 0)
1942 dev->q_depth = result;
1943 else
1944 nvme_release_cmb(dev);
1945 }
1946
97f6ef64
XY		 1947 do {
1948 size = db_bar_size(dev, nr_io_queues);
1949 result = nvme_remap_bar(dev, size);
1950 if (!result)
1951 break;
1952 if (!--nr_io_queues)
1953 return -ENOMEM;
1954 } while (1);
1955 adminq->q_db = dev->dbs;
f1938f6e 1956
9d713c2b 1957 /* Deregister the admin queue's interrupt */
0ff199cb 1958 pci_free_irq(pdev, 0, adminq);
9d713c2b 1959
e32efbfc
JA		 1960 /*
1961 * If we enable msix early due to not intx, disable it again before
1962 * setting up the full range we need.
1963 */
dca51e78 1964 pci_free_irq_vectors(pdev);
22b55601
KB		 1965 result = pci_alloc_irq_vectors_affinity(pdev, 1, nr_io_queues + 1,
1966 PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd);
1967 if (result <= 0)
dca51e78 1968 return -EIO;
22b55601
KB		 1969 dev->num_vecs = result;
1970 dev->max_qid = max(result - 1, 1);
fa08a396 1971
063a8096
MW		 1972 /*
1973 * Should investigate if there's a performance win from allocating
1974 * more queues than interrupt vectors; it might allow the submission
1975 * path to scale better, even if the receive path is limited by the
1976 * number of interrupts.
1977 */
063a8096 1978
dca51e78 1979 result = queue_request_irq(adminq);
758dd7fd
JD		 1980 if (result) {
1981 adminq->cq_vector = -1;
d4875622 1982 return result;
758dd7fd 1983 }
749941f2 1984 return nvme_create_io_queues(dev);
b60503ba
MW		 1985}
1986
2a842aca 1987static void nvme_del_queue_end(struct request *req, blk_status_t error)
a5768aa8 1988{
db3cbfff 1989 struct nvme_queue *nvmeq = req->end_io_data;
b5875222 1990
db3cbfff
KB		 1991 blk_mq_free_request(req);
1992 complete(&nvmeq->dev->ioq_wait);
a5768aa8
KB		 1993}
1994
2a842aca 1995static void nvme_del_cq_end(struct request *req, blk_status_t error)
a5768aa8 1996{
db3cbfff 1997 struct nvme_queue *nvmeq = req->end_io_data;
a5768aa8 1998
db3cbfff
KB		 1999 if (!error) {
2000 unsigned long flags;
2001
2e39e0f6
ML		 2002 /*
2003 * We might be called with the AQ q_lock held
2004 * and the I/O queue q_lock should always
2005 * nest inside the AQ one.
2006 */
2007 spin_lock_irqsave_nested(&nvmeq->q_lock, flags,
2008 SINGLE_DEPTH_NESTING);
db3cbfff
KB		 2009 nvme_process_cq(nvmeq);
2010 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
a5768aa8 2011 }
db3cbfff
KB		 2012
2013 nvme_del_queue_end(req, error);
a5768aa8
KB		 2014}
2015
db3cbfff 2016static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
bda4e0fb 2017{
db3cbfff
KB		 2018 struct request_queue *q = nvmeq->dev->ctrl.admin_q;
2019 struct request *req;
2020 struct nvme_command cmd;
bda4e0fb 2021
db3cbfff
KB		 2022 memset(&cmd, 0, sizeof(cmd));
2023 cmd.delete_queue.opcode = opcode;
2024 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
bda4e0fb 2025
eb71f435 2026 req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
db3cbfff
KB		 2027 if (IS_ERR(req))
2028 return PTR_ERR(req);
bda4e0fb 2029
db3cbfff
KB		 2030 req->timeout = ADMIN_TIMEOUT;
2031 req->end_io_data = nvmeq;
2032
2033 blk_execute_rq_nowait(q, NULL, req, false,
2034 opcode == nvme_admin_delete_cq ?
2035 nvme_del_cq_end : nvme_del_queue_end);
2036 return 0;
bda4e0fb
KB		 2037}
2038
ee9aebb2 2039static void nvme_disable_io_queues(struct nvme_dev *dev)
a5768aa8 2040{
ee9aebb2 2041 int pass, queues = dev->online_queues - 1;
db3cbfff
KB		 2042 unsigned long timeout;
2043 u8 opcode = nvme_admin_delete_sq;
a5768aa8 2044
db3cbfff 2045 for (pass = 0; pass < 2; pass++) {
014a0d60 2046 int sent = 0, i = queues;
db3cbfff
KB		 2047
2048 reinit_completion(&dev->ioq_wait);
2049 retry:
2050 timeout = ADMIN_TIMEOUT;
c21377f8 2051 for (; i > 0; i--, sent++)
147b27e4 2052 if (nvme_delete_queue(&dev->queues[i], opcode))
db3cbfff 2053 break;
c21377f8 2054
db3cbfff
KB		 2055 while (sent--) {
2056 timeout = wait_for_completion_io_timeout(&dev->ioq_wait, timeout);
2057 if (timeout == 0)
2058 return;
2059 if (i)
2060 goto retry;
2061 }
2062 opcode = nvme_admin_delete_cq;
2063 }
a5768aa8
KB		 2064}
2065
422ef0c7 2066/*
2b1b7e78 2067 * return error value only when tagset allocation failed
422ef0c7 2068 */
8d85fce7 2069static int nvme_dev_add(struct nvme_dev *dev)
b60503ba 2070{
2b1b7e78
JW		 2071 int ret;
2072
5bae7f73 2073 if (!dev->ctrl.tagset) {
ffe7704d
KB		 2074 dev->tagset.ops = &nvme_mq_ops;
2075 dev->tagset.nr_hw_queues = dev->online_queues - 1;
2076 dev->tagset.timeout = NVME_IO_TIMEOUT;
2077 dev->tagset.numa_node = dev_to_node(dev->dev);
2078 dev->tagset.queue_depth =
a4aea562 2079 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
a7a7cbe3
CK		 2080 dev->tagset.cmd_size = nvme_pci_cmd_size(dev, false);
2081 if ((dev->ctrl.sgls & ((1 << 0) | (1 << 1))) && sgl_threshold) {
2082 dev->tagset.cmd_size = max(dev->tagset.cmd_size,
2083 nvme_pci_cmd_size(dev, true));
2084 }
ffe7704d
KB		 2085 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2086 dev->tagset.driver_data = dev;
b60503ba 2087
2b1b7e78
JW		 2088 ret = blk_mq_alloc_tag_set(&dev->tagset);
2089 if (ret) {
2090 dev_warn(dev->ctrl.device,
2091 "IO queues tagset allocation failed %d\n", ret);
2092 return ret;
2093 }
5bae7f73 2094 dev->ctrl.tagset = &dev->tagset;
f9f38e33
HK		 2095
2096 nvme_dbbuf_set(dev);
949928c1
KB		 2097 } else {
2098 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2099
2100 /* Free previously allocated queues that are no longer usable */
2101 nvme_free_queues(dev, dev->online_queues);
ffe7704d 2102 }
949928c1 2103
e1e5e564 2104 return 0;
b60503ba
MW		 2105}
2106
b00a726a 2107static int nvme_pci_enable(struct nvme_dev *dev)
0877cb0d 2108{
b00a726a 2109 int result = -ENOMEM;
e75ec752 2110 struct pci_dev *pdev = to_pci_dev(dev->dev);
0877cb0d
KB		 2111
2112 if (pci_enable_device_mem(pdev))
2113 return result;
2114
0877cb0d 2115 pci_set_master(pdev);
0877cb0d 2116
e75ec752
CH		 2117 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) &&
2118 dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32)))
052d0efa 2119 goto disable;
0877cb0d 2120
7a67cbea 2121 if (readl(dev->bar + NVME_REG_CSTS) == -1) {
0e53d180 2122 result = -ENODEV;
b00a726a 2123 goto disable;
0e53d180 2124 }
e32efbfc
JA		 2125
2126 /*
a5229050
KB		 2127 * Some devices and/or platforms don't advertise or work with INTx
2128 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2129 * adjust this later.
e32efbfc 2130 */
dca51e78
CH		 2131 result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
2132 if (result < 0)
2133 return result;
e32efbfc 2134
20d0dfe6 2135 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
7a67cbea 2136
20d0dfe6 2137 dev->q_depth = min_t(int, NVME_CAP_MQES(dev->ctrl.cap) + 1,
b27c1e68 2138 io_queue_depth);
20d0dfe6 2139 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
7a67cbea 2140 dev->dbs = dev->bar + 4096;
1f390c1f
SG		 2141
2142 /*
2143 * Temporary fix for the Apple controller found in the MacBook8,1 and
2144 * some MacBook7,1 to avoid controller resets and data loss.
2145 */
2146 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
2147 dev->q_depth = 2;
9bdcfb10
CH		 2148 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
2149 "set queue depth=%u to work around controller resets\n",
1f390c1f 2150 dev->q_depth);
d554b5e1
MP		 2151 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2152 (pdev->device == 0xa821 || pdev->device == 0xa822) &&
20d0dfe6 2153 NVME_CAP_MQES(dev->ctrl.cap) == 0) {
d554b5e1
MP		 2154 dev->q_depth = 64;
2155 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2156 "set queue depth=%u\n", dev->q_depth);
1f390c1f
SG		 2157 }
2158
f65efd6d 2159 nvme_map_cmb(dev);
202021c1 2160
a0a3408e
KB		 2161 pci_enable_pcie_error_reporting(pdev);
2162 pci_save_state(pdev);
0877cb0d
KB		 2163 return 0;
2164
2165 disable:
0877cb0d
KB		 2166 pci_disable_device(pdev);
2167 return result;
2168}
2169
2170static void nvme_dev_unmap(struct nvme_dev *dev)
b00a726a
KB		 2171{
2172 if (dev->bar)
2173 iounmap(dev->bar);
a1f447b3 2174 pci_release_mem_regions(to_pci_dev(dev->dev));
b00a726a
KB		 2175}
2176
2177static void nvme_pci_disable(struct nvme_dev *dev)
0877cb0d 2178{
e75ec752
CH		 2179 struct pci_dev *pdev = to_pci_dev(dev->dev);
2180
f63572df 2181 nvme_release_cmb(dev);
dca51e78 2182 pci_free_irq_vectors(pdev);
0877cb0d 2183
a0a3408e
KB		 2184 if (pci_is_enabled(pdev)) {
2185 pci_disable_pcie_error_reporting(pdev);
e75ec752 2186 pci_disable_device(pdev);
4d115420 2187 }
4d115420
KB		 2188}
2189
a5cdb68c 2190static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
b60503ba 2191{
ee9aebb2 2192 int i;
302ad8cc
KB		 2193 bool dead = true;
2194 struct pci_dev *pdev = to_pci_dev(dev->dev);
22404274 2195
77bf25ea 2196 mutex_lock(&dev->shutdown_lock);
302ad8cc
KB		 2197 if (pci_is_enabled(pdev)) {
2198 u32 csts = readl(dev->bar + NVME_REG_CSTS);
2199
ebef7368
KB		 2200 if (dev->ctrl.state == NVME_CTRL_LIVE ||
2201 dev->ctrl.state == NVME_CTRL_RESETTING)
302ad8cc
KB		 2202 nvme_start_freeze(&dev->ctrl);
2203 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
2204 pdev->error_state != pci_channel_io_normal);
c9d3bf88 2205 }
c21377f8 2206
302ad8cc
KB		 2207 /*
2208 * Give the controller a chance to complete all entered requests if
2209 * doing a safe shutdown.
2210 */
87ad72a5
CH		 2211 if (!dead) {
2212 if (shutdown)
2213 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
9a915a5b
JW		 2214 }
2215
2216 nvme_stop_queues(&dev->ctrl);
87ad72a5 2217
64ee0ac0 2218 if (!dead && dev->ctrl.queue_count > 0) {
87ad72a5
CH		 2219 /*
2220 * If the controller is still alive tell it to stop using the
2221 * host memory buffer. In theory the shutdown / reset should
2222 * make sure that it doesn't access the host memoery anymore,
2223 * but I'd rather be safe than sorry..
2224 */
2225 if (dev->host_mem_descs)
2226 nvme_set_host_mem(dev, 0);
ee9aebb2 2227 nvme_disable_io_queues(dev);
a5cdb68c 2228 nvme_disable_admin_queue(dev, shutdown);
4d115420 2229 }
ee9aebb2
KB		 2230 for (i = dev->ctrl.queue_count - 1; i >= 0; i--)
2231 nvme_suspend_queue(&dev->queues[i]);
2232
b00a726a 2233 nvme_pci_disable(dev);
07836e65 2234
e1958e65
ML		 2235 blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
2236 blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
302ad8cc
KB		 2237
2238 /*
2239 * The driver will not be starting up queues again if shutting down so
2240 * must flush all entered requests to their failed completion to avoid
2241 * deadlocking blk-mq hot-cpu notifier.
2242 */
2243 if (shutdown)
2244 nvme_start_queues(&dev->ctrl);
77bf25ea 2245 mutex_unlock(&dev->shutdown_lock);
b60503ba
MW		 2246}
2247
091b6092
MW		 2248static int nvme_setup_prp_pools(struct nvme_dev *dev)
2249{
e75ec752 2250 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
091b6092
MW		 2251 PAGE_SIZE, PAGE_SIZE, 0);
2252 if (!dev->prp_page_pool)
2253 return -ENOMEM;
2254
99802a7a 2255 /* Optimisation for I/Os between 4k and 128k */
e75ec752 2256 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
99802a7a
MW		 2257 256, 256, 0);
2258 if (!dev->prp_small_pool) {
2259 dma_pool_destroy(dev->prp_page_pool);
2260 return -ENOMEM;
2261 }
091b6092
MW		 2262 return 0;
2263}
2264
2265static void nvme_release_prp_pools(struct nvme_dev *dev)
2266{
2267 dma_pool_destroy(dev->prp_page_pool);
99802a7a 2268 dma_pool_destroy(dev->prp_small_pool);
091b6092
MW		 2269}
2270
1673f1f0 2271static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
5e82e952 2272{
1673f1f0 2273 struct nvme_dev *dev = to_nvme_dev(ctrl);
9ac27090 2274
f9f38e33 2275 nvme_dbbuf_dma_free(dev);
e75ec752 2276 put_device(dev->dev);
4af0e21c
KB		 2277 if (dev->tagset.tags)
2278 blk_mq_free_tag_set(&dev->tagset);
1c63dc66
CH		 2279 if (dev->ctrl.admin_q)
2280 blk_put_queue(dev->ctrl.admin_q);
5e82e952 2281 kfree(dev->queues);
e286bcfc 2282 free_opal_dev(dev->ctrl.opal_dev);
5e82e952
KB		 2283 kfree(dev);
2284}
2285
f58944e2
KB		 2286static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status)
2287{
237045fc 2288 dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status);
f58944e2 2289
d22524a4 2290 nvme_get_ctrl(&dev->ctrl);
69d9a99c 2291 nvme_dev_disable(dev, false);
03e0f3a6 2292 if (!queue_work(nvme_wq, &dev->remove_work))
f58944e2
KB		 2293 nvme_put_ctrl(&dev->ctrl);
2294}
2295
fd634f41 2296static void nvme_reset_work(struct work_struct *work)
5e82e952 2297{
d86c4d8e
CH		 2298 struct nvme_dev *dev =
2299 container_of(work, struct nvme_dev, ctrl.reset_work);
a98e58e5 2300 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
f58944e2 2301 int result = -ENODEV;
2b1b7e78 2302 enum nvme_ctrl_state new_state = NVME_CTRL_LIVE;
5e82e952 2303
82b057ca 2304 if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING))
fd634f41 2305 goto out;
5e82e952 2306
fd634f41
CH		 2307 /*
2308 * If we're called to reset a live controller first shut it down before
2309 * moving on.
2310 */
b00a726a 2311 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
a5cdb68c 2312 nvme_dev_disable(dev, false);
5e82e952 2313
ad70062c 2314 /*
ad6a0a52 2315 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
ad70062c
JW		 2316 * initializing procedure here.
2317 */
ad6a0a52 2318 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
ad70062c 2319 dev_warn(dev->ctrl.device,
ad6a0a52 2320 "failed to mark controller CONNECTING\n");
ad70062c
JW		 2321 goto out;
2322 }
2323
b00a726a 2324 result = nvme_pci_enable(dev);
f0b50732 2325 if (result)
3cf519b5 2326 goto out;
f0b50732 2327
01ad0990 2328 result = nvme_pci_configure_admin_queue(dev);
f0b50732 2329 if (result)
f58944e2 2330 goto out;
f0b50732 2331
0fb59cbc
KB		 2332 result = nvme_alloc_admin_tags(dev);
2333 if (result)
f58944e2 2334 goto out;
b9afca3e 2335
ce4541f4
CH		 2336 result = nvme_init_identify(&dev->ctrl);
2337 if (result)
f58944e2 2338 goto out;
ce4541f4 2339
e286bcfc
SB		 2340 if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
2341 if (!dev->ctrl.opal_dev)
2342 dev->ctrl.opal_dev =
2343 init_opal_dev(&dev->ctrl, &nvme_sec_submit);
2344 else if (was_suspend)
2345 opal_unlock_from_suspend(dev->ctrl.opal_dev);
2346 } else {
2347 free_opal_dev(dev->ctrl.opal_dev);
2348 dev->ctrl.opal_dev = NULL;
4f1244c8 2349 }
a98e58e5 2350
f9f38e33
HK		 2351 if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) {
2352 result = nvme_dbbuf_dma_alloc(dev);
2353 if (result)
2354 dev_warn(dev->dev,
2355 "unable to allocate dma for dbbuf\n");
2356 }
2357
9620cfba
CH		 2358 if (dev->ctrl.hmpre) {
2359 result = nvme_setup_host_mem(dev);
2360 if (result < 0)
2361 goto out;
2362 }
87ad72a5 2363
f0b50732 2364 result = nvme_setup_io_queues(dev);
badc34d4 2365 if (result)
f58944e2 2366 goto out;
f0b50732 2367
2659e57b
CH		 2368 /*
2369 * Keep the controller around but remove all namespaces if we don't have
2370 * any working I/O queue.
2371 */
3cf519b5 2372 if (dev->online_queues < 2) {
1b3c47c1 2373 dev_warn(dev->ctrl.device, "IO queues not created\n");
3b24774e 2374 nvme_kill_queues(&dev->ctrl);
5bae7f73 2375 nvme_remove_namespaces(&dev->ctrl);
2b1b7e78 2376 new_state = NVME_CTRL_ADMIN_ONLY;
3cf519b5 2377 } else {
25646264 2378 nvme_start_queues(&dev->ctrl);
302ad8cc 2379 nvme_wait_freeze(&dev->ctrl);
2b1b7e78
JW		 2380 /* hit this only when allocate tagset fails */
2381 if (nvme_dev_add(dev))
2382 new_state = NVME_CTRL_ADMIN_ONLY;
302ad8cc 2383 nvme_unfreeze(&dev->ctrl);
3cf519b5
CH		 2384 }
2385
2b1b7e78
JW		 2386 /*
2387 * If only admin queue live, keep it to do further investigation or
2388 * recovery.
2389 */
2390 if (!nvme_change_ctrl_state(&dev->ctrl, new_state)) {
2391 dev_warn(dev->ctrl.device,
2392 "failed to mark controller state %d\n", new_state);
bb8d261e
CH		 2393 goto out;
2394 }
92911a55 2395
d09f2b45 2396 nvme_start_ctrl(&dev->ctrl);
3cf519b5 2397 return;
f0b50732 2398
3cf519b5 2399 out:
f58944e2 2400 nvme_remove_dead_ctrl(dev, result);
f0b50732
KB		 2401}
2402
5c8809e6 2403static void nvme_remove_dead_ctrl_work(struct work_struct *work)
9a6b9458 2404{
5c8809e6 2405 struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
e75ec752 2406 struct pci_dev *pdev = to_pci_dev(dev->dev);
9a6b9458 2407
69d9a99c 2408 nvme_kill_queues(&dev->ctrl);
9a6b9458 2409 if (pci_get_drvdata(pdev))
921920ab 2410 device_release_driver(&pdev->dev);
1673f1f0 2411 nvme_put_ctrl(&dev->ctrl);
9a6b9458
KB		 2412}
2413
1c63dc66 2414static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
9ca97374 2415{
1c63dc66 2416 *val = readl(to_nvme_dev(ctrl)->bar + off);
90667892 2417 return 0;
9ca97374
TH		 2418}
2419
5fd4ce1b 2420static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
4cc06521 2421{
5fd4ce1b
CH		 2422 writel(val, to_nvme_dev(ctrl)->bar + off);
2423 return 0;
2424}
4cc06521 2425
7fd8930f
CH		 2426static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2427{
2428 *val = readq(to_nvme_dev(ctrl)->bar + off);
2429 return 0;
4cc06521
KB		 2430}
2431
97c12223
KB		 2432static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
2433{
2434 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2435
2436 return snprintf(buf, size, "%s", dev_name(&pdev->dev));
2437}
2438
1c63dc66 2439static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
1a353d85 2440 .name = "pcie",
e439bb12 2441 .module = THIS_MODULE,
c81bfba9 2442 .flags = NVME_F_METADATA_SUPPORTED,
1c63dc66 2443 .reg_read32 = nvme_pci_reg_read32,
5fd4ce1b 2444 .reg_write32 = nvme_pci_reg_write32,
7fd8930f 2445 .reg_read64 = nvme_pci_reg_read64,
1673f1f0 2446 .free_ctrl = nvme_pci_free_ctrl,
f866fc42 2447 .submit_async_event = nvme_pci_submit_async_event,
97c12223 2448 .get_address = nvme_pci_get_address,
1c63dc66 2449};
4cc06521 2450
b00a726a
KB		 2451static int nvme_dev_map(struct nvme_dev *dev)
2452{
b00a726a
KB		 2453 struct pci_dev *pdev = to_pci_dev(dev->dev);
2454
a1f447b3 2455 if (pci_request_mem_regions(pdev, "nvme"))
b00a726a
KB		 2456 return -ENODEV;
2457
97f6ef64 2458 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
b00a726a
KB		 2459 goto release;
2460
9fa196e7 2461 return 0;
b00a726a 2462 release:
9fa196e7
MG		 2463 pci_release_mem_regions(pdev);
2464 return -ENODEV;
b00a726a
KB		 2465}
2466
8427bbc2 2467static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
ff5350a8
AL		 2468{
2469 if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
2470 /*
2471 * Several Samsung devices seem to drop off the PCIe bus
2472 * randomly when APST is on and uses the deepest sleep state.
2473 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2474 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2475 * 950 PRO 256GB", but it seems to be restricted to two Dell
2476 * laptops.
2477 */
2478 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
2479 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
2480 dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
2481 return NVME_QUIRK_NO_DEEPEST_PS;
8427bbc2
KHF		 2482 } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
2483 /*
2484 * Samsung SSD 960 EVO drops off the PCIe bus after system
467c77d4
JJ		 2485 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
2486 * within few minutes after bootup on a Coffee Lake board -
2487 * ASUS PRIME Z370-A
8427bbc2
KHF		 2488 */
2489 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
467c77d4
JJ		 2490 (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") ||
2491 dmi_match(DMI_BOARD_NAME, "PRIME Z370-A")))
8427bbc2 2492 return NVME_QUIRK_NO_APST;
ff5350a8
AL		 2493 }
2494
2495 return 0;
2496}
2497
18119775
KB		 2498static void nvme_async_probe(void *data, async_cookie_t cookie)
2499{
2500 struct nvme_dev *dev = data;
80f513b5 2501
18119775
KB		 2502 nvme_reset_ctrl_sync(&dev->ctrl);
2503 flush_work(&dev->ctrl.scan_work);
80f513b5 2504 nvme_put_ctrl(&dev->ctrl);
18119775
KB		 2505}
2506
8d85fce7 2507static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
b60503ba 2508{
a4aea562 2509 int node, result = -ENOMEM;
b60503ba 2510 struct nvme_dev *dev;
ff5350a8 2511 unsigned long quirks = id->driver_data;
b60503ba 2512
a4aea562
MB		 2513 node = dev_to_node(&pdev->dev);
2514 if (node == NUMA_NO_NODE)
2fa84351 2515 set_dev_node(&pdev->dev, first_memory_node);
a4aea562
MB		 2516
2517 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
b60503ba
MW		 2518 if (!dev)
2519 return -ENOMEM;
147b27e4
SG		 2520
2521 dev->queues = kcalloc_node(num_possible_cpus() + 1,
2522 sizeof(struct nvme_queue), GFP_KERNEL, node);
b60503ba
MW		 2523 if (!dev->queues)
2524 goto free;
2525
e75ec752 2526 dev->dev = get_device(&pdev->dev);
9a6b9458 2527 pci_set_drvdata(pdev, dev);
1c63dc66 2528
b00a726a
KB		 2529 result = nvme_dev_map(dev);
2530 if (result)
b00c9b7a 2531 goto put_pci;
b00a726a 2532
d86c4d8e 2533 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
5c8809e6 2534 INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
77bf25ea 2535 mutex_init(&dev->shutdown_lock);
db3cbfff 2536 init_completion(&dev->ioq_wait);
b60503ba 2537
091b6092
MW		 2538 result = nvme_setup_prp_pools(dev);
2539 if (result)
b00c9b7a 2540 goto unmap;
4cc06521 2541
8427bbc2 2542 quirks |= check_vendor_combination_bug(pdev);
ff5350a8 2543
f3ca80fc 2544 result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
ff5350a8 2545 quirks);
4cc06521 2546 if (result)
2e1d8448 2547 goto release_pools;
740216fc 2548
1b3c47c1
SG		 2549 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
2550
80f513b5 2551 nvme_get_ctrl(&dev->ctrl);
18119775 2552 async_schedule(nvme_async_probe, dev);
4caff8fc 2553
b60503ba
MW		 2554 return 0;
2555
0877cb0d 2556 release_pools:
091b6092 2557 nvme_release_prp_pools(dev);
b00c9b7a
CJ		 2558 unmap:
2559 nvme_dev_unmap(dev);
a96d4f5c 2560 put_pci:
e75ec752 2561 put_device(dev->dev);
b60503ba
MW		 2562 free:
2563 kfree(dev->queues);
b60503ba
MW		 2564 kfree(dev);
2565 return result;
2566}
2567
775755ed 2568static void nvme_reset_prepare(struct pci_dev *pdev)
f0d54a54 2569{
a6739479 2570 struct nvme_dev *dev = pci_get_drvdata(pdev);
f263fbb8 2571 nvme_dev_disable(dev, false);
775755ed 2572}
f0d54a54 2573
775755ed
CH		 2574static void nvme_reset_done(struct pci_dev *pdev)
2575{
f263fbb8 2576 struct nvme_dev *dev = pci_get_drvdata(pdev);
79c48ccf 2577 nvme_reset_ctrl_sync(&dev->ctrl);
f0d54a54
KB		 2578}
2579
09ece142
KB		 2580static void nvme_shutdown(struct pci_dev *pdev)
2581{
2582 struct nvme_dev *dev = pci_get_drvdata(pdev);
a5cdb68c 2583 nvme_dev_disable(dev, true);
09ece142
KB		 2584}
2585
f58944e2
KB		 2586/*
2587 * The driver's remove may be called on a device in a partially initialized
2588 * state. This function must not have any dependencies on the device state in
2589 * order to proceed.
2590 */
8d85fce7 2591static void nvme_remove(struct pci_dev *pdev)
b60503ba
MW		 2592{
2593 struct nvme_dev *dev = pci_get_drvdata(pdev);
9a6b9458 2594
bb8d261e
CH		 2595 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
2596
d86c4d8e 2597 cancel_work_sync(&dev->ctrl.reset_work);
9a6b9458 2598 pci_set_drvdata(pdev, NULL);
0ff9d4e1 2599
6db28eda 2600 if (!pci_device_is_present(pdev)) {
0ff9d4e1 2601 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
6db28eda
KB		 2602 nvme_dev_disable(dev, false);
2603 }
0ff9d4e1 2604
d86c4d8e 2605 flush_work(&dev->ctrl.reset_work);
d09f2b45
SG		 2606 nvme_stop_ctrl(&dev->ctrl);
2607 nvme_remove_namespaces(&dev->ctrl);
a5cdb68c 2608 nvme_dev_disable(dev, true);
87ad72a5 2609 nvme_free_host_mem(dev);
a4aea562 2610 nvme_dev_remove_admin(dev);
a1a5ef99 2611 nvme_free_queues(dev, 0);
d09f2b45 2612 nvme_uninit_ctrl(&dev->ctrl);
9a6b9458 2613 nvme_release_prp_pools(dev);
b00a726a 2614 nvme_dev_unmap(dev);
1673f1f0 2615 nvme_put_ctrl(&dev->ctrl);
b60503ba
MW		 2616}
2617
13880f5b
KB		 2618static int nvme_pci_sriov_configure(struct pci_dev *pdev, int numvfs)
2619{
2620 int ret = 0;
2621
2622 if (numvfs == 0) {
2623 if (pci_vfs_assigned(pdev)) {
2624 dev_warn(&pdev->dev,
2625 "Cannot disable SR-IOV VFs while assigned\n");
2626 return -EPERM;
2627 }
2628 pci_disable_sriov(pdev);
2629 return 0;
2630 }
2631
2632 ret = pci_enable_sriov(pdev, numvfs);
2633 return ret ? ret : numvfs;
2634}
2635
671a6018 2636#ifdef CONFIG_PM_SLEEP
cd638946
KB		 2637static int nvme_suspend(struct device *dev)
2638{
2639 struct pci_dev *pdev = to_pci_dev(dev);
2640 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2641
a5cdb68c 2642 nvme_dev_disable(ndev, true);
cd638946
KB		 2643 return 0;
2644}
2645
2646static int nvme_resume(struct device *dev)
2647{
2648 struct pci_dev *pdev = to_pci_dev(dev);
2649 struct nvme_dev *ndev = pci_get_drvdata(pdev);
cd638946 2650
d86c4d8e 2651 nvme_reset_ctrl(&ndev->ctrl);
9a6b9458 2652 return 0;
cd638946 2653}
671a6018 2654#endif
cd638946
KB		 2655
2656static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
b60503ba 2657
a0a3408e
KB		 2658static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
2659 pci_channel_state_t state)
2660{
2661 struct nvme_dev *dev = pci_get_drvdata(pdev);
2662
2663 /*
2664 * A frozen channel requires a reset. When detected, this method will
2665 * shutdown the controller to quiesce. The controller will be restarted
2666 * after the slot reset through driver's slot_reset callback.
2667 */
a0a3408e
KB		 2668 switch (state) {
2669 case pci_channel_io_normal:
2670 return PCI_ERS_RESULT_CAN_RECOVER;
2671 case pci_channel_io_frozen:
d011fb31
KB		 2672 dev_warn(dev->ctrl.device,
2673 "frozen state error detected, reset controller\n");
a5cdb68c 2674 nvme_dev_disable(dev, false);
a0a3408e
KB		 2675 return PCI_ERS_RESULT_NEED_RESET;
2676 case pci_channel_io_perm_failure:
d011fb31
KB		 2677 dev_warn(dev->ctrl.device,
2678 "failure state error detected, request disconnect\n");
a0a3408e
KB		 2679 return PCI_ERS_RESULT_DISCONNECT;
2680 }
2681 return PCI_ERS_RESULT_NEED_RESET;
2682}
2683
2684static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
2685{
2686 struct nvme_dev *dev = pci_get_drvdata(pdev);
2687
1b3c47c1 2688 dev_info(dev->ctrl.device, "restart after slot reset\n");
a0a3408e 2689 pci_restore_state(pdev);
cc1d5e74
KB		 2690 nvme_reset_ctrl_sync(&dev->ctrl);
2691
2692 switch (dev->ctrl.state) {
2693 case NVME_CTRL_LIVE:
2694 case NVME_CTRL_ADMIN_ONLY:
2695 return PCI_ERS_RESULT_RECOVERED;
2696 default:
2697 return PCI_ERS_RESULT_DISCONNECT;
2698 }
a0a3408e
KB		 2699}
2700
2701static void nvme_error_resume(struct pci_dev *pdev)
2702{
2703 pci_cleanup_aer_uncorrect_error_status(pdev);
2704}
2705
1d352035 2706static const struct pci_error_handlers nvme_err_handler = {
b60503ba 2707 .error_detected = nvme_error_detected,
b60503ba
MW		 2708 .slot_reset = nvme_slot_reset,
2709 .resume = nvme_error_resume,
775755ed
CH		 2710 .reset_prepare = nvme_reset_prepare,
2711 .reset_done = nvme_reset_done,
b60503ba
MW		 2712};
2713
6eb0d698 2714static const struct pci_device_id nvme_id_table[] = {
106198ed 2715 { PCI_VDEVICE(INTEL, 0x0953),
08095e70 2716 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 2717 NVME_QUIRK_DEALLOCATE_ZEROES, },
99466e70
KB		 2718 { PCI_VDEVICE(INTEL, 0x0a53),
2719 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 2720 NVME_QUIRK_DEALLOCATE_ZEROES, },
99466e70
KB		 2721 { PCI_VDEVICE(INTEL, 0x0a54),
2722 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 2723 NVME_QUIRK_DEALLOCATE_ZEROES, },
f99cb7af
DWF		 2724 { PCI_VDEVICE(INTEL, 0x0a55),
2725 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2726 NVME_QUIRK_DEALLOCATE_ZEROES, },
50af47d0
AL		 2727 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */
2728 .driver_data = NVME_QUIRK_NO_DEEPEST_PS },
540c801c
KB		 2729 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */
2730 .driver_data = NVME_QUIRK_IDENTIFY_CNS, },
0302ae60
MP		 2731 { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */
2732 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
54adc010
GP		 2733 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
2734 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
8c97eecc
JL		 2735 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */
2736 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
015282c9
WW		 2737 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
2738 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
d554b5e1
MP		 2739 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */
2740 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2741 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */
2742 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
608cc4b1
CH		 2743 { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */
2744 .driver_data = NVME_QUIRK_LIGHTNVM, },
2745 { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */
2746 .driver_data = NVME_QUIRK_LIGHTNVM, },
ea48e877
WX		 2747 { PCI_DEVICE(0x1d1d, 0x2601), /* CNEX Granby */
2748 .driver_data = NVME_QUIRK_LIGHTNVM, },
b60503ba 2749 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
c74dc780 2750 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) },
124298bd 2751 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
b60503ba
MW		 2752 { 0, }
2753};
2754MODULE_DEVICE_TABLE(pci, nvme_id_table);
2755
2756static struct pci_driver nvme_driver = {
2757 .name = "nvme",
2758 .id_table = nvme_id_table,
2759 .probe = nvme_probe,
8d85fce7 2760 .remove = nvme_remove,
09ece142 2761 .shutdown = nvme_shutdown,
cd638946
KB		 2762 .driver = {
2763 .pm = &nvme_dev_pm_ops,
2764 },
13880f5b 2765 .sriov_configure = nvme_pci_sriov_configure,
b60503ba
MW		 2766 .err_handler = &nvme_err_handler,
2767};
2768
2769static int __init nvme_init(void)
2770{
9a6327d2 2771 return pci_register_driver(&nvme_driver);
b60503ba
MW		 2772}
2773
2774static void __exit nvme_exit(void)
2775{
2776 pci_unregister_driver(&nvme_driver);
03e0f3a6 2777 flush_workqueue(nvme_wq);
21bd78bc 2778 _nvme_check_size();
b60503ba
MW		 2779}
2780
2781MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2782MODULE_LICENSE("GPL");
c78b4713 2783MODULE_VERSION("1.0");
b60503ba
MW		 2784module_init(nvme_init);
2785module_exit(nvme_exit);
Linux 6.x block layer and io_uring tree(s)