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nvme-tcp: fix possible hang caused during ctrl deletion
[linux-2.6-block.git] / drivers / nvme / host / pci.c
CommitLineData
5f37396d 1// SPDX-License-Identifier: GPL-2.0
b60503ba
MW		 2/*
3 * NVM Express device driver
6eb0d698 4 * Copyright (c) 2011-2014, Intel Corporation.
b60503ba
MW		 5 */
6
df4f9bc4 7#include <linux/acpi.h>
a0a3408e 8#include <linux/aer.h>
18119775 9#include <linux/async.h>
b60503ba 10#include <linux/blkdev.h>
a4aea562 11#include <linux/blk-mq.h>
dca51e78 12#include <linux/blk-mq-pci.h>
fe45e630 13#include <linux/blk-integrity.h>
ff5350a8 14#include <linux/dmi.h>
b60503ba
MW		 15#include <linux/init.h>
16#include <linux/interrupt.h>
17#include <linux/io.h>
dc90f084 18#include <linux/memremap.h>
b60503ba
MW		 19#include <linux/mm.h>
20#include <linux/module.h>
77bf25ea 21#include <linux/mutex.h>
d0877473 22#include <linux/once.h>
b60503ba 23#include <linux/pci.h>
d916b1be 24#include <linux/suspend.h>
e1e5e564 25#include <linux/t10-pi.h>
b60503ba 26#include <linux/types.h>
2f8e2c87 27#include <linux/io-64-nonatomic-lo-hi.h>
20d3bb92 28#include <linux/io-64-nonatomic-hi-lo.h>
a98e58e5 29#include <linux/sed-opal.h>
0f238ff5 30#include <linux/pci-p2pdma.h>
797a796a 31
604c01d5 32#include "trace.h"
f11bb3e2
CH		 33#include "nvme.h"
34
c1e0cc7e 35#define SQ_SIZE(q) ((q)->q_depth << (q)->sqes)
8a1d09a6 36#define CQ_SIZE(q) ((q)->q_depth * sizeof(struct nvme_completion))
c965809c 37
a7a7cbe3 38#define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc))
9d43cf64 39
943e942e
JA		 40/*
41 * These can be higher, but we need to ensure that any command doesn't
42 * require an sg allocation that needs more than a page of data.
43 */
44#define NVME_MAX_KB_SZ 4096
45#define NVME_MAX_SEGS 127
46
58ffacb5 47static int use_threaded_interrupts;
2e21e445 48module_param(use_threaded_interrupts, int, 0444);
58ffacb5 49
8ffaadf7 50static bool use_cmb_sqes = true;
69f4eb9f 51module_param(use_cmb_sqes, bool, 0444);
8ffaadf7
JD		 52MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
53
87ad72a5
CH		 54static unsigned int max_host_mem_size_mb = 128;
55module_param(max_host_mem_size_mb, uint, 0444);
56MODULE_PARM_DESC(max_host_mem_size_mb,
57 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
1fa6aead 58
a7a7cbe3
CK		 59static unsigned int sgl_threshold = SZ_32K;
60module_param(sgl_threshold, uint, 0644);
61MODULE_PARM_DESC(sgl_threshold,
62 "Use SGLs when average request segment size is larger or equal to "
63 "this size. Use 0 to disable SGLs.");
64
27453b45
SG		 65#define NVME_PCI_MIN_QUEUE_SIZE 2
66#define NVME_PCI_MAX_QUEUE_SIZE 4095
b27c1e68 67static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
68static const struct kernel_param_ops io_queue_depth_ops = {
69 .set = io_queue_depth_set,
61f3b896 70 .get = param_get_uint,
b27c1e68 71};
72
61f3b896 73static unsigned int io_queue_depth = 1024;
b27c1e68 74module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
27453b45 75MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2 and < 4096");
b27c1e68 76
9c9e76d5
WZ		 77static int io_queue_count_set(const char *val, const struct kernel_param *kp)
78{
79 unsigned int n;
80 int ret;
81
82 ret = kstrtouint(val, 10, &n);
83 if (ret != 0 || n > num_possible_cpus())
84 return -EINVAL;
85 return param_set_uint(val, kp);
86}
87
88static const struct kernel_param_ops io_queue_count_ops = {
89 .set = io_queue_count_set,
90 .get = param_get_uint,
91};
92
3f68baf7 93static unsigned int write_queues;
9c9e76d5 94module_param_cb(write_queues, &io_queue_count_ops, &write_queues, 0644);
3b6592f7
JA		 95MODULE_PARM_DESC(write_queues,
96 "Number of queues to use for writes. If not set, reads and writes "
97 "will share a queue set.");
98
3f68baf7 99static unsigned int poll_queues;
9c9e76d5 100module_param_cb(poll_queues, &io_queue_count_ops, &poll_queues, 0644);
4b04cc6a
JA		 101MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO.");
102
df4f9bc4
DB		 103static bool noacpi;
104module_param(noacpi, bool, 0444);
105MODULE_PARM_DESC(noacpi, "disable acpi bios quirks");
106
1c63dc66
CH		 107struct nvme_dev;
108struct nvme_queue;
b3fffdef 109
a5cdb68c 110static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
8fae268b 111static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode);
d4b4ff8e 112
1c63dc66
CH		 113/*
114 * Represents an NVM Express device. Each nvme_dev is a PCI function.
115 */
116struct nvme_dev {
147b27e4 117 struct nvme_queue *queues;
1c63dc66
CH		 118 struct blk_mq_tag_set tagset;
119 struct blk_mq_tag_set admin_tagset;
120 u32 __iomem *dbs;
121 struct device *dev;
122 struct dma_pool *prp_page_pool;
123 struct dma_pool *prp_small_pool;
1c63dc66
CH		 124 unsigned online_queues;
125 unsigned max_qid;
e20ba6e1 126 unsigned io_queues[HCTX_MAX_TYPES];
22b55601 127 unsigned int num_vecs;
7442ddce 128 u32 q_depth;
c1e0cc7e 129 int io_sqes;
1c63dc66 130 u32 db_stride;
1c63dc66 131 void __iomem *bar;
97f6ef64 132 unsigned long bar_mapped_size;
5c8809e6 133 struct work_struct remove_work;
77bf25ea 134 struct mutex shutdown_lock;
1c63dc66 135 bool subsystem;
1c63dc66 136 u64 cmb_size;
0f238ff5 137 bool cmb_use_sqes;
1c63dc66 138 u32 cmbsz;
202021c1 139 u32 cmbloc;
1c63dc66 140 struct nvme_ctrl ctrl;
d916b1be 141 u32 last_ps;
a5df5e79 142 bool hmb;
87ad72a5 143
943e942e
JA		 144 mempool_t *iod_mempool;
145
87ad72a5 146 /* shadow doorbell buffer support: */
f9f38e33
HK		 147 u32 *dbbuf_dbs;
148 dma_addr_t dbbuf_dbs_dma_addr;
149 u32 *dbbuf_eis;
150 dma_addr_t dbbuf_eis_dma_addr;
87ad72a5
CH		 151
152 /* host memory buffer support: */
153 u64 host_mem_size;
154 u32 nr_host_mem_descs;
4033f35d 155 dma_addr_t host_mem_descs_dma;
87ad72a5
CH		 156 struct nvme_host_mem_buf_desc *host_mem_descs;
157 void **host_mem_desc_bufs;
2a5bcfdd
WZ		 158 unsigned int nr_allocated_queues;
159 unsigned int nr_write_queues;
160 unsigned int nr_poll_queues;
0521905e
KB		 161
162 bool attrs_added;
4d115420 163};
1fa6aead 164
b27c1e68 165static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
166{
27453b45
SG		 167 return param_set_uint_minmax(val, kp, NVME_PCI_MIN_QUEUE_SIZE,
168 NVME_PCI_MAX_QUEUE_SIZE);
b27c1e68 169}
170
f9f38e33
HK		 171static inline unsigned int sq_idx(unsigned int qid, u32 stride)
172{
173 return qid * 2 * stride;
174}
175
176static inline unsigned int cq_idx(unsigned int qid, u32 stride)
177{
178 return (qid * 2 + 1) * stride;
179}
180
1c63dc66
CH		 181static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
182{
183 return container_of(ctrl, struct nvme_dev, ctrl);
184}
185
b60503ba
MW		 186/*
187 * An NVM Express queue. Each device has at least two (one for admin
188 * commands and one for I/O commands).
189 */
190struct nvme_queue {
091b6092 191 struct nvme_dev *dev;
1ab0cd69 192 spinlock_t sq_lock;
c1e0cc7e 193 void *sq_cmds;
3a7afd8e
CH		 194 /* only used for poll queues: */
195 spinlock_t cq_poll_lock ____cacheline_aligned_in_smp;
74943d45 196 struct nvme_completion *cqes;
b60503ba
MW		 197 dma_addr_t sq_dma_addr;
198 dma_addr_t cq_dma_addr;
b60503ba 199 u32 __iomem *q_db;
7442ddce 200 u32 q_depth;
7c349dde 201 u16 cq_vector;
b60503ba 202 u16 sq_tail;
38210800 203 u16 last_sq_tail;
b60503ba 204 u16 cq_head;
c30341dc 205 u16 qid;
e9539f47 206 u8 cq_phase;
c1e0cc7e 207 u8 sqes;
4e224106
CH		 208 unsigned long flags;
209#define NVMEQ_ENABLED 0
63223078 210#define NVMEQ_SQ_CMB 1
d1ed6aa1 211#define NVMEQ_DELETE_ERROR 2
7c349dde 212#define NVMEQ_POLLED 3
f9f38e33
HK		 213 u32 *dbbuf_sq_db;
214 u32 *dbbuf_cq_db;
215 u32 *dbbuf_sq_ei;
216 u32 *dbbuf_cq_ei;
d1ed6aa1 217 struct completion delete_done;
b60503ba
MW		 218};
219
71bd150c 220/*
9b048119
CH		 221 * The nvme_iod describes the data in an I/O.
222 *
223 * The sg pointer contains the list of PRP/SGL chunk allocations in addition
224 * to the actual struct scatterlist.
71bd150c
CH		 225 */
226struct nvme_iod {
d49187e9 227 struct nvme_request req;
af7fae85 228 struct nvme_command cmd;
a7a7cbe3 229 bool use_sgl;
52da4f3f 230 bool aborted;
c372cdd1
KB		 231 s8 nr_allocations; /* PRP list pool allocations. 0 means small
232 pool in use */
dff824b2 233 unsigned int dma_len; /* length of single DMA segment mapping */
c4c22c52 234 dma_addr_t first_dma;
783b94bd 235 dma_addr_t meta_dma;
91fb2b60 236 struct sg_table sgt;
b60503ba
MW		 237};
238
2a5bcfdd 239static inline unsigned int nvme_dbbuf_size(struct nvme_dev *dev)
3b6592f7 240{
2a5bcfdd 241 return dev->nr_allocated_queues * 8 * dev->db_stride;
f9f38e33
HK		 242}
243
244static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
245{
2a5bcfdd 246 unsigned int mem_size = nvme_dbbuf_size(dev);
f9f38e33 247
58847f12
KB		 248 if (dev->dbbuf_dbs) {
249 /*
250 * Clear the dbbuf memory so the driver doesn't observe stale
251 * values from the previous instantiation.
252 */
253 memset(dev->dbbuf_dbs, 0, mem_size);
254 memset(dev->dbbuf_eis, 0, mem_size);
f9f38e33 255 return 0;
58847f12 256 }
f9f38e33
HK		 257
258 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
259 &dev->dbbuf_dbs_dma_addr,
260 GFP_KERNEL);
261 if (!dev->dbbuf_dbs)
262 return -ENOMEM;
263 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
264 &dev->dbbuf_eis_dma_addr,
265 GFP_KERNEL);
266 if (!dev->dbbuf_eis) {
267 dma_free_coherent(dev->dev, mem_size,
268 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
269 dev->dbbuf_dbs = NULL;
270 return -ENOMEM;
271 }
272
273 return 0;
274}
275
276static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
277{
2a5bcfdd 278 unsigned int mem_size = nvme_dbbuf_size(dev);
f9f38e33
HK		 279
280 if (dev->dbbuf_dbs) {
281 dma_free_coherent(dev->dev, mem_size,
282 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
283 dev->dbbuf_dbs = NULL;
284 }
285 if (dev->dbbuf_eis) {
286 dma_free_coherent(dev->dev, mem_size,
287 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
288 dev->dbbuf_eis = NULL;
289 }
290}
291
292static void nvme_dbbuf_init(struct nvme_dev *dev,
293 struct nvme_queue *nvmeq, int qid)
294{
295 if (!dev->dbbuf_dbs || !qid)
296 return;
297
298 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
299 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
300 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
301 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
302}
303
0f0d2c87
MI		 304static void nvme_dbbuf_free(struct nvme_queue *nvmeq)
305{
306 if (!nvmeq->qid)
307 return;
308
309 nvmeq->dbbuf_sq_db = NULL;
310 nvmeq->dbbuf_cq_db = NULL;
311 nvmeq->dbbuf_sq_ei = NULL;
312 nvmeq->dbbuf_cq_ei = NULL;
313}
314
f9f38e33
HK		 315static void nvme_dbbuf_set(struct nvme_dev *dev)
316{
f66e2804 317 struct nvme_command c = { };
0f0d2c87 318 unsigned int i;
f9f38e33
HK		 319
320 if (!dev->dbbuf_dbs)
321 return;
322
f9f38e33
HK		 323 c.dbbuf.opcode = nvme_admin_dbbuf;
324 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
325 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
326
327 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
9bdcfb10 328 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
f9f38e33
HK		 329 /* Free memory and continue on */
330 nvme_dbbuf_dma_free(dev);
0f0d2c87
MI		 331
332 for (i = 1; i <= dev->online_queues; i++)
333 nvme_dbbuf_free(&dev->queues[i]);
f9f38e33
HK		 334 }
335}
336
337static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
338{
339 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
340}
341
342/* Update dbbuf and return true if an MMIO is required */
343static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
344 volatile u32 *dbbuf_ei)
345{
346 if (dbbuf_db) {
347 u16 old_value;
348
349 /*
350 * Ensure that the queue is written before updating
351 * the doorbell in memory
352 */
353 wmb();
354
355 old_value = *dbbuf_db;
356 *dbbuf_db = value;
357
f1ed3df2
MW		 358 /*
359 * Ensure that the doorbell is updated before reading the event
360 * index from memory. The controller needs to provide similar
361 * ordering to ensure the envent index is updated before reading
362 * the doorbell.
363 */
364 mb();
365
f9f38e33
HK		 366 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value))
367 return false;
368 }
369
370 return true;
b60503ba
MW		 371}
372
ac3dd5bd
JA		 373/*
374 * Will slightly overestimate the number of pages needed. This is OK
375 * as it only leads to a small amount of wasted memory for the lifetime of
376 * the I/O.
377 */
b13c6393 378static int nvme_pci_npages_prp(void)
ac3dd5bd 379{
b13c6393 380 unsigned nprps = DIV_ROUND_UP(NVME_MAX_KB_SZ + NVME_CTRL_PAGE_SIZE,
6c3c05b0 381 NVME_CTRL_PAGE_SIZE);
ac3dd5bd
JA		 382 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
383}
384
a7a7cbe3
CK		 385/*
386 * Calculates the number of pages needed for the SGL segments. For example a 4k
387 * page can accommodate 256 SGL descriptors.
388 */
b13c6393 389static int nvme_pci_npages_sgl(void)
ac3dd5bd 390{
b13c6393
CK		 391 return DIV_ROUND_UP(NVME_MAX_SEGS * sizeof(struct nvme_sgl_desc),
392 PAGE_SIZE);
f4800d6d 393}
ac3dd5bd 394
b13c6393 395static size_t nvme_pci_iod_alloc_size(void)
f4800d6d 396{
b13c6393 397 size_t npages = max(nvme_pci_npages_prp(), nvme_pci_npages_sgl());
a7a7cbe3 398
b13c6393
CK		 399 return sizeof(__le64 *) * npages +
400 sizeof(struct scatterlist) * NVME_MAX_SEGS;
f4800d6d 401}
ac3dd5bd 402
a4aea562
MB		 403static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
404 unsigned int hctx_idx)
e85248e5 405{
a4aea562 406 struct nvme_dev *dev = data;
147b27e4 407 struct nvme_queue *nvmeq = &dev->queues[0];
a4aea562 408
42483228
KB		 409 WARN_ON(hctx_idx != 0);
410 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
42483228 411
a4aea562
MB		 412 hctx->driver_data = nvmeq;
413 return 0;
e85248e5
MW		 414}
415
a4aea562
MB		 416static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
417 unsigned int hctx_idx)
b60503ba 418{
a4aea562 419 struct nvme_dev *dev = data;
147b27e4 420 struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
a4aea562 421
42483228 422 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
a4aea562
MB		 423 hctx->driver_data = nvmeq;
424 return 0;
b60503ba
MW		 425}
426
e559398f
CH		 427static int nvme_pci_init_request(struct blk_mq_tag_set *set,
428 struct request *req, unsigned int hctx_idx,
429 unsigned int numa_node)
b60503ba 430{
d6296d39 431 struct nvme_dev *dev = set->driver_data;
f4800d6d 432 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
59e29ce6
SG		 433
434 nvme_req(req)->ctrl = &dev->ctrl;
f4b9e6c9 435 nvme_req(req)->cmd = &iod->cmd;
a4aea562
MB		 436 return 0;
437}
438
3b6592f7
JA		 439static int queue_irq_offset(struct nvme_dev *dev)
440{
441 /* if we have more than 1 vec, admin queue offsets us by 1 */
442 if (dev->num_vecs > 1)
443 return 1;
444
445 return 0;
446}
447
a4e1d0b7 448static void nvme_pci_map_queues(struct blk_mq_tag_set *set)
dca51e78
CH		 449{
450 struct nvme_dev *dev = set->driver_data;
3b6592f7
JA		 451 int i, qoff, offset;
452
453 offset = queue_irq_offset(dev);
454 for (i = 0, qoff = 0; i < set->nr_maps; i++) {
455 struct blk_mq_queue_map *map = &set->map[i];
456
457 map->nr_queues = dev->io_queues[i];
458 if (!map->nr_queues) {
e20ba6e1 459 BUG_ON(i == HCTX_TYPE_DEFAULT);
7e849dd9 460 continue;
3b6592f7
JA		 461 }
462
4b04cc6a
JA		 463 /*
464 * The poll queue(s) doesn't have an IRQ (and hence IRQ
465 * affinity), so use the regular blk-mq cpu mapping
466 */
3b6592f7 467 map->queue_offset = qoff;
cb9e0e50 468 if (i != HCTX_TYPE_POLL && offset)
4b04cc6a
JA		 469 blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset);
470 else
471 blk_mq_map_queues(map);
3b6592f7
JA		 472 qoff += map->nr_queues;
473 offset += map->nr_queues;
474 }
dca51e78
CH		 475}
476
38210800
KB		 477/*
478 * Write sq tail if we are asked to, or if the next command would wrap.
479 */
480static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq)
04f3eafd 481{
38210800
KB		 482 if (!write_sq) {
483 u16 next_tail = nvmeq->sq_tail + 1;
484
485 if (next_tail == nvmeq->q_depth)
486 next_tail = 0;
487 if (next_tail != nvmeq->last_sq_tail)
488 return;
489 }
490
04f3eafd
JA		 491 if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail,
492 nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei))
493 writel(nvmeq->sq_tail, nvmeq->q_db);
38210800 494 nvmeq->last_sq_tail = nvmeq->sq_tail;
04f3eafd
JA		 495}
496
3233b94c
JA		 497static inline void nvme_sq_copy_cmd(struct nvme_queue *nvmeq,
498 struct nvme_command *cmd)
b60503ba 499{
c1e0cc7e 500 memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes),
3233b94c 501 absolute_pointer(cmd), sizeof(*cmd));
90ea5ca4
CH		 502 if (++nvmeq->sq_tail == nvmeq->q_depth)
503 nvmeq->sq_tail = 0;
04f3eafd
JA		 504}
505
506static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx)
507{
508 struct nvme_queue *nvmeq = hctx->driver_data;
509
510 spin_lock(&nvmeq->sq_lock);
38210800
KB		 511 if (nvmeq->sq_tail != nvmeq->last_sq_tail)
512 nvme_write_sq_db(nvmeq, true);
90ea5ca4 513 spin_unlock(&nvmeq->sq_lock);
b60503ba
MW		 514}
515
a7a7cbe3 516static void **nvme_pci_iod_list(struct request *req)
b60503ba 517{
f4800d6d 518 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
91fb2b60 519 return (void **)(iod->sgt.sgl + blk_rq_nr_phys_segments(req));
b60503ba
MW		 520}
521
955b1b5a
MI		 522static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req)
523{
a53232cb 524 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
20469a37 525 int nseg = blk_rq_nr_phys_segments(req);
955b1b5a
MI		 526 unsigned int avg_seg_size;
527
20469a37 528 avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
955b1b5a 529
253a0b76 530 if (!nvme_ctrl_sgl_supported(&dev->ctrl))
955b1b5a 531 return false;
a53232cb 532 if (!nvmeq->qid)
955b1b5a
MI		 533 return false;
534 if (!sgl_threshold || avg_seg_size < sgl_threshold)
535 return false;
536 return true;
537}
538
9275c206 539static void nvme_free_prps(struct nvme_dev *dev, struct request *req)
b60503ba 540{
6c3c05b0 541 const int last_prp = NVME_CTRL_PAGE_SIZE / sizeof(__le64) - 1;
9275c206
CH		 542 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
543 dma_addr_t dma_addr = iod->first_dma;
eca18b23 544 int i;
eca18b23 545
c372cdd1 546 for (i = 0; i < iod->nr_allocations; i++) {
9275c206
CH		 547 __le64 *prp_list = nvme_pci_iod_list(req)[i];
548 dma_addr_t next_dma_addr = le64_to_cpu(prp_list[last_prp]);
549
550 dma_pool_free(dev->prp_page_pool, prp_list, dma_addr);
551 dma_addr = next_dma_addr;
7fe07d14 552 }
9275c206 553}
dff824b2 554
9275c206
CH		 555static void nvme_free_sgls(struct nvme_dev *dev, struct request *req)
556{
557 const int last_sg = SGES_PER_PAGE - 1;
558 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
559 dma_addr_t dma_addr = iod->first_dma;
560 int i;
dff824b2 561
c372cdd1 562 for (i = 0; i < iod->nr_allocations; i++) {
9275c206
CH		 563 struct nvme_sgl_desc *sg_list = nvme_pci_iod_list(req)[i];
564 dma_addr_t next_dma_addr = le64_to_cpu((sg_list[last_sg]).addr);
dff824b2 565
9275c206
CH		 566 dma_pool_free(dev->prp_page_pool, sg_list, dma_addr);
567 dma_addr = next_dma_addr;
568 }
9275c206 569}
a7a7cbe3 570
9275c206
CH		 571static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
572{
573 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3 574
9275c206
CH		 575 if (iod->dma_len) {
576 dma_unmap_page(dev->dev, iod->first_dma, iod->dma_len,
577 rq_dma_dir(req));
578 return;
eca18b23 579 }
ac3dd5bd 580
91fb2b60
LG		 581 WARN_ON_ONCE(!iod->sgt.nents);
582
583 dma_unmap_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req), 0);
9275c206 584
c372cdd1 585 if (iod->nr_allocations == 0)
9275c206
CH		 586 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0],
587 iod->first_dma);
588 else if (iod->use_sgl)
589 nvme_free_sgls(dev, req);
590 else
591 nvme_free_prps(dev, req);
91fb2b60 592 mempool_free(iod->sgt.sgl, dev->iod_mempool);
b4ff9c8d
KB		 593}
594
d0877473
KB		 595static void nvme_print_sgl(struct scatterlist *sgl, int nents)
596{
597 int i;
598 struct scatterlist *sg;
599
600 for_each_sg(sgl, sg, nents, i) {
601 dma_addr_t phys = sg_phys(sg);
602 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
603 "dma_address:%pad dma_length:%d\n",
604 i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
605 sg_dma_len(sg));
606 }
607}
608
a7a7cbe3
CK		 609static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
610 struct request *req, struct nvme_rw_command *cmnd)
ff22b54f 611{
f4800d6d 612 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
99802a7a 613 struct dma_pool *pool;
b131c61d 614 int length = blk_rq_payload_bytes(req);
91fb2b60 615 struct scatterlist *sg = iod->sgt.sgl;
ff22b54f
MW		 616 int dma_len = sg_dma_len(sg);
617 u64 dma_addr = sg_dma_address(sg);
6c3c05b0 618 int offset = dma_addr & (NVME_CTRL_PAGE_SIZE - 1);
e025344c 619 __le64 *prp_list;
a7a7cbe3 620 void **list = nvme_pci_iod_list(req);
e025344c 621 dma_addr_t prp_dma;
eca18b23 622 int nprps, i;
ff22b54f 623
6c3c05b0 624 length -= (NVME_CTRL_PAGE_SIZE - offset);
5228b328
JS		 625 if (length <= 0) {
626 iod->first_dma = 0;
a7a7cbe3 627 goto done;
5228b328 628 }
ff22b54f 629
6c3c05b0 630 dma_len -= (NVME_CTRL_PAGE_SIZE - offset);
ff22b54f 631 if (dma_len) {
6c3c05b0 632 dma_addr += (NVME_CTRL_PAGE_SIZE - offset);
ff22b54f
MW		 633 } else {
634 sg = sg_next(sg);
635 dma_addr = sg_dma_address(sg);
636 dma_len = sg_dma_len(sg);
637 }
638
6c3c05b0 639 if (length <= NVME_CTRL_PAGE_SIZE) {
edd10d33 640 iod->first_dma = dma_addr;
a7a7cbe3 641 goto done;
e025344c
SMM		 642 }
643
6c3c05b0 644 nprps = DIV_ROUND_UP(length, NVME_CTRL_PAGE_SIZE);
99802a7a
MW		 645 if (nprps <= (256 / 8)) {
646 pool = dev->prp_small_pool;
c372cdd1 647 iod->nr_allocations = 0;
99802a7a
MW		 648 } else {
649 pool = dev->prp_page_pool;
c372cdd1 650 iod->nr_allocations = 1;
99802a7a
MW		 651 }
652
69d2b571 653 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
b77954cb 654 if (!prp_list) {
c372cdd1 655 iod->nr_allocations = -1;
86eea289 656 return BLK_STS_RESOURCE;
b77954cb 657 }
eca18b23
MW		 658 list[0] = prp_list;
659 iod->first_dma = prp_dma;
e025344c
SMM		 660 i = 0;
661 for (;;) {
6c3c05b0 662 if (i == NVME_CTRL_PAGE_SIZE >> 3) {
e025344c 663 __le64 *old_prp_list = prp_list;
69d2b571 664 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
eca18b23 665 if (!prp_list)
fa073216 666 goto free_prps;
c372cdd1 667 list[iod->nr_allocations++] = prp_list;
7523d834
MW		 668 prp_list[0] = old_prp_list[i - 1];
669 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
670 i = 1;
e025344c
SMM		 671 }
672 prp_list[i++] = cpu_to_le64(dma_addr);
6c3c05b0
CK		 673 dma_len -= NVME_CTRL_PAGE_SIZE;
674 dma_addr += NVME_CTRL_PAGE_SIZE;
675 length -= NVME_CTRL_PAGE_SIZE;
e025344c
SMM		 676 if (length <= 0)
677 break;
678 if (dma_len > 0)
679 continue;
86eea289
KB		 680 if (unlikely(dma_len < 0))
681 goto bad_sgl;
e025344c
SMM		 682 sg = sg_next(sg);
683 dma_addr = sg_dma_address(sg);
684 dma_len = sg_dma_len(sg);
ff22b54f 685 }
a7a7cbe3 686done:
91fb2b60 687 cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sgt.sgl));
a7a7cbe3 688 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
86eea289 689 return BLK_STS_OK;
fa073216
CH		 690free_prps:
691 nvme_free_prps(dev, req);
692 return BLK_STS_RESOURCE;
693bad_sgl:
91fb2b60 694 WARN(DO_ONCE(nvme_print_sgl, iod->sgt.sgl, iod->sgt.nents),
d0877473 695 "Invalid SGL for payload:%d nents:%d\n",
91fb2b60 696 blk_rq_payload_bytes(req), iod->sgt.nents);
86eea289 697 return BLK_STS_IOERR;
ff22b54f
MW		 698}
699
a7a7cbe3
CK		 700static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
701 struct scatterlist *sg)
702{
703 sge->addr = cpu_to_le64(sg_dma_address(sg));
704 sge->length = cpu_to_le32(sg_dma_len(sg));
705 sge->type = NVME_SGL_FMT_DATA_DESC << 4;
706}
707
708static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
709 dma_addr_t dma_addr, int entries)
710{
711 sge->addr = cpu_to_le64(dma_addr);
712 if (entries < SGES_PER_PAGE) {
713 sge->length = cpu_to_le32(entries * sizeof(*sge));
714 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
715 } else {
716 sge->length = cpu_to_le32(PAGE_SIZE);
717 sge->type = NVME_SGL_FMT_SEG_DESC << 4;
718 }
719}
720
721static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
91fb2b60 722 struct request *req, struct nvme_rw_command *cmd)
a7a7cbe3
CK		 723{
724 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3
CK		 725 struct dma_pool *pool;
726 struct nvme_sgl_desc *sg_list;
91fb2b60
LG		 727 struct scatterlist *sg = iod->sgt.sgl;
728 unsigned int entries = iod->sgt.nents;
a7a7cbe3 729 dma_addr_t sgl_dma;
b0f2853b 730 int i = 0;
a7a7cbe3 731
a7a7cbe3
CK		 732 /* setting the transfer type as SGL */
733 cmd->flags = NVME_CMD_SGL_METABUF;
734
b0f2853b 735 if (entries == 1) {
a7a7cbe3
CK		 736 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
737 return BLK_STS_OK;
738 }
739
740 if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
741 pool = dev->prp_small_pool;
c372cdd1 742 iod->nr_allocations = 0;
a7a7cbe3
CK		 743 } else {
744 pool = dev->prp_page_pool;
c372cdd1 745 iod->nr_allocations = 1;
a7a7cbe3
CK		 746 }
747
748 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
749 if (!sg_list) {
c372cdd1 750 iod->nr_allocations = -1;
a7a7cbe3
CK		 751 return BLK_STS_RESOURCE;
752 }
753
754 nvme_pci_iod_list(req)[0] = sg_list;
755 iod->first_dma = sgl_dma;
756
757 nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
758
759 do {
760 if (i == SGES_PER_PAGE) {
761 struct nvme_sgl_desc *old_sg_desc = sg_list;
762 struct nvme_sgl_desc *link = &old_sg_desc[i - 1];
763
764 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
765 if (!sg_list)
fa073216 766 goto free_sgls;
a7a7cbe3
CK		 767
768 i = 0;
c372cdd1 769 nvme_pci_iod_list(req)[iod->nr_allocations++] = sg_list;
a7a7cbe3
CK		 770 sg_list[i++] = *link;
771 nvme_pci_sgl_set_seg(link, sgl_dma, entries);
772 }
773
774 nvme_pci_sgl_set_data(&sg_list[i++], sg);
a7a7cbe3 775 sg = sg_next(sg);
b0f2853b 776 } while (--entries > 0);
a7a7cbe3 777
a7a7cbe3 778 return BLK_STS_OK;
fa073216
CH		 779free_sgls:
780 nvme_free_sgls(dev, req);
781 return BLK_STS_RESOURCE;
a7a7cbe3
CK		 782}
783
dff824b2
CH		 784static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev,
785 struct request *req, struct nvme_rw_command *cmnd,
786 struct bio_vec *bv)
787{
788 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
6c3c05b0
CK		 789 unsigned int offset = bv->bv_offset & (NVME_CTRL_PAGE_SIZE - 1);
790 unsigned int first_prp_len = NVME_CTRL_PAGE_SIZE - offset;
dff824b2
CH		 791
792 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
793 if (dma_mapping_error(dev->dev, iod->first_dma))
794 return BLK_STS_RESOURCE;
795 iod->dma_len = bv->bv_len;
796
797 cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma);
798 if (bv->bv_len > first_prp_len)
799 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len);
359c1f88 800 return BLK_STS_OK;
dff824b2
CH		 801}
802
29791057
CH		 803static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev,
804 struct request *req, struct nvme_rw_command *cmnd,
805 struct bio_vec *bv)
806{
807 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
808
809 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
810 if (dma_mapping_error(dev->dev, iod->first_dma))
811 return BLK_STS_RESOURCE;
812 iod->dma_len = bv->bv_len;
813
049bf372 814 cmnd->flags = NVME_CMD_SGL_METABUF;
29791057
CH		 815 cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma);
816 cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len);
817 cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4;
359c1f88 818 return BLK_STS_OK;
29791057
CH		 819}
820
fc17b653 821static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
b131c61d 822 struct nvme_command *cmnd)
d29ec824 823{
f4800d6d 824 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
70479b71 825 blk_status_t ret = BLK_STS_RESOURCE;
91fb2b60 826 int rc;
d29ec824 827
dff824b2 828 if (blk_rq_nr_phys_segments(req) == 1) {
a53232cb 829 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
dff824b2
CH		 830 struct bio_vec bv = req_bvec(req);
831
832 if (!is_pci_p2pdma_page(bv.bv_page)) {
6c3c05b0 833 if (bv.bv_offset + bv.bv_len <= NVME_CTRL_PAGE_SIZE * 2)
dff824b2
CH		 834 return nvme_setup_prp_simple(dev, req,
835 &cmnd->rw, &bv);
29791057 836
a53232cb 837 if (nvmeq->qid && sgl_threshold &&
253a0b76 838 nvme_ctrl_sgl_supported(&dev->ctrl))
29791057
CH		 839 return nvme_setup_sgl_simple(dev, req,
840 &cmnd->rw, &bv);
dff824b2
CH		 841 }
842 }
843
844 iod->dma_len = 0;
91fb2b60
LG		 845 iod->sgt.sgl = mempool_alloc(dev->iod_mempool, GFP_ATOMIC);
846 if (!iod->sgt.sgl)
d43f1ccf 847 return BLK_STS_RESOURCE;
91fb2b60
LG		 848 sg_init_table(iod->sgt.sgl, blk_rq_nr_phys_segments(req));
849 iod->sgt.orig_nents = blk_rq_map_sg(req->q, req, iod->sgt.sgl);
850 if (!iod->sgt.orig_nents)
fa073216 851 goto out_free_sg;
d29ec824 852
91fb2b60
LG		 853 rc = dma_map_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req),
854 DMA_ATTR_NO_WARN);
855 if (rc) {
856 if (rc == -EREMOTEIO)
857 ret = BLK_STS_TARGET;
fa073216 858 goto out_free_sg;
91fb2b60 859 }
d29ec824 860
70479b71 861 iod->use_sgl = nvme_pci_use_sgls(dev, req);
955b1b5a 862 if (iod->use_sgl)
91fb2b60 863 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw);
a7a7cbe3
CK		 864 else
865 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
86eea289 866 if (ret != BLK_STS_OK)
fa073216
CH		 867 goto out_unmap_sg;
868 return BLK_STS_OK;
869
870out_unmap_sg:
91fb2b60 871 dma_unmap_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req), 0);
fa073216 872out_free_sg:
91fb2b60 873 mempool_free(iod->sgt.sgl, dev->iod_mempool);
4aedb705
CH		 874 return ret;
875}
3045c0d0 876
4aedb705
CH		 877static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req,
878 struct nvme_command *cmnd)
879{
880 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
00df5cb4 881
4aedb705
CH		 882 iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req),
883 rq_dma_dir(req), 0);
884 if (dma_mapping_error(dev->dev, iod->meta_dma))
885 return BLK_STS_IOERR;
886 cmnd->rw.metadata = cpu_to_le64(iod->meta_dma);
359c1f88 887 return BLK_STS_OK;
00df5cb4
MW		 888}
889
62451a2b 890static blk_status_t nvme_prep_rq(struct nvme_dev *dev, struct request *req)
edd10d33 891{
9b048119 892 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
ebe6d874 893 blk_status_t ret;
e1e5e564 894
52da4f3f 895 iod->aborted = false;
c372cdd1 896 iod->nr_allocations = -1;
91fb2b60 897 iod->sgt.nents = 0;
9b048119 898
62451a2b 899 ret = nvme_setup_cmd(req->q->queuedata, req);
fc17b653 900 if (ret)
f4800d6d 901 return ret;
a4aea562 902
fc17b653 903 if (blk_rq_nr_phys_segments(req)) {
62451a2b 904 ret = nvme_map_data(dev, req, &iod->cmd);
fc17b653 905 if (ret)
9b048119 906 goto out_free_cmd;
fc17b653 907 }
a4aea562 908
4aedb705 909 if (blk_integrity_rq(req)) {
62451a2b 910 ret = nvme_map_metadata(dev, req, &iod->cmd);
4aedb705
CH		 911 if (ret)
912 goto out_unmap_data;
913 }
914
aae239e1 915 blk_mq_start_request(req);
fc17b653 916 return BLK_STS_OK;
4aedb705
CH		 917out_unmap_data:
918 nvme_unmap_data(dev, req);
f9d03f96
CH		 919out_free_cmd:
920 nvme_cleanup_cmd(req);
ba1ca37e 921 return ret;
b60503ba 922}
e1e5e564 923
62451a2b
JA		 924/*
925 * NOTE: ns is NULL when called on the admin queue.
926 */
927static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
928 const struct blk_mq_queue_data *bd)
929{
930 struct nvme_queue *nvmeq = hctx->driver_data;
931 struct nvme_dev *dev = nvmeq->dev;
932 struct request *req = bd->rq;
933 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
934 blk_status_t ret;
935
936 /*
937 * We should not need to do this, but we're still using this to
938 * ensure we can drain requests on a dying queue.
939 */
940 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
941 return BLK_STS_IOERR;
942
943 if (unlikely(!nvme_check_ready(&dev->ctrl, req, true)))
944 return nvme_fail_nonready_command(&dev->ctrl, req);
945
946 ret = nvme_prep_rq(dev, req);
947 if (unlikely(ret))
948 return ret;
949 spin_lock(&nvmeq->sq_lock);
950 nvme_sq_copy_cmd(nvmeq, &iod->cmd);
951 nvme_write_sq_db(nvmeq, bd->last);
952 spin_unlock(&nvmeq->sq_lock);
953 return BLK_STS_OK;
954}
955
d62cbcf6
JA		 956static void nvme_submit_cmds(struct nvme_queue *nvmeq, struct request **rqlist)
957{
958 spin_lock(&nvmeq->sq_lock);
959 while (!rq_list_empty(*rqlist)) {
960 struct request *req = rq_list_pop(rqlist);
961 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
962
963 nvme_sq_copy_cmd(nvmeq, &iod->cmd);
964 }
965 nvme_write_sq_db(nvmeq, true);
966 spin_unlock(&nvmeq->sq_lock);
967}
968
969static bool nvme_prep_rq_batch(struct nvme_queue *nvmeq, struct request *req)
970{
971 /*
972 * We should not need to do this, but we're still using this to
973 * ensure we can drain requests on a dying queue.
974 */
975 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
976 return false;
977 if (unlikely(!nvme_check_ready(&nvmeq->dev->ctrl, req, true)))
978 return false;
979
980 req->mq_hctx->tags->rqs[req->tag] = req;
981 return nvme_prep_rq(nvmeq->dev, req) == BLK_STS_OK;
982}
983
984static void nvme_queue_rqs(struct request **rqlist)
985{
6bfec799 986 struct request *req, *next, *prev = NULL;
d62cbcf6
JA		 987 struct request *requeue_list = NULL;
988
6bfec799 989 rq_list_for_each_safe(rqlist, req, next) {
d62cbcf6
JA		 990 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
991
992 if (!nvme_prep_rq_batch(nvmeq, req)) {
993 /* detach 'req' and add to remainder list */
6bfec799
KB		 994 rq_list_move(rqlist, &requeue_list, req, prev);
995
996 req = prev;
997 if (!req)
998 continue;
d62cbcf6
JA		 999 }
1000
6bfec799 1001 if (!next || req->mq_hctx != next->mq_hctx) {
d62cbcf6 1002 /* detach rest of list, and submit */
6bfec799 1003 req->rq_next = NULL;
d62cbcf6 1004 nvme_submit_cmds(nvmeq, rqlist);
6bfec799
KB		 1005 *rqlist = next;
1006 prev = NULL;
1007 } else
1008 prev = req;
1009 }
d62cbcf6
JA		 1010
1011 *rqlist = requeue_list;
1012}
1013
c234a653 1014static __always_inline void nvme_pci_unmap_rq(struct request *req)
eee417b0 1015{
a53232cb
KB		 1016 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
1017 struct nvme_dev *dev = nvmeq->dev;
1018
1019 if (blk_integrity_rq(req)) {
1020 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a4aea562 1021
4aedb705
CH		 1022 dma_unmap_page(dev->dev, iod->meta_dma,
1023 rq_integrity_vec(req)->bv_len, rq_data_dir(req));
a53232cb
KB		 1024 }
1025
b15c592d 1026 if (blk_rq_nr_phys_segments(req))
4aedb705 1027 nvme_unmap_data(dev, req);
c234a653
JA		 1028}
1029
1030static void nvme_pci_complete_rq(struct request *req)
1031{
1032 nvme_pci_unmap_rq(req);
77f02a7a 1033 nvme_complete_rq(req);
b60503ba
MW		 1034}
1035
c234a653
JA		 1036static void nvme_pci_complete_batch(struct io_comp_batch *iob)
1037{
1038 nvme_complete_batch(iob, nvme_pci_unmap_rq);
1039}
1040
d783e0bd 1041/* We read the CQE phase first to check if the rest of the entry is valid */
750dde44 1042static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq)
d783e0bd 1043{
74943d45
KB		 1044 struct nvme_completion *hcqe = &nvmeq->cqes[nvmeq->cq_head];
1045
1046 return (le16_to_cpu(READ_ONCE(hcqe->status)) & 1) == nvmeq->cq_phase;
d783e0bd
MR		 1047}
1048
eb281c82 1049static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
b60503ba 1050{
eb281c82 1051 u16 head = nvmeq->cq_head;
adf68f21 1052
397c699f
KB		 1053 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
1054 nvmeq->dbbuf_cq_ei))
1055 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
eb281c82 1056}
aae239e1 1057
cfa27356
CH		 1058static inline struct blk_mq_tags *nvme_queue_tagset(struct nvme_queue *nvmeq)
1059{
1060 if (!nvmeq->qid)
1061 return nvmeq->dev->admin_tagset.tags[0];
1062 return nvmeq->dev->tagset.tags[nvmeq->qid - 1];
1063}
1064
c234a653
JA		 1065static inline void nvme_handle_cqe(struct nvme_queue *nvmeq,
1066 struct io_comp_batch *iob, u16 idx)
83a12fb7 1067{
74943d45 1068 struct nvme_completion *cqe = &nvmeq->cqes[idx];
62df8016 1069 __u16 command_id = READ_ONCE(cqe->command_id);
83a12fb7 1070 struct request *req;
adf68f21 1071
83a12fb7
SG		 1072 /*
1073 * AEN requests are special as they don't time out and can
1074 * survive any kind of queue freeze and often don't respond to
1075 * aborts. We don't even bother to allocate a struct request
1076 * for them but rather special case them here.
1077 */
62df8016 1078 if (unlikely(nvme_is_aen_req(nvmeq->qid, command_id))) {
83a12fb7
SG		 1079 nvme_complete_async_event(&nvmeq->dev->ctrl,
1080 cqe->status, &cqe->result);
a0fa9647 1081 return;
83a12fb7 1082 }
b60503ba 1083
e7006de6 1084 req = nvme_find_rq(nvme_queue_tagset(nvmeq), command_id);
50b7c243
XT		 1085 if (unlikely(!req)) {
1086 dev_warn(nvmeq->dev->ctrl.device,
1087 "invalid id %d completed on queue %d\n",
62df8016 1088 command_id, le16_to_cpu(cqe->sq_id));
50b7c243
XT		 1089 return;
1090 }
1091
604c01d5 1092 trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail);
c234a653
JA		 1093 if (!nvme_try_complete_req(req, cqe->status, cqe->result) &&
1094 !blk_mq_add_to_batch(req, iob, nvme_req(req)->status,
1095 nvme_pci_complete_batch))
ff029451 1096 nvme_pci_complete_rq(req);
83a12fb7 1097}
b60503ba 1098
5cb525c8
JA		 1099static inline void nvme_update_cq_head(struct nvme_queue *nvmeq)
1100{
a0aac973 1101 u32 tmp = nvmeq->cq_head + 1;
a8de6639
AD		 1102
1103 if (tmp == nvmeq->q_depth) {
5cb525c8 1104 nvmeq->cq_head = 0;
e2a366a4 1105 nvmeq->cq_phase ^= 1;
a8de6639
AD		 1106 } else {
1107 nvmeq->cq_head = tmp;
b60503ba 1108 }
a0fa9647
JA		 1109}
1110
c234a653
JA		 1111static inline int nvme_poll_cq(struct nvme_queue *nvmeq,
1112 struct io_comp_batch *iob)
a0fa9647 1113{
1052b8ac 1114 int found = 0;
b60503ba 1115
1052b8ac 1116 while (nvme_cqe_pending(nvmeq)) {
bf392a5d 1117 found++;
b69e2ef2
KB		 1118 /*
1119 * load-load control dependency between phase and the rest of
1120 * the cqe requires a full read memory barrier
1121 */
1122 dma_rmb();
c234a653 1123 nvme_handle_cqe(nvmeq, iob, nvmeq->cq_head);
5cb525c8 1124 nvme_update_cq_head(nvmeq);
920d13a8 1125 }
eb281c82 1126
324b494c 1127 if (found)
920d13a8 1128 nvme_ring_cq_doorbell(nvmeq);
5cb525c8 1129 return found;
b60503ba
MW		 1130}
1131
1132static irqreturn_t nvme_irq(int irq, void *data)
58ffacb5 1133{
58ffacb5 1134 struct nvme_queue *nvmeq = data;
4f502245 1135 DEFINE_IO_COMP_BATCH(iob);
5cb525c8 1136
4f502245
JA		 1137 if (nvme_poll_cq(nvmeq, &iob)) {
1138 if (!rq_list_empty(iob.req_list))
1139 nvme_pci_complete_batch(&iob);
05fae499 1140 return IRQ_HANDLED;
4f502245 1141 }
05fae499 1142 return IRQ_NONE;
58ffacb5
MW		 1143}
1144
1145static irqreturn_t nvme_irq_check(int irq, void *data)
1146{
1147 struct nvme_queue *nvmeq = data;
4e523547 1148
750dde44 1149 if (nvme_cqe_pending(nvmeq))
d783e0bd
MR		 1150 return IRQ_WAKE_THREAD;
1151 return IRQ_NONE;
58ffacb5
MW		 1152}
1153
0b2a8a9f 1154/*
fa059b85 1155 * Poll for completions for any interrupt driven queue
0b2a8a9f
CH		 1156 * Can be called from any context.
1157 */
fa059b85 1158static void nvme_poll_irqdisable(struct nvme_queue *nvmeq)
a0fa9647 1159{
3a7afd8e 1160 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
a0fa9647 1161
fa059b85 1162 WARN_ON_ONCE(test_bit(NVMEQ_POLLED, &nvmeq->flags));
442e19b7 1163
fa059b85 1164 disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
c234a653 1165 nvme_poll_cq(nvmeq, NULL);
fa059b85 1166 enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
a0fa9647
JA		 1167}
1168
5a72e899 1169static int nvme_poll(struct blk_mq_hw_ctx *hctx, struct io_comp_batch *iob)
dabcefab
JA		 1170{
1171 struct nvme_queue *nvmeq = hctx->driver_data;
dabcefab
JA		 1172 bool found;
1173
1174 if (!nvme_cqe_pending(nvmeq))
1175 return 0;
1176
3a7afd8e 1177 spin_lock(&nvmeq->cq_poll_lock);
c234a653 1178 found = nvme_poll_cq(nvmeq, iob);
3a7afd8e 1179 spin_unlock(&nvmeq->cq_poll_lock);
dabcefab 1180
dabcefab
JA		 1181 return found;
1182}
1183
ad22c355 1184static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
b60503ba 1185{
f866fc42 1186 struct nvme_dev *dev = to_nvme_dev(ctrl);
147b27e4 1187 struct nvme_queue *nvmeq = &dev->queues[0];
f66e2804 1188 struct nvme_command c = { };
b60503ba 1189
a4aea562 1190 c.common.opcode = nvme_admin_async_event;
ad22c355 1191 c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
3233b94c
JA		 1192
1193 spin_lock(&nvmeq->sq_lock);
1194 nvme_sq_copy_cmd(nvmeq, &c);
1195 nvme_write_sq_db(nvmeq, true);
1196 spin_unlock(&nvmeq->sq_lock);
f705f837
CH		 1197}
1198
b60503ba 1199static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
f705f837 1200{
f66e2804 1201 struct nvme_command c = { };
b60503ba 1202
b60503ba
MW		 1203 c.delete_queue.opcode = opcode;
1204 c.delete_queue.qid = cpu_to_le16(id);
1205
1c63dc66 1206 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1207}
1208
b60503ba 1209static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
a8e3e0bb 1210 struct nvme_queue *nvmeq, s16 vector)
b60503ba 1211{
f66e2804 1212 struct nvme_command c = { };
4b04cc6a
JA		 1213 int flags = NVME_QUEUE_PHYS_CONTIG;
1214
7c349dde 1215 if (!test_bit(NVMEQ_POLLED, &nvmeq->flags))
4b04cc6a 1216 flags |= NVME_CQ_IRQ_ENABLED;
b60503ba 1217
d29ec824 1218 /*
16772ae6 1219 * Note: we (ab)use the fact that the prp fields survive if no data
d29ec824
CH		 1220 * is attached to the request.
1221 */
b60503ba
MW		 1222 c.create_cq.opcode = nvme_admin_create_cq;
1223 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1224 c.create_cq.cqid = cpu_to_le16(qid);
1225 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1226 c.create_cq.cq_flags = cpu_to_le16(flags);
7c349dde 1227 c.create_cq.irq_vector = cpu_to_le16(vector);
b60503ba 1228
1c63dc66 1229 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1230}
1231
1232static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1233 struct nvme_queue *nvmeq)
1234{
9abd68ef 1235 struct nvme_ctrl *ctrl = &dev->ctrl;
f66e2804 1236 struct nvme_command c = { };
81c1cd98 1237 int flags = NVME_QUEUE_PHYS_CONTIG;
b60503ba 1238
9abd68ef
JA		 1239 /*
1240 * Some drives have a bug that auto-enables WRRU if MEDIUM isn't
1241 * set. Since URGENT priority is zeroes, it makes all queues
1242 * URGENT.
1243 */
1244 if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ)
1245 flags |= NVME_SQ_PRIO_MEDIUM;
1246
d29ec824 1247 /*
16772ae6 1248 * Note: we (ab)use the fact that the prp fields survive if no data
d29ec824
CH		 1249 * is attached to the request.
1250 */
b60503ba
MW		 1251 c.create_sq.opcode = nvme_admin_create_sq;
1252 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1253 c.create_sq.sqid = cpu_to_le16(qid);
1254 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1255 c.create_sq.sq_flags = cpu_to_le16(flags);
1256 c.create_sq.cqid = cpu_to_le16(qid);
1257
1c63dc66 1258 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1259}
1260
1261static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1262{
1263 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1264}
1265
1266static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1267{
1268 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1269}
1270
de671d61 1271static enum rq_end_io_ret abort_endio(struct request *req, blk_status_t error)
bc5fc7e4 1272{
a53232cb 1273 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
e44ac588 1274
27fa9bc5
CH		 1275 dev_warn(nvmeq->dev->ctrl.device,
1276 "Abort status: 0x%x", nvme_req(req)->status);
e7a2a87d 1277 atomic_inc(&nvmeq->dev->ctrl.abort_limit);
e7a2a87d 1278 blk_mq_free_request(req);
de671d61 1279 return RQ_END_IO_NONE;
bc5fc7e4
MW		 1280}
1281
b2a0eb1a
KB		 1282static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1283{
b2a0eb1a
KB		 1284 /* If true, indicates loss of adapter communication, possibly by a
1285 * NVMe Subsystem reset.
1286 */
1287 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1288
ad70062c
JW		 1289 /* If there is a reset/reinit ongoing, we shouldn't reset again. */
1290 switch (dev->ctrl.state) {
1291 case NVME_CTRL_RESETTING:
ad6a0a52 1292 case NVME_CTRL_CONNECTING:
b2a0eb1a 1293 return false;
ad70062c
JW		 1294 default:
1295 break;
1296 }
b2a0eb1a
KB		 1297
1298 /* We shouldn't reset unless the controller is on fatal error state
1299 * _or_ if we lost the communication with it.
1300 */
1301 if (!(csts & NVME_CSTS_CFS) && !nssro)
1302 return false;
1303
b2a0eb1a
KB		 1304 return true;
1305}
1306
1307static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1308{
1309 /* Read a config register to help see what died. */
1310 u16 pci_status;
1311 int result;
1312
1313 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1314 &pci_status);
1315 if (result == PCIBIOS_SUCCESSFUL)
1316 dev_warn(dev->ctrl.device,
1317 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1318 csts, pci_status);
1319 else
1320 dev_warn(dev->ctrl.device,
1321 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1322 csts, result);
4641a8e6
KB		 1323
1324 if (csts != ~0)
1325 return;
1326
1327 dev_warn(dev->ctrl.device,
1328 "Does your device have a faulty power saving mode enabled?\n");
1329 dev_warn(dev->ctrl.device,
1330 "Try \"nvme_core.default_ps_max_latency_us=0 pcie_aspm=off\" and report a bug\n");
b2a0eb1a
KB		 1331}
1332
9bdb4833 1333static enum blk_eh_timer_return nvme_timeout(struct request *req)
c30341dc 1334{
f4800d6d 1335 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a53232cb 1336 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
c30341dc 1337 struct nvme_dev *dev = nvmeq->dev;
a4aea562 1338 struct request *abort_req;
f66e2804 1339 struct nvme_command cmd = { };
b2a0eb1a
KB		 1340 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1341
651438bb
WX		 1342 /* If PCI error recovery process is happening, we cannot reset or
1343 * the recovery mechanism will surely fail.
1344 */
1345 mb();
1346 if (pci_channel_offline(to_pci_dev(dev->dev)))
1347 return BLK_EH_RESET_TIMER;
1348
b2a0eb1a
KB		 1349 /*
1350 * Reset immediately if the controller is failed
1351 */
1352 if (nvme_should_reset(dev, csts)) {
1353 nvme_warn_reset(dev, csts);
1354 nvme_dev_disable(dev, false);
d86c4d8e 1355 nvme_reset_ctrl(&dev->ctrl);
db8c48e4 1356 return BLK_EH_DONE;
b2a0eb1a 1357 }
c30341dc 1358
7776db1c
KB		 1359 /*
1360 * Did we miss an interrupt?
1361 */
fa059b85 1362 if (test_bit(NVMEQ_POLLED, &nvmeq->flags))
5a72e899 1363 nvme_poll(req->mq_hctx, NULL);
fa059b85
KB		 1364 else
1365 nvme_poll_irqdisable(nvmeq);
1366
bf392a5d 1367 if (blk_mq_request_completed(req)) {
7776db1c
KB		 1368 dev_warn(dev->ctrl.device,
1369 "I/O %d QID %d timeout, completion polled\n",
1370 req->tag, nvmeq->qid);
db8c48e4 1371 return BLK_EH_DONE;
7776db1c
KB		 1372 }
1373
31c7c7d2 1374 /*
fd634f41
CH		 1375 * Shutdown immediately if controller times out while starting. The
1376 * reset work will see the pci device disabled when it gets the forced
1377 * cancellation error. All outstanding requests are completed on
db8c48e4 1378 * shutdown, so we return BLK_EH_DONE.
fd634f41 1379 */
4244140d
KB		 1380 switch (dev->ctrl.state) {
1381 case NVME_CTRL_CONNECTING:
2036f726 1382 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
df561f66 1383 fallthrough;
2036f726 1384 case NVME_CTRL_DELETING:
b9cac43c 1385 dev_warn_ratelimited(dev->ctrl.device,
fd634f41
CH		 1386 "I/O %d QID %d timeout, disable controller\n",
1387 req->tag, nvmeq->qid);
27fa9bc5 1388 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
7ad92f65 1389 nvme_dev_disable(dev, true);
db8c48e4 1390 return BLK_EH_DONE;
39a9dd81
KB		 1391 case NVME_CTRL_RESETTING:
1392 return BLK_EH_RESET_TIMER;
4244140d
KB		 1393 default:
1394 break;
c30341dc
KB		 1395 }
1396
fd634f41 1397 /*
ee0d96d3
BW		 1398 * Shutdown the controller immediately and schedule a reset if the
1399 * command was already aborted once before and still hasn't been
1400 * returned to the driver, or if this is the admin queue.
31c7c7d2 1401 */
f4800d6d 1402 if (!nvmeq->qid || iod->aborted) {
1b3c47c1 1403 dev_warn(dev->ctrl.device,
e1569a16
KB		 1404 "I/O %d QID %d timeout, reset controller\n",
1405 req->tag, nvmeq->qid);
7ad92f65 1406 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
a5cdb68c 1407 nvme_dev_disable(dev, false);
d86c4d8e 1408 nvme_reset_ctrl(&dev->ctrl);
c30341dc 1409
db8c48e4 1410 return BLK_EH_DONE;
c30341dc 1411 }
c30341dc 1412
e7a2a87d 1413 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
6bf25d16 1414 atomic_inc(&dev->ctrl.abort_limit);
31c7c7d2 1415 return BLK_EH_RESET_TIMER;
6bf25d16 1416 }
52da4f3f 1417 iod->aborted = true;
a4aea562 1418
c30341dc 1419 cmd.abort.opcode = nvme_admin_abort_cmd;
85f74acf 1420 cmd.abort.cid = nvme_cid(req);
c30341dc 1421 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
c30341dc 1422
1b3c47c1 1423 dev_warn(nvmeq->dev->ctrl.device,
86141440
CH		 1424 "I/O %d (%s) QID %d timeout, aborting\n",
1425 req->tag,
1426 nvme_get_opcode_str(nvme_req(req)->cmd->common.opcode),
1427 nvmeq->qid);
e7a2a87d 1428
e559398f
CH		 1429 abort_req = blk_mq_alloc_request(dev->ctrl.admin_q, nvme_req_op(&cmd),
1430 BLK_MQ_REQ_NOWAIT);
e7a2a87d
CH		 1431 if (IS_ERR(abort_req)) {
1432 atomic_inc(&dev->ctrl.abort_limit);
1433 return BLK_EH_RESET_TIMER;
1434 }
e559398f 1435 nvme_init_request(abort_req, &cmd);
e7a2a87d 1436
e2e53086 1437 abort_req->end_io = abort_endio;
e7a2a87d 1438 abort_req->end_io_data = NULL;
128126a7 1439 abort_req->rq_flags |= RQF_QUIET;
e2e53086 1440 blk_execute_rq_nowait(abort_req, false);
c30341dc 1441
31c7c7d2
CH		 1442 /*
1443 * The aborted req will be completed on receiving the abort req.
1444 * We enable the timer again. If hit twice, it'll cause a device reset,
1445 * as the device then is in a faulty state.
1446 */
1447 return BLK_EH_RESET_TIMER;
c30341dc
KB		 1448}
1449
a4aea562
MB		 1450static void nvme_free_queue(struct nvme_queue *nvmeq)
1451{
8a1d09a6 1452 dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq),
9e866774 1453 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
63223078
CH		 1454 if (!nvmeq->sq_cmds)
1455 return;
0f238ff5 1456
63223078 1457 if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) {
88a041f4 1458 pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev),
8a1d09a6 1459 nvmeq->sq_cmds, SQ_SIZE(nvmeq));
63223078 1460 } else {
8a1d09a6 1461 dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq),
63223078 1462 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
0f238ff5 1463 }
9e866774
MW		 1464}
1465
a1a5ef99 1466static void nvme_free_queues(struct nvme_dev *dev, int lowest)
22404274
KB		 1467{
1468 int i;
1469
d858e5f0 1470 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
d858e5f0 1471 dev->ctrl.queue_count--;
147b27e4 1472 nvme_free_queue(&dev->queues[i]);
121c7ad4 1473 }
22404274
KB		 1474}
1475
4d115420
KB		 1476/**
1477 * nvme_suspend_queue - put queue into suspended state
40581d1a 1478 * @nvmeq: queue to suspend
4d115420
KB		 1479 */
1480static int nvme_suspend_queue(struct nvme_queue *nvmeq)
b60503ba 1481{
4e224106 1482 if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags))
2b25d981 1483 return 1;
a09115b2 1484
4e224106 1485 /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */
d1f06f4a 1486 mb();
a09115b2 1487
4e224106 1488 nvmeq->dev->online_queues--;
1c63dc66 1489 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
6ca1d902 1490 nvme_stop_admin_queue(&nvmeq->dev->ctrl);
7c349dde
KB		 1491 if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags))
1492 pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq);
4d115420
KB		 1493 return 0;
1494}
b60503ba 1495
8fae268b
KB		 1496static void nvme_suspend_io_queues(struct nvme_dev *dev)
1497{
1498 int i;
1499
1500 for (i = dev->ctrl.queue_count - 1; i > 0; i--)
1501 nvme_suspend_queue(&dev->queues[i]);
1502}
1503
a5cdb68c 1504static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
4d115420 1505{
147b27e4 1506 struct nvme_queue *nvmeq = &dev->queues[0];
4d115420 1507
a5cdb68c
KB		 1508 if (shutdown)
1509 nvme_shutdown_ctrl(&dev->ctrl);
1510 else
b5b05048 1511 nvme_disable_ctrl(&dev->ctrl);
07836e65 1512
bf392a5d 1513 nvme_poll_irqdisable(nvmeq);
b60503ba
MW		 1514}
1515
fa46c6fb
KB		 1516/*
1517 * Called only on a device that has been disabled and after all other threads
9210c075
DZ		 1518 * that can check this device's completion queues have synced, except
1519 * nvme_poll(). This is the last chance for the driver to see a natural
1520 * completion before nvme_cancel_request() terminates all incomplete requests.
fa46c6fb
KB		 1521 */
1522static void nvme_reap_pending_cqes(struct nvme_dev *dev)
1523{
fa46c6fb
KB		 1524 int i;
1525
9210c075
DZ		 1526 for (i = dev->ctrl.queue_count - 1; i > 0; i--) {
1527 spin_lock(&dev->queues[i].cq_poll_lock);
c234a653 1528 nvme_poll_cq(&dev->queues[i], NULL);
9210c075
DZ		 1529 spin_unlock(&dev->queues[i].cq_poll_lock);
1530 }
fa46c6fb
KB		 1531}
1532
8ffaadf7
JD		 1533static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1534 int entry_size)
1535{
1536 int q_depth = dev->q_depth;
5fd4ce1b 1537 unsigned q_size_aligned = roundup(q_depth * entry_size,
6c3c05b0 1538 NVME_CTRL_PAGE_SIZE);
8ffaadf7
JD		 1539
1540 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
c45f5c99 1541 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
4e523547 1542
6c3c05b0 1543 mem_per_q = round_down(mem_per_q, NVME_CTRL_PAGE_SIZE);
c45f5c99 1544 q_depth = div_u64(mem_per_q, entry_size);
8ffaadf7
JD		 1545
1546 /*
1547 * Ensure the reduced q_depth is above some threshold where it
1548 * would be better to map queues in system memory with the
1549 * original depth
1550 */
1551 if (q_depth < 64)
1552 return -ENOMEM;
1553 }
1554
1555 return q_depth;
1556}
1557
1558static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
8a1d09a6 1559 int qid)
8ffaadf7 1560{
0f238ff5
LG		 1561 struct pci_dev *pdev = to_pci_dev(dev->dev);
1562
1563 if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
8a1d09a6 1564 nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq));
bfac8e9f
AM		 1565 if (nvmeq->sq_cmds) {
1566 nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev,
1567 nvmeq->sq_cmds);
1568 if (nvmeq->sq_dma_addr) {
1569 set_bit(NVMEQ_SQ_CMB, &nvmeq->flags);
1570 return 0;
1571 }
1572
8a1d09a6 1573 pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq));
63223078 1574 }
0f238ff5 1575 }
8ffaadf7 1576
8a1d09a6 1577 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq),
63223078 1578 &nvmeq->sq_dma_addr, GFP_KERNEL);
815c6704
KB		 1579 if (!nvmeq->sq_cmds)
1580 return -ENOMEM;
8ffaadf7
JD		 1581 return 0;
1582}
1583
a6ff7262 1584static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
b60503ba 1585{
147b27e4 1586 struct nvme_queue *nvmeq = &dev->queues[qid];
b60503ba 1587
62314e40
KB		 1588 if (dev->ctrl.queue_count > qid)
1589 return 0;
b60503ba 1590
c1e0cc7e 1591 nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES;
8a1d09a6
BH		 1592 nvmeq->q_depth = depth;
1593 nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq),
750afb08 1594 &nvmeq->cq_dma_addr, GFP_KERNEL);
b60503ba
MW		 1595 if (!nvmeq->cqes)
1596 goto free_nvmeq;
b60503ba 1597
8a1d09a6 1598 if (nvme_alloc_sq_cmds(dev, nvmeq, qid))
b60503ba
MW		 1599 goto free_cqdma;
1600
091b6092 1601 nvmeq->dev = dev;
1ab0cd69 1602 spin_lock_init(&nvmeq->sq_lock);
3a7afd8e 1603 spin_lock_init(&nvmeq->cq_poll_lock);
b60503ba 1604 nvmeq->cq_head = 0;
82123460 1605 nvmeq->cq_phase = 1;
b80d5ccc 1606 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
c30341dc 1607 nvmeq->qid = qid;
d858e5f0 1608 dev->ctrl.queue_count++;
36a7e993 1609
147b27e4 1610 return 0;
b60503ba
MW		 1611
1612 free_cqdma:
8a1d09a6
BH		 1613 dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes,
1614 nvmeq->cq_dma_addr);
b60503ba 1615 free_nvmeq:
147b27e4 1616 return -ENOMEM;
b60503ba
MW		 1617}
1618
dca51e78 1619static int queue_request_irq(struct nvme_queue *nvmeq)
3001082c 1620{
0ff199cb
CH		 1621 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1622 int nr = nvmeq->dev->ctrl.instance;
1623
1624 if (use_threaded_interrupts) {
1625 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1626 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1627 } else {
1628 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1629 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1630 }
3001082c
MW		 1631}
1632
22404274 1633static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
b60503ba 1634{
22404274 1635 struct nvme_dev *dev = nvmeq->dev;
b60503ba 1636
22404274 1637 nvmeq->sq_tail = 0;
38210800 1638 nvmeq->last_sq_tail = 0;
22404274
KB		 1639 nvmeq->cq_head = 0;
1640 nvmeq->cq_phase = 1;
b80d5ccc 1641 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
8a1d09a6 1642 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq));
f9f38e33 1643 nvme_dbbuf_init(dev, nvmeq, qid);
42f61420 1644 dev->online_queues++;
3a7afd8e 1645 wmb(); /* ensure the first interrupt sees the initialization */
22404274
KB		 1646}
1647
e4b9852a
CC		 1648/*
1649 * Try getting shutdown_lock while setting up IO queues.
1650 */
1651static int nvme_setup_io_queues_trylock(struct nvme_dev *dev)
1652{
1653 /*
1654 * Give up if the lock is being held by nvme_dev_disable.
1655 */
1656 if (!mutex_trylock(&dev->shutdown_lock))
1657 return -ENODEV;
1658
1659 /*
1660 * Controller is in wrong state, fail early.
1661 */
1662 if (dev->ctrl.state != NVME_CTRL_CONNECTING) {
1663 mutex_unlock(&dev->shutdown_lock);
1664 return -ENODEV;
1665 }
1666
1667 return 0;
1668}
1669
4b04cc6a 1670static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled)
22404274
KB		 1671{
1672 struct nvme_dev *dev = nvmeq->dev;
1673 int result;
7c349dde 1674 u16 vector = 0;
3f85d50b 1675
d1ed6aa1
CH		 1676 clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
1677
22b55601
KB		 1678 /*
1679 * A queue's vector matches the queue identifier unless the controller
1680 * has only one vector available.
1681 */
4b04cc6a
JA		 1682 if (!polled)
1683 vector = dev->num_vecs == 1 ? 0 : qid;
1684 else
7c349dde 1685 set_bit(NVMEQ_POLLED, &nvmeq->flags);
4b04cc6a 1686
a8e3e0bb 1687 result = adapter_alloc_cq(dev, qid, nvmeq, vector);
ded45505
KB		 1688 if (result)
1689 return result;
b60503ba
MW		 1690
1691 result = adapter_alloc_sq(dev, qid, nvmeq);
1692 if (result < 0)
ded45505 1693 return result;
c80b36cd 1694 if (result)
b60503ba
MW		 1695 goto release_cq;
1696
a8e3e0bb 1697 nvmeq->cq_vector = vector;
4b04cc6a 1698
e4b9852a
CC		 1699 result = nvme_setup_io_queues_trylock(dev);
1700 if (result)
1701 return result;
1702 nvme_init_queue(nvmeq, qid);
7c349dde 1703 if (!polled) {
4b04cc6a
JA		 1704 result = queue_request_irq(nvmeq);
1705 if (result < 0)
1706 goto release_sq;
1707 }
b60503ba 1708
4e224106 1709 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
e4b9852a 1710 mutex_unlock(&dev->shutdown_lock);
22404274 1711 return result;
b60503ba 1712
a8e3e0bb 1713release_sq:
f25a2dfc 1714 dev->online_queues--;
e4b9852a 1715 mutex_unlock(&dev->shutdown_lock);
b60503ba 1716 adapter_delete_sq(dev, qid);
a8e3e0bb 1717release_cq:
b60503ba 1718 adapter_delete_cq(dev, qid);
22404274 1719 return result;
b60503ba
MW		 1720}
1721
f363b089 1722static const struct blk_mq_ops nvme_mq_admin_ops = {
d29ec824 1723 .queue_rq = nvme_queue_rq,
77f02a7a 1724 .complete = nvme_pci_complete_rq,
a4aea562 1725 .init_hctx = nvme_admin_init_hctx,
e559398f 1726 .init_request = nvme_pci_init_request,
a4aea562
MB		 1727 .timeout = nvme_timeout,
1728};
1729
f363b089 1730static const struct blk_mq_ops nvme_mq_ops = {
376f7ef8 1731 .queue_rq = nvme_queue_rq,
d62cbcf6 1732 .queue_rqs = nvme_queue_rqs,
376f7ef8
CH		 1733 .complete = nvme_pci_complete_rq,
1734 .commit_rqs = nvme_commit_rqs,
1735 .init_hctx = nvme_init_hctx,
e559398f 1736 .init_request = nvme_pci_init_request,
376f7ef8
CH		 1737 .map_queues = nvme_pci_map_queues,
1738 .timeout = nvme_timeout,
1739 .poll = nvme_poll,
dabcefab
JA		 1740};
1741
ea191d2f
KB		 1742static void nvme_dev_remove_admin(struct nvme_dev *dev)
1743{
1c63dc66 1744 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
69d9a99c
KB		 1745 /*
1746 * If the controller was reset during removal, it's possible
1747 * user requests may be waiting on a stopped queue. Start the
1748 * queue to flush these to completion.
1749 */
6ca1d902 1750 nvme_start_admin_queue(&dev->ctrl);
6f8191fd 1751 blk_mq_destroy_queue(dev->ctrl.admin_q);
ea191d2f
KB		 1752 blk_mq_free_tag_set(&dev->admin_tagset);
1753 }
1754}
1755
f91b727c 1756static int nvme_pci_alloc_admin_tag_set(struct nvme_dev *dev)
a4aea562 1757{
f91b727c 1758 struct blk_mq_tag_set *set = &dev->admin_tagset;
e3e9d50c 1759
f91b727c
CH		 1760 set->ops = &nvme_mq_admin_ops;
1761 set->nr_hw_queues = 1;
a4aea562 1762
f91b727c
CH		 1763 set->queue_depth = NVME_AQ_MQ_TAG_DEPTH;
1764 set->timeout = NVME_ADMIN_TIMEOUT;
1765 set->numa_node = dev->ctrl.numa_node;
1766 set->cmd_size = sizeof(struct nvme_iod);
1767 set->flags = BLK_MQ_F_NO_SCHED;
1768 set->driver_data = dev;
a4aea562 1769
f91b727c
CH		 1770 if (blk_mq_alloc_tag_set(set))
1771 return -ENOMEM;
1772 dev->ctrl.admin_tagset = set;
a4aea562 1773
f91b727c
CH		 1774 dev->ctrl.admin_q = blk_mq_init_queue(set);
1775 if (IS_ERR(dev->ctrl.admin_q)) {
1776 blk_mq_free_tag_set(set);
1777 dev->ctrl.admin_q = NULL;
1778 return -ENOMEM;
1779 }
1780 if (!blk_get_queue(dev->ctrl.admin_q)) {
1781 nvme_dev_remove_admin(dev);
1782 dev->ctrl.admin_q = NULL;
1783 return -ENODEV;
1784 }
a4aea562
MB		 1785 return 0;
1786}
1787
97f6ef64
XY		 1788static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1789{
1790 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1791}
1792
1793static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1794{
1795 struct pci_dev *pdev = to_pci_dev(dev->dev);
1796
1797 if (size <= dev->bar_mapped_size)
1798 return 0;
1799 if (size > pci_resource_len(pdev, 0))
1800 return -ENOMEM;
1801 if (dev->bar)
1802 iounmap(dev->bar);
1803 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1804 if (!dev->bar) {
1805 dev->bar_mapped_size = 0;
1806 return -ENOMEM;
1807 }
1808 dev->bar_mapped_size = size;
1809 dev->dbs = dev->bar + NVME_REG_DBS;
1810
1811 return 0;
1812}
1813
01ad0990 1814static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
b60503ba 1815{
ba47e386 1816 int result;
b60503ba
MW		 1817 u32 aqa;
1818 struct nvme_queue *nvmeq;
1819
97f6ef64
XY		 1820 result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1821 if (result < 0)
1822 return result;
1823
8ef2074d 1824 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
20d0dfe6 1825 NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
dfbac8c7 1826
7a67cbea
CH		 1827 if (dev->subsystem &&
1828 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1829 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
dfbac8c7 1830
b5b05048 1831 result = nvme_disable_ctrl(&dev->ctrl);
ba47e386
MW		 1832 if (result < 0)
1833 return result;
b60503ba 1834
a6ff7262 1835 result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
147b27e4
SG		 1836 if (result)
1837 return result;
b60503ba 1838
635333e4
MG		 1839 dev->ctrl.numa_node = dev_to_node(dev->dev);
1840
147b27e4 1841 nvmeq = &dev->queues[0];
b60503ba
MW		 1842 aqa = nvmeq->q_depth - 1;
1843 aqa |= aqa << 16;
1844
7a67cbea
CH		 1845 writel(aqa, dev->bar + NVME_REG_AQA);
1846 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1847 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
b60503ba 1848
c0f2f45b 1849 result = nvme_enable_ctrl(&dev->ctrl);
025c557a 1850 if (result)
d4875622 1851 return result;
a4aea562 1852
2b25d981 1853 nvmeq->cq_vector = 0;
161b8be2 1854 nvme_init_queue(nvmeq, 0);
dca51e78 1855 result = queue_request_irq(nvmeq);
758dd7fd 1856 if (result) {
7c349dde 1857 dev->online_queues--;
d4875622 1858 return result;
758dd7fd 1859 }
025c557a 1860
4e224106 1861 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
b60503ba
MW		 1862 return result;
1863}
1864
749941f2 1865static int nvme_create_io_queues(struct nvme_dev *dev)
42f61420 1866{
4b04cc6a 1867 unsigned i, max, rw_queues;
749941f2 1868 int ret = 0;
42f61420 1869
d858e5f0 1870 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
a6ff7262 1871 if (nvme_alloc_queue(dev, i, dev->q_depth)) {
749941f2 1872 ret = -ENOMEM;
42f61420 1873 break;
749941f2
CH		 1874 }
1875 }
42f61420 1876
d858e5f0 1877 max = min(dev->max_qid, dev->ctrl.queue_count - 1);
e20ba6e1
CH		 1878 if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) {
1879 rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] +
1880 dev->io_queues[HCTX_TYPE_READ];
4b04cc6a
JA		 1881 } else {
1882 rw_queues = max;
1883 }
1884
949928c1 1885 for (i = dev->online_queues; i <= max; i++) {
4b04cc6a
JA		 1886 bool polled = i > rw_queues;
1887
1888 ret = nvme_create_queue(&dev->queues[i], i, polled);
d4875622 1889 if (ret)
42f61420 1890 break;
27e8166c 1891 }
749941f2
CH		 1892
1893 /*
1894 * Ignore failing Create SQ/CQ commands, we can continue with less
8adb8c14
MI		 1895 * than the desired amount of queues, and even a controller without
1896 * I/O queues can still be used to issue admin commands. This might
749941f2
CH		 1897 * be useful to upgrade a buggy firmware for example.
1898 */
1899 return ret >= 0 ? 0 : ret;
b60503ba
MW		 1900}
1901
88de4598 1902static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
8ffaadf7 1903{
88de4598
CH		 1904 u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
1905
1906 return 1ULL << (12 + 4 * szu);
1907}
1908
1909static u32 nvme_cmb_size(struct nvme_dev *dev)
1910{
1911 return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
1912}
1913
f65efd6d 1914static void nvme_map_cmb(struct nvme_dev *dev)
8ffaadf7 1915{
88de4598 1916 u64 size, offset;
8ffaadf7
JD		 1917 resource_size_t bar_size;
1918 struct pci_dev *pdev = to_pci_dev(dev->dev);
8969f1f8 1919 int bar;
8ffaadf7 1920
9fe5c59f
KB		 1921 if (dev->cmb_size)
1922 return;
1923
20d3bb92
KJ		 1924 if (NVME_CAP_CMBS(dev->ctrl.cap))
1925 writel(NVME_CMBMSC_CRE, dev->bar + NVME_REG_CMBMSC);
1926
7a67cbea 1927 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
f65efd6d
CH		 1928 if (!dev->cmbsz)
1929 return;
202021c1 1930 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
8ffaadf7 1931
88de4598
CH		 1932 size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
1933 offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
8969f1f8
CH		 1934 bar = NVME_CMB_BIR(dev->cmbloc);
1935 bar_size = pci_resource_len(pdev, bar);
8ffaadf7
JD		 1936
1937 if (offset > bar_size)
f65efd6d 1938 return;
8ffaadf7 1939
20d3bb92
KJ		 1940 /*
1941 * Tell the controller about the host side address mapping the CMB,
1942 * and enable CMB decoding for the NVMe 1.4+ scheme:
1943 */
1944 if (NVME_CAP_CMBS(dev->ctrl.cap)) {
1945 hi_lo_writeq(NVME_CMBMSC_CRE | NVME_CMBMSC_CMSE |
1946 (pci_bus_address(pdev, bar) + offset),
1947 dev->bar + NVME_REG_CMBMSC);
1948 }
1949
8ffaadf7
JD		 1950 /*
1951 * Controllers may support a CMB size larger than their BAR,
1952 * for example, due to being behind a bridge. Reduce the CMB to
1953 * the reported size of the BAR
1954 */
1955 if (size > bar_size - offset)
1956 size = bar_size - offset;
1957
0f238ff5
LG		 1958 if (pci_p2pdma_add_resource(pdev, bar, size, offset)) {
1959 dev_warn(dev->ctrl.device,
1960 "failed to register the CMB\n");
f65efd6d 1961 return;
0f238ff5
LG		 1962 }
1963
8ffaadf7 1964 dev->cmb_size = size;
0f238ff5
LG		 1965 dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS);
1966
1967 if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) ==
1968 (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS))
1969 pci_p2pmem_publish(pdev, true);
8ffaadf7
JD		 1970}
1971
87ad72a5
CH		 1972static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1973{
6c3c05b0 1974 u32 host_mem_size = dev->host_mem_size >> NVME_CTRL_PAGE_SHIFT;
4033f35d 1975 u64 dma_addr = dev->host_mem_descs_dma;
f66e2804 1976 struct nvme_command c = { };
87ad72a5
CH		 1977 int ret;
1978
87ad72a5
CH		 1979 c.features.opcode = nvme_admin_set_features;
1980 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1981 c.features.dword11 = cpu_to_le32(bits);
6c3c05b0 1982 c.features.dword12 = cpu_to_le32(host_mem_size);
87ad72a5
CH		 1983 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr));
1984 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr));
1985 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs);
1986
1987 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1988 if (ret) {
1989 dev_warn(dev->ctrl.device,
1990 "failed to set host mem (err %d, flags %#x).\n",
1991 ret, bits);
a5df5e79
KB		 1992 } else
1993 dev->hmb = bits & NVME_HOST_MEM_ENABLE;
1994
87ad72a5
CH		 1995 return ret;
1996}
1997
1998static void nvme_free_host_mem(struct nvme_dev *dev)
1999{
2000 int i;
2001
2002 for (i = 0; i < dev->nr_host_mem_descs; i++) {
2003 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
6c3c05b0 2004 size_t size = le32_to_cpu(desc->size) * NVME_CTRL_PAGE_SIZE;
87ad72a5 2005
cc667f6d
LD		 2006 dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i],
2007 le64_to_cpu(desc->addr),
2008 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
87ad72a5
CH		 2009 }
2010
2011 kfree(dev->host_mem_desc_bufs);
2012 dev->host_mem_desc_bufs = NULL;
4033f35d
CH		 2013 dma_free_coherent(dev->dev,
2014 dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
2015 dev->host_mem_descs, dev->host_mem_descs_dma);
87ad72a5 2016 dev->host_mem_descs = NULL;
7e5dd57e 2017 dev->nr_host_mem_descs = 0;
87ad72a5
CH		 2018}
2019
92dc6895
CH		 2020static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
2021 u32 chunk_size)
9d713c2b 2022{
87ad72a5 2023 struct nvme_host_mem_buf_desc *descs;
92dc6895 2024 u32 max_entries, len;
4033f35d 2025 dma_addr_t descs_dma;
2ee0e4ed 2026 int i = 0;
87ad72a5 2027 void **bufs;
6fbcde66 2028 u64 size, tmp;
87ad72a5 2029
87ad72a5
CH		 2030 tmp = (preferred + chunk_size - 1);
2031 do_div(tmp, chunk_size);
2032 max_entries = tmp;
044a9df1
CH		 2033
2034 if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
2035 max_entries = dev->ctrl.hmmaxd;
2036
750afb08
LC		 2037 descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs),
2038 &descs_dma, GFP_KERNEL);
87ad72a5
CH		 2039 if (!descs)
2040 goto out;
2041
2042 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
2043 if (!bufs)
2044 goto out_free_descs;
2045
244a8fe4 2046 for (size = 0; size < preferred && i < max_entries; size += len) {
87ad72a5
CH		 2047 dma_addr_t dma_addr;
2048
50cdb7c6 2049 len = min_t(u64, chunk_size, preferred - size);
87ad72a5
CH		 2050 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
2051 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
2052 if (!bufs[i])
2053 break;
2054
2055 descs[i].addr = cpu_to_le64(dma_addr);
6c3c05b0 2056 descs[i].size = cpu_to_le32(len / NVME_CTRL_PAGE_SIZE);
87ad72a5
CH		 2057 i++;
2058 }
2059
92dc6895 2060 if (!size)
87ad72a5 2061 goto out_free_bufs;
87ad72a5 2062
87ad72a5
CH		 2063 dev->nr_host_mem_descs = i;
2064 dev->host_mem_size = size;
2065 dev->host_mem_descs = descs;
4033f35d 2066 dev->host_mem_descs_dma = descs_dma;
87ad72a5
CH		 2067 dev->host_mem_desc_bufs = bufs;
2068 return 0;
2069
2070out_free_bufs:
2071 while (--i >= 0) {
6c3c05b0 2072 size_t size = le32_to_cpu(descs[i].size) * NVME_CTRL_PAGE_SIZE;
87ad72a5 2073
cc667f6d
LD		 2074 dma_free_attrs(dev->dev, size, bufs[i],
2075 le64_to_cpu(descs[i].addr),
2076 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
87ad72a5
CH		 2077 }
2078
2079 kfree(bufs);
2080out_free_descs:
4033f35d
CH		 2081 dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
2082 descs_dma);
87ad72a5 2083out:
87ad72a5
CH		 2084 dev->host_mem_descs = NULL;
2085 return -ENOMEM;
2086}
2087
92dc6895
CH		 2088static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
2089{
9dc54a0d
CK		 2090 u64 min_chunk = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
2091 u64 hmminds = max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
2092 u64 chunk_size;
92dc6895
CH		 2093
2094 /* start big and work our way down */
9dc54a0d 2095 for (chunk_size = min_chunk; chunk_size >= hmminds; chunk_size /= 2) {
92dc6895
CH		 2096 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
2097 if (!min || dev->host_mem_size >= min)
2098 return 0;
2099 nvme_free_host_mem(dev);
2100 }
2101 }
2102
2103 return -ENOMEM;
2104}
2105
9620cfba 2106static int nvme_setup_host_mem(struct nvme_dev *dev)
87ad72a5
CH		 2107{
2108 u64 max = (u64)max_host_mem_size_mb * SZ_1M;
2109 u64 preferred = (u64)dev->ctrl.hmpre * 4096;
2110 u64 min = (u64)dev->ctrl.hmmin * 4096;
2111 u32 enable_bits = NVME_HOST_MEM_ENABLE;
6fbcde66 2112 int ret;
87ad72a5
CH		 2113
2114 preferred = min(preferred, max);
2115 if (min > max) {
2116 dev_warn(dev->ctrl.device,
2117 "min host memory (%lld MiB) above limit (%d MiB).\n",
2118 min >> ilog2(SZ_1M), max_host_mem_size_mb);
2119 nvme_free_host_mem(dev);
9620cfba 2120 return 0;
87ad72a5
CH		 2121 }
2122
2123 /*
2124 * If we already have a buffer allocated check if we can reuse it.
2125 */
2126 if (dev->host_mem_descs) {
2127 if (dev->host_mem_size >= min)
2128 enable_bits |= NVME_HOST_MEM_RETURN;
2129 else
2130 nvme_free_host_mem(dev);
2131 }
2132
2133 if (!dev->host_mem_descs) {
92dc6895
CH		 2134 if (nvme_alloc_host_mem(dev, min, preferred)) {
2135 dev_warn(dev->ctrl.device,
2136 "failed to allocate host memory buffer.\n");
9620cfba 2137 return 0; /* controller must work without HMB */
92dc6895
CH		 2138 }
2139
2140 dev_info(dev->ctrl.device,
2141 "allocated %lld MiB host memory buffer.\n",
2142 dev->host_mem_size >> ilog2(SZ_1M));
87ad72a5
CH		 2143 }
2144
9620cfba
CH		 2145 ret = nvme_set_host_mem(dev, enable_bits);
2146 if (ret)
87ad72a5 2147 nvme_free_host_mem(dev);
9620cfba 2148 return ret;
9d713c2b
KB		 2149}
2150
0521905e
KB		 2151static ssize_t cmb_show(struct device *dev, struct device_attribute *attr,
2152 char *buf)
2153{
2154 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2155
2156 return sysfs_emit(buf, "cmbloc : x%08x\ncmbsz : x%08x\n",
2157 ndev->cmbloc, ndev->cmbsz);
2158}
2159static DEVICE_ATTR_RO(cmb);
2160
1751e97a
KB		 2161static ssize_t cmbloc_show(struct device *dev, struct device_attribute *attr,
2162 char *buf)
2163{
2164 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2165
2166 return sysfs_emit(buf, "%u\n", ndev->cmbloc);
2167}
2168static DEVICE_ATTR_RO(cmbloc);
2169
2170static ssize_t cmbsz_show(struct device *dev, struct device_attribute *attr,
2171 char *buf)
2172{
2173 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2174
2175 return sysfs_emit(buf, "%u\n", ndev->cmbsz);
2176}
2177static DEVICE_ATTR_RO(cmbsz);
2178
a5df5e79
KB		 2179static ssize_t hmb_show(struct device *dev, struct device_attribute *attr,
2180 char *buf)
2181{
2182 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2183
2184 return sysfs_emit(buf, "%d\n", ndev->hmb);
2185}
2186
2187static ssize_t hmb_store(struct device *dev, struct device_attribute *attr,
2188 const char *buf, size_t count)
2189{
2190 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2191 bool new;
2192 int ret;
2193
2194 if (strtobool(buf, &new) < 0)
2195 return -EINVAL;
2196
2197 if (new == ndev->hmb)
2198 return count;
2199
2200 if (new) {
2201 ret = nvme_setup_host_mem(ndev);
2202 } else {
2203 ret = nvme_set_host_mem(ndev, 0);
2204 if (!ret)
2205 nvme_free_host_mem(ndev);
2206 }
2207
2208 if (ret < 0)
2209 return ret;
2210
2211 return count;
2212}
2213static DEVICE_ATTR_RW(hmb);
2214
0521905e
KB		 2215static umode_t nvme_pci_attrs_are_visible(struct kobject *kobj,
2216 struct attribute *a, int n)
2217{
2218 struct nvme_ctrl *ctrl =
2219 dev_get_drvdata(container_of(kobj, struct device, kobj));
2220 struct nvme_dev *dev = to_nvme_dev(ctrl);
2221
1751e97a
KB		 2222 if (a == &dev_attr_cmb.attr ||
2223 a == &dev_attr_cmbloc.attr ||
2224 a == &dev_attr_cmbsz.attr) {
2225 if (!dev->cmbsz)
2226 return 0;
2227 }
a5df5e79
KB		 2228 if (a == &dev_attr_hmb.attr && !ctrl->hmpre)
2229 return 0;
2230
0521905e
KB		 2231 return a->mode;
2232}
2233
2234static struct attribute *nvme_pci_attrs[] = {
2235 &dev_attr_cmb.attr,
1751e97a
KB		 2236 &dev_attr_cmbloc.attr,
2237 &dev_attr_cmbsz.attr,
a5df5e79 2238 &dev_attr_hmb.attr,
0521905e
KB		 2239 NULL,
2240};
2241
2242static const struct attribute_group nvme_pci_attr_group = {
2243 .attrs = nvme_pci_attrs,
2244 .is_visible = nvme_pci_attrs_are_visible,
2245};
2246
612b7286
ML		 2247/*
2248 * nirqs is the number of interrupts available for write and read
2249 * queues. The core already reserved an interrupt for the admin queue.
2250 */
2251static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs)
3b6592f7 2252{
612b7286 2253 struct nvme_dev *dev = affd->priv;
2a5bcfdd 2254 unsigned int nr_read_queues, nr_write_queues = dev->nr_write_queues;
3b6592f7
JA		 2255
2256 /*
ee0d96d3 2257 * If there is no interrupt available for queues, ensure that
612b7286
ML		 2258 * the default queue is set to 1. The affinity set size is
2259 * also set to one, but the irq core ignores it for this case.
2260 *
2261 * If only one interrupt is available or 'write_queue' == 0, combine
2262 * write and read queues.
2263 *
2264 * If 'write_queues' > 0, ensure it leaves room for at least one read
2265 * queue.
3b6592f7 2266 */
612b7286
ML		 2267 if (!nrirqs) {
2268 nrirqs = 1;
2269 nr_read_queues = 0;
2a5bcfdd 2270 } else if (nrirqs == 1 || !nr_write_queues) {
612b7286 2271 nr_read_queues = 0;
2a5bcfdd 2272 } else if (nr_write_queues >= nrirqs) {
612b7286 2273 nr_read_queues = 1;
3b6592f7 2274 } else {
2a5bcfdd 2275 nr_read_queues = nrirqs - nr_write_queues;
3b6592f7 2276 }
612b7286
ML		 2277
2278 dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2279 affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2280 dev->io_queues[HCTX_TYPE_READ] = nr_read_queues;
2281 affd->set_size[HCTX_TYPE_READ] = nr_read_queues;
2282 affd->nr_sets = nr_read_queues ? 2 : 1;
3b6592f7
JA		 2283}
2284
6451fe73 2285static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues)
3b6592f7
JA		 2286{
2287 struct pci_dev *pdev = to_pci_dev(dev->dev);
3b6592f7 2288 struct irq_affinity affd = {
9cfef55b 2289 .pre_vectors = 1,
612b7286
ML		 2290 .calc_sets = nvme_calc_irq_sets,
2291 .priv = dev,
3b6592f7 2292 };
21cc2f3f 2293 unsigned int irq_queues, poll_queues;
6451fe73
JA		 2294
2295 /*
21cc2f3f
JX		 2296 * Poll queues don't need interrupts, but we need at least one I/O queue
2297 * left over for non-polled I/O.
6451fe73 2298 */
21cc2f3f
JX		 2299 poll_queues = min(dev->nr_poll_queues, nr_io_queues - 1);
2300 dev->io_queues[HCTX_TYPE_POLL] = poll_queues;
3b6592f7 2301
21cc2f3f
JX		 2302 /*
2303 * Initialize for the single interrupt case, will be updated in
2304 * nvme_calc_irq_sets().
2305 */
612b7286
ML		 2306 dev->io_queues[HCTX_TYPE_DEFAULT] = 1;
2307 dev->io_queues[HCTX_TYPE_READ] = 0;
3b6592f7 2308
66341331 2309 /*
21cc2f3f
JX		 2310 * We need interrupts for the admin queue and each non-polled I/O queue,
2311 * but some Apple controllers require all queues to use the first
2312 * vector.
66341331 2313 */
21cc2f3f
JX		 2314 irq_queues = 1;
2315 if (!(dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR))
2316 irq_queues += (nr_io_queues - poll_queues);
612b7286
ML		 2317 return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues,
2318 PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd);
3b6592f7
JA		 2319}
2320
8fae268b
KB		 2321static void nvme_disable_io_queues(struct nvme_dev *dev)
2322{
2323 if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq))
2324 __nvme_disable_io_queues(dev, nvme_admin_delete_cq);
2325}
2326
2a5bcfdd
WZ		 2327static unsigned int nvme_max_io_queues(struct nvme_dev *dev)
2328{
e3aef095
NS		 2329 /*
2330 * If tags are shared with admin queue (Apple bug), then
2331 * make sure we only use one IO queue.
2332 */
2333 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2334 return 1;
2a5bcfdd
WZ		 2335 return num_possible_cpus() + dev->nr_write_queues + dev->nr_poll_queues;
2336}
2337
8d85fce7 2338static int nvme_setup_io_queues(struct nvme_dev *dev)
b60503ba 2339{
147b27e4 2340 struct nvme_queue *adminq = &dev->queues[0];
e75ec752 2341 struct pci_dev *pdev = to_pci_dev(dev->dev);
2a5bcfdd 2342 unsigned int nr_io_queues;
97f6ef64 2343 unsigned long size;
2a5bcfdd 2344 int result;
b60503ba 2345
2a5bcfdd
WZ		 2346 /*
2347 * Sample the module parameters once at reset time so that we have
2348 * stable values to work with.
2349 */
2350 dev->nr_write_queues = write_queues;
2351 dev->nr_poll_queues = poll_queues;
d38e9f04 2352
e3aef095 2353 nr_io_queues = dev->nr_allocated_queues - 1;
9a0be7ab
CH		 2354 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
2355 if (result < 0)
1b23484b 2356 return result;
9a0be7ab 2357
f5fa90dc 2358 if (nr_io_queues == 0)
a5229050 2359 return 0;
53dc180e 2360
e4b9852a
CC		 2361 /*
2362 * Free IRQ resources as soon as NVMEQ_ENABLED bit transitions
2363 * from set to unset. If there is a window to it is truely freed,
2364 * pci_free_irq_vectors() jumping into this window will crash.
2365 * And take lock to avoid racing with pci_free_irq_vectors() in
2366 * nvme_dev_disable() path.
2367 */
2368 result = nvme_setup_io_queues_trylock(dev);
2369 if (result)
2370 return result;
2371 if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags))
2372 pci_free_irq(pdev, 0, adminq);
b60503ba 2373
0f238ff5 2374 if (dev->cmb_use_sqes) {
8ffaadf7
JD		 2375 result = nvme_cmb_qdepth(dev, nr_io_queues,
2376 sizeof(struct nvme_command));
2377 if (result > 0)
2378 dev->q_depth = result;
2379 else
0f238ff5 2380 dev->cmb_use_sqes = false;
8ffaadf7
JD		 2381 }
2382
97f6ef64
XY		 2383 do {
2384 size = db_bar_size(dev, nr_io_queues);
2385 result = nvme_remap_bar(dev, size);
2386 if (!result)
2387 break;
e4b9852a
CC		 2388 if (!--nr_io_queues) {
2389 result = -ENOMEM;
2390 goto out_unlock;
2391 }
97f6ef64
XY		 2392 } while (1);
2393 adminq->q_db = dev->dbs;
f1938f6e 2394
8fae268b 2395 retry:
9d713c2b 2396 /* Deregister the admin queue's interrupt */
e4b9852a
CC		 2397 if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags))
2398 pci_free_irq(pdev, 0, adminq);
9d713c2b 2399
e32efbfc
JA		 2400 /*
2401 * If we enable msix early due to not intx, disable it again before
2402 * setting up the full range we need.
2403 */
dca51e78 2404 pci_free_irq_vectors(pdev);
3b6592f7
JA		 2405
2406 result = nvme_setup_irqs(dev, nr_io_queues);
e4b9852a
CC		 2407 if (result <= 0) {
2408 result = -EIO;
2409 goto out_unlock;
2410 }
3b6592f7 2411
22b55601 2412 dev->num_vecs = result;
4b04cc6a 2413 result = max(result - 1, 1);
e20ba6e1 2414 dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL];
fa08a396 2415
063a8096
MW		 2416 /*
2417 * Should investigate if there's a performance win from allocating
2418 * more queues than interrupt vectors; it might allow the submission
2419 * path to scale better, even if the receive path is limited by the
2420 * number of interrupts.
2421 */
dca51e78 2422 result = queue_request_irq(adminq);
7c349dde 2423 if (result)
e4b9852a 2424 goto out_unlock;
4e224106 2425 set_bit(NVMEQ_ENABLED, &adminq->flags);
e4b9852a 2426 mutex_unlock(&dev->shutdown_lock);
8fae268b
KB		 2427
2428 result = nvme_create_io_queues(dev);
2429 if (result || dev->online_queues < 2)
2430 return result;
2431
2432 if (dev->online_queues - 1 < dev->max_qid) {
2433 nr_io_queues = dev->online_queues - 1;
2434 nvme_disable_io_queues(dev);
e4b9852a
CC		 2435 result = nvme_setup_io_queues_trylock(dev);
2436 if (result)
2437 return result;
8fae268b
KB		 2438 nvme_suspend_io_queues(dev);
2439 goto retry;
2440 }
2441 dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n",
2442 dev->io_queues[HCTX_TYPE_DEFAULT],
2443 dev->io_queues[HCTX_TYPE_READ],
2444 dev->io_queues[HCTX_TYPE_POLL]);
2445 return 0;
e4b9852a
CC		 2446out_unlock:
2447 mutex_unlock(&dev->shutdown_lock);
2448 return result;
b60503ba
MW		 2449}
2450
de671d61
JA		 2451static enum rq_end_io_ret nvme_del_queue_end(struct request *req,
2452 blk_status_t error)
a5768aa8 2453{
db3cbfff 2454 struct nvme_queue *nvmeq = req->end_io_data;
b5875222 2455
db3cbfff 2456 blk_mq_free_request(req);
d1ed6aa1 2457 complete(&nvmeq->delete_done);
de671d61 2458 return RQ_END_IO_NONE;
a5768aa8
KB		 2459}
2460
de671d61
JA		 2461static enum rq_end_io_ret nvme_del_cq_end(struct request *req,
2462 blk_status_t error)
a5768aa8 2463{
db3cbfff 2464 struct nvme_queue *nvmeq = req->end_io_data;
a5768aa8 2465
d1ed6aa1
CH		 2466 if (error)
2467 set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
db3cbfff 2468
de671d61 2469 return nvme_del_queue_end(req, error);
a5768aa8
KB		 2470}
2471
db3cbfff 2472static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
bda4e0fb 2473{
db3cbfff
KB		 2474 struct request_queue *q = nvmeq->dev->ctrl.admin_q;
2475 struct request *req;
f66e2804 2476 struct nvme_command cmd = { };
bda4e0fb 2477
db3cbfff
KB		 2478 cmd.delete_queue.opcode = opcode;
2479 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
bda4e0fb 2480
e559398f 2481 req = blk_mq_alloc_request(q, nvme_req_op(&cmd), BLK_MQ_REQ_NOWAIT);
db3cbfff
KB		 2482 if (IS_ERR(req))
2483 return PTR_ERR(req);
e559398f 2484 nvme_init_request(req, &cmd);
bda4e0fb 2485
e2e53086
CH		 2486 if (opcode == nvme_admin_delete_cq)
2487 req->end_io = nvme_del_cq_end;
2488 else
2489 req->end_io = nvme_del_queue_end;
db3cbfff
KB		 2490 req->end_io_data = nvmeq;
2491
d1ed6aa1 2492 init_completion(&nvmeq->delete_done);
128126a7 2493 req->rq_flags |= RQF_QUIET;
e2e53086 2494 blk_execute_rq_nowait(req, false);
db3cbfff 2495 return 0;
bda4e0fb
KB		 2496}
2497
8fae268b 2498static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode)
a5768aa8 2499{
5271edd4 2500 int nr_queues = dev->online_queues - 1, sent = 0;
db3cbfff 2501 unsigned long timeout;
a5768aa8 2502
db3cbfff 2503 retry:
dc96f938 2504 timeout = NVME_ADMIN_TIMEOUT;
5271edd4
CH		 2505 while (nr_queues > 0) {
2506 if (nvme_delete_queue(&dev->queues[nr_queues], opcode))
2507 break;
2508 nr_queues--;
2509 sent++;
db3cbfff 2510 }
d1ed6aa1
CH		 2511 while (sent) {
2512 struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent];
2513
2514 timeout = wait_for_completion_io_timeout(&nvmeq->delete_done,
5271edd4
CH		 2515 timeout);
2516 if (timeout == 0)
2517 return false;
d1ed6aa1 2518
d1ed6aa1 2519 sent--;
5271edd4
CH		 2520 if (nr_queues)
2521 goto retry;
2522 }
2523 return true;
a5768aa8
KB		 2524}
2525
2455a4b7 2526static void nvme_pci_alloc_tag_set(struct nvme_dev *dev)
b60503ba 2527{
2455a4b7 2528 struct blk_mq_tag_set * set = &dev->tagset;
2b1b7e78
JW		 2529 int ret;
2530
2455a4b7
CH		 2531 set->ops = &nvme_mq_ops;
2532 set->nr_hw_queues = dev->online_queues - 1;
6ee742fa
KB		 2533 set->nr_maps = 1;
2534 if (dev->io_queues[HCTX_TYPE_READ])
2535 set->nr_maps = 2;
2455a4b7 2536 if (dev->io_queues[HCTX_TYPE_POLL])
6ee742fa 2537 set->nr_maps = 3;
2455a4b7
CH		 2538 set->timeout = NVME_IO_TIMEOUT;
2539 set->numa_node = dev->ctrl.numa_node;
2540 set->queue_depth = min_t(unsigned, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
2541 set->cmd_size = sizeof(struct nvme_iod);
2542 set->flags = BLK_MQ_F_SHOULD_MERGE;
2543 set->driver_data = dev;
d38e9f04 2544
2455a4b7
CH		 2545 /*
2546 * Some Apple controllers requires tags to be unique
2547 * across admin and IO queue, so reserve the first 32
2548 * tags of the IO queue.
2549 */
2550 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2551 set->reserved_tags = NVME_AQ_DEPTH;
949928c1 2552
2455a4b7
CH		 2553 ret = blk_mq_alloc_tag_set(set);
2554 if (ret) {
2555 dev_warn(dev->ctrl.device,
2556 "IO queues tagset allocation failed %d\n", ret);
2557 return;
ffe7704d 2558 }
2455a4b7
CH		 2559 dev->ctrl.tagset = set;
2560}
949928c1 2561
2455a4b7
CH		 2562static void nvme_pci_update_nr_queues(struct nvme_dev *dev)
2563{
2564 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2565 /* free previously allocated queues that are no longer usable */
2566 nvme_free_queues(dev, dev->online_queues);
b60503ba
MW		 2567}
2568
b00a726a 2569static int nvme_pci_enable(struct nvme_dev *dev)
0877cb0d 2570{
b00a726a 2571 int result = -ENOMEM;
e75ec752 2572 struct pci_dev *pdev = to_pci_dev(dev->dev);
4bdf2603 2573 int dma_address_bits = 64;
0877cb0d
KB		 2574
2575 if (pci_enable_device_mem(pdev))
2576 return result;
2577
0877cb0d 2578 pci_set_master(pdev);
0877cb0d 2579
4bdf2603
FS		 2580 if (dev->ctrl.quirks & NVME_QUIRK_DMA_ADDRESS_BITS_48)
2581 dma_address_bits = 48;
2582 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(dma_address_bits)))
052d0efa 2583 goto disable;
0877cb0d 2584
7a67cbea 2585 if (readl(dev->bar + NVME_REG_CSTS) == -1) {
0e53d180 2586 result = -ENODEV;
b00a726a 2587 goto disable;
0e53d180 2588 }
e32efbfc
JA		 2589
2590 /*
a5229050
KB		 2591 * Some devices and/or platforms don't advertise or work with INTx
2592 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2593 * adjust this later.
e32efbfc 2594 */
dca51e78
CH		 2595 result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
2596 if (result < 0)
2597 return result;
e32efbfc 2598
20d0dfe6 2599 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
7a67cbea 2600
7442ddce 2601 dev->q_depth = min_t(u32, NVME_CAP_MQES(dev->ctrl.cap) + 1,
b27c1e68 2602 io_queue_depth);
aa22c8e6 2603 dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */
20d0dfe6 2604 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
7a67cbea 2605 dev->dbs = dev->bar + 4096;
1f390c1f 2606
66341331
BH		 2607 /*
2608 * Some Apple controllers require a non-standard SQE size.
2609 * Interestingly they also seem to ignore the CC:IOSQES register
2610 * so we don't bother updating it here.
2611 */
2612 if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES)
2613 dev->io_sqes = 7;
2614 else
2615 dev->io_sqes = NVME_NVM_IOSQES;
1f390c1f
SG		 2616
2617 /*
2618 * Temporary fix for the Apple controller found in the MacBook8,1 and
2619 * some MacBook7,1 to avoid controller resets and data loss.
2620 */
2621 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
2622 dev->q_depth = 2;
9bdcfb10
CH		 2623 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
2624 "set queue depth=%u to work around controller resets\n",
1f390c1f 2625 dev->q_depth);
d554b5e1
MP		 2626 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2627 (pdev->device == 0xa821 || pdev->device == 0xa822) &&
20d0dfe6 2628 NVME_CAP_MQES(dev->ctrl.cap) == 0) {
d554b5e1
MP		 2629 dev->q_depth = 64;
2630 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2631 "set queue depth=%u\n", dev->q_depth);
1f390c1f
SG		 2632 }
2633
d38e9f04
BH		 2634 /*
2635 * Controllers with the shared tags quirk need the IO queue to be
2636 * big enough so that we get 32 tags for the admin queue
2637 */
2638 if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) &&
2639 (dev->q_depth < (NVME_AQ_DEPTH + 2))) {
2640 dev->q_depth = NVME_AQ_DEPTH + 2;
2641 dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n",
2642 dev->q_depth);
2643 }
2644
2645
f65efd6d 2646 nvme_map_cmb(dev);
202021c1 2647
a0a3408e
KB		 2648 pci_enable_pcie_error_reporting(pdev);
2649 pci_save_state(pdev);
0877cb0d
KB		 2650 return 0;
2651
2652 disable:
0877cb0d
KB		 2653 pci_disable_device(pdev);
2654 return result;
2655}
2656
2657static void nvme_dev_unmap(struct nvme_dev *dev)
b00a726a
KB		 2658{
2659 if (dev->bar)
2660 iounmap(dev->bar);
a1f447b3 2661 pci_release_mem_regions(to_pci_dev(dev->dev));
b00a726a
KB		 2662}
2663
2664static void nvme_pci_disable(struct nvme_dev *dev)
0877cb0d 2665{
e75ec752
CH		 2666 struct pci_dev *pdev = to_pci_dev(dev->dev);
2667
dca51e78 2668 pci_free_irq_vectors(pdev);
0877cb0d 2669
a0a3408e
KB		 2670 if (pci_is_enabled(pdev)) {
2671 pci_disable_pcie_error_reporting(pdev);
e75ec752 2672 pci_disable_device(pdev);
4d115420 2673 }
4d115420
KB		 2674}
2675
a5cdb68c 2676static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
b60503ba 2677{
e43269e6 2678 bool dead = true, freeze = false;
302ad8cc 2679 struct pci_dev *pdev = to_pci_dev(dev->dev);
22404274 2680
77bf25ea 2681 mutex_lock(&dev->shutdown_lock);
081f5e75
KB		 2682 if (pci_is_enabled(pdev)) {
2683 u32 csts;
2684
2685 if (pci_device_is_present(pdev))
2686 csts = readl(dev->bar + NVME_REG_CSTS);
2687 else
2688 csts = ~0;
302ad8cc 2689
ebef7368 2690 if (dev->ctrl.state == NVME_CTRL_LIVE ||
e43269e6
KB		 2691 dev->ctrl.state == NVME_CTRL_RESETTING) {
2692 freeze = true;
302ad8cc 2693 nvme_start_freeze(&dev->ctrl);
e43269e6 2694 }
302ad8cc
KB		 2695 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
2696 pdev->error_state != pci_channel_io_normal);
c9d3bf88 2697 }
c21377f8 2698
302ad8cc
KB		 2699 /*
2700 * Give the controller a chance to complete all entered requests if
2701 * doing a safe shutdown.
2702 */
e43269e6
KB		 2703 if (!dead && shutdown && freeze)
2704 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
9a915a5b
JW		 2705
2706 nvme_stop_queues(&dev->ctrl);
87ad72a5 2707
64ee0ac0 2708 if (!dead && dev->ctrl.queue_count > 0) {
8fae268b 2709 nvme_disable_io_queues(dev);
a5cdb68c 2710 nvme_disable_admin_queue(dev, shutdown);
4d115420 2711 }
8fae268b
KB		 2712 nvme_suspend_io_queues(dev);
2713 nvme_suspend_queue(&dev->queues[0]);
b00a726a 2714 nvme_pci_disable(dev);
fa46c6fb 2715 nvme_reap_pending_cqes(dev);
07836e65 2716
1fcfca78
GL		 2717 nvme_cancel_tagset(&dev->ctrl);
2718 nvme_cancel_admin_tagset(&dev->ctrl);
302ad8cc
KB		 2719
2720 /*
2721 * The driver will not be starting up queues again if shutting down so
2722 * must flush all entered requests to their failed completion to avoid
2723 * deadlocking blk-mq hot-cpu notifier.
2724 */
c8e9e9b7 2725 if (shutdown) {
302ad8cc 2726 nvme_start_queues(&dev->ctrl);
c8e9e9b7 2727 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q))
6ca1d902 2728 nvme_start_admin_queue(&dev->ctrl);
c8e9e9b7 2729 }
77bf25ea 2730 mutex_unlock(&dev->shutdown_lock);
b60503ba
MW		 2731}
2732
c1ac9a4b
KB		 2733static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown)
2734{
2735 if (!nvme_wait_reset(&dev->ctrl))
2736 return -EBUSY;
2737 nvme_dev_disable(dev, shutdown);
2738 return 0;
2739}
2740
091b6092
MW		 2741static int nvme_setup_prp_pools(struct nvme_dev *dev)
2742{
e75ec752 2743 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
c61b82c7
CH		 2744 NVME_CTRL_PAGE_SIZE,
2745 NVME_CTRL_PAGE_SIZE, 0);
091b6092
MW		 2746 if (!dev->prp_page_pool)
2747 return -ENOMEM;
2748
99802a7a 2749 /* Optimisation for I/Os between 4k and 128k */
e75ec752 2750 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
99802a7a
MW		 2751 256, 256, 0);
2752 if (!dev->prp_small_pool) {
2753 dma_pool_destroy(dev->prp_page_pool);
2754 return -ENOMEM;
2755 }
091b6092
MW		 2756 return 0;
2757}
2758
2759static void nvme_release_prp_pools(struct nvme_dev *dev)
2760{
2761 dma_pool_destroy(dev->prp_page_pool);
99802a7a 2762 dma_pool_destroy(dev->prp_small_pool);
091b6092
MW		 2763}
2764
770597ec
KB		 2765static void nvme_free_tagset(struct nvme_dev *dev)
2766{
2767 if (dev->tagset.tags)
2768 blk_mq_free_tag_set(&dev->tagset);
2769 dev->ctrl.tagset = NULL;
2770}
2771
1673f1f0 2772static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
5e82e952 2773{
1673f1f0 2774 struct nvme_dev *dev = to_nvme_dev(ctrl);
9ac27090 2775
f9f38e33 2776 nvme_dbbuf_dma_free(dev);
770597ec 2777 nvme_free_tagset(dev);
1c63dc66
CH		 2778 if (dev->ctrl.admin_q)
2779 blk_put_queue(dev->ctrl.admin_q);
e286bcfc 2780 free_opal_dev(dev->ctrl.opal_dev);
943e942e 2781 mempool_destroy(dev->iod_mempool);
253fd4ac
IR		 2782 put_device(dev->dev);
2783 kfree(dev->queues);
5e82e952
KB		 2784 kfree(dev);
2785}
2786
7c1ce408 2787static void nvme_remove_dead_ctrl(struct nvme_dev *dev)
f58944e2 2788{
c1ac9a4b
KB		 2789 /*
2790 * Set state to deleting now to avoid blocking nvme_wait_reset(), which
2791 * may be holding this pci_dev's device lock.
2792 */
2793 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
d22524a4 2794 nvme_get_ctrl(&dev->ctrl);
69d9a99c 2795 nvme_dev_disable(dev, false);
9f9cafc1 2796 nvme_kill_queues(&dev->ctrl);
03e0f3a6 2797 if (!queue_work(nvme_wq, &dev->remove_work))
f58944e2
KB		 2798 nvme_put_ctrl(&dev->ctrl);
2799}
2800
fd634f41 2801static void nvme_reset_work(struct work_struct *work)
5e82e952 2802{
d86c4d8e
CH		 2803 struct nvme_dev *dev =
2804 container_of(work, struct nvme_dev, ctrl.reset_work);
a98e58e5 2805 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
e71afda4 2806 int result;
5e82e952 2807
7764656b
ZC		 2808 if (dev->ctrl.state != NVME_CTRL_RESETTING) {
2809 dev_warn(dev->ctrl.device, "ctrl state %d is not RESETTING\n",
2810 dev->ctrl.state);
e71afda4 2811 result = -ENODEV;
fd634f41 2812 goto out;
e71afda4 2813 }
5e82e952 2814
fd634f41
CH		 2815 /*
2816 * If we're called to reset a live controller first shut it down before
2817 * moving on.
2818 */
b00a726a 2819 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
a5cdb68c 2820 nvme_dev_disable(dev, false);
d6135c3a 2821 nvme_sync_queues(&dev->ctrl);
5e82e952 2822
5c959d73 2823 mutex_lock(&dev->shutdown_lock);
b00a726a 2824 result = nvme_pci_enable(dev);
f0b50732 2825 if (result)
4726bcf3 2826 goto out_unlock;
f0b50732 2827
01ad0990 2828 result = nvme_pci_configure_admin_queue(dev);
f0b50732 2829 if (result)
4726bcf3 2830 goto out_unlock;
f0b50732 2831
f91b727c
CH		 2832 if (!dev->ctrl.admin_q) {
2833 result = nvme_pci_alloc_admin_tag_set(dev);
2834 if (result)
2835 goto out_unlock;
2836 } else {
2837 nvme_start_admin_queue(&dev->ctrl);
2838 }
b9afca3e 2839
61ce339f
RB		 2840 dma_set_min_align_mask(dev->dev, NVME_CTRL_PAGE_SIZE - 1);
2841
943e942e
JA		 2842 /*
2843 * Limit the max command size to prevent iod->sg allocations going
2844 * over a single page.
2845 */
7637de31
CH		 2846 dev->ctrl.max_hw_sectors = min_t(u32,
2847 NVME_MAX_KB_SZ << 1, dma_max_mapping_size(dev->dev) >> 9);
943e942e 2848 dev->ctrl.max_segments = NVME_MAX_SEGS;
a48bc520
CH		 2849
2850 /*
2851 * Don't limit the IOMMU merged segment size.
2852 */
2853 dma_set_max_seg_size(dev->dev, 0xffffffff);
2854
5c959d73
KB		 2855 mutex_unlock(&dev->shutdown_lock);
2856
2857 /*
2858 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
2859 * initializing procedure here.
2860 */
2861 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
2862 dev_warn(dev->ctrl.device,
2863 "failed to mark controller CONNECTING\n");
cee6c269 2864 result = -EBUSY;
5c959d73
KB		 2865 goto out;
2866 }
943e942e 2867
95093350
MG		 2868 /*
2869 * We do not support an SGL for metadata (yet), so we are limited to a
2870 * single integrity segment for the separate metadata pointer.
2871 */
2872 dev->ctrl.max_integrity_segments = 1;
2873
f21c4769 2874 result = nvme_init_ctrl_finish(&dev->ctrl);
ce4541f4 2875 if (result)
f58944e2 2876 goto out;
ce4541f4 2877
e286bcfc
SB		 2878 if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
2879 if (!dev->ctrl.opal_dev)
2880 dev->ctrl.opal_dev =
2881 init_opal_dev(&dev->ctrl, &nvme_sec_submit);
2882 else if (was_suspend)
2883 opal_unlock_from_suspend(dev->ctrl.opal_dev);
2884 } else {
2885 free_opal_dev(dev->ctrl.opal_dev);
2886 dev->ctrl.opal_dev = NULL;
4f1244c8 2887 }
a98e58e5 2888
f9f38e33
HK		 2889 if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) {
2890 result = nvme_dbbuf_dma_alloc(dev);
2891 if (result)
2892 dev_warn(dev->dev,
2893 "unable to allocate dma for dbbuf\n");
2894 }
2895
9620cfba
CH		 2896 if (dev->ctrl.hmpre) {
2897 result = nvme_setup_host_mem(dev);
2898 if (result < 0)
2899 goto out;
2900 }
87ad72a5 2901
f0b50732 2902 result = nvme_setup_io_queues(dev);
badc34d4 2903 if (result)
f58944e2 2904 goto out;
f0b50732 2905
2659e57b
CH		 2906 /*
2907 * Keep the controller around but remove all namespaces if we don't have
2908 * any working I/O queue.
2909 */
3cf519b5 2910 if (dev->online_queues < 2) {
1b3c47c1 2911 dev_warn(dev->ctrl.device, "IO queues not created\n");
3b24774e 2912 nvme_kill_queues(&dev->ctrl);
5bae7f73 2913 nvme_remove_namespaces(&dev->ctrl);
770597ec 2914 nvme_free_tagset(dev);
3cf519b5 2915 } else {
25646264 2916 nvme_start_queues(&dev->ctrl);
302ad8cc 2917 nvme_wait_freeze(&dev->ctrl);
2455a4b7
CH		 2918 if (!dev->ctrl.tagset)
2919 nvme_pci_alloc_tag_set(dev);
2920 else
2921 nvme_pci_update_nr_queues(dev);
2922 nvme_dbbuf_set(dev);
302ad8cc 2923 nvme_unfreeze(&dev->ctrl);
3cf519b5
CH		 2924 }
2925
2b1b7e78
JW		 2926 /*
2927 * If only admin queue live, keep it to do further investigation or
2928 * recovery.
2929 */
5d02a5c1 2930 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
2b1b7e78 2931 dev_warn(dev->ctrl.device,
5d02a5c1 2932 "failed to mark controller live state\n");
e71afda4 2933 result = -ENODEV;
bb8d261e
CH		 2934 goto out;
2935 }
92911a55 2936
0521905e
KB		 2937 if (!dev->attrs_added && !sysfs_create_group(&dev->ctrl.device->kobj,
2938 &nvme_pci_attr_group))
2939 dev->attrs_added = true;
2940
d09f2b45 2941 nvme_start_ctrl(&dev->ctrl);
3cf519b5 2942 return;
f0b50732 2943
4726bcf3
KB		 2944 out_unlock:
2945 mutex_unlock(&dev->shutdown_lock);
3cf519b5 2946 out:
7c1ce408
CK		 2947 if (result)
2948 dev_warn(dev->ctrl.device,
2949 "Removing after probe failure status: %d\n", result);
2950 nvme_remove_dead_ctrl(dev);
f0b50732
KB		 2951}
2952
5c8809e6 2953static void nvme_remove_dead_ctrl_work(struct work_struct *work)
9a6b9458 2954{
5c8809e6 2955 struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
e75ec752 2956 struct pci_dev *pdev = to_pci_dev(dev->dev);
9a6b9458
KB		 2957
2958 if (pci_get_drvdata(pdev))
921920ab 2959 device_release_driver(&pdev->dev);
1673f1f0 2960 nvme_put_ctrl(&dev->ctrl);
9a6b9458
KB		 2961}
2962
1c63dc66 2963static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
9ca97374 2964{
1c63dc66 2965 *val = readl(to_nvme_dev(ctrl)->bar + off);
90667892 2966 return 0;
9ca97374
TH		 2967}
2968
5fd4ce1b 2969static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
4cc06521 2970{
5fd4ce1b
CH		 2971 writel(val, to_nvme_dev(ctrl)->bar + off);
2972 return 0;
2973}
4cc06521 2974
7fd8930f
CH		 2975static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2976{
3a8ecc93 2977 *val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off);
7fd8930f 2978 return 0;
4cc06521
KB		 2979}
2980
97c12223
KB		 2981static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
2982{
2983 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2984
2db24e4a 2985 return snprintf(buf, size, "%s\n", dev_name(&pdev->dev));
97c12223
KB		 2986}
2987
2f0dad17
KB		 2988static void nvme_pci_print_device_info(struct nvme_ctrl *ctrl)
2989{
2990 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2991 struct nvme_subsystem *subsys = ctrl->subsys;
2992
2993 dev_err(ctrl->device,
2994 "VID:DID %04x:%04x model:%.*s firmware:%.*s\n",
2995 pdev->vendor, pdev->device,
2996 nvme_strlen(subsys->model, sizeof(subsys->model)),
2997 subsys->model, nvme_strlen(subsys->firmware_rev,
2998 sizeof(subsys->firmware_rev)),
2999 subsys->firmware_rev);
3000}
3001
2f859441
LG		 3002static bool nvme_pci_supports_pci_p2pdma(struct nvme_ctrl *ctrl)
3003{
3004 struct nvme_dev *dev = to_nvme_dev(ctrl);
3005
3006 return dma_pci_p2pdma_supported(dev->dev);
3007}
3008
1c63dc66 3009static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
1a353d85 3010 .name = "pcie",
e439bb12 3011 .module = THIS_MODULE,
2f859441 3012 .flags = NVME_F_METADATA_SUPPORTED,
1c63dc66 3013 .reg_read32 = nvme_pci_reg_read32,
5fd4ce1b 3014 .reg_write32 = nvme_pci_reg_write32,
7fd8930f 3015 .reg_read64 = nvme_pci_reg_read64,
1673f1f0 3016 .free_ctrl = nvme_pci_free_ctrl,
f866fc42 3017 .submit_async_event = nvme_pci_submit_async_event,
97c12223 3018 .get_address = nvme_pci_get_address,
2f0dad17 3019 .print_device_info = nvme_pci_print_device_info,
2f859441 3020 .supports_pci_p2pdma = nvme_pci_supports_pci_p2pdma,
1c63dc66 3021};
4cc06521 3022
b00a726a
KB		 3023static int nvme_dev_map(struct nvme_dev *dev)
3024{
b00a726a
KB		 3025 struct pci_dev *pdev = to_pci_dev(dev->dev);
3026
a1f447b3 3027 if (pci_request_mem_regions(pdev, "nvme"))
b00a726a
KB		 3028 return -ENODEV;
3029
97f6ef64 3030 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
b00a726a
KB		 3031 goto release;
3032
9fa196e7 3033 return 0;
b00a726a 3034 release:
9fa196e7
MG		 3035 pci_release_mem_regions(pdev);
3036 return -ENODEV;
b00a726a
KB		 3037}
3038
8427bbc2 3039static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
ff5350a8
AL		 3040{
3041 if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
3042 /*
3043 * Several Samsung devices seem to drop off the PCIe bus
3044 * randomly when APST is on and uses the deepest sleep state.
3045 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
3046 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
3047 * 950 PRO 256GB", but it seems to be restricted to two Dell
3048 * laptops.
3049 */
3050 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
3051 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
3052 dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
3053 return NVME_QUIRK_NO_DEEPEST_PS;
8427bbc2
KHF		 3054 } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
3055 /*
3056 * Samsung SSD 960 EVO drops off the PCIe bus after system
467c77d4
JJ		 3057 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
3058 * within few minutes after bootup on a Coffee Lake board -
3059 * ASUS PRIME Z370-A
8427bbc2
KHF		 3060 */
3061 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
467c77d4
JJ		 3062 (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") ||
3063 dmi_match(DMI_BOARD_NAME, "PRIME Z370-A")))
8427bbc2 3064 return NVME_QUIRK_NO_APST;
1fae37ac
S		 3065 } else if ((pdev->vendor == 0x144d && (pdev->device == 0xa801 ||
3066 pdev->device == 0xa808 || pdev->device == 0xa809)) ||
3067 (pdev->vendor == 0x1e0f && pdev->device == 0x0001)) {
3068 /*
3069 * Forcing to use host managed nvme power settings for
3070 * lowest idle power with quick resume latency on
3071 * Samsung and Toshiba SSDs based on suspend behavior
3072 * on Coffee Lake board for LENOVO C640
3073 */
3074 if ((dmi_match(DMI_BOARD_VENDOR, "LENOVO")) &&
3075 dmi_match(DMI_BOARD_NAME, "LNVNB161216"))
3076 return NVME_QUIRK_SIMPLE_SUSPEND;
ff5350a8
AL		 3077 }
3078
3079 return 0;
3080}
3081
18119775
KB		 3082static void nvme_async_probe(void *data, async_cookie_t cookie)
3083{
3084 struct nvme_dev *dev = data;
80f513b5 3085
bd46a906 3086 flush_work(&dev->ctrl.reset_work);
18119775 3087 flush_work(&dev->ctrl.scan_work);
80f513b5 3088 nvme_put_ctrl(&dev->ctrl);
18119775
KB		 3089}
3090
8d85fce7 3091static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
b60503ba 3092{
a4aea562 3093 int node, result = -ENOMEM;
b60503ba 3094 struct nvme_dev *dev;
ff5350a8 3095 unsigned long quirks = id->driver_data;
943e942e 3096 size_t alloc_size;
b60503ba 3097
a4aea562
MB		 3098 node = dev_to_node(&pdev->dev);
3099 if (node == NUMA_NO_NODE)
2fa84351 3100 set_dev_node(&pdev->dev, first_memory_node);
a4aea562
MB		 3101
3102 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
b60503ba
MW		 3103 if (!dev)
3104 return -ENOMEM;
147b27e4 3105
2a5bcfdd
WZ		 3106 dev->nr_write_queues = write_queues;
3107 dev->nr_poll_queues = poll_queues;
3108 dev->nr_allocated_queues = nvme_max_io_queues(dev) + 1;
3109 dev->queues = kcalloc_node(dev->nr_allocated_queues,
3110 sizeof(struct nvme_queue), GFP_KERNEL, node);
b60503ba
MW		 3111 if (!dev->queues)
3112 goto free;
3113
e75ec752 3114 dev->dev = get_device(&pdev->dev);
9a6b9458 3115 pci_set_drvdata(pdev, dev);
1c63dc66 3116
b00a726a
KB		 3117 result = nvme_dev_map(dev);
3118 if (result)
b00c9b7a 3119 goto put_pci;
b00a726a 3120
d86c4d8e 3121 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
5c8809e6 3122 INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
77bf25ea 3123 mutex_init(&dev->shutdown_lock);
b60503ba 3124
091b6092
MW		 3125 result = nvme_setup_prp_pools(dev);
3126 if (result)
b00c9b7a 3127 goto unmap;
4cc06521 3128
8427bbc2 3129 quirks |= check_vendor_combination_bug(pdev);
ff5350a8 3130
2744d7a0 3131 if (!noacpi && acpi_storage_d3(&pdev->dev)) {
df4f9bc4
DB		 3132 /*
3133 * Some systems use a bios work around to ask for D3 on
3134 * platforms that support kernel managed suspend.
3135 */
3136 dev_info(&pdev->dev,
3137 "platform quirk: setting simple suspend\n");
3138 quirks |= NVME_QUIRK_SIMPLE_SUSPEND;
3139 }
3140
943e942e
JA		 3141 /*
3142 * Double check that our mempool alloc size will cover the biggest
3143 * command we support.
3144 */
b13c6393 3145 alloc_size = nvme_pci_iod_alloc_size();
943e942e
JA		 3146 WARN_ON_ONCE(alloc_size > PAGE_SIZE);
3147
3148 dev->iod_mempool = mempool_create_node(1, mempool_kmalloc,
3149 mempool_kfree,
3150 (void *) alloc_size,
3151 GFP_KERNEL, node);
3152 if (!dev->iod_mempool) {
3153 result = -ENOMEM;
3154 goto release_pools;
3155 }
3156
b6e44b4c
KB		 3157 result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
3158 quirks);
3159 if (result)
3160 goto release_mempool;
3161
1b3c47c1
SG		 3162 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
3163
bd46a906 3164 nvme_reset_ctrl(&dev->ctrl);
18119775 3165 async_schedule(nvme_async_probe, dev);
4caff8fc 3166
b60503ba
MW		 3167 return 0;
3168
b6e44b4c
KB		 3169 release_mempool:
3170 mempool_destroy(dev->iod_mempool);
0877cb0d 3171 release_pools:
091b6092 3172 nvme_release_prp_pools(dev);
b00c9b7a
CJ		 3173 unmap:
3174 nvme_dev_unmap(dev);
a96d4f5c 3175 put_pci:
e75ec752 3176 put_device(dev->dev);
b60503ba
MW		 3177 free:
3178 kfree(dev->queues);
b60503ba
MW		 3179 kfree(dev);
3180 return result;
3181}
3182
775755ed 3183static void nvme_reset_prepare(struct pci_dev *pdev)
f0d54a54 3184{
a6739479 3185 struct nvme_dev *dev = pci_get_drvdata(pdev);
c1ac9a4b
KB		 3186
3187 /*
3188 * We don't need to check the return value from waiting for the reset
3189 * state as pci_dev device lock is held, making it impossible to race
3190 * with ->remove().
3191 */
3192 nvme_disable_prepare_reset(dev, false);
3193 nvme_sync_queues(&dev->ctrl);
775755ed 3194}
f0d54a54 3195
775755ed
CH		 3196static void nvme_reset_done(struct pci_dev *pdev)
3197{
f263fbb8 3198 struct nvme_dev *dev = pci_get_drvdata(pdev);
c1ac9a4b
KB		 3199
3200 if (!nvme_try_sched_reset(&dev->ctrl))
3201 flush_work(&dev->ctrl.reset_work);
f0d54a54
KB		 3202}
3203
09ece142
KB		 3204static void nvme_shutdown(struct pci_dev *pdev)
3205{
3206 struct nvme_dev *dev = pci_get_drvdata(pdev);
4e523547 3207
c1ac9a4b 3208 nvme_disable_prepare_reset(dev, true);
09ece142
KB		 3209}
3210
0521905e
KB		 3211static void nvme_remove_attrs(struct nvme_dev *dev)
3212{
3213 if (dev->attrs_added)
3214 sysfs_remove_group(&dev->ctrl.device->kobj,
3215 &nvme_pci_attr_group);
3216}
3217
f58944e2
KB		 3218/*
3219 * The driver's remove may be called on a device in a partially initialized
3220 * state. This function must not have any dependencies on the device state in
3221 * order to proceed.
3222 */
8d85fce7 3223static void nvme_remove(struct pci_dev *pdev)
b60503ba
MW		 3224{
3225 struct nvme_dev *dev = pci_get_drvdata(pdev);
9a6b9458 3226
bb8d261e 3227 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
9a6b9458 3228 pci_set_drvdata(pdev, NULL);
0ff9d4e1 3229
6db28eda 3230 if (!pci_device_is_present(pdev)) {
0ff9d4e1 3231 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
1d39e692 3232 nvme_dev_disable(dev, true);
6db28eda 3233 }
0ff9d4e1 3234
d86c4d8e 3235 flush_work(&dev->ctrl.reset_work);
d09f2b45
SG		 3236 nvme_stop_ctrl(&dev->ctrl);
3237 nvme_remove_namespaces(&dev->ctrl);
a5cdb68c 3238 nvme_dev_disable(dev, true);
0521905e 3239 nvme_remove_attrs(dev);
87ad72a5 3240 nvme_free_host_mem(dev);
a4aea562 3241 nvme_dev_remove_admin(dev);
a1a5ef99 3242 nvme_free_queues(dev, 0);
9a6b9458 3243 nvme_release_prp_pools(dev);
b00a726a 3244 nvme_dev_unmap(dev);
726612b6 3245 nvme_uninit_ctrl(&dev->ctrl);
b60503ba
MW		 3246}
3247
671a6018 3248#ifdef CONFIG_PM_SLEEP
d916b1be
KB		 3249static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps)
3250{
3251 return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps);
3252}
3253
3254static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps)
3255{
3256 return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL);
3257}
3258
3259static int nvme_resume(struct device *dev)
3260{
3261 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
3262 struct nvme_ctrl *ctrl = &ndev->ctrl;
3263
4eaefe8c 3264 if (ndev->last_ps == U32_MAX ||
d916b1be 3265 nvme_set_power_state(ctrl, ndev->last_ps) != 0)
e5ad96f3
KB		 3266 goto reset;
3267 if (ctrl->hmpre && nvme_setup_host_mem(ndev))
3268 goto reset;
3269
d916b1be 3270 return 0;
e5ad96f3
KB		 3271reset:
3272 return nvme_try_sched_reset(ctrl);
d916b1be
KB		 3273}
3274
cd638946
KB		 3275static int nvme_suspend(struct device *dev)
3276{
3277 struct pci_dev *pdev = to_pci_dev(dev);
3278 struct nvme_dev *ndev = pci_get_drvdata(pdev);
d916b1be
KB		 3279 struct nvme_ctrl *ctrl = &ndev->ctrl;
3280 int ret = -EBUSY;
3281
4eaefe8c
RW		 3282 ndev->last_ps = U32_MAX;
3283
d916b1be
KB		 3284 /*
3285 * The platform does not remove power for a kernel managed suspend so
3286 * use host managed nvme power settings for lowest idle power if
3287 * possible. This should have quicker resume latency than a full device
3288 * shutdown. But if the firmware is involved after the suspend or the
3289 * device does not support any non-default power states, shut down the
3290 * device fully.
4eaefe8c
RW		 3291 *
3292 * If ASPM is not enabled for the device, shut down the device and allow
3293 * the PCI bus layer to put it into D3 in order to take the PCIe link
3294 * down, so as to allow the platform to achieve its minimum low-power
3295 * state (which may not be possible if the link is up).
d916b1be 3296 */
4eaefe8c 3297 if (pm_suspend_via_firmware() || !ctrl->npss ||
cb32de1b 3298 !pcie_aspm_enabled(pdev) ||
c1ac9a4b
KB		 3299 (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND))
3300 return nvme_disable_prepare_reset(ndev, true);
d916b1be
KB		 3301
3302 nvme_start_freeze(ctrl);
3303 nvme_wait_freeze(ctrl);
3304 nvme_sync_queues(ctrl);
3305
5d02a5c1 3306 if (ctrl->state != NVME_CTRL_LIVE)
d916b1be
KB		 3307 goto unfreeze;
3308
e5ad96f3
KB		 3309 /*
3310 * Host memory access may not be successful in a system suspend state,
3311 * but the specification allows the controller to access memory in a
3312 * non-operational power state.
3313 */
3314 if (ndev->hmb) {
3315 ret = nvme_set_host_mem(ndev, 0);
3316 if (ret < 0)
3317 goto unfreeze;
3318 }
3319
d916b1be
KB		 3320 ret = nvme_get_power_state(ctrl, &ndev->last_ps);
3321 if (ret < 0)
3322 goto unfreeze;
3323
7cbb5c6f
ML		 3324 /*
3325 * A saved state prevents pci pm from generically controlling the
3326 * device's power. If we're using protocol specific settings, we don't
3327 * want pci interfering.
3328 */
3329 pci_save_state(pdev);
3330
d916b1be
KB		 3331 ret = nvme_set_power_state(ctrl, ctrl->npss);
3332 if (ret < 0)
3333 goto unfreeze;
3334
3335 if (ret) {
7cbb5c6f
ML		 3336 /* discard the saved state */
3337 pci_load_saved_state(pdev, NULL);
3338
d916b1be
KB		 3339 /*
3340 * Clearing npss forces a controller reset on resume. The
05d3046f 3341 * correct value will be rediscovered then.
d916b1be 3342 */
c1ac9a4b 3343 ret = nvme_disable_prepare_reset(ndev, true);
d916b1be 3344 ctrl->npss = 0;
d916b1be 3345 }
d916b1be
KB		 3346unfreeze:
3347 nvme_unfreeze(ctrl);
3348 return ret;
3349}
3350
3351static int nvme_simple_suspend(struct device *dev)
3352{
3353 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
4e523547 3354
c1ac9a4b 3355 return nvme_disable_prepare_reset(ndev, true);
cd638946
KB		 3356}
3357
d916b1be 3358static int nvme_simple_resume(struct device *dev)
cd638946
KB		 3359{
3360 struct pci_dev *pdev = to_pci_dev(dev);
3361 struct nvme_dev *ndev = pci_get_drvdata(pdev);
cd638946 3362
c1ac9a4b 3363 return nvme_try_sched_reset(&ndev->ctrl);
cd638946
KB		 3364}
3365
21774222 3366static const struct dev_pm_ops nvme_dev_pm_ops = {
d916b1be
KB		 3367 .suspend = nvme_suspend,
3368 .resume = nvme_resume,
3369 .freeze = nvme_simple_suspend,
3370 .thaw = nvme_simple_resume,
3371 .poweroff = nvme_simple_suspend,
3372 .restore = nvme_simple_resume,
3373};
3374#endif /* CONFIG_PM_SLEEP */
b60503ba 3375
a0a3408e
KB		 3376static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
3377 pci_channel_state_t state)
3378{
3379 struct nvme_dev *dev = pci_get_drvdata(pdev);
3380
3381 /*
3382 * A frozen channel requires a reset. When detected, this method will
3383 * shutdown the controller to quiesce. The controller will be restarted
3384 * after the slot reset through driver's slot_reset callback.
3385 */
a0a3408e
KB		 3386 switch (state) {
3387 case pci_channel_io_normal:
3388 return PCI_ERS_RESULT_CAN_RECOVER;
3389 case pci_channel_io_frozen:
d011fb31
KB		 3390 dev_warn(dev->ctrl.device,
3391 "frozen state error detected, reset controller\n");
a5cdb68c 3392 nvme_dev_disable(dev, false);
a0a3408e
KB		 3393 return PCI_ERS_RESULT_NEED_RESET;
3394 case pci_channel_io_perm_failure:
d011fb31
KB		 3395 dev_warn(dev->ctrl.device,
3396 "failure state error detected, request disconnect\n");
a0a3408e
KB		 3397 return PCI_ERS_RESULT_DISCONNECT;
3398 }
3399 return PCI_ERS_RESULT_NEED_RESET;
3400}
3401
3402static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
3403{
3404 struct nvme_dev *dev = pci_get_drvdata(pdev);
3405
1b3c47c1 3406 dev_info(dev->ctrl.device, "restart after slot reset\n");
a0a3408e 3407 pci_restore_state(pdev);
d86c4d8e 3408 nvme_reset_ctrl(&dev->ctrl);
a0a3408e
KB		 3409 return PCI_ERS_RESULT_RECOVERED;
3410}
3411
3412static void nvme_error_resume(struct pci_dev *pdev)
3413{
72cd4cc2
KB		 3414 struct nvme_dev *dev = pci_get_drvdata(pdev);
3415
3416 flush_work(&dev->ctrl.reset_work);
a0a3408e
KB		 3417}
3418
1d352035 3419static const struct pci_error_handlers nvme_err_handler = {
b60503ba 3420 .error_detected = nvme_error_detected,
b60503ba
MW		 3421 .slot_reset = nvme_slot_reset,
3422 .resume = nvme_error_resume,
775755ed
CH		 3423 .reset_prepare = nvme_reset_prepare,
3424 .reset_done = nvme_reset_done,
b60503ba
MW		 3425};
3426
6eb0d698 3427static const struct pci_device_id nvme_id_table[] = {
972b13e2 3428 { PCI_VDEVICE(INTEL, 0x0953), /* Intel 750/P3500/P3600/P3700 */
08095e70 3429 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 3430 NVME_QUIRK_DEALLOCATE_ZEROES, },
972b13e2 3431 { PCI_VDEVICE(INTEL, 0x0a53), /* Intel P3520 */
99466e70 3432 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 3433 NVME_QUIRK_DEALLOCATE_ZEROES, },
972b13e2 3434 { PCI_VDEVICE(INTEL, 0x0a54), /* Intel P4500/P4600 */
99466e70 3435 .driver_data = NVME_QUIRK_STRIPE_SIZE |
25e58af4
WZ		 3436 NVME_QUIRK_DEALLOCATE_ZEROES |
3437 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
972b13e2 3438 { PCI_VDEVICE(INTEL, 0x0a55), /* Dell Express Flash P4600 */
f99cb7af
DWF		 3439 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3440 NVME_QUIRK_DEALLOCATE_ZEROES, },
50af47d0 3441 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */
9abd68ef 3442 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
6c6aa2f2 3443 NVME_QUIRK_MEDIUM_PRIO_SQ |
ce4cc313
DM		 3444 NVME_QUIRK_NO_TEMP_THRESH_CHANGE |
3445 NVME_QUIRK_DISABLE_WRITE_ZEROES, },
6299358d
JD		 3446 { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */
3447 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
540c801c 3448 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */
7b210e4e 3449 .driver_data = NVME_QUIRK_IDENTIFY_CNS |
66dd346b
CH		 3450 NVME_QUIRK_DISABLE_WRITE_ZEROES |
3451 NVME_QUIRK_BOGUS_NID, },
3452 { PCI_VDEVICE(REDHAT, 0x0010), /* Qemu emulated controller */
3453 .driver_data = NVME_QUIRK_BOGUS_NID, },
5bedd3af 3454 { PCI_DEVICE(0x126f, 0x2263), /* Silicon Motion unidentified */
c98a8793
KB		 3455 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST |
3456 NVME_QUIRK_BOGUS_NID, },
0302ae60 3457 { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */
5e112d3f
JE		 3458 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
3459 NVME_QUIRK_NO_NS_DESC_LIST, },
54adc010
GP		 3460 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
3461 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
8c97eecc
JL		 3462 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */
3463 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
015282c9
WW		 3464 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
3465 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
d554b5e1
MP		 3466 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */
3467 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3468 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */
7ee5c78c 3469 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
abbb5f59 3470 NVME_QUIRK_DISABLE_WRITE_ZEROES|
7ee5c78c 3471 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
2cf7a77e
KB		 3472 { PCI_DEVICE(0x1987, 0x5012), /* Phison E12 */
3473 .driver_data = NVME_QUIRK_BOGUS_NID, },
c9e95c39 3474 { PCI_DEVICE(0x1987, 0x5016), /* Phison E16 */
73029c9b
KB		 3475 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN |
3476 NVME_QUIRK_BOGUS_NID, },
d14c2731
TH		 3477 { PCI_DEVICE(0x1987, 0x5019), /* phison E19 */
3478 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3479 { PCI_DEVICE(0x1987, 0x5021), /* Phison E21 */
3480 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
6e6a6828
PT		 3481 { PCI_DEVICE(0x1b4b, 0x1092), /* Lexar 256 GB SSD */
3482 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST |
3483 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
e1c70d79
LVS		 3484 { PCI_DEVICE(0x1cc1, 0x33f8), /* ADATA IM2P33F8ABR1 1 TB */
3485 .driver_data = NVME_QUIRK_BOGUS_NID, },
08b903b5 3486 { PCI_DEVICE(0x10ec, 0x5762), /* ADATA SX6000LNP */
1629de0e
PG		 3487 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN |
3488 NVME_QUIRK_BOGUS_NID, },
f03e42c6
GC		 3489 { PCI_DEVICE(0x1cc1, 0x8201), /* ADATA SX8200PNP 512GB */
3490 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3491 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
41f38043
LS		 3492 { PCI_DEVICE(0x1344, 0x5407), /* Micron Technology Inc NVMe SSD */
3493 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN },
5611ec2b
KHF		 3494 { PCI_DEVICE(0x1c5c, 0x1504), /* SK Hynix PC400 */
3495 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
c4f01a77
KB		 3496 { PCI_DEVICE(0x1c5c, 0x174a), /* SK Hynix P31 SSD */
3497 .driver_data = NVME_QUIRK_BOGUS_NID, },
02ca079c
KHF		 3498 { PCI_DEVICE(0x15b7, 0x2001), /* Sandisk Skyhawk */
3499 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
89919929
CK		 3500 { PCI_DEVICE(0x1d97, 0x2263), /* SPCC */
3501 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
43047e08 3502 { PCI_DEVICE(0x144d, 0xa80b), /* Samsung PM9B1 256G and 512G */
3503 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3504 { PCI_DEVICE(0x144d, 0xa809), /* Samsung MZALQ256HBJD 256G */
3505 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3506 { PCI_DEVICE(0x1cc4, 0x6303), /* UMIS RPJTJ512MGE1QDY 512G */
3507 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3508 { PCI_DEVICE(0x1cc4, 0x6302), /* UMIS RPJTJ256MGE1QDY 256G */
3509 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
dc22c1c0
ZB		 3510 { PCI_DEVICE(0x2646, 0x2262), /* KINGSTON SKC2000 NVMe SSD */
3511 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
538e4a8c
TL		 3512 { PCI_DEVICE(0x2646, 0x2263), /* KINGSTON A2000 NVMe SSD */
3513 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
70ce3455
CH		 3514 { PCI_DEVICE(0x1e4B, 0x1001), /* MAXIO MAP1001 */
3515 .driver_data = NVME_QUIRK_BOGUS_NID, },
a98a945b
CH		 3516 { PCI_DEVICE(0x1e4B, 0x1002), /* MAXIO MAP1002 */
3517 .driver_data = NVME_QUIRK_BOGUS_NID, },
3518 { PCI_DEVICE(0x1e4B, 0x1202), /* MAXIO MAP1202 */
3519 .driver_data = NVME_QUIRK_BOGUS_NID, },
3765fad5
SR		 3520 { PCI_DEVICE(0x1cc1, 0x5350), /* ADATA XPG GAMMIX S50 */
3521 .driver_data = NVME_QUIRK_BOGUS_NID, },
f37527a0
DK		 3522 { PCI_DEVICE(0x1dbe, 0x5236), /* ADATA XPG GAMMIX S70 */
3523 .driver_data = NVME_QUIRK_BOGUS_NID, },
6b961bce
NW		 3524 { PCI_DEVICE(0x1e49, 0x0041), /* ZHITAI TiPro7000 NVMe SSD */
3525 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
d6c52fa3
TG		 3526 { PCI_DEVICE(0xc0a9, 0x540a), /* Crucial P2 */
3527 .driver_data = NVME_QUIRK_BOGUS_NID, },
200dccd0
SA		 3528 { PCI_DEVICE(0x1d97, 0x2263), /* Lexar NM610 */
3529 .driver_data = NVME_QUIRK_BOGUS_NID, },
4bdf2603
FS		 3530 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0061),
3531 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3532 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0065),
3533 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3534 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x8061),
3535 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3536 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd00),
3537 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3538 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd01),
3539 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3540 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd02),
3541 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
98f7b86a
AS		 3542 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001),
3543 .driver_data = NVME_QUIRK_SINGLE_VECTOR },
124298bd 3544 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
66341331
BH		 3545 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005),
3546 .driver_data = NVME_QUIRK_SINGLE_VECTOR |
d38e9f04 3547 NVME_QUIRK_128_BYTES_SQES |
a2941f6a
KB		 3548 NVME_QUIRK_SHARED_TAGS |
3549 NVME_QUIRK_SKIP_CID_GEN },
0b85f59d 3550 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
b60503ba
MW		 3551 { 0, }
3552};
3553MODULE_DEVICE_TABLE(pci, nvme_id_table);
3554
3555static struct pci_driver nvme_driver = {
3556 .name = "nvme",
3557 .id_table = nvme_id_table,
3558 .probe = nvme_probe,
8d85fce7 3559 .remove = nvme_remove,
09ece142 3560 .shutdown = nvme_shutdown,
d916b1be 3561#ifdef CONFIG_PM_SLEEP
cd638946
KB		 3562 .driver = {
3563 .pm = &nvme_dev_pm_ops,
3564 },
d916b1be 3565#endif
74d986ab 3566 .sriov_configure = pci_sriov_configure_simple,
b60503ba
MW		 3567 .err_handler = &nvme_err_handler,
3568};
3569
3570static int __init nvme_init(void)
3571{
81101540
CH		 3572 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
3573 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
3574 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
612b7286 3575 BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2);
c372cdd1
KB		 3576 BUILD_BUG_ON(DIV_ROUND_UP(nvme_pci_npages_prp(), NVME_CTRL_PAGE_SIZE) >
3577 S8_MAX);
17c33167 3578
9a6327d2 3579 return pci_register_driver(&nvme_driver);
b60503ba
MW		 3580}
3581
3582static void __exit nvme_exit(void)
3583{
3584 pci_unregister_driver(&nvme_driver);
03e0f3a6 3585 flush_workqueue(nvme_wq);
b60503ba
MW		 3586}
3587
3588MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3589MODULE_LICENSE("GPL");
c78b4713 3590MODULE_VERSION("1.0");
b60503ba
MW		 3591module_init(nvme_init);
3592module_exit(nvme_exit);
Linux 6.x block layer and io_uring tree(s)