Commit | Line | Data |
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b60503ba MW |
1 | /* |
2 | * NVM Express device driver | |
6eb0d698 | 3 | * Copyright (c) 2011-2014, Intel Corporation. |
b60503ba MW |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
b60503ba MW |
13 | */ |
14 | ||
8de05535 | 15 | #include <linux/bitops.h> |
b60503ba | 16 | #include <linux/blkdev.h> |
a4aea562 | 17 | #include <linux/blk-mq.h> |
42f61420 | 18 | #include <linux/cpu.h> |
fd63e9ce | 19 | #include <linux/delay.h> |
b60503ba MW |
20 | #include <linux/errno.h> |
21 | #include <linux/fs.h> | |
22 | #include <linux/genhd.h> | |
4cc09e2d | 23 | #include <linux/hdreg.h> |
5aff9382 | 24 | #include <linux/idr.h> |
b60503ba MW |
25 | #include <linux/init.h> |
26 | #include <linux/interrupt.h> | |
27 | #include <linux/io.h> | |
28 | #include <linux/kdev_t.h> | |
1fa6aead | 29 | #include <linux/kthread.h> |
b60503ba MW |
30 | #include <linux/kernel.h> |
31 | #include <linux/mm.h> | |
32 | #include <linux/module.h> | |
33 | #include <linux/moduleparam.h> | |
77bf25ea | 34 | #include <linux/mutex.h> |
b60503ba | 35 | #include <linux/pci.h> |
be7b6275 | 36 | #include <linux/poison.h> |
c3bfe717 | 37 | #include <linux/ptrace.h> |
b60503ba MW |
38 | #include <linux/sched.h> |
39 | #include <linux/slab.h> | |
e1e5e564 | 40 | #include <linux/t10-pi.h> |
b60503ba | 41 | #include <linux/types.h> |
2f8e2c87 | 42 | #include <linux/io-64-nonatomic-lo-hi.h> |
1d277a63 | 43 | #include <asm/unaligned.h> |
797a796a | 44 | |
f11bb3e2 CH |
45 | #include "nvme.h" |
46 | ||
9d43cf64 | 47 | #define NVME_Q_DEPTH 1024 |
d31af0a3 | 48 | #define NVME_AQ_DEPTH 256 |
b60503ba MW |
49 | #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command)) |
50 | #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion)) | |
adf68f21 CH |
51 | |
52 | /* | |
53 | * We handle AEN commands ourselves and don't even let the | |
54 | * block layer know about them. | |
55 | */ | |
56 | #define NVME_NR_AEN_COMMANDS 1 | |
57 | #define NVME_AQ_BLKMQ_DEPTH (NVME_AQ_DEPTH - NVME_NR_AEN_COMMANDS) | |
9d43cf64 | 58 | |
21d34711 | 59 | unsigned char admin_timeout = 60; |
9d43cf64 KB |
60 | module_param(admin_timeout, byte, 0644); |
61 | MODULE_PARM_DESC(admin_timeout, "timeout in seconds for admin commands"); | |
b60503ba | 62 | |
bd67608a MW |
63 | unsigned char nvme_io_timeout = 30; |
64 | module_param_named(io_timeout, nvme_io_timeout, byte, 0644); | |
b355084a | 65 | MODULE_PARM_DESC(io_timeout, "timeout in seconds for I/O"); |
b60503ba | 66 | |
5fd4ce1b | 67 | unsigned char shutdown_timeout = 5; |
2484f407 DM |
68 | module_param(shutdown_timeout, byte, 0644); |
69 | MODULE_PARM_DESC(shutdown_timeout, "timeout in seconds for controller shutdown"); | |
70 | ||
58ffacb5 MW |
71 | static int use_threaded_interrupts; |
72 | module_param(use_threaded_interrupts, int, 0); | |
73 | ||
8ffaadf7 JD |
74 | static bool use_cmb_sqes = true; |
75 | module_param(use_cmb_sqes, bool, 0644); | |
76 | MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes"); | |
77 | ||
1fa6aead MW |
78 | static LIST_HEAD(dev_list); |
79 | static struct task_struct *nvme_thread; | |
9a6b9458 | 80 | static struct workqueue_struct *nvme_workq; |
b9afca3e | 81 | static wait_queue_head_t nvme_kthread_wait; |
1fa6aead | 82 | |
1c63dc66 CH |
83 | struct nvme_dev; |
84 | struct nvme_queue; | |
85 | ||
4cc06521 | 86 | static int nvme_reset(struct nvme_dev *dev); |
a0fa9647 | 87 | static void nvme_process_cq(struct nvme_queue *nvmeq); |
5c8809e6 | 88 | static void nvme_remove_dead_ctrl(struct nvme_dev *dev); |
e1569a16 | 89 | static void nvme_dev_shutdown(struct nvme_dev *dev); |
d4b4ff8e | 90 | |
4d115420 KB |
91 | struct async_cmd_info { |
92 | struct kthread_work work; | |
93 | struct kthread_worker *worker; | |
4d115420 KB |
94 | int status; |
95 | void *ctx; | |
96 | }; | |
1fa6aead | 97 | |
1c63dc66 CH |
98 | /* |
99 | * Represents an NVM Express device. Each nvme_dev is a PCI function. | |
100 | */ | |
101 | struct nvme_dev { | |
102 | struct list_head node; | |
103 | struct nvme_queue **queues; | |
104 | struct blk_mq_tag_set tagset; | |
105 | struct blk_mq_tag_set admin_tagset; | |
106 | u32 __iomem *dbs; | |
107 | struct device *dev; | |
108 | struct dma_pool *prp_page_pool; | |
109 | struct dma_pool *prp_small_pool; | |
110 | unsigned queue_count; | |
111 | unsigned online_queues; | |
112 | unsigned max_qid; | |
113 | int q_depth; | |
114 | u32 db_stride; | |
1c63dc66 CH |
115 | struct msix_entry *entry; |
116 | void __iomem *bar; | |
1c63dc66 | 117 | struct work_struct reset_work; |
1c63dc66 | 118 | struct work_struct scan_work; |
5c8809e6 | 119 | struct work_struct remove_work; |
77bf25ea | 120 | struct mutex shutdown_lock; |
1c63dc66 | 121 | bool subsystem; |
1c63dc66 CH |
122 | void __iomem *cmb; |
123 | dma_addr_t cmb_dma_addr; | |
124 | u64 cmb_size; | |
125 | u32 cmbsz; | |
fd634f41 CH |
126 | unsigned long flags; |
127 | #define NVME_CTRL_RESETTING 0 | |
1c63dc66 CH |
128 | |
129 | struct nvme_ctrl ctrl; | |
130 | }; | |
131 | ||
132 | static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl) | |
133 | { | |
134 | return container_of(ctrl, struct nvme_dev, ctrl); | |
135 | } | |
136 | ||
b60503ba MW |
137 | /* |
138 | * An NVM Express queue. Each device has at least two (one for admin | |
139 | * commands and one for I/O commands). | |
140 | */ | |
141 | struct nvme_queue { | |
142 | struct device *q_dmadev; | |
091b6092 | 143 | struct nvme_dev *dev; |
3193f07b | 144 | char irqname[24]; /* nvme4294967295-65535\0 */ |
b60503ba MW |
145 | spinlock_t q_lock; |
146 | struct nvme_command *sq_cmds; | |
8ffaadf7 | 147 | struct nvme_command __iomem *sq_cmds_io; |
b60503ba | 148 | volatile struct nvme_completion *cqes; |
42483228 | 149 | struct blk_mq_tags **tags; |
b60503ba MW |
150 | dma_addr_t sq_dma_addr; |
151 | dma_addr_t cq_dma_addr; | |
b60503ba MW |
152 | u32 __iomem *q_db; |
153 | u16 q_depth; | |
6222d172 | 154 | s16 cq_vector; |
b60503ba MW |
155 | u16 sq_head; |
156 | u16 sq_tail; | |
157 | u16 cq_head; | |
c30341dc | 158 | u16 qid; |
e9539f47 MW |
159 | u8 cq_phase; |
160 | u8 cqe_seen; | |
4d115420 | 161 | struct async_cmd_info cmdinfo; |
b60503ba MW |
162 | }; |
163 | ||
71bd150c CH |
164 | /* |
165 | * The nvme_iod describes the data in an I/O, including the list of PRP | |
166 | * entries. You can't see it in this data structure because C doesn't let | |
f4800d6d | 167 | * me express that. Use nvme_init_iod to ensure there's enough space |
71bd150c CH |
168 | * allocated to store the PRP list. |
169 | */ | |
170 | struct nvme_iod { | |
f4800d6d CH |
171 | struct nvme_queue *nvmeq; |
172 | int aborted; | |
71bd150c | 173 | int npages; /* In the PRP list. 0 means small pool in use */ |
71bd150c CH |
174 | int nents; /* Used in scatterlist */ |
175 | int length; /* Of data, in bytes */ | |
176 | dma_addr_t first_dma; | |
bf684057 | 177 | struct scatterlist meta_sg; /* metadata requires single contiguous buffer */ |
f4800d6d CH |
178 | struct scatterlist *sg; |
179 | struct scatterlist inline_sg[0]; | |
71bd150c CH |
180 | }; |
181 | ||
b60503ba MW |
182 | /* |
183 | * Check we didin't inadvertently grow the command struct | |
184 | */ | |
185 | static inline void _nvme_check_size(void) | |
186 | { | |
187 | BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64); | |
188 | BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); | |
189 | BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); | |
190 | BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); | |
191 | BUILD_BUG_ON(sizeof(struct nvme_features) != 64); | |
f8ebf840 | 192 | BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64); |
c30341dc | 193 | BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64); |
b60503ba MW |
194 | BUILD_BUG_ON(sizeof(struct nvme_command) != 64); |
195 | BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096); | |
196 | BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096); | |
197 | BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64); | |
6ecec745 | 198 | BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512); |
b60503ba MW |
199 | } |
200 | ||
ac3dd5bd JA |
201 | /* |
202 | * Max size of iod being embedded in the request payload | |
203 | */ | |
204 | #define NVME_INT_PAGES 2 | |
5fd4ce1b | 205 | #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size) |
ac3dd5bd JA |
206 | |
207 | /* | |
208 | * Will slightly overestimate the number of pages needed. This is OK | |
209 | * as it only leads to a small amount of wasted memory for the lifetime of | |
210 | * the I/O. | |
211 | */ | |
212 | static int nvme_npages(unsigned size, struct nvme_dev *dev) | |
213 | { | |
5fd4ce1b CH |
214 | unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size, |
215 | dev->ctrl.page_size); | |
ac3dd5bd JA |
216 | return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); |
217 | } | |
218 | ||
f4800d6d CH |
219 | static unsigned int nvme_iod_alloc_size(struct nvme_dev *dev, |
220 | unsigned int size, unsigned int nseg) | |
ac3dd5bd | 221 | { |
f4800d6d CH |
222 | return sizeof(__le64 *) * nvme_npages(size, dev) + |
223 | sizeof(struct scatterlist) * nseg; | |
224 | } | |
ac3dd5bd | 225 | |
f4800d6d CH |
226 | static unsigned int nvme_cmd_size(struct nvme_dev *dev) |
227 | { | |
228 | return sizeof(struct nvme_iod) + | |
229 | nvme_iod_alloc_size(dev, NVME_INT_BYTES(dev), NVME_INT_PAGES); | |
ac3dd5bd JA |
230 | } |
231 | ||
a4aea562 MB |
232 | static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, |
233 | unsigned int hctx_idx) | |
e85248e5 | 234 | { |
a4aea562 MB |
235 | struct nvme_dev *dev = data; |
236 | struct nvme_queue *nvmeq = dev->queues[0]; | |
237 | ||
42483228 KB |
238 | WARN_ON(hctx_idx != 0); |
239 | WARN_ON(dev->admin_tagset.tags[0] != hctx->tags); | |
240 | WARN_ON(nvmeq->tags); | |
241 | ||
a4aea562 | 242 | hctx->driver_data = nvmeq; |
42483228 | 243 | nvmeq->tags = &dev->admin_tagset.tags[0]; |
a4aea562 | 244 | return 0; |
e85248e5 MW |
245 | } |
246 | ||
4af0e21c KB |
247 | static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx) |
248 | { | |
249 | struct nvme_queue *nvmeq = hctx->driver_data; | |
250 | ||
251 | nvmeq->tags = NULL; | |
252 | } | |
253 | ||
a4aea562 MB |
254 | static int nvme_admin_init_request(void *data, struct request *req, |
255 | unsigned int hctx_idx, unsigned int rq_idx, | |
256 | unsigned int numa_node) | |
22404274 | 257 | { |
a4aea562 | 258 | struct nvme_dev *dev = data; |
f4800d6d | 259 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
a4aea562 MB |
260 | struct nvme_queue *nvmeq = dev->queues[0]; |
261 | ||
262 | BUG_ON(!nvmeq); | |
f4800d6d | 263 | iod->nvmeq = nvmeq; |
a4aea562 | 264 | return 0; |
22404274 KB |
265 | } |
266 | ||
a4aea562 MB |
267 | static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, |
268 | unsigned int hctx_idx) | |
b60503ba | 269 | { |
a4aea562 | 270 | struct nvme_dev *dev = data; |
42483228 | 271 | struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1]; |
a4aea562 | 272 | |
42483228 KB |
273 | if (!nvmeq->tags) |
274 | nvmeq->tags = &dev->tagset.tags[hctx_idx]; | |
b60503ba | 275 | |
42483228 | 276 | WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags); |
a4aea562 MB |
277 | hctx->driver_data = nvmeq; |
278 | return 0; | |
b60503ba MW |
279 | } |
280 | ||
a4aea562 MB |
281 | static int nvme_init_request(void *data, struct request *req, |
282 | unsigned int hctx_idx, unsigned int rq_idx, | |
283 | unsigned int numa_node) | |
b60503ba | 284 | { |
a4aea562 | 285 | struct nvme_dev *dev = data; |
f4800d6d | 286 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
a4aea562 MB |
287 | struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1]; |
288 | ||
289 | BUG_ON(!nvmeq); | |
f4800d6d | 290 | iod->nvmeq = nvmeq; |
a4aea562 MB |
291 | return 0; |
292 | } | |
293 | ||
adf68f21 CH |
294 | static void nvme_complete_async_event(struct nvme_dev *dev, |
295 | struct nvme_completion *cqe) | |
3c0cf138 | 296 | { |
adf68f21 CH |
297 | u16 status = le16_to_cpu(cqe->status) >> 1; |
298 | u32 result = le32_to_cpu(cqe->result); | |
a4aea562 MB |
299 | |
300 | if (status == NVME_SC_SUCCESS || status == NVME_SC_ABORT_REQ) | |
adf68f21 | 301 | ++dev->ctrl.event_limit; |
a5768aa8 KB |
302 | if (status != NVME_SC_SUCCESS) |
303 | return; | |
304 | ||
305 | switch (result & 0xff07) { | |
306 | case NVME_AER_NOTICE_NS_CHANGED: | |
adf68f21 CH |
307 | dev_info(dev->dev, "rescanning\n"); |
308 | queue_work(nvme_workq, &dev->scan_work); | |
a5768aa8 | 309 | default: |
adf68f21 | 310 | dev_warn(dev->dev, "async event result %08x\n", result); |
a5768aa8 | 311 | } |
b60503ba MW |
312 | } |
313 | ||
b60503ba | 314 | /** |
adf68f21 | 315 | * __nvme_submit_cmd() - Copy a command into a queue and ring the doorbell |
b60503ba MW |
316 | * @nvmeq: The queue to use |
317 | * @cmd: The command to send | |
318 | * | |
319 | * Safe to use from interrupt context | |
320 | */ | |
e3f879bf SB |
321 | static void __nvme_submit_cmd(struct nvme_queue *nvmeq, |
322 | struct nvme_command *cmd) | |
b60503ba | 323 | { |
a4aea562 MB |
324 | u16 tail = nvmeq->sq_tail; |
325 | ||
8ffaadf7 JD |
326 | if (nvmeq->sq_cmds_io) |
327 | memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd)); | |
328 | else | |
329 | memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd)); | |
330 | ||
b60503ba MW |
331 | if (++tail == nvmeq->q_depth) |
332 | tail = 0; | |
7547881d | 333 | writel(tail, nvmeq->q_db); |
b60503ba | 334 | nvmeq->sq_tail = tail; |
b60503ba MW |
335 | } |
336 | ||
f4800d6d | 337 | static __le64 **iod_list(struct request *req) |
b60503ba | 338 | { |
f4800d6d CH |
339 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
340 | return (__le64 **)(iod->sg + req->nr_phys_segments); | |
b60503ba MW |
341 | } |
342 | ||
f4800d6d | 343 | static int nvme_init_iod(struct request *rq, struct nvme_dev *dev) |
ac3dd5bd | 344 | { |
f4800d6d CH |
345 | struct nvme_iod *iod = blk_mq_rq_to_pdu(rq); |
346 | int nseg = rq->nr_phys_segments; | |
347 | unsigned size; | |
ac3dd5bd | 348 | |
f4800d6d CH |
349 | if (rq->cmd_flags & REQ_DISCARD) |
350 | size = sizeof(struct nvme_dsm_range); | |
351 | else | |
352 | size = blk_rq_bytes(rq); | |
ac3dd5bd | 353 | |
f4800d6d CH |
354 | if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) { |
355 | iod->sg = kmalloc(nvme_iod_alloc_size(dev, size, nseg), GFP_ATOMIC); | |
356 | if (!iod->sg) | |
357 | return BLK_MQ_RQ_QUEUE_BUSY; | |
358 | } else { | |
359 | iod->sg = iod->inline_sg; | |
ac3dd5bd JA |
360 | } |
361 | ||
f4800d6d CH |
362 | iod->aborted = 0; |
363 | iod->npages = -1; | |
364 | iod->nents = 0; | |
365 | iod->length = size; | |
366 | return 0; | |
ac3dd5bd JA |
367 | } |
368 | ||
f4800d6d | 369 | static void nvme_free_iod(struct nvme_dev *dev, struct request *req) |
b60503ba | 370 | { |
f4800d6d | 371 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
5fd4ce1b | 372 | const int last_prp = dev->ctrl.page_size / 8 - 1; |
eca18b23 | 373 | int i; |
f4800d6d | 374 | __le64 **list = iod_list(req); |
eca18b23 MW |
375 | dma_addr_t prp_dma = iod->first_dma; |
376 | ||
377 | if (iod->npages == 0) | |
378 | dma_pool_free(dev->prp_small_pool, list[0], prp_dma); | |
379 | for (i = 0; i < iod->npages; i++) { | |
380 | __le64 *prp_list = list[i]; | |
381 | dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]); | |
382 | dma_pool_free(dev->prp_page_pool, prp_list, prp_dma); | |
383 | prp_dma = next_prp_dma; | |
384 | } | |
ac3dd5bd | 385 | |
f4800d6d CH |
386 | if (iod->sg != iod->inline_sg) |
387 | kfree(iod->sg); | |
b60503ba MW |
388 | } |
389 | ||
52b68d7e | 390 | #ifdef CONFIG_BLK_DEV_INTEGRITY |
e1e5e564 KB |
391 | static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi) |
392 | { | |
393 | if (be32_to_cpu(pi->ref_tag) == v) | |
394 | pi->ref_tag = cpu_to_be32(p); | |
395 | } | |
396 | ||
397 | static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi) | |
398 | { | |
399 | if (be32_to_cpu(pi->ref_tag) == p) | |
400 | pi->ref_tag = cpu_to_be32(v); | |
401 | } | |
402 | ||
403 | /** | |
404 | * nvme_dif_remap - remaps ref tags to bip seed and physical lba | |
405 | * | |
406 | * The virtual start sector is the one that was originally submitted by the | |
407 | * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical | |
408 | * start sector may be different. Remap protection information to match the | |
409 | * physical LBA on writes, and back to the original seed on reads. | |
410 | * | |
411 | * Type 0 and 3 do not have a ref tag, so no remapping required. | |
412 | */ | |
413 | static void nvme_dif_remap(struct request *req, | |
414 | void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi)) | |
415 | { | |
416 | struct nvme_ns *ns = req->rq_disk->private_data; | |
417 | struct bio_integrity_payload *bip; | |
418 | struct t10_pi_tuple *pi; | |
419 | void *p, *pmap; | |
420 | u32 i, nlb, ts, phys, virt; | |
421 | ||
422 | if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3) | |
423 | return; | |
424 | ||
425 | bip = bio_integrity(req->bio); | |
426 | if (!bip) | |
427 | return; | |
428 | ||
429 | pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset; | |
e1e5e564 KB |
430 | |
431 | p = pmap; | |
432 | virt = bip_get_seed(bip); | |
433 | phys = nvme_block_nr(ns, blk_rq_pos(req)); | |
434 | nlb = (blk_rq_bytes(req) >> ns->lba_shift); | |
ac6fc48c | 435 | ts = ns->disk->queue->integrity.tuple_size; |
e1e5e564 KB |
436 | |
437 | for (i = 0; i < nlb; i++, virt++, phys++) { | |
438 | pi = (struct t10_pi_tuple *)p; | |
439 | dif_swap(phys, virt, pi); | |
440 | p += ts; | |
441 | } | |
442 | kunmap_atomic(pmap); | |
443 | } | |
52b68d7e KB |
444 | #else /* CONFIG_BLK_DEV_INTEGRITY */ |
445 | static void nvme_dif_remap(struct request *req, | |
446 | void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi)) | |
447 | { | |
448 | } | |
449 | static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi) | |
450 | { | |
451 | } | |
452 | static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi) | |
453 | { | |
454 | } | |
52b68d7e KB |
455 | #endif |
456 | ||
f4800d6d | 457 | static bool nvme_setup_prps(struct nvme_dev *dev, struct request *req, |
69d2b571 | 458 | int total_len) |
ff22b54f | 459 | { |
f4800d6d | 460 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
99802a7a | 461 | struct dma_pool *pool; |
eca18b23 MW |
462 | int length = total_len; |
463 | struct scatterlist *sg = iod->sg; | |
ff22b54f MW |
464 | int dma_len = sg_dma_len(sg); |
465 | u64 dma_addr = sg_dma_address(sg); | |
5fd4ce1b | 466 | u32 page_size = dev->ctrl.page_size; |
f137e0f1 | 467 | int offset = dma_addr & (page_size - 1); |
e025344c | 468 | __le64 *prp_list; |
f4800d6d | 469 | __le64 **list = iod_list(req); |
e025344c | 470 | dma_addr_t prp_dma; |
eca18b23 | 471 | int nprps, i; |
ff22b54f | 472 | |
1d090624 | 473 | length -= (page_size - offset); |
ff22b54f | 474 | if (length <= 0) |
69d2b571 | 475 | return true; |
ff22b54f | 476 | |
1d090624 | 477 | dma_len -= (page_size - offset); |
ff22b54f | 478 | if (dma_len) { |
1d090624 | 479 | dma_addr += (page_size - offset); |
ff22b54f MW |
480 | } else { |
481 | sg = sg_next(sg); | |
482 | dma_addr = sg_dma_address(sg); | |
483 | dma_len = sg_dma_len(sg); | |
484 | } | |
485 | ||
1d090624 | 486 | if (length <= page_size) { |
edd10d33 | 487 | iod->first_dma = dma_addr; |
69d2b571 | 488 | return true; |
e025344c SMM |
489 | } |
490 | ||
1d090624 | 491 | nprps = DIV_ROUND_UP(length, page_size); |
99802a7a MW |
492 | if (nprps <= (256 / 8)) { |
493 | pool = dev->prp_small_pool; | |
eca18b23 | 494 | iod->npages = 0; |
99802a7a MW |
495 | } else { |
496 | pool = dev->prp_page_pool; | |
eca18b23 | 497 | iod->npages = 1; |
99802a7a MW |
498 | } |
499 | ||
69d2b571 | 500 | prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); |
b77954cb | 501 | if (!prp_list) { |
edd10d33 | 502 | iod->first_dma = dma_addr; |
eca18b23 | 503 | iod->npages = -1; |
69d2b571 | 504 | return false; |
b77954cb | 505 | } |
eca18b23 MW |
506 | list[0] = prp_list; |
507 | iod->first_dma = prp_dma; | |
e025344c SMM |
508 | i = 0; |
509 | for (;;) { | |
1d090624 | 510 | if (i == page_size >> 3) { |
e025344c | 511 | __le64 *old_prp_list = prp_list; |
69d2b571 | 512 | prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); |
eca18b23 | 513 | if (!prp_list) |
69d2b571 | 514 | return false; |
eca18b23 | 515 | list[iod->npages++] = prp_list; |
7523d834 MW |
516 | prp_list[0] = old_prp_list[i - 1]; |
517 | old_prp_list[i - 1] = cpu_to_le64(prp_dma); | |
518 | i = 1; | |
e025344c SMM |
519 | } |
520 | prp_list[i++] = cpu_to_le64(dma_addr); | |
1d090624 KB |
521 | dma_len -= page_size; |
522 | dma_addr += page_size; | |
523 | length -= page_size; | |
e025344c SMM |
524 | if (length <= 0) |
525 | break; | |
526 | if (dma_len > 0) | |
527 | continue; | |
528 | BUG_ON(dma_len < 0); | |
529 | sg = sg_next(sg); | |
530 | dma_addr = sg_dma_address(sg); | |
531 | dma_len = sg_dma_len(sg); | |
ff22b54f MW |
532 | } |
533 | ||
69d2b571 | 534 | return true; |
ff22b54f MW |
535 | } |
536 | ||
f4800d6d | 537 | static int nvme_map_data(struct nvme_dev *dev, struct request *req, |
ba1ca37e | 538 | struct nvme_command *cmnd) |
d29ec824 | 539 | { |
f4800d6d | 540 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
ba1ca37e CH |
541 | struct request_queue *q = req->q; |
542 | enum dma_data_direction dma_dir = rq_data_dir(req) ? | |
543 | DMA_TO_DEVICE : DMA_FROM_DEVICE; | |
544 | int ret = BLK_MQ_RQ_QUEUE_ERROR; | |
545 | ||
546 | sg_init_table(iod->sg, req->nr_phys_segments); | |
547 | iod->nents = blk_rq_map_sg(q, req, iod->sg); | |
548 | if (!iod->nents) | |
549 | goto out; | |
550 | ||
551 | ret = BLK_MQ_RQ_QUEUE_BUSY; | |
552 | if (!dma_map_sg(dev->dev, iod->sg, iod->nents, dma_dir)) | |
553 | goto out; | |
554 | ||
f4800d6d | 555 | if (!nvme_setup_prps(dev, req, blk_rq_bytes(req))) |
ba1ca37e CH |
556 | goto out_unmap; |
557 | ||
558 | ret = BLK_MQ_RQ_QUEUE_ERROR; | |
559 | if (blk_integrity_rq(req)) { | |
560 | if (blk_rq_count_integrity_sg(q, req->bio) != 1) | |
561 | goto out_unmap; | |
562 | ||
bf684057 CH |
563 | sg_init_table(&iod->meta_sg, 1); |
564 | if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1) | |
ba1ca37e | 565 | goto out_unmap; |
d29ec824 | 566 | |
ba1ca37e CH |
567 | if (rq_data_dir(req)) |
568 | nvme_dif_remap(req, nvme_dif_prep); | |
569 | ||
bf684057 | 570 | if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir)) |
ba1ca37e | 571 | goto out_unmap; |
d29ec824 CH |
572 | } |
573 | ||
ba1ca37e CH |
574 | cmnd->rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg)); |
575 | cmnd->rw.prp2 = cpu_to_le64(iod->first_dma); | |
576 | if (blk_integrity_rq(req)) | |
bf684057 | 577 | cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg)); |
ba1ca37e CH |
578 | return BLK_MQ_RQ_QUEUE_OK; |
579 | ||
580 | out_unmap: | |
581 | dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); | |
582 | out: | |
583 | return ret; | |
d29ec824 CH |
584 | } |
585 | ||
f4800d6d | 586 | static void nvme_unmap_data(struct nvme_dev *dev, struct request *req) |
d4f6c3ab | 587 | { |
f4800d6d | 588 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
d4f6c3ab CH |
589 | enum dma_data_direction dma_dir = rq_data_dir(req) ? |
590 | DMA_TO_DEVICE : DMA_FROM_DEVICE; | |
591 | ||
592 | if (iod->nents) { | |
593 | dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); | |
594 | if (blk_integrity_rq(req)) { | |
595 | if (!rq_data_dir(req)) | |
596 | nvme_dif_remap(req, nvme_dif_complete); | |
bf684057 | 597 | dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir); |
d4f6c3ab CH |
598 | } |
599 | } | |
600 | ||
f4800d6d | 601 | nvme_free_iod(dev, req); |
d4f6c3ab CH |
602 | } |
603 | ||
a4aea562 MB |
604 | /* |
605 | * We reuse the small pool to allocate the 16-byte range here as it is not | |
606 | * worth having a special pool for these or additional cases to handle freeing | |
607 | * the iod. | |
608 | */ | |
ba1ca37e | 609 | static int nvme_setup_discard(struct nvme_queue *nvmeq, struct nvme_ns *ns, |
f4800d6d | 610 | struct request *req, struct nvme_command *cmnd) |
0e5e4f0e | 611 | { |
f4800d6d | 612 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
ba1ca37e CH |
613 | struct nvme_dsm_range *range; |
614 | ||
615 | range = dma_pool_alloc(nvmeq->dev->prp_small_pool, GFP_ATOMIC, | |
616 | &iod->first_dma); | |
617 | if (!range) | |
618 | return BLK_MQ_RQ_QUEUE_BUSY; | |
f4800d6d | 619 | iod_list(req)[0] = (__le64 *)range; |
ba1ca37e | 620 | iod->npages = 0; |
0e5e4f0e | 621 | |
0e5e4f0e | 622 | range->cattr = cpu_to_le32(0); |
a4aea562 MB |
623 | range->nlb = cpu_to_le32(blk_rq_bytes(req) >> ns->lba_shift); |
624 | range->slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req))); | |
0e5e4f0e | 625 | |
ba1ca37e CH |
626 | memset(cmnd, 0, sizeof(*cmnd)); |
627 | cmnd->dsm.opcode = nvme_cmd_dsm; | |
628 | cmnd->dsm.nsid = cpu_to_le32(ns->ns_id); | |
629 | cmnd->dsm.prp1 = cpu_to_le64(iod->first_dma); | |
630 | cmnd->dsm.nr = 0; | |
631 | cmnd->dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD); | |
632 | return BLK_MQ_RQ_QUEUE_OK; | |
0e5e4f0e KB |
633 | } |
634 | ||
d29ec824 CH |
635 | /* |
636 | * NOTE: ns is NULL when called on the admin queue. | |
637 | */ | |
a4aea562 MB |
638 | static int nvme_queue_rq(struct blk_mq_hw_ctx *hctx, |
639 | const struct blk_mq_queue_data *bd) | |
edd10d33 | 640 | { |
a4aea562 MB |
641 | struct nvme_ns *ns = hctx->queue->queuedata; |
642 | struct nvme_queue *nvmeq = hctx->driver_data; | |
d29ec824 | 643 | struct nvme_dev *dev = nvmeq->dev; |
a4aea562 | 644 | struct request *req = bd->rq; |
ba1ca37e CH |
645 | struct nvme_command cmnd; |
646 | int ret = BLK_MQ_RQ_QUEUE_OK; | |
edd10d33 | 647 | |
e1e5e564 KB |
648 | /* |
649 | * If formated with metadata, require the block layer provide a buffer | |
650 | * unless this namespace is formated such that the metadata can be | |
651 | * stripped/generated by the controller with PRACT=1. | |
652 | */ | |
d29ec824 | 653 | if (ns && ns->ms && !blk_integrity_rq(req)) { |
71feb364 KB |
654 | if (!(ns->pi_type && ns->ms == 8) && |
655 | req->cmd_type != REQ_TYPE_DRV_PRIV) { | |
eee417b0 | 656 | blk_mq_end_request(req, -EFAULT); |
e1e5e564 KB |
657 | return BLK_MQ_RQ_QUEUE_OK; |
658 | } | |
659 | } | |
660 | ||
f4800d6d CH |
661 | ret = nvme_init_iod(req, dev); |
662 | if (ret) | |
663 | return ret; | |
a4aea562 | 664 | |
a4aea562 | 665 | if (req->cmd_flags & REQ_DISCARD) { |
f4800d6d | 666 | ret = nvme_setup_discard(nvmeq, ns, req, &cmnd); |
ba1ca37e CH |
667 | } else { |
668 | if (req->cmd_type == REQ_TYPE_DRV_PRIV) | |
669 | memcpy(&cmnd, req->cmd, sizeof(cmnd)); | |
670 | else if (req->cmd_flags & REQ_FLUSH) | |
671 | nvme_setup_flush(ns, &cmnd); | |
672 | else | |
673 | nvme_setup_rw(ns, req, &cmnd); | |
a4aea562 | 674 | |
ba1ca37e | 675 | if (req->nr_phys_segments) |
f4800d6d | 676 | ret = nvme_map_data(dev, req, &cmnd); |
edd10d33 | 677 | } |
1974b1ae | 678 | |
ba1ca37e CH |
679 | if (ret) |
680 | goto out; | |
681 | ||
682 | cmnd.common.command_id = req->tag; | |
aae239e1 | 683 | blk_mq_start_request(req); |
a4aea562 | 684 | |
ba1ca37e CH |
685 | spin_lock_irq(&nvmeq->q_lock); |
686 | __nvme_submit_cmd(nvmeq, &cmnd); | |
a4aea562 MB |
687 | nvme_process_cq(nvmeq); |
688 | spin_unlock_irq(&nvmeq->q_lock); | |
689 | return BLK_MQ_RQ_QUEUE_OK; | |
ba1ca37e | 690 | out: |
f4800d6d | 691 | nvme_free_iod(dev, req); |
ba1ca37e | 692 | return ret; |
b60503ba MW |
693 | } |
694 | ||
eee417b0 CH |
695 | static void nvme_complete_rq(struct request *req) |
696 | { | |
f4800d6d CH |
697 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
698 | struct nvme_dev *dev = iod->nvmeq->dev; | |
eee417b0 CH |
699 | int error = 0; |
700 | ||
f4800d6d | 701 | nvme_unmap_data(dev, req); |
eee417b0 CH |
702 | |
703 | if (unlikely(req->errors)) { | |
704 | if (nvme_req_needs_retry(req, req->errors)) { | |
705 | nvme_requeue_req(req); | |
706 | return; | |
707 | } | |
708 | ||
709 | if (req->cmd_type == REQ_TYPE_DRV_PRIV) | |
710 | error = req->errors; | |
711 | else | |
712 | error = nvme_error_status(req->errors); | |
713 | } | |
714 | ||
f4800d6d | 715 | if (unlikely(iod->aborted)) { |
eee417b0 CH |
716 | dev_warn(dev->dev, |
717 | "completing aborted command with status: %04x\n", | |
718 | req->errors); | |
719 | } | |
720 | ||
721 | blk_mq_end_request(req, error); | |
722 | } | |
723 | ||
a0fa9647 | 724 | static void __nvme_process_cq(struct nvme_queue *nvmeq, unsigned int *tag) |
b60503ba | 725 | { |
82123460 | 726 | u16 head, phase; |
b60503ba | 727 | |
b60503ba | 728 | head = nvmeq->cq_head; |
82123460 | 729 | phase = nvmeq->cq_phase; |
b60503ba MW |
730 | |
731 | for (;;) { | |
b60503ba | 732 | struct nvme_completion cqe = nvmeq->cqes[head]; |
adf68f21 | 733 | u16 status = le16_to_cpu(cqe.status); |
eee417b0 | 734 | struct request *req; |
adf68f21 CH |
735 | |
736 | if ((status & 1) != phase) | |
b60503ba MW |
737 | break; |
738 | nvmeq->sq_head = le16_to_cpu(cqe.sq_head); | |
739 | if (++head == nvmeq->q_depth) { | |
740 | head = 0; | |
82123460 | 741 | phase = !phase; |
b60503ba | 742 | } |
adf68f21 | 743 | |
a0fa9647 JA |
744 | if (tag && *tag == cqe.command_id) |
745 | *tag = -1; | |
adf68f21 | 746 | |
aae239e1 CH |
747 | if (unlikely(cqe.command_id >= nvmeq->q_depth)) { |
748 | dev_warn(nvmeq->q_dmadev, | |
749 | "invalid id %d completed on queue %d\n", | |
750 | cqe.command_id, le16_to_cpu(cqe.sq_id)); | |
751 | continue; | |
752 | } | |
753 | ||
adf68f21 CH |
754 | /* |
755 | * AEN requests are special as they don't time out and can | |
756 | * survive any kind of queue freeze and often don't respond to | |
757 | * aborts. We don't even bother to allocate a struct request | |
758 | * for them but rather special case them here. | |
759 | */ | |
760 | if (unlikely(nvmeq->qid == 0 && | |
761 | cqe.command_id >= NVME_AQ_BLKMQ_DEPTH)) { | |
762 | nvme_complete_async_event(nvmeq->dev, &cqe); | |
763 | continue; | |
764 | } | |
765 | ||
eee417b0 CH |
766 | req = blk_mq_tag_to_rq(*nvmeq->tags, cqe.command_id); |
767 | if (req->cmd_type == REQ_TYPE_DRV_PRIV) { | |
768 | u32 result = le32_to_cpu(cqe.result); | |
769 | req->special = (void *)(uintptr_t)result; | |
770 | } | |
771 | blk_mq_complete_request(req, status >> 1); | |
772 | ||
b60503ba MW |
773 | } |
774 | ||
775 | /* If the controller ignores the cq head doorbell and continuously | |
776 | * writes to the queue, it is theoretically possible to wrap around | |
777 | * the queue twice and mistakenly return IRQ_NONE. Linux only | |
778 | * requires that 0.1% of your interrupts are handled, so this isn't | |
779 | * a big problem. | |
780 | */ | |
82123460 | 781 | if (head == nvmeq->cq_head && phase == nvmeq->cq_phase) |
a0fa9647 | 782 | return; |
b60503ba | 783 | |
604e8c8d KB |
784 | if (likely(nvmeq->cq_vector >= 0)) |
785 | writel(head, nvmeq->q_db + nvmeq->dev->db_stride); | |
b60503ba | 786 | nvmeq->cq_head = head; |
82123460 | 787 | nvmeq->cq_phase = phase; |
b60503ba | 788 | |
e9539f47 | 789 | nvmeq->cqe_seen = 1; |
a0fa9647 JA |
790 | } |
791 | ||
792 | static void nvme_process_cq(struct nvme_queue *nvmeq) | |
793 | { | |
794 | __nvme_process_cq(nvmeq, NULL); | |
b60503ba MW |
795 | } |
796 | ||
797 | static irqreturn_t nvme_irq(int irq, void *data) | |
58ffacb5 MW |
798 | { |
799 | irqreturn_t result; | |
800 | struct nvme_queue *nvmeq = data; | |
801 | spin_lock(&nvmeq->q_lock); | |
e9539f47 MW |
802 | nvme_process_cq(nvmeq); |
803 | result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE; | |
804 | nvmeq->cqe_seen = 0; | |
58ffacb5 MW |
805 | spin_unlock(&nvmeq->q_lock); |
806 | return result; | |
807 | } | |
808 | ||
809 | static irqreturn_t nvme_irq_check(int irq, void *data) | |
810 | { | |
811 | struct nvme_queue *nvmeq = data; | |
812 | struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head]; | |
813 | if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase) | |
814 | return IRQ_NONE; | |
815 | return IRQ_WAKE_THREAD; | |
816 | } | |
817 | ||
a0fa9647 JA |
818 | static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag) |
819 | { | |
820 | struct nvme_queue *nvmeq = hctx->driver_data; | |
821 | ||
822 | if ((le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) == | |
823 | nvmeq->cq_phase) { | |
824 | spin_lock_irq(&nvmeq->q_lock); | |
825 | __nvme_process_cq(nvmeq, &tag); | |
826 | spin_unlock_irq(&nvmeq->q_lock); | |
827 | ||
828 | if (tag == -1) | |
829 | return 1; | |
830 | } | |
831 | ||
832 | return 0; | |
833 | } | |
834 | ||
adf68f21 | 835 | static void nvme_submit_async_event(struct nvme_dev *dev) |
a4aea562 | 836 | { |
a4aea562 | 837 | struct nvme_command c; |
a4aea562 MB |
838 | |
839 | memset(&c, 0, sizeof(c)); | |
840 | c.common.opcode = nvme_admin_async_event; | |
adf68f21 | 841 | c.common.command_id = NVME_AQ_BLKMQ_DEPTH + --dev->ctrl.event_limit; |
a4aea562 | 842 | |
adf68f21 | 843 | __nvme_submit_cmd(dev->queues[0], &c); |
a4aea562 MB |
844 | } |
845 | ||
d8f32166 | 846 | static void async_cmd_info_endio(struct request *req, int error) |
4d115420 | 847 | { |
d8f32166 | 848 | struct async_cmd_info *cmdinfo = req->end_io_data; |
a4aea562 | 849 | |
d8f32166 CH |
850 | cmdinfo->status = req->errors; |
851 | queue_kthread_work(cmdinfo->worker, &cmdinfo->work); | |
852 | blk_mq_free_request(req); | |
4d115420 KB |
853 | } |
854 | ||
b60503ba MW |
855 | static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) |
856 | { | |
b60503ba MW |
857 | struct nvme_command c; |
858 | ||
859 | memset(&c, 0, sizeof(c)); | |
860 | c.delete_queue.opcode = opcode; | |
861 | c.delete_queue.qid = cpu_to_le16(id); | |
862 | ||
1c63dc66 | 863 | return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); |
b60503ba MW |
864 | } |
865 | ||
866 | static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, | |
867 | struct nvme_queue *nvmeq) | |
868 | { | |
b60503ba MW |
869 | struct nvme_command c; |
870 | int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED; | |
871 | ||
d29ec824 CH |
872 | /* |
873 | * Note: we (ab)use the fact the the prp fields survive if no data | |
874 | * is attached to the request. | |
875 | */ | |
b60503ba MW |
876 | memset(&c, 0, sizeof(c)); |
877 | c.create_cq.opcode = nvme_admin_create_cq; | |
878 | c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); | |
879 | c.create_cq.cqid = cpu_to_le16(qid); | |
880 | c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); | |
881 | c.create_cq.cq_flags = cpu_to_le16(flags); | |
882 | c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector); | |
883 | ||
1c63dc66 | 884 | return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); |
b60503ba MW |
885 | } |
886 | ||
887 | static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, | |
888 | struct nvme_queue *nvmeq) | |
889 | { | |
b60503ba MW |
890 | struct nvme_command c; |
891 | int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM; | |
892 | ||
d29ec824 CH |
893 | /* |
894 | * Note: we (ab)use the fact the the prp fields survive if no data | |
895 | * is attached to the request. | |
896 | */ | |
b60503ba MW |
897 | memset(&c, 0, sizeof(c)); |
898 | c.create_sq.opcode = nvme_admin_create_sq; | |
899 | c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); | |
900 | c.create_sq.sqid = cpu_to_le16(qid); | |
901 | c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); | |
902 | c.create_sq.sq_flags = cpu_to_le16(flags); | |
903 | c.create_sq.cqid = cpu_to_le16(qid); | |
904 | ||
1c63dc66 | 905 | return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); |
b60503ba MW |
906 | } |
907 | ||
908 | static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) | |
909 | { | |
910 | return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); | |
911 | } | |
912 | ||
913 | static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) | |
914 | { | |
915 | return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); | |
916 | } | |
917 | ||
e7a2a87d CH |
918 | static void abort_endio(struct request *req, int error) |
919 | { | |
f4800d6d CH |
920 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
921 | struct nvme_queue *nvmeq = iod->nvmeq; | |
e7a2a87d CH |
922 | u32 result = (u32)(uintptr_t)req->special; |
923 | u16 status = req->errors; | |
924 | ||
925 | dev_warn(nvmeq->q_dmadev, "Abort status:%x result:%x", status, result); | |
926 | atomic_inc(&nvmeq->dev->ctrl.abort_limit); | |
927 | ||
928 | blk_mq_free_request(req); | |
929 | } | |
930 | ||
31c7c7d2 | 931 | static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved) |
c30341dc | 932 | { |
f4800d6d CH |
933 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
934 | struct nvme_queue *nvmeq = iod->nvmeq; | |
c30341dc | 935 | struct nvme_dev *dev = nvmeq->dev; |
a4aea562 | 936 | struct request *abort_req; |
a4aea562 | 937 | struct nvme_command cmd; |
c30341dc | 938 | |
31c7c7d2 | 939 | /* |
fd634f41 CH |
940 | * Shutdown immediately if controller times out while starting. The |
941 | * reset work will see the pci device disabled when it gets the forced | |
942 | * cancellation error. All outstanding requests are completed on | |
943 | * shutdown, so we return BLK_EH_HANDLED. | |
944 | */ | |
945 | if (test_bit(NVME_CTRL_RESETTING, &dev->flags)) { | |
946 | dev_warn(dev->dev, | |
947 | "I/O %d QID %d timeout, disable controller\n", | |
948 | req->tag, nvmeq->qid); | |
949 | nvme_dev_shutdown(dev); | |
950 | req->errors = NVME_SC_CANCELLED; | |
951 | return BLK_EH_HANDLED; | |
952 | } | |
953 | ||
954 | /* | |
955 | * Shutdown the controller immediately and schedule a reset if the | |
956 | * command was already aborted once before and still hasn't been | |
957 | * returned to the driver, or if this is the admin queue. | |
31c7c7d2 | 958 | */ |
f4800d6d | 959 | if (!nvmeq->qid || iod->aborted) { |
e1569a16 KB |
960 | dev_warn(dev->dev, |
961 | "I/O %d QID %d timeout, reset controller\n", | |
962 | req->tag, nvmeq->qid); | |
963 | nvme_dev_shutdown(dev); | |
964 | queue_work(nvme_workq, &dev->reset_work); | |
965 | ||
966 | /* | |
967 | * Mark the request as handled, since the inline shutdown | |
968 | * forces all outstanding requests to complete. | |
969 | */ | |
970 | req->errors = NVME_SC_CANCELLED; | |
971 | return BLK_EH_HANDLED; | |
c30341dc KB |
972 | } |
973 | ||
f4800d6d | 974 | iod->aborted = 1; |
c30341dc | 975 | |
e7a2a87d | 976 | if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) { |
6bf25d16 | 977 | atomic_inc(&dev->ctrl.abort_limit); |
31c7c7d2 | 978 | return BLK_EH_RESET_TIMER; |
6bf25d16 | 979 | } |
c30341dc KB |
980 | |
981 | memset(&cmd, 0, sizeof(cmd)); | |
982 | cmd.abort.opcode = nvme_admin_abort_cmd; | |
a4aea562 | 983 | cmd.abort.cid = req->tag; |
c30341dc | 984 | cmd.abort.sqid = cpu_to_le16(nvmeq->qid); |
c30341dc | 985 | |
31c7c7d2 CH |
986 | dev_warn(nvmeq->q_dmadev, "I/O %d QID %d timeout, aborting\n", |
987 | req->tag, nvmeq->qid); | |
e7a2a87d CH |
988 | |
989 | abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd, | |
990 | BLK_MQ_REQ_NOWAIT); | |
991 | if (IS_ERR(abort_req)) { | |
992 | atomic_inc(&dev->ctrl.abort_limit); | |
993 | return BLK_EH_RESET_TIMER; | |
994 | } | |
995 | ||
996 | abort_req->timeout = ADMIN_TIMEOUT; | |
997 | abort_req->end_io_data = NULL; | |
998 | blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio); | |
31c7c7d2 CH |
999 | |
1000 | /* | |
1001 | * The aborted req will be completed on receiving the abort req. | |
1002 | * We enable the timer again. If hit twice, it'll cause a device reset, | |
1003 | * as the device then is in a faulty state. | |
1004 | */ | |
1005 | return BLK_EH_RESET_TIMER; | |
c30341dc KB |
1006 | } |
1007 | ||
42483228 | 1008 | static void nvme_cancel_queue_ios(struct request *req, void *data, bool reserved) |
a09115b2 | 1009 | { |
a4aea562 | 1010 | struct nvme_queue *nvmeq = data; |
aae239e1 | 1011 | int status; |
cef6a948 KB |
1012 | |
1013 | if (!blk_mq_request_started(req)) | |
1014 | return; | |
a09115b2 | 1015 | |
aae239e1 CH |
1016 | dev_warn(nvmeq->q_dmadev, |
1017 | "Cancelling I/O %d QID %d\n", req->tag, nvmeq->qid); | |
a4aea562 | 1018 | |
aae239e1 | 1019 | status = NVME_SC_CANCELLED; |
cef6a948 | 1020 | if (blk_queue_dying(req->q)) |
aae239e1 CH |
1021 | status |= NVME_SC_DNR; |
1022 | blk_mq_complete_request(req, status); | |
a09115b2 MW |
1023 | } |
1024 | ||
a4aea562 MB |
1025 | static void nvme_free_queue(struct nvme_queue *nvmeq) |
1026 | { | |
9e866774 MW |
1027 | dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth), |
1028 | (void *)nvmeq->cqes, nvmeq->cq_dma_addr); | |
8ffaadf7 JD |
1029 | if (nvmeq->sq_cmds) |
1030 | dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth), | |
9e866774 MW |
1031 | nvmeq->sq_cmds, nvmeq->sq_dma_addr); |
1032 | kfree(nvmeq); | |
1033 | } | |
1034 | ||
a1a5ef99 | 1035 | static void nvme_free_queues(struct nvme_dev *dev, int lowest) |
22404274 KB |
1036 | { |
1037 | int i; | |
1038 | ||
a1a5ef99 | 1039 | for (i = dev->queue_count - 1; i >= lowest; i--) { |
a4aea562 | 1040 | struct nvme_queue *nvmeq = dev->queues[i]; |
22404274 | 1041 | dev->queue_count--; |
a4aea562 | 1042 | dev->queues[i] = NULL; |
f435c282 | 1043 | nvme_free_queue(nvmeq); |
121c7ad4 | 1044 | } |
22404274 KB |
1045 | } |
1046 | ||
4d115420 KB |
1047 | /** |
1048 | * nvme_suspend_queue - put queue into suspended state | |
1049 | * @nvmeq - queue to suspend | |
4d115420 KB |
1050 | */ |
1051 | static int nvme_suspend_queue(struct nvme_queue *nvmeq) | |
b60503ba | 1052 | { |
2b25d981 | 1053 | int vector; |
b60503ba | 1054 | |
a09115b2 | 1055 | spin_lock_irq(&nvmeq->q_lock); |
2b25d981 KB |
1056 | if (nvmeq->cq_vector == -1) { |
1057 | spin_unlock_irq(&nvmeq->q_lock); | |
1058 | return 1; | |
1059 | } | |
1060 | vector = nvmeq->dev->entry[nvmeq->cq_vector].vector; | |
42f61420 | 1061 | nvmeq->dev->online_queues--; |
2b25d981 | 1062 | nvmeq->cq_vector = -1; |
a09115b2 MW |
1063 | spin_unlock_irq(&nvmeq->q_lock); |
1064 | ||
1c63dc66 CH |
1065 | if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q) |
1066 | blk_mq_freeze_queue_start(nvmeq->dev->ctrl.admin_q); | |
6df3dbc8 | 1067 | |
aba2080f MW |
1068 | irq_set_affinity_hint(vector, NULL); |
1069 | free_irq(vector, nvmeq); | |
b60503ba | 1070 | |
4d115420 KB |
1071 | return 0; |
1072 | } | |
b60503ba | 1073 | |
4d115420 KB |
1074 | static void nvme_clear_queue(struct nvme_queue *nvmeq) |
1075 | { | |
22404274 | 1076 | spin_lock_irq(&nvmeq->q_lock); |
42483228 KB |
1077 | if (nvmeq->tags && *nvmeq->tags) |
1078 | blk_mq_all_tag_busy_iter(*nvmeq->tags, nvme_cancel_queue_ios, nvmeq); | |
22404274 | 1079 | spin_unlock_irq(&nvmeq->q_lock); |
b60503ba MW |
1080 | } |
1081 | ||
4d115420 KB |
1082 | static void nvme_disable_queue(struct nvme_dev *dev, int qid) |
1083 | { | |
a4aea562 | 1084 | struct nvme_queue *nvmeq = dev->queues[qid]; |
4d115420 KB |
1085 | |
1086 | if (!nvmeq) | |
1087 | return; | |
1088 | if (nvme_suspend_queue(nvmeq)) | |
1089 | return; | |
1090 | ||
0e53d180 KB |
1091 | /* Don't tell the adapter to delete the admin queue. |
1092 | * Don't tell a removed adapter to delete IO queues. */ | |
7a67cbea | 1093 | if (qid && readl(dev->bar + NVME_REG_CSTS) != -1) { |
b60503ba MW |
1094 | adapter_delete_sq(dev, qid); |
1095 | adapter_delete_cq(dev, qid); | |
1096 | } | |
07836e65 KB |
1097 | |
1098 | spin_lock_irq(&nvmeq->q_lock); | |
1099 | nvme_process_cq(nvmeq); | |
1100 | spin_unlock_irq(&nvmeq->q_lock); | |
b60503ba MW |
1101 | } |
1102 | ||
8ffaadf7 JD |
1103 | static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues, |
1104 | int entry_size) | |
1105 | { | |
1106 | int q_depth = dev->q_depth; | |
5fd4ce1b CH |
1107 | unsigned q_size_aligned = roundup(q_depth * entry_size, |
1108 | dev->ctrl.page_size); | |
8ffaadf7 JD |
1109 | |
1110 | if (q_size_aligned * nr_io_queues > dev->cmb_size) { | |
c45f5c99 | 1111 | u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues); |
5fd4ce1b | 1112 | mem_per_q = round_down(mem_per_q, dev->ctrl.page_size); |
c45f5c99 | 1113 | q_depth = div_u64(mem_per_q, entry_size); |
8ffaadf7 JD |
1114 | |
1115 | /* | |
1116 | * Ensure the reduced q_depth is above some threshold where it | |
1117 | * would be better to map queues in system memory with the | |
1118 | * original depth | |
1119 | */ | |
1120 | if (q_depth < 64) | |
1121 | return -ENOMEM; | |
1122 | } | |
1123 | ||
1124 | return q_depth; | |
1125 | } | |
1126 | ||
1127 | static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq, | |
1128 | int qid, int depth) | |
1129 | { | |
1130 | if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz)) { | |
5fd4ce1b CH |
1131 | unsigned offset = (qid - 1) * roundup(SQ_SIZE(depth), |
1132 | dev->ctrl.page_size); | |
8ffaadf7 JD |
1133 | nvmeq->sq_dma_addr = dev->cmb_dma_addr + offset; |
1134 | nvmeq->sq_cmds_io = dev->cmb + offset; | |
1135 | } else { | |
1136 | nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth), | |
1137 | &nvmeq->sq_dma_addr, GFP_KERNEL); | |
1138 | if (!nvmeq->sq_cmds) | |
1139 | return -ENOMEM; | |
1140 | } | |
1141 | ||
1142 | return 0; | |
1143 | } | |
1144 | ||
b60503ba | 1145 | static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid, |
2b25d981 | 1146 | int depth) |
b60503ba | 1147 | { |
a4aea562 | 1148 | struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq), GFP_KERNEL); |
b60503ba MW |
1149 | if (!nvmeq) |
1150 | return NULL; | |
1151 | ||
e75ec752 | 1152 | nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth), |
4d51abf9 | 1153 | &nvmeq->cq_dma_addr, GFP_KERNEL); |
b60503ba MW |
1154 | if (!nvmeq->cqes) |
1155 | goto free_nvmeq; | |
b60503ba | 1156 | |
8ffaadf7 | 1157 | if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth)) |
b60503ba MW |
1158 | goto free_cqdma; |
1159 | ||
e75ec752 | 1160 | nvmeq->q_dmadev = dev->dev; |
091b6092 | 1161 | nvmeq->dev = dev; |
3193f07b | 1162 | snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d", |
1c63dc66 | 1163 | dev->ctrl.instance, qid); |
b60503ba MW |
1164 | spin_lock_init(&nvmeq->q_lock); |
1165 | nvmeq->cq_head = 0; | |
82123460 | 1166 | nvmeq->cq_phase = 1; |
b80d5ccc | 1167 | nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; |
b60503ba | 1168 | nvmeq->q_depth = depth; |
c30341dc | 1169 | nvmeq->qid = qid; |
758dd7fd | 1170 | nvmeq->cq_vector = -1; |
a4aea562 | 1171 | dev->queues[qid] = nvmeq; |
b60503ba | 1172 | |
36a7e993 JD |
1173 | /* make sure queue descriptor is set before queue count, for kthread */ |
1174 | mb(); | |
1175 | dev->queue_count++; | |
1176 | ||
b60503ba MW |
1177 | return nvmeq; |
1178 | ||
1179 | free_cqdma: | |
e75ec752 | 1180 | dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes, |
b60503ba MW |
1181 | nvmeq->cq_dma_addr); |
1182 | free_nvmeq: | |
1183 | kfree(nvmeq); | |
1184 | return NULL; | |
1185 | } | |
1186 | ||
3001082c MW |
1187 | static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq, |
1188 | const char *name) | |
1189 | { | |
58ffacb5 MW |
1190 | if (use_threaded_interrupts) |
1191 | return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector, | |
481e5bad | 1192 | nvme_irq_check, nvme_irq, IRQF_SHARED, |
58ffacb5 | 1193 | name, nvmeq); |
3001082c | 1194 | return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq, |
481e5bad | 1195 | IRQF_SHARED, name, nvmeq); |
3001082c MW |
1196 | } |
1197 | ||
22404274 | 1198 | static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) |
b60503ba | 1199 | { |
22404274 | 1200 | struct nvme_dev *dev = nvmeq->dev; |
b60503ba | 1201 | |
7be50e93 | 1202 | spin_lock_irq(&nvmeq->q_lock); |
22404274 KB |
1203 | nvmeq->sq_tail = 0; |
1204 | nvmeq->cq_head = 0; | |
1205 | nvmeq->cq_phase = 1; | |
b80d5ccc | 1206 | nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; |
22404274 | 1207 | memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth)); |
42f61420 | 1208 | dev->online_queues++; |
7be50e93 | 1209 | spin_unlock_irq(&nvmeq->q_lock); |
22404274 KB |
1210 | } |
1211 | ||
1212 | static int nvme_create_queue(struct nvme_queue *nvmeq, int qid) | |
1213 | { | |
1214 | struct nvme_dev *dev = nvmeq->dev; | |
1215 | int result; | |
3f85d50b | 1216 | |
2b25d981 | 1217 | nvmeq->cq_vector = qid - 1; |
b60503ba MW |
1218 | result = adapter_alloc_cq(dev, qid, nvmeq); |
1219 | if (result < 0) | |
22404274 | 1220 | return result; |
b60503ba MW |
1221 | |
1222 | result = adapter_alloc_sq(dev, qid, nvmeq); | |
1223 | if (result < 0) | |
1224 | goto release_cq; | |
1225 | ||
3193f07b | 1226 | result = queue_request_irq(dev, nvmeq, nvmeq->irqname); |
b60503ba MW |
1227 | if (result < 0) |
1228 | goto release_sq; | |
1229 | ||
22404274 | 1230 | nvme_init_queue(nvmeq, qid); |
22404274 | 1231 | return result; |
b60503ba MW |
1232 | |
1233 | release_sq: | |
1234 | adapter_delete_sq(dev, qid); | |
1235 | release_cq: | |
1236 | adapter_delete_cq(dev, qid); | |
22404274 | 1237 | return result; |
b60503ba MW |
1238 | } |
1239 | ||
a4aea562 | 1240 | static struct blk_mq_ops nvme_mq_admin_ops = { |
d29ec824 | 1241 | .queue_rq = nvme_queue_rq, |
eee417b0 | 1242 | .complete = nvme_complete_rq, |
a4aea562 MB |
1243 | .map_queue = blk_mq_map_queue, |
1244 | .init_hctx = nvme_admin_init_hctx, | |
4af0e21c | 1245 | .exit_hctx = nvme_admin_exit_hctx, |
a4aea562 MB |
1246 | .init_request = nvme_admin_init_request, |
1247 | .timeout = nvme_timeout, | |
1248 | }; | |
1249 | ||
1250 | static struct blk_mq_ops nvme_mq_ops = { | |
1251 | .queue_rq = nvme_queue_rq, | |
eee417b0 | 1252 | .complete = nvme_complete_rq, |
a4aea562 MB |
1253 | .map_queue = blk_mq_map_queue, |
1254 | .init_hctx = nvme_init_hctx, | |
1255 | .init_request = nvme_init_request, | |
1256 | .timeout = nvme_timeout, | |
a0fa9647 | 1257 | .poll = nvme_poll, |
a4aea562 MB |
1258 | }; |
1259 | ||
ea191d2f KB |
1260 | static void nvme_dev_remove_admin(struct nvme_dev *dev) |
1261 | { | |
1c63dc66 CH |
1262 | if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) { |
1263 | blk_cleanup_queue(dev->ctrl.admin_q); | |
ea191d2f KB |
1264 | blk_mq_free_tag_set(&dev->admin_tagset); |
1265 | } | |
1266 | } | |
1267 | ||
a4aea562 MB |
1268 | static int nvme_alloc_admin_tags(struct nvme_dev *dev) |
1269 | { | |
1c63dc66 | 1270 | if (!dev->ctrl.admin_q) { |
a4aea562 MB |
1271 | dev->admin_tagset.ops = &nvme_mq_admin_ops; |
1272 | dev->admin_tagset.nr_hw_queues = 1; | |
adf68f21 | 1273 | dev->admin_tagset.queue_depth = NVME_AQ_BLKMQ_DEPTH; |
a4aea562 | 1274 | dev->admin_tagset.timeout = ADMIN_TIMEOUT; |
e75ec752 | 1275 | dev->admin_tagset.numa_node = dev_to_node(dev->dev); |
ac3dd5bd | 1276 | dev->admin_tagset.cmd_size = nvme_cmd_size(dev); |
a4aea562 MB |
1277 | dev->admin_tagset.driver_data = dev; |
1278 | ||
1279 | if (blk_mq_alloc_tag_set(&dev->admin_tagset)) | |
1280 | return -ENOMEM; | |
1281 | ||
1c63dc66 CH |
1282 | dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset); |
1283 | if (IS_ERR(dev->ctrl.admin_q)) { | |
a4aea562 MB |
1284 | blk_mq_free_tag_set(&dev->admin_tagset); |
1285 | return -ENOMEM; | |
1286 | } | |
1c63dc66 | 1287 | if (!blk_get_queue(dev->ctrl.admin_q)) { |
ea191d2f | 1288 | nvme_dev_remove_admin(dev); |
1c63dc66 | 1289 | dev->ctrl.admin_q = NULL; |
ea191d2f KB |
1290 | return -ENODEV; |
1291 | } | |
0fb59cbc | 1292 | } else |
1c63dc66 | 1293 | blk_mq_unfreeze_queue(dev->ctrl.admin_q); |
a4aea562 MB |
1294 | |
1295 | return 0; | |
1296 | } | |
1297 | ||
8d85fce7 | 1298 | static int nvme_configure_admin_queue(struct nvme_dev *dev) |
b60503ba | 1299 | { |
ba47e386 | 1300 | int result; |
b60503ba | 1301 | u32 aqa; |
7a67cbea | 1302 | u64 cap = lo_hi_readq(dev->bar + NVME_REG_CAP); |
b60503ba MW |
1303 | struct nvme_queue *nvmeq; |
1304 | ||
7a67cbea | 1305 | dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1) ? |
dfbac8c7 KB |
1306 | NVME_CAP_NSSRC(cap) : 0; |
1307 | ||
7a67cbea CH |
1308 | if (dev->subsystem && |
1309 | (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO)) | |
1310 | writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS); | |
dfbac8c7 | 1311 | |
5fd4ce1b | 1312 | result = nvme_disable_ctrl(&dev->ctrl, cap); |
ba47e386 MW |
1313 | if (result < 0) |
1314 | return result; | |
b60503ba | 1315 | |
a4aea562 | 1316 | nvmeq = dev->queues[0]; |
cd638946 | 1317 | if (!nvmeq) { |
2b25d981 | 1318 | nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH); |
cd638946 KB |
1319 | if (!nvmeq) |
1320 | return -ENOMEM; | |
cd638946 | 1321 | } |
b60503ba MW |
1322 | |
1323 | aqa = nvmeq->q_depth - 1; | |
1324 | aqa |= aqa << 16; | |
1325 | ||
7a67cbea CH |
1326 | writel(aqa, dev->bar + NVME_REG_AQA); |
1327 | lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ); | |
1328 | lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ); | |
b60503ba | 1329 | |
5fd4ce1b | 1330 | result = nvme_enable_ctrl(&dev->ctrl, cap); |
025c557a | 1331 | if (result) |
a4aea562 MB |
1332 | goto free_nvmeq; |
1333 | ||
2b25d981 | 1334 | nvmeq->cq_vector = 0; |
3193f07b | 1335 | result = queue_request_irq(dev, nvmeq, nvmeq->irqname); |
758dd7fd JD |
1336 | if (result) { |
1337 | nvmeq->cq_vector = -1; | |
0fb59cbc | 1338 | goto free_nvmeq; |
758dd7fd | 1339 | } |
025c557a | 1340 | |
b60503ba | 1341 | return result; |
a4aea562 | 1342 | |
a4aea562 MB |
1343 | free_nvmeq: |
1344 | nvme_free_queues(dev, 0); | |
1345 | return result; | |
b60503ba MW |
1346 | } |
1347 | ||
1fa6aead MW |
1348 | static int nvme_kthread(void *data) |
1349 | { | |
d4b4ff8e | 1350 | struct nvme_dev *dev, *next; |
1fa6aead MW |
1351 | |
1352 | while (!kthread_should_stop()) { | |
564a232c | 1353 | set_current_state(TASK_INTERRUPTIBLE); |
1fa6aead | 1354 | spin_lock(&dev_list_lock); |
d4b4ff8e | 1355 | list_for_each_entry_safe(dev, next, &dev_list, node) { |
1fa6aead | 1356 | int i; |
7a67cbea | 1357 | u32 csts = readl(dev->bar + NVME_REG_CSTS); |
dfbac8c7 | 1358 | |
846cc05f CH |
1359 | /* |
1360 | * Skip controllers currently under reset. | |
1361 | */ | |
1362 | if (work_pending(&dev->reset_work) || work_busy(&dev->reset_work)) | |
1363 | continue; | |
1364 | ||
dfbac8c7 KB |
1365 | if ((dev->subsystem && (csts & NVME_CSTS_NSSRO)) || |
1366 | csts & NVME_CSTS_CFS) { | |
846cc05f | 1367 | if (queue_work(nvme_workq, &dev->reset_work)) { |
90667892 CH |
1368 | dev_warn(dev->dev, |
1369 | "Failed status: %x, reset controller\n", | |
7a67cbea | 1370 | readl(dev->bar + NVME_REG_CSTS)); |
90667892 | 1371 | } |
d4b4ff8e KB |
1372 | continue; |
1373 | } | |
1fa6aead | 1374 | for (i = 0; i < dev->queue_count; i++) { |
a4aea562 | 1375 | struct nvme_queue *nvmeq = dev->queues[i]; |
740216fc MW |
1376 | if (!nvmeq) |
1377 | continue; | |
1fa6aead | 1378 | spin_lock_irq(&nvmeq->q_lock); |
bc57a0f7 | 1379 | nvme_process_cq(nvmeq); |
6fccf938 | 1380 | |
adf68f21 CH |
1381 | while (i == 0 && dev->ctrl.event_limit > 0) |
1382 | nvme_submit_async_event(dev); | |
1fa6aead MW |
1383 | spin_unlock_irq(&nvmeq->q_lock); |
1384 | } | |
1385 | } | |
1386 | spin_unlock(&dev_list_lock); | |
acb7aa0d | 1387 | schedule_timeout(round_jiffies_relative(HZ)); |
1fa6aead MW |
1388 | } |
1389 | return 0; | |
1390 | } | |
1391 | ||
749941f2 | 1392 | static int nvme_create_io_queues(struct nvme_dev *dev) |
42f61420 | 1393 | { |
a4aea562 | 1394 | unsigned i; |
749941f2 | 1395 | int ret = 0; |
42f61420 | 1396 | |
749941f2 CH |
1397 | for (i = dev->queue_count; i <= dev->max_qid; i++) { |
1398 | if (!nvme_alloc_queue(dev, i, dev->q_depth)) { | |
1399 | ret = -ENOMEM; | |
42f61420 | 1400 | break; |
749941f2 CH |
1401 | } |
1402 | } | |
42f61420 | 1403 | |
749941f2 CH |
1404 | for (i = dev->online_queues; i <= dev->queue_count - 1; i++) { |
1405 | ret = nvme_create_queue(dev->queues[i], i); | |
1406 | if (ret) { | |
2659e57b | 1407 | nvme_free_queues(dev, i); |
42f61420 | 1408 | break; |
2659e57b | 1409 | } |
749941f2 CH |
1410 | } |
1411 | ||
1412 | /* | |
1413 | * Ignore failing Create SQ/CQ commands, we can continue with less | |
1414 | * than the desired aount of queues, and even a controller without | |
1415 | * I/O queues an still be used to issue admin commands. This might | |
1416 | * be useful to upgrade a buggy firmware for example. | |
1417 | */ | |
1418 | return ret >= 0 ? 0 : ret; | |
42f61420 KB |
1419 | } |
1420 | ||
8ffaadf7 JD |
1421 | static void __iomem *nvme_map_cmb(struct nvme_dev *dev) |
1422 | { | |
1423 | u64 szu, size, offset; | |
1424 | u32 cmbloc; | |
1425 | resource_size_t bar_size; | |
1426 | struct pci_dev *pdev = to_pci_dev(dev->dev); | |
1427 | void __iomem *cmb; | |
1428 | dma_addr_t dma_addr; | |
1429 | ||
1430 | if (!use_cmb_sqes) | |
1431 | return NULL; | |
1432 | ||
7a67cbea | 1433 | dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ); |
8ffaadf7 JD |
1434 | if (!(NVME_CMB_SZ(dev->cmbsz))) |
1435 | return NULL; | |
1436 | ||
7a67cbea | 1437 | cmbloc = readl(dev->bar + NVME_REG_CMBLOC); |
8ffaadf7 JD |
1438 | |
1439 | szu = (u64)1 << (12 + 4 * NVME_CMB_SZU(dev->cmbsz)); | |
1440 | size = szu * NVME_CMB_SZ(dev->cmbsz); | |
1441 | offset = szu * NVME_CMB_OFST(cmbloc); | |
1442 | bar_size = pci_resource_len(pdev, NVME_CMB_BIR(cmbloc)); | |
1443 | ||
1444 | if (offset > bar_size) | |
1445 | return NULL; | |
1446 | ||
1447 | /* | |
1448 | * Controllers may support a CMB size larger than their BAR, | |
1449 | * for example, due to being behind a bridge. Reduce the CMB to | |
1450 | * the reported size of the BAR | |
1451 | */ | |
1452 | if (size > bar_size - offset) | |
1453 | size = bar_size - offset; | |
1454 | ||
1455 | dma_addr = pci_resource_start(pdev, NVME_CMB_BIR(cmbloc)) + offset; | |
1456 | cmb = ioremap_wc(dma_addr, size); | |
1457 | if (!cmb) | |
1458 | return NULL; | |
1459 | ||
1460 | dev->cmb_dma_addr = dma_addr; | |
1461 | dev->cmb_size = size; | |
1462 | return cmb; | |
1463 | } | |
1464 | ||
1465 | static inline void nvme_release_cmb(struct nvme_dev *dev) | |
1466 | { | |
1467 | if (dev->cmb) { | |
1468 | iounmap(dev->cmb); | |
1469 | dev->cmb = NULL; | |
1470 | } | |
1471 | } | |
1472 | ||
9d713c2b KB |
1473 | static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) |
1474 | { | |
b80d5ccc | 1475 | return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride); |
9d713c2b KB |
1476 | } |
1477 | ||
8d85fce7 | 1478 | static int nvme_setup_io_queues(struct nvme_dev *dev) |
b60503ba | 1479 | { |
a4aea562 | 1480 | struct nvme_queue *adminq = dev->queues[0]; |
e75ec752 | 1481 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
42f61420 | 1482 | int result, i, vecs, nr_io_queues, size; |
b60503ba | 1483 | |
42f61420 | 1484 | nr_io_queues = num_possible_cpus(); |
9a0be7ab CH |
1485 | result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues); |
1486 | if (result < 0) | |
1b23484b | 1487 | return result; |
9a0be7ab CH |
1488 | |
1489 | /* | |
1490 | * Degraded controllers might return an error when setting the queue | |
1491 | * count. We still want to be able to bring them online and offer | |
1492 | * access to the admin queue, as that might be only way to fix them up. | |
1493 | */ | |
1494 | if (result > 0) { | |
1495 | dev_err(dev->dev, "Could not set queue count (%d)\n", result); | |
1496 | nr_io_queues = 0; | |
1497 | result = 0; | |
1498 | } | |
b60503ba | 1499 | |
8ffaadf7 JD |
1500 | if (dev->cmb && NVME_CMB_SQS(dev->cmbsz)) { |
1501 | result = nvme_cmb_qdepth(dev, nr_io_queues, | |
1502 | sizeof(struct nvme_command)); | |
1503 | if (result > 0) | |
1504 | dev->q_depth = result; | |
1505 | else | |
1506 | nvme_release_cmb(dev); | |
1507 | } | |
1508 | ||
9d713c2b KB |
1509 | size = db_bar_size(dev, nr_io_queues); |
1510 | if (size > 8192) { | |
f1938f6e | 1511 | iounmap(dev->bar); |
9d713c2b KB |
1512 | do { |
1513 | dev->bar = ioremap(pci_resource_start(pdev, 0), size); | |
1514 | if (dev->bar) | |
1515 | break; | |
1516 | if (!--nr_io_queues) | |
1517 | return -ENOMEM; | |
1518 | size = db_bar_size(dev, nr_io_queues); | |
1519 | } while (1); | |
7a67cbea | 1520 | dev->dbs = dev->bar + 4096; |
5a92e700 | 1521 | adminq->q_db = dev->dbs; |
f1938f6e MW |
1522 | } |
1523 | ||
9d713c2b | 1524 | /* Deregister the admin queue's interrupt */ |
3193f07b | 1525 | free_irq(dev->entry[0].vector, adminq); |
9d713c2b | 1526 | |
e32efbfc JA |
1527 | /* |
1528 | * If we enable msix early due to not intx, disable it again before | |
1529 | * setting up the full range we need. | |
1530 | */ | |
1531 | if (!pdev->irq) | |
1532 | pci_disable_msix(pdev); | |
1533 | ||
be577fab | 1534 | for (i = 0; i < nr_io_queues; i++) |
1b23484b | 1535 | dev->entry[i].entry = i; |
be577fab AG |
1536 | vecs = pci_enable_msix_range(pdev, dev->entry, 1, nr_io_queues); |
1537 | if (vecs < 0) { | |
1538 | vecs = pci_enable_msi_range(pdev, 1, min(nr_io_queues, 32)); | |
1539 | if (vecs < 0) { | |
1540 | vecs = 1; | |
1541 | } else { | |
1542 | for (i = 0; i < vecs; i++) | |
1543 | dev->entry[i].vector = i + pdev->irq; | |
fa08a396 RRG |
1544 | } |
1545 | } | |
1546 | ||
063a8096 MW |
1547 | /* |
1548 | * Should investigate if there's a performance win from allocating | |
1549 | * more queues than interrupt vectors; it might allow the submission | |
1550 | * path to scale better, even if the receive path is limited by the | |
1551 | * number of interrupts. | |
1552 | */ | |
1553 | nr_io_queues = vecs; | |
42f61420 | 1554 | dev->max_qid = nr_io_queues; |
063a8096 | 1555 | |
3193f07b | 1556 | result = queue_request_irq(dev, adminq, adminq->irqname); |
758dd7fd JD |
1557 | if (result) { |
1558 | adminq->cq_vector = -1; | |
22404274 | 1559 | goto free_queues; |
758dd7fd | 1560 | } |
1b23484b | 1561 | |
cd638946 | 1562 | /* Free previously allocated queues that are no longer usable */ |
42f61420 | 1563 | nvme_free_queues(dev, nr_io_queues + 1); |
749941f2 | 1564 | return nvme_create_io_queues(dev); |
b60503ba | 1565 | |
22404274 | 1566 | free_queues: |
a1a5ef99 | 1567 | nvme_free_queues(dev, 1); |
22404274 | 1568 | return result; |
b60503ba MW |
1569 | } |
1570 | ||
bda4e0fb KB |
1571 | static void nvme_set_irq_hints(struct nvme_dev *dev) |
1572 | { | |
1573 | struct nvme_queue *nvmeq; | |
1574 | int i; | |
1575 | ||
1576 | for (i = 0; i < dev->online_queues; i++) { | |
1577 | nvmeq = dev->queues[i]; | |
1578 | ||
1579 | if (!nvmeq->tags || !(*nvmeq->tags)) | |
1580 | continue; | |
1581 | ||
1582 | irq_set_affinity_hint(dev->entry[nvmeq->cq_vector].vector, | |
1583 | blk_mq_tags_cpumask(*nvmeq->tags)); | |
1584 | } | |
1585 | } | |
1586 | ||
a5768aa8 KB |
1587 | static void nvme_dev_scan(struct work_struct *work) |
1588 | { | |
1589 | struct nvme_dev *dev = container_of(work, struct nvme_dev, scan_work); | |
a5768aa8 KB |
1590 | |
1591 | if (!dev->tagset.tags) | |
1592 | return; | |
5bae7f73 | 1593 | nvme_scan_namespaces(&dev->ctrl); |
bda4e0fb | 1594 | nvme_set_irq_hints(dev); |
a5768aa8 KB |
1595 | } |
1596 | ||
422ef0c7 MW |
1597 | /* |
1598 | * Return: error value if an error occurred setting up the queues or calling | |
1599 | * Identify Device. 0 if these succeeded, even if adding some of the | |
1600 | * namespaces failed. At the moment, these failures are silent. TBD which | |
1601 | * failures should be reported. | |
1602 | */ | |
8d85fce7 | 1603 | static int nvme_dev_add(struct nvme_dev *dev) |
b60503ba | 1604 | { |
5bae7f73 | 1605 | if (!dev->ctrl.tagset) { |
ffe7704d KB |
1606 | dev->tagset.ops = &nvme_mq_ops; |
1607 | dev->tagset.nr_hw_queues = dev->online_queues - 1; | |
1608 | dev->tagset.timeout = NVME_IO_TIMEOUT; | |
1609 | dev->tagset.numa_node = dev_to_node(dev->dev); | |
1610 | dev->tagset.queue_depth = | |
a4aea562 | 1611 | min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1; |
ffe7704d KB |
1612 | dev->tagset.cmd_size = nvme_cmd_size(dev); |
1613 | dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE; | |
1614 | dev->tagset.driver_data = dev; | |
b60503ba | 1615 | |
ffe7704d KB |
1616 | if (blk_mq_alloc_tag_set(&dev->tagset)) |
1617 | return 0; | |
5bae7f73 | 1618 | dev->ctrl.tagset = &dev->tagset; |
ffe7704d | 1619 | } |
92f7a162 | 1620 | queue_work(nvme_workq, &dev->scan_work); |
e1e5e564 | 1621 | return 0; |
b60503ba MW |
1622 | } |
1623 | ||
0877cb0d KB |
1624 | static int nvme_dev_map(struct nvme_dev *dev) |
1625 | { | |
42f61420 | 1626 | u64 cap; |
0877cb0d | 1627 | int bars, result = -ENOMEM; |
e75ec752 | 1628 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
0877cb0d KB |
1629 | |
1630 | if (pci_enable_device_mem(pdev)) | |
1631 | return result; | |
1632 | ||
1633 | dev->entry[0].vector = pdev->irq; | |
1634 | pci_set_master(pdev); | |
1635 | bars = pci_select_bars(pdev, IORESOURCE_MEM); | |
be7837e8 JA |
1636 | if (!bars) |
1637 | goto disable_pci; | |
1638 | ||
0877cb0d KB |
1639 | if (pci_request_selected_regions(pdev, bars, "nvme")) |
1640 | goto disable_pci; | |
1641 | ||
e75ec752 CH |
1642 | if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) && |
1643 | dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32))) | |
052d0efa | 1644 | goto disable; |
0877cb0d | 1645 | |
0877cb0d KB |
1646 | dev->bar = ioremap(pci_resource_start(pdev, 0), 8192); |
1647 | if (!dev->bar) | |
1648 | goto disable; | |
e32efbfc | 1649 | |
7a67cbea | 1650 | if (readl(dev->bar + NVME_REG_CSTS) == -1) { |
0e53d180 KB |
1651 | result = -ENODEV; |
1652 | goto unmap; | |
1653 | } | |
e32efbfc JA |
1654 | |
1655 | /* | |
1656 | * Some devices don't advertse INTx interrupts, pre-enable a single | |
1657 | * MSIX vec for setup. We'll adjust this later. | |
1658 | */ | |
1659 | if (!pdev->irq) { | |
1660 | result = pci_enable_msix(pdev, dev->entry, 1); | |
1661 | if (result < 0) | |
1662 | goto unmap; | |
1663 | } | |
1664 | ||
7a67cbea CH |
1665 | cap = lo_hi_readq(dev->bar + NVME_REG_CAP); |
1666 | ||
42f61420 KB |
1667 | dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH); |
1668 | dev->db_stride = 1 << NVME_CAP_STRIDE(cap); | |
7a67cbea CH |
1669 | dev->dbs = dev->bar + 4096; |
1670 | if (readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 2)) | |
8ffaadf7 | 1671 | dev->cmb = nvme_map_cmb(dev); |
0877cb0d KB |
1672 | |
1673 | return 0; | |
1674 | ||
0e53d180 KB |
1675 | unmap: |
1676 | iounmap(dev->bar); | |
1677 | dev->bar = NULL; | |
0877cb0d KB |
1678 | disable: |
1679 | pci_release_regions(pdev); | |
1680 | disable_pci: | |
1681 | pci_disable_device(pdev); | |
1682 | return result; | |
1683 | } | |
1684 | ||
1685 | static void nvme_dev_unmap(struct nvme_dev *dev) | |
1686 | { | |
e75ec752 CH |
1687 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
1688 | ||
1689 | if (pdev->msi_enabled) | |
1690 | pci_disable_msi(pdev); | |
1691 | else if (pdev->msix_enabled) | |
1692 | pci_disable_msix(pdev); | |
0877cb0d KB |
1693 | |
1694 | if (dev->bar) { | |
1695 | iounmap(dev->bar); | |
1696 | dev->bar = NULL; | |
e75ec752 | 1697 | pci_release_regions(pdev); |
0877cb0d KB |
1698 | } |
1699 | ||
e75ec752 CH |
1700 | if (pci_is_enabled(pdev)) |
1701 | pci_disable_device(pdev); | |
0877cb0d KB |
1702 | } |
1703 | ||
4d115420 KB |
1704 | struct nvme_delq_ctx { |
1705 | struct task_struct *waiter; | |
1706 | struct kthread_worker *worker; | |
1707 | atomic_t refcount; | |
1708 | }; | |
1709 | ||
1710 | static void nvme_wait_dq(struct nvme_delq_ctx *dq, struct nvme_dev *dev) | |
1711 | { | |
1712 | dq->waiter = current; | |
1713 | mb(); | |
1714 | ||
1715 | for (;;) { | |
1716 | set_current_state(TASK_KILLABLE); | |
1717 | if (!atomic_read(&dq->refcount)) | |
1718 | break; | |
1719 | if (!schedule_timeout(ADMIN_TIMEOUT) || | |
1720 | fatal_signal_pending(current)) { | |
0fb59cbc KB |
1721 | /* |
1722 | * Disable the controller first since we can't trust it | |
1723 | * at this point, but leave the admin queue enabled | |
1724 | * until all queue deletion requests are flushed. | |
1725 | * FIXME: This may take a while if there are more h/w | |
1726 | * queues than admin tags. | |
1727 | */ | |
4d115420 | 1728 | set_current_state(TASK_RUNNING); |
5fd4ce1b | 1729 | nvme_disable_ctrl(&dev->ctrl, |
7a67cbea | 1730 | lo_hi_readq(dev->bar + NVME_REG_CAP)); |
0fb59cbc | 1731 | nvme_clear_queue(dev->queues[0]); |
4d115420 | 1732 | flush_kthread_worker(dq->worker); |
0fb59cbc | 1733 | nvme_disable_queue(dev, 0); |
4d115420 KB |
1734 | return; |
1735 | } | |
1736 | } | |
1737 | set_current_state(TASK_RUNNING); | |
1738 | } | |
1739 | ||
1740 | static void nvme_put_dq(struct nvme_delq_ctx *dq) | |
1741 | { | |
1742 | atomic_dec(&dq->refcount); | |
1743 | if (dq->waiter) | |
1744 | wake_up_process(dq->waiter); | |
1745 | } | |
1746 | ||
1747 | static struct nvme_delq_ctx *nvme_get_dq(struct nvme_delq_ctx *dq) | |
1748 | { | |
1749 | atomic_inc(&dq->refcount); | |
1750 | return dq; | |
1751 | } | |
1752 | ||
1753 | static void nvme_del_queue_end(struct nvme_queue *nvmeq) | |
1754 | { | |
1755 | struct nvme_delq_ctx *dq = nvmeq->cmdinfo.ctx; | |
4d115420 | 1756 | nvme_put_dq(dq); |
604e8c8d KB |
1757 | |
1758 | spin_lock_irq(&nvmeq->q_lock); | |
1759 | nvme_process_cq(nvmeq); | |
1760 | spin_unlock_irq(&nvmeq->q_lock); | |
4d115420 KB |
1761 | } |
1762 | ||
1763 | static int adapter_async_del_queue(struct nvme_queue *nvmeq, u8 opcode, | |
1764 | kthread_work_func_t fn) | |
1765 | { | |
d8f32166 | 1766 | struct request *req; |
4d115420 KB |
1767 | struct nvme_command c; |
1768 | ||
1769 | memset(&c, 0, sizeof(c)); | |
1770 | c.delete_queue.opcode = opcode; | |
1771 | c.delete_queue.qid = cpu_to_le16(nvmeq->qid); | |
1772 | ||
1773 | init_kthread_work(&nvmeq->cmdinfo.work, fn); | |
d8f32166 CH |
1774 | |
1775 | req = nvme_alloc_request(nvmeq->dev->ctrl.admin_q, &c, 0); | |
1776 | if (IS_ERR(req)) | |
1777 | return PTR_ERR(req); | |
1778 | ||
1779 | req->timeout = ADMIN_TIMEOUT; | |
1780 | req->end_io_data = &nvmeq->cmdinfo; | |
1781 | blk_execute_rq_nowait(req->q, NULL, req, 0, async_cmd_info_endio); | |
1782 | return 0; | |
4d115420 KB |
1783 | } |
1784 | ||
1785 | static void nvme_del_cq_work_handler(struct kthread_work *work) | |
1786 | { | |
1787 | struct nvme_queue *nvmeq = container_of(work, struct nvme_queue, | |
1788 | cmdinfo.work); | |
1789 | nvme_del_queue_end(nvmeq); | |
1790 | } | |
1791 | ||
1792 | static int nvme_delete_cq(struct nvme_queue *nvmeq) | |
1793 | { | |
1794 | return adapter_async_del_queue(nvmeq, nvme_admin_delete_cq, | |
1795 | nvme_del_cq_work_handler); | |
1796 | } | |
1797 | ||
1798 | static void nvme_del_sq_work_handler(struct kthread_work *work) | |
1799 | { | |
1800 | struct nvme_queue *nvmeq = container_of(work, struct nvme_queue, | |
1801 | cmdinfo.work); | |
1802 | int status = nvmeq->cmdinfo.status; | |
1803 | ||
1804 | if (!status) | |
1805 | status = nvme_delete_cq(nvmeq); | |
1806 | if (status) | |
1807 | nvme_del_queue_end(nvmeq); | |
1808 | } | |
1809 | ||
1810 | static int nvme_delete_sq(struct nvme_queue *nvmeq) | |
1811 | { | |
1812 | return adapter_async_del_queue(nvmeq, nvme_admin_delete_sq, | |
1813 | nvme_del_sq_work_handler); | |
1814 | } | |
1815 | ||
1816 | static void nvme_del_queue_start(struct kthread_work *work) | |
1817 | { | |
1818 | struct nvme_queue *nvmeq = container_of(work, struct nvme_queue, | |
1819 | cmdinfo.work); | |
4d115420 KB |
1820 | if (nvme_delete_sq(nvmeq)) |
1821 | nvme_del_queue_end(nvmeq); | |
1822 | } | |
1823 | ||
1824 | static void nvme_disable_io_queues(struct nvme_dev *dev) | |
1825 | { | |
1826 | int i; | |
1827 | DEFINE_KTHREAD_WORKER_ONSTACK(worker); | |
1828 | struct nvme_delq_ctx dq; | |
1829 | struct task_struct *kworker_task = kthread_run(kthread_worker_fn, | |
1c63dc66 | 1830 | &worker, "nvme%d", dev->ctrl.instance); |
4d115420 KB |
1831 | |
1832 | if (IS_ERR(kworker_task)) { | |
e75ec752 | 1833 | dev_err(dev->dev, |
4d115420 KB |
1834 | "Failed to create queue del task\n"); |
1835 | for (i = dev->queue_count - 1; i > 0; i--) | |
1836 | nvme_disable_queue(dev, i); | |
1837 | return; | |
1838 | } | |
1839 | ||
1840 | dq.waiter = NULL; | |
1841 | atomic_set(&dq.refcount, 0); | |
1842 | dq.worker = &worker; | |
1843 | for (i = dev->queue_count - 1; i > 0; i--) { | |
a4aea562 | 1844 | struct nvme_queue *nvmeq = dev->queues[i]; |
4d115420 KB |
1845 | |
1846 | if (nvme_suspend_queue(nvmeq)) | |
1847 | continue; | |
1848 | nvmeq->cmdinfo.ctx = nvme_get_dq(&dq); | |
1849 | nvmeq->cmdinfo.worker = dq.worker; | |
1850 | init_kthread_work(&nvmeq->cmdinfo.work, nvme_del_queue_start); | |
1851 | queue_kthread_work(dq.worker, &nvmeq->cmdinfo.work); | |
1852 | } | |
1853 | nvme_wait_dq(&dq, dev); | |
1854 | kthread_stop(kworker_task); | |
1855 | } | |
1856 | ||
7385014c CH |
1857 | static int nvme_dev_list_add(struct nvme_dev *dev) |
1858 | { | |
1859 | bool start_thread = false; | |
1860 | ||
1861 | spin_lock(&dev_list_lock); | |
1862 | if (list_empty(&dev_list) && IS_ERR_OR_NULL(nvme_thread)) { | |
1863 | start_thread = true; | |
1864 | nvme_thread = NULL; | |
1865 | } | |
1866 | list_add(&dev->node, &dev_list); | |
1867 | spin_unlock(&dev_list_lock); | |
1868 | ||
1869 | if (start_thread) { | |
1870 | nvme_thread = kthread_run(nvme_kthread, NULL, "nvme"); | |
1871 | wake_up_all(&nvme_kthread_wait); | |
1872 | } else | |
1873 | wait_event_killable(nvme_kthread_wait, nvme_thread); | |
1874 | ||
1875 | if (IS_ERR_OR_NULL(nvme_thread)) | |
1876 | return nvme_thread ? PTR_ERR(nvme_thread) : -EINTR; | |
1877 | ||
1878 | return 0; | |
1879 | } | |
1880 | ||
b9afca3e DM |
1881 | /* |
1882 | * Remove the node from the device list and check | |
1883 | * for whether or not we need to stop the nvme_thread. | |
1884 | */ | |
1885 | static void nvme_dev_list_remove(struct nvme_dev *dev) | |
1886 | { | |
1887 | struct task_struct *tmp = NULL; | |
1888 | ||
1889 | spin_lock(&dev_list_lock); | |
1890 | list_del_init(&dev->node); | |
1891 | if (list_empty(&dev_list) && !IS_ERR_OR_NULL(nvme_thread)) { | |
1892 | tmp = nvme_thread; | |
1893 | nvme_thread = NULL; | |
1894 | } | |
1895 | spin_unlock(&dev_list_lock); | |
1896 | ||
1897 | if (tmp) | |
1898 | kthread_stop(tmp); | |
1899 | } | |
1900 | ||
c9d3bf88 KB |
1901 | static void nvme_freeze_queues(struct nvme_dev *dev) |
1902 | { | |
1903 | struct nvme_ns *ns; | |
1904 | ||
5bae7f73 | 1905 | list_for_each_entry(ns, &dev->ctrl.namespaces, list) { |
c9d3bf88 KB |
1906 | blk_mq_freeze_queue_start(ns->queue); |
1907 | ||
cddcd72b | 1908 | spin_lock_irq(ns->queue->queue_lock); |
c9d3bf88 | 1909 | queue_flag_set(QUEUE_FLAG_STOPPED, ns->queue); |
cddcd72b | 1910 | spin_unlock_irq(ns->queue->queue_lock); |
c9d3bf88 KB |
1911 | |
1912 | blk_mq_cancel_requeue_work(ns->queue); | |
1913 | blk_mq_stop_hw_queues(ns->queue); | |
1914 | } | |
1915 | } | |
1916 | ||
1917 | static void nvme_unfreeze_queues(struct nvme_dev *dev) | |
1918 | { | |
1919 | struct nvme_ns *ns; | |
1920 | ||
5bae7f73 | 1921 | list_for_each_entry(ns, &dev->ctrl.namespaces, list) { |
c9d3bf88 KB |
1922 | queue_flag_clear_unlocked(QUEUE_FLAG_STOPPED, ns->queue); |
1923 | blk_mq_unfreeze_queue(ns->queue); | |
1924 | blk_mq_start_stopped_hw_queues(ns->queue, true); | |
1925 | blk_mq_kick_requeue_list(ns->queue); | |
1926 | } | |
1927 | } | |
1928 | ||
f0b50732 | 1929 | static void nvme_dev_shutdown(struct nvme_dev *dev) |
b60503ba | 1930 | { |
22404274 | 1931 | int i; |
7c1b2450 | 1932 | u32 csts = -1; |
22404274 | 1933 | |
b9afca3e | 1934 | nvme_dev_list_remove(dev); |
1fa6aead | 1935 | |
77bf25ea | 1936 | mutex_lock(&dev->shutdown_lock); |
c9d3bf88 KB |
1937 | if (dev->bar) { |
1938 | nvme_freeze_queues(dev); | |
7a67cbea | 1939 | csts = readl(dev->bar + NVME_REG_CSTS); |
c9d3bf88 | 1940 | } |
7c1b2450 | 1941 | if (csts & NVME_CSTS_CFS || !(csts & NVME_CSTS_RDY)) { |
4d115420 | 1942 | for (i = dev->queue_count - 1; i >= 0; i--) { |
a4aea562 | 1943 | struct nvme_queue *nvmeq = dev->queues[i]; |
4d115420 | 1944 | nvme_suspend_queue(nvmeq); |
4d115420 KB |
1945 | } |
1946 | } else { | |
1947 | nvme_disable_io_queues(dev); | |
5fd4ce1b | 1948 | nvme_shutdown_ctrl(&dev->ctrl); |
4d115420 KB |
1949 | nvme_disable_queue(dev, 0); |
1950 | } | |
f0b50732 | 1951 | nvme_dev_unmap(dev); |
07836e65 KB |
1952 | |
1953 | for (i = dev->queue_count - 1; i >= 0; i--) | |
1954 | nvme_clear_queue(dev->queues[i]); | |
77bf25ea | 1955 | mutex_unlock(&dev->shutdown_lock); |
f0b50732 KB |
1956 | } |
1957 | ||
091b6092 MW |
1958 | static int nvme_setup_prp_pools(struct nvme_dev *dev) |
1959 | { | |
e75ec752 | 1960 | dev->prp_page_pool = dma_pool_create("prp list page", dev->dev, |
091b6092 MW |
1961 | PAGE_SIZE, PAGE_SIZE, 0); |
1962 | if (!dev->prp_page_pool) | |
1963 | return -ENOMEM; | |
1964 | ||
99802a7a | 1965 | /* Optimisation for I/Os between 4k and 128k */ |
e75ec752 | 1966 | dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev, |
99802a7a MW |
1967 | 256, 256, 0); |
1968 | if (!dev->prp_small_pool) { | |
1969 | dma_pool_destroy(dev->prp_page_pool); | |
1970 | return -ENOMEM; | |
1971 | } | |
091b6092 MW |
1972 | return 0; |
1973 | } | |
1974 | ||
1975 | static void nvme_release_prp_pools(struct nvme_dev *dev) | |
1976 | { | |
1977 | dma_pool_destroy(dev->prp_page_pool); | |
99802a7a | 1978 | dma_pool_destroy(dev->prp_small_pool); |
091b6092 MW |
1979 | } |
1980 | ||
1673f1f0 | 1981 | static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl) |
5e82e952 | 1982 | { |
1673f1f0 | 1983 | struct nvme_dev *dev = to_nvme_dev(ctrl); |
9ac27090 | 1984 | |
e75ec752 | 1985 | put_device(dev->dev); |
4af0e21c KB |
1986 | if (dev->tagset.tags) |
1987 | blk_mq_free_tag_set(&dev->tagset); | |
1c63dc66 CH |
1988 | if (dev->ctrl.admin_q) |
1989 | blk_put_queue(dev->ctrl.admin_q); | |
5e82e952 KB |
1990 | kfree(dev->queues); |
1991 | kfree(dev->entry); | |
1992 | kfree(dev); | |
1993 | } | |
1994 | ||
fd634f41 | 1995 | static void nvme_reset_work(struct work_struct *work) |
f0b50732 | 1996 | { |
fd634f41 | 1997 | struct nvme_dev *dev = container_of(work, struct nvme_dev, reset_work); |
3cf519b5 | 1998 | int result; |
f0b50732 | 1999 | |
fd634f41 CH |
2000 | if (WARN_ON(test_bit(NVME_CTRL_RESETTING, &dev->flags))) |
2001 | goto out; | |
2002 | ||
2003 | /* | |
2004 | * If we're called to reset a live controller first shut it down before | |
2005 | * moving on. | |
2006 | */ | |
2007 | if (dev->bar) | |
2008 | nvme_dev_shutdown(dev); | |
2009 | ||
2010 | set_bit(NVME_CTRL_RESETTING, &dev->flags); | |
2011 | ||
f0b50732 KB |
2012 | result = nvme_dev_map(dev); |
2013 | if (result) | |
3cf519b5 | 2014 | goto out; |
f0b50732 KB |
2015 | |
2016 | result = nvme_configure_admin_queue(dev); | |
2017 | if (result) | |
2018 | goto unmap; | |
2019 | ||
a4aea562 | 2020 | nvme_init_queue(dev->queues[0], 0); |
0fb59cbc KB |
2021 | result = nvme_alloc_admin_tags(dev); |
2022 | if (result) | |
2023 | goto disable; | |
b9afca3e | 2024 | |
ce4541f4 CH |
2025 | result = nvme_init_identify(&dev->ctrl); |
2026 | if (result) | |
2027 | goto free_tags; | |
2028 | ||
f0b50732 | 2029 | result = nvme_setup_io_queues(dev); |
badc34d4 | 2030 | if (result) |
0fb59cbc | 2031 | goto free_tags; |
f0b50732 | 2032 | |
adf68f21 | 2033 | dev->ctrl.event_limit = NVME_NR_AEN_COMMANDS; |
3cf519b5 | 2034 | |
7385014c CH |
2035 | result = nvme_dev_list_add(dev); |
2036 | if (result) | |
2037 | goto remove; | |
2038 | ||
2659e57b CH |
2039 | /* |
2040 | * Keep the controller around but remove all namespaces if we don't have | |
2041 | * any working I/O queue. | |
2042 | */ | |
3cf519b5 CH |
2043 | if (dev->online_queues < 2) { |
2044 | dev_warn(dev->dev, "IO queues not created\n"); | |
5bae7f73 | 2045 | nvme_remove_namespaces(&dev->ctrl); |
3cf519b5 CH |
2046 | } else { |
2047 | nvme_unfreeze_queues(dev); | |
2048 | nvme_dev_add(dev); | |
2049 | } | |
2050 | ||
fd634f41 | 2051 | clear_bit(NVME_CTRL_RESETTING, &dev->flags); |
3cf519b5 | 2052 | return; |
f0b50732 | 2053 | |
7385014c CH |
2054 | remove: |
2055 | nvme_dev_list_remove(dev); | |
0fb59cbc KB |
2056 | free_tags: |
2057 | nvme_dev_remove_admin(dev); | |
1c63dc66 CH |
2058 | blk_put_queue(dev->ctrl.admin_q); |
2059 | dev->ctrl.admin_q = NULL; | |
4af0e21c | 2060 | dev->queues[0]->tags = NULL; |
f0b50732 | 2061 | disable: |
a1a5ef99 | 2062 | nvme_disable_queue(dev, 0); |
f0b50732 KB |
2063 | unmap: |
2064 | nvme_dev_unmap(dev); | |
3cf519b5 | 2065 | out: |
5c8809e6 | 2066 | nvme_remove_dead_ctrl(dev); |
f0b50732 KB |
2067 | } |
2068 | ||
5c8809e6 | 2069 | static void nvme_remove_dead_ctrl_work(struct work_struct *work) |
9a6b9458 | 2070 | { |
5c8809e6 | 2071 | struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work); |
e75ec752 | 2072 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
9a6b9458 KB |
2073 | |
2074 | if (pci_get_drvdata(pdev)) | |
c81f4975 | 2075 | pci_stop_and_remove_bus_device_locked(pdev); |
1673f1f0 | 2076 | nvme_put_ctrl(&dev->ctrl); |
9a6b9458 KB |
2077 | } |
2078 | ||
5c8809e6 | 2079 | static void nvme_remove_dead_ctrl(struct nvme_dev *dev) |
de3eff2b | 2080 | { |
5c8809e6 | 2081 | dev_warn(dev->dev, "Removing after probe failure\n"); |
1673f1f0 | 2082 | kref_get(&dev->ctrl.kref); |
5c8809e6 | 2083 | if (!schedule_work(&dev->remove_work)) |
1673f1f0 | 2084 | nvme_put_ctrl(&dev->ctrl); |
de3eff2b KB |
2085 | } |
2086 | ||
4cc06521 KB |
2087 | static int nvme_reset(struct nvme_dev *dev) |
2088 | { | |
1c63dc66 | 2089 | if (!dev->ctrl.admin_q || blk_queue_dying(dev->ctrl.admin_q)) |
4cc06521 KB |
2090 | return -ENODEV; |
2091 | ||
846cc05f CH |
2092 | if (!queue_work(nvme_workq, &dev->reset_work)) |
2093 | return -EBUSY; | |
4cc06521 | 2094 | |
846cc05f | 2095 | flush_work(&dev->reset_work); |
846cc05f | 2096 | return 0; |
4cc06521 KB |
2097 | } |
2098 | ||
1c63dc66 CH |
2099 | static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val) |
2100 | { | |
2101 | *val = readl(to_nvme_dev(ctrl)->bar + off); | |
2102 | return 0; | |
2103 | } | |
2104 | ||
5fd4ce1b CH |
2105 | static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val) |
2106 | { | |
2107 | writel(val, to_nvme_dev(ctrl)->bar + off); | |
2108 | return 0; | |
2109 | } | |
2110 | ||
7fd8930f CH |
2111 | static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val) |
2112 | { | |
2113 | *val = readq(to_nvme_dev(ctrl)->bar + off); | |
2114 | return 0; | |
2115 | } | |
2116 | ||
5bae7f73 CH |
2117 | static bool nvme_pci_io_incapable(struct nvme_ctrl *ctrl) |
2118 | { | |
2119 | struct nvme_dev *dev = to_nvme_dev(ctrl); | |
2120 | ||
2121 | return !dev->bar || dev->online_queues < 2; | |
2122 | } | |
2123 | ||
f3ca80fc CH |
2124 | static int nvme_pci_reset_ctrl(struct nvme_ctrl *ctrl) |
2125 | { | |
2126 | return nvme_reset(to_nvme_dev(ctrl)); | |
2127 | } | |
2128 | ||
1c63dc66 CH |
2129 | static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = { |
2130 | .reg_read32 = nvme_pci_reg_read32, | |
5fd4ce1b | 2131 | .reg_write32 = nvme_pci_reg_write32, |
7fd8930f | 2132 | .reg_read64 = nvme_pci_reg_read64, |
5bae7f73 | 2133 | .io_incapable = nvme_pci_io_incapable, |
f3ca80fc | 2134 | .reset_ctrl = nvme_pci_reset_ctrl, |
1673f1f0 | 2135 | .free_ctrl = nvme_pci_free_ctrl, |
1c63dc66 CH |
2136 | }; |
2137 | ||
8d85fce7 | 2138 | static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) |
b60503ba | 2139 | { |
a4aea562 | 2140 | int node, result = -ENOMEM; |
b60503ba MW |
2141 | struct nvme_dev *dev; |
2142 | ||
a4aea562 MB |
2143 | node = dev_to_node(&pdev->dev); |
2144 | if (node == NUMA_NO_NODE) | |
2145 | set_dev_node(&pdev->dev, 0); | |
2146 | ||
2147 | dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); | |
b60503ba MW |
2148 | if (!dev) |
2149 | return -ENOMEM; | |
a4aea562 MB |
2150 | dev->entry = kzalloc_node(num_possible_cpus() * sizeof(*dev->entry), |
2151 | GFP_KERNEL, node); | |
b60503ba MW |
2152 | if (!dev->entry) |
2153 | goto free; | |
a4aea562 MB |
2154 | dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *), |
2155 | GFP_KERNEL, node); | |
b60503ba MW |
2156 | if (!dev->queues) |
2157 | goto free; | |
2158 | ||
e75ec752 | 2159 | dev->dev = get_device(&pdev->dev); |
9a6b9458 | 2160 | pci_set_drvdata(pdev, dev); |
1c63dc66 | 2161 | |
f3ca80fc CH |
2162 | INIT_LIST_HEAD(&dev->node); |
2163 | INIT_WORK(&dev->scan_work, nvme_dev_scan); | |
f3ca80fc | 2164 | INIT_WORK(&dev->reset_work, nvme_reset_work); |
5c8809e6 | 2165 | INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work); |
77bf25ea | 2166 | mutex_init(&dev->shutdown_lock); |
1c63dc66 | 2167 | |
f3ca80fc | 2168 | result = nvme_setup_prp_pools(dev); |
cd58ad7d | 2169 | if (result) |
a96d4f5c | 2170 | goto put_pci; |
b60503ba | 2171 | |
f3ca80fc CH |
2172 | result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops, |
2173 | id->driver_data); | |
091b6092 | 2174 | if (result) |
2e1d8448 | 2175 | goto release_pools; |
740216fc | 2176 | |
92f7a162 | 2177 | queue_work(nvme_workq, &dev->reset_work); |
b60503ba MW |
2178 | return 0; |
2179 | ||
0877cb0d | 2180 | release_pools: |
091b6092 | 2181 | nvme_release_prp_pools(dev); |
a96d4f5c | 2182 | put_pci: |
e75ec752 | 2183 | put_device(dev->dev); |
b60503ba MW |
2184 | free: |
2185 | kfree(dev->queues); | |
2186 | kfree(dev->entry); | |
2187 | kfree(dev); | |
2188 | return result; | |
2189 | } | |
2190 | ||
f0d54a54 KB |
2191 | static void nvme_reset_notify(struct pci_dev *pdev, bool prepare) |
2192 | { | |
a6739479 | 2193 | struct nvme_dev *dev = pci_get_drvdata(pdev); |
f0d54a54 | 2194 | |
a6739479 KB |
2195 | if (prepare) |
2196 | nvme_dev_shutdown(dev); | |
2197 | else | |
92f7a162 | 2198 | queue_work(nvme_workq, &dev->reset_work); |
f0d54a54 KB |
2199 | } |
2200 | ||
09ece142 KB |
2201 | static void nvme_shutdown(struct pci_dev *pdev) |
2202 | { | |
2203 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
2204 | nvme_dev_shutdown(dev); | |
2205 | } | |
2206 | ||
8d85fce7 | 2207 | static void nvme_remove(struct pci_dev *pdev) |
b60503ba MW |
2208 | { |
2209 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
9a6b9458 KB |
2210 | |
2211 | spin_lock(&dev_list_lock); | |
2212 | list_del_init(&dev->node); | |
2213 | spin_unlock(&dev_list_lock); | |
2214 | ||
2215 | pci_set_drvdata(pdev, NULL); | |
2216 | flush_work(&dev->reset_work); | |
a5768aa8 | 2217 | flush_work(&dev->scan_work); |
5bae7f73 | 2218 | nvme_remove_namespaces(&dev->ctrl); |
53029b04 | 2219 | nvme_uninit_ctrl(&dev->ctrl); |
3399a3f7 | 2220 | nvme_dev_shutdown(dev); |
a4aea562 | 2221 | nvme_dev_remove_admin(dev); |
a1a5ef99 | 2222 | nvme_free_queues(dev, 0); |
8ffaadf7 | 2223 | nvme_release_cmb(dev); |
9a6b9458 | 2224 | nvme_release_prp_pools(dev); |
1673f1f0 | 2225 | nvme_put_ctrl(&dev->ctrl); |
b60503ba MW |
2226 | } |
2227 | ||
2228 | /* These functions are yet to be implemented */ | |
2229 | #define nvme_error_detected NULL | |
2230 | #define nvme_dump_registers NULL | |
2231 | #define nvme_link_reset NULL | |
2232 | #define nvme_slot_reset NULL | |
2233 | #define nvme_error_resume NULL | |
cd638946 | 2234 | |
671a6018 | 2235 | #ifdef CONFIG_PM_SLEEP |
cd638946 KB |
2236 | static int nvme_suspend(struct device *dev) |
2237 | { | |
2238 | struct pci_dev *pdev = to_pci_dev(dev); | |
2239 | struct nvme_dev *ndev = pci_get_drvdata(pdev); | |
2240 | ||
2241 | nvme_dev_shutdown(ndev); | |
2242 | return 0; | |
2243 | } | |
2244 | ||
2245 | static int nvme_resume(struct device *dev) | |
2246 | { | |
2247 | struct pci_dev *pdev = to_pci_dev(dev); | |
2248 | struct nvme_dev *ndev = pci_get_drvdata(pdev); | |
cd638946 | 2249 | |
92f7a162 | 2250 | queue_work(nvme_workq, &ndev->reset_work); |
9a6b9458 | 2251 | return 0; |
cd638946 | 2252 | } |
671a6018 | 2253 | #endif |
cd638946 KB |
2254 | |
2255 | static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume); | |
b60503ba | 2256 | |
1d352035 | 2257 | static const struct pci_error_handlers nvme_err_handler = { |
b60503ba MW |
2258 | .error_detected = nvme_error_detected, |
2259 | .mmio_enabled = nvme_dump_registers, | |
2260 | .link_reset = nvme_link_reset, | |
2261 | .slot_reset = nvme_slot_reset, | |
2262 | .resume = nvme_error_resume, | |
f0d54a54 | 2263 | .reset_notify = nvme_reset_notify, |
b60503ba MW |
2264 | }; |
2265 | ||
2266 | /* Move to pci_ids.h later */ | |
2267 | #define PCI_CLASS_STORAGE_EXPRESS 0x010802 | |
2268 | ||
6eb0d698 | 2269 | static const struct pci_device_id nvme_id_table[] = { |
106198ed CH |
2270 | { PCI_VDEVICE(INTEL, 0x0953), |
2271 | .driver_data = NVME_QUIRK_STRIPE_SIZE, }, | |
540c801c KB |
2272 | { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */ |
2273 | .driver_data = NVME_QUIRK_IDENTIFY_CNS, }, | |
b60503ba | 2274 | { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, |
c74dc780 | 2275 | { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) }, |
b60503ba MW |
2276 | { 0, } |
2277 | }; | |
2278 | MODULE_DEVICE_TABLE(pci, nvme_id_table); | |
2279 | ||
2280 | static struct pci_driver nvme_driver = { | |
2281 | .name = "nvme", | |
2282 | .id_table = nvme_id_table, | |
2283 | .probe = nvme_probe, | |
8d85fce7 | 2284 | .remove = nvme_remove, |
09ece142 | 2285 | .shutdown = nvme_shutdown, |
cd638946 KB |
2286 | .driver = { |
2287 | .pm = &nvme_dev_pm_ops, | |
2288 | }, | |
b60503ba MW |
2289 | .err_handler = &nvme_err_handler, |
2290 | }; | |
2291 | ||
2292 | static int __init nvme_init(void) | |
2293 | { | |
0ac13140 | 2294 | int result; |
1fa6aead | 2295 | |
b9afca3e | 2296 | init_waitqueue_head(&nvme_kthread_wait); |
b60503ba | 2297 | |
92f7a162 | 2298 | nvme_workq = alloc_workqueue("nvme", WQ_UNBOUND | WQ_MEM_RECLAIM, 0); |
9a6b9458 | 2299 | if (!nvme_workq) |
b9afca3e | 2300 | return -ENOMEM; |
9a6b9458 | 2301 | |
5bae7f73 | 2302 | result = nvme_core_init(); |
5c42ea16 | 2303 | if (result < 0) |
9a6b9458 | 2304 | goto kill_workq; |
b60503ba | 2305 | |
f3db22fe KB |
2306 | result = pci_register_driver(&nvme_driver); |
2307 | if (result) | |
f3ca80fc | 2308 | goto core_exit; |
1fa6aead | 2309 | return 0; |
b60503ba | 2310 | |
f3ca80fc | 2311 | core_exit: |
5bae7f73 | 2312 | nvme_core_exit(); |
9a6b9458 KB |
2313 | kill_workq: |
2314 | destroy_workqueue(nvme_workq); | |
b60503ba MW |
2315 | return result; |
2316 | } | |
2317 | ||
2318 | static void __exit nvme_exit(void) | |
2319 | { | |
2320 | pci_unregister_driver(&nvme_driver); | |
5bae7f73 | 2321 | nvme_core_exit(); |
9a6b9458 | 2322 | destroy_workqueue(nvme_workq); |
b9afca3e | 2323 | BUG_ON(nvme_thread && !IS_ERR(nvme_thread)); |
21bd78bc | 2324 | _nvme_check_size(); |
b60503ba MW |
2325 | } |
2326 | ||
2327 | MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); | |
2328 | MODULE_LICENSE("GPL"); | |
c78b4713 | 2329 | MODULE_VERSION("1.0"); |
b60503ba MW |
2330 | module_init(nvme_init); |
2331 | module_exit(nvme_exit); |