projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
nvme-fc: use ctrl sgl check helper
[linux-2.6-block.git] / drivers / nvme / host / pci.c
CommitLineData
5f37396d 1// SPDX-License-Identifier: GPL-2.0
b60503ba
MW		 2/*
3 * NVM Express device driver
6eb0d698 4 * Copyright (c) 2011-2014, Intel Corporation.
b60503ba
MW		 5 */
6
df4f9bc4 7#include <linux/acpi.h>
a0a3408e 8#include <linux/aer.h>
18119775 9#include <linux/async.h>
b60503ba 10#include <linux/blkdev.h>
a4aea562 11#include <linux/blk-mq.h>
dca51e78 12#include <linux/blk-mq-pci.h>
ff5350a8 13#include <linux/dmi.h>
b60503ba
MW		 14#include <linux/init.h>
15#include <linux/interrupt.h>
16#include <linux/io.h>
b60503ba
MW		 17#include <linux/mm.h>
18#include <linux/module.h>
77bf25ea 19#include <linux/mutex.h>
d0877473 20#include <linux/once.h>
b60503ba 21#include <linux/pci.h>
d916b1be 22#include <linux/suspend.h>
e1e5e564 23#include <linux/t10-pi.h>
b60503ba 24#include <linux/types.h>
2f8e2c87 25#include <linux/io-64-nonatomic-lo-hi.h>
20d3bb92 26#include <linux/io-64-nonatomic-hi-lo.h>
a98e58e5 27#include <linux/sed-opal.h>
0f238ff5 28#include <linux/pci-p2pdma.h>
797a796a 29
604c01d5 30#include "trace.h"
f11bb3e2
CH		 31#include "nvme.h"
32
c1e0cc7e 33#define SQ_SIZE(q) ((q)->q_depth << (q)->sqes)
8a1d09a6 34#define CQ_SIZE(q) ((q)->q_depth * sizeof(struct nvme_completion))
c965809c 35
a7a7cbe3 36#define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc))
9d43cf64 37
943e942e
JA		 38/*
39 * These can be higher, but we need to ensure that any command doesn't
40 * require an sg allocation that needs more than a page of data.
41 */
42#define NVME_MAX_KB_SZ 4096
43#define NVME_MAX_SEGS 127
44
58ffacb5
MW		 45static int use_threaded_interrupts;
46module_param(use_threaded_interrupts, int, 0);
47
8ffaadf7 48static bool use_cmb_sqes = true;
69f4eb9f 49module_param(use_cmb_sqes, bool, 0444);
8ffaadf7
JD		 50MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
51
87ad72a5
CH		 52static unsigned int max_host_mem_size_mb = 128;
53module_param(max_host_mem_size_mb, uint, 0444);
54MODULE_PARM_DESC(max_host_mem_size_mb,
55 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
1fa6aead 56
a7a7cbe3
CK		 57static unsigned int sgl_threshold = SZ_32K;
58module_param(sgl_threshold, uint, 0644);
59MODULE_PARM_DESC(sgl_threshold,
60 "Use SGLs when average request segment size is larger or equal to "
61 "this size. Use 0 to disable SGLs.");
62
b27c1e68 63static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
64static const struct kernel_param_ops io_queue_depth_ops = {
65 .set = io_queue_depth_set,
61f3b896 66 .get = param_get_uint,
b27c1e68 67};
68
61f3b896 69static unsigned int io_queue_depth = 1024;
b27c1e68 70module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
71MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2");
72
9c9e76d5
WZ		 73static int io_queue_count_set(const char *val, const struct kernel_param *kp)
74{
75 unsigned int n;
76 int ret;
77
78 ret = kstrtouint(val, 10, &n);
79 if (ret != 0 || n > num_possible_cpus())
80 return -EINVAL;
81 return param_set_uint(val, kp);
82}
83
84static const struct kernel_param_ops io_queue_count_ops = {
85 .set = io_queue_count_set,
86 .get = param_get_uint,
87};
88
3f68baf7 89static unsigned int write_queues;
9c9e76d5 90module_param_cb(write_queues, &io_queue_count_ops, &write_queues, 0644);
3b6592f7
JA		 91MODULE_PARM_DESC(write_queues,
92 "Number of queues to use for writes. If not set, reads and writes "
93 "will share a queue set.");
94
3f68baf7 95static unsigned int poll_queues;
9c9e76d5 96module_param_cb(poll_queues, &io_queue_count_ops, &poll_queues, 0644);
4b04cc6a
JA		 97MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO.");
98
df4f9bc4
DB		 99static bool noacpi;
100module_param(noacpi, bool, 0444);
101MODULE_PARM_DESC(noacpi, "disable acpi bios quirks");
102
1c63dc66
CH		 103struct nvme_dev;
104struct nvme_queue;
b3fffdef 105
a5cdb68c 106static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
8fae268b 107static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode);
d4b4ff8e 108
1c63dc66
CH		 109/*
110 * Represents an NVM Express device. Each nvme_dev is a PCI function.
111 */
112struct nvme_dev {
147b27e4 113 struct nvme_queue *queues;
1c63dc66
CH		 114 struct blk_mq_tag_set tagset;
115 struct blk_mq_tag_set admin_tagset;
116 u32 __iomem *dbs;
117 struct device *dev;
118 struct dma_pool *prp_page_pool;
119 struct dma_pool *prp_small_pool;
1c63dc66
CH		 120 unsigned online_queues;
121 unsigned max_qid;
e20ba6e1 122 unsigned io_queues[HCTX_MAX_TYPES];
22b55601 123 unsigned int num_vecs;
7442ddce 124 u32 q_depth;
c1e0cc7e 125 int io_sqes;
1c63dc66 126 u32 db_stride;
1c63dc66 127 void __iomem *bar;
97f6ef64 128 unsigned long bar_mapped_size;
5c8809e6 129 struct work_struct remove_work;
77bf25ea 130 struct mutex shutdown_lock;
1c63dc66 131 bool subsystem;
1c63dc66 132 u64 cmb_size;
0f238ff5 133 bool cmb_use_sqes;
1c63dc66 134 u32 cmbsz;
202021c1 135 u32 cmbloc;
1c63dc66 136 struct nvme_ctrl ctrl;
d916b1be 137 u32 last_ps;
87ad72a5 138
943e942e
JA		 139 mempool_t *iod_mempool;
140
87ad72a5 141 /* shadow doorbell buffer support: */
f9f38e33
HK		 142 u32 *dbbuf_dbs;
143 dma_addr_t dbbuf_dbs_dma_addr;
144 u32 *dbbuf_eis;
145 dma_addr_t dbbuf_eis_dma_addr;
87ad72a5
CH		 146
147 /* host memory buffer support: */
148 u64 host_mem_size;
149 u32 nr_host_mem_descs;
4033f35d 150 dma_addr_t host_mem_descs_dma;
87ad72a5
CH		 151 struct nvme_host_mem_buf_desc *host_mem_descs;
152 void **host_mem_desc_bufs;
2a5bcfdd
WZ		 153 unsigned int nr_allocated_queues;
154 unsigned int nr_write_queues;
155 unsigned int nr_poll_queues;
4d115420 156};
1fa6aead 157
b27c1e68 158static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
159{
61f3b896 160 int ret;
7442ddce 161 u32 n;
b27c1e68 162
7442ddce 163 ret = kstrtou32(val, 10, &n);
b27c1e68 164 if (ret != 0 || n < 2)
165 return -EINVAL;
166
7442ddce 167 return param_set_uint(val, kp);
b27c1e68 168}
169
f9f38e33
HK		 170static inline unsigned int sq_idx(unsigned int qid, u32 stride)
171{
172 return qid * 2 * stride;
173}
174
175static inline unsigned int cq_idx(unsigned int qid, u32 stride)
176{
177 return (qid * 2 + 1) * stride;
178}
179
1c63dc66
CH		 180static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
181{
182 return container_of(ctrl, struct nvme_dev, ctrl);
183}
184
b60503ba
MW		 185/*
186 * An NVM Express queue. Each device has at least two (one for admin
187 * commands and one for I/O commands).
188 */
189struct nvme_queue {
091b6092 190 struct nvme_dev *dev;
1ab0cd69 191 spinlock_t sq_lock;
c1e0cc7e 192 void *sq_cmds;
3a7afd8e
CH		 193 /* only used for poll queues: */
194 spinlock_t cq_poll_lock ____cacheline_aligned_in_smp;
74943d45 195 struct nvme_completion *cqes;
b60503ba
MW		 196 dma_addr_t sq_dma_addr;
197 dma_addr_t cq_dma_addr;
b60503ba 198 u32 __iomem *q_db;
7442ddce 199 u32 q_depth;
7c349dde 200 u16 cq_vector;
b60503ba 201 u16 sq_tail;
38210800 202 u16 last_sq_tail;
b60503ba 203 u16 cq_head;
c30341dc 204 u16 qid;
e9539f47 205 u8 cq_phase;
c1e0cc7e 206 u8 sqes;
4e224106
CH		 207 unsigned long flags;
208#define NVMEQ_ENABLED 0
63223078 209#define NVMEQ_SQ_CMB 1
d1ed6aa1 210#define NVMEQ_DELETE_ERROR 2
7c349dde 211#define NVMEQ_POLLED 3
f9f38e33
HK		 212 u32 *dbbuf_sq_db;
213 u32 *dbbuf_cq_db;
214 u32 *dbbuf_sq_ei;
215 u32 *dbbuf_cq_ei;
d1ed6aa1 216 struct completion delete_done;
b60503ba
MW		 217};
218
71bd150c 219/*
9b048119
CH		 220 * The nvme_iod describes the data in an I/O.
221 *
222 * The sg pointer contains the list of PRP/SGL chunk allocations in addition
223 * to the actual struct scatterlist.
71bd150c
CH		 224 */
225struct nvme_iod {
d49187e9 226 struct nvme_request req;
af7fae85 227 struct nvme_command cmd;
f4800d6d 228 struct nvme_queue *nvmeq;
a7a7cbe3 229 bool use_sgl;
f4800d6d 230 int aborted;
71bd150c 231 int npages; /* In the PRP list. 0 means small pool in use */
71bd150c 232 int nents; /* Used in scatterlist */
71bd150c 233 dma_addr_t first_dma;
dff824b2 234 unsigned int dma_len; /* length of single DMA segment mapping */
783b94bd 235 dma_addr_t meta_dma;
f4800d6d 236 struct scatterlist *sg;
b60503ba
MW		 237};
238
2a5bcfdd 239static inline unsigned int nvme_dbbuf_size(struct nvme_dev *dev)
3b6592f7 240{
2a5bcfdd 241 return dev->nr_allocated_queues * 8 * dev->db_stride;
f9f38e33
HK		 242}
243
244static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
245{
2a5bcfdd 246 unsigned int mem_size = nvme_dbbuf_size(dev);
f9f38e33
HK		 247
248 if (dev->dbbuf_dbs)
249 return 0;
250
251 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
252 &dev->dbbuf_dbs_dma_addr,
253 GFP_KERNEL);
254 if (!dev->dbbuf_dbs)
255 return -ENOMEM;
256 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
257 &dev->dbbuf_eis_dma_addr,
258 GFP_KERNEL);
259 if (!dev->dbbuf_eis) {
260 dma_free_coherent(dev->dev, mem_size,
261 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
262 dev->dbbuf_dbs = NULL;
263 return -ENOMEM;
264 }
265
266 return 0;
267}
268
269static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
270{
2a5bcfdd 271 unsigned int mem_size = nvme_dbbuf_size(dev);
f9f38e33
HK		 272
273 if (dev->dbbuf_dbs) {
274 dma_free_coherent(dev->dev, mem_size,
275 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
276 dev->dbbuf_dbs = NULL;
277 }
278 if (dev->dbbuf_eis) {
279 dma_free_coherent(dev->dev, mem_size,
280 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
281 dev->dbbuf_eis = NULL;
282 }
283}
284
285static void nvme_dbbuf_init(struct nvme_dev *dev,
286 struct nvme_queue *nvmeq, int qid)
287{
288 if (!dev->dbbuf_dbs || !qid)
289 return;
290
291 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
292 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
293 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
294 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
295}
296
0f0d2c87
MI		 297static void nvme_dbbuf_free(struct nvme_queue *nvmeq)
298{
299 if (!nvmeq->qid)
300 return;
301
302 nvmeq->dbbuf_sq_db = NULL;
303 nvmeq->dbbuf_cq_db = NULL;
304 nvmeq->dbbuf_sq_ei = NULL;
305 nvmeq->dbbuf_cq_ei = NULL;
306}
307
f9f38e33
HK		 308static void nvme_dbbuf_set(struct nvme_dev *dev)
309{
310 struct nvme_command c;
0f0d2c87 311 unsigned int i;
f9f38e33
HK		 312
313 if (!dev->dbbuf_dbs)
314 return;
315
316 memset(&c, 0, sizeof(c));
317 c.dbbuf.opcode = nvme_admin_dbbuf;
318 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
319 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
320
321 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
9bdcfb10 322 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
f9f38e33
HK		 323 /* Free memory and continue on */
324 nvme_dbbuf_dma_free(dev);
0f0d2c87
MI		 325
326 for (i = 1; i <= dev->online_queues; i++)
327 nvme_dbbuf_free(&dev->queues[i]);
f9f38e33
HK		 328 }
329}
330
331static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
332{
333 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
334}
335
336/* Update dbbuf and return true if an MMIO is required */
337static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
338 volatile u32 *dbbuf_ei)
339{
340 if (dbbuf_db) {
341 u16 old_value;
342
343 /*
344 * Ensure that the queue is written before updating
345 * the doorbell in memory
346 */
347 wmb();
348
349 old_value = *dbbuf_db;
350 *dbbuf_db = value;
351
f1ed3df2
MW		 352 /*
353 * Ensure that the doorbell is updated before reading the event
354 * index from memory. The controller needs to provide similar
355 * ordering to ensure the envent index is updated before reading
356 * the doorbell.
357 */
358 mb();
359
f9f38e33
HK		 360 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value))
361 return false;
362 }
363
364 return true;
b60503ba
MW		 365}
366
ac3dd5bd
JA		 367/*
368 * Will slightly overestimate the number of pages needed. This is OK
369 * as it only leads to a small amount of wasted memory for the lifetime of
370 * the I/O.
371 */
b13c6393 372static int nvme_pci_npages_prp(void)
ac3dd5bd 373{
b13c6393 374 unsigned nprps = DIV_ROUND_UP(NVME_MAX_KB_SZ + NVME_CTRL_PAGE_SIZE,
6c3c05b0 375 NVME_CTRL_PAGE_SIZE);
ac3dd5bd
JA		 376 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
377}
378
a7a7cbe3
CK		 379/*
380 * Calculates the number of pages needed for the SGL segments. For example a 4k
381 * page can accommodate 256 SGL descriptors.
382 */
b13c6393 383static int nvme_pci_npages_sgl(void)
ac3dd5bd 384{
b13c6393
CK		 385 return DIV_ROUND_UP(NVME_MAX_SEGS * sizeof(struct nvme_sgl_desc),
386 PAGE_SIZE);
f4800d6d 387}
ac3dd5bd 388
b13c6393 389static size_t nvme_pci_iod_alloc_size(void)
f4800d6d 390{
b13c6393 391 size_t npages = max(nvme_pci_npages_prp(), nvme_pci_npages_sgl());
a7a7cbe3 392
b13c6393
CK		 393 return sizeof(__le64 *) * npages +
394 sizeof(struct scatterlist) * NVME_MAX_SEGS;
f4800d6d 395}
ac3dd5bd 396
a4aea562
MB		 397static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
398 unsigned int hctx_idx)
e85248e5 399{
a4aea562 400 struct nvme_dev *dev = data;
147b27e4 401 struct nvme_queue *nvmeq = &dev->queues[0];
a4aea562 402
42483228
KB		 403 WARN_ON(hctx_idx != 0);
404 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
42483228 405
a4aea562
MB		 406 hctx->driver_data = nvmeq;
407 return 0;
e85248e5
MW		 408}
409
a4aea562
MB		 410static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
411 unsigned int hctx_idx)
b60503ba 412{
a4aea562 413 struct nvme_dev *dev = data;
147b27e4 414 struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
a4aea562 415
42483228 416 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
a4aea562
MB		 417 hctx->driver_data = nvmeq;
418 return 0;
b60503ba
MW		 419}
420
d6296d39
CH		 421static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req,
422 unsigned int hctx_idx, unsigned int numa_node)
b60503ba 423{
d6296d39 424 struct nvme_dev *dev = set->driver_data;
f4800d6d 425 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
0350815a 426 int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0;
147b27e4 427 struct nvme_queue *nvmeq = &dev->queues[queue_idx];
a4aea562
MB		 428
429 BUG_ON(!nvmeq);
f4800d6d 430 iod->nvmeq = nvmeq;
59e29ce6
SG		 431
432 nvme_req(req)->ctrl = &dev->ctrl;
f4b9e6c9 433 nvme_req(req)->cmd = &iod->cmd;
a4aea562
MB		 434 return 0;
435}
436
3b6592f7
JA		 437static int queue_irq_offset(struct nvme_dev *dev)
438{
439 /* if we have more than 1 vec, admin queue offsets us by 1 */
440 if (dev->num_vecs > 1)
441 return 1;
442
443 return 0;
444}
445
dca51e78
CH		 446static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
447{
448 struct nvme_dev *dev = set->driver_data;
3b6592f7
JA		 449 int i, qoff, offset;
450
451 offset = queue_irq_offset(dev);
452 for (i = 0, qoff = 0; i < set->nr_maps; i++) {
453 struct blk_mq_queue_map *map = &set->map[i];
454
455 map->nr_queues = dev->io_queues[i];
456 if (!map->nr_queues) {
e20ba6e1 457 BUG_ON(i == HCTX_TYPE_DEFAULT);
7e849dd9 458 continue;
3b6592f7
JA		 459 }
460
4b04cc6a
JA		 461 /*
462 * The poll queue(s) doesn't have an IRQ (and hence IRQ
463 * affinity), so use the regular blk-mq cpu mapping
464 */
3b6592f7 465 map->queue_offset = qoff;
cb9e0e50 466 if (i != HCTX_TYPE_POLL && offset)
4b04cc6a
JA		 467 blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset);
468 else
469 blk_mq_map_queues(map);
3b6592f7
JA		 470 qoff += map->nr_queues;
471 offset += map->nr_queues;
472 }
473
474 return 0;
dca51e78
CH		 475}
476
38210800
KB		 477/*
478 * Write sq tail if we are asked to, or if the next command would wrap.
479 */
480static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq)
04f3eafd 481{
38210800
KB		 482 if (!write_sq) {
483 u16 next_tail = nvmeq->sq_tail + 1;
484
485 if (next_tail == nvmeq->q_depth)
486 next_tail = 0;
487 if (next_tail != nvmeq->last_sq_tail)
488 return;
489 }
490
04f3eafd
JA		 491 if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail,
492 nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei))
493 writel(nvmeq->sq_tail, nvmeq->q_db);
38210800 494 nvmeq->last_sq_tail = nvmeq->sq_tail;
04f3eafd
JA		 495}
496
b60503ba 497/**
90ea5ca4 498 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
b60503ba
MW		 499 * @nvmeq: The queue to use
500 * @cmd: The command to send
04f3eafd 501 * @write_sq: whether to write to the SQ doorbell
b60503ba 502 */
04f3eafd
JA		 503static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd,
504 bool write_sq)
b60503ba 505{
90ea5ca4 506 spin_lock(&nvmeq->sq_lock);
c1e0cc7e
BH		 507 memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes),
508 cmd, sizeof(*cmd));
90ea5ca4
CH		 509 if (++nvmeq->sq_tail == nvmeq->q_depth)
510 nvmeq->sq_tail = 0;
38210800 511 nvme_write_sq_db(nvmeq, write_sq);
04f3eafd
JA		 512 spin_unlock(&nvmeq->sq_lock);
513}
514
515static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx)
516{
517 struct nvme_queue *nvmeq = hctx->driver_data;
518
519 spin_lock(&nvmeq->sq_lock);
38210800
KB		 520 if (nvmeq->sq_tail != nvmeq->last_sq_tail)
521 nvme_write_sq_db(nvmeq, true);
90ea5ca4 522 spin_unlock(&nvmeq->sq_lock);
b60503ba
MW		 523}
524
a7a7cbe3 525static void **nvme_pci_iod_list(struct request *req)
b60503ba 526{
f4800d6d 527 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3 528 return (void **)(iod->sg + blk_rq_nr_phys_segments(req));
b60503ba
MW		 529}
530
955b1b5a
MI		 531static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req)
532{
533 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
20469a37 534 int nseg = blk_rq_nr_phys_segments(req);
955b1b5a
MI		 535 unsigned int avg_seg_size;
536
20469a37 537 avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
955b1b5a
MI		 538
539 if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1))))
540 return false;
541 if (!iod->nvmeq->qid)
542 return false;
543 if (!sgl_threshold || avg_seg_size < sgl_threshold)
544 return false;
545 return true;
546}
547
9275c206 548static void nvme_free_prps(struct nvme_dev *dev, struct request *req)
b60503ba 549{
6c3c05b0 550 const int last_prp = NVME_CTRL_PAGE_SIZE / sizeof(__le64) - 1;
9275c206
CH		 551 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
552 dma_addr_t dma_addr = iod->first_dma;
eca18b23 553 int i;
eca18b23 554
9275c206
CH		 555 for (i = 0; i < iod->npages; i++) {
556 __le64 *prp_list = nvme_pci_iod_list(req)[i];
557 dma_addr_t next_dma_addr = le64_to_cpu(prp_list[last_prp]);
558
559 dma_pool_free(dev->prp_page_pool, prp_list, dma_addr);
560 dma_addr = next_dma_addr;
7fe07d14 561 }
9275c206 562}
dff824b2 563
9275c206
CH		 564static void nvme_free_sgls(struct nvme_dev *dev, struct request *req)
565{
566 const int last_sg = SGES_PER_PAGE - 1;
567 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
568 dma_addr_t dma_addr = iod->first_dma;
569 int i;
dff824b2 570
9275c206
CH		 571 for (i = 0; i < iod->npages; i++) {
572 struct nvme_sgl_desc *sg_list = nvme_pci_iod_list(req)[i];
573 dma_addr_t next_dma_addr = le64_to_cpu((sg_list[last_sg]).addr);
dff824b2 574
9275c206
CH		 575 dma_pool_free(dev->prp_page_pool, sg_list, dma_addr);
576 dma_addr = next_dma_addr;
577 }
9275c206 578}
a7a7cbe3 579
9275c206
CH		 580static void nvme_unmap_sg(struct nvme_dev *dev, struct request *req)
581{
582 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3 583
9275c206
CH		 584 if (is_pci_p2pdma_page(sg_page(iod->sg)))
585 pci_p2pdma_unmap_sg(dev->dev, iod->sg, iod->nents,
586 rq_dma_dir(req));
587 else
588 dma_unmap_sg(dev->dev, iod->sg, iod->nents, rq_dma_dir(req));
589}
a7a7cbe3 590
9275c206
CH		 591static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
592{
593 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3 594
9275c206
CH		 595 if (iod->dma_len) {
596 dma_unmap_page(dev->dev, iod->first_dma, iod->dma_len,
597 rq_dma_dir(req));
598 return;
eca18b23 599 }
ac3dd5bd 600
9275c206
CH		 601 WARN_ON_ONCE(!iod->nents);
602
603 nvme_unmap_sg(dev, req);
604 if (iod->npages == 0)
605 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0],
606 iod->first_dma);
607 else if (iod->use_sgl)
608 nvme_free_sgls(dev, req);
609 else
610 nvme_free_prps(dev, req);
d43f1ccf 611 mempool_free(iod->sg, dev->iod_mempool);
b4ff9c8d
KB		 612}
613
d0877473
KB		 614static void nvme_print_sgl(struct scatterlist *sgl, int nents)
615{
616 int i;
617 struct scatterlist *sg;
618
619 for_each_sg(sgl, sg, nents, i) {
620 dma_addr_t phys = sg_phys(sg);
621 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
622 "dma_address:%pad dma_length:%d\n",
623 i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
624 sg_dma_len(sg));
625 }
626}
627
a7a7cbe3
CK		 628static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
629 struct request *req, struct nvme_rw_command *cmnd)
ff22b54f 630{
f4800d6d 631 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
99802a7a 632 struct dma_pool *pool;
b131c61d 633 int length = blk_rq_payload_bytes(req);
eca18b23 634 struct scatterlist *sg = iod->sg;
ff22b54f
MW		 635 int dma_len = sg_dma_len(sg);
636 u64 dma_addr = sg_dma_address(sg);
6c3c05b0 637 int offset = dma_addr & (NVME_CTRL_PAGE_SIZE - 1);
e025344c 638 __le64 *prp_list;
a7a7cbe3 639 void **list = nvme_pci_iod_list(req);
e025344c 640 dma_addr_t prp_dma;
eca18b23 641 int nprps, i;
ff22b54f 642
6c3c05b0 643 length -= (NVME_CTRL_PAGE_SIZE - offset);
5228b328
JS		 644 if (length <= 0) {
645 iod->first_dma = 0;
a7a7cbe3 646 goto done;
5228b328 647 }
ff22b54f 648
6c3c05b0 649 dma_len -= (NVME_CTRL_PAGE_SIZE - offset);
ff22b54f 650 if (dma_len) {
6c3c05b0 651 dma_addr += (NVME_CTRL_PAGE_SIZE - offset);
ff22b54f
MW		 652 } else {
653 sg = sg_next(sg);
654 dma_addr = sg_dma_address(sg);
655 dma_len = sg_dma_len(sg);
656 }
657
6c3c05b0 658 if (length <= NVME_CTRL_PAGE_SIZE) {
edd10d33 659 iod->first_dma = dma_addr;
a7a7cbe3 660 goto done;
e025344c
SMM		 661 }
662
6c3c05b0 663 nprps = DIV_ROUND_UP(length, NVME_CTRL_PAGE_SIZE);
99802a7a
MW		 664 if (nprps <= (256 / 8)) {
665 pool = dev->prp_small_pool;
eca18b23 666 iod->npages = 0;
99802a7a
MW		 667 } else {
668 pool = dev->prp_page_pool;
eca18b23 669 iod->npages = 1;
99802a7a
MW		 670 }
671
69d2b571 672 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
b77954cb 673 if (!prp_list) {
edd10d33 674 iod->first_dma = dma_addr;
eca18b23 675 iod->npages = -1;
86eea289 676 return BLK_STS_RESOURCE;
b77954cb 677 }
eca18b23
MW		 678 list[0] = prp_list;
679 iod->first_dma = prp_dma;
e025344c
SMM		 680 i = 0;
681 for (;;) {
6c3c05b0 682 if (i == NVME_CTRL_PAGE_SIZE >> 3) {
e025344c 683 __le64 *old_prp_list = prp_list;
69d2b571 684 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
eca18b23 685 if (!prp_list)
fa073216 686 goto free_prps;
eca18b23 687 list[iod->npages++] = prp_list;
7523d834
MW		 688 prp_list[0] = old_prp_list[i - 1];
689 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
690 i = 1;
e025344c
SMM		 691 }
692 prp_list[i++] = cpu_to_le64(dma_addr);
6c3c05b0
CK		 693 dma_len -= NVME_CTRL_PAGE_SIZE;
694 dma_addr += NVME_CTRL_PAGE_SIZE;
695 length -= NVME_CTRL_PAGE_SIZE;
e025344c
SMM		 696 if (length <= 0)
697 break;
698 if (dma_len > 0)
699 continue;
86eea289
KB		 700 if (unlikely(dma_len < 0))
701 goto bad_sgl;
e025344c
SMM		 702 sg = sg_next(sg);
703 dma_addr = sg_dma_address(sg);
704 dma_len = sg_dma_len(sg);
ff22b54f 705 }
a7a7cbe3
CK		 706done:
707 cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
708 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
86eea289 709 return BLK_STS_OK;
fa073216
CH		 710free_prps:
711 nvme_free_prps(dev, req);
712 return BLK_STS_RESOURCE;
713bad_sgl:
d0877473
KB		 714 WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents),
715 "Invalid SGL for payload:%d nents:%d\n",
716 blk_rq_payload_bytes(req), iod->nents);
86eea289 717 return BLK_STS_IOERR;
ff22b54f
MW		 718}
719
a7a7cbe3
CK		 720static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
721 struct scatterlist *sg)
722{
723 sge->addr = cpu_to_le64(sg_dma_address(sg));
724 sge->length = cpu_to_le32(sg_dma_len(sg));
725 sge->type = NVME_SGL_FMT_DATA_DESC << 4;
726}
727
728static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
729 dma_addr_t dma_addr, int entries)
730{
731 sge->addr = cpu_to_le64(dma_addr);
732 if (entries < SGES_PER_PAGE) {
733 sge->length = cpu_to_le32(entries * sizeof(*sge));
734 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
735 } else {
736 sge->length = cpu_to_le32(PAGE_SIZE);
737 sge->type = NVME_SGL_FMT_SEG_DESC << 4;
738 }
739}
740
741static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
b0f2853b 742 struct request *req, struct nvme_rw_command *cmd, int entries)
a7a7cbe3
CK		 743{
744 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3
CK		 745 struct dma_pool *pool;
746 struct nvme_sgl_desc *sg_list;
747 struct scatterlist *sg = iod->sg;
a7a7cbe3 748 dma_addr_t sgl_dma;
b0f2853b 749 int i = 0;
a7a7cbe3 750
a7a7cbe3
CK		 751 /* setting the transfer type as SGL */
752 cmd->flags = NVME_CMD_SGL_METABUF;
753
b0f2853b 754 if (entries == 1) {
a7a7cbe3
CK		 755 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
756 return BLK_STS_OK;
757 }
758
759 if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
760 pool = dev->prp_small_pool;
761 iod->npages = 0;
762 } else {
763 pool = dev->prp_page_pool;
764 iod->npages = 1;
765 }
766
767 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
768 if (!sg_list) {
769 iod->npages = -1;
770 return BLK_STS_RESOURCE;
771 }
772
773 nvme_pci_iod_list(req)[0] = sg_list;
774 iod->first_dma = sgl_dma;
775
776 nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
777
778 do {
779 if (i == SGES_PER_PAGE) {
780 struct nvme_sgl_desc *old_sg_desc = sg_list;
781 struct nvme_sgl_desc *link = &old_sg_desc[i - 1];
782
783 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
784 if (!sg_list)
fa073216 785 goto free_sgls;
a7a7cbe3
CK		 786
787 i = 0;
788 nvme_pci_iod_list(req)[iod->npages++] = sg_list;
789 sg_list[i++] = *link;
790 nvme_pci_sgl_set_seg(link, sgl_dma, entries);
791 }
792
793 nvme_pci_sgl_set_data(&sg_list[i++], sg);
a7a7cbe3 794 sg = sg_next(sg);
b0f2853b 795 } while (--entries > 0);
a7a7cbe3 796
a7a7cbe3 797 return BLK_STS_OK;
fa073216
CH		 798free_sgls:
799 nvme_free_sgls(dev, req);
800 return BLK_STS_RESOURCE;
a7a7cbe3
CK		 801}
802
dff824b2
CH		 803static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev,
804 struct request *req, struct nvme_rw_command *cmnd,
805 struct bio_vec *bv)
806{
807 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
6c3c05b0
CK		 808 unsigned int offset = bv->bv_offset & (NVME_CTRL_PAGE_SIZE - 1);
809 unsigned int first_prp_len = NVME_CTRL_PAGE_SIZE - offset;
dff824b2
CH		 810
811 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
812 if (dma_mapping_error(dev->dev, iod->first_dma))
813 return BLK_STS_RESOURCE;
814 iod->dma_len = bv->bv_len;
815
816 cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma);
817 if (bv->bv_len > first_prp_len)
818 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len);
359c1f88 819 return BLK_STS_OK;
dff824b2
CH		 820}
821
29791057
CH		 822static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev,
823 struct request *req, struct nvme_rw_command *cmnd,
824 struct bio_vec *bv)
825{
826 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
827
828 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
829 if (dma_mapping_error(dev->dev, iod->first_dma))
830 return BLK_STS_RESOURCE;
831 iod->dma_len = bv->bv_len;
832
049bf372 833 cmnd->flags = NVME_CMD_SGL_METABUF;
29791057
CH		 834 cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma);
835 cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len);
836 cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4;
359c1f88 837 return BLK_STS_OK;
29791057
CH		 838}
839
fc17b653 840static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
b131c61d 841 struct nvme_command *cmnd)
d29ec824 842{
f4800d6d 843 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
70479b71 844 blk_status_t ret = BLK_STS_RESOURCE;
b0f2853b 845 int nr_mapped;
d29ec824 846
dff824b2
CH		 847 if (blk_rq_nr_phys_segments(req) == 1) {
848 struct bio_vec bv = req_bvec(req);
849
850 if (!is_pci_p2pdma_page(bv.bv_page)) {
6c3c05b0 851 if (bv.bv_offset + bv.bv_len <= NVME_CTRL_PAGE_SIZE * 2)
dff824b2
CH		 852 return nvme_setup_prp_simple(dev, req,
853 &cmnd->rw, &bv);
29791057 854
e51183be 855 if (iod->nvmeq->qid && sgl_threshold &&
29791057
CH		 856 dev->ctrl.sgls & ((1 << 0) | (1 << 1)))
857 return nvme_setup_sgl_simple(dev, req,
858 &cmnd->rw, &bv);
dff824b2
CH		 859 }
860 }
861
862 iod->dma_len = 0;
d43f1ccf
CH		 863 iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC);
864 if (!iod->sg)
865 return BLK_STS_RESOURCE;
f9d03f96 866 sg_init_table(iod->sg, blk_rq_nr_phys_segments(req));
70479b71 867 iod->nents = blk_rq_map_sg(req->q, req, iod->sg);
ba1ca37e 868 if (!iod->nents)
fa073216 869 goto out_free_sg;
d29ec824 870
e0596ab2 871 if (is_pci_p2pdma_page(sg_page(iod->sg)))
2b9f4bb2
LG		 872 nr_mapped = pci_p2pdma_map_sg_attrs(dev->dev, iod->sg,
873 iod->nents, rq_dma_dir(req), DMA_ATTR_NO_WARN);
e0596ab2
LG		 874 else
875 nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents,
70479b71 876 rq_dma_dir(req), DMA_ATTR_NO_WARN);
b0f2853b 877 if (!nr_mapped)
fa073216 878 goto out_free_sg;
d29ec824 879
70479b71 880 iod->use_sgl = nvme_pci_use_sgls(dev, req);
955b1b5a 881 if (iod->use_sgl)
b0f2853b 882 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped);
a7a7cbe3
CK		 883 else
884 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
86eea289 885 if (ret != BLK_STS_OK)
fa073216
CH		 886 goto out_unmap_sg;
887 return BLK_STS_OK;
888
889out_unmap_sg:
890 nvme_unmap_sg(dev, req);
891out_free_sg:
892 mempool_free(iod->sg, dev->iod_mempool);
4aedb705
CH		 893 return ret;
894}
3045c0d0 895
4aedb705
CH		 896static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req,
897 struct nvme_command *cmnd)
898{
899 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
00df5cb4 900
4aedb705
CH		 901 iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req),
902 rq_dma_dir(req), 0);
903 if (dma_mapping_error(dev->dev, iod->meta_dma))
904 return BLK_STS_IOERR;
905 cmnd->rw.metadata = cpu_to_le64(iod->meta_dma);
359c1f88 906 return BLK_STS_OK;
00df5cb4
MW		 907}
908
d29ec824
CH		 909/*
910 * NOTE: ns is NULL when called on the admin queue.
911 */
fc17b653 912static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
a4aea562 913 const struct blk_mq_queue_data *bd)
edd10d33 914{
a4aea562
MB		 915 struct nvme_ns *ns = hctx->queue->queuedata;
916 struct nvme_queue *nvmeq = hctx->driver_data;
d29ec824 917 struct nvme_dev *dev = nvmeq->dev;
a4aea562 918 struct request *req = bd->rq;
9b048119 919 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
af7fae85 920 struct nvme_command *cmnd = &iod->cmd;
ebe6d874 921 blk_status_t ret;
e1e5e564 922
9b048119
CH		 923 iod->aborted = 0;
924 iod->npages = -1;
925 iod->nents = 0;
926
d1f06f4a
JA		 927 /*
928 * We should not need to do this, but we're still using this to
929 * ensure we can drain requests on a dying queue.
930 */
4e224106 931 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
d1f06f4a
JA		 932 return BLK_STS_IOERR;
933
d4060d2b
TC		 934 if (!nvme_check_ready(&dev->ctrl, req, true))
935 return nvme_fail_nonready_command(&dev->ctrl, req);
936
f4b9e6c9 937 ret = nvme_setup_cmd(ns, req);
fc17b653 938 if (ret)
f4800d6d 939 return ret;
a4aea562 940
fc17b653 941 if (blk_rq_nr_phys_segments(req)) {
af7fae85 942 ret = nvme_map_data(dev, req, cmnd);
fc17b653 943 if (ret)
9b048119 944 goto out_free_cmd;
fc17b653 945 }
a4aea562 946
4aedb705 947 if (blk_integrity_rq(req)) {
af7fae85 948 ret = nvme_map_metadata(dev, req, cmnd);
4aedb705
CH		 949 if (ret)
950 goto out_unmap_data;
951 }
952
aae239e1 953 blk_mq_start_request(req);
af7fae85 954 nvme_submit_cmd(nvmeq, cmnd, bd->last);
fc17b653 955 return BLK_STS_OK;
4aedb705
CH		 956out_unmap_data:
957 nvme_unmap_data(dev, req);
f9d03f96
CH		 958out_free_cmd:
959 nvme_cleanup_cmd(req);
ba1ca37e 960 return ret;
b60503ba 961}
e1e5e564 962
77f02a7a 963static void nvme_pci_complete_rq(struct request *req)
eee417b0 964{
f4800d6d 965 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
4aedb705 966 struct nvme_dev *dev = iod->nvmeq->dev;
a4aea562 967
4aedb705
CH		 968 if (blk_integrity_rq(req))
969 dma_unmap_page(dev->dev, iod->meta_dma,
970 rq_integrity_vec(req)->bv_len, rq_data_dir(req));
b15c592d 971 if (blk_rq_nr_phys_segments(req))
4aedb705 972 nvme_unmap_data(dev, req);
77f02a7a 973 nvme_complete_rq(req);
b60503ba
MW		 974}
975
d783e0bd 976/* We read the CQE phase first to check if the rest of the entry is valid */
750dde44 977static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq)
d783e0bd 978{
74943d45
KB		 979 struct nvme_completion *hcqe = &nvmeq->cqes[nvmeq->cq_head];
980
981 return (le16_to_cpu(READ_ONCE(hcqe->status)) & 1) == nvmeq->cq_phase;
d783e0bd
MR		 982}
983
eb281c82 984static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
b60503ba 985{
eb281c82 986 u16 head = nvmeq->cq_head;
adf68f21 987
397c699f
KB		 988 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
989 nvmeq->dbbuf_cq_ei))
990 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
eb281c82 991}
aae239e1 992
cfa27356
CH		 993static inline struct blk_mq_tags *nvme_queue_tagset(struct nvme_queue *nvmeq)
994{
995 if (!nvmeq->qid)
996 return nvmeq->dev->admin_tagset.tags[0];
997 return nvmeq->dev->tagset.tags[nvmeq->qid - 1];
998}
999
5cb525c8 1000static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx)
83a12fb7 1001{
74943d45 1002 struct nvme_completion *cqe = &nvmeq->cqes[idx];
62df8016 1003 __u16 command_id = READ_ONCE(cqe->command_id);
83a12fb7 1004 struct request *req;
adf68f21 1005
83a12fb7
SG		 1006 /*
1007 * AEN requests are special as they don't time out and can
1008 * survive any kind of queue freeze and often don't respond to
1009 * aborts. We don't even bother to allocate a struct request
1010 * for them but rather special case them here.
1011 */
62df8016 1012 if (unlikely(nvme_is_aen_req(nvmeq->qid, command_id))) {
83a12fb7
SG		 1013 nvme_complete_async_event(&nvmeq->dev->ctrl,
1014 cqe->status, &cqe->result);
a0fa9647 1015 return;
83a12fb7 1016 }
b60503ba 1017
62df8016 1018 req = blk_mq_tag_to_rq(nvme_queue_tagset(nvmeq), command_id);
50b7c243
XT		 1019 if (unlikely(!req)) {
1020 dev_warn(nvmeq->dev->ctrl.device,
1021 "invalid id %d completed on queue %d\n",
62df8016 1022 command_id, le16_to_cpu(cqe->sq_id));
50b7c243
XT		 1023 return;
1024 }
1025
604c01d5 1026 trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail);
2eb81a33 1027 if (!nvme_try_complete_req(req, cqe->status, cqe->result))
ff029451 1028 nvme_pci_complete_rq(req);
83a12fb7 1029}
b60503ba 1030
5cb525c8
JA		 1031static inline void nvme_update_cq_head(struct nvme_queue *nvmeq)
1032{
a0aac973 1033 u32 tmp = nvmeq->cq_head + 1;
a8de6639
AD		 1034
1035 if (tmp == nvmeq->q_depth) {
5cb525c8 1036 nvmeq->cq_head = 0;
e2a366a4 1037 nvmeq->cq_phase ^= 1;
a8de6639
AD		 1038 } else {
1039 nvmeq->cq_head = tmp;
b60503ba 1040 }
a0fa9647
JA		 1041}
1042
324b494c 1043static inline int nvme_process_cq(struct nvme_queue *nvmeq)
a0fa9647 1044{
1052b8ac 1045 int found = 0;
b60503ba 1046
1052b8ac 1047 while (nvme_cqe_pending(nvmeq)) {
bf392a5d 1048 found++;
b69e2ef2
KB		 1049 /*
1050 * load-load control dependency between phase and the rest of
1051 * the cqe requires a full read memory barrier
1052 */
1053 dma_rmb();
324b494c 1054 nvme_handle_cqe(nvmeq, nvmeq->cq_head);
5cb525c8 1055 nvme_update_cq_head(nvmeq);
920d13a8 1056 }
eb281c82 1057
324b494c 1058 if (found)
920d13a8 1059 nvme_ring_cq_doorbell(nvmeq);
5cb525c8 1060 return found;
b60503ba
MW		 1061}
1062
1063static irqreturn_t nvme_irq(int irq, void *data)
58ffacb5 1064{
58ffacb5 1065 struct nvme_queue *nvmeq = data;
5cb525c8 1066
324b494c 1067 if (nvme_process_cq(nvmeq))
05fae499
CK		 1068 return IRQ_HANDLED;
1069 return IRQ_NONE;
58ffacb5
MW		 1070}
1071
1072static irqreturn_t nvme_irq_check(int irq, void *data)
1073{
1074 struct nvme_queue *nvmeq = data;
4e523547 1075
750dde44 1076 if (nvme_cqe_pending(nvmeq))
d783e0bd
MR		 1077 return IRQ_WAKE_THREAD;
1078 return IRQ_NONE;
58ffacb5
MW		 1079}
1080
0b2a8a9f 1081/*
fa059b85 1082 * Poll for completions for any interrupt driven queue
0b2a8a9f
CH		 1083 * Can be called from any context.
1084 */
fa059b85 1085static void nvme_poll_irqdisable(struct nvme_queue *nvmeq)
a0fa9647 1086{
3a7afd8e 1087 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
a0fa9647 1088
fa059b85 1089 WARN_ON_ONCE(test_bit(NVMEQ_POLLED, &nvmeq->flags));
442e19b7 1090
fa059b85
KB		 1091 disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1092 nvme_process_cq(nvmeq);
1093 enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
a0fa9647
JA		 1094}
1095
9743139c 1096static int nvme_poll(struct blk_mq_hw_ctx *hctx)
dabcefab
JA		 1097{
1098 struct nvme_queue *nvmeq = hctx->driver_data;
dabcefab
JA		 1099 bool found;
1100
1101 if (!nvme_cqe_pending(nvmeq))
1102 return 0;
1103
3a7afd8e 1104 spin_lock(&nvmeq->cq_poll_lock);
324b494c 1105 found = nvme_process_cq(nvmeq);
3a7afd8e 1106 spin_unlock(&nvmeq->cq_poll_lock);
dabcefab 1107
dabcefab
JA		 1108 return found;
1109}
1110
ad22c355 1111static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
b60503ba 1112{
f866fc42 1113 struct nvme_dev *dev = to_nvme_dev(ctrl);
147b27e4 1114 struct nvme_queue *nvmeq = &dev->queues[0];
a4aea562 1115 struct nvme_command c;
b60503ba 1116
a4aea562
MB		 1117 memset(&c, 0, sizeof(c));
1118 c.common.opcode = nvme_admin_async_event;
ad22c355 1119 c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
04f3eafd 1120 nvme_submit_cmd(nvmeq, &c, true);
f705f837
CH		 1121}
1122
b60503ba 1123static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
f705f837 1124{
b60503ba
MW		 1125 struct nvme_command c;
1126
1127 memset(&c, 0, sizeof(c));
1128 c.delete_queue.opcode = opcode;
1129 c.delete_queue.qid = cpu_to_le16(id);
1130
1c63dc66 1131 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1132}
1133
b60503ba 1134static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
a8e3e0bb 1135 struct nvme_queue *nvmeq, s16 vector)
b60503ba 1136{
b60503ba 1137 struct nvme_command c;
4b04cc6a
JA		 1138 int flags = NVME_QUEUE_PHYS_CONTIG;
1139
7c349dde 1140 if (!test_bit(NVMEQ_POLLED, &nvmeq->flags))
4b04cc6a 1141 flags |= NVME_CQ_IRQ_ENABLED;
b60503ba 1142
d29ec824 1143 /*
16772ae6 1144 * Note: we (ab)use the fact that the prp fields survive if no data
d29ec824
CH		 1145 * is attached to the request.
1146 */
b60503ba
MW		 1147 memset(&c, 0, sizeof(c));
1148 c.create_cq.opcode = nvme_admin_create_cq;
1149 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1150 c.create_cq.cqid = cpu_to_le16(qid);
1151 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1152 c.create_cq.cq_flags = cpu_to_le16(flags);
7c349dde 1153 c.create_cq.irq_vector = cpu_to_le16(vector);
b60503ba 1154
1c63dc66 1155 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1156}
1157
1158static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1159 struct nvme_queue *nvmeq)
1160{
9abd68ef 1161 struct nvme_ctrl *ctrl = &dev->ctrl;
b60503ba 1162 struct nvme_command c;
81c1cd98 1163 int flags = NVME_QUEUE_PHYS_CONTIG;
b60503ba 1164
9abd68ef
JA		 1165 /*
1166 * Some drives have a bug that auto-enables WRRU if MEDIUM isn't
1167 * set. Since URGENT priority is zeroes, it makes all queues
1168 * URGENT.
1169 */
1170 if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ)
1171 flags |= NVME_SQ_PRIO_MEDIUM;
1172
d29ec824 1173 /*
16772ae6 1174 * Note: we (ab)use the fact that the prp fields survive if no data
d29ec824
CH		 1175 * is attached to the request.
1176 */
b60503ba
MW		 1177 memset(&c, 0, sizeof(c));
1178 c.create_sq.opcode = nvme_admin_create_sq;
1179 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1180 c.create_sq.sqid = cpu_to_le16(qid);
1181 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1182 c.create_sq.sq_flags = cpu_to_le16(flags);
1183 c.create_sq.cqid = cpu_to_le16(qid);
1184
1c63dc66 1185 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1186}
1187
1188static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1189{
1190 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1191}
1192
1193static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1194{
1195 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1196}
1197
2a842aca 1198static void abort_endio(struct request *req, blk_status_t error)
bc5fc7e4 1199{
f4800d6d
CH		 1200 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1201 struct nvme_queue *nvmeq = iod->nvmeq;
e44ac588 1202
27fa9bc5
CH		 1203 dev_warn(nvmeq->dev->ctrl.device,
1204 "Abort status: 0x%x", nvme_req(req)->status);
e7a2a87d 1205 atomic_inc(&nvmeq->dev->ctrl.abort_limit);
e7a2a87d 1206 blk_mq_free_request(req);
bc5fc7e4
MW		 1207}
1208
b2a0eb1a
KB		 1209static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1210{
b2a0eb1a
KB		 1211 /* If true, indicates loss of adapter communication, possibly by a
1212 * NVMe Subsystem reset.
1213 */
1214 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1215
ad70062c
JW		 1216 /* If there is a reset/reinit ongoing, we shouldn't reset again. */
1217 switch (dev->ctrl.state) {
1218 case NVME_CTRL_RESETTING:
ad6a0a52 1219 case NVME_CTRL_CONNECTING:
b2a0eb1a 1220 return false;
ad70062c
JW		 1221 default:
1222 break;
1223 }
b2a0eb1a
KB		 1224
1225 /* We shouldn't reset unless the controller is on fatal error state
1226 * _or_ if we lost the communication with it.
1227 */
1228 if (!(csts & NVME_CSTS_CFS) && !nssro)
1229 return false;
1230
b2a0eb1a
KB		 1231 return true;
1232}
1233
1234static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1235{
1236 /* Read a config register to help see what died. */
1237 u16 pci_status;
1238 int result;
1239
1240 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1241 &pci_status);
1242 if (result == PCIBIOS_SUCCESSFUL)
1243 dev_warn(dev->ctrl.device,
1244 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1245 csts, pci_status);
1246 else
1247 dev_warn(dev->ctrl.device,
1248 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1249 csts, result);
1250}
1251
31c7c7d2 1252static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
c30341dc 1253{
f4800d6d
CH		 1254 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1255 struct nvme_queue *nvmeq = iod->nvmeq;
c30341dc 1256 struct nvme_dev *dev = nvmeq->dev;
a4aea562 1257 struct request *abort_req;
a4aea562 1258 struct nvme_command cmd;
b2a0eb1a
KB		 1259 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1260
651438bb
WX		 1261 /* If PCI error recovery process is happening, we cannot reset or
1262 * the recovery mechanism will surely fail.
1263 */
1264 mb();
1265 if (pci_channel_offline(to_pci_dev(dev->dev)))
1266 return BLK_EH_RESET_TIMER;
1267
b2a0eb1a
KB		 1268 /*
1269 * Reset immediately if the controller is failed
1270 */
1271 if (nvme_should_reset(dev, csts)) {
1272 nvme_warn_reset(dev, csts);
1273 nvme_dev_disable(dev, false);
d86c4d8e 1274 nvme_reset_ctrl(&dev->ctrl);
db8c48e4 1275 return BLK_EH_DONE;
b2a0eb1a 1276 }
c30341dc 1277
7776db1c
KB		 1278 /*
1279 * Did we miss an interrupt?
1280 */
fa059b85
KB		 1281 if (test_bit(NVMEQ_POLLED, &nvmeq->flags))
1282 nvme_poll(req->mq_hctx);
1283 else
1284 nvme_poll_irqdisable(nvmeq);
1285
bf392a5d 1286 if (blk_mq_request_completed(req)) {
7776db1c
KB		 1287 dev_warn(dev->ctrl.device,
1288 "I/O %d QID %d timeout, completion polled\n",
1289 req->tag, nvmeq->qid);
db8c48e4 1290 return BLK_EH_DONE;
7776db1c
KB		 1291 }
1292
31c7c7d2 1293 /*
fd634f41
CH		 1294 * Shutdown immediately if controller times out while starting. The
1295 * reset work will see the pci device disabled when it gets the forced
1296 * cancellation error. All outstanding requests are completed on
db8c48e4 1297 * shutdown, so we return BLK_EH_DONE.
fd634f41 1298 */
4244140d
KB		 1299 switch (dev->ctrl.state) {
1300 case NVME_CTRL_CONNECTING:
2036f726 1301 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
df561f66 1302 fallthrough;
2036f726 1303 case NVME_CTRL_DELETING:
b9cac43c 1304 dev_warn_ratelimited(dev->ctrl.device,
fd634f41
CH		 1305 "I/O %d QID %d timeout, disable controller\n",
1306 req->tag, nvmeq->qid);
27fa9bc5 1307 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
7ad92f65 1308 nvme_dev_disable(dev, true);
db8c48e4 1309 return BLK_EH_DONE;
39a9dd81
KB		 1310 case NVME_CTRL_RESETTING:
1311 return BLK_EH_RESET_TIMER;
4244140d
KB		 1312 default:
1313 break;
c30341dc
KB		 1314 }
1315
fd634f41 1316 /*
ee0d96d3
BW		 1317 * Shutdown the controller immediately and schedule a reset if the
1318 * command was already aborted once before and still hasn't been
1319 * returned to the driver, or if this is the admin queue.
31c7c7d2 1320 */
f4800d6d 1321 if (!nvmeq->qid || iod->aborted) {
1b3c47c1 1322 dev_warn(dev->ctrl.device,
e1569a16
KB		 1323 "I/O %d QID %d timeout, reset controller\n",
1324 req->tag, nvmeq->qid);
7ad92f65 1325 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
a5cdb68c 1326 nvme_dev_disable(dev, false);
d86c4d8e 1327 nvme_reset_ctrl(&dev->ctrl);
c30341dc 1328
db8c48e4 1329 return BLK_EH_DONE;
c30341dc 1330 }
c30341dc 1331
e7a2a87d 1332 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
6bf25d16 1333 atomic_inc(&dev->ctrl.abort_limit);
31c7c7d2 1334 return BLK_EH_RESET_TIMER;
6bf25d16 1335 }
7bf7d778 1336 iod->aborted = 1;
a4aea562 1337
c30341dc
KB		 1338 memset(&cmd, 0, sizeof(cmd));
1339 cmd.abort.opcode = nvme_admin_abort_cmd;
a4aea562 1340 cmd.abort.cid = req->tag;
c30341dc 1341 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
c30341dc 1342
1b3c47c1
SG		 1343 dev_warn(nvmeq->dev->ctrl.device,
1344 "I/O %d QID %d timeout, aborting\n",
1345 req->tag, nvmeq->qid);
e7a2a87d
CH		 1346
1347 abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
39dfe844 1348 BLK_MQ_REQ_NOWAIT);
e7a2a87d
CH		 1349 if (IS_ERR(abort_req)) {
1350 atomic_inc(&dev->ctrl.abort_limit);
1351 return BLK_EH_RESET_TIMER;
1352 }
1353
e7a2a87d 1354 abort_req->end_io_data = NULL;
8eeed0b5 1355 blk_execute_rq_nowait(NULL, abort_req, 0, abort_endio);
c30341dc 1356
31c7c7d2
CH		 1357 /*
1358 * The aborted req will be completed on receiving the abort req.
1359 * We enable the timer again. If hit twice, it'll cause a device reset,
1360 * as the device then is in a faulty state.
1361 */
1362 return BLK_EH_RESET_TIMER;
c30341dc
KB		 1363}
1364
a4aea562
MB		 1365static void nvme_free_queue(struct nvme_queue *nvmeq)
1366{
8a1d09a6 1367 dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq),
9e866774 1368 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
63223078
CH		 1369 if (!nvmeq->sq_cmds)
1370 return;
0f238ff5 1371
63223078 1372 if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) {
88a041f4 1373 pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev),
8a1d09a6 1374 nvmeq->sq_cmds, SQ_SIZE(nvmeq));
63223078 1375 } else {
8a1d09a6 1376 dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq),
63223078 1377 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
0f238ff5 1378 }
9e866774
MW		 1379}
1380
a1a5ef99 1381static void nvme_free_queues(struct nvme_dev *dev, int lowest)
22404274
KB		 1382{
1383 int i;
1384
d858e5f0 1385 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
d858e5f0 1386 dev->ctrl.queue_count--;
147b27e4 1387 nvme_free_queue(&dev->queues[i]);
121c7ad4 1388 }
22404274
KB		 1389}
1390
4d115420
KB		 1391/**
1392 * nvme_suspend_queue - put queue into suspended state
40581d1a 1393 * @nvmeq: queue to suspend
4d115420
KB		 1394 */
1395static int nvme_suspend_queue(struct nvme_queue *nvmeq)
b60503ba 1396{
4e224106 1397 if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags))
2b25d981 1398 return 1;
a09115b2 1399
4e224106 1400 /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */
d1f06f4a 1401 mb();
a09115b2 1402
4e224106 1403 nvmeq->dev->online_queues--;
1c63dc66 1404 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
c81545f9 1405 blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q);
7c349dde
KB		 1406 if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags))
1407 pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq);
4d115420
KB		 1408 return 0;
1409}
b60503ba 1410
8fae268b
KB		 1411static void nvme_suspend_io_queues(struct nvme_dev *dev)
1412{
1413 int i;
1414
1415 for (i = dev->ctrl.queue_count - 1; i > 0; i--)
1416 nvme_suspend_queue(&dev->queues[i]);
1417}
1418
a5cdb68c 1419static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
4d115420 1420{
147b27e4 1421 struct nvme_queue *nvmeq = &dev->queues[0];
4d115420 1422
a5cdb68c
KB		 1423 if (shutdown)
1424 nvme_shutdown_ctrl(&dev->ctrl);
1425 else
b5b05048 1426 nvme_disable_ctrl(&dev->ctrl);
07836e65 1427
bf392a5d 1428 nvme_poll_irqdisable(nvmeq);
b60503ba
MW		 1429}
1430
fa46c6fb
KB		 1431/*
1432 * Called only on a device that has been disabled and after all other threads
9210c075
DZ		 1433 * that can check this device's completion queues have synced, except
1434 * nvme_poll(). This is the last chance for the driver to see a natural
1435 * completion before nvme_cancel_request() terminates all incomplete requests.
fa46c6fb
KB		 1436 */
1437static void nvme_reap_pending_cqes(struct nvme_dev *dev)
1438{
fa46c6fb
KB		 1439 int i;
1440
9210c075
DZ		 1441 for (i = dev->ctrl.queue_count - 1; i > 0; i--) {
1442 spin_lock(&dev->queues[i].cq_poll_lock);
324b494c 1443 nvme_process_cq(&dev->queues[i]);
9210c075
DZ		 1444 spin_unlock(&dev->queues[i].cq_poll_lock);
1445 }
fa46c6fb
KB		 1446}
1447
8ffaadf7
JD		 1448static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1449 int entry_size)
1450{
1451 int q_depth = dev->q_depth;
5fd4ce1b 1452 unsigned q_size_aligned = roundup(q_depth * entry_size,
6c3c05b0 1453 NVME_CTRL_PAGE_SIZE);
8ffaadf7
JD		 1454
1455 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
c45f5c99 1456 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
4e523547 1457
6c3c05b0 1458 mem_per_q = round_down(mem_per_q, NVME_CTRL_PAGE_SIZE);
c45f5c99 1459 q_depth = div_u64(mem_per_q, entry_size);
8ffaadf7
JD		 1460
1461 /*
1462 * Ensure the reduced q_depth is above some threshold where it
1463 * would be better to map queues in system memory with the
1464 * original depth
1465 */
1466 if (q_depth < 64)
1467 return -ENOMEM;
1468 }
1469
1470 return q_depth;
1471}
1472
1473static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
8a1d09a6 1474 int qid)
8ffaadf7 1475{
0f238ff5
LG		 1476 struct pci_dev *pdev = to_pci_dev(dev->dev);
1477
1478 if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
8a1d09a6 1479 nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq));
bfac8e9f
AM		 1480 if (nvmeq->sq_cmds) {
1481 nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev,
1482 nvmeq->sq_cmds);
1483 if (nvmeq->sq_dma_addr) {
1484 set_bit(NVMEQ_SQ_CMB, &nvmeq->flags);
1485 return 0;
1486 }
1487
8a1d09a6 1488 pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq));
63223078 1489 }
0f238ff5 1490 }
8ffaadf7 1491
8a1d09a6 1492 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq),
63223078 1493 &nvmeq->sq_dma_addr, GFP_KERNEL);
815c6704
KB		 1494 if (!nvmeq->sq_cmds)
1495 return -ENOMEM;
8ffaadf7
JD		 1496 return 0;
1497}
1498
a6ff7262 1499static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
b60503ba 1500{
147b27e4 1501 struct nvme_queue *nvmeq = &dev->queues[qid];
b60503ba 1502
62314e40
KB		 1503 if (dev->ctrl.queue_count > qid)
1504 return 0;
b60503ba 1505
c1e0cc7e 1506 nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES;
8a1d09a6
BH		 1507 nvmeq->q_depth = depth;
1508 nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq),
750afb08 1509 &nvmeq->cq_dma_addr, GFP_KERNEL);
b60503ba
MW		 1510 if (!nvmeq->cqes)
1511 goto free_nvmeq;
b60503ba 1512
8a1d09a6 1513 if (nvme_alloc_sq_cmds(dev, nvmeq, qid))
b60503ba
MW		 1514 goto free_cqdma;
1515
091b6092 1516 nvmeq->dev = dev;
1ab0cd69 1517 spin_lock_init(&nvmeq->sq_lock);
3a7afd8e 1518 spin_lock_init(&nvmeq->cq_poll_lock);
b60503ba 1519 nvmeq->cq_head = 0;
82123460 1520 nvmeq->cq_phase = 1;
b80d5ccc 1521 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
c30341dc 1522 nvmeq->qid = qid;
d858e5f0 1523 dev->ctrl.queue_count++;
36a7e993 1524
147b27e4 1525 return 0;
b60503ba
MW		 1526
1527 free_cqdma:
8a1d09a6
BH		 1528 dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes,
1529 nvmeq->cq_dma_addr);
b60503ba 1530 free_nvmeq:
147b27e4 1531 return -ENOMEM;
b60503ba
MW		 1532}
1533
dca51e78 1534static int queue_request_irq(struct nvme_queue *nvmeq)
3001082c 1535{
0ff199cb
CH		 1536 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1537 int nr = nvmeq->dev->ctrl.instance;
1538
1539 if (use_threaded_interrupts) {
1540 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1541 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1542 } else {
1543 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1544 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1545 }
3001082c
MW		 1546}
1547
22404274 1548static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
b60503ba 1549{
22404274 1550 struct nvme_dev *dev = nvmeq->dev;
b60503ba 1551
22404274 1552 nvmeq->sq_tail = 0;
38210800 1553 nvmeq->last_sq_tail = 0;
22404274
KB		 1554 nvmeq->cq_head = 0;
1555 nvmeq->cq_phase = 1;
b80d5ccc 1556 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
8a1d09a6 1557 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq));
f9f38e33 1558 nvme_dbbuf_init(dev, nvmeq, qid);
42f61420 1559 dev->online_queues++;
3a7afd8e 1560 wmb(); /* ensure the first interrupt sees the initialization */
22404274
KB		 1561}
1562
4b04cc6a 1563static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled)
22404274
KB		 1564{
1565 struct nvme_dev *dev = nvmeq->dev;
1566 int result;
7c349dde 1567 u16 vector = 0;
3f85d50b 1568
d1ed6aa1
CH		 1569 clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
1570
22b55601
KB		 1571 /*
1572 * A queue's vector matches the queue identifier unless the controller
1573 * has only one vector available.
1574 */
4b04cc6a
JA		 1575 if (!polled)
1576 vector = dev->num_vecs == 1 ? 0 : qid;
1577 else
7c349dde 1578 set_bit(NVMEQ_POLLED, &nvmeq->flags);
4b04cc6a 1579
a8e3e0bb 1580 result = adapter_alloc_cq(dev, qid, nvmeq, vector);
ded45505
KB		 1581 if (result)
1582 return result;
b60503ba
MW		 1583
1584 result = adapter_alloc_sq(dev, qid, nvmeq);
1585 if (result < 0)
ded45505 1586 return result;
c80b36cd 1587 if (result)
b60503ba
MW		 1588 goto release_cq;
1589
a8e3e0bb 1590 nvmeq->cq_vector = vector;
161b8be2 1591 nvme_init_queue(nvmeq, qid);
4b04cc6a 1592
7c349dde 1593 if (!polled) {
4b04cc6a
JA		 1594 result = queue_request_irq(nvmeq);
1595 if (result < 0)
1596 goto release_sq;
1597 }
b60503ba 1598
4e224106 1599 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
22404274 1600 return result;
b60503ba 1601
a8e3e0bb 1602release_sq:
f25a2dfc 1603 dev->online_queues--;
b60503ba 1604 adapter_delete_sq(dev, qid);
a8e3e0bb 1605release_cq:
b60503ba 1606 adapter_delete_cq(dev, qid);
22404274 1607 return result;
b60503ba
MW		 1608}
1609
f363b089 1610static const struct blk_mq_ops nvme_mq_admin_ops = {
d29ec824 1611 .queue_rq = nvme_queue_rq,
77f02a7a 1612 .complete = nvme_pci_complete_rq,
a4aea562 1613 .init_hctx = nvme_admin_init_hctx,
0350815a 1614 .init_request = nvme_init_request,
a4aea562
MB		 1615 .timeout = nvme_timeout,
1616};
1617
f363b089 1618static const struct blk_mq_ops nvme_mq_ops = {
376f7ef8
CH		 1619 .queue_rq = nvme_queue_rq,
1620 .complete = nvme_pci_complete_rq,
1621 .commit_rqs = nvme_commit_rqs,
1622 .init_hctx = nvme_init_hctx,
1623 .init_request = nvme_init_request,
1624 .map_queues = nvme_pci_map_queues,
1625 .timeout = nvme_timeout,
1626 .poll = nvme_poll,
dabcefab
JA		 1627};
1628
ea191d2f
KB		 1629static void nvme_dev_remove_admin(struct nvme_dev *dev)
1630{
1c63dc66 1631 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
69d9a99c
KB		 1632 /*
1633 * If the controller was reset during removal, it's possible
1634 * user requests may be waiting on a stopped queue. Start the
1635 * queue to flush these to completion.
1636 */
c81545f9 1637 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1c63dc66 1638 blk_cleanup_queue(dev->ctrl.admin_q);
ea191d2f
KB		 1639 blk_mq_free_tag_set(&dev->admin_tagset);
1640 }
1641}
1642
a4aea562
MB		 1643static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1644{
1c63dc66 1645 if (!dev->ctrl.admin_q) {
a4aea562
MB		 1646 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1647 dev->admin_tagset.nr_hw_queues = 1;
e3e9d50c 1648
38dabe21 1649 dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH;
dc96f938 1650 dev->admin_tagset.timeout = NVME_ADMIN_TIMEOUT;
d4ec47f1 1651 dev->admin_tagset.numa_node = dev->ctrl.numa_node;
d43f1ccf 1652 dev->admin_tagset.cmd_size = sizeof(struct nvme_iod);
d3484991 1653 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED;
a4aea562
MB		 1654 dev->admin_tagset.driver_data = dev;
1655
1656 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1657 return -ENOMEM;
34b6c231 1658 dev->ctrl.admin_tagset = &dev->admin_tagset;
a4aea562 1659
1c63dc66
CH		 1660 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1661 if (IS_ERR(dev->ctrl.admin_q)) {
a4aea562
MB		 1662 blk_mq_free_tag_set(&dev->admin_tagset);
1663 return -ENOMEM;
1664 }
1c63dc66 1665 if (!blk_get_queue(dev->ctrl.admin_q)) {
ea191d2f 1666 nvme_dev_remove_admin(dev);
1c63dc66 1667 dev->ctrl.admin_q = NULL;
ea191d2f
KB		 1668 return -ENODEV;
1669 }
0fb59cbc 1670 } else
c81545f9 1671 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
a4aea562
MB		 1672
1673 return 0;
1674}
1675
97f6ef64
XY		 1676static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1677{
1678 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1679}
1680
1681static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1682{
1683 struct pci_dev *pdev = to_pci_dev(dev->dev);
1684
1685 if (size <= dev->bar_mapped_size)
1686 return 0;
1687 if (size > pci_resource_len(pdev, 0))
1688 return -ENOMEM;
1689 if (dev->bar)
1690 iounmap(dev->bar);
1691 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1692 if (!dev->bar) {
1693 dev->bar_mapped_size = 0;
1694 return -ENOMEM;
1695 }
1696 dev->bar_mapped_size = size;
1697 dev->dbs = dev->bar + NVME_REG_DBS;
1698
1699 return 0;
1700}
1701
01ad0990 1702static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
b60503ba 1703{
ba47e386 1704 int result;
b60503ba
MW		 1705 u32 aqa;
1706 struct nvme_queue *nvmeq;
1707
97f6ef64
XY		 1708 result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1709 if (result < 0)
1710 return result;
1711
8ef2074d 1712 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
20d0dfe6 1713 NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
dfbac8c7 1714
7a67cbea
CH		 1715 if (dev->subsystem &&
1716 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1717 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
dfbac8c7 1718
b5b05048 1719 result = nvme_disable_ctrl(&dev->ctrl);
ba47e386
MW		 1720 if (result < 0)
1721 return result;
b60503ba 1722
a6ff7262 1723 result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
147b27e4
SG		 1724 if (result)
1725 return result;
b60503ba 1726
635333e4
MG		 1727 dev->ctrl.numa_node = dev_to_node(dev->dev);
1728
147b27e4 1729 nvmeq = &dev->queues[0];
b60503ba
MW		 1730 aqa = nvmeq->q_depth - 1;
1731 aqa |= aqa << 16;
1732
7a67cbea
CH		 1733 writel(aqa, dev->bar + NVME_REG_AQA);
1734 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1735 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
b60503ba 1736
c0f2f45b 1737 result = nvme_enable_ctrl(&dev->ctrl);
025c557a 1738 if (result)
d4875622 1739 return result;
a4aea562 1740
2b25d981 1741 nvmeq->cq_vector = 0;
161b8be2 1742 nvme_init_queue(nvmeq, 0);
dca51e78 1743 result = queue_request_irq(nvmeq);
758dd7fd 1744 if (result) {
7c349dde 1745 dev->online_queues--;
d4875622 1746 return result;
758dd7fd 1747 }
025c557a 1748
4e224106 1749 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
b60503ba
MW		 1750 return result;
1751}
1752
749941f2 1753static int nvme_create_io_queues(struct nvme_dev *dev)
42f61420 1754{
4b04cc6a 1755 unsigned i, max, rw_queues;
749941f2 1756 int ret = 0;
42f61420 1757
d858e5f0 1758 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
a6ff7262 1759 if (nvme_alloc_queue(dev, i, dev->q_depth)) {
749941f2 1760 ret = -ENOMEM;
42f61420 1761 break;
749941f2
CH		 1762 }
1763 }
42f61420 1764
d858e5f0 1765 max = min(dev->max_qid, dev->ctrl.queue_count - 1);
e20ba6e1
CH		 1766 if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) {
1767 rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] +
1768 dev->io_queues[HCTX_TYPE_READ];
4b04cc6a
JA		 1769 } else {
1770 rw_queues = max;
1771 }
1772
949928c1 1773 for (i = dev->online_queues; i <= max; i++) {
4b04cc6a
JA		 1774 bool polled = i > rw_queues;
1775
1776 ret = nvme_create_queue(&dev->queues[i], i, polled);
d4875622 1777 if (ret)
42f61420 1778 break;
27e8166c 1779 }
749941f2
CH		 1780
1781 /*
1782 * Ignore failing Create SQ/CQ commands, we can continue with less
8adb8c14
MI		 1783 * than the desired amount of queues, and even a controller without
1784 * I/O queues can still be used to issue admin commands. This might
749941f2
CH		 1785 * be useful to upgrade a buggy firmware for example.
1786 */
1787 return ret >= 0 ? 0 : ret;
b60503ba
MW		 1788}
1789
202021c1
SB		 1790static ssize_t nvme_cmb_show(struct device *dev,
1791 struct device_attribute *attr,
1792 char *buf)
1793{
1794 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
1795
c965809c 1796 return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n",
202021c1
SB		 1797 ndev->cmbloc, ndev->cmbsz);
1798}
1799static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL);
1800
88de4598 1801static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
8ffaadf7 1802{
88de4598
CH		 1803 u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
1804
1805 return 1ULL << (12 + 4 * szu);
1806}
1807
1808static u32 nvme_cmb_size(struct nvme_dev *dev)
1809{
1810 return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
1811}
1812
f65efd6d 1813static void nvme_map_cmb(struct nvme_dev *dev)
8ffaadf7 1814{
88de4598 1815 u64 size, offset;
8ffaadf7
JD		 1816 resource_size_t bar_size;
1817 struct pci_dev *pdev = to_pci_dev(dev->dev);
8969f1f8 1818 int bar;
8ffaadf7 1819
9fe5c59f
KB		 1820 if (dev->cmb_size)
1821 return;
1822
20d3bb92
KJ		 1823 if (NVME_CAP_CMBS(dev->ctrl.cap))
1824 writel(NVME_CMBMSC_CRE, dev->bar + NVME_REG_CMBMSC);
1825
7a67cbea 1826 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
f65efd6d
CH		 1827 if (!dev->cmbsz)
1828 return;
202021c1 1829 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
8ffaadf7 1830
88de4598
CH		 1831 size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
1832 offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
8969f1f8
CH		 1833 bar = NVME_CMB_BIR(dev->cmbloc);
1834 bar_size = pci_resource_len(pdev, bar);
8ffaadf7
JD		 1835
1836 if (offset > bar_size)
f65efd6d 1837 return;
8ffaadf7 1838
20d3bb92
KJ		 1839 /*
1840 * Tell the controller about the host side address mapping the CMB,
1841 * and enable CMB decoding for the NVMe 1.4+ scheme:
1842 */
1843 if (NVME_CAP_CMBS(dev->ctrl.cap)) {
1844 hi_lo_writeq(NVME_CMBMSC_CRE | NVME_CMBMSC_CMSE |
1845 (pci_bus_address(pdev, bar) + offset),
1846 dev->bar + NVME_REG_CMBMSC);
1847 }
1848
8ffaadf7
JD		 1849 /*
1850 * Controllers may support a CMB size larger than their BAR,
1851 * for example, due to being behind a bridge. Reduce the CMB to
1852 * the reported size of the BAR
1853 */
1854 if (size > bar_size - offset)
1855 size = bar_size - offset;
1856
0f238ff5
LG		 1857 if (pci_p2pdma_add_resource(pdev, bar, size, offset)) {
1858 dev_warn(dev->ctrl.device,
1859 "failed to register the CMB\n");
f65efd6d 1860 return;
0f238ff5
LG		 1861 }
1862
8ffaadf7 1863 dev->cmb_size = size;
0f238ff5
LG		 1864 dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS);
1865
1866 if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) ==
1867 (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS))
1868 pci_p2pmem_publish(pdev, true);
f65efd6d
CH		 1869
1870 if (sysfs_add_file_to_group(&dev->ctrl.device->kobj,
1871 &dev_attr_cmb.attr, NULL))
1872 dev_warn(dev->ctrl.device,
1873 "failed to add sysfs attribute for CMB\n");
8ffaadf7
JD		 1874}
1875
1876static inline void nvme_release_cmb(struct nvme_dev *dev)
1877{
0f238ff5 1878 if (dev->cmb_size) {
1c78f773
MG		 1879 sysfs_remove_file_from_group(&dev->ctrl.device->kobj,
1880 &dev_attr_cmb.attr, NULL);
0f238ff5 1881 dev->cmb_size = 0;
8ffaadf7
JD		 1882 }
1883}
1884
87ad72a5
CH		 1885static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1886{
6c3c05b0 1887 u32 host_mem_size = dev->host_mem_size >> NVME_CTRL_PAGE_SHIFT;
4033f35d 1888 u64 dma_addr = dev->host_mem_descs_dma;
87ad72a5 1889 struct nvme_command c;
87ad72a5
CH		 1890 int ret;
1891
87ad72a5
CH		 1892 memset(&c, 0, sizeof(c));
1893 c.features.opcode = nvme_admin_set_features;
1894 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1895 c.features.dword11 = cpu_to_le32(bits);
6c3c05b0 1896 c.features.dword12 = cpu_to_le32(host_mem_size);
87ad72a5
CH		 1897 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr));
1898 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr));
1899 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs);
1900
1901 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1902 if (ret) {
1903 dev_warn(dev->ctrl.device,
1904 "failed to set host mem (err %d, flags %#x).\n",
1905 ret, bits);
1906 }
87ad72a5
CH		 1907 return ret;
1908}
1909
1910static void nvme_free_host_mem(struct nvme_dev *dev)
1911{
1912 int i;
1913
1914 for (i = 0; i < dev->nr_host_mem_descs; i++) {
1915 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
6c3c05b0 1916 size_t size = le32_to_cpu(desc->size) * NVME_CTRL_PAGE_SIZE;
87ad72a5 1917
cc667f6d
LD		 1918 dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i],
1919 le64_to_cpu(desc->addr),
1920 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
87ad72a5
CH		 1921 }
1922
1923 kfree(dev->host_mem_desc_bufs);
1924 dev->host_mem_desc_bufs = NULL;
4033f35d
CH		 1925 dma_free_coherent(dev->dev,
1926 dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
1927 dev->host_mem_descs, dev->host_mem_descs_dma);
87ad72a5 1928 dev->host_mem_descs = NULL;
7e5dd57e 1929 dev->nr_host_mem_descs = 0;
87ad72a5
CH		 1930}
1931
92dc6895
CH		 1932static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
1933 u32 chunk_size)
9d713c2b 1934{
87ad72a5 1935 struct nvme_host_mem_buf_desc *descs;
92dc6895 1936 u32 max_entries, len;
4033f35d 1937 dma_addr_t descs_dma;
2ee0e4ed 1938 int i = 0;
87ad72a5 1939 void **bufs;
6fbcde66 1940 u64 size, tmp;
87ad72a5 1941
87ad72a5
CH		 1942 tmp = (preferred + chunk_size - 1);
1943 do_div(tmp, chunk_size);
1944 max_entries = tmp;
044a9df1
CH		 1945
1946 if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
1947 max_entries = dev->ctrl.hmmaxd;
1948
750afb08
LC		 1949 descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs),
1950 &descs_dma, GFP_KERNEL);
87ad72a5
CH		 1951 if (!descs)
1952 goto out;
1953
1954 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
1955 if (!bufs)
1956 goto out_free_descs;
1957
244a8fe4 1958 for (size = 0; size < preferred && i < max_entries; size += len) {
87ad72a5
CH		 1959 dma_addr_t dma_addr;
1960
50cdb7c6 1961 len = min_t(u64, chunk_size, preferred - size);
87ad72a5
CH		 1962 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
1963 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1964 if (!bufs[i])
1965 break;
1966
1967 descs[i].addr = cpu_to_le64(dma_addr);
6c3c05b0 1968 descs[i].size = cpu_to_le32(len / NVME_CTRL_PAGE_SIZE);
87ad72a5
CH		 1969 i++;
1970 }
1971
92dc6895 1972 if (!size)
87ad72a5 1973 goto out_free_bufs;
87ad72a5 1974
87ad72a5
CH		 1975 dev->nr_host_mem_descs = i;
1976 dev->host_mem_size = size;
1977 dev->host_mem_descs = descs;
4033f35d 1978 dev->host_mem_descs_dma = descs_dma;
87ad72a5
CH		 1979 dev->host_mem_desc_bufs = bufs;
1980 return 0;
1981
1982out_free_bufs:
1983 while (--i >= 0) {
6c3c05b0 1984 size_t size = le32_to_cpu(descs[i].size) * NVME_CTRL_PAGE_SIZE;
87ad72a5 1985
cc667f6d
LD		 1986 dma_free_attrs(dev->dev, size, bufs[i],
1987 le64_to_cpu(descs[i].addr),
1988 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
87ad72a5
CH		 1989 }
1990
1991 kfree(bufs);
1992out_free_descs:
4033f35d
CH		 1993 dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
1994 descs_dma);
87ad72a5 1995out:
87ad72a5
CH		 1996 dev->host_mem_descs = NULL;
1997 return -ENOMEM;
1998}
1999
92dc6895
CH		 2000static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
2001{
9dc54a0d
CK		 2002 u64 min_chunk = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
2003 u64 hmminds = max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
2004 u64 chunk_size;
92dc6895
CH		 2005
2006 /* start big and work our way down */
9dc54a0d 2007 for (chunk_size = min_chunk; chunk_size >= hmminds; chunk_size /= 2) {
92dc6895
CH		 2008 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
2009 if (!min || dev->host_mem_size >= min)
2010 return 0;
2011 nvme_free_host_mem(dev);
2012 }
2013 }
2014
2015 return -ENOMEM;
2016}
2017
9620cfba 2018static int nvme_setup_host_mem(struct nvme_dev *dev)
87ad72a5
CH		 2019{
2020 u64 max = (u64)max_host_mem_size_mb * SZ_1M;
2021 u64 preferred = (u64)dev->ctrl.hmpre * 4096;
2022 u64 min = (u64)dev->ctrl.hmmin * 4096;
2023 u32 enable_bits = NVME_HOST_MEM_ENABLE;
6fbcde66 2024 int ret;
87ad72a5
CH		 2025
2026 preferred = min(preferred, max);
2027 if (min > max) {
2028 dev_warn(dev->ctrl.device,
2029 "min host memory (%lld MiB) above limit (%d MiB).\n",
2030 min >> ilog2(SZ_1M), max_host_mem_size_mb);
2031 nvme_free_host_mem(dev);
9620cfba 2032 return 0;
87ad72a5
CH		 2033 }
2034
2035 /*
2036 * If we already have a buffer allocated check if we can reuse it.
2037 */
2038 if (dev->host_mem_descs) {
2039 if (dev->host_mem_size >= min)
2040 enable_bits |= NVME_HOST_MEM_RETURN;
2041 else
2042 nvme_free_host_mem(dev);
2043 }
2044
2045 if (!dev->host_mem_descs) {
92dc6895
CH		 2046 if (nvme_alloc_host_mem(dev, min, preferred)) {
2047 dev_warn(dev->ctrl.device,
2048 "failed to allocate host memory buffer.\n");
9620cfba 2049 return 0; /* controller must work without HMB */
92dc6895
CH		 2050 }
2051
2052 dev_info(dev->ctrl.device,
2053 "allocated %lld MiB host memory buffer.\n",
2054 dev->host_mem_size >> ilog2(SZ_1M));
87ad72a5
CH		 2055 }
2056
9620cfba
CH		 2057 ret = nvme_set_host_mem(dev, enable_bits);
2058 if (ret)
87ad72a5 2059 nvme_free_host_mem(dev);
9620cfba 2060 return ret;
9d713c2b
KB		 2061}
2062
612b7286
ML		 2063/*
2064 * nirqs is the number of interrupts available for write and read
2065 * queues. The core already reserved an interrupt for the admin queue.
2066 */
2067static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs)
3b6592f7 2068{
612b7286 2069 struct nvme_dev *dev = affd->priv;
2a5bcfdd 2070 unsigned int nr_read_queues, nr_write_queues = dev->nr_write_queues;
3b6592f7
JA		 2071
2072 /*
ee0d96d3 2073 * If there is no interrupt available for queues, ensure that
612b7286
ML		 2074 * the default queue is set to 1. The affinity set size is
2075 * also set to one, but the irq core ignores it for this case.
2076 *
2077 * If only one interrupt is available or 'write_queue' == 0, combine
2078 * write and read queues.
2079 *
2080 * If 'write_queues' > 0, ensure it leaves room for at least one read
2081 * queue.
3b6592f7 2082 */
612b7286
ML		 2083 if (!nrirqs) {
2084 nrirqs = 1;
2085 nr_read_queues = 0;
2a5bcfdd 2086 } else if (nrirqs == 1 || !nr_write_queues) {
612b7286 2087 nr_read_queues = 0;
2a5bcfdd 2088 } else if (nr_write_queues >= nrirqs) {
612b7286 2089 nr_read_queues = 1;
3b6592f7 2090 } else {
2a5bcfdd 2091 nr_read_queues = nrirqs - nr_write_queues;
3b6592f7 2092 }
612b7286
ML		 2093
2094 dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2095 affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2096 dev->io_queues[HCTX_TYPE_READ] = nr_read_queues;
2097 affd->set_size[HCTX_TYPE_READ] = nr_read_queues;
2098 affd->nr_sets = nr_read_queues ? 2 : 1;
3b6592f7
JA		 2099}
2100
6451fe73 2101static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues)
3b6592f7
JA		 2102{
2103 struct pci_dev *pdev = to_pci_dev(dev->dev);
3b6592f7 2104 struct irq_affinity affd = {
9cfef55b 2105 .pre_vectors = 1,
612b7286
ML		 2106 .calc_sets = nvme_calc_irq_sets,
2107 .priv = dev,
3b6592f7 2108 };
21cc2f3f 2109 unsigned int irq_queues, poll_queues;
6451fe73
JA		 2110
2111 /*
21cc2f3f
JX		 2112 * Poll queues don't need interrupts, but we need at least one I/O queue
2113 * left over for non-polled I/O.
6451fe73 2114 */
21cc2f3f
JX		 2115 poll_queues = min(dev->nr_poll_queues, nr_io_queues - 1);
2116 dev->io_queues[HCTX_TYPE_POLL] = poll_queues;
3b6592f7 2117
21cc2f3f
JX		 2118 /*
2119 * Initialize for the single interrupt case, will be updated in
2120 * nvme_calc_irq_sets().
2121 */
612b7286
ML		 2122 dev->io_queues[HCTX_TYPE_DEFAULT] = 1;
2123 dev->io_queues[HCTX_TYPE_READ] = 0;
3b6592f7 2124
66341331 2125 /*
21cc2f3f
JX		 2126 * We need interrupts for the admin queue and each non-polled I/O queue,
2127 * but some Apple controllers require all queues to use the first
2128 * vector.
66341331 2129 */
21cc2f3f
JX		 2130 irq_queues = 1;
2131 if (!(dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR))
2132 irq_queues += (nr_io_queues - poll_queues);
612b7286
ML		 2133 return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues,
2134 PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd);
3b6592f7
JA		 2135}
2136
8fae268b
KB		 2137static void nvme_disable_io_queues(struct nvme_dev *dev)
2138{
2139 if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq))
2140 __nvme_disable_io_queues(dev, nvme_admin_delete_cq);
2141}
2142
2a5bcfdd
WZ		 2143static unsigned int nvme_max_io_queues(struct nvme_dev *dev)
2144{
e3aef095
NS		 2145 /*
2146 * If tags are shared with admin queue (Apple bug), then
2147 * make sure we only use one IO queue.
2148 */
2149 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2150 return 1;
2a5bcfdd
WZ		 2151 return num_possible_cpus() + dev->nr_write_queues + dev->nr_poll_queues;
2152}
2153
8d85fce7 2154static int nvme_setup_io_queues(struct nvme_dev *dev)
b60503ba 2155{
147b27e4 2156 struct nvme_queue *adminq = &dev->queues[0];
e75ec752 2157 struct pci_dev *pdev = to_pci_dev(dev->dev);
2a5bcfdd 2158 unsigned int nr_io_queues;
97f6ef64 2159 unsigned long size;
2a5bcfdd 2160 int result;
b60503ba 2161
2a5bcfdd
WZ		 2162 /*
2163 * Sample the module parameters once at reset time so that we have
2164 * stable values to work with.
2165 */
2166 dev->nr_write_queues = write_queues;
2167 dev->nr_poll_queues = poll_queues;
d38e9f04 2168
e3aef095 2169 nr_io_queues = dev->nr_allocated_queues - 1;
9a0be7ab
CH		 2170 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
2171 if (result < 0)
1b23484b 2172 return result;
9a0be7ab 2173
f5fa90dc 2174 if (nr_io_queues == 0)
a5229050 2175 return 0;
53dc180e 2176
4e224106 2177 clear_bit(NVMEQ_ENABLED, &adminq->flags);
b60503ba 2178
0f238ff5 2179 if (dev->cmb_use_sqes) {
8ffaadf7
JD		 2180 result = nvme_cmb_qdepth(dev, nr_io_queues,
2181 sizeof(struct nvme_command));
2182 if (result > 0)
2183 dev->q_depth = result;
2184 else
0f238ff5 2185 dev->cmb_use_sqes = false;
8ffaadf7
JD		 2186 }
2187
97f6ef64
XY		 2188 do {
2189 size = db_bar_size(dev, nr_io_queues);
2190 result = nvme_remap_bar(dev, size);
2191 if (!result)
2192 break;
2193 if (!--nr_io_queues)
2194 return -ENOMEM;
2195 } while (1);
2196 adminq->q_db = dev->dbs;
f1938f6e 2197
8fae268b 2198 retry:
9d713c2b 2199 /* Deregister the admin queue's interrupt */
0ff199cb 2200 pci_free_irq(pdev, 0, adminq);
9d713c2b 2201
e32efbfc
JA		 2202 /*
2203 * If we enable msix early due to not intx, disable it again before
2204 * setting up the full range we need.
2205 */
dca51e78 2206 pci_free_irq_vectors(pdev);
3b6592f7
JA		 2207
2208 result = nvme_setup_irqs(dev, nr_io_queues);
22b55601 2209 if (result <= 0)
dca51e78 2210 return -EIO;
3b6592f7 2211
22b55601 2212 dev->num_vecs = result;
4b04cc6a 2213 result = max(result - 1, 1);
e20ba6e1 2214 dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL];
fa08a396 2215
063a8096
MW		 2216 /*
2217 * Should investigate if there's a performance win from allocating
2218 * more queues than interrupt vectors; it might allow the submission
2219 * path to scale better, even if the receive path is limited by the
2220 * number of interrupts.
2221 */
dca51e78 2222 result = queue_request_irq(adminq);
7c349dde 2223 if (result)
d4875622 2224 return result;
4e224106 2225 set_bit(NVMEQ_ENABLED, &adminq->flags);
8fae268b
KB		 2226
2227 result = nvme_create_io_queues(dev);
2228 if (result || dev->online_queues < 2)
2229 return result;
2230
2231 if (dev->online_queues - 1 < dev->max_qid) {
2232 nr_io_queues = dev->online_queues - 1;
2233 nvme_disable_io_queues(dev);
2234 nvme_suspend_io_queues(dev);
2235 goto retry;
2236 }
2237 dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n",
2238 dev->io_queues[HCTX_TYPE_DEFAULT],
2239 dev->io_queues[HCTX_TYPE_READ],
2240 dev->io_queues[HCTX_TYPE_POLL]);
2241 return 0;
b60503ba
MW		 2242}
2243
2a842aca 2244static void nvme_del_queue_end(struct request *req, blk_status_t error)
a5768aa8 2245{
db3cbfff 2246 struct nvme_queue *nvmeq = req->end_io_data;
b5875222 2247
db3cbfff 2248 blk_mq_free_request(req);
d1ed6aa1 2249 complete(&nvmeq->delete_done);
a5768aa8
KB		 2250}
2251
2a842aca 2252static void nvme_del_cq_end(struct request *req, blk_status_t error)
a5768aa8 2253{
db3cbfff 2254 struct nvme_queue *nvmeq = req->end_io_data;
a5768aa8 2255
d1ed6aa1
CH		 2256 if (error)
2257 set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
db3cbfff
KB		 2258
2259 nvme_del_queue_end(req, error);
a5768aa8
KB		 2260}
2261
db3cbfff 2262static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
bda4e0fb 2263{
db3cbfff
KB		 2264 struct request_queue *q = nvmeq->dev->ctrl.admin_q;
2265 struct request *req;
2266 struct nvme_command cmd;
bda4e0fb 2267
db3cbfff
KB		 2268 memset(&cmd, 0, sizeof(cmd));
2269 cmd.delete_queue.opcode = opcode;
2270 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
bda4e0fb 2271
39dfe844 2272 req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT);
db3cbfff
KB		 2273 if (IS_ERR(req))
2274 return PTR_ERR(req);
bda4e0fb 2275
db3cbfff
KB		 2276 req->end_io_data = nvmeq;
2277
d1ed6aa1 2278 init_completion(&nvmeq->delete_done);
8eeed0b5 2279 blk_execute_rq_nowait(NULL, req, false,
db3cbfff
KB		 2280 opcode == nvme_admin_delete_cq ?
2281 nvme_del_cq_end : nvme_del_queue_end);
2282 return 0;
bda4e0fb
KB		 2283}
2284
8fae268b 2285static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode)
a5768aa8 2286{
5271edd4 2287 int nr_queues = dev->online_queues - 1, sent = 0;
db3cbfff 2288 unsigned long timeout;
a5768aa8 2289
db3cbfff 2290 retry:
dc96f938 2291 timeout = NVME_ADMIN_TIMEOUT;
5271edd4
CH		 2292 while (nr_queues > 0) {
2293 if (nvme_delete_queue(&dev->queues[nr_queues], opcode))
2294 break;
2295 nr_queues--;
2296 sent++;
db3cbfff 2297 }
d1ed6aa1
CH		 2298 while (sent) {
2299 struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent];
2300
2301 timeout = wait_for_completion_io_timeout(&nvmeq->delete_done,
5271edd4
CH		 2302 timeout);
2303 if (timeout == 0)
2304 return false;
d1ed6aa1 2305
d1ed6aa1 2306 sent--;
5271edd4
CH		 2307 if (nr_queues)
2308 goto retry;
2309 }
2310 return true;
a5768aa8
KB		 2311}
2312
5d02a5c1 2313static void nvme_dev_add(struct nvme_dev *dev)
b60503ba 2314{
2b1b7e78
JW		 2315 int ret;
2316
5bae7f73 2317 if (!dev->ctrl.tagset) {
376f7ef8 2318 dev->tagset.ops = &nvme_mq_ops;
ffe7704d 2319 dev->tagset.nr_hw_queues = dev->online_queues - 1;
8fe34be1 2320 dev->tagset.nr_maps = 2; /* default + read */
ed92ad37
CH		 2321 if (dev->io_queues[HCTX_TYPE_POLL])
2322 dev->tagset.nr_maps++;
ffe7704d 2323 dev->tagset.timeout = NVME_IO_TIMEOUT;
d4ec47f1 2324 dev->tagset.numa_node = dev->ctrl.numa_node;
61f3b896
CK		 2325 dev->tagset.queue_depth = min_t(unsigned int, dev->q_depth,
2326 BLK_MQ_MAX_DEPTH) - 1;
d43f1ccf 2327 dev->tagset.cmd_size = sizeof(struct nvme_iod);
ffe7704d
KB		 2328 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2329 dev->tagset.driver_data = dev;
b60503ba 2330
d38e9f04
BH		 2331 /*
2332 * Some Apple controllers requires tags to be unique
2333 * across admin and IO queue, so reserve the first 32
2334 * tags of the IO queue.
2335 */
2336 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2337 dev->tagset.reserved_tags = NVME_AQ_DEPTH;
2338
2b1b7e78
JW		 2339 ret = blk_mq_alloc_tag_set(&dev->tagset);
2340 if (ret) {
2341 dev_warn(dev->ctrl.device,
2342 "IO queues tagset allocation failed %d\n", ret);
5d02a5c1 2343 return;
2b1b7e78 2344 }
5bae7f73 2345 dev->ctrl.tagset = &dev->tagset;
949928c1
KB		 2346 } else {
2347 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2348
2349 /* Free previously allocated queues that are no longer usable */
2350 nvme_free_queues(dev, dev->online_queues);
ffe7704d 2351 }
949928c1 2352
e8fd41bb 2353 nvme_dbbuf_set(dev);
b60503ba
MW		 2354}
2355
b00a726a 2356static int nvme_pci_enable(struct nvme_dev *dev)
0877cb0d 2357{
b00a726a 2358 int result = -ENOMEM;
e75ec752 2359 struct pci_dev *pdev = to_pci_dev(dev->dev);
4bdf2603 2360 int dma_address_bits = 64;
0877cb0d
KB		 2361
2362 if (pci_enable_device_mem(pdev))
2363 return result;
2364
0877cb0d 2365 pci_set_master(pdev);
0877cb0d 2366
4bdf2603
FS		 2367 if (dev->ctrl.quirks & NVME_QUIRK_DMA_ADDRESS_BITS_48)
2368 dma_address_bits = 48;
2369 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(dma_address_bits)))
052d0efa 2370 goto disable;
0877cb0d 2371
7a67cbea 2372 if (readl(dev->bar + NVME_REG_CSTS) == -1) {
0e53d180 2373 result = -ENODEV;
b00a726a 2374 goto disable;
0e53d180 2375 }
e32efbfc
JA		 2376
2377 /*
a5229050
KB		 2378 * Some devices and/or platforms don't advertise or work with INTx
2379 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2380 * adjust this later.
e32efbfc 2381 */
dca51e78
CH		 2382 result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
2383 if (result < 0)
2384 return result;
e32efbfc 2385
20d0dfe6 2386 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
7a67cbea 2387
7442ddce 2388 dev->q_depth = min_t(u32, NVME_CAP_MQES(dev->ctrl.cap) + 1,
b27c1e68 2389 io_queue_depth);
aa22c8e6 2390 dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */
20d0dfe6 2391 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
7a67cbea 2392 dev->dbs = dev->bar + 4096;
1f390c1f 2393
66341331
BH		 2394 /*
2395 * Some Apple controllers require a non-standard SQE size.
2396 * Interestingly they also seem to ignore the CC:IOSQES register
2397 * so we don't bother updating it here.
2398 */
2399 if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES)
2400 dev->io_sqes = 7;
2401 else
2402 dev->io_sqes = NVME_NVM_IOSQES;
1f390c1f
SG		 2403
2404 /*
2405 * Temporary fix for the Apple controller found in the MacBook8,1 and
2406 * some MacBook7,1 to avoid controller resets and data loss.
2407 */
2408 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
2409 dev->q_depth = 2;
9bdcfb10
CH		 2410 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
2411 "set queue depth=%u to work around controller resets\n",
1f390c1f 2412 dev->q_depth);
d554b5e1
MP		 2413 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2414 (pdev->device == 0xa821 || pdev->device == 0xa822) &&
20d0dfe6 2415 NVME_CAP_MQES(dev->ctrl.cap) == 0) {
d554b5e1
MP		 2416 dev->q_depth = 64;
2417 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2418 "set queue depth=%u\n", dev->q_depth);
1f390c1f
SG		 2419 }
2420
d38e9f04
BH		 2421 /*
2422 * Controllers with the shared tags quirk need the IO queue to be
2423 * big enough so that we get 32 tags for the admin queue
2424 */
2425 if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) &&
2426 (dev->q_depth < (NVME_AQ_DEPTH + 2))) {
2427 dev->q_depth = NVME_AQ_DEPTH + 2;
2428 dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n",
2429 dev->q_depth);
2430 }
2431
2432
f65efd6d 2433 nvme_map_cmb(dev);
202021c1 2434
a0a3408e
KB		 2435 pci_enable_pcie_error_reporting(pdev);
2436 pci_save_state(pdev);
0877cb0d
KB		 2437 return 0;
2438
2439 disable:
0877cb0d
KB		 2440 pci_disable_device(pdev);
2441 return result;
2442}
2443
2444static void nvme_dev_unmap(struct nvme_dev *dev)
b00a726a
KB		 2445{
2446 if (dev->bar)
2447 iounmap(dev->bar);
a1f447b3 2448 pci_release_mem_regions(to_pci_dev(dev->dev));
b00a726a
KB		 2449}
2450
2451static void nvme_pci_disable(struct nvme_dev *dev)
0877cb0d 2452{
e75ec752
CH		 2453 struct pci_dev *pdev = to_pci_dev(dev->dev);
2454
dca51e78 2455 pci_free_irq_vectors(pdev);
0877cb0d 2456
a0a3408e
KB		 2457 if (pci_is_enabled(pdev)) {
2458 pci_disable_pcie_error_reporting(pdev);
e75ec752 2459 pci_disable_device(pdev);
4d115420 2460 }
4d115420
KB		 2461}
2462
a5cdb68c 2463static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
b60503ba 2464{
e43269e6 2465 bool dead = true, freeze = false;
302ad8cc 2466 struct pci_dev *pdev = to_pci_dev(dev->dev);
22404274 2467
77bf25ea 2468 mutex_lock(&dev->shutdown_lock);
302ad8cc
KB		 2469 if (pci_is_enabled(pdev)) {
2470 u32 csts = readl(dev->bar + NVME_REG_CSTS);
2471
ebef7368 2472 if (dev->ctrl.state == NVME_CTRL_LIVE ||
e43269e6
KB		 2473 dev->ctrl.state == NVME_CTRL_RESETTING) {
2474 freeze = true;
302ad8cc 2475 nvme_start_freeze(&dev->ctrl);
e43269e6 2476 }
302ad8cc
KB		 2477 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
2478 pdev->error_state != pci_channel_io_normal);
c9d3bf88 2479 }
c21377f8 2480
302ad8cc
KB		 2481 /*
2482 * Give the controller a chance to complete all entered requests if
2483 * doing a safe shutdown.
2484 */
e43269e6
KB		 2485 if (!dead && shutdown && freeze)
2486 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
9a915a5b
JW		 2487
2488 nvme_stop_queues(&dev->ctrl);
87ad72a5 2489
64ee0ac0 2490 if (!dead && dev->ctrl.queue_count > 0) {
8fae268b 2491 nvme_disable_io_queues(dev);
a5cdb68c 2492 nvme_disable_admin_queue(dev, shutdown);
4d115420 2493 }
8fae268b
KB		 2494 nvme_suspend_io_queues(dev);
2495 nvme_suspend_queue(&dev->queues[0]);
b00a726a 2496 nvme_pci_disable(dev);
fa46c6fb 2497 nvme_reap_pending_cqes(dev);
07836e65 2498
e1958e65
ML		 2499 blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
2500 blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
622b8b68
ML		 2501 blk_mq_tagset_wait_completed_request(&dev->tagset);
2502 blk_mq_tagset_wait_completed_request(&dev->admin_tagset);
302ad8cc
KB		 2503
2504 /*
2505 * The driver will not be starting up queues again if shutting down so
2506 * must flush all entered requests to their failed completion to avoid
2507 * deadlocking blk-mq hot-cpu notifier.
2508 */
c8e9e9b7 2509 if (shutdown) {
302ad8cc 2510 nvme_start_queues(&dev->ctrl);
c8e9e9b7
KB		 2511 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q))
2512 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
2513 }
77bf25ea 2514 mutex_unlock(&dev->shutdown_lock);
b60503ba
MW		 2515}
2516
c1ac9a4b
KB		 2517static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown)
2518{
2519 if (!nvme_wait_reset(&dev->ctrl))
2520 return -EBUSY;
2521 nvme_dev_disable(dev, shutdown);
2522 return 0;
2523}
2524
091b6092
MW		 2525static int nvme_setup_prp_pools(struct nvme_dev *dev)
2526{
e75ec752 2527 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
c61b82c7
CH		 2528 NVME_CTRL_PAGE_SIZE,
2529 NVME_CTRL_PAGE_SIZE, 0);
091b6092
MW		 2530 if (!dev->prp_page_pool)
2531 return -ENOMEM;
2532
99802a7a 2533 /* Optimisation for I/Os between 4k and 128k */
e75ec752 2534 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
99802a7a
MW		 2535 256, 256, 0);
2536 if (!dev->prp_small_pool) {
2537 dma_pool_destroy(dev->prp_page_pool);
2538 return -ENOMEM;
2539 }
091b6092
MW		 2540 return 0;
2541}
2542
2543static void nvme_release_prp_pools(struct nvme_dev *dev)
2544{
2545 dma_pool_destroy(dev->prp_page_pool);
99802a7a 2546 dma_pool_destroy(dev->prp_small_pool);
091b6092
MW		 2547}
2548
770597ec
KB		 2549static void nvme_free_tagset(struct nvme_dev *dev)
2550{
2551 if (dev->tagset.tags)
2552 blk_mq_free_tag_set(&dev->tagset);
2553 dev->ctrl.tagset = NULL;
2554}
2555
1673f1f0 2556static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
5e82e952 2557{
1673f1f0 2558 struct nvme_dev *dev = to_nvme_dev(ctrl);
9ac27090 2559
f9f38e33 2560 nvme_dbbuf_dma_free(dev);
770597ec 2561 nvme_free_tagset(dev);
1c63dc66
CH		 2562 if (dev->ctrl.admin_q)
2563 blk_put_queue(dev->ctrl.admin_q);
e286bcfc 2564 free_opal_dev(dev->ctrl.opal_dev);
943e942e 2565 mempool_destroy(dev->iod_mempool);
253fd4ac
IR		 2566 put_device(dev->dev);
2567 kfree(dev->queues);
5e82e952
KB		 2568 kfree(dev);
2569}
2570
7c1ce408 2571static void nvme_remove_dead_ctrl(struct nvme_dev *dev)
f58944e2 2572{
c1ac9a4b
KB		 2573 /*
2574 * Set state to deleting now to avoid blocking nvme_wait_reset(), which
2575 * may be holding this pci_dev's device lock.
2576 */
2577 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
d22524a4 2578 nvme_get_ctrl(&dev->ctrl);
69d9a99c 2579 nvme_dev_disable(dev, false);
9f9cafc1 2580 nvme_kill_queues(&dev->ctrl);
03e0f3a6 2581 if (!queue_work(nvme_wq, &dev->remove_work))
f58944e2
KB		 2582 nvme_put_ctrl(&dev->ctrl);
2583}
2584
fd634f41 2585static void nvme_reset_work(struct work_struct *work)
5e82e952 2586{
d86c4d8e
CH		 2587 struct nvme_dev *dev =
2588 container_of(work, struct nvme_dev, ctrl.reset_work);
a98e58e5 2589 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
e71afda4 2590 int result;
5e82e952 2591
e71afda4
CK		 2592 if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING)) {
2593 result = -ENODEV;
fd634f41 2594 goto out;
e71afda4 2595 }
5e82e952 2596
fd634f41
CH		 2597 /*
2598 * If we're called to reset a live controller first shut it down before
2599 * moving on.
2600 */
b00a726a 2601 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
a5cdb68c 2602 nvme_dev_disable(dev, false);
d6135c3a 2603 nvme_sync_queues(&dev->ctrl);
5e82e952 2604
5c959d73 2605 mutex_lock(&dev->shutdown_lock);
b00a726a 2606 result = nvme_pci_enable(dev);
f0b50732 2607 if (result)
4726bcf3 2608 goto out_unlock;
f0b50732 2609
01ad0990 2610 result = nvme_pci_configure_admin_queue(dev);
f0b50732 2611 if (result)
4726bcf3 2612 goto out_unlock;
f0b50732 2613
0fb59cbc
KB		 2614 result = nvme_alloc_admin_tags(dev);
2615 if (result)
4726bcf3 2616 goto out_unlock;
b9afca3e 2617
943e942e
JA		 2618 /*
2619 * Limit the max command size to prevent iod->sg allocations going
2620 * over a single page.
2621 */
7637de31
CH		 2622 dev->ctrl.max_hw_sectors = min_t(u32,
2623 NVME_MAX_KB_SZ << 1, dma_max_mapping_size(dev->dev) >> 9);
943e942e 2624 dev->ctrl.max_segments = NVME_MAX_SEGS;
a48bc520
CH		 2625
2626 /*
2627 * Don't limit the IOMMU merged segment size.
2628 */
2629 dma_set_max_seg_size(dev->dev, 0xffffffff);
3d2d861e 2630 dma_set_min_align_mask(dev->dev, NVME_CTRL_PAGE_SIZE - 1);
a48bc520 2631
5c959d73
KB		 2632 mutex_unlock(&dev->shutdown_lock);
2633
2634 /*
2635 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
2636 * initializing procedure here.
2637 */
2638 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
2639 dev_warn(dev->ctrl.device,
2640 "failed to mark controller CONNECTING\n");
cee6c269 2641 result = -EBUSY;
5c959d73
KB		 2642 goto out;
2643 }
943e942e 2644
95093350
MG		 2645 /*
2646 * We do not support an SGL for metadata (yet), so we are limited to a
2647 * single integrity segment for the separate metadata pointer.
2648 */
2649 dev->ctrl.max_integrity_segments = 1;
2650
f21c4769 2651 result = nvme_init_ctrl_finish(&dev->ctrl);
ce4541f4 2652 if (result)
f58944e2 2653 goto out;
ce4541f4 2654
e286bcfc
SB		 2655 if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
2656 if (!dev->ctrl.opal_dev)
2657 dev->ctrl.opal_dev =
2658 init_opal_dev(&dev->ctrl, &nvme_sec_submit);
2659 else if (was_suspend)
2660 opal_unlock_from_suspend(dev->ctrl.opal_dev);
2661 } else {
2662 free_opal_dev(dev->ctrl.opal_dev);
2663 dev->ctrl.opal_dev = NULL;
4f1244c8 2664 }
a98e58e5 2665
f9f38e33
HK		 2666 if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) {
2667 result = nvme_dbbuf_dma_alloc(dev);
2668 if (result)
2669 dev_warn(dev->dev,
2670 "unable to allocate dma for dbbuf\n");
2671 }
2672
9620cfba
CH		 2673 if (dev->ctrl.hmpre) {
2674 result = nvme_setup_host_mem(dev);
2675 if (result < 0)
2676 goto out;
2677 }
87ad72a5 2678
f0b50732 2679 result = nvme_setup_io_queues(dev);
badc34d4 2680 if (result)
f58944e2 2681 goto out;
f0b50732 2682
2659e57b
CH		 2683 /*
2684 * Keep the controller around but remove all namespaces if we don't have
2685 * any working I/O queue.
2686 */
3cf519b5 2687 if (dev->online_queues < 2) {
1b3c47c1 2688 dev_warn(dev->ctrl.device, "IO queues not created\n");
3b24774e 2689 nvme_kill_queues(&dev->ctrl);
5bae7f73 2690 nvme_remove_namespaces(&dev->ctrl);
770597ec 2691 nvme_free_tagset(dev);
3cf519b5 2692 } else {
25646264 2693 nvme_start_queues(&dev->ctrl);
302ad8cc 2694 nvme_wait_freeze(&dev->ctrl);
5d02a5c1 2695 nvme_dev_add(dev);
302ad8cc 2696 nvme_unfreeze(&dev->ctrl);
3cf519b5
CH		 2697 }
2698
2b1b7e78
JW		 2699 /*
2700 * If only admin queue live, keep it to do further investigation or
2701 * recovery.
2702 */
5d02a5c1 2703 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
2b1b7e78 2704 dev_warn(dev->ctrl.device,
5d02a5c1 2705 "failed to mark controller live state\n");
e71afda4 2706 result = -ENODEV;
bb8d261e
CH		 2707 goto out;
2708 }
92911a55 2709
d09f2b45 2710 nvme_start_ctrl(&dev->ctrl);
3cf519b5 2711 return;
f0b50732 2712
4726bcf3
KB		 2713 out_unlock:
2714 mutex_unlock(&dev->shutdown_lock);
3cf519b5 2715 out:
7c1ce408
CK		 2716 if (result)
2717 dev_warn(dev->ctrl.device,
2718 "Removing after probe failure status: %d\n", result);
2719 nvme_remove_dead_ctrl(dev);
f0b50732
KB		 2720}
2721
5c8809e6 2722static void nvme_remove_dead_ctrl_work(struct work_struct *work)
9a6b9458 2723{
5c8809e6 2724 struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
e75ec752 2725 struct pci_dev *pdev = to_pci_dev(dev->dev);
9a6b9458
KB		 2726
2727 if (pci_get_drvdata(pdev))
921920ab 2728 device_release_driver(&pdev->dev);
1673f1f0 2729 nvme_put_ctrl(&dev->ctrl);
9a6b9458
KB		 2730}
2731
1c63dc66 2732static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
9ca97374 2733{
1c63dc66 2734 *val = readl(to_nvme_dev(ctrl)->bar + off);
90667892 2735 return 0;
9ca97374
TH		 2736}
2737
5fd4ce1b 2738static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
4cc06521 2739{
5fd4ce1b
CH		 2740 writel(val, to_nvme_dev(ctrl)->bar + off);
2741 return 0;
2742}
4cc06521 2743
7fd8930f
CH		 2744static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2745{
3a8ecc93 2746 *val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off);
7fd8930f 2747 return 0;
4cc06521
KB		 2748}
2749
97c12223
KB		 2750static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
2751{
2752 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2753
2db24e4a 2754 return snprintf(buf, size, "%s\n", dev_name(&pdev->dev));
97c12223
KB		 2755}
2756
1c63dc66 2757static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
1a353d85 2758 .name = "pcie",
e439bb12 2759 .module = THIS_MODULE,
e0596ab2
LG		 2760 .flags = NVME_F_METADATA_SUPPORTED |
2761 NVME_F_PCI_P2PDMA,
1c63dc66 2762 .reg_read32 = nvme_pci_reg_read32,
5fd4ce1b 2763 .reg_write32 = nvme_pci_reg_write32,
7fd8930f 2764 .reg_read64 = nvme_pci_reg_read64,
1673f1f0 2765 .free_ctrl = nvme_pci_free_ctrl,
f866fc42 2766 .submit_async_event = nvme_pci_submit_async_event,
97c12223 2767 .get_address = nvme_pci_get_address,
1c63dc66 2768};
4cc06521 2769
b00a726a
KB		 2770static int nvme_dev_map(struct nvme_dev *dev)
2771{
b00a726a
KB		 2772 struct pci_dev *pdev = to_pci_dev(dev->dev);
2773
a1f447b3 2774 if (pci_request_mem_regions(pdev, "nvme"))
b00a726a
KB		 2775 return -ENODEV;
2776
97f6ef64 2777 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
b00a726a
KB		 2778 goto release;
2779
9fa196e7 2780 return 0;
b00a726a 2781 release:
9fa196e7
MG		 2782 pci_release_mem_regions(pdev);
2783 return -ENODEV;
b00a726a
KB		 2784}
2785
8427bbc2 2786static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
ff5350a8
AL		 2787{
2788 if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
2789 /*
2790 * Several Samsung devices seem to drop off the PCIe bus
2791 * randomly when APST is on and uses the deepest sleep state.
2792 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2793 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2794 * 950 PRO 256GB", but it seems to be restricted to two Dell
2795 * laptops.
2796 */
2797 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
2798 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
2799 dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
2800 return NVME_QUIRK_NO_DEEPEST_PS;
8427bbc2
KHF		 2801 } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
2802 /*
2803 * Samsung SSD 960 EVO drops off the PCIe bus after system
467c77d4
JJ		 2804 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
2805 * within few minutes after bootup on a Coffee Lake board -
2806 * ASUS PRIME Z370-A
8427bbc2
KHF		 2807 */
2808 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
467c77d4
JJ		 2809 (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") ||
2810 dmi_match(DMI_BOARD_NAME, "PRIME Z370-A")))
8427bbc2 2811 return NVME_QUIRK_NO_APST;
1fae37ac
S		 2812 } else if ((pdev->vendor == 0x144d && (pdev->device == 0xa801 ||
2813 pdev->device == 0xa808 || pdev->device == 0xa809)) ||
2814 (pdev->vendor == 0x1e0f && pdev->device == 0x0001)) {
2815 /*
2816 * Forcing to use host managed nvme power settings for
2817 * lowest idle power with quick resume latency on
2818 * Samsung and Toshiba SSDs based on suspend behavior
2819 * on Coffee Lake board for LENOVO C640
2820 */
2821 if ((dmi_match(DMI_BOARD_VENDOR, "LENOVO")) &&
2822 dmi_match(DMI_BOARD_NAME, "LNVNB161216"))
2823 return NVME_QUIRK_SIMPLE_SUSPEND;
ff5350a8
AL		 2824 }
2825
2826 return 0;
2827}
2828
18119775
KB		 2829static void nvme_async_probe(void *data, async_cookie_t cookie)
2830{
2831 struct nvme_dev *dev = data;
80f513b5 2832
bd46a906 2833 flush_work(&dev->ctrl.reset_work);
18119775 2834 flush_work(&dev->ctrl.scan_work);
80f513b5 2835 nvme_put_ctrl(&dev->ctrl);
18119775
KB		 2836}
2837
8d85fce7 2838static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
b60503ba 2839{
a4aea562 2840 int node, result = -ENOMEM;
b60503ba 2841 struct nvme_dev *dev;
ff5350a8 2842 unsigned long quirks = id->driver_data;
943e942e 2843 size_t alloc_size;
b60503ba 2844
a4aea562
MB		 2845 node = dev_to_node(&pdev->dev);
2846 if (node == NUMA_NO_NODE)
2fa84351 2847 set_dev_node(&pdev->dev, first_memory_node);
a4aea562
MB		 2848
2849 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
b60503ba
MW		 2850 if (!dev)
2851 return -ENOMEM;
147b27e4 2852
2a5bcfdd
WZ		 2853 dev->nr_write_queues = write_queues;
2854 dev->nr_poll_queues = poll_queues;
2855 dev->nr_allocated_queues = nvme_max_io_queues(dev) + 1;
2856 dev->queues = kcalloc_node(dev->nr_allocated_queues,
2857 sizeof(struct nvme_queue), GFP_KERNEL, node);
b60503ba
MW		 2858 if (!dev->queues)
2859 goto free;
2860
e75ec752 2861 dev->dev = get_device(&pdev->dev);
9a6b9458 2862 pci_set_drvdata(pdev, dev);
1c63dc66 2863
b00a726a
KB		 2864 result = nvme_dev_map(dev);
2865 if (result)
b00c9b7a 2866 goto put_pci;
b00a726a 2867
d86c4d8e 2868 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
5c8809e6 2869 INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
77bf25ea 2870 mutex_init(&dev->shutdown_lock);
b60503ba 2871
091b6092
MW		 2872 result = nvme_setup_prp_pools(dev);
2873 if (result)
b00c9b7a 2874 goto unmap;
4cc06521 2875
8427bbc2 2876 quirks |= check_vendor_combination_bug(pdev);
ff5350a8 2877
2744d7a0 2878 if (!noacpi && acpi_storage_d3(&pdev->dev)) {
df4f9bc4
DB		 2879 /*
2880 * Some systems use a bios work around to ask for D3 on
2881 * platforms that support kernel managed suspend.
2882 */
2883 dev_info(&pdev->dev,
2884 "platform quirk: setting simple suspend\n");
2885 quirks |= NVME_QUIRK_SIMPLE_SUSPEND;
2886 }
2887
943e942e
JA		 2888 /*
2889 * Double check that our mempool alloc size will cover the biggest
2890 * command we support.
2891 */
b13c6393 2892 alloc_size = nvme_pci_iod_alloc_size();
943e942e
JA		 2893 WARN_ON_ONCE(alloc_size > PAGE_SIZE);
2894
2895 dev->iod_mempool = mempool_create_node(1, mempool_kmalloc,
2896 mempool_kfree,
2897 (void *) alloc_size,
2898 GFP_KERNEL, node);
2899 if (!dev->iod_mempool) {
2900 result = -ENOMEM;
2901 goto release_pools;
2902 }
2903
b6e44b4c
KB		 2904 result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
2905 quirks);
2906 if (result)
2907 goto release_mempool;
2908
1b3c47c1
SG		 2909 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
2910
bd46a906 2911 nvme_reset_ctrl(&dev->ctrl);
18119775 2912 async_schedule(nvme_async_probe, dev);
4caff8fc 2913
b60503ba
MW		 2914 return 0;
2915
b6e44b4c
KB		 2916 release_mempool:
2917 mempool_destroy(dev->iod_mempool);
0877cb0d 2918 release_pools:
091b6092 2919 nvme_release_prp_pools(dev);
b00c9b7a
CJ		 2920 unmap:
2921 nvme_dev_unmap(dev);
a96d4f5c 2922 put_pci:
e75ec752 2923 put_device(dev->dev);
b60503ba
MW		 2924 free:
2925 kfree(dev->queues);
b60503ba
MW		 2926 kfree(dev);
2927 return result;
2928}
2929
775755ed 2930static void nvme_reset_prepare(struct pci_dev *pdev)
f0d54a54 2931{
a6739479 2932 struct nvme_dev *dev = pci_get_drvdata(pdev);
c1ac9a4b
KB		 2933
2934 /*
2935 * We don't need to check the return value from waiting for the reset
2936 * state as pci_dev device lock is held, making it impossible to race
2937 * with ->remove().
2938 */
2939 nvme_disable_prepare_reset(dev, false);
2940 nvme_sync_queues(&dev->ctrl);
775755ed 2941}
f0d54a54 2942
775755ed
CH		 2943static void nvme_reset_done(struct pci_dev *pdev)
2944{
f263fbb8 2945 struct nvme_dev *dev = pci_get_drvdata(pdev);
c1ac9a4b
KB		 2946
2947 if (!nvme_try_sched_reset(&dev->ctrl))
2948 flush_work(&dev->ctrl.reset_work);
f0d54a54
KB		 2949}
2950
09ece142
KB		 2951static void nvme_shutdown(struct pci_dev *pdev)
2952{
2953 struct nvme_dev *dev = pci_get_drvdata(pdev);
4e523547 2954
c1ac9a4b 2955 nvme_disable_prepare_reset(dev, true);
09ece142
KB		 2956}
2957
f58944e2
KB		 2958/*
2959 * The driver's remove may be called on a device in a partially initialized
2960 * state. This function must not have any dependencies on the device state in
2961 * order to proceed.
2962 */
8d85fce7 2963static void nvme_remove(struct pci_dev *pdev)
b60503ba
MW		 2964{
2965 struct nvme_dev *dev = pci_get_drvdata(pdev);
9a6b9458 2966
bb8d261e 2967 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
9a6b9458 2968 pci_set_drvdata(pdev, NULL);
0ff9d4e1 2969
6db28eda 2970 if (!pci_device_is_present(pdev)) {
0ff9d4e1 2971 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
1d39e692 2972 nvme_dev_disable(dev, true);
cb4bfda6 2973 nvme_dev_remove_admin(dev);
6db28eda 2974 }
0ff9d4e1 2975
d86c4d8e 2976 flush_work(&dev->ctrl.reset_work);
d09f2b45
SG		 2977 nvme_stop_ctrl(&dev->ctrl);
2978 nvme_remove_namespaces(&dev->ctrl);
a5cdb68c 2979 nvme_dev_disable(dev, true);
9fe5c59f 2980 nvme_release_cmb(dev);
87ad72a5 2981 nvme_free_host_mem(dev);
a4aea562 2982 nvme_dev_remove_admin(dev);
a1a5ef99 2983 nvme_free_queues(dev, 0);
9a6b9458 2984 nvme_release_prp_pools(dev);
b00a726a 2985 nvme_dev_unmap(dev);
726612b6 2986 nvme_uninit_ctrl(&dev->ctrl);
b60503ba
MW		 2987}
2988
671a6018 2989#ifdef CONFIG_PM_SLEEP
d916b1be
KB		 2990static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps)
2991{
2992 return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps);
2993}
2994
2995static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps)
2996{
2997 return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL);
2998}
2999
3000static int nvme_resume(struct device *dev)
3001{
3002 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
3003 struct nvme_ctrl *ctrl = &ndev->ctrl;
3004
4eaefe8c 3005 if (ndev->last_ps == U32_MAX ||
d916b1be 3006 nvme_set_power_state(ctrl, ndev->last_ps) != 0)
c1ac9a4b 3007 return nvme_try_sched_reset(&ndev->ctrl);
d916b1be
KB		 3008 return 0;
3009}
3010
cd638946
KB		 3011static int nvme_suspend(struct device *dev)
3012{
3013 struct pci_dev *pdev = to_pci_dev(dev);
3014 struct nvme_dev *ndev = pci_get_drvdata(pdev);
d916b1be
KB		 3015 struct nvme_ctrl *ctrl = &ndev->ctrl;
3016 int ret = -EBUSY;
3017
4eaefe8c
RW		 3018 ndev->last_ps = U32_MAX;
3019
d916b1be
KB		 3020 /*
3021 * The platform does not remove power for a kernel managed suspend so
3022 * use host managed nvme power settings for lowest idle power if
3023 * possible. This should have quicker resume latency than a full device
3024 * shutdown. But if the firmware is involved after the suspend or the
3025 * device does not support any non-default power states, shut down the
3026 * device fully.
4eaefe8c
RW		 3027 *
3028 * If ASPM is not enabled for the device, shut down the device and allow
3029 * the PCI bus layer to put it into D3 in order to take the PCIe link
3030 * down, so as to allow the platform to achieve its minimum low-power
3031 * state (which may not be possible if the link is up).
b97120b1
CH		 3032 *
3033 * If a host memory buffer is enabled, shut down the device as the NVMe
3034 * specification allows the device to access the host memory buffer in
3035 * host DRAM from all power states, but hosts will fail access to DRAM
3036 * during S3.
d916b1be 3037 */
4eaefe8c 3038 if (pm_suspend_via_firmware() || !ctrl->npss ||
cb32de1b 3039 !pcie_aspm_enabled(pdev) ||
b97120b1 3040 ndev->nr_host_mem_descs ||
c1ac9a4b
KB		 3041 (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND))
3042 return nvme_disable_prepare_reset(ndev, true);
d916b1be
KB		 3043
3044 nvme_start_freeze(ctrl);
3045 nvme_wait_freeze(ctrl);
3046 nvme_sync_queues(ctrl);
3047
5d02a5c1 3048 if (ctrl->state != NVME_CTRL_LIVE)
d916b1be
KB		 3049 goto unfreeze;
3050
d916b1be
KB		 3051 ret = nvme_get_power_state(ctrl, &ndev->last_ps);
3052 if (ret < 0)
3053 goto unfreeze;
3054
7cbb5c6f
ML		 3055 /*
3056 * A saved state prevents pci pm from generically controlling the
3057 * device's power. If we're using protocol specific settings, we don't
3058 * want pci interfering.
3059 */
3060 pci_save_state(pdev);
3061
d916b1be
KB		 3062 ret = nvme_set_power_state(ctrl, ctrl->npss);
3063 if (ret < 0)
3064 goto unfreeze;
3065
3066 if (ret) {
7cbb5c6f
ML		 3067 /* discard the saved state */
3068 pci_load_saved_state(pdev, NULL);
3069
d916b1be
KB		 3070 /*
3071 * Clearing npss forces a controller reset on resume. The
05d3046f 3072 * correct value will be rediscovered then.
d916b1be 3073 */
c1ac9a4b 3074 ret = nvme_disable_prepare_reset(ndev, true);
d916b1be 3075 ctrl->npss = 0;
d916b1be 3076 }
d916b1be
KB		 3077unfreeze:
3078 nvme_unfreeze(ctrl);
3079 return ret;
3080}
3081
3082static int nvme_simple_suspend(struct device *dev)
3083{
3084 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
4e523547 3085
c1ac9a4b 3086 return nvme_disable_prepare_reset(ndev, true);
cd638946
KB		 3087}
3088
d916b1be 3089static int nvme_simple_resume(struct device *dev)
cd638946
KB		 3090{
3091 struct pci_dev *pdev = to_pci_dev(dev);
3092 struct nvme_dev *ndev = pci_get_drvdata(pdev);
cd638946 3093
c1ac9a4b 3094 return nvme_try_sched_reset(&ndev->ctrl);
cd638946
KB		 3095}
3096
21774222 3097static const struct dev_pm_ops nvme_dev_pm_ops = {
d916b1be
KB		 3098 .suspend = nvme_suspend,
3099 .resume = nvme_resume,
3100 .freeze = nvme_simple_suspend,
3101 .thaw = nvme_simple_resume,
3102 .poweroff = nvme_simple_suspend,
3103 .restore = nvme_simple_resume,
3104};
3105#endif /* CONFIG_PM_SLEEP */
b60503ba 3106
a0a3408e
KB		 3107static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
3108 pci_channel_state_t state)
3109{
3110 struct nvme_dev *dev = pci_get_drvdata(pdev);
3111
3112 /*
3113 * A frozen channel requires a reset. When detected, this method will
3114 * shutdown the controller to quiesce. The controller will be restarted
3115 * after the slot reset through driver's slot_reset callback.
3116 */
a0a3408e
KB		 3117 switch (state) {
3118 case pci_channel_io_normal:
3119 return PCI_ERS_RESULT_CAN_RECOVER;
3120 case pci_channel_io_frozen:
d011fb31
KB		 3121 dev_warn(dev->ctrl.device,
3122 "frozen state error detected, reset controller\n");
a5cdb68c 3123 nvme_dev_disable(dev, false);
a0a3408e
KB		 3124 return PCI_ERS_RESULT_NEED_RESET;
3125 case pci_channel_io_perm_failure:
d011fb31
KB		 3126 dev_warn(dev->ctrl.device,
3127 "failure state error detected, request disconnect\n");
a0a3408e
KB		 3128 return PCI_ERS_RESULT_DISCONNECT;
3129 }
3130 return PCI_ERS_RESULT_NEED_RESET;
3131}
3132
3133static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
3134{
3135 struct nvme_dev *dev = pci_get_drvdata(pdev);
3136
1b3c47c1 3137 dev_info(dev->ctrl.device, "restart after slot reset\n");
a0a3408e 3138 pci_restore_state(pdev);
d86c4d8e 3139 nvme_reset_ctrl(&dev->ctrl);
a0a3408e
KB		 3140 return PCI_ERS_RESULT_RECOVERED;
3141}
3142
3143static void nvme_error_resume(struct pci_dev *pdev)
3144{
72cd4cc2
KB		 3145 struct nvme_dev *dev = pci_get_drvdata(pdev);
3146
3147 flush_work(&dev->ctrl.reset_work);
a0a3408e
KB		 3148}
3149
1d352035 3150static const struct pci_error_handlers nvme_err_handler = {
b60503ba 3151 .error_detected = nvme_error_detected,
b60503ba
MW		 3152 .slot_reset = nvme_slot_reset,
3153 .resume = nvme_error_resume,
775755ed
CH		 3154 .reset_prepare = nvme_reset_prepare,
3155 .reset_done = nvme_reset_done,
b60503ba
MW		 3156};
3157
6eb0d698 3158static const struct pci_device_id nvme_id_table[] = {
972b13e2 3159 { PCI_VDEVICE(INTEL, 0x0953), /* Intel 750/P3500/P3600/P3700 */
08095e70 3160 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 3161 NVME_QUIRK_DEALLOCATE_ZEROES, },
972b13e2 3162 { PCI_VDEVICE(INTEL, 0x0a53), /* Intel P3520 */
99466e70 3163 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 3164 NVME_QUIRK_DEALLOCATE_ZEROES, },
972b13e2 3165 { PCI_VDEVICE(INTEL, 0x0a54), /* Intel P4500/P4600 */
99466e70 3166 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 3167 NVME_QUIRK_DEALLOCATE_ZEROES, },
972b13e2 3168 { PCI_VDEVICE(INTEL, 0x0a55), /* Dell Express Flash P4600 */
f99cb7af
DWF		 3169 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3170 NVME_QUIRK_DEALLOCATE_ZEROES, },
50af47d0 3171 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */
9abd68ef 3172 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
6c6aa2f2 3173 NVME_QUIRK_MEDIUM_PRIO_SQ |
ce4cc313
DM		 3174 NVME_QUIRK_NO_TEMP_THRESH_CHANGE |
3175 NVME_QUIRK_DISABLE_WRITE_ZEROES, },
6299358d
JD		 3176 { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */
3177 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
540c801c 3178 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */
7b210e4e
CH		 3179 .driver_data = NVME_QUIRK_IDENTIFY_CNS |
3180 NVME_QUIRK_DISABLE_WRITE_ZEROES, },
5bedd3af
CH		 3181 { PCI_DEVICE(0x126f, 0x2263), /* Silicon Motion unidentified */
3182 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST, },
0302ae60 3183 { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */
5e112d3f
JE		 3184 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
3185 NVME_QUIRK_NO_NS_DESC_LIST, },
54adc010
GP		 3186 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
3187 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
8c97eecc
JL		 3188 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */
3189 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
015282c9
WW		 3190 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
3191 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
d554b5e1
MP		 3192 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */
3193 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3194 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */
7ee5c78c 3195 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
abbb5f59 3196 NVME_QUIRK_DISABLE_WRITE_ZEROES|
7ee5c78c 3197 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
c9e95c39
CS		 3198 { PCI_DEVICE(0x1987, 0x5016), /* Phison E16 */
3199 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
6e6a6828
PT		 3200 { PCI_DEVICE(0x1b4b, 0x1092), /* Lexar 256 GB SSD */
3201 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST |
3202 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
608cc4b1
CH		 3203 { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */
3204 .driver_data = NVME_QUIRK_LIGHTNVM, },
3205 { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */
3206 .driver_data = NVME_QUIRK_LIGHTNVM, },
ea48e877
WX		 3207 { PCI_DEVICE(0x1d1d, 0x2601), /* CNEX Granby */
3208 .driver_data = NVME_QUIRK_LIGHTNVM, },
08b903b5
MN		 3209 { PCI_DEVICE(0x10ec, 0x5762), /* ADATA SX6000LNP */
3210 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
f03e42c6
GC		 3211 { PCI_DEVICE(0x1cc1, 0x8201), /* ADATA SX8200PNP 512GB */
3212 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3213 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
5611ec2b
KHF		 3214 { PCI_DEVICE(0x1c5c, 0x1504), /* SK Hynix PC400 */
3215 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
02ca079c
KHF		 3216 { PCI_DEVICE(0x15b7, 0x2001), /* Sandisk Skyhawk */
3217 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
89919929
CK		 3218 { PCI_DEVICE(0x1d97, 0x2263), /* SPCC */
3219 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
dc22c1c0
ZB		 3220 { PCI_DEVICE(0x2646, 0x2262), /* KINGSTON SKC2000 NVMe SSD */
3221 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
538e4a8c
TL		 3222 { PCI_DEVICE(0x2646, 0x2263), /* KINGSTON A2000 NVMe SSD */
3223 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
4bdf2603
FS		 3224 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0061),
3225 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3226 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0065),
3227 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3228 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x8061),
3229 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3230 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd00),
3231 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3232 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd01),
3233 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3234 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd02),
3235 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
98f7b86a
AS		 3236 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001),
3237 .driver_data = NVME_QUIRK_SINGLE_VECTOR },
124298bd 3238 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
66341331
BH		 3239 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005),
3240 .driver_data = NVME_QUIRK_SINGLE_VECTOR |
d38e9f04
BH		 3241 NVME_QUIRK_128_BYTES_SQES |
3242 NVME_QUIRK_SHARED_TAGS },
0b85f59d
AS		 3243
3244 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
b60503ba
MW		 3245 { 0, }
3246};
3247MODULE_DEVICE_TABLE(pci, nvme_id_table);
3248
3249static struct pci_driver nvme_driver = {
3250 .name = "nvme",
3251 .id_table = nvme_id_table,
3252 .probe = nvme_probe,
8d85fce7 3253 .remove = nvme_remove,
09ece142 3254 .shutdown = nvme_shutdown,
d916b1be 3255#ifdef CONFIG_PM_SLEEP
cd638946
KB		 3256 .driver = {
3257 .pm = &nvme_dev_pm_ops,
3258 },
d916b1be 3259#endif
74d986ab 3260 .sriov_configure = pci_sriov_configure_simple,
b60503ba
MW		 3261 .err_handler = &nvme_err_handler,
3262};
3263
3264static int __init nvme_init(void)
3265{
81101540
CH		 3266 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
3267 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
3268 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
612b7286 3269 BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2);
17c33167 3270
9a6327d2 3271 return pci_register_driver(&nvme_driver);
b60503ba
MW		 3272}
3273
3274static void __exit nvme_exit(void)
3275{
3276 pci_unregister_driver(&nvme_driver);
03e0f3a6 3277 flush_workqueue(nvme_wq);
b60503ba
MW		 3278}
3279
3280MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3281MODULE_LICENSE("GPL");
c78b4713 3282MODULE_VERSION("1.0");
b60503ba
MW		 3283module_init(nvme_init);
3284module_exit(nvme_exit);
Linux 6.x block layer and io_uring tree(s)