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nvme-pci: only call nvme_unmap_data for requests transferring data
[linux-2.6-block.git] / drivers / nvme / host / pci.c
CommitLineData
5f37396d 1// SPDX-License-Identifier: GPL-2.0
b60503ba
MW		 2/*
3 * NVM Express device driver
6eb0d698 4 * Copyright (c) 2011-2014, Intel Corporation.
b60503ba
MW		 5 */
6
a0a3408e 7#include <linux/aer.h>
18119775 8#include <linux/async.h>
b60503ba 9#include <linux/blkdev.h>
a4aea562 10#include <linux/blk-mq.h>
dca51e78 11#include <linux/blk-mq-pci.h>
ff5350a8 12#include <linux/dmi.h>
b60503ba
MW		 13#include <linux/init.h>
14#include <linux/interrupt.h>
15#include <linux/io.h>
b60503ba
MW		 16#include <linux/mm.h>
17#include <linux/module.h>
77bf25ea 18#include <linux/mutex.h>
d0877473 19#include <linux/once.h>
b60503ba 20#include <linux/pci.h>
e1e5e564 21#include <linux/t10-pi.h>
b60503ba 22#include <linux/types.h>
2f8e2c87 23#include <linux/io-64-nonatomic-lo-hi.h>
a98e58e5 24#include <linux/sed-opal.h>
0f238ff5 25#include <linux/pci-p2pdma.h>
797a796a 26
604c01d5 27#include "trace.h"
f11bb3e2
CH		 28#include "nvme.h"
29
b60503ba
MW		 30#define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
31#define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
c965809c 32
a7a7cbe3 33#define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc))
9d43cf64 34
943e942e
JA		 35/*
36 * These can be higher, but we need to ensure that any command doesn't
37 * require an sg allocation that needs more than a page of data.
38 */
39#define NVME_MAX_KB_SZ 4096
40#define NVME_MAX_SEGS 127
41
58ffacb5
MW		 42static int use_threaded_interrupts;
43module_param(use_threaded_interrupts, int, 0);
44
8ffaadf7 45static bool use_cmb_sqes = true;
69f4eb9f 46module_param(use_cmb_sqes, bool, 0444);
8ffaadf7
JD		 47MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
48
87ad72a5
CH		 49static unsigned int max_host_mem_size_mb = 128;
50module_param(max_host_mem_size_mb, uint, 0444);
51MODULE_PARM_DESC(max_host_mem_size_mb,
52 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
1fa6aead 53
a7a7cbe3
CK		 54static unsigned int sgl_threshold = SZ_32K;
55module_param(sgl_threshold, uint, 0644);
56MODULE_PARM_DESC(sgl_threshold,
57 "Use SGLs when average request segment size is larger or equal to "
58 "this size. Use 0 to disable SGLs.");
59
b27c1e68 60static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
61static const struct kernel_param_ops io_queue_depth_ops = {
62 .set = io_queue_depth_set,
63 .get = param_get_int,
64};
65
66static int io_queue_depth = 1024;
67module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
68MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2");
69
3b6592f7
JA		 70static int queue_count_set(const char *val, const struct kernel_param *kp);
71static const struct kernel_param_ops queue_count_ops = {
72 .set = queue_count_set,
73 .get = param_get_int,
74};
75
76static int write_queues;
77module_param_cb(write_queues, &queue_count_ops, &write_queues, 0644);
78MODULE_PARM_DESC(write_queues,
79 "Number of queues to use for writes. If not set, reads and writes "
80 "will share a queue set.");
81
a4668d9b 82static int poll_queues = 0;
4b04cc6a
JA		 83module_param_cb(poll_queues, &queue_count_ops, &poll_queues, 0644);
84MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO.");
85
1c63dc66
CH		 86struct nvme_dev;
87struct nvme_queue;
b3fffdef 88
a5cdb68c 89static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
8fae268b 90static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode);
d4b4ff8e 91
1c63dc66
CH		 92/*
93 * Represents an NVM Express device. Each nvme_dev is a PCI function.
94 */
95struct nvme_dev {
147b27e4 96 struct nvme_queue *queues;
1c63dc66
CH		 97 struct blk_mq_tag_set tagset;
98 struct blk_mq_tag_set admin_tagset;
99 u32 __iomem *dbs;
100 struct device *dev;
101 struct dma_pool *prp_page_pool;
102 struct dma_pool *prp_small_pool;
1c63dc66
CH		 103 unsigned online_queues;
104 unsigned max_qid;
e20ba6e1 105 unsigned io_queues[HCTX_MAX_TYPES];
22b55601 106 unsigned int num_vecs;
1c63dc66
CH		 107 int q_depth;
108 u32 db_stride;
1c63dc66 109 void __iomem *bar;
97f6ef64 110 unsigned long bar_mapped_size;
5c8809e6 111 struct work_struct remove_work;
77bf25ea 112 struct mutex shutdown_lock;
1c63dc66 113 bool subsystem;
1c63dc66 114 u64 cmb_size;
0f238ff5 115 bool cmb_use_sqes;
1c63dc66 116 u32 cmbsz;
202021c1 117 u32 cmbloc;
1c63dc66 118 struct nvme_ctrl ctrl;
87ad72a5 119
943e942e
JA		 120 mempool_t *iod_mempool;
121
87ad72a5 122 /* shadow doorbell buffer support: */
f9f38e33
HK		 123 u32 *dbbuf_dbs;
124 dma_addr_t dbbuf_dbs_dma_addr;
125 u32 *dbbuf_eis;
126 dma_addr_t dbbuf_eis_dma_addr;
87ad72a5
CH		 127
128 /* host memory buffer support: */
129 u64 host_mem_size;
130 u32 nr_host_mem_descs;
4033f35d 131 dma_addr_t host_mem_descs_dma;
87ad72a5
CH		 132 struct nvme_host_mem_buf_desc *host_mem_descs;
133 void **host_mem_desc_bufs;
4d115420 134};
1fa6aead 135
b27c1e68 136static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
137{
138 int n = 0, ret;
139
140 ret = kstrtoint(val, 10, &n);
141 if (ret != 0 || n < 2)
142 return -EINVAL;
143
144 return param_set_int(val, kp);
145}
146
3b6592f7
JA		 147static int queue_count_set(const char *val, const struct kernel_param *kp)
148{
149 int n = 0, ret;
150
151 ret = kstrtoint(val, 10, &n);
e895fedf
BVA		 152 if (ret)
153 return ret;
3b6592f7
JA		 154 if (n > num_possible_cpus())
155 n = num_possible_cpus();
156
157 return param_set_int(val, kp);
158}
159
f9f38e33
HK		 160static inline unsigned int sq_idx(unsigned int qid, u32 stride)
161{
162 return qid * 2 * stride;
163}
164
165static inline unsigned int cq_idx(unsigned int qid, u32 stride)
166{
167 return (qid * 2 + 1) * stride;
168}
169
1c63dc66
CH		 170static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
171{
172 return container_of(ctrl, struct nvme_dev, ctrl);
173}
174
b60503ba
MW		 175/*
176 * An NVM Express queue. Each device has at least two (one for admin
177 * commands and one for I/O commands).
178 */
179struct nvme_queue {
091b6092 180 struct nvme_dev *dev;
1ab0cd69 181 spinlock_t sq_lock;
b60503ba 182 struct nvme_command *sq_cmds;
3a7afd8e
CH		 183 /* only used for poll queues: */
184 spinlock_t cq_poll_lock ____cacheline_aligned_in_smp;
b60503ba 185 volatile struct nvme_completion *cqes;
42483228 186 struct blk_mq_tags **tags;
b60503ba
MW		 187 dma_addr_t sq_dma_addr;
188 dma_addr_t cq_dma_addr;
b60503ba
MW		 189 u32 __iomem *q_db;
190 u16 q_depth;
7c349dde 191 u16 cq_vector;
b60503ba 192 u16 sq_tail;
04f3eafd 193 u16 last_sq_tail;
b60503ba 194 u16 cq_head;
68fa9dbe 195 u16 last_cq_head;
c30341dc 196 u16 qid;
e9539f47 197 u8 cq_phase;
4e224106
CH		 198 unsigned long flags;
199#define NVMEQ_ENABLED 0
63223078 200#define NVMEQ_SQ_CMB 1
d1ed6aa1 201#define NVMEQ_DELETE_ERROR 2
7c349dde 202#define NVMEQ_POLLED 3
f9f38e33
HK		 203 u32 *dbbuf_sq_db;
204 u32 *dbbuf_cq_db;
205 u32 *dbbuf_sq_ei;
206 u32 *dbbuf_cq_ei;
d1ed6aa1 207 struct completion delete_done;
b60503ba
MW		 208};
209
71bd150c 210/*
9b048119
CH		 211 * The nvme_iod describes the data in an I/O.
212 *
213 * The sg pointer contains the list of PRP/SGL chunk allocations in addition
214 * to the actual struct scatterlist.
71bd150c
CH		 215 */
216struct nvme_iod {
d49187e9 217 struct nvme_request req;
f4800d6d 218 struct nvme_queue *nvmeq;
a7a7cbe3 219 bool use_sgl;
f4800d6d 220 int aborted;
71bd150c 221 int npages; /* In the PRP list. 0 means small pool in use */
71bd150c 222 int nents; /* Used in scatterlist */
71bd150c 223 dma_addr_t first_dma;
bf684057 224 struct scatterlist meta_sg; /* metadata requires single contiguous buffer */
f4800d6d
CH		 225 struct scatterlist *sg;
226 struct scatterlist inline_sg[0];
b60503ba
MW		 227};
228
229/*
230 * Check we didin't inadvertently grow the command struct
231 */
232static inline void _nvme_check_size(void)
233{
234 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
235 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
236 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
237 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
238 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
f8ebf840 239 BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
c30341dc 240 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
b60503ba 241 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
0add5e8e
JT		 242 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != NVME_IDENTIFY_DATA_SIZE);
243 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != NVME_IDENTIFY_DATA_SIZE);
b60503ba 244 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
6ecec745 245 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
f9f38e33
HK		 246 BUILD_BUG_ON(sizeof(struct nvme_dbbuf) != 64);
247}
248
3b6592f7
JA		 249static unsigned int max_io_queues(void)
250{
4b04cc6a 251 return num_possible_cpus() + write_queues + poll_queues;
3b6592f7
JA		 252}
253
254static unsigned int max_queue_count(void)
255{
256 /* IO queues + admin queue */
257 return 1 + max_io_queues();
258}
259
f9f38e33
HK		 260static inline unsigned int nvme_dbbuf_size(u32 stride)
261{
3b6592f7 262 return (max_queue_count() * 8 * stride);
f9f38e33
HK		 263}
264
265static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
266{
267 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
268
269 if (dev->dbbuf_dbs)
270 return 0;
271
272 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
273 &dev->dbbuf_dbs_dma_addr,
274 GFP_KERNEL);
275 if (!dev->dbbuf_dbs)
276 return -ENOMEM;
277 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
278 &dev->dbbuf_eis_dma_addr,
279 GFP_KERNEL);
280 if (!dev->dbbuf_eis) {
281 dma_free_coherent(dev->dev, mem_size,
282 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
283 dev->dbbuf_dbs = NULL;
284 return -ENOMEM;
285 }
286
287 return 0;
288}
289
290static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
291{
292 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
293
294 if (dev->dbbuf_dbs) {
295 dma_free_coherent(dev->dev, mem_size,
296 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
297 dev->dbbuf_dbs = NULL;
298 }
299 if (dev->dbbuf_eis) {
300 dma_free_coherent(dev->dev, mem_size,
301 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
302 dev->dbbuf_eis = NULL;
303 }
304}
305
306static void nvme_dbbuf_init(struct nvme_dev *dev,
307 struct nvme_queue *nvmeq, int qid)
308{
309 if (!dev->dbbuf_dbs || !qid)
310 return;
311
312 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
313 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
314 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
315 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
316}
317
318static void nvme_dbbuf_set(struct nvme_dev *dev)
319{
320 struct nvme_command c;
321
322 if (!dev->dbbuf_dbs)
323 return;
324
325 memset(&c, 0, sizeof(c));
326 c.dbbuf.opcode = nvme_admin_dbbuf;
327 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
328 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
329
330 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
9bdcfb10 331 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
f9f38e33
HK		 332 /* Free memory and continue on */
333 nvme_dbbuf_dma_free(dev);
334 }
335}
336
337static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
338{
339 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
340}
341
342/* Update dbbuf and return true if an MMIO is required */
343static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
344 volatile u32 *dbbuf_ei)
345{
346 if (dbbuf_db) {
347 u16 old_value;
348
349 /*
350 * Ensure that the queue is written before updating
351 * the doorbell in memory
352 */
353 wmb();
354
355 old_value = *dbbuf_db;
356 *dbbuf_db = value;
357
f1ed3df2
MW		 358 /*
359 * Ensure that the doorbell is updated before reading the event
360 * index from memory. The controller needs to provide similar
361 * ordering to ensure the envent index is updated before reading
362 * the doorbell.
363 */
364 mb();
365
f9f38e33
HK		 366 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value))
367 return false;
368 }
369
370 return true;
b60503ba
MW		 371}
372
ac3dd5bd
JA		 373/*
374 * Max size of iod being embedded in the request payload
375 */
376#define NVME_INT_PAGES 2
5fd4ce1b 377#define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size)
ac3dd5bd
JA		 378
379/*
380 * Will slightly overestimate the number of pages needed. This is OK
381 * as it only leads to a small amount of wasted memory for the lifetime of
382 * the I/O.
383 */
384static int nvme_npages(unsigned size, struct nvme_dev *dev)
385{
5fd4ce1b
CH		 386 unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size,
387 dev->ctrl.page_size);
ac3dd5bd
JA		 388 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
389}
390
a7a7cbe3
CK		 391/*
392 * Calculates the number of pages needed for the SGL segments. For example a 4k
393 * page can accommodate 256 SGL descriptors.
394 */
395static int nvme_pci_npages_sgl(unsigned int num_seg)
ac3dd5bd 396{
a7a7cbe3 397 return DIV_ROUND_UP(num_seg * sizeof(struct nvme_sgl_desc), PAGE_SIZE);
f4800d6d 398}
ac3dd5bd 399
a7a7cbe3
CK		 400static unsigned int nvme_pci_iod_alloc_size(struct nvme_dev *dev,
401 unsigned int size, unsigned int nseg, bool use_sgl)
f4800d6d 402{
a7a7cbe3
CK		 403 size_t alloc_size;
404
405 if (use_sgl)
406 alloc_size = sizeof(__le64 *) * nvme_pci_npages_sgl(nseg);
407 else
408 alloc_size = sizeof(__le64 *) * nvme_npages(size, dev);
409
410 return alloc_size + sizeof(struct scatterlist) * nseg;
f4800d6d 411}
ac3dd5bd 412
a7a7cbe3 413static unsigned int nvme_pci_cmd_size(struct nvme_dev *dev, bool use_sgl)
f4800d6d 414{
a7a7cbe3
CK		 415 unsigned int alloc_size = nvme_pci_iod_alloc_size(dev,
416 NVME_INT_BYTES(dev), NVME_INT_PAGES,
417 use_sgl);
418
419 return sizeof(struct nvme_iod) + alloc_size;
ac3dd5bd
JA		 420}
421
a4aea562
MB		 422static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
423 unsigned int hctx_idx)
e85248e5 424{
a4aea562 425 struct nvme_dev *dev = data;
147b27e4 426 struct nvme_queue *nvmeq = &dev->queues[0];
a4aea562 427
42483228
KB		 428 WARN_ON(hctx_idx != 0);
429 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
430 WARN_ON(nvmeq->tags);
431
a4aea562 432 hctx->driver_data = nvmeq;
42483228 433 nvmeq->tags = &dev->admin_tagset.tags[0];
a4aea562 434 return 0;
e85248e5
MW		 435}
436
4af0e21c
KB		 437static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
438{
439 struct nvme_queue *nvmeq = hctx->driver_data;
440
441 nvmeq->tags = NULL;
442}
443
a4aea562
MB		 444static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
445 unsigned int hctx_idx)
b60503ba 446{
a4aea562 447 struct nvme_dev *dev = data;
147b27e4 448 struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
a4aea562 449
42483228
KB		 450 if (!nvmeq->tags)
451 nvmeq->tags = &dev->tagset.tags[hctx_idx];
b60503ba 452
42483228 453 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
a4aea562
MB		 454 hctx->driver_data = nvmeq;
455 return 0;
b60503ba
MW		 456}
457
d6296d39
CH		 458static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req,
459 unsigned int hctx_idx, unsigned int numa_node)
b60503ba 460{
d6296d39 461 struct nvme_dev *dev = set->driver_data;
f4800d6d 462 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
0350815a 463 int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0;
147b27e4 464 struct nvme_queue *nvmeq = &dev->queues[queue_idx];
a4aea562
MB		 465
466 BUG_ON(!nvmeq);
f4800d6d 467 iod->nvmeq = nvmeq;
59e29ce6
SG		 468
469 nvme_req(req)->ctrl = &dev->ctrl;
a4aea562
MB		 470 return 0;
471}
472
3b6592f7
JA		 473static int queue_irq_offset(struct nvme_dev *dev)
474{
475 /* if we have more than 1 vec, admin queue offsets us by 1 */
476 if (dev->num_vecs > 1)
477 return 1;
478
479 return 0;
480}
481
dca51e78
CH		 482static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
483{
484 struct nvme_dev *dev = set->driver_data;
3b6592f7
JA		 485 int i, qoff, offset;
486
487 offset = queue_irq_offset(dev);
488 for (i = 0, qoff = 0; i < set->nr_maps; i++) {
489 struct blk_mq_queue_map *map = &set->map[i];
490
491 map->nr_queues = dev->io_queues[i];
492 if (!map->nr_queues) {
e20ba6e1 493 BUG_ON(i == HCTX_TYPE_DEFAULT);
7e849dd9 494 continue;
3b6592f7
JA		 495 }
496
4b04cc6a
JA		 497 /*
498 * The poll queue(s) doesn't have an IRQ (and hence IRQ
499 * affinity), so use the regular blk-mq cpu mapping
500 */
3b6592f7 501 map->queue_offset = qoff;
e20ba6e1 502 if (i != HCTX_TYPE_POLL)
4b04cc6a
JA		 503 blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset);
504 else
505 blk_mq_map_queues(map);
3b6592f7
JA		 506 qoff += map->nr_queues;
507 offset += map->nr_queues;
508 }
509
510 return 0;
dca51e78
CH		 511}
512
04f3eafd
JA		 513/*
514 * Write sq tail if we are asked to, or if the next command would wrap.
515 */
516static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq)
517{
518 if (!write_sq) {
519 u16 next_tail = nvmeq->sq_tail + 1;
520
521 if (next_tail == nvmeq->q_depth)
522 next_tail = 0;
523 if (next_tail != nvmeq->last_sq_tail)
524 return;
525 }
526
527 if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail,
528 nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei))
529 writel(nvmeq->sq_tail, nvmeq->q_db);
530 nvmeq->last_sq_tail = nvmeq->sq_tail;
531}
532
b60503ba 533/**
90ea5ca4 534 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
b60503ba
MW		 535 * @nvmeq: The queue to use
536 * @cmd: The command to send
04f3eafd 537 * @write_sq: whether to write to the SQ doorbell
b60503ba 538 */
04f3eafd
JA		 539static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd,
540 bool write_sq)
b60503ba 541{
90ea5ca4 542 spin_lock(&nvmeq->sq_lock);
0f238ff5 543 memcpy(&nvmeq->sq_cmds[nvmeq->sq_tail], cmd, sizeof(*cmd));
90ea5ca4
CH		 544 if (++nvmeq->sq_tail == nvmeq->q_depth)
545 nvmeq->sq_tail = 0;
04f3eafd
JA		 546 nvme_write_sq_db(nvmeq, write_sq);
547 spin_unlock(&nvmeq->sq_lock);
548}
549
550static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx)
551{
552 struct nvme_queue *nvmeq = hctx->driver_data;
553
554 spin_lock(&nvmeq->sq_lock);
555 if (nvmeq->sq_tail != nvmeq->last_sq_tail)
556 nvme_write_sq_db(nvmeq, true);
90ea5ca4 557 spin_unlock(&nvmeq->sq_lock);
b60503ba
MW		 558}
559
a7a7cbe3 560static void **nvme_pci_iod_list(struct request *req)
b60503ba 561{
f4800d6d 562 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3 563 return (void **)(iod->sg + blk_rq_nr_phys_segments(req));
b60503ba
MW		 564}
565
955b1b5a
MI		 566static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req)
567{
568 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
20469a37 569 int nseg = blk_rq_nr_phys_segments(req);
955b1b5a
MI		 570 unsigned int avg_seg_size;
571
20469a37
KB		 572 if (nseg == 0)
573 return false;
574
575 avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
955b1b5a
MI		 576
577 if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1))))
578 return false;
579 if (!iod->nvmeq->qid)
580 return false;
581 if (!sgl_threshold || avg_seg_size < sgl_threshold)
582 return false;
583 return true;
584}
585
7fe07d14 586static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
b60503ba 587{
f4800d6d 588 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
7fe07d14
CH		 589 enum dma_data_direction dma_dir = rq_data_dir(req) ?
590 DMA_TO_DEVICE : DMA_FROM_DEVICE;
a7a7cbe3
CK		 591 const int last_prp = dev->ctrl.page_size / sizeof(__le64) - 1;
592 dma_addr_t dma_addr = iod->first_dma, next_dma_addr;
eca18b23 593 int i;
eca18b23 594
7fe07d14
CH		 595 if (iod->nents) {
596 /* P2PDMA requests do not need to be unmapped */
597 if (!is_pci_p2pdma_page(sg_page(iod->sg)))
598 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
599
600 if (blk_integrity_rq(req))
601 dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir);
602 }
603
eca18b23 604 if (iod->npages == 0)
a7a7cbe3
CK		 605 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0],
606 dma_addr);
607
eca18b23 608 for (i = 0; i < iod->npages; i++) {
a7a7cbe3
CK		 609 void *addr = nvme_pci_iod_list(req)[i];
610
611 if (iod->use_sgl) {
612 struct nvme_sgl_desc *sg_list = addr;
613
614 next_dma_addr =
615 le64_to_cpu((sg_list[SGES_PER_PAGE - 1]).addr);
616 } else {
617 __le64 *prp_list = addr;
618
619 next_dma_addr = le64_to_cpu(prp_list[last_prp]);
620 }
621
622 dma_pool_free(dev->prp_page_pool, addr, dma_addr);
623 dma_addr = next_dma_addr;
eca18b23 624 }
ac3dd5bd 625
f4800d6d 626 if (iod->sg != iod->inline_sg)
943e942e 627 mempool_free(iod->sg, dev->iod_mempool);
b4ff9c8d
KB		 628}
629
d0877473
KB		 630static void nvme_print_sgl(struct scatterlist *sgl, int nents)
631{
632 int i;
633 struct scatterlist *sg;
634
635 for_each_sg(sgl, sg, nents, i) {
636 dma_addr_t phys = sg_phys(sg);
637 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
638 "dma_address:%pad dma_length:%d\n",
639 i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
640 sg_dma_len(sg));
641 }
642}
643
a7a7cbe3
CK		 644static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
645 struct request *req, struct nvme_rw_command *cmnd)
ff22b54f 646{
f4800d6d 647 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
99802a7a 648 struct dma_pool *pool;
b131c61d 649 int length = blk_rq_payload_bytes(req);
eca18b23 650 struct scatterlist *sg = iod->sg;
ff22b54f
MW		 651 int dma_len = sg_dma_len(sg);
652 u64 dma_addr = sg_dma_address(sg);
5fd4ce1b 653 u32 page_size = dev->ctrl.page_size;
f137e0f1 654 int offset = dma_addr & (page_size - 1);
e025344c 655 __le64 *prp_list;
a7a7cbe3 656 void **list = nvme_pci_iod_list(req);
e025344c 657 dma_addr_t prp_dma;
eca18b23 658 int nprps, i;
ff22b54f 659
1d090624 660 length -= (page_size - offset);
5228b328
JS		 661 if (length <= 0) {
662 iod->first_dma = 0;
a7a7cbe3 663 goto done;
5228b328 664 }
ff22b54f 665
1d090624 666 dma_len -= (page_size - offset);
ff22b54f 667 if (dma_len) {
1d090624 668 dma_addr += (page_size - offset);
ff22b54f
MW		 669 } else {
670 sg = sg_next(sg);
671 dma_addr = sg_dma_address(sg);
672 dma_len = sg_dma_len(sg);
673 }
674
1d090624 675 if (length <= page_size) {
edd10d33 676 iod->first_dma = dma_addr;
a7a7cbe3 677 goto done;
e025344c
SMM		 678 }
679
1d090624 680 nprps = DIV_ROUND_UP(length, page_size);
99802a7a
MW		 681 if (nprps <= (256 / 8)) {
682 pool = dev->prp_small_pool;
eca18b23 683 iod->npages = 0;
99802a7a
MW		 684 } else {
685 pool = dev->prp_page_pool;
eca18b23 686 iod->npages = 1;
99802a7a
MW		 687 }
688
69d2b571 689 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
b77954cb 690 if (!prp_list) {
edd10d33 691 iod->first_dma = dma_addr;
eca18b23 692 iod->npages = -1;
86eea289 693 return BLK_STS_RESOURCE;
b77954cb 694 }
eca18b23
MW		 695 list[0] = prp_list;
696 iod->first_dma = prp_dma;
e025344c
SMM		 697 i = 0;
698 for (;;) {
1d090624 699 if (i == page_size >> 3) {
e025344c 700 __le64 *old_prp_list = prp_list;
69d2b571 701 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
eca18b23 702 if (!prp_list)
86eea289 703 return BLK_STS_RESOURCE;
eca18b23 704 list[iod->npages++] = prp_list;
7523d834
MW		 705 prp_list[0] = old_prp_list[i - 1];
706 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
707 i = 1;
e025344c
SMM		 708 }
709 prp_list[i++] = cpu_to_le64(dma_addr);
1d090624
KB		 710 dma_len -= page_size;
711 dma_addr += page_size;
712 length -= page_size;
e025344c
SMM		 713 if (length <= 0)
714 break;
715 if (dma_len > 0)
716 continue;
86eea289
KB		 717 if (unlikely(dma_len < 0))
718 goto bad_sgl;
e025344c
SMM		 719 sg = sg_next(sg);
720 dma_addr = sg_dma_address(sg);
721 dma_len = sg_dma_len(sg);
ff22b54f
MW		 722 }
723
a7a7cbe3
CK		 724done:
725 cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
726 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
727
86eea289
KB		 728 return BLK_STS_OK;
729
730 bad_sgl:
d0877473
KB		 731 WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents),
732 "Invalid SGL for payload:%d nents:%d\n",
733 blk_rq_payload_bytes(req), iod->nents);
86eea289 734 return BLK_STS_IOERR;
ff22b54f
MW		 735}
736
a7a7cbe3
CK		 737static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
738 struct scatterlist *sg)
739{
740 sge->addr = cpu_to_le64(sg_dma_address(sg));
741 sge->length = cpu_to_le32(sg_dma_len(sg));
742 sge->type = NVME_SGL_FMT_DATA_DESC << 4;
743}
744
745static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
746 dma_addr_t dma_addr, int entries)
747{
748 sge->addr = cpu_to_le64(dma_addr);
749 if (entries < SGES_PER_PAGE) {
750 sge->length = cpu_to_le32(entries * sizeof(*sge));
751 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
752 } else {
753 sge->length = cpu_to_le32(PAGE_SIZE);
754 sge->type = NVME_SGL_FMT_SEG_DESC << 4;
755 }
756}
757
758static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
b0f2853b 759 struct request *req, struct nvme_rw_command *cmd, int entries)
a7a7cbe3
CK		 760{
761 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3
CK		 762 struct dma_pool *pool;
763 struct nvme_sgl_desc *sg_list;
764 struct scatterlist *sg = iod->sg;
a7a7cbe3 765 dma_addr_t sgl_dma;
b0f2853b 766 int i = 0;
a7a7cbe3 767
a7a7cbe3
CK		 768 /* setting the transfer type as SGL */
769 cmd->flags = NVME_CMD_SGL_METABUF;
770
b0f2853b 771 if (entries == 1) {
a7a7cbe3
CK		 772 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
773 return BLK_STS_OK;
774 }
775
776 if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
777 pool = dev->prp_small_pool;
778 iod->npages = 0;
779 } else {
780 pool = dev->prp_page_pool;
781 iod->npages = 1;
782 }
783
784 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
785 if (!sg_list) {
786 iod->npages = -1;
787 return BLK_STS_RESOURCE;
788 }
789
790 nvme_pci_iod_list(req)[0] = sg_list;
791 iod->first_dma = sgl_dma;
792
793 nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
794
795 do {
796 if (i == SGES_PER_PAGE) {
797 struct nvme_sgl_desc *old_sg_desc = sg_list;
798 struct nvme_sgl_desc *link = &old_sg_desc[i - 1];
799
800 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
801 if (!sg_list)
802 return BLK_STS_RESOURCE;
803
804 i = 0;
805 nvme_pci_iod_list(req)[iod->npages++] = sg_list;
806 sg_list[i++] = *link;
807 nvme_pci_sgl_set_seg(link, sgl_dma, entries);
808 }
809
810 nvme_pci_sgl_set_data(&sg_list[i++], sg);
a7a7cbe3 811 sg = sg_next(sg);
b0f2853b 812 } while (--entries > 0);
a7a7cbe3 813
a7a7cbe3
CK		 814 return BLK_STS_OK;
815}
816
fc17b653 817static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
b131c61d 818 struct nvme_command *cmnd)
d29ec824 819{
f4800d6d 820 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
ba1ca37e
CH		 821 struct request_queue *q = req->q;
822 enum dma_data_direction dma_dir = rq_data_dir(req) ?
823 DMA_TO_DEVICE : DMA_FROM_DEVICE;
fc17b653 824 blk_status_t ret = BLK_STS_IOERR;
b0f2853b 825 int nr_mapped;
d29ec824 826
9b048119
CH		 827 if (blk_rq_payload_bytes(req) > NVME_INT_BYTES(dev) ||
828 blk_rq_nr_phys_segments(req) > NVME_INT_PAGES) {
829 iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC);
830 if (!iod->sg)
831 return BLK_STS_RESOURCE;
832 } else {
833 iod->sg = iod->inline_sg;
834 }
835
836 iod->use_sgl = nvme_pci_use_sgls(dev, req);
837
f9d03f96 838 sg_init_table(iod->sg, blk_rq_nr_phys_segments(req));
ba1ca37e
CH		 839 iod->nents = blk_rq_map_sg(q, req, iod->sg);
840 if (!iod->nents)
841 goto out;
d29ec824 842
fc17b653 843 ret = BLK_STS_RESOURCE;
e0596ab2
LG		 844
845 if (is_pci_p2pdma_page(sg_page(iod->sg)))
846 nr_mapped = pci_p2pdma_map_sg(dev->dev, iod->sg, iod->nents,
847 dma_dir);
848 else
849 nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents,
850 dma_dir, DMA_ATTR_NO_WARN);
b0f2853b 851 if (!nr_mapped)
ba1ca37e 852 goto out;
d29ec824 853
955b1b5a 854 if (iod->use_sgl)
b0f2853b 855 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped);
a7a7cbe3
CK		 856 else
857 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
858
86eea289 859 if (ret != BLK_STS_OK)
7fe07d14 860 goto out;
0e5e4f0e 861
fc17b653 862 ret = BLK_STS_IOERR;
ba1ca37e
CH		 863 if (blk_integrity_rq(req)) {
864 if (blk_rq_count_integrity_sg(q, req->bio) != 1)
7fe07d14 865 goto out;
0e5e4f0e 866
bf684057
CH		 867 sg_init_table(&iod->meta_sg, 1);
868 if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1)
7fe07d14 869 goto out;
0e5e4f0e 870
bf684057 871 if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir))
7fe07d14 872 goto out;
00df5cb4 873
bf684057 874 cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg));
3045c0d0
CK		 875 }
876
fc17b653 877 return BLK_STS_OK;
00df5cb4 878
ba1ca37e 879out:
7fe07d14 880 nvme_unmap_data(dev, req);
ba1ca37e 881 return ret;
00df5cb4
MW		 882}
883
d29ec824
CH		 884/*
885 * NOTE: ns is NULL when called on the admin queue.
886 */
fc17b653 887static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
a4aea562 888 const struct blk_mq_queue_data *bd)
edd10d33 889{
a4aea562
MB		 890 struct nvme_ns *ns = hctx->queue->queuedata;
891 struct nvme_queue *nvmeq = hctx->driver_data;
d29ec824 892 struct nvme_dev *dev = nvmeq->dev;
a4aea562 893 struct request *req = bd->rq;
9b048119 894 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
ba1ca37e 895 struct nvme_command cmnd;
ebe6d874 896 blk_status_t ret;
e1e5e564 897
9b048119
CH		 898 iod->aborted = 0;
899 iod->npages = -1;
900 iod->nents = 0;
901
d1f06f4a
JA		 902 /*
903 * We should not need to do this, but we're still using this to
904 * ensure we can drain requests on a dying queue.
905 */
4e224106 906 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
d1f06f4a
JA		 907 return BLK_STS_IOERR;
908
f9d03f96 909 ret = nvme_setup_cmd(ns, req, &cmnd);
fc17b653 910 if (ret)
f4800d6d 911 return ret;
a4aea562 912
fc17b653 913 if (blk_rq_nr_phys_segments(req)) {
b131c61d 914 ret = nvme_map_data(dev, req, &cmnd);
fc17b653 915 if (ret)
9b048119 916 goto out_free_cmd;
fc17b653 917 }
a4aea562 918
aae239e1 919 blk_mq_start_request(req);
04f3eafd 920 nvme_submit_cmd(nvmeq, &cmnd, bd->last);
fc17b653 921 return BLK_STS_OK;
f9d03f96
CH		 922out_free_cmd:
923 nvme_cleanup_cmd(req);
ba1ca37e 924 return ret;
b60503ba 925}
e1e5e564 926
77f02a7a 927static void nvme_pci_complete_rq(struct request *req)
eee417b0 928{
f4800d6d 929 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a4aea562 930
915f04c9 931 nvme_cleanup_cmd(req);
b15c592d
CH		 932 if (blk_rq_nr_phys_segments(req))
933 nvme_unmap_data(iod->nvmeq->dev, req);
77f02a7a 934 nvme_complete_rq(req);
b60503ba
MW		 935}
936
d783e0bd 937/* We read the CQE phase first to check if the rest of the entry is valid */
750dde44 938static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq)
d783e0bd 939{
750dde44
CH		 940 return (le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) ==
941 nvmeq->cq_phase;
d783e0bd
MR		 942}
943
eb281c82 944static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
b60503ba 945{
eb281c82 946 u16 head = nvmeq->cq_head;
adf68f21 947
397c699f
KB		 948 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
949 nvmeq->dbbuf_cq_ei))
950 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
eb281c82 951}
aae239e1 952
5cb525c8 953static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx)
83a12fb7 954{
5cb525c8 955 volatile struct nvme_completion *cqe = &nvmeq->cqes[idx];
83a12fb7 956 struct request *req;
adf68f21 957
83a12fb7
SG		 958 if (unlikely(cqe->command_id >= nvmeq->q_depth)) {
959 dev_warn(nvmeq->dev->ctrl.device,
960 "invalid id %d completed on queue %d\n",
961 cqe->command_id, le16_to_cpu(cqe->sq_id));
962 return;
b60503ba
MW		 963 }
964
83a12fb7
SG		 965 /*
966 * AEN requests are special as they don't time out and can
967 * survive any kind of queue freeze and often don't respond to
968 * aborts. We don't even bother to allocate a struct request
969 * for them but rather special case them here.
970 */
971 if (unlikely(nvmeq->qid == 0 &&
38dabe21 972 cqe->command_id >= NVME_AQ_BLK_MQ_DEPTH)) {
83a12fb7
SG		 973 nvme_complete_async_event(&nvmeq->dev->ctrl,
974 cqe->status, &cqe->result);
a0fa9647 975 return;
83a12fb7 976 }
b60503ba 977
83a12fb7 978 req = blk_mq_tag_to_rq(*nvmeq->tags, cqe->command_id);
604c01d5 979 trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail);
83a12fb7
SG		 980 nvme_end_request(req, cqe->status, cqe->result);
981}
b60503ba 982
5cb525c8 983static void nvme_complete_cqes(struct nvme_queue *nvmeq, u16 start, u16 end)
b60503ba 984{
5cb525c8
JA		 985 while (start != end) {
986 nvme_handle_cqe(nvmeq, start);
987 if (++start == nvmeq->q_depth)
988 start = 0;
989 }
990}
adf68f21 991
5cb525c8
JA		 992static inline void nvme_update_cq_head(struct nvme_queue *nvmeq)
993{
dcca1662 994 if (nvmeq->cq_head == nvmeq->q_depth - 1) {
5cb525c8
JA		 995 nvmeq->cq_head = 0;
996 nvmeq->cq_phase = !nvmeq->cq_phase;
dcca1662
HY		 997 } else {
998 nvmeq->cq_head++;
b60503ba 999 }
a0fa9647
JA		 1000}
1001
1052b8ac
JA		 1002static inline int nvme_process_cq(struct nvme_queue *nvmeq, u16 *start,
1003 u16 *end, unsigned int tag)
a0fa9647 1004{
1052b8ac 1005 int found = 0;
b60503ba 1006
5cb525c8 1007 *start = nvmeq->cq_head;
1052b8ac
JA		 1008 while (nvme_cqe_pending(nvmeq)) {
1009 if (tag == -1U || nvmeq->cqes[nvmeq->cq_head].command_id == tag)
1010 found++;
5cb525c8 1011 nvme_update_cq_head(nvmeq);
920d13a8 1012 }
5cb525c8 1013 *end = nvmeq->cq_head;
eb281c82 1014
5cb525c8 1015 if (*start != *end)
920d13a8 1016 nvme_ring_cq_doorbell(nvmeq);
5cb525c8 1017 return found;
b60503ba
MW		 1018}
1019
1020static irqreturn_t nvme_irq(int irq, void *data)
58ffacb5 1021{
58ffacb5 1022 struct nvme_queue *nvmeq = data;
68fa9dbe 1023 irqreturn_t ret = IRQ_NONE;
5cb525c8
JA		 1024 u16 start, end;
1025
3a7afd8e
CH		 1026 /*
1027 * The rmb/wmb pair ensures we see all updates from a previous run of
1028 * the irq handler, even if that was on another CPU.
1029 */
1030 rmb();
68fa9dbe
JA		 1031 if (nvmeq->cq_head != nvmeq->last_cq_head)
1032 ret = IRQ_HANDLED;
5cb525c8 1033 nvme_process_cq(nvmeq, &start, &end, -1);
68fa9dbe 1034 nvmeq->last_cq_head = nvmeq->cq_head;
3a7afd8e 1035 wmb();
5cb525c8 1036
68fa9dbe
JA		 1037 if (start != end) {
1038 nvme_complete_cqes(nvmeq, start, end);
1039 return IRQ_HANDLED;
1040 }
1041
1042 return ret;
58ffacb5
MW		 1043}
1044
1045static irqreturn_t nvme_irq_check(int irq, void *data)
1046{
1047 struct nvme_queue *nvmeq = data;
750dde44 1048 if (nvme_cqe_pending(nvmeq))
d783e0bd
MR		 1049 return IRQ_WAKE_THREAD;
1050 return IRQ_NONE;
58ffacb5
MW		 1051}
1052
0b2a8a9f
CH		 1053/*
1054 * Poll for completions any queue, including those not dedicated to polling.
1055 * Can be called from any context.
1056 */
1057static int nvme_poll_irqdisable(struct nvme_queue *nvmeq, unsigned int tag)
a0fa9647 1058{
3a7afd8e 1059 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
5cb525c8 1060 u16 start, end;
1052b8ac 1061 int found;
a0fa9647 1062
3a7afd8e
CH		 1063 /*
1064 * For a poll queue we need to protect against the polling thread
1065 * using the CQ lock. For normal interrupt driven threads we have
1066 * to disable the interrupt to avoid racing with it.
1067 */
7c349dde 1068 if (test_bit(NVMEQ_POLLED, &nvmeq->flags)) {
3a7afd8e 1069 spin_lock(&nvmeq->cq_poll_lock);
91a509f8 1070 found = nvme_process_cq(nvmeq, &start, &end, tag);
3a7afd8e 1071 spin_unlock(&nvmeq->cq_poll_lock);
91a509f8
CH		 1072 } else {
1073 disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1074 found = nvme_process_cq(nvmeq, &start, &end, tag);
3a7afd8e 1075 enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
91a509f8 1076 }
442e19b7 1077
5cb525c8 1078 nvme_complete_cqes(nvmeq, start, end);
442e19b7 1079 return found;
a0fa9647
JA		 1080}
1081
9743139c 1082static int nvme_poll(struct blk_mq_hw_ctx *hctx)
dabcefab
JA		 1083{
1084 struct nvme_queue *nvmeq = hctx->driver_data;
1085 u16 start, end;
1086 bool found;
1087
1088 if (!nvme_cqe_pending(nvmeq))
1089 return 0;
1090
3a7afd8e 1091 spin_lock(&nvmeq->cq_poll_lock);
9743139c 1092 found = nvme_process_cq(nvmeq, &start, &end, -1);
3a7afd8e 1093 spin_unlock(&nvmeq->cq_poll_lock);
dabcefab
JA		 1094
1095 nvme_complete_cqes(nvmeq, start, end);
1096 return found;
1097}
1098
ad22c355 1099static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
b60503ba 1100{
f866fc42 1101 struct nvme_dev *dev = to_nvme_dev(ctrl);
147b27e4 1102 struct nvme_queue *nvmeq = &dev->queues[0];
a4aea562 1103 struct nvme_command c;
b60503ba 1104
a4aea562
MB		 1105 memset(&c, 0, sizeof(c));
1106 c.common.opcode = nvme_admin_async_event;
ad22c355 1107 c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
04f3eafd 1108 nvme_submit_cmd(nvmeq, &c, true);
f705f837
CH		 1109}
1110
b60503ba 1111static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
f705f837 1112{
b60503ba
MW		 1113 struct nvme_command c;
1114
1115 memset(&c, 0, sizeof(c));
1116 c.delete_queue.opcode = opcode;
1117 c.delete_queue.qid = cpu_to_le16(id);
1118
1c63dc66 1119 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1120}
1121
b60503ba 1122static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
a8e3e0bb 1123 struct nvme_queue *nvmeq, s16 vector)
b60503ba 1124{
b60503ba 1125 struct nvme_command c;
4b04cc6a
JA		 1126 int flags = NVME_QUEUE_PHYS_CONTIG;
1127
7c349dde 1128 if (!test_bit(NVMEQ_POLLED, &nvmeq->flags))
4b04cc6a 1129 flags |= NVME_CQ_IRQ_ENABLED;
b60503ba 1130
d29ec824 1131 /*
16772ae6 1132 * Note: we (ab)use the fact that the prp fields survive if no data
d29ec824
CH		 1133 * is attached to the request.
1134 */
b60503ba
MW		 1135 memset(&c, 0, sizeof(c));
1136 c.create_cq.opcode = nvme_admin_create_cq;
1137 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1138 c.create_cq.cqid = cpu_to_le16(qid);
1139 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1140 c.create_cq.cq_flags = cpu_to_le16(flags);
7c349dde 1141 c.create_cq.irq_vector = cpu_to_le16(vector);
b60503ba 1142
1c63dc66 1143 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1144}
1145
1146static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1147 struct nvme_queue *nvmeq)
1148{
9abd68ef 1149 struct nvme_ctrl *ctrl = &dev->ctrl;
b60503ba 1150 struct nvme_command c;
81c1cd98 1151 int flags = NVME_QUEUE_PHYS_CONTIG;
b60503ba 1152
9abd68ef
JA		 1153 /*
1154 * Some drives have a bug that auto-enables WRRU if MEDIUM isn't
1155 * set. Since URGENT priority is zeroes, it makes all queues
1156 * URGENT.
1157 */
1158 if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ)
1159 flags |= NVME_SQ_PRIO_MEDIUM;
1160
d29ec824 1161 /*
16772ae6 1162 * Note: we (ab)use the fact that the prp fields survive if no data
d29ec824
CH		 1163 * is attached to the request.
1164 */
b60503ba
MW		 1165 memset(&c, 0, sizeof(c));
1166 c.create_sq.opcode = nvme_admin_create_sq;
1167 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1168 c.create_sq.sqid = cpu_to_le16(qid);
1169 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1170 c.create_sq.sq_flags = cpu_to_le16(flags);
1171 c.create_sq.cqid = cpu_to_le16(qid);
1172
1c63dc66 1173 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1174}
1175
1176static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1177{
1178 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1179}
1180
1181static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1182{
1183 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1184}
1185
2a842aca 1186static void abort_endio(struct request *req, blk_status_t error)
bc5fc7e4 1187{
f4800d6d
CH		 1188 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1189 struct nvme_queue *nvmeq = iod->nvmeq;
e44ac588 1190
27fa9bc5
CH		 1191 dev_warn(nvmeq->dev->ctrl.device,
1192 "Abort status: 0x%x", nvme_req(req)->status);
e7a2a87d 1193 atomic_inc(&nvmeq->dev->ctrl.abort_limit);
e7a2a87d 1194 blk_mq_free_request(req);
bc5fc7e4
MW		 1195}
1196
b2a0eb1a
KB		 1197static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1198{
1199
1200 /* If true, indicates loss of adapter communication, possibly by a
1201 * NVMe Subsystem reset.
1202 */
1203 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1204
ad70062c
JW		 1205 /* If there is a reset/reinit ongoing, we shouldn't reset again. */
1206 switch (dev->ctrl.state) {
1207 case NVME_CTRL_RESETTING:
ad6a0a52 1208 case NVME_CTRL_CONNECTING:
b2a0eb1a 1209 return false;
ad70062c
JW		 1210 default:
1211 break;
1212 }
b2a0eb1a
KB		 1213
1214 /* We shouldn't reset unless the controller is on fatal error state
1215 * _or_ if we lost the communication with it.
1216 */
1217 if (!(csts & NVME_CSTS_CFS) && !nssro)
1218 return false;
1219
b2a0eb1a
KB		 1220 return true;
1221}
1222
1223static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1224{
1225 /* Read a config register to help see what died. */
1226 u16 pci_status;
1227 int result;
1228
1229 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1230 &pci_status);
1231 if (result == PCIBIOS_SUCCESSFUL)
1232 dev_warn(dev->ctrl.device,
1233 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1234 csts, pci_status);
1235 else
1236 dev_warn(dev->ctrl.device,
1237 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1238 csts, result);
1239}
1240
31c7c7d2 1241static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
c30341dc 1242{
f4800d6d
CH		 1243 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1244 struct nvme_queue *nvmeq = iod->nvmeq;
c30341dc 1245 struct nvme_dev *dev = nvmeq->dev;
a4aea562 1246 struct request *abort_req;
a4aea562 1247 struct nvme_command cmd;
b2a0eb1a
KB		 1248 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1249
651438bb
WX		 1250 /* If PCI error recovery process is happening, we cannot reset or
1251 * the recovery mechanism will surely fail.
1252 */
1253 mb();
1254 if (pci_channel_offline(to_pci_dev(dev->dev)))
1255 return BLK_EH_RESET_TIMER;
1256
b2a0eb1a
KB		 1257 /*
1258 * Reset immediately if the controller is failed
1259 */
1260 if (nvme_should_reset(dev, csts)) {
1261 nvme_warn_reset(dev, csts);
1262 nvme_dev_disable(dev, false);
d86c4d8e 1263 nvme_reset_ctrl(&dev->ctrl);
db8c48e4 1264 return BLK_EH_DONE;
b2a0eb1a 1265 }
c30341dc 1266
7776db1c
KB		 1267 /*
1268 * Did we miss an interrupt?
1269 */
0b2a8a9f 1270 if (nvme_poll_irqdisable(nvmeq, req->tag)) {
7776db1c
KB		 1271 dev_warn(dev->ctrl.device,
1272 "I/O %d QID %d timeout, completion polled\n",
1273 req->tag, nvmeq->qid);
db8c48e4 1274 return BLK_EH_DONE;
7776db1c
KB		 1275 }
1276
31c7c7d2 1277 /*
fd634f41
CH		 1278 * Shutdown immediately if controller times out while starting. The
1279 * reset work will see the pci device disabled when it gets the forced
1280 * cancellation error. All outstanding requests are completed on
db8c48e4 1281 * shutdown, so we return BLK_EH_DONE.
fd634f41 1282 */
4244140d
KB		 1283 switch (dev->ctrl.state) {
1284 case NVME_CTRL_CONNECTING:
1285 case NVME_CTRL_RESETTING:
b9cac43c 1286 dev_warn_ratelimited(dev->ctrl.device,
fd634f41
CH		 1287 "I/O %d QID %d timeout, disable controller\n",
1288 req->tag, nvmeq->qid);
a5cdb68c 1289 nvme_dev_disable(dev, false);
27fa9bc5 1290 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
db8c48e4 1291 return BLK_EH_DONE;
4244140d
KB		 1292 default:
1293 break;
c30341dc
KB		 1294 }
1295
fd634f41
CH		 1296 /*
1297 * Shutdown the controller immediately and schedule a reset if the
1298 * command was already aborted once before and still hasn't been
1299 * returned to the driver, or if this is the admin queue.
31c7c7d2 1300 */
f4800d6d 1301 if (!nvmeq->qid || iod->aborted) {
1b3c47c1 1302 dev_warn(dev->ctrl.device,
e1569a16
KB		 1303 "I/O %d QID %d timeout, reset controller\n",
1304 req->tag, nvmeq->qid);
a5cdb68c 1305 nvme_dev_disable(dev, false);
d86c4d8e 1306 nvme_reset_ctrl(&dev->ctrl);
c30341dc 1307
27fa9bc5 1308 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
db8c48e4 1309 return BLK_EH_DONE;
c30341dc 1310 }
c30341dc 1311
e7a2a87d 1312 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
6bf25d16 1313 atomic_inc(&dev->ctrl.abort_limit);
31c7c7d2 1314 return BLK_EH_RESET_TIMER;
6bf25d16 1315 }
7bf7d778 1316 iod->aborted = 1;
a4aea562 1317
c30341dc
KB		 1318 memset(&cmd, 0, sizeof(cmd));
1319 cmd.abort.opcode = nvme_admin_abort_cmd;
a4aea562 1320 cmd.abort.cid = req->tag;
c30341dc 1321 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
c30341dc 1322
1b3c47c1
SG		 1323 dev_warn(nvmeq->dev->ctrl.device,
1324 "I/O %d QID %d timeout, aborting\n",
1325 req->tag, nvmeq->qid);
e7a2a87d
CH		 1326
1327 abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
eb71f435 1328 BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
e7a2a87d
CH		 1329 if (IS_ERR(abort_req)) {
1330 atomic_inc(&dev->ctrl.abort_limit);
1331 return BLK_EH_RESET_TIMER;
1332 }
1333
1334 abort_req->timeout = ADMIN_TIMEOUT;
1335 abort_req->end_io_data = NULL;
1336 blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio);
c30341dc 1337
31c7c7d2
CH		 1338 /*
1339 * The aborted req will be completed on receiving the abort req.
1340 * We enable the timer again. If hit twice, it'll cause a device reset,
1341 * as the device then is in a faulty state.
1342 */
1343 return BLK_EH_RESET_TIMER;
c30341dc
KB		 1344}
1345
a4aea562
MB		 1346static void nvme_free_queue(struct nvme_queue *nvmeq)
1347{
88a041f4 1348 dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq->q_depth),
9e866774 1349 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
63223078
CH		 1350 if (!nvmeq->sq_cmds)
1351 return;
0f238ff5 1352
63223078 1353 if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) {
88a041f4 1354 pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev),
63223078
CH		 1355 nvmeq->sq_cmds, SQ_SIZE(nvmeq->q_depth));
1356 } else {
88a041f4 1357 dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq->q_depth),
63223078 1358 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
0f238ff5 1359 }
9e866774
MW		 1360}
1361
a1a5ef99 1362static void nvme_free_queues(struct nvme_dev *dev, int lowest)
22404274
KB		 1363{
1364 int i;
1365
d858e5f0 1366 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
d858e5f0 1367 dev->ctrl.queue_count--;
147b27e4 1368 nvme_free_queue(&dev->queues[i]);
121c7ad4 1369 }
22404274
KB		 1370}
1371
4d115420
KB		 1372/**
1373 * nvme_suspend_queue - put queue into suspended state
40581d1a 1374 * @nvmeq: queue to suspend
4d115420
KB		 1375 */
1376static int nvme_suspend_queue(struct nvme_queue *nvmeq)
b60503ba 1377{
4e224106 1378 if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags))
2b25d981 1379 return 1;
a09115b2 1380
4e224106 1381 /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */
d1f06f4a 1382 mb();
a09115b2 1383
4e224106 1384 nvmeq->dev->online_queues--;
1c63dc66 1385 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
c81545f9 1386 blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q);
7c349dde
KB		 1387 if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags))
1388 pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq);
4d115420
KB		 1389 return 0;
1390}
b60503ba 1391
8fae268b
KB		 1392static void nvme_suspend_io_queues(struct nvme_dev *dev)
1393{
1394 int i;
1395
1396 for (i = dev->ctrl.queue_count - 1; i > 0; i--)
1397 nvme_suspend_queue(&dev->queues[i]);
1398}
1399
a5cdb68c 1400static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
4d115420 1401{
147b27e4 1402 struct nvme_queue *nvmeq = &dev->queues[0];
4d115420 1403
a5cdb68c
KB		 1404 if (shutdown)
1405 nvme_shutdown_ctrl(&dev->ctrl);
1406 else
20d0dfe6 1407 nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap);
07836e65 1408
0b2a8a9f 1409 nvme_poll_irqdisable(nvmeq, -1);
b60503ba
MW		 1410}
1411
8ffaadf7
JD		 1412static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1413 int entry_size)
1414{
1415 int q_depth = dev->q_depth;
5fd4ce1b
CH		 1416 unsigned q_size_aligned = roundup(q_depth * entry_size,
1417 dev->ctrl.page_size);
8ffaadf7
JD		 1418
1419 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
c45f5c99 1420 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
5fd4ce1b 1421 mem_per_q = round_down(mem_per_q, dev->ctrl.page_size);
c45f5c99 1422 q_depth = div_u64(mem_per_q, entry_size);
8ffaadf7
JD		 1423
1424 /*
1425 * Ensure the reduced q_depth is above some threshold where it
1426 * would be better to map queues in system memory with the
1427 * original depth
1428 */
1429 if (q_depth < 64)
1430 return -ENOMEM;
1431 }
1432
1433 return q_depth;
1434}
1435
1436static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1437 int qid, int depth)
1438{
0f238ff5
LG		 1439 struct pci_dev *pdev = to_pci_dev(dev->dev);
1440
1441 if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
1442 nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(depth));
1443 nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev,
1444 nvmeq->sq_cmds);
63223078
CH		 1445 if (nvmeq->sq_dma_addr) {
1446 set_bit(NVMEQ_SQ_CMB, &nvmeq->flags);
1447 return 0;
1448 }
0f238ff5 1449 }
8ffaadf7 1450
63223078
CH		 1451 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
1452 &nvmeq->sq_dma_addr, GFP_KERNEL);
815c6704
KB		 1453 if (!nvmeq->sq_cmds)
1454 return -ENOMEM;
8ffaadf7
JD		 1455 return 0;
1456}
1457
a6ff7262 1458static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
b60503ba 1459{
147b27e4 1460 struct nvme_queue *nvmeq = &dev->queues[qid];
b60503ba 1461
62314e40
KB		 1462 if (dev->ctrl.queue_count > qid)
1463 return 0;
b60503ba 1464
750afb08
LC		 1465 nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(depth),
1466 &nvmeq->cq_dma_addr, GFP_KERNEL);
b60503ba
MW		 1467 if (!nvmeq->cqes)
1468 goto free_nvmeq;
b60503ba 1469
8ffaadf7 1470 if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth))
b60503ba
MW		 1471 goto free_cqdma;
1472
091b6092 1473 nvmeq->dev = dev;
1ab0cd69 1474 spin_lock_init(&nvmeq->sq_lock);
3a7afd8e 1475 spin_lock_init(&nvmeq->cq_poll_lock);
b60503ba 1476 nvmeq->cq_head = 0;
82123460 1477 nvmeq->cq_phase = 1;
b80d5ccc 1478 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
b60503ba 1479 nvmeq->q_depth = depth;
c30341dc 1480 nvmeq->qid = qid;
d858e5f0 1481 dev->ctrl.queue_count++;
36a7e993 1482
147b27e4 1483 return 0;
b60503ba
MW		 1484
1485 free_cqdma:
e75ec752 1486 dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes,
b60503ba
MW		 1487 nvmeq->cq_dma_addr);
1488 free_nvmeq:
147b27e4 1489 return -ENOMEM;
b60503ba
MW		 1490}
1491
dca51e78 1492static int queue_request_irq(struct nvme_queue *nvmeq)
3001082c 1493{
0ff199cb
CH		 1494 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1495 int nr = nvmeq->dev->ctrl.instance;
1496
1497 if (use_threaded_interrupts) {
1498 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1499 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1500 } else {
1501 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1502 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1503 }
3001082c
MW		 1504}
1505
22404274 1506static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
b60503ba 1507{
22404274 1508 struct nvme_dev *dev = nvmeq->dev;
b60503ba 1509
22404274 1510 nvmeq->sq_tail = 0;
04f3eafd 1511 nvmeq->last_sq_tail = 0;
22404274
KB		 1512 nvmeq->cq_head = 0;
1513 nvmeq->cq_phase = 1;
b80d5ccc 1514 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
22404274 1515 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
f9f38e33 1516 nvme_dbbuf_init(dev, nvmeq, qid);
42f61420 1517 dev->online_queues++;
3a7afd8e 1518 wmb(); /* ensure the first interrupt sees the initialization */
22404274
KB		 1519}
1520
4b04cc6a 1521static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled)
22404274
KB		 1522{
1523 struct nvme_dev *dev = nvmeq->dev;
1524 int result;
7c349dde 1525 u16 vector = 0;
3f85d50b 1526
d1ed6aa1
CH		 1527 clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
1528
22b55601
KB		 1529 /*
1530 * A queue's vector matches the queue identifier unless the controller
1531 * has only one vector available.
1532 */
4b04cc6a
JA		 1533 if (!polled)
1534 vector = dev->num_vecs == 1 ? 0 : qid;
1535 else
7c349dde 1536 set_bit(NVMEQ_POLLED, &nvmeq->flags);
4b04cc6a 1537
a8e3e0bb 1538 result = adapter_alloc_cq(dev, qid, nvmeq, vector);
ded45505
KB		 1539 if (result)
1540 return result;
b60503ba
MW		 1541
1542 result = adapter_alloc_sq(dev, qid, nvmeq);
1543 if (result < 0)
ded45505
KB		 1544 return result;
1545 else if (result)
b60503ba
MW		 1546 goto release_cq;
1547
a8e3e0bb 1548 nvmeq->cq_vector = vector;
161b8be2 1549 nvme_init_queue(nvmeq, qid);
4b04cc6a 1550
7c349dde
KB		 1551 if (!polled) {
1552 nvmeq->cq_vector = vector;
4b04cc6a
JA		 1553 result = queue_request_irq(nvmeq);
1554 if (result < 0)
1555 goto release_sq;
1556 }
b60503ba 1557
4e224106 1558 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
22404274 1559 return result;
b60503ba 1560
a8e3e0bb 1561release_sq:
f25a2dfc 1562 dev->online_queues--;
b60503ba 1563 adapter_delete_sq(dev, qid);
a8e3e0bb 1564release_cq:
b60503ba 1565 adapter_delete_cq(dev, qid);
22404274 1566 return result;
b60503ba
MW		 1567}
1568
f363b089 1569static const struct blk_mq_ops nvme_mq_admin_ops = {
d29ec824 1570 .queue_rq = nvme_queue_rq,
77f02a7a 1571 .complete = nvme_pci_complete_rq,
a4aea562 1572 .init_hctx = nvme_admin_init_hctx,
4af0e21c 1573 .exit_hctx = nvme_admin_exit_hctx,
0350815a 1574 .init_request = nvme_init_request,
a4aea562
MB		 1575 .timeout = nvme_timeout,
1576};
1577
f363b089 1578static const struct blk_mq_ops nvme_mq_ops = {
376f7ef8
CH		 1579 .queue_rq = nvme_queue_rq,
1580 .complete = nvme_pci_complete_rq,
1581 .commit_rqs = nvme_commit_rqs,
1582 .init_hctx = nvme_init_hctx,
1583 .init_request = nvme_init_request,
1584 .map_queues = nvme_pci_map_queues,
1585 .timeout = nvme_timeout,
1586 .poll = nvme_poll,
dabcefab
JA		 1587};
1588
ea191d2f
KB		 1589static void nvme_dev_remove_admin(struct nvme_dev *dev)
1590{
1c63dc66 1591 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
69d9a99c
KB		 1592 /*
1593 * If the controller was reset during removal, it's possible
1594 * user requests may be waiting on a stopped queue. Start the
1595 * queue to flush these to completion.
1596 */
c81545f9 1597 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1c63dc66 1598 blk_cleanup_queue(dev->ctrl.admin_q);
ea191d2f
KB		 1599 blk_mq_free_tag_set(&dev->admin_tagset);
1600 }
1601}
1602
a4aea562
MB		 1603static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1604{
1c63dc66 1605 if (!dev->ctrl.admin_q) {
a4aea562
MB		 1606 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1607 dev->admin_tagset.nr_hw_queues = 1;
e3e9d50c 1608
38dabe21 1609 dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH;
a4aea562 1610 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
e75ec752 1611 dev->admin_tagset.numa_node = dev_to_node(dev->dev);
a7a7cbe3 1612 dev->admin_tagset.cmd_size = nvme_pci_cmd_size(dev, false);
d3484991 1613 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED;
a4aea562
MB		 1614 dev->admin_tagset.driver_data = dev;
1615
1616 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1617 return -ENOMEM;
34b6c231 1618 dev->ctrl.admin_tagset = &dev->admin_tagset;
a4aea562 1619
1c63dc66
CH		 1620 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1621 if (IS_ERR(dev->ctrl.admin_q)) {
a4aea562
MB		 1622 blk_mq_free_tag_set(&dev->admin_tagset);
1623 return -ENOMEM;
1624 }
1c63dc66 1625 if (!blk_get_queue(dev->ctrl.admin_q)) {
ea191d2f 1626 nvme_dev_remove_admin(dev);
1c63dc66 1627 dev->ctrl.admin_q = NULL;
ea191d2f
KB		 1628 return -ENODEV;
1629 }
0fb59cbc 1630 } else
c81545f9 1631 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
a4aea562
MB		 1632
1633 return 0;
1634}
1635
97f6ef64
XY		 1636static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1637{
1638 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1639}
1640
1641static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1642{
1643 struct pci_dev *pdev = to_pci_dev(dev->dev);
1644
1645 if (size <= dev->bar_mapped_size)
1646 return 0;
1647 if (size > pci_resource_len(pdev, 0))
1648 return -ENOMEM;
1649 if (dev->bar)
1650 iounmap(dev->bar);
1651 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1652 if (!dev->bar) {
1653 dev->bar_mapped_size = 0;
1654 return -ENOMEM;
1655 }
1656 dev->bar_mapped_size = size;
1657 dev->dbs = dev->bar + NVME_REG_DBS;
1658
1659 return 0;
1660}
1661
01ad0990 1662static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
b60503ba 1663{
ba47e386 1664 int result;
b60503ba
MW		 1665 u32 aqa;
1666 struct nvme_queue *nvmeq;
1667
97f6ef64
XY		 1668 result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1669 if (result < 0)
1670 return result;
1671
8ef2074d 1672 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
20d0dfe6 1673 NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
dfbac8c7 1674
7a67cbea
CH		 1675 if (dev->subsystem &&
1676 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1677 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
dfbac8c7 1678
20d0dfe6 1679 result = nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap);
ba47e386
MW		 1680 if (result < 0)
1681 return result;
b60503ba 1682
a6ff7262 1683 result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
147b27e4
SG		 1684 if (result)
1685 return result;
b60503ba 1686
147b27e4 1687 nvmeq = &dev->queues[0];
b60503ba
MW		 1688 aqa = nvmeq->q_depth - 1;
1689 aqa |= aqa << 16;
1690
7a67cbea
CH		 1691 writel(aqa, dev->bar + NVME_REG_AQA);
1692 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1693 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
b60503ba 1694
20d0dfe6 1695 result = nvme_enable_ctrl(&dev->ctrl, dev->ctrl.cap);
025c557a 1696 if (result)
d4875622 1697 return result;
a4aea562 1698
2b25d981 1699 nvmeq->cq_vector = 0;
161b8be2 1700 nvme_init_queue(nvmeq, 0);
dca51e78 1701 result = queue_request_irq(nvmeq);
758dd7fd 1702 if (result) {
7c349dde 1703 dev->online_queues--;
d4875622 1704 return result;
758dd7fd 1705 }
025c557a 1706
4e224106 1707 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
b60503ba
MW		 1708 return result;
1709}
1710
749941f2 1711static int nvme_create_io_queues(struct nvme_dev *dev)
42f61420 1712{
4b04cc6a 1713 unsigned i, max, rw_queues;
749941f2 1714 int ret = 0;
42f61420 1715
d858e5f0 1716 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
a6ff7262 1717 if (nvme_alloc_queue(dev, i, dev->q_depth)) {
749941f2 1718 ret = -ENOMEM;
42f61420 1719 break;
749941f2
CH		 1720 }
1721 }
42f61420 1722
d858e5f0 1723 max = min(dev->max_qid, dev->ctrl.queue_count - 1);
e20ba6e1
CH		 1724 if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) {
1725 rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] +
1726 dev->io_queues[HCTX_TYPE_READ];
4b04cc6a
JA		 1727 } else {
1728 rw_queues = max;
1729 }
1730
949928c1 1731 for (i = dev->online_queues; i <= max; i++) {
4b04cc6a
JA		 1732 bool polled = i > rw_queues;
1733
1734 ret = nvme_create_queue(&dev->queues[i], i, polled);
d4875622 1735 if (ret)
42f61420 1736 break;
27e8166c 1737 }
749941f2
CH		 1738
1739 /*
1740 * Ignore failing Create SQ/CQ commands, we can continue with less
8adb8c14
MI		 1741 * than the desired amount of queues, and even a controller without
1742 * I/O queues can still be used to issue admin commands. This might
749941f2
CH		 1743 * be useful to upgrade a buggy firmware for example.
1744 */
1745 return ret >= 0 ? 0 : ret;
b60503ba
MW		 1746}
1747
202021c1
SB		 1748static ssize_t nvme_cmb_show(struct device *dev,
1749 struct device_attribute *attr,
1750 char *buf)
1751{
1752 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
1753
c965809c 1754 return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n",
202021c1
SB		 1755 ndev->cmbloc, ndev->cmbsz);
1756}
1757static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL);
1758
88de4598 1759static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
8ffaadf7 1760{
88de4598
CH		 1761 u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
1762
1763 return 1ULL << (12 + 4 * szu);
1764}
1765
1766static u32 nvme_cmb_size(struct nvme_dev *dev)
1767{
1768 return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
1769}
1770
f65efd6d 1771static void nvme_map_cmb(struct nvme_dev *dev)
8ffaadf7 1772{
88de4598 1773 u64 size, offset;
8ffaadf7
JD		 1774 resource_size_t bar_size;
1775 struct pci_dev *pdev = to_pci_dev(dev->dev);
8969f1f8 1776 int bar;
8ffaadf7 1777
9fe5c59f
KB		 1778 if (dev->cmb_size)
1779 return;
1780
7a67cbea 1781 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
f65efd6d
CH		 1782 if (!dev->cmbsz)
1783 return;
202021c1 1784 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
8ffaadf7 1785
88de4598
CH		 1786 size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
1787 offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
8969f1f8
CH		 1788 bar = NVME_CMB_BIR(dev->cmbloc);
1789 bar_size = pci_resource_len(pdev, bar);
8ffaadf7
JD		 1790
1791 if (offset > bar_size)
f65efd6d 1792 return;
8ffaadf7
JD		 1793
1794 /*
1795 * Controllers may support a CMB size larger than their BAR,
1796 * for example, due to being behind a bridge. Reduce the CMB to
1797 * the reported size of the BAR
1798 */
1799 if (size > bar_size - offset)
1800 size = bar_size - offset;
1801
0f238ff5
LG		 1802 if (pci_p2pdma_add_resource(pdev, bar, size, offset)) {
1803 dev_warn(dev->ctrl.device,
1804 "failed to register the CMB\n");
f65efd6d 1805 return;
0f238ff5
LG		 1806 }
1807
8ffaadf7 1808 dev->cmb_size = size;
0f238ff5
LG		 1809 dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS);
1810
1811 if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) ==
1812 (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS))
1813 pci_p2pmem_publish(pdev, true);
f65efd6d
CH		 1814
1815 if (sysfs_add_file_to_group(&dev->ctrl.device->kobj,
1816 &dev_attr_cmb.attr, NULL))
1817 dev_warn(dev->ctrl.device,
1818 "failed to add sysfs attribute for CMB\n");
8ffaadf7
JD		 1819}
1820
1821static inline void nvme_release_cmb(struct nvme_dev *dev)
1822{
0f238ff5 1823 if (dev->cmb_size) {
1c78f773
MG		 1824 sysfs_remove_file_from_group(&dev->ctrl.device->kobj,
1825 &dev_attr_cmb.attr, NULL);
0f238ff5 1826 dev->cmb_size = 0;
8ffaadf7
JD		 1827 }
1828}
1829
87ad72a5
CH		 1830static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1831{
4033f35d 1832 u64 dma_addr = dev->host_mem_descs_dma;
87ad72a5 1833 struct nvme_command c;
87ad72a5
CH		 1834 int ret;
1835
87ad72a5
CH		 1836 memset(&c, 0, sizeof(c));
1837 c.features.opcode = nvme_admin_set_features;
1838 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1839 c.features.dword11 = cpu_to_le32(bits);
1840 c.features.dword12 = cpu_to_le32(dev->host_mem_size >>
1841 ilog2(dev->ctrl.page_size));
1842 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr));
1843 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr));
1844 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs);
1845
1846 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1847 if (ret) {
1848 dev_warn(dev->ctrl.device,
1849 "failed to set host mem (err %d, flags %#x).\n",
1850 ret, bits);
1851 }
87ad72a5
CH		 1852 return ret;
1853}
1854
1855static void nvme_free_host_mem(struct nvme_dev *dev)
1856{
1857 int i;
1858
1859 for (i = 0; i < dev->nr_host_mem_descs; i++) {
1860 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
1861 size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size;
1862
cc667f6d
LD		 1863 dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i],
1864 le64_to_cpu(desc->addr),
1865 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
87ad72a5
CH		 1866 }
1867
1868 kfree(dev->host_mem_desc_bufs);
1869 dev->host_mem_desc_bufs = NULL;
4033f35d
CH		 1870 dma_free_coherent(dev->dev,
1871 dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
1872 dev->host_mem_descs, dev->host_mem_descs_dma);
87ad72a5 1873 dev->host_mem_descs = NULL;
7e5dd57e 1874 dev->nr_host_mem_descs = 0;
87ad72a5
CH		 1875}
1876
92dc6895
CH		 1877static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
1878 u32 chunk_size)
9d713c2b 1879{
87ad72a5 1880 struct nvme_host_mem_buf_desc *descs;
92dc6895 1881 u32 max_entries, len;
4033f35d 1882 dma_addr_t descs_dma;
2ee0e4ed 1883 int i = 0;
87ad72a5 1884 void **bufs;
6fbcde66 1885 u64 size, tmp;
87ad72a5 1886
87ad72a5
CH		 1887 tmp = (preferred + chunk_size - 1);
1888 do_div(tmp, chunk_size);
1889 max_entries = tmp;
044a9df1
CH		 1890
1891 if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
1892 max_entries = dev->ctrl.hmmaxd;
1893
750afb08
LC		 1894 descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs),
1895 &descs_dma, GFP_KERNEL);
87ad72a5
CH		 1896 if (!descs)
1897 goto out;
1898
1899 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
1900 if (!bufs)
1901 goto out_free_descs;
1902
244a8fe4 1903 for (size = 0; size < preferred && i < max_entries; size += len) {
87ad72a5
CH		 1904 dma_addr_t dma_addr;
1905
50cdb7c6 1906 len = min_t(u64, chunk_size, preferred - size);
87ad72a5
CH		 1907 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
1908 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1909 if (!bufs[i])
1910 break;
1911
1912 descs[i].addr = cpu_to_le64(dma_addr);
1913 descs[i].size = cpu_to_le32(len / dev->ctrl.page_size);
1914 i++;
1915 }
1916
92dc6895 1917 if (!size)
87ad72a5 1918 goto out_free_bufs;
87ad72a5 1919
87ad72a5
CH		 1920 dev->nr_host_mem_descs = i;
1921 dev->host_mem_size = size;
1922 dev->host_mem_descs = descs;
4033f35d 1923 dev->host_mem_descs_dma = descs_dma;
87ad72a5
CH		 1924 dev->host_mem_desc_bufs = bufs;
1925 return 0;
1926
1927out_free_bufs:
1928 while (--i >= 0) {
1929 size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size;
1930
cc667f6d
LD		 1931 dma_free_attrs(dev->dev, size, bufs[i],
1932 le64_to_cpu(descs[i].addr),
1933 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
87ad72a5
CH		 1934 }
1935
1936 kfree(bufs);
1937out_free_descs:
4033f35d
CH		 1938 dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
1939 descs_dma);
87ad72a5 1940out:
87ad72a5
CH		 1941 dev->host_mem_descs = NULL;
1942 return -ENOMEM;
1943}
1944
92dc6895
CH		 1945static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
1946{
1947 u32 chunk_size;
1948
1949 /* start big and work our way down */
30f92d62 1950 for (chunk_size = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
044a9df1 1951 chunk_size >= max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
92dc6895
CH		 1952 chunk_size /= 2) {
1953 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
1954 if (!min || dev->host_mem_size >= min)
1955 return 0;
1956 nvme_free_host_mem(dev);
1957 }
1958 }
1959
1960 return -ENOMEM;
1961}
1962
9620cfba 1963static int nvme_setup_host_mem(struct nvme_dev *dev)
87ad72a5
CH		 1964{
1965 u64 max = (u64)max_host_mem_size_mb * SZ_1M;
1966 u64 preferred = (u64)dev->ctrl.hmpre * 4096;
1967 u64 min = (u64)dev->ctrl.hmmin * 4096;
1968 u32 enable_bits = NVME_HOST_MEM_ENABLE;
6fbcde66 1969 int ret;
87ad72a5
CH		 1970
1971 preferred = min(preferred, max);
1972 if (min > max) {
1973 dev_warn(dev->ctrl.device,
1974 "min host memory (%lld MiB) above limit (%d MiB).\n",
1975 min >> ilog2(SZ_1M), max_host_mem_size_mb);
1976 nvme_free_host_mem(dev);
9620cfba 1977 return 0;
87ad72a5
CH		 1978 }
1979
1980 /*
1981 * If we already have a buffer allocated check if we can reuse it.
1982 */
1983 if (dev->host_mem_descs) {
1984 if (dev->host_mem_size >= min)
1985 enable_bits |= NVME_HOST_MEM_RETURN;
1986 else
1987 nvme_free_host_mem(dev);
1988 }
1989
1990 if (!dev->host_mem_descs) {
92dc6895
CH		 1991 if (nvme_alloc_host_mem(dev, min, preferred)) {
1992 dev_warn(dev->ctrl.device,
1993 "failed to allocate host memory buffer.\n");
9620cfba 1994 return 0; /* controller must work without HMB */
92dc6895
CH		 1995 }
1996
1997 dev_info(dev->ctrl.device,
1998 "allocated %lld MiB host memory buffer.\n",
1999 dev->host_mem_size >> ilog2(SZ_1M));
87ad72a5
CH		 2000 }
2001
9620cfba
CH		 2002 ret = nvme_set_host_mem(dev, enable_bits);
2003 if (ret)
87ad72a5 2004 nvme_free_host_mem(dev);
9620cfba 2005 return ret;
9d713c2b
KB		 2006}
2007
612b7286
ML		 2008/*
2009 * nirqs is the number of interrupts available for write and read
2010 * queues. The core already reserved an interrupt for the admin queue.
2011 */
2012static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs)
3b6592f7 2013{
612b7286
ML		 2014 struct nvme_dev *dev = affd->priv;
2015 unsigned int nr_read_queues;
3b6592f7
JA		 2016
2017 /*
612b7286
ML		 2018 * If there is no interupt available for queues, ensure that
2019 * the default queue is set to 1. The affinity set size is
2020 * also set to one, but the irq core ignores it for this case.
2021 *
2022 * If only one interrupt is available or 'write_queue' == 0, combine
2023 * write and read queues.
2024 *
2025 * If 'write_queues' > 0, ensure it leaves room for at least one read
2026 * queue.
3b6592f7 2027 */
612b7286
ML		 2028 if (!nrirqs) {
2029 nrirqs = 1;
2030 nr_read_queues = 0;
2031 } else if (nrirqs == 1 || !write_queues) {
2032 nr_read_queues = 0;
2033 } else if (write_queues >= nrirqs) {
2034 nr_read_queues = 1;
3b6592f7 2035 } else {
612b7286 2036 nr_read_queues = nrirqs - write_queues;
3b6592f7 2037 }
612b7286
ML		 2038
2039 dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2040 affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2041 dev->io_queues[HCTX_TYPE_READ] = nr_read_queues;
2042 affd->set_size[HCTX_TYPE_READ] = nr_read_queues;
2043 affd->nr_sets = nr_read_queues ? 2 : 1;
3b6592f7
JA		 2044}
2045
6451fe73 2046static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues)
3b6592f7
JA		 2047{
2048 struct pci_dev *pdev = to_pci_dev(dev->dev);
3b6592f7 2049 struct irq_affinity affd = {
9cfef55b 2050 .pre_vectors = 1,
612b7286
ML		 2051 .calc_sets = nvme_calc_irq_sets,
2052 .priv = dev,
3b6592f7 2053 };
6451fe73
JA		 2054 unsigned int irq_queues, this_p_queues;
2055
2056 /*
2057 * Poll queues don't need interrupts, but we need at least one IO
2058 * queue left over for non-polled IO.
2059 */
2060 this_p_queues = poll_queues;
2061 if (this_p_queues >= nr_io_queues) {
2062 this_p_queues = nr_io_queues - 1;
2063 irq_queues = 1;
2064 } else {
c45b1fa2 2065 irq_queues = nr_io_queues - this_p_queues + 1;
6451fe73
JA		 2066 }
2067 dev->io_queues[HCTX_TYPE_POLL] = this_p_queues;
3b6592f7 2068
612b7286
ML		 2069 /* Initialize for the single interrupt case */
2070 dev->io_queues[HCTX_TYPE_DEFAULT] = 1;
2071 dev->io_queues[HCTX_TYPE_READ] = 0;
3b6592f7 2072
612b7286
ML		 2073 return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues,
2074 PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd);
3b6592f7
JA		 2075}
2076
8fae268b
KB		 2077static void nvme_disable_io_queues(struct nvme_dev *dev)
2078{
2079 if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq))
2080 __nvme_disable_io_queues(dev, nvme_admin_delete_cq);
2081}
2082
8d85fce7 2083static int nvme_setup_io_queues(struct nvme_dev *dev)
b60503ba 2084{
147b27e4 2085 struct nvme_queue *adminq = &dev->queues[0];
e75ec752 2086 struct pci_dev *pdev = to_pci_dev(dev->dev);
97f6ef64
XY		 2087 int result, nr_io_queues;
2088 unsigned long size;
b60503ba 2089
3b6592f7 2090 nr_io_queues = max_io_queues();
9a0be7ab
CH		 2091 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
2092 if (result < 0)
1b23484b 2093 return result;
9a0be7ab 2094
f5fa90dc 2095 if (nr_io_queues == 0)
a5229050 2096 return 0;
4e224106
CH		 2097
2098 clear_bit(NVMEQ_ENABLED, &adminq->flags);
b60503ba 2099
0f238ff5 2100 if (dev->cmb_use_sqes) {
8ffaadf7
JD		 2101 result = nvme_cmb_qdepth(dev, nr_io_queues,
2102 sizeof(struct nvme_command));
2103 if (result > 0)
2104 dev->q_depth = result;
2105 else
0f238ff5 2106 dev->cmb_use_sqes = false;
8ffaadf7
JD		 2107 }
2108
97f6ef64
XY		 2109 do {
2110 size = db_bar_size(dev, nr_io_queues);
2111 result = nvme_remap_bar(dev, size);
2112 if (!result)
2113 break;
2114 if (!--nr_io_queues)
2115 return -ENOMEM;
2116 } while (1);
2117 adminq->q_db = dev->dbs;
f1938f6e 2118
8fae268b 2119 retry:
9d713c2b 2120 /* Deregister the admin queue's interrupt */
0ff199cb 2121 pci_free_irq(pdev, 0, adminq);
9d713c2b 2122
e32efbfc
JA		 2123 /*
2124 * If we enable msix early due to not intx, disable it again before
2125 * setting up the full range we need.
2126 */
dca51e78 2127 pci_free_irq_vectors(pdev);
3b6592f7
JA		 2128
2129 result = nvme_setup_irqs(dev, nr_io_queues);
22b55601 2130 if (result <= 0)
dca51e78 2131 return -EIO;
3b6592f7 2132
22b55601 2133 dev->num_vecs = result;
4b04cc6a 2134 result = max(result - 1, 1);
e20ba6e1 2135 dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL];
fa08a396 2136
063a8096
MW		 2137 /*
2138 * Should investigate if there's a performance win from allocating
2139 * more queues than interrupt vectors; it might allow the submission
2140 * path to scale better, even if the receive path is limited by the
2141 * number of interrupts.
2142 */
dca51e78 2143 result = queue_request_irq(adminq);
7c349dde 2144 if (result)
d4875622 2145 return result;
4e224106 2146 set_bit(NVMEQ_ENABLED, &adminq->flags);
8fae268b
KB		 2147
2148 result = nvme_create_io_queues(dev);
2149 if (result || dev->online_queues < 2)
2150 return result;
2151
2152 if (dev->online_queues - 1 < dev->max_qid) {
2153 nr_io_queues = dev->online_queues - 1;
2154 nvme_disable_io_queues(dev);
2155 nvme_suspend_io_queues(dev);
2156 goto retry;
2157 }
2158 dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n",
2159 dev->io_queues[HCTX_TYPE_DEFAULT],
2160 dev->io_queues[HCTX_TYPE_READ],
2161 dev->io_queues[HCTX_TYPE_POLL]);
2162 return 0;
b60503ba
MW		 2163}
2164
2a842aca 2165static void nvme_del_queue_end(struct request *req, blk_status_t error)
a5768aa8 2166{
db3cbfff 2167 struct nvme_queue *nvmeq = req->end_io_data;
b5875222 2168
db3cbfff 2169 blk_mq_free_request(req);
d1ed6aa1 2170 complete(&nvmeq->delete_done);
a5768aa8
KB		 2171}
2172
2a842aca 2173static void nvme_del_cq_end(struct request *req, blk_status_t error)
a5768aa8 2174{
db3cbfff 2175 struct nvme_queue *nvmeq = req->end_io_data;
a5768aa8 2176
d1ed6aa1
CH		 2177 if (error)
2178 set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
db3cbfff
KB		 2179
2180 nvme_del_queue_end(req, error);
a5768aa8
KB		 2181}
2182
db3cbfff 2183static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
bda4e0fb 2184{
db3cbfff
KB		 2185 struct request_queue *q = nvmeq->dev->ctrl.admin_q;
2186 struct request *req;
2187 struct nvme_command cmd;
bda4e0fb 2188
db3cbfff
KB		 2189 memset(&cmd, 0, sizeof(cmd));
2190 cmd.delete_queue.opcode = opcode;
2191 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
bda4e0fb 2192
eb71f435 2193 req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
db3cbfff
KB		 2194 if (IS_ERR(req))
2195 return PTR_ERR(req);
bda4e0fb 2196
db3cbfff
KB		 2197 req->timeout = ADMIN_TIMEOUT;
2198 req->end_io_data = nvmeq;
2199
d1ed6aa1 2200 init_completion(&nvmeq->delete_done);
db3cbfff
KB		 2201 blk_execute_rq_nowait(q, NULL, req, false,
2202 opcode == nvme_admin_delete_cq ?
2203 nvme_del_cq_end : nvme_del_queue_end);
2204 return 0;
bda4e0fb
KB		 2205}
2206
8fae268b 2207static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode)
a5768aa8 2208{
5271edd4 2209 int nr_queues = dev->online_queues - 1, sent = 0;
db3cbfff 2210 unsigned long timeout;
a5768aa8 2211
db3cbfff 2212 retry:
5271edd4
CH		 2213 timeout = ADMIN_TIMEOUT;
2214 while (nr_queues > 0) {
2215 if (nvme_delete_queue(&dev->queues[nr_queues], opcode))
2216 break;
2217 nr_queues--;
2218 sent++;
db3cbfff 2219 }
d1ed6aa1
CH		 2220 while (sent) {
2221 struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent];
2222
2223 timeout = wait_for_completion_io_timeout(&nvmeq->delete_done,
5271edd4
CH		 2224 timeout);
2225 if (timeout == 0)
2226 return false;
d1ed6aa1
CH		 2227
2228 /* handle any remaining CQEs */
2229 if (opcode == nvme_admin_delete_cq &&
2230 !test_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags))
2231 nvme_poll_irqdisable(nvmeq, -1);
2232
2233 sent--;
5271edd4
CH		 2234 if (nr_queues)
2235 goto retry;
2236 }
2237 return true;
a5768aa8
KB		 2238}
2239
422ef0c7 2240/*
2b1b7e78 2241 * return error value only when tagset allocation failed
422ef0c7 2242 */
8d85fce7 2243static int nvme_dev_add(struct nvme_dev *dev)
b60503ba 2244{
2b1b7e78
JW		 2245 int ret;
2246
5bae7f73 2247 if (!dev->ctrl.tagset) {
376f7ef8 2248 dev->tagset.ops = &nvme_mq_ops;
ffe7704d 2249 dev->tagset.nr_hw_queues = dev->online_queues - 1;
ed92ad37
CH		 2250 dev->tagset.nr_maps = 2; /* default + read */
2251 if (dev->io_queues[HCTX_TYPE_POLL])
2252 dev->tagset.nr_maps++;
ffe7704d
KB		 2253 dev->tagset.timeout = NVME_IO_TIMEOUT;
2254 dev->tagset.numa_node = dev_to_node(dev->dev);
2255 dev->tagset.queue_depth =
a4aea562 2256 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
a7a7cbe3
CK		 2257 dev->tagset.cmd_size = nvme_pci_cmd_size(dev, false);
2258 if ((dev->ctrl.sgls & ((1 << 0) | (1 << 1))) && sgl_threshold) {
2259 dev->tagset.cmd_size = max(dev->tagset.cmd_size,
2260 nvme_pci_cmd_size(dev, true));
2261 }
ffe7704d
KB		 2262 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2263 dev->tagset.driver_data = dev;
b60503ba 2264
2b1b7e78
JW		 2265 ret = blk_mq_alloc_tag_set(&dev->tagset);
2266 if (ret) {
2267 dev_warn(dev->ctrl.device,
2268 "IO queues tagset allocation failed %d\n", ret);
2269 return ret;
2270 }
5bae7f73 2271 dev->ctrl.tagset = &dev->tagset;
f9f38e33
HK		 2272
2273 nvme_dbbuf_set(dev);
949928c1
KB		 2274 } else {
2275 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2276
2277 /* Free previously allocated queues that are no longer usable */
2278 nvme_free_queues(dev, dev->online_queues);
ffe7704d 2279 }
949928c1 2280
e1e5e564 2281 return 0;
b60503ba
MW		 2282}
2283
b00a726a 2284static int nvme_pci_enable(struct nvme_dev *dev)
0877cb0d 2285{
b00a726a 2286 int result = -ENOMEM;
e75ec752 2287 struct pci_dev *pdev = to_pci_dev(dev->dev);
0877cb0d
KB		 2288
2289 if (pci_enable_device_mem(pdev))
2290 return result;
2291
0877cb0d 2292 pci_set_master(pdev);
0877cb0d 2293
e75ec752
CH		 2294 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) &&
2295 dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32)))
052d0efa 2296 goto disable;
0877cb0d 2297
7a67cbea 2298 if (readl(dev->bar + NVME_REG_CSTS) == -1) {
0e53d180 2299 result = -ENODEV;
b00a726a 2300 goto disable;
0e53d180 2301 }
e32efbfc
JA		 2302
2303 /*
a5229050
KB		 2304 * Some devices and/or platforms don't advertise or work with INTx
2305 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2306 * adjust this later.
e32efbfc 2307 */
dca51e78
CH		 2308 result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
2309 if (result < 0)
2310 return result;
e32efbfc 2311
20d0dfe6 2312 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
7a67cbea 2313
20d0dfe6 2314 dev->q_depth = min_t(int, NVME_CAP_MQES(dev->ctrl.cap) + 1,
b27c1e68 2315 io_queue_depth);
20d0dfe6 2316 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
7a67cbea 2317 dev->dbs = dev->bar + 4096;
1f390c1f
SG		 2318
2319 /*
2320 * Temporary fix for the Apple controller found in the MacBook8,1 and
2321 * some MacBook7,1 to avoid controller resets and data loss.
2322 */
2323 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
2324 dev->q_depth = 2;
9bdcfb10
CH		 2325 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
2326 "set queue depth=%u to work around controller resets\n",
1f390c1f 2327 dev->q_depth);
d554b5e1
MP		 2328 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2329 (pdev->device == 0xa821 || pdev->device == 0xa822) &&
20d0dfe6 2330 NVME_CAP_MQES(dev->ctrl.cap) == 0) {
d554b5e1
MP		 2331 dev->q_depth = 64;
2332 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2333 "set queue depth=%u\n", dev->q_depth);
1f390c1f
SG		 2334 }
2335
f65efd6d 2336 nvme_map_cmb(dev);
202021c1 2337
a0a3408e
KB		 2338 pci_enable_pcie_error_reporting(pdev);
2339 pci_save_state(pdev);
0877cb0d
KB		 2340 return 0;
2341
2342 disable:
0877cb0d
KB		 2343 pci_disable_device(pdev);
2344 return result;
2345}
2346
2347static void nvme_dev_unmap(struct nvme_dev *dev)
b00a726a
KB		 2348{
2349 if (dev->bar)
2350 iounmap(dev->bar);
a1f447b3 2351 pci_release_mem_regions(to_pci_dev(dev->dev));
b00a726a
KB		 2352}
2353
2354static void nvme_pci_disable(struct nvme_dev *dev)
0877cb0d 2355{
e75ec752
CH		 2356 struct pci_dev *pdev = to_pci_dev(dev->dev);
2357
dca51e78 2358 pci_free_irq_vectors(pdev);
0877cb0d 2359
a0a3408e
KB		 2360 if (pci_is_enabled(pdev)) {
2361 pci_disable_pcie_error_reporting(pdev);
e75ec752 2362 pci_disable_device(pdev);
4d115420 2363 }
4d115420
KB		 2364}
2365
a5cdb68c 2366static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
b60503ba 2367{
302ad8cc
KB		 2368 bool dead = true;
2369 struct pci_dev *pdev = to_pci_dev(dev->dev);
22404274 2370
77bf25ea 2371 mutex_lock(&dev->shutdown_lock);
302ad8cc
KB		 2372 if (pci_is_enabled(pdev)) {
2373 u32 csts = readl(dev->bar + NVME_REG_CSTS);
2374
ebef7368
KB		 2375 if (dev->ctrl.state == NVME_CTRL_LIVE ||
2376 dev->ctrl.state == NVME_CTRL_RESETTING)
302ad8cc
KB		 2377 nvme_start_freeze(&dev->ctrl);
2378 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
2379 pdev->error_state != pci_channel_io_normal);
c9d3bf88 2380 }
c21377f8 2381
302ad8cc
KB		 2382 /*
2383 * Give the controller a chance to complete all entered requests if
2384 * doing a safe shutdown.
2385 */
87ad72a5
CH		 2386 if (!dead) {
2387 if (shutdown)
2388 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
9a915a5b
JW		 2389 }
2390
2391 nvme_stop_queues(&dev->ctrl);
87ad72a5 2392
64ee0ac0 2393 if (!dead && dev->ctrl.queue_count > 0) {
8fae268b 2394 nvme_disable_io_queues(dev);
a5cdb68c 2395 nvme_disable_admin_queue(dev, shutdown);
4d115420 2396 }
8fae268b
KB		 2397 nvme_suspend_io_queues(dev);
2398 nvme_suspend_queue(&dev->queues[0]);
b00a726a 2399 nvme_pci_disable(dev);
07836e65 2400
e1958e65
ML		 2401 blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
2402 blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
302ad8cc
KB		 2403
2404 /*
2405 * The driver will not be starting up queues again if shutting down so
2406 * must flush all entered requests to their failed completion to avoid
2407 * deadlocking blk-mq hot-cpu notifier.
2408 */
2409 if (shutdown)
2410 nvme_start_queues(&dev->ctrl);
77bf25ea 2411 mutex_unlock(&dev->shutdown_lock);
b60503ba
MW		 2412}
2413
091b6092
MW		 2414static int nvme_setup_prp_pools(struct nvme_dev *dev)
2415{
e75ec752 2416 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
091b6092
MW		 2417 PAGE_SIZE, PAGE_SIZE, 0);
2418 if (!dev->prp_page_pool)
2419 return -ENOMEM;
2420
99802a7a 2421 /* Optimisation for I/Os between 4k and 128k */
e75ec752 2422 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
99802a7a
MW		 2423 256, 256, 0);
2424 if (!dev->prp_small_pool) {
2425 dma_pool_destroy(dev->prp_page_pool);
2426 return -ENOMEM;
2427 }
091b6092
MW		 2428 return 0;
2429}
2430
2431static void nvme_release_prp_pools(struct nvme_dev *dev)
2432{
2433 dma_pool_destroy(dev->prp_page_pool);
99802a7a 2434 dma_pool_destroy(dev->prp_small_pool);
091b6092
MW		 2435}
2436
1673f1f0 2437static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
5e82e952 2438{
1673f1f0 2439 struct nvme_dev *dev = to_nvme_dev(ctrl);
9ac27090 2440
f9f38e33 2441 nvme_dbbuf_dma_free(dev);
e75ec752 2442 put_device(dev->dev);
4af0e21c
KB		 2443 if (dev->tagset.tags)
2444 blk_mq_free_tag_set(&dev->tagset);
1c63dc66
CH		 2445 if (dev->ctrl.admin_q)
2446 blk_put_queue(dev->ctrl.admin_q);
5e82e952 2447 kfree(dev->queues);
e286bcfc 2448 free_opal_dev(dev->ctrl.opal_dev);
943e942e 2449 mempool_destroy(dev->iod_mempool);
5e82e952
KB		 2450 kfree(dev);
2451}
2452
f58944e2
KB		 2453static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status)
2454{
237045fc 2455 dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status);
f58944e2 2456
d22524a4 2457 nvme_get_ctrl(&dev->ctrl);
69d9a99c 2458 nvme_dev_disable(dev, false);
9f9cafc1 2459 nvme_kill_queues(&dev->ctrl);
03e0f3a6 2460 if (!queue_work(nvme_wq, &dev->remove_work))
f58944e2
KB		 2461 nvme_put_ctrl(&dev->ctrl);
2462}
2463
fd634f41 2464static void nvme_reset_work(struct work_struct *work)
5e82e952 2465{
d86c4d8e
CH		 2466 struct nvme_dev *dev =
2467 container_of(work, struct nvme_dev, ctrl.reset_work);
a98e58e5 2468 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
f58944e2 2469 int result = -ENODEV;
2b1b7e78 2470 enum nvme_ctrl_state new_state = NVME_CTRL_LIVE;
5e82e952 2471
82b057ca 2472 if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING))
fd634f41 2473 goto out;
5e82e952 2474
fd634f41
CH		 2475 /*
2476 * If we're called to reset a live controller first shut it down before
2477 * moving on.
2478 */
b00a726a 2479 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
a5cdb68c 2480 nvme_dev_disable(dev, false);
5e82e952 2481
5c959d73 2482 mutex_lock(&dev->shutdown_lock);
b00a726a 2483 result = nvme_pci_enable(dev);
f0b50732 2484 if (result)
4726bcf3 2485 goto out_unlock;
f0b50732 2486
01ad0990 2487 result = nvme_pci_configure_admin_queue(dev);
f0b50732 2488 if (result)
4726bcf3 2489 goto out_unlock;
f0b50732 2490
0fb59cbc
KB		 2491 result = nvme_alloc_admin_tags(dev);
2492 if (result)
4726bcf3 2493 goto out_unlock;
b9afca3e 2494
943e942e
JA		 2495 /*
2496 * Limit the max command size to prevent iod->sg allocations going
2497 * over a single page.
2498 */
2499 dev->ctrl.max_hw_sectors = NVME_MAX_KB_SZ << 1;
2500 dev->ctrl.max_segments = NVME_MAX_SEGS;
5c959d73
KB		 2501 mutex_unlock(&dev->shutdown_lock);
2502
2503 /*
2504 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
2505 * initializing procedure here.
2506 */
2507 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
2508 dev_warn(dev->ctrl.device,
2509 "failed to mark controller CONNECTING\n");
2510 goto out;
2511 }
943e942e 2512
ce4541f4
CH		 2513 result = nvme_init_identify(&dev->ctrl);
2514 if (result)
f58944e2 2515 goto out;
ce4541f4 2516
e286bcfc
SB		 2517 if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
2518 if (!dev->ctrl.opal_dev)
2519 dev->ctrl.opal_dev =
2520 init_opal_dev(&dev->ctrl, &nvme_sec_submit);
2521 else if (was_suspend)
2522 opal_unlock_from_suspend(dev->ctrl.opal_dev);
2523 } else {
2524 free_opal_dev(dev->ctrl.opal_dev);
2525 dev->ctrl.opal_dev = NULL;
4f1244c8 2526 }
a98e58e5 2527
f9f38e33
HK		 2528 if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) {
2529 result = nvme_dbbuf_dma_alloc(dev);
2530 if (result)
2531 dev_warn(dev->dev,
2532 "unable to allocate dma for dbbuf\n");
2533 }
2534
9620cfba
CH		 2535 if (dev->ctrl.hmpre) {
2536 result = nvme_setup_host_mem(dev);
2537 if (result < 0)
2538 goto out;
2539 }
87ad72a5 2540
f0b50732 2541 result = nvme_setup_io_queues(dev);
badc34d4 2542 if (result)
f58944e2 2543 goto out;
f0b50732 2544
2659e57b
CH		 2545 /*
2546 * Keep the controller around but remove all namespaces if we don't have
2547 * any working I/O queue.
2548 */
3cf519b5 2549 if (dev->online_queues < 2) {
1b3c47c1 2550 dev_warn(dev->ctrl.device, "IO queues not created\n");
3b24774e 2551 nvme_kill_queues(&dev->ctrl);
5bae7f73 2552 nvme_remove_namespaces(&dev->ctrl);
2b1b7e78 2553 new_state = NVME_CTRL_ADMIN_ONLY;
3cf519b5 2554 } else {
25646264 2555 nvme_start_queues(&dev->ctrl);
302ad8cc 2556 nvme_wait_freeze(&dev->ctrl);
2b1b7e78
JW		 2557 /* hit this only when allocate tagset fails */
2558 if (nvme_dev_add(dev))
2559 new_state = NVME_CTRL_ADMIN_ONLY;
302ad8cc 2560 nvme_unfreeze(&dev->ctrl);
3cf519b5
CH		 2561 }
2562
2b1b7e78
JW		 2563 /*
2564 * If only admin queue live, keep it to do further investigation or
2565 * recovery.
2566 */
2567 if (!nvme_change_ctrl_state(&dev->ctrl, new_state)) {
2568 dev_warn(dev->ctrl.device,
2569 "failed to mark controller state %d\n", new_state);
bb8d261e
CH		 2570 goto out;
2571 }
92911a55 2572
d09f2b45 2573 nvme_start_ctrl(&dev->ctrl);
3cf519b5 2574 return;
f0b50732 2575
4726bcf3
KB		 2576 out_unlock:
2577 mutex_unlock(&dev->shutdown_lock);
3cf519b5 2578 out:
f58944e2 2579 nvme_remove_dead_ctrl(dev, result);
f0b50732
KB		 2580}
2581
5c8809e6 2582static void nvme_remove_dead_ctrl_work(struct work_struct *work)
9a6b9458 2583{
5c8809e6 2584 struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
e75ec752 2585 struct pci_dev *pdev = to_pci_dev(dev->dev);
9a6b9458
KB		 2586
2587 if (pci_get_drvdata(pdev))
921920ab 2588 device_release_driver(&pdev->dev);
1673f1f0 2589 nvme_put_ctrl(&dev->ctrl);
9a6b9458
KB		 2590}
2591
1c63dc66 2592static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
9ca97374 2593{
1c63dc66 2594 *val = readl(to_nvme_dev(ctrl)->bar + off);
90667892 2595 return 0;
9ca97374
TH		 2596}
2597
5fd4ce1b 2598static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
4cc06521 2599{
5fd4ce1b
CH		 2600 writel(val, to_nvme_dev(ctrl)->bar + off);
2601 return 0;
2602}
4cc06521 2603
7fd8930f
CH		 2604static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2605{
2606 *val = readq(to_nvme_dev(ctrl)->bar + off);
2607 return 0;
4cc06521
KB		 2608}
2609
97c12223
KB		 2610static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
2611{
2612 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2613
2614 return snprintf(buf, size, "%s", dev_name(&pdev->dev));
2615}
2616
1c63dc66 2617static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
1a353d85 2618 .name = "pcie",
e439bb12 2619 .module = THIS_MODULE,
e0596ab2
LG		 2620 .flags = NVME_F_METADATA_SUPPORTED |
2621 NVME_F_PCI_P2PDMA,
1c63dc66 2622 .reg_read32 = nvme_pci_reg_read32,
5fd4ce1b 2623 .reg_write32 = nvme_pci_reg_write32,
7fd8930f 2624 .reg_read64 = nvme_pci_reg_read64,
1673f1f0 2625 .free_ctrl = nvme_pci_free_ctrl,
f866fc42 2626 .submit_async_event = nvme_pci_submit_async_event,
97c12223 2627 .get_address = nvme_pci_get_address,
1c63dc66 2628};
4cc06521 2629
b00a726a
KB		 2630static int nvme_dev_map(struct nvme_dev *dev)
2631{
b00a726a
KB		 2632 struct pci_dev *pdev = to_pci_dev(dev->dev);
2633
a1f447b3 2634 if (pci_request_mem_regions(pdev, "nvme"))
b00a726a
KB		 2635 return -ENODEV;
2636
97f6ef64 2637 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
b00a726a
KB		 2638 goto release;
2639
9fa196e7 2640 return 0;
b00a726a 2641 release:
9fa196e7
MG		 2642 pci_release_mem_regions(pdev);
2643 return -ENODEV;
b00a726a
KB		 2644}
2645
8427bbc2 2646static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
ff5350a8
AL		 2647{
2648 if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
2649 /*
2650 * Several Samsung devices seem to drop off the PCIe bus
2651 * randomly when APST is on and uses the deepest sleep state.
2652 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2653 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2654 * 950 PRO 256GB", but it seems to be restricted to two Dell
2655 * laptops.
2656 */
2657 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
2658 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
2659 dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
2660 return NVME_QUIRK_NO_DEEPEST_PS;
8427bbc2
KHF		 2661 } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
2662 /*
2663 * Samsung SSD 960 EVO drops off the PCIe bus after system
467c77d4
JJ		 2664 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
2665 * within few minutes after bootup on a Coffee Lake board -
2666 * ASUS PRIME Z370-A
8427bbc2
KHF		 2667 */
2668 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
467c77d4
JJ		 2669 (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") ||
2670 dmi_match(DMI_BOARD_NAME, "PRIME Z370-A")))
8427bbc2 2671 return NVME_QUIRK_NO_APST;
ff5350a8
AL		 2672 }
2673
2674 return 0;
2675}
2676
18119775
KB		 2677static void nvme_async_probe(void *data, async_cookie_t cookie)
2678{
2679 struct nvme_dev *dev = data;
80f513b5 2680
18119775
KB		 2681 nvme_reset_ctrl_sync(&dev->ctrl);
2682 flush_work(&dev->ctrl.scan_work);
80f513b5 2683 nvme_put_ctrl(&dev->ctrl);
18119775
KB		 2684}
2685
8d85fce7 2686static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
b60503ba 2687{
a4aea562 2688 int node, result = -ENOMEM;
b60503ba 2689 struct nvme_dev *dev;
ff5350a8 2690 unsigned long quirks = id->driver_data;
943e942e 2691 size_t alloc_size;
b60503ba 2692
a4aea562
MB		 2693 node = dev_to_node(&pdev->dev);
2694 if (node == NUMA_NO_NODE)
2fa84351 2695 set_dev_node(&pdev->dev, first_memory_node);
a4aea562
MB		 2696
2697 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
b60503ba
MW		 2698 if (!dev)
2699 return -ENOMEM;
147b27e4 2700
3b6592f7
JA		 2701 dev->queues = kcalloc_node(max_queue_count(), sizeof(struct nvme_queue),
2702 GFP_KERNEL, node);
b60503ba
MW		 2703 if (!dev->queues)
2704 goto free;
2705
e75ec752 2706 dev->dev = get_device(&pdev->dev);
9a6b9458 2707 pci_set_drvdata(pdev, dev);
1c63dc66 2708
b00a726a
KB		 2709 result = nvme_dev_map(dev);
2710 if (result)
b00c9b7a 2711 goto put_pci;
b00a726a 2712
d86c4d8e 2713 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
5c8809e6 2714 INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
77bf25ea 2715 mutex_init(&dev->shutdown_lock);
b60503ba 2716
091b6092
MW		 2717 result = nvme_setup_prp_pools(dev);
2718 if (result)
b00c9b7a 2719 goto unmap;
4cc06521 2720
8427bbc2 2721 quirks |= check_vendor_combination_bug(pdev);
ff5350a8 2722
943e942e
JA		 2723 /*
2724 * Double check that our mempool alloc size will cover the biggest
2725 * command we support.
2726 */
2727 alloc_size = nvme_pci_iod_alloc_size(dev, NVME_MAX_KB_SZ,
2728 NVME_MAX_SEGS, true);
2729 WARN_ON_ONCE(alloc_size > PAGE_SIZE);
2730
2731 dev->iod_mempool = mempool_create_node(1, mempool_kmalloc,
2732 mempool_kfree,
2733 (void *) alloc_size,
2734 GFP_KERNEL, node);
2735 if (!dev->iod_mempool) {
2736 result = -ENOMEM;
2737 goto release_pools;
2738 }
2739
b6e44b4c
KB		 2740 result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
2741 quirks);
2742 if (result)
2743 goto release_mempool;
2744
1b3c47c1
SG		 2745 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
2746
80f513b5 2747 nvme_get_ctrl(&dev->ctrl);
18119775 2748 async_schedule(nvme_async_probe, dev);
4caff8fc 2749
b60503ba
MW		 2750 return 0;
2751
b6e44b4c
KB		 2752 release_mempool:
2753 mempool_destroy(dev->iod_mempool);
0877cb0d 2754 release_pools:
091b6092 2755 nvme_release_prp_pools(dev);
b00c9b7a
CJ		 2756 unmap:
2757 nvme_dev_unmap(dev);
a96d4f5c 2758 put_pci:
e75ec752 2759 put_device(dev->dev);
b60503ba
MW		 2760 free:
2761 kfree(dev->queues);
b60503ba
MW		 2762 kfree(dev);
2763 return result;
2764}
2765
775755ed 2766static void nvme_reset_prepare(struct pci_dev *pdev)
f0d54a54 2767{
a6739479 2768 struct nvme_dev *dev = pci_get_drvdata(pdev);
f263fbb8 2769 nvme_dev_disable(dev, false);
775755ed 2770}
f0d54a54 2771
775755ed
CH		 2772static void nvme_reset_done(struct pci_dev *pdev)
2773{
f263fbb8 2774 struct nvme_dev *dev = pci_get_drvdata(pdev);
79c48ccf 2775 nvme_reset_ctrl_sync(&dev->ctrl);
f0d54a54
KB		 2776}
2777
09ece142
KB		 2778static void nvme_shutdown(struct pci_dev *pdev)
2779{
2780 struct nvme_dev *dev = pci_get_drvdata(pdev);
a5cdb68c 2781 nvme_dev_disable(dev, true);
09ece142
KB		 2782}
2783
f58944e2
KB		 2784/*
2785 * The driver's remove may be called on a device in a partially initialized
2786 * state. This function must not have any dependencies on the device state in
2787 * order to proceed.
2788 */
8d85fce7 2789static void nvme_remove(struct pci_dev *pdev)
b60503ba
MW		 2790{
2791 struct nvme_dev *dev = pci_get_drvdata(pdev);
9a6b9458 2792
bb8d261e 2793 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
9a6b9458 2794 pci_set_drvdata(pdev, NULL);
0ff9d4e1 2795
6db28eda 2796 if (!pci_device_is_present(pdev)) {
0ff9d4e1 2797 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
1d39e692 2798 nvme_dev_disable(dev, true);
cb4bfda6 2799 nvme_dev_remove_admin(dev);
6db28eda 2800 }
0ff9d4e1 2801
d86c4d8e 2802 flush_work(&dev->ctrl.reset_work);
d09f2b45
SG		 2803 nvme_stop_ctrl(&dev->ctrl);
2804 nvme_remove_namespaces(&dev->ctrl);
a5cdb68c 2805 nvme_dev_disable(dev, true);
9fe5c59f 2806 nvme_release_cmb(dev);
87ad72a5 2807 nvme_free_host_mem(dev);
a4aea562 2808 nvme_dev_remove_admin(dev);
a1a5ef99 2809 nvme_free_queues(dev, 0);
d09f2b45 2810 nvme_uninit_ctrl(&dev->ctrl);
9a6b9458 2811 nvme_release_prp_pools(dev);
b00a726a 2812 nvme_dev_unmap(dev);
1673f1f0 2813 nvme_put_ctrl(&dev->ctrl);
b60503ba
MW		 2814}
2815
671a6018 2816#ifdef CONFIG_PM_SLEEP
cd638946
KB		 2817static int nvme_suspend(struct device *dev)
2818{
2819 struct pci_dev *pdev = to_pci_dev(dev);
2820 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2821
a5cdb68c 2822 nvme_dev_disable(ndev, true);
cd638946
KB		 2823 return 0;
2824}
2825
2826static int nvme_resume(struct device *dev)
2827{
2828 struct pci_dev *pdev = to_pci_dev(dev);
2829 struct nvme_dev *ndev = pci_get_drvdata(pdev);
cd638946 2830
d86c4d8e 2831 nvme_reset_ctrl(&ndev->ctrl);
9a6b9458 2832 return 0;
cd638946 2833}
671a6018 2834#endif
cd638946
KB		 2835
2836static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
b60503ba 2837
a0a3408e
KB		 2838static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
2839 pci_channel_state_t state)
2840{
2841 struct nvme_dev *dev = pci_get_drvdata(pdev);
2842
2843 /*
2844 * A frozen channel requires a reset. When detected, this method will
2845 * shutdown the controller to quiesce. The controller will be restarted
2846 * after the slot reset through driver's slot_reset callback.
2847 */
a0a3408e
KB		 2848 switch (state) {
2849 case pci_channel_io_normal:
2850 return PCI_ERS_RESULT_CAN_RECOVER;
2851 case pci_channel_io_frozen:
d011fb31
KB		 2852 dev_warn(dev->ctrl.device,
2853 "frozen state error detected, reset controller\n");
a5cdb68c 2854 nvme_dev_disable(dev, false);
a0a3408e
KB		 2855 return PCI_ERS_RESULT_NEED_RESET;
2856 case pci_channel_io_perm_failure:
d011fb31
KB		 2857 dev_warn(dev->ctrl.device,
2858 "failure state error detected, request disconnect\n");
a0a3408e
KB		 2859 return PCI_ERS_RESULT_DISCONNECT;
2860 }
2861 return PCI_ERS_RESULT_NEED_RESET;
2862}
2863
2864static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
2865{
2866 struct nvme_dev *dev = pci_get_drvdata(pdev);
2867
1b3c47c1 2868 dev_info(dev->ctrl.device, "restart after slot reset\n");
a0a3408e 2869 pci_restore_state(pdev);
d86c4d8e 2870 nvme_reset_ctrl(&dev->ctrl);
a0a3408e
KB		 2871 return PCI_ERS_RESULT_RECOVERED;
2872}
2873
2874static void nvme_error_resume(struct pci_dev *pdev)
2875{
72cd4cc2
KB		 2876 struct nvme_dev *dev = pci_get_drvdata(pdev);
2877
2878 flush_work(&dev->ctrl.reset_work);
a0a3408e
KB		 2879}
2880
1d352035 2881static const struct pci_error_handlers nvme_err_handler = {
b60503ba 2882 .error_detected = nvme_error_detected,
b60503ba
MW		 2883 .slot_reset = nvme_slot_reset,
2884 .resume = nvme_error_resume,
775755ed
CH		 2885 .reset_prepare = nvme_reset_prepare,
2886 .reset_done = nvme_reset_done,
b60503ba
MW		 2887};
2888
6eb0d698 2889static const struct pci_device_id nvme_id_table[] = {
106198ed 2890 { PCI_VDEVICE(INTEL, 0x0953),
08095e70 2891 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 2892 NVME_QUIRK_DEALLOCATE_ZEROES, },
99466e70
KB		 2893 { PCI_VDEVICE(INTEL, 0x0a53),
2894 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 2895 NVME_QUIRK_DEALLOCATE_ZEROES, },
99466e70
KB		 2896 { PCI_VDEVICE(INTEL, 0x0a54),
2897 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 2898 NVME_QUIRK_DEALLOCATE_ZEROES, },
f99cb7af
DWF		 2899 { PCI_VDEVICE(INTEL, 0x0a55),
2900 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2901 NVME_QUIRK_DEALLOCATE_ZEROES, },
50af47d0 2902 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */
9abd68ef
JA		 2903 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
2904 NVME_QUIRK_MEDIUM_PRIO_SQ },
6299358d
JD		 2905 { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */
2906 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
540c801c 2907 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */
7b210e4e
CH		 2908 .driver_data = NVME_QUIRK_IDENTIFY_CNS |
2909 NVME_QUIRK_DISABLE_WRITE_ZEROES, },
0302ae60
MP		 2910 { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */
2911 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
54adc010
GP		 2912 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
2913 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
8c97eecc
JL		 2914 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */
2915 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
015282c9
WW		 2916 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
2917 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
d554b5e1
MP		 2918 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */
2919 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2920 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */
2921 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
608cc4b1
CH		 2922 { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */
2923 .driver_data = NVME_QUIRK_LIGHTNVM, },
2924 { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */
2925 .driver_data = NVME_QUIRK_LIGHTNVM, },
ea48e877
WX		 2926 { PCI_DEVICE(0x1d1d, 0x2601), /* CNEX Granby */
2927 .driver_data = NVME_QUIRK_LIGHTNVM, },
b60503ba 2928 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
c74dc780 2929 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) },
124298bd 2930 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
b60503ba
MW		 2931 { 0, }
2932};
2933MODULE_DEVICE_TABLE(pci, nvme_id_table);
2934
2935static struct pci_driver nvme_driver = {
2936 .name = "nvme",
2937 .id_table = nvme_id_table,
2938 .probe = nvme_probe,
8d85fce7 2939 .remove = nvme_remove,
09ece142 2940 .shutdown = nvme_shutdown,
cd638946
KB		 2941 .driver = {
2942 .pm = &nvme_dev_pm_ops,
2943 },
74d986ab 2944 .sriov_configure = pci_sriov_configure_simple,
b60503ba
MW		 2945 .err_handler = &nvme_err_handler,
2946};
2947
2948static int __init nvme_init(void)
2949{
612b7286 2950 BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2);
9a6327d2 2951 return pci_register_driver(&nvme_driver);
b60503ba
MW		 2952}
2953
2954static void __exit nvme_exit(void)
2955{
2956 pci_unregister_driver(&nvme_driver);
03e0f3a6 2957 flush_workqueue(nvme_wq);
21bd78bc 2958 _nvme_check_size();
b60503ba
MW		 2959}
2960
2961MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2962MODULE_LICENSE("GPL");
c78b4713 2963MODULE_VERSION("1.0");
b60503ba
MW		 2964module_init(nvme_init);
2965module_exit(nvme_exit);
Linux 6.x block layer and io_uring tree(s)