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nvme-fabrics: check more command sizes
[linux-2.6-block.git] / drivers / nvme / host / pci.c
CommitLineData
5f37396d 1// SPDX-License-Identifier: GPL-2.0
b60503ba
MW		 2/*
3 * NVM Express device driver
6eb0d698 4 * Copyright (c) 2011-2014, Intel Corporation.
b60503ba
MW		 5 */
6
a0a3408e 7#include <linux/aer.h>
18119775 8#include <linux/async.h>
b60503ba 9#include <linux/blkdev.h>
a4aea562 10#include <linux/blk-mq.h>
dca51e78 11#include <linux/blk-mq-pci.h>
ff5350a8 12#include <linux/dmi.h>
b60503ba
MW		 13#include <linux/init.h>
14#include <linux/interrupt.h>
15#include <linux/io.h>
b60503ba
MW		 16#include <linux/mm.h>
17#include <linux/module.h>
77bf25ea 18#include <linux/mutex.h>
d0877473 19#include <linux/once.h>
b60503ba 20#include <linux/pci.h>
e1e5e564 21#include <linux/t10-pi.h>
b60503ba 22#include <linux/types.h>
2f8e2c87 23#include <linux/io-64-nonatomic-lo-hi.h>
a98e58e5 24#include <linux/sed-opal.h>
0f238ff5 25#include <linux/pci-p2pdma.h>
797a796a 26
604c01d5 27#include "trace.h"
f11bb3e2
CH		 28#include "nvme.h"
29
b60503ba
MW		 30#define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
31#define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
c965809c 32
a7a7cbe3 33#define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc))
9d43cf64 34
943e942e
JA		 35/*
36 * These can be higher, but we need to ensure that any command doesn't
37 * require an sg allocation that needs more than a page of data.
38 */
39#define NVME_MAX_KB_SZ 4096
40#define NVME_MAX_SEGS 127
41
58ffacb5
MW		 42static int use_threaded_interrupts;
43module_param(use_threaded_interrupts, int, 0);
44
8ffaadf7 45static bool use_cmb_sqes = true;
69f4eb9f 46module_param(use_cmb_sqes, bool, 0444);
8ffaadf7
JD		 47MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
48
87ad72a5
CH		 49static unsigned int max_host_mem_size_mb = 128;
50module_param(max_host_mem_size_mb, uint, 0444);
51MODULE_PARM_DESC(max_host_mem_size_mb,
52 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
1fa6aead 53
a7a7cbe3
CK		 54static unsigned int sgl_threshold = SZ_32K;
55module_param(sgl_threshold, uint, 0644);
56MODULE_PARM_DESC(sgl_threshold,
57 "Use SGLs when average request segment size is larger or equal to "
58 "this size. Use 0 to disable SGLs.");
59
b27c1e68 60static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
61static const struct kernel_param_ops io_queue_depth_ops = {
62 .set = io_queue_depth_set,
63 .get = param_get_int,
64};
65
66static int io_queue_depth = 1024;
67module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
68MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2");
69
3b6592f7
JA		 70static int queue_count_set(const char *val, const struct kernel_param *kp);
71static const struct kernel_param_ops queue_count_ops = {
72 .set = queue_count_set,
73 .get = param_get_int,
74};
75
76static int write_queues;
77module_param_cb(write_queues, &queue_count_ops, &write_queues, 0644);
78MODULE_PARM_DESC(write_queues,
79 "Number of queues to use for writes. If not set, reads and writes "
80 "will share a queue set.");
81
a4668d9b 82static int poll_queues = 0;
4b04cc6a
JA		 83module_param_cb(poll_queues, &queue_count_ops, &poll_queues, 0644);
84MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO.");
85
1c63dc66
CH		 86struct nvme_dev;
87struct nvme_queue;
b3fffdef 88
a5cdb68c 89static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
8fae268b 90static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode);
d4b4ff8e 91
1c63dc66
CH		 92/*
93 * Represents an NVM Express device. Each nvme_dev is a PCI function.
94 */
95struct nvme_dev {
147b27e4 96 struct nvme_queue *queues;
1c63dc66
CH		 97 struct blk_mq_tag_set tagset;
98 struct blk_mq_tag_set admin_tagset;
99 u32 __iomem *dbs;
100 struct device *dev;
101 struct dma_pool *prp_page_pool;
102 struct dma_pool *prp_small_pool;
1c63dc66
CH		 103 unsigned online_queues;
104 unsigned max_qid;
e20ba6e1 105 unsigned io_queues[HCTX_MAX_TYPES];
22b55601 106 unsigned int num_vecs;
1c63dc66
CH		 107 int q_depth;
108 u32 db_stride;
1c63dc66 109 void __iomem *bar;
97f6ef64 110 unsigned long bar_mapped_size;
5c8809e6 111 struct work_struct remove_work;
77bf25ea 112 struct mutex shutdown_lock;
1c63dc66 113 bool subsystem;
1c63dc66 114 u64 cmb_size;
0f238ff5 115 bool cmb_use_sqes;
1c63dc66 116 u32 cmbsz;
202021c1 117 u32 cmbloc;
1c63dc66 118 struct nvme_ctrl ctrl;
87ad72a5 119
943e942e
JA		 120 mempool_t *iod_mempool;
121
87ad72a5 122 /* shadow doorbell buffer support: */
f9f38e33
HK		 123 u32 *dbbuf_dbs;
124 dma_addr_t dbbuf_dbs_dma_addr;
125 u32 *dbbuf_eis;
126 dma_addr_t dbbuf_eis_dma_addr;
87ad72a5
CH		 127
128 /* host memory buffer support: */
129 u64 host_mem_size;
130 u32 nr_host_mem_descs;
4033f35d 131 dma_addr_t host_mem_descs_dma;
87ad72a5
CH		 132 struct nvme_host_mem_buf_desc *host_mem_descs;
133 void **host_mem_desc_bufs;
4d115420 134};
1fa6aead 135
b27c1e68 136static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
137{
138 int n = 0, ret;
139
140 ret = kstrtoint(val, 10, &n);
141 if (ret != 0 || n < 2)
142 return -EINVAL;
143
144 return param_set_int(val, kp);
145}
146
3b6592f7
JA		 147static int queue_count_set(const char *val, const struct kernel_param *kp)
148{
66564867 149 int n, ret;
3b6592f7
JA		 150
151 ret = kstrtoint(val, 10, &n);
e895fedf
BVA		 152 if (ret)
153 return ret;
3b6592f7
JA		 154 if (n > num_possible_cpus())
155 n = num_possible_cpus();
156
157 return param_set_int(val, kp);
158}
159
f9f38e33
HK		 160static inline unsigned int sq_idx(unsigned int qid, u32 stride)
161{
162 return qid * 2 * stride;
163}
164
165static inline unsigned int cq_idx(unsigned int qid, u32 stride)
166{
167 return (qid * 2 + 1) * stride;
168}
169
1c63dc66
CH		 170static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
171{
172 return container_of(ctrl, struct nvme_dev, ctrl);
173}
174
b60503ba
MW		 175/*
176 * An NVM Express queue. Each device has at least two (one for admin
177 * commands and one for I/O commands).
178 */
179struct nvme_queue {
091b6092 180 struct nvme_dev *dev;
1ab0cd69 181 spinlock_t sq_lock;
b60503ba 182 struct nvme_command *sq_cmds;
3a7afd8e
CH		 183 /* only used for poll queues: */
184 spinlock_t cq_poll_lock ____cacheline_aligned_in_smp;
b60503ba 185 volatile struct nvme_completion *cqes;
42483228 186 struct blk_mq_tags **tags;
b60503ba
MW		 187 dma_addr_t sq_dma_addr;
188 dma_addr_t cq_dma_addr;
b60503ba
MW		 189 u32 __iomem *q_db;
190 u16 q_depth;
7c349dde 191 u16 cq_vector;
b60503ba 192 u16 sq_tail;
04f3eafd 193 u16 last_sq_tail;
b60503ba 194 u16 cq_head;
68fa9dbe 195 u16 last_cq_head;
c30341dc 196 u16 qid;
e9539f47 197 u8 cq_phase;
4e224106
CH		 198 unsigned long flags;
199#define NVMEQ_ENABLED 0
63223078 200#define NVMEQ_SQ_CMB 1
d1ed6aa1 201#define NVMEQ_DELETE_ERROR 2
7c349dde 202#define NVMEQ_POLLED 3
f9f38e33
HK		 203 u32 *dbbuf_sq_db;
204 u32 *dbbuf_cq_db;
205 u32 *dbbuf_sq_ei;
206 u32 *dbbuf_cq_ei;
d1ed6aa1 207 struct completion delete_done;
b60503ba
MW		 208};
209
71bd150c 210/*
9b048119
CH		 211 * The nvme_iod describes the data in an I/O.
212 *
213 * The sg pointer contains the list of PRP/SGL chunk allocations in addition
214 * to the actual struct scatterlist.
71bd150c
CH		 215 */
216struct nvme_iod {
d49187e9 217 struct nvme_request req;
f4800d6d 218 struct nvme_queue *nvmeq;
a7a7cbe3 219 bool use_sgl;
f4800d6d 220 int aborted;
71bd150c 221 int npages; /* In the PRP list. 0 means small pool in use */
71bd150c 222 int nents; /* Used in scatterlist */
71bd150c 223 dma_addr_t first_dma;
dff824b2 224 unsigned int dma_len; /* length of single DMA segment mapping */
783b94bd 225 dma_addr_t meta_dma;
f4800d6d 226 struct scatterlist *sg;
b60503ba
MW		 227};
228
229/*
230 * Check we didin't inadvertently grow the command struct
231 */
232static inline void _nvme_check_size(void)
233{
a97234e1 234 BUILD_BUG_ON(sizeof(struct nvme_common_command) != 64);
b60503ba 235 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
a97234e1 236 BUILD_BUG_ON(sizeof(struct nvme_identify) != 64);
b60503ba
MW		 237 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
238 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
239 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
240 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
a97234e1 241 BUILD_BUG_ON(sizeof(struct nvme_download_firmware) != 64);
f8ebf840 242 BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
a97234e1
MI		 243 BUILD_BUG_ON(sizeof(struct nvme_dsm_cmd) != 64);
244 BUILD_BUG_ON(sizeof(struct nvme_write_zeroes_cmd) != 64);
c30341dc 245 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
a97234e1 246 BUILD_BUG_ON(sizeof(struct nvme_get_log_page_command) != 64);
b60503ba 247 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
0add5e8e
JT		 248 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != NVME_IDENTIFY_DATA_SIZE);
249 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != NVME_IDENTIFY_DATA_SIZE);
b60503ba 250 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
6ecec745 251 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
f9f38e33 252 BUILD_BUG_ON(sizeof(struct nvme_dbbuf) != 64);
a97234e1 253 BUILD_BUG_ON(sizeof(struct nvme_directive_cmd) != 64);
f9f38e33
HK		 254}
255
3b6592f7
JA		 256static unsigned int max_io_queues(void)
257{
4b04cc6a 258 return num_possible_cpus() + write_queues + poll_queues;
3b6592f7
JA		 259}
260
261static unsigned int max_queue_count(void)
262{
263 /* IO queues + admin queue */
264 return 1 + max_io_queues();
265}
266
f9f38e33
HK		 267static inline unsigned int nvme_dbbuf_size(u32 stride)
268{
3b6592f7 269 return (max_queue_count() * 8 * stride);
f9f38e33
HK		 270}
271
272static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
273{
274 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
275
276 if (dev->dbbuf_dbs)
277 return 0;
278
279 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
280 &dev->dbbuf_dbs_dma_addr,
281 GFP_KERNEL);
282 if (!dev->dbbuf_dbs)
283 return -ENOMEM;
284 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
285 &dev->dbbuf_eis_dma_addr,
286 GFP_KERNEL);
287 if (!dev->dbbuf_eis) {
288 dma_free_coherent(dev->dev, mem_size,
289 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
290 dev->dbbuf_dbs = NULL;
291 return -ENOMEM;
292 }
293
294 return 0;
295}
296
297static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
298{
299 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
300
301 if (dev->dbbuf_dbs) {
302 dma_free_coherent(dev->dev, mem_size,
303 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
304 dev->dbbuf_dbs = NULL;
305 }
306 if (dev->dbbuf_eis) {
307 dma_free_coherent(dev->dev, mem_size,
308 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
309 dev->dbbuf_eis = NULL;
310 }
311}
312
313static void nvme_dbbuf_init(struct nvme_dev *dev,
314 struct nvme_queue *nvmeq, int qid)
315{
316 if (!dev->dbbuf_dbs || !qid)
317 return;
318
319 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
320 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
321 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
322 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
323}
324
325static void nvme_dbbuf_set(struct nvme_dev *dev)
326{
327 struct nvme_command c;
328
329 if (!dev->dbbuf_dbs)
330 return;
331
332 memset(&c, 0, sizeof(c));
333 c.dbbuf.opcode = nvme_admin_dbbuf;
334 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
335 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
336
337 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
9bdcfb10 338 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
f9f38e33
HK		 339 /* Free memory and continue on */
340 nvme_dbbuf_dma_free(dev);
341 }
342}
343
344static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
345{
346 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
347}
348
349/* Update dbbuf and return true if an MMIO is required */
350static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
351 volatile u32 *dbbuf_ei)
352{
353 if (dbbuf_db) {
354 u16 old_value;
355
356 /*
357 * Ensure that the queue is written before updating
358 * the doorbell in memory
359 */
360 wmb();
361
362 old_value = *dbbuf_db;
363 *dbbuf_db = value;
364
f1ed3df2
MW		 365 /*
366 * Ensure that the doorbell is updated before reading the event
367 * index from memory. The controller needs to provide similar
368 * ordering to ensure the envent index is updated before reading
369 * the doorbell.
370 */
371 mb();
372
f9f38e33
HK		 373 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value))
374 return false;
375 }
376
377 return true;
b60503ba
MW		 378}
379
ac3dd5bd
JA		 380/*
381 * Will slightly overestimate the number of pages needed. This is OK
382 * as it only leads to a small amount of wasted memory for the lifetime of
383 * the I/O.
384 */
385static int nvme_npages(unsigned size, struct nvme_dev *dev)
386{
5fd4ce1b
CH		 387 unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size,
388 dev->ctrl.page_size);
ac3dd5bd
JA		 389 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
390}
391
a7a7cbe3
CK		 392/*
393 * Calculates the number of pages needed for the SGL segments. For example a 4k
394 * page can accommodate 256 SGL descriptors.
395 */
396static int nvme_pci_npages_sgl(unsigned int num_seg)
ac3dd5bd 397{
a7a7cbe3 398 return DIV_ROUND_UP(num_seg * sizeof(struct nvme_sgl_desc), PAGE_SIZE);
f4800d6d 399}
ac3dd5bd 400
a7a7cbe3
CK		 401static unsigned int nvme_pci_iod_alloc_size(struct nvme_dev *dev,
402 unsigned int size, unsigned int nseg, bool use_sgl)
f4800d6d 403{
a7a7cbe3
CK		 404 size_t alloc_size;
405
406 if (use_sgl)
407 alloc_size = sizeof(__le64 *) * nvme_pci_npages_sgl(nseg);
408 else
409 alloc_size = sizeof(__le64 *) * nvme_npages(size, dev);
410
411 return alloc_size + sizeof(struct scatterlist) * nseg;
f4800d6d 412}
ac3dd5bd 413
a4aea562
MB		 414static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
415 unsigned int hctx_idx)
e85248e5 416{
a4aea562 417 struct nvme_dev *dev = data;
147b27e4 418 struct nvme_queue *nvmeq = &dev->queues[0];
a4aea562 419
42483228
KB		 420 WARN_ON(hctx_idx != 0);
421 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
422 WARN_ON(nvmeq->tags);
423
a4aea562 424 hctx->driver_data = nvmeq;
42483228 425 nvmeq->tags = &dev->admin_tagset.tags[0];
a4aea562 426 return 0;
e85248e5
MW		 427}
428
4af0e21c
KB		 429static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
430{
431 struct nvme_queue *nvmeq = hctx->driver_data;
432
433 nvmeq->tags = NULL;
434}
435
a4aea562
MB		 436static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
437 unsigned int hctx_idx)
b60503ba 438{
a4aea562 439 struct nvme_dev *dev = data;
147b27e4 440 struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
a4aea562 441
42483228
KB		 442 if (!nvmeq->tags)
443 nvmeq->tags = &dev->tagset.tags[hctx_idx];
b60503ba 444
42483228 445 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
a4aea562
MB		 446 hctx->driver_data = nvmeq;
447 return 0;
b60503ba
MW		 448}
449
d6296d39
CH		 450static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req,
451 unsigned int hctx_idx, unsigned int numa_node)
b60503ba 452{
d6296d39 453 struct nvme_dev *dev = set->driver_data;
f4800d6d 454 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
0350815a 455 int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0;
147b27e4 456 struct nvme_queue *nvmeq = &dev->queues[queue_idx];
a4aea562
MB		 457
458 BUG_ON(!nvmeq);
f4800d6d 459 iod->nvmeq = nvmeq;
59e29ce6
SG		 460
461 nvme_req(req)->ctrl = &dev->ctrl;
a4aea562
MB		 462 return 0;
463}
464
3b6592f7
JA		 465static int queue_irq_offset(struct nvme_dev *dev)
466{
467 /* if we have more than 1 vec, admin queue offsets us by 1 */
468 if (dev->num_vecs > 1)
469 return 1;
470
471 return 0;
472}
473
dca51e78
CH		 474static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
475{
476 struct nvme_dev *dev = set->driver_data;
3b6592f7
JA		 477 int i, qoff, offset;
478
479 offset = queue_irq_offset(dev);
480 for (i = 0, qoff = 0; i < set->nr_maps; i++) {
481 struct blk_mq_queue_map *map = &set->map[i];
482
483 map->nr_queues = dev->io_queues[i];
484 if (!map->nr_queues) {
e20ba6e1 485 BUG_ON(i == HCTX_TYPE_DEFAULT);
7e849dd9 486 continue;
3b6592f7
JA		 487 }
488
4b04cc6a
JA		 489 /*
490 * The poll queue(s) doesn't have an IRQ (and hence IRQ
491 * affinity), so use the regular blk-mq cpu mapping
492 */
3b6592f7 493 map->queue_offset = qoff;
e20ba6e1 494 if (i != HCTX_TYPE_POLL)
4b04cc6a
JA		 495 blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset);
496 else
497 blk_mq_map_queues(map);
3b6592f7
JA		 498 qoff += map->nr_queues;
499 offset += map->nr_queues;
500 }
501
502 return 0;
dca51e78
CH		 503}
504
04f3eafd
JA		 505/*
506 * Write sq tail if we are asked to, or if the next command would wrap.
507 */
508static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq)
509{
510 if (!write_sq) {
511 u16 next_tail = nvmeq->sq_tail + 1;
512
513 if (next_tail == nvmeq->q_depth)
514 next_tail = 0;
515 if (next_tail != nvmeq->last_sq_tail)
516 return;
517 }
518
519 if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail,
520 nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei))
521 writel(nvmeq->sq_tail, nvmeq->q_db);
522 nvmeq->last_sq_tail = nvmeq->sq_tail;
523}
524
b60503ba 525/**
90ea5ca4 526 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
b60503ba
MW		 527 * @nvmeq: The queue to use
528 * @cmd: The command to send
04f3eafd 529 * @write_sq: whether to write to the SQ doorbell
b60503ba 530 */
04f3eafd
JA		 531static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd,
532 bool write_sq)
b60503ba 533{
90ea5ca4 534 spin_lock(&nvmeq->sq_lock);
0f238ff5 535 memcpy(&nvmeq->sq_cmds[nvmeq->sq_tail], cmd, sizeof(*cmd));
90ea5ca4
CH		 536 if (++nvmeq->sq_tail == nvmeq->q_depth)
537 nvmeq->sq_tail = 0;
04f3eafd
JA		 538 nvme_write_sq_db(nvmeq, write_sq);
539 spin_unlock(&nvmeq->sq_lock);
540}
541
542static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx)
543{
544 struct nvme_queue *nvmeq = hctx->driver_data;
545
546 spin_lock(&nvmeq->sq_lock);
547 if (nvmeq->sq_tail != nvmeq->last_sq_tail)
548 nvme_write_sq_db(nvmeq, true);
90ea5ca4 549 spin_unlock(&nvmeq->sq_lock);
b60503ba
MW		 550}
551
a7a7cbe3 552static void **nvme_pci_iod_list(struct request *req)
b60503ba 553{
f4800d6d 554 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3 555 return (void **)(iod->sg + blk_rq_nr_phys_segments(req));
b60503ba
MW		 556}
557
955b1b5a
MI		 558static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req)
559{
560 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
20469a37 561 int nseg = blk_rq_nr_phys_segments(req);
955b1b5a
MI		 562 unsigned int avg_seg_size;
563
20469a37
KB		 564 if (nseg == 0)
565 return false;
566
567 avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
955b1b5a
MI		 568
569 if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1))))
570 return false;
571 if (!iod->nvmeq->qid)
572 return false;
573 if (!sgl_threshold || avg_seg_size < sgl_threshold)
574 return false;
575 return true;
576}
577
7fe07d14 578static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
b60503ba 579{
f4800d6d 580 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
7fe07d14
CH		 581 enum dma_data_direction dma_dir = rq_data_dir(req) ?
582 DMA_TO_DEVICE : DMA_FROM_DEVICE;
a7a7cbe3
CK		 583 const int last_prp = dev->ctrl.page_size / sizeof(__le64) - 1;
584 dma_addr_t dma_addr = iod->first_dma, next_dma_addr;
eca18b23 585 int i;
eca18b23 586
dff824b2
CH		 587 if (iod->dma_len) {
588 dma_unmap_page(dev->dev, dma_addr, iod->dma_len, dma_dir);
589 return;
7fe07d14
CH		 590 }
591
dff824b2
CH		 592 WARN_ON_ONCE(!iod->nents);
593
594 /* P2PDMA requests do not need to be unmapped */
595 if (!is_pci_p2pdma_page(sg_page(iod->sg)))
596 dma_unmap_sg(dev->dev, iod->sg, iod->nents, rq_dma_dir(req));
597
598
eca18b23 599 if (iod->npages == 0)
a7a7cbe3
CK		 600 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0],
601 dma_addr);
602
eca18b23 603 for (i = 0; i < iod->npages; i++) {
a7a7cbe3
CK		 604 void *addr = nvme_pci_iod_list(req)[i];
605
606 if (iod->use_sgl) {
607 struct nvme_sgl_desc *sg_list = addr;
608
609 next_dma_addr =
610 le64_to_cpu((sg_list[SGES_PER_PAGE - 1]).addr);
611 } else {
612 __le64 *prp_list = addr;
613
614 next_dma_addr = le64_to_cpu(prp_list[last_prp]);
615 }
616
617 dma_pool_free(dev->prp_page_pool, addr, dma_addr);
618 dma_addr = next_dma_addr;
eca18b23 619 }
ac3dd5bd 620
d43f1ccf 621 mempool_free(iod->sg, dev->iod_mempool);
b4ff9c8d
KB		 622}
623
d0877473
KB		 624static void nvme_print_sgl(struct scatterlist *sgl, int nents)
625{
626 int i;
627 struct scatterlist *sg;
628
629 for_each_sg(sgl, sg, nents, i) {
630 dma_addr_t phys = sg_phys(sg);
631 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
632 "dma_address:%pad dma_length:%d\n",
633 i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
634 sg_dma_len(sg));
635 }
636}
637
a7a7cbe3
CK		 638static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
639 struct request *req, struct nvme_rw_command *cmnd)
ff22b54f 640{
f4800d6d 641 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
99802a7a 642 struct dma_pool *pool;
b131c61d 643 int length = blk_rq_payload_bytes(req);
eca18b23 644 struct scatterlist *sg = iod->sg;
ff22b54f
MW		 645 int dma_len = sg_dma_len(sg);
646 u64 dma_addr = sg_dma_address(sg);
5fd4ce1b 647 u32 page_size = dev->ctrl.page_size;
f137e0f1 648 int offset = dma_addr & (page_size - 1);
e025344c 649 __le64 *prp_list;
a7a7cbe3 650 void **list = nvme_pci_iod_list(req);
e025344c 651 dma_addr_t prp_dma;
eca18b23 652 int nprps, i;
ff22b54f 653
1d090624 654 length -= (page_size - offset);
5228b328
JS		 655 if (length <= 0) {
656 iod->first_dma = 0;
a7a7cbe3 657 goto done;
5228b328 658 }
ff22b54f 659
1d090624 660 dma_len -= (page_size - offset);
ff22b54f 661 if (dma_len) {
1d090624 662 dma_addr += (page_size - offset);
ff22b54f
MW		 663 } else {
664 sg = sg_next(sg);
665 dma_addr = sg_dma_address(sg);
666 dma_len = sg_dma_len(sg);
667 }
668
1d090624 669 if (length <= page_size) {
edd10d33 670 iod->first_dma = dma_addr;
a7a7cbe3 671 goto done;
e025344c
SMM		 672 }
673
1d090624 674 nprps = DIV_ROUND_UP(length, page_size);
99802a7a
MW		 675 if (nprps <= (256 / 8)) {
676 pool = dev->prp_small_pool;
eca18b23 677 iod->npages = 0;
99802a7a
MW		 678 } else {
679 pool = dev->prp_page_pool;
eca18b23 680 iod->npages = 1;
99802a7a
MW		 681 }
682
69d2b571 683 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
b77954cb 684 if (!prp_list) {
edd10d33 685 iod->first_dma = dma_addr;
eca18b23 686 iod->npages = -1;
86eea289 687 return BLK_STS_RESOURCE;
b77954cb 688 }
eca18b23
MW		 689 list[0] = prp_list;
690 iod->first_dma = prp_dma;
e025344c
SMM		 691 i = 0;
692 for (;;) {
1d090624 693 if (i == page_size >> 3) {
e025344c 694 __le64 *old_prp_list = prp_list;
69d2b571 695 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
eca18b23 696 if (!prp_list)
86eea289 697 return BLK_STS_RESOURCE;
eca18b23 698 list[iod->npages++] = prp_list;
7523d834
MW		 699 prp_list[0] = old_prp_list[i - 1];
700 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
701 i = 1;
e025344c
SMM		 702 }
703 prp_list[i++] = cpu_to_le64(dma_addr);
1d090624
KB		 704 dma_len -= page_size;
705 dma_addr += page_size;
706 length -= page_size;
e025344c
SMM		 707 if (length <= 0)
708 break;
709 if (dma_len > 0)
710 continue;
86eea289
KB		 711 if (unlikely(dma_len < 0))
712 goto bad_sgl;
e025344c
SMM		 713 sg = sg_next(sg);
714 dma_addr = sg_dma_address(sg);
715 dma_len = sg_dma_len(sg);
ff22b54f
MW		 716 }
717
a7a7cbe3
CK		 718done:
719 cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
720 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
721
86eea289
KB		 722 return BLK_STS_OK;
723
724 bad_sgl:
d0877473
KB		 725 WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents),
726 "Invalid SGL for payload:%d nents:%d\n",
727 blk_rq_payload_bytes(req), iod->nents);
86eea289 728 return BLK_STS_IOERR;
ff22b54f
MW		 729}
730
a7a7cbe3
CK		 731static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
732 struct scatterlist *sg)
733{
734 sge->addr = cpu_to_le64(sg_dma_address(sg));
735 sge->length = cpu_to_le32(sg_dma_len(sg));
736 sge->type = NVME_SGL_FMT_DATA_DESC << 4;
737}
738
739static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
740 dma_addr_t dma_addr, int entries)
741{
742 sge->addr = cpu_to_le64(dma_addr);
743 if (entries < SGES_PER_PAGE) {
744 sge->length = cpu_to_le32(entries * sizeof(*sge));
745 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
746 } else {
747 sge->length = cpu_to_le32(PAGE_SIZE);
748 sge->type = NVME_SGL_FMT_SEG_DESC << 4;
749 }
750}
751
752static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
b0f2853b 753 struct request *req, struct nvme_rw_command *cmd, int entries)
a7a7cbe3
CK		 754{
755 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3
CK		 756 struct dma_pool *pool;
757 struct nvme_sgl_desc *sg_list;
758 struct scatterlist *sg = iod->sg;
a7a7cbe3 759 dma_addr_t sgl_dma;
b0f2853b 760 int i = 0;
a7a7cbe3 761
a7a7cbe3
CK		 762 /* setting the transfer type as SGL */
763 cmd->flags = NVME_CMD_SGL_METABUF;
764
b0f2853b 765 if (entries == 1) {
a7a7cbe3
CK		 766 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
767 return BLK_STS_OK;
768 }
769
770 if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
771 pool = dev->prp_small_pool;
772 iod->npages = 0;
773 } else {
774 pool = dev->prp_page_pool;
775 iod->npages = 1;
776 }
777
778 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
779 if (!sg_list) {
780 iod->npages = -1;
781 return BLK_STS_RESOURCE;
782 }
783
784 nvme_pci_iod_list(req)[0] = sg_list;
785 iod->first_dma = sgl_dma;
786
787 nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
788
789 do {
790 if (i == SGES_PER_PAGE) {
791 struct nvme_sgl_desc *old_sg_desc = sg_list;
792 struct nvme_sgl_desc *link = &old_sg_desc[i - 1];
793
794 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
795 if (!sg_list)
796 return BLK_STS_RESOURCE;
797
798 i = 0;
799 nvme_pci_iod_list(req)[iod->npages++] = sg_list;
800 sg_list[i++] = *link;
801 nvme_pci_sgl_set_seg(link, sgl_dma, entries);
802 }
803
804 nvme_pci_sgl_set_data(&sg_list[i++], sg);
a7a7cbe3 805 sg = sg_next(sg);
b0f2853b 806 } while (--entries > 0);
a7a7cbe3 807
a7a7cbe3
CK		 808 return BLK_STS_OK;
809}
810
dff824b2
CH		 811static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev,
812 struct request *req, struct nvme_rw_command *cmnd,
813 struct bio_vec *bv)
814{
815 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
816 unsigned int first_prp_len = dev->ctrl.page_size - bv->bv_offset;
817
818 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
819 if (dma_mapping_error(dev->dev, iod->first_dma))
820 return BLK_STS_RESOURCE;
821 iod->dma_len = bv->bv_len;
822
823 cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma);
824 if (bv->bv_len > first_prp_len)
825 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len);
826 return 0;
827}
828
29791057
CH		 829static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev,
830 struct request *req, struct nvme_rw_command *cmnd,
831 struct bio_vec *bv)
832{
833 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
834
835 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
836 if (dma_mapping_error(dev->dev, iod->first_dma))
837 return BLK_STS_RESOURCE;
838 iod->dma_len = bv->bv_len;
839
049bf372 840 cmnd->flags = NVME_CMD_SGL_METABUF;
29791057
CH		 841 cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma);
842 cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len);
843 cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4;
844 return 0;
845}
846
fc17b653 847static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
b131c61d 848 struct nvme_command *cmnd)
d29ec824 849{
f4800d6d 850 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
70479b71 851 blk_status_t ret = BLK_STS_RESOURCE;
b0f2853b 852 int nr_mapped;
d29ec824 853
dff824b2
CH		 854 if (blk_rq_nr_phys_segments(req) == 1) {
855 struct bio_vec bv = req_bvec(req);
856
857 if (!is_pci_p2pdma_page(bv.bv_page)) {
858 if (bv.bv_offset + bv.bv_len <= dev->ctrl.page_size * 2)
859 return nvme_setup_prp_simple(dev, req,
860 &cmnd->rw, &bv);
29791057
CH		 861
862 if (iod->nvmeq->qid &&
863 dev->ctrl.sgls & ((1 << 0) | (1 << 1)))
864 return nvme_setup_sgl_simple(dev, req,
865 &cmnd->rw, &bv);
dff824b2
CH		 866 }
867 }
868
869 iod->dma_len = 0;
d43f1ccf
CH		 870 iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC);
871 if (!iod->sg)
872 return BLK_STS_RESOURCE;
f9d03f96 873 sg_init_table(iod->sg, blk_rq_nr_phys_segments(req));
70479b71 874 iod->nents = blk_rq_map_sg(req->q, req, iod->sg);
ba1ca37e
CH		 875 if (!iod->nents)
876 goto out;
d29ec824 877
e0596ab2
LG		 878 if (is_pci_p2pdma_page(sg_page(iod->sg)))
879 nr_mapped = pci_p2pdma_map_sg(dev->dev, iod->sg, iod->nents,
70479b71 880 rq_dma_dir(req));
e0596ab2
LG		 881 else
882 nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents,
70479b71 883 rq_dma_dir(req), DMA_ATTR_NO_WARN);
b0f2853b 884 if (!nr_mapped)
ba1ca37e 885 goto out;
d29ec824 886
70479b71 887 iod->use_sgl = nvme_pci_use_sgls(dev, req);
955b1b5a 888 if (iod->use_sgl)
b0f2853b 889 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped);
a7a7cbe3
CK		 890 else
891 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
4aedb705 892out:
86eea289 893 if (ret != BLK_STS_OK)
4aedb705
CH		 894 nvme_unmap_data(dev, req);
895 return ret;
896}
3045c0d0 897
4aedb705
CH		 898static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req,
899 struct nvme_command *cmnd)
900{
901 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
00df5cb4 902
4aedb705
CH		 903 iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req),
904 rq_dma_dir(req), 0);
905 if (dma_mapping_error(dev->dev, iod->meta_dma))
906 return BLK_STS_IOERR;
907 cmnd->rw.metadata = cpu_to_le64(iod->meta_dma);
908 return 0;
00df5cb4
MW		 909}
910
d29ec824
CH		 911/*
912 * NOTE: ns is NULL when called on the admin queue.
913 */
fc17b653 914static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
a4aea562 915 const struct blk_mq_queue_data *bd)
edd10d33 916{
a4aea562
MB		 917 struct nvme_ns *ns = hctx->queue->queuedata;
918 struct nvme_queue *nvmeq = hctx->driver_data;
d29ec824 919 struct nvme_dev *dev = nvmeq->dev;
a4aea562 920 struct request *req = bd->rq;
9b048119 921 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
ba1ca37e 922 struct nvme_command cmnd;
ebe6d874 923 blk_status_t ret;
e1e5e564 924
9b048119
CH		 925 iod->aborted = 0;
926 iod->npages = -1;
927 iod->nents = 0;
928
d1f06f4a
JA		 929 /*
930 * We should not need to do this, but we're still using this to
931 * ensure we can drain requests on a dying queue.
932 */
4e224106 933 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
d1f06f4a
JA		 934 return BLK_STS_IOERR;
935
f9d03f96 936 ret = nvme_setup_cmd(ns, req, &cmnd);
fc17b653 937 if (ret)
f4800d6d 938 return ret;
a4aea562 939
fc17b653 940 if (blk_rq_nr_phys_segments(req)) {
b131c61d 941 ret = nvme_map_data(dev, req, &cmnd);
fc17b653 942 if (ret)
9b048119 943 goto out_free_cmd;
fc17b653 944 }
a4aea562 945
4aedb705
CH		 946 if (blk_integrity_rq(req)) {
947 ret = nvme_map_metadata(dev, req, &cmnd);
948 if (ret)
949 goto out_unmap_data;
950 }
951
aae239e1 952 blk_mq_start_request(req);
04f3eafd 953 nvme_submit_cmd(nvmeq, &cmnd, bd->last);
fc17b653 954 return BLK_STS_OK;
4aedb705
CH		 955out_unmap_data:
956 nvme_unmap_data(dev, req);
f9d03f96
CH		 957out_free_cmd:
958 nvme_cleanup_cmd(req);
ba1ca37e 959 return ret;
b60503ba 960}
e1e5e564 961
77f02a7a 962static void nvme_pci_complete_rq(struct request *req)
eee417b0 963{
f4800d6d 964 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
4aedb705 965 struct nvme_dev *dev = iod->nvmeq->dev;
a4aea562 966
915f04c9 967 nvme_cleanup_cmd(req);
4aedb705
CH		 968 if (blk_integrity_rq(req))
969 dma_unmap_page(dev->dev, iod->meta_dma,
970 rq_integrity_vec(req)->bv_len, rq_data_dir(req));
b15c592d 971 if (blk_rq_nr_phys_segments(req))
4aedb705 972 nvme_unmap_data(dev, req);
77f02a7a 973 nvme_complete_rq(req);
b60503ba
MW		 974}
975
d783e0bd 976/* We read the CQE phase first to check if the rest of the entry is valid */
750dde44 977static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq)
d783e0bd 978{
750dde44
CH		 979 return (le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) ==
980 nvmeq->cq_phase;
d783e0bd
MR		 981}
982
eb281c82 983static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
b60503ba 984{
eb281c82 985 u16 head = nvmeq->cq_head;
adf68f21 986
397c699f
KB		 987 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
988 nvmeq->dbbuf_cq_ei))
989 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
eb281c82 990}
aae239e1 991
5cb525c8 992static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx)
83a12fb7 993{
5cb525c8 994 volatile struct nvme_completion *cqe = &nvmeq->cqes[idx];
83a12fb7 995 struct request *req;
adf68f21 996
83a12fb7
SG		 997 if (unlikely(cqe->command_id >= nvmeq->q_depth)) {
998 dev_warn(nvmeq->dev->ctrl.device,
999 "invalid id %d completed on queue %d\n",
1000 cqe->command_id, le16_to_cpu(cqe->sq_id));
1001 return;
b60503ba
MW		 1002 }
1003
83a12fb7
SG		 1004 /*
1005 * AEN requests are special as they don't time out and can
1006 * survive any kind of queue freeze and often don't respond to
1007 * aborts. We don't even bother to allocate a struct request
1008 * for them but rather special case them here.
1009 */
1010 if (unlikely(nvmeq->qid == 0 &&
38dabe21 1011 cqe->command_id >= NVME_AQ_BLK_MQ_DEPTH)) {
83a12fb7
SG		 1012 nvme_complete_async_event(&nvmeq->dev->ctrl,
1013 cqe->status, &cqe->result);
a0fa9647 1014 return;
83a12fb7 1015 }
b60503ba 1016
83a12fb7 1017 req = blk_mq_tag_to_rq(*nvmeq->tags, cqe->command_id);
604c01d5 1018 trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail);
83a12fb7
SG		 1019 nvme_end_request(req, cqe->status, cqe->result);
1020}
b60503ba 1021
5cb525c8 1022static void nvme_complete_cqes(struct nvme_queue *nvmeq, u16 start, u16 end)
b60503ba 1023{
5cb525c8
JA		 1024 while (start != end) {
1025 nvme_handle_cqe(nvmeq, start);
1026 if (++start == nvmeq->q_depth)
1027 start = 0;
1028 }
1029}
adf68f21 1030
5cb525c8
JA		 1031static inline void nvme_update_cq_head(struct nvme_queue *nvmeq)
1032{
dcca1662 1033 if (nvmeq->cq_head == nvmeq->q_depth - 1) {
5cb525c8
JA		 1034 nvmeq->cq_head = 0;
1035 nvmeq->cq_phase = !nvmeq->cq_phase;
dcca1662
HY		 1036 } else {
1037 nvmeq->cq_head++;
b60503ba 1038 }
a0fa9647
JA		 1039}
1040
1052b8ac
JA		 1041static inline int nvme_process_cq(struct nvme_queue *nvmeq, u16 *start,
1042 u16 *end, unsigned int tag)
a0fa9647 1043{
1052b8ac 1044 int found = 0;
b60503ba 1045
5cb525c8 1046 *start = nvmeq->cq_head;
1052b8ac
JA		 1047 while (nvme_cqe_pending(nvmeq)) {
1048 if (tag == -1U || nvmeq->cqes[nvmeq->cq_head].command_id == tag)
1049 found++;
5cb525c8 1050 nvme_update_cq_head(nvmeq);
920d13a8 1051 }
5cb525c8 1052 *end = nvmeq->cq_head;
eb281c82 1053
5cb525c8 1054 if (*start != *end)
920d13a8 1055 nvme_ring_cq_doorbell(nvmeq);
5cb525c8 1056 return found;
b60503ba
MW		 1057}
1058
1059static irqreturn_t nvme_irq(int irq, void *data)
58ffacb5 1060{
58ffacb5 1061 struct nvme_queue *nvmeq = data;
68fa9dbe 1062 irqreturn_t ret = IRQ_NONE;
5cb525c8
JA		 1063 u16 start, end;
1064
3a7afd8e
CH		 1065 /*
1066 * The rmb/wmb pair ensures we see all updates from a previous run of
1067 * the irq handler, even if that was on another CPU.
1068 */
1069 rmb();
68fa9dbe
JA		 1070 if (nvmeq->cq_head != nvmeq->last_cq_head)
1071 ret = IRQ_HANDLED;
5cb525c8 1072 nvme_process_cq(nvmeq, &start, &end, -1);
68fa9dbe 1073 nvmeq->last_cq_head = nvmeq->cq_head;
3a7afd8e 1074 wmb();
5cb525c8 1075
68fa9dbe
JA		 1076 if (start != end) {
1077 nvme_complete_cqes(nvmeq, start, end);
1078 return IRQ_HANDLED;
1079 }
1080
1081 return ret;
58ffacb5
MW		 1082}
1083
1084static irqreturn_t nvme_irq_check(int irq, void *data)
1085{
1086 struct nvme_queue *nvmeq = data;
750dde44 1087 if (nvme_cqe_pending(nvmeq))
d783e0bd
MR		 1088 return IRQ_WAKE_THREAD;
1089 return IRQ_NONE;
58ffacb5
MW		 1090}
1091
0b2a8a9f
CH		 1092/*
1093 * Poll for completions any queue, including those not dedicated to polling.
1094 * Can be called from any context.
1095 */
1096static int nvme_poll_irqdisable(struct nvme_queue *nvmeq, unsigned int tag)
a0fa9647 1097{
3a7afd8e 1098 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
5cb525c8 1099 u16 start, end;
1052b8ac 1100 int found;
a0fa9647 1101
3a7afd8e
CH		 1102 /*
1103 * For a poll queue we need to protect against the polling thread
1104 * using the CQ lock. For normal interrupt driven threads we have
1105 * to disable the interrupt to avoid racing with it.
1106 */
7c349dde 1107 if (test_bit(NVMEQ_POLLED, &nvmeq->flags)) {
3a7afd8e 1108 spin_lock(&nvmeq->cq_poll_lock);
91a509f8 1109 found = nvme_process_cq(nvmeq, &start, &end, tag);
3a7afd8e 1110 spin_unlock(&nvmeq->cq_poll_lock);
91a509f8
CH		 1111 } else {
1112 disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1113 found = nvme_process_cq(nvmeq, &start, &end, tag);
3a7afd8e 1114 enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
91a509f8 1115 }
442e19b7 1116
5cb525c8 1117 nvme_complete_cqes(nvmeq, start, end);
442e19b7 1118 return found;
a0fa9647
JA		 1119}
1120
9743139c 1121static int nvme_poll(struct blk_mq_hw_ctx *hctx)
dabcefab
JA		 1122{
1123 struct nvme_queue *nvmeq = hctx->driver_data;
1124 u16 start, end;
1125 bool found;
1126
1127 if (!nvme_cqe_pending(nvmeq))
1128 return 0;
1129
3a7afd8e 1130 spin_lock(&nvmeq->cq_poll_lock);
9743139c 1131 found = nvme_process_cq(nvmeq, &start, &end, -1);
3a7afd8e 1132 spin_unlock(&nvmeq->cq_poll_lock);
dabcefab
JA		 1133
1134 nvme_complete_cqes(nvmeq, start, end);
1135 return found;
1136}
1137
ad22c355 1138static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
b60503ba 1139{
f866fc42 1140 struct nvme_dev *dev = to_nvme_dev(ctrl);
147b27e4 1141 struct nvme_queue *nvmeq = &dev->queues[0];
a4aea562 1142 struct nvme_command c;
b60503ba 1143
a4aea562
MB		 1144 memset(&c, 0, sizeof(c));
1145 c.common.opcode = nvme_admin_async_event;
ad22c355 1146 c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
04f3eafd 1147 nvme_submit_cmd(nvmeq, &c, true);
f705f837
CH		 1148}
1149
b60503ba 1150static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
f705f837 1151{
b60503ba
MW		 1152 struct nvme_command c;
1153
1154 memset(&c, 0, sizeof(c));
1155 c.delete_queue.opcode = opcode;
1156 c.delete_queue.qid = cpu_to_le16(id);
1157
1c63dc66 1158 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1159}
1160
b60503ba 1161static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
a8e3e0bb 1162 struct nvme_queue *nvmeq, s16 vector)
b60503ba 1163{
b60503ba 1164 struct nvme_command c;
4b04cc6a
JA		 1165 int flags = NVME_QUEUE_PHYS_CONTIG;
1166
7c349dde 1167 if (!test_bit(NVMEQ_POLLED, &nvmeq->flags))
4b04cc6a 1168 flags |= NVME_CQ_IRQ_ENABLED;
b60503ba 1169
d29ec824 1170 /*
16772ae6 1171 * Note: we (ab)use the fact that the prp fields survive if no data
d29ec824
CH		 1172 * is attached to the request.
1173 */
b60503ba
MW		 1174 memset(&c, 0, sizeof(c));
1175 c.create_cq.opcode = nvme_admin_create_cq;
1176 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1177 c.create_cq.cqid = cpu_to_le16(qid);
1178 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1179 c.create_cq.cq_flags = cpu_to_le16(flags);
7c349dde 1180 c.create_cq.irq_vector = cpu_to_le16(vector);
b60503ba 1181
1c63dc66 1182 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1183}
1184
1185static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1186 struct nvme_queue *nvmeq)
1187{
9abd68ef 1188 struct nvme_ctrl *ctrl = &dev->ctrl;
b60503ba 1189 struct nvme_command c;
81c1cd98 1190 int flags = NVME_QUEUE_PHYS_CONTIG;
b60503ba 1191
9abd68ef
JA		 1192 /*
1193 * Some drives have a bug that auto-enables WRRU if MEDIUM isn't
1194 * set. Since URGENT priority is zeroes, it makes all queues
1195 * URGENT.
1196 */
1197 if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ)
1198 flags |= NVME_SQ_PRIO_MEDIUM;
1199
d29ec824 1200 /*
16772ae6 1201 * Note: we (ab)use the fact that the prp fields survive if no data
d29ec824
CH		 1202 * is attached to the request.
1203 */
b60503ba
MW		 1204 memset(&c, 0, sizeof(c));
1205 c.create_sq.opcode = nvme_admin_create_sq;
1206 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1207 c.create_sq.sqid = cpu_to_le16(qid);
1208 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1209 c.create_sq.sq_flags = cpu_to_le16(flags);
1210 c.create_sq.cqid = cpu_to_le16(qid);
1211
1c63dc66 1212 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1213}
1214
1215static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1216{
1217 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1218}
1219
1220static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1221{
1222 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1223}
1224
2a842aca 1225static void abort_endio(struct request *req, blk_status_t error)
bc5fc7e4 1226{
f4800d6d
CH		 1227 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1228 struct nvme_queue *nvmeq = iod->nvmeq;
e44ac588 1229
27fa9bc5
CH		 1230 dev_warn(nvmeq->dev->ctrl.device,
1231 "Abort status: 0x%x", nvme_req(req)->status);
e7a2a87d 1232 atomic_inc(&nvmeq->dev->ctrl.abort_limit);
e7a2a87d 1233 blk_mq_free_request(req);
bc5fc7e4
MW		 1234}
1235
b2a0eb1a
KB		 1236static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1237{
1238
1239 /* If true, indicates loss of adapter communication, possibly by a
1240 * NVMe Subsystem reset.
1241 */
1242 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1243
ad70062c
JW		 1244 /* If there is a reset/reinit ongoing, we shouldn't reset again. */
1245 switch (dev->ctrl.state) {
1246 case NVME_CTRL_RESETTING:
ad6a0a52 1247 case NVME_CTRL_CONNECTING:
b2a0eb1a 1248 return false;
ad70062c
JW		 1249 default:
1250 break;
1251 }
b2a0eb1a
KB		 1252
1253 /* We shouldn't reset unless the controller is on fatal error state
1254 * _or_ if we lost the communication with it.
1255 */
1256 if (!(csts & NVME_CSTS_CFS) && !nssro)
1257 return false;
1258
b2a0eb1a
KB		 1259 return true;
1260}
1261
1262static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1263{
1264 /* Read a config register to help see what died. */
1265 u16 pci_status;
1266 int result;
1267
1268 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1269 &pci_status);
1270 if (result == PCIBIOS_SUCCESSFUL)
1271 dev_warn(dev->ctrl.device,
1272 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1273 csts, pci_status);
1274 else
1275 dev_warn(dev->ctrl.device,
1276 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1277 csts, result);
1278}
1279
31c7c7d2 1280static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
c30341dc 1281{
f4800d6d
CH		 1282 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1283 struct nvme_queue *nvmeq = iod->nvmeq;
c30341dc 1284 struct nvme_dev *dev = nvmeq->dev;
a4aea562 1285 struct request *abort_req;
a4aea562 1286 struct nvme_command cmd;
9dc1a38e 1287 bool shutdown = false;
b2a0eb1a
KB		 1288 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1289
651438bb
WX		 1290 /* If PCI error recovery process is happening, we cannot reset or
1291 * the recovery mechanism will surely fail.
1292 */
1293 mb();
1294 if (pci_channel_offline(to_pci_dev(dev->dev)))
1295 return BLK_EH_RESET_TIMER;
1296
b2a0eb1a
KB		 1297 /*
1298 * Reset immediately if the controller is failed
1299 */
1300 if (nvme_should_reset(dev, csts)) {
1301 nvme_warn_reset(dev, csts);
1302 nvme_dev_disable(dev, false);
d86c4d8e 1303 nvme_reset_ctrl(&dev->ctrl);
db8c48e4 1304 return BLK_EH_DONE;
b2a0eb1a 1305 }
c30341dc 1306
7776db1c
KB		 1307 /*
1308 * Did we miss an interrupt?
1309 */
0b2a8a9f 1310 if (nvme_poll_irqdisable(nvmeq, req->tag)) {
7776db1c
KB		 1311 dev_warn(dev->ctrl.device,
1312 "I/O %d QID %d timeout, completion polled\n",
1313 req->tag, nvmeq->qid);
db8c48e4 1314 return BLK_EH_DONE;
7776db1c
KB		 1315 }
1316
31c7c7d2 1317 /*
fd634f41
CH		 1318 * Shutdown immediately if controller times out while starting. The
1319 * reset work will see the pci device disabled when it gets the forced
1320 * cancellation error. All outstanding requests are completed on
db8c48e4 1321 * shutdown, so we return BLK_EH_DONE.
fd634f41 1322 */
4244140d 1323 switch (dev->ctrl.state) {
9dc1a38e
KB		 1324 case NVME_CTRL_DELETING:
1325 shutdown = true;
4244140d
KB		 1326 case NVME_CTRL_CONNECTING:
1327 case NVME_CTRL_RESETTING:
b9cac43c 1328 dev_warn_ratelimited(dev->ctrl.device,
fd634f41
CH		 1329 "I/O %d QID %d timeout, disable controller\n",
1330 req->tag, nvmeq->qid);
9dc1a38e 1331 nvme_dev_disable(dev, shutdown);
27fa9bc5 1332 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
db8c48e4 1333 return BLK_EH_DONE;
4244140d
KB		 1334 default:
1335 break;
c30341dc
KB		 1336 }
1337
fd634f41
CH		 1338 /*
1339 * Shutdown the controller immediately and schedule a reset if the
1340 * command was already aborted once before and still hasn't been
1341 * returned to the driver, or if this is the admin queue.
31c7c7d2 1342 */
f4800d6d 1343 if (!nvmeq->qid || iod->aborted) {
1b3c47c1 1344 dev_warn(dev->ctrl.device,
e1569a16
KB		 1345 "I/O %d QID %d timeout, reset controller\n",
1346 req->tag, nvmeq->qid);
a5cdb68c 1347 nvme_dev_disable(dev, false);
d86c4d8e 1348 nvme_reset_ctrl(&dev->ctrl);
c30341dc 1349
27fa9bc5 1350 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
db8c48e4 1351 return BLK_EH_DONE;
c30341dc 1352 }
c30341dc 1353
e7a2a87d 1354 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
6bf25d16 1355 atomic_inc(&dev->ctrl.abort_limit);
31c7c7d2 1356 return BLK_EH_RESET_TIMER;
6bf25d16 1357 }
7bf7d778 1358 iod->aborted = 1;
a4aea562 1359
c30341dc
KB		 1360 memset(&cmd, 0, sizeof(cmd));
1361 cmd.abort.opcode = nvme_admin_abort_cmd;
a4aea562 1362 cmd.abort.cid = req->tag;
c30341dc 1363 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
c30341dc 1364
1b3c47c1
SG		 1365 dev_warn(nvmeq->dev->ctrl.device,
1366 "I/O %d QID %d timeout, aborting\n",
1367 req->tag, nvmeq->qid);
e7a2a87d
CH		 1368
1369 abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
eb71f435 1370 BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
e7a2a87d
CH		 1371 if (IS_ERR(abort_req)) {
1372 atomic_inc(&dev->ctrl.abort_limit);
1373 return BLK_EH_RESET_TIMER;
1374 }
1375
1376 abort_req->timeout = ADMIN_TIMEOUT;
1377 abort_req->end_io_data = NULL;
1378 blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio);
c30341dc 1379
31c7c7d2
CH		 1380 /*
1381 * The aborted req will be completed on receiving the abort req.
1382 * We enable the timer again. If hit twice, it'll cause a device reset,
1383 * as the device then is in a faulty state.
1384 */
1385 return BLK_EH_RESET_TIMER;
c30341dc
KB		 1386}
1387
a4aea562
MB		 1388static void nvme_free_queue(struct nvme_queue *nvmeq)
1389{
88a041f4 1390 dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq->q_depth),
9e866774 1391 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
63223078
CH		 1392 if (!nvmeq->sq_cmds)
1393 return;
0f238ff5 1394
63223078 1395 if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) {
88a041f4 1396 pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev),
63223078
CH		 1397 nvmeq->sq_cmds, SQ_SIZE(nvmeq->q_depth));
1398 } else {
88a041f4 1399 dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq->q_depth),
63223078 1400 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
0f238ff5 1401 }
9e866774
MW		 1402}
1403
a1a5ef99 1404static void nvme_free_queues(struct nvme_dev *dev, int lowest)
22404274
KB		 1405{
1406 int i;
1407
d858e5f0 1408 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
d858e5f0 1409 dev->ctrl.queue_count--;
147b27e4 1410 nvme_free_queue(&dev->queues[i]);
121c7ad4 1411 }
22404274
KB		 1412}
1413
4d115420
KB		 1414/**
1415 * nvme_suspend_queue - put queue into suspended state
40581d1a 1416 * @nvmeq: queue to suspend
4d115420
KB		 1417 */
1418static int nvme_suspend_queue(struct nvme_queue *nvmeq)
b60503ba 1419{
4e224106 1420 if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags))
2b25d981 1421 return 1;
a09115b2 1422
4e224106 1423 /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */
d1f06f4a 1424 mb();
a09115b2 1425
4e224106 1426 nvmeq->dev->online_queues--;
1c63dc66 1427 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
c81545f9 1428 blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q);
7c349dde
KB		 1429 if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags))
1430 pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq);
4d115420
KB		 1431 return 0;
1432}
b60503ba 1433
8fae268b
KB		 1434static void nvme_suspend_io_queues(struct nvme_dev *dev)
1435{
1436 int i;
1437
1438 for (i = dev->ctrl.queue_count - 1; i > 0; i--)
1439 nvme_suspend_queue(&dev->queues[i]);
1440}
1441
a5cdb68c 1442static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
4d115420 1443{
147b27e4 1444 struct nvme_queue *nvmeq = &dev->queues[0];
4d115420 1445
a5cdb68c
KB		 1446 if (shutdown)
1447 nvme_shutdown_ctrl(&dev->ctrl);
1448 else
20d0dfe6 1449 nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap);
07836e65 1450
0b2a8a9f 1451 nvme_poll_irqdisable(nvmeq, -1);
b60503ba
MW		 1452}
1453
8ffaadf7
JD		 1454static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1455 int entry_size)
1456{
1457 int q_depth = dev->q_depth;
5fd4ce1b
CH		 1458 unsigned q_size_aligned = roundup(q_depth * entry_size,
1459 dev->ctrl.page_size);
8ffaadf7
JD		 1460
1461 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
c45f5c99 1462 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
5fd4ce1b 1463 mem_per_q = round_down(mem_per_q, dev->ctrl.page_size);
c45f5c99 1464 q_depth = div_u64(mem_per_q, entry_size);
8ffaadf7
JD		 1465
1466 /*
1467 * Ensure the reduced q_depth is above some threshold where it
1468 * would be better to map queues in system memory with the
1469 * original depth
1470 */
1471 if (q_depth < 64)
1472 return -ENOMEM;
1473 }
1474
1475 return q_depth;
1476}
1477
1478static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1479 int qid, int depth)
1480{
0f238ff5
LG		 1481 struct pci_dev *pdev = to_pci_dev(dev->dev);
1482
1483 if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
1484 nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(depth));
1485 nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev,
1486 nvmeq->sq_cmds);
63223078
CH		 1487 if (nvmeq->sq_dma_addr) {
1488 set_bit(NVMEQ_SQ_CMB, &nvmeq->flags);
1489 return 0;
1490 }
0f238ff5 1491 }
8ffaadf7 1492
63223078
CH		 1493 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
1494 &nvmeq->sq_dma_addr, GFP_KERNEL);
815c6704
KB		 1495 if (!nvmeq->sq_cmds)
1496 return -ENOMEM;
8ffaadf7
JD		 1497 return 0;
1498}
1499
a6ff7262 1500static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
b60503ba 1501{
147b27e4 1502 struct nvme_queue *nvmeq = &dev->queues[qid];
b60503ba 1503
62314e40
KB		 1504 if (dev->ctrl.queue_count > qid)
1505 return 0;
b60503ba 1506
750afb08
LC		 1507 nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(depth),
1508 &nvmeq->cq_dma_addr, GFP_KERNEL);
b60503ba
MW		 1509 if (!nvmeq->cqes)
1510 goto free_nvmeq;
b60503ba 1511
8ffaadf7 1512 if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth))
b60503ba
MW		 1513 goto free_cqdma;
1514
091b6092 1515 nvmeq->dev = dev;
1ab0cd69 1516 spin_lock_init(&nvmeq->sq_lock);
3a7afd8e 1517 spin_lock_init(&nvmeq->cq_poll_lock);
b60503ba 1518 nvmeq->cq_head = 0;
82123460 1519 nvmeq->cq_phase = 1;
b80d5ccc 1520 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
b60503ba 1521 nvmeq->q_depth = depth;
c30341dc 1522 nvmeq->qid = qid;
d858e5f0 1523 dev->ctrl.queue_count++;
36a7e993 1524
147b27e4 1525 return 0;
b60503ba
MW		 1526
1527 free_cqdma:
e75ec752 1528 dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes,
b60503ba
MW		 1529 nvmeq->cq_dma_addr);
1530 free_nvmeq:
147b27e4 1531 return -ENOMEM;
b60503ba
MW		 1532}
1533
dca51e78 1534static int queue_request_irq(struct nvme_queue *nvmeq)
3001082c 1535{
0ff199cb
CH		 1536 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1537 int nr = nvmeq->dev->ctrl.instance;
1538
1539 if (use_threaded_interrupts) {
1540 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1541 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1542 } else {
1543 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1544 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1545 }
3001082c
MW		 1546}
1547
22404274 1548static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
b60503ba 1549{
22404274 1550 struct nvme_dev *dev = nvmeq->dev;
b60503ba 1551
22404274 1552 nvmeq->sq_tail = 0;
04f3eafd 1553 nvmeq->last_sq_tail = 0;
22404274
KB		 1554 nvmeq->cq_head = 0;
1555 nvmeq->cq_phase = 1;
b80d5ccc 1556 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
22404274 1557 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
f9f38e33 1558 nvme_dbbuf_init(dev, nvmeq, qid);
42f61420 1559 dev->online_queues++;
3a7afd8e 1560 wmb(); /* ensure the first interrupt sees the initialization */
22404274
KB		 1561}
1562
4b04cc6a 1563static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled)
22404274
KB		 1564{
1565 struct nvme_dev *dev = nvmeq->dev;
1566 int result;
7c349dde 1567 u16 vector = 0;
3f85d50b 1568
d1ed6aa1
CH		 1569 clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
1570
22b55601
KB		 1571 /*
1572 * A queue's vector matches the queue identifier unless the controller
1573 * has only one vector available.
1574 */
4b04cc6a
JA		 1575 if (!polled)
1576 vector = dev->num_vecs == 1 ? 0 : qid;
1577 else
7c349dde 1578 set_bit(NVMEQ_POLLED, &nvmeq->flags);
4b04cc6a 1579
a8e3e0bb 1580 result = adapter_alloc_cq(dev, qid, nvmeq, vector);
ded45505
KB		 1581 if (result)
1582 return result;
b60503ba
MW		 1583
1584 result = adapter_alloc_sq(dev, qid, nvmeq);
1585 if (result < 0)
ded45505
KB		 1586 return result;
1587 else if (result)
b60503ba
MW		 1588 goto release_cq;
1589
a8e3e0bb 1590 nvmeq->cq_vector = vector;
161b8be2 1591 nvme_init_queue(nvmeq, qid);
4b04cc6a 1592
7c349dde
KB		 1593 if (!polled) {
1594 nvmeq->cq_vector = vector;
4b04cc6a
JA		 1595 result = queue_request_irq(nvmeq);
1596 if (result < 0)
1597 goto release_sq;
1598 }
b60503ba 1599
4e224106 1600 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
22404274 1601 return result;
b60503ba 1602
a8e3e0bb 1603release_sq:
f25a2dfc 1604 dev->online_queues--;
b60503ba 1605 adapter_delete_sq(dev, qid);
a8e3e0bb 1606release_cq:
b60503ba 1607 adapter_delete_cq(dev, qid);
22404274 1608 return result;
b60503ba
MW		 1609}
1610
f363b089 1611static const struct blk_mq_ops nvme_mq_admin_ops = {
d29ec824 1612 .queue_rq = nvme_queue_rq,
77f02a7a 1613 .complete = nvme_pci_complete_rq,
a4aea562 1614 .init_hctx = nvme_admin_init_hctx,
4af0e21c 1615 .exit_hctx = nvme_admin_exit_hctx,
0350815a 1616 .init_request = nvme_init_request,
a4aea562
MB		 1617 .timeout = nvme_timeout,
1618};
1619
f363b089 1620static const struct blk_mq_ops nvme_mq_ops = {
376f7ef8
CH		 1621 .queue_rq = nvme_queue_rq,
1622 .complete = nvme_pci_complete_rq,
1623 .commit_rqs = nvme_commit_rqs,
1624 .init_hctx = nvme_init_hctx,
1625 .init_request = nvme_init_request,
1626 .map_queues = nvme_pci_map_queues,
1627 .timeout = nvme_timeout,
1628 .poll = nvme_poll,
dabcefab
JA		 1629};
1630
ea191d2f
KB		 1631static void nvme_dev_remove_admin(struct nvme_dev *dev)
1632{
1c63dc66 1633 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
69d9a99c
KB		 1634 /*
1635 * If the controller was reset during removal, it's possible
1636 * user requests may be waiting on a stopped queue. Start the
1637 * queue to flush these to completion.
1638 */
c81545f9 1639 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1c63dc66 1640 blk_cleanup_queue(dev->ctrl.admin_q);
ea191d2f
KB		 1641 blk_mq_free_tag_set(&dev->admin_tagset);
1642 }
1643}
1644
a4aea562
MB		 1645static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1646{
1c63dc66 1647 if (!dev->ctrl.admin_q) {
a4aea562
MB		 1648 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1649 dev->admin_tagset.nr_hw_queues = 1;
e3e9d50c 1650
38dabe21 1651 dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH;
a4aea562 1652 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
e75ec752 1653 dev->admin_tagset.numa_node = dev_to_node(dev->dev);
d43f1ccf 1654 dev->admin_tagset.cmd_size = sizeof(struct nvme_iod);
d3484991 1655 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED;
a4aea562
MB		 1656 dev->admin_tagset.driver_data = dev;
1657
1658 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1659 return -ENOMEM;
34b6c231 1660 dev->ctrl.admin_tagset = &dev->admin_tagset;
a4aea562 1661
1c63dc66
CH		 1662 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1663 if (IS_ERR(dev->ctrl.admin_q)) {
a4aea562
MB		 1664 blk_mq_free_tag_set(&dev->admin_tagset);
1665 return -ENOMEM;
1666 }
1c63dc66 1667 if (!blk_get_queue(dev->ctrl.admin_q)) {
ea191d2f 1668 nvme_dev_remove_admin(dev);
1c63dc66 1669 dev->ctrl.admin_q = NULL;
ea191d2f
KB		 1670 return -ENODEV;
1671 }
0fb59cbc 1672 } else
c81545f9 1673 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
a4aea562
MB		 1674
1675 return 0;
1676}
1677
97f6ef64
XY		 1678static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1679{
1680 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1681}
1682
1683static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1684{
1685 struct pci_dev *pdev = to_pci_dev(dev->dev);
1686
1687 if (size <= dev->bar_mapped_size)
1688 return 0;
1689 if (size > pci_resource_len(pdev, 0))
1690 return -ENOMEM;
1691 if (dev->bar)
1692 iounmap(dev->bar);
1693 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1694 if (!dev->bar) {
1695 dev->bar_mapped_size = 0;
1696 return -ENOMEM;
1697 }
1698 dev->bar_mapped_size = size;
1699 dev->dbs = dev->bar + NVME_REG_DBS;
1700
1701 return 0;
1702}
1703
01ad0990 1704static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
b60503ba 1705{
ba47e386 1706 int result;
b60503ba
MW		 1707 u32 aqa;
1708 struct nvme_queue *nvmeq;
1709
97f6ef64
XY		 1710 result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1711 if (result < 0)
1712 return result;
1713
8ef2074d 1714 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
20d0dfe6 1715 NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
dfbac8c7 1716
7a67cbea
CH		 1717 if (dev->subsystem &&
1718 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1719 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
dfbac8c7 1720
20d0dfe6 1721 result = nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap);
ba47e386
MW		 1722 if (result < 0)
1723 return result;
b60503ba 1724
a6ff7262 1725 result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
147b27e4
SG		 1726 if (result)
1727 return result;
b60503ba 1728
147b27e4 1729 nvmeq = &dev->queues[0];
b60503ba
MW		 1730 aqa = nvmeq->q_depth - 1;
1731 aqa |= aqa << 16;
1732
7a67cbea
CH		 1733 writel(aqa, dev->bar + NVME_REG_AQA);
1734 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1735 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
b60503ba 1736
20d0dfe6 1737 result = nvme_enable_ctrl(&dev->ctrl, dev->ctrl.cap);
025c557a 1738 if (result)
d4875622 1739 return result;
a4aea562 1740
2b25d981 1741 nvmeq->cq_vector = 0;
161b8be2 1742 nvme_init_queue(nvmeq, 0);
dca51e78 1743 result = queue_request_irq(nvmeq);
758dd7fd 1744 if (result) {
7c349dde 1745 dev->online_queues--;
d4875622 1746 return result;
758dd7fd 1747 }
025c557a 1748
4e224106 1749 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
b60503ba
MW		 1750 return result;
1751}
1752
749941f2 1753static int nvme_create_io_queues(struct nvme_dev *dev)
42f61420 1754{
4b04cc6a 1755 unsigned i, max, rw_queues;
749941f2 1756 int ret = 0;
42f61420 1757
d858e5f0 1758 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
a6ff7262 1759 if (nvme_alloc_queue(dev, i, dev->q_depth)) {
749941f2 1760 ret = -ENOMEM;
42f61420 1761 break;
749941f2
CH		 1762 }
1763 }
42f61420 1764
d858e5f0 1765 max = min(dev->max_qid, dev->ctrl.queue_count - 1);
e20ba6e1
CH		 1766 if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) {
1767 rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] +
1768 dev->io_queues[HCTX_TYPE_READ];
4b04cc6a
JA		 1769 } else {
1770 rw_queues = max;
1771 }
1772
949928c1 1773 for (i = dev->online_queues; i <= max; i++) {
4b04cc6a
JA		 1774 bool polled = i > rw_queues;
1775
1776 ret = nvme_create_queue(&dev->queues[i], i, polled);
d4875622 1777 if (ret)
42f61420 1778 break;
27e8166c 1779 }
749941f2
CH		 1780
1781 /*
1782 * Ignore failing Create SQ/CQ commands, we can continue with less
8adb8c14
MI		 1783 * than the desired amount of queues, and even a controller without
1784 * I/O queues can still be used to issue admin commands. This might
749941f2
CH		 1785 * be useful to upgrade a buggy firmware for example.
1786 */
1787 return ret >= 0 ? 0 : ret;
b60503ba
MW		 1788}
1789
202021c1
SB		 1790static ssize_t nvme_cmb_show(struct device *dev,
1791 struct device_attribute *attr,
1792 char *buf)
1793{
1794 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
1795
c965809c 1796 return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n",
202021c1
SB		 1797 ndev->cmbloc, ndev->cmbsz);
1798}
1799static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL);
1800
88de4598 1801static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
8ffaadf7 1802{
88de4598
CH		 1803 u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
1804
1805 return 1ULL << (12 + 4 * szu);
1806}
1807
1808static u32 nvme_cmb_size(struct nvme_dev *dev)
1809{
1810 return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
1811}
1812
f65efd6d 1813static void nvme_map_cmb(struct nvme_dev *dev)
8ffaadf7 1814{
88de4598 1815 u64 size, offset;
8ffaadf7
JD		 1816 resource_size_t bar_size;
1817 struct pci_dev *pdev = to_pci_dev(dev->dev);
8969f1f8 1818 int bar;
8ffaadf7 1819
9fe5c59f
KB		 1820 if (dev->cmb_size)
1821 return;
1822
7a67cbea 1823 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
f65efd6d
CH		 1824 if (!dev->cmbsz)
1825 return;
202021c1 1826 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
8ffaadf7 1827
88de4598
CH		 1828 size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
1829 offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
8969f1f8
CH		 1830 bar = NVME_CMB_BIR(dev->cmbloc);
1831 bar_size = pci_resource_len(pdev, bar);
8ffaadf7
JD		 1832
1833 if (offset > bar_size)
f65efd6d 1834 return;
8ffaadf7
JD		 1835
1836 /*
1837 * Controllers may support a CMB size larger than their BAR,
1838 * for example, due to being behind a bridge. Reduce the CMB to
1839 * the reported size of the BAR
1840 */
1841 if (size > bar_size - offset)
1842 size = bar_size - offset;
1843
0f238ff5
LG		 1844 if (pci_p2pdma_add_resource(pdev, bar, size, offset)) {
1845 dev_warn(dev->ctrl.device,
1846 "failed to register the CMB\n");
f65efd6d 1847 return;
0f238ff5
LG		 1848 }
1849
8ffaadf7 1850 dev->cmb_size = size;
0f238ff5
LG		 1851 dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS);
1852
1853 if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) ==
1854 (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS))
1855 pci_p2pmem_publish(pdev, true);
f65efd6d
CH		 1856
1857 if (sysfs_add_file_to_group(&dev->ctrl.device->kobj,
1858 &dev_attr_cmb.attr, NULL))
1859 dev_warn(dev->ctrl.device,
1860 "failed to add sysfs attribute for CMB\n");
8ffaadf7
JD		 1861}
1862
1863static inline void nvme_release_cmb(struct nvme_dev *dev)
1864{
0f238ff5 1865 if (dev->cmb_size) {
1c78f773
MG		 1866 sysfs_remove_file_from_group(&dev->ctrl.device->kobj,
1867 &dev_attr_cmb.attr, NULL);
0f238ff5 1868 dev->cmb_size = 0;
8ffaadf7
JD		 1869 }
1870}
1871
87ad72a5
CH		 1872static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1873{
4033f35d 1874 u64 dma_addr = dev->host_mem_descs_dma;
87ad72a5 1875 struct nvme_command c;
87ad72a5
CH		 1876 int ret;
1877
87ad72a5
CH		 1878 memset(&c, 0, sizeof(c));
1879 c.features.opcode = nvme_admin_set_features;
1880 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1881 c.features.dword11 = cpu_to_le32(bits);
1882 c.features.dword12 = cpu_to_le32(dev->host_mem_size >>
1883 ilog2(dev->ctrl.page_size));
1884 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr));
1885 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr));
1886 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs);
1887
1888 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1889 if (ret) {
1890 dev_warn(dev->ctrl.device,
1891 "failed to set host mem (err %d, flags %#x).\n",
1892 ret, bits);
1893 }
87ad72a5
CH		 1894 return ret;
1895}
1896
1897static void nvme_free_host_mem(struct nvme_dev *dev)
1898{
1899 int i;
1900
1901 for (i = 0; i < dev->nr_host_mem_descs; i++) {
1902 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
1903 size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size;
1904
cc667f6d
LD		 1905 dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i],
1906 le64_to_cpu(desc->addr),
1907 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
87ad72a5
CH		 1908 }
1909
1910 kfree(dev->host_mem_desc_bufs);
1911 dev->host_mem_desc_bufs = NULL;
4033f35d
CH		 1912 dma_free_coherent(dev->dev,
1913 dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
1914 dev->host_mem_descs, dev->host_mem_descs_dma);
87ad72a5 1915 dev->host_mem_descs = NULL;
7e5dd57e 1916 dev->nr_host_mem_descs = 0;
87ad72a5
CH		 1917}
1918
92dc6895
CH		 1919static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
1920 u32 chunk_size)
9d713c2b 1921{
87ad72a5 1922 struct nvme_host_mem_buf_desc *descs;
92dc6895 1923 u32 max_entries, len;
4033f35d 1924 dma_addr_t descs_dma;
2ee0e4ed 1925 int i = 0;
87ad72a5 1926 void **bufs;
6fbcde66 1927 u64 size, tmp;
87ad72a5 1928
87ad72a5
CH		 1929 tmp = (preferred + chunk_size - 1);
1930 do_div(tmp, chunk_size);
1931 max_entries = tmp;
044a9df1
CH		 1932
1933 if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
1934 max_entries = dev->ctrl.hmmaxd;
1935
750afb08
LC		 1936 descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs),
1937 &descs_dma, GFP_KERNEL);
87ad72a5
CH		 1938 if (!descs)
1939 goto out;
1940
1941 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
1942 if (!bufs)
1943 goto out_free_descs;
1944
244a8fe4 1945 for (size = 0; size < preferred && i < max_entries; size += len) {
87ad72a5
CH		 1946 dma_addr_t dma_addr;
1947
50cdb7c6 1948 len = min_t(u64, chunk_size, preferred - size);
87ad72a5
CH		 1949 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
1950 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1951 if (!bufs[i])
1952 break;
1953
1954 descs[i].addr = cpu_to_le64(dma_addr);
1955 descs[i].size = cpu_to_le32(len / dev->ctrl.page_size);
1956 i++;
1957 }
1958
92dc6895 1959 if (!size)
87ad72a5 1960 goto out_free_bufs;
87ad72a5 1961
87ad72a5
CH		 1962 dev->nr_host_mem_descs = i;
1963 dev->host_mem_size = size;
1964 dev->host_mem_descs = descs;
4033f35d 1965 dev->host_mem_descs_dma = descs_dma;
87ad72a5
CH		 1966 dev->host_mem_desc_bufs = bufs;
1967 return 0;
1968
1969out_free_bufs:
1970 while (--i >= 0) {
1971 size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size;
1972
cc667f6d
LD		 1973 dma_free_attrs(dev->dev, size, bufs[i],
1974 le64_to_cpu(descs[i].addr),
1975 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
87ad72a5
CH		 1976 }
1977
1978 kfree(bufs);
1979out_free_descs:
4033f35d
CH		 1980 dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
1981 descs_dma);
87ad72a5 1982out:
87ad72a5
CH		 1983 dev->host_mem_descs = NULL;
1984 return -ENOMEM;
1985}
1986
92dc6895
CH		 1987static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
1988{
1989 u32 chunk_size;
1990
1991 /* start big and work our way down */
30f92d62 1992 for (chunk_size = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
044a9df1 1993 chunk_size >= max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
92dc6895
CH		 1994 chunk_size /= 2) {
1995 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
1996 if (!min || dev->host_mem_size >= min)
1997 return 0;
1998 nvme_free_host_mem(dev);
1999 }
2000 }
2001
2002 return -ENOMEM;
2003}
2004
9620cfba 2005static int nvme_setup_host_mem(struct nvme_dev *dev)
87ad72a5
CH		 2006{
2007 u64 max = (u64)max_host_mem_size_mb * SZ_1M;
2008 u64 preferred = (u64)dev->ctrl.hmpre * 4096;
2009 u64 min = (u64)dev->ctrl.hmmin * 4096;
2010 u32 enable_bits = NVME_HOST_MEM_ENABLE;
6fbcde66 2011 int ret;
87ad72a5
CH		 2012
2013 preferred = min(preferred, max);
2014 if (min > max) {
2015 dev_warn(dev->ctrl.device,
2016 "min host memory (%lld MiB) above limit (%d MiB).\n",
2017 min >> ilog2(SZ_1M), max_host_mem_size_mb);
2018 nvme_free_host_mem(dev);
9620cfba 2019 return 0;
87ad72a5
CH		 2020 }
2021
2022 /*
2023 * If we already have a buffer allocated check if we can reuse it.
2024 */
2025 if (dev->host_mem_descs) {
2026 if (dev->host_mem_size >= min)
2027 enable_bits |= NVME_HOST_MEM_RETURN;
2028 else
2029 nvme_free_host_mem(dev);
2030 }
2031
2032 if (!dev->host_mem_descs) {
92dc6895
CH		 2033 if (nvme_alloc_host_mem(dev, min, preferred)) {
2034 dev_warn(dev->ctrl.device,
2035 "failed to allocate host memory buffer.\n");
9620cfba 2036 return 0; /* controller must work without HMB */
92dc6895
CH		 2037 }
2038
2039 dev_info(dev->ctrl.device,
2040 "allocated %lld MiB host memory buffer.\n",
2041 dev->host_mem_size >> ilog2(SZ_1M));
87ad72a5
CH		 2042 }
2043
9620cfba
CH		 2044 ret = nvme_set_host_mem(dev, enable_bits);
2045 if (ret)
87ad72a5 2046 nvme_free_host_mem(dev);
9620cfba 2047 return ret;
9d713c2b
KB		 2048}
2049
612b7286
ML		 2050/*
2051 * nirqs is the number of interrupts available for write and read
2052 * queues. The core already reserved an interrupt for the admin queue.
2053 */
2054static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs)
3b6592f7 2055{
612b7286
ML		 2056 struct nvme_dev *dev = affd->priv;
2057 unsigned int nr_read_queues;
3b6592f7
JA		 2058
2059 /*
612b7286
ML		 2060 * If there is no interupt available for queues, ensure that
2061 * the default queue is set to 1. The affinity set size is
2062 * also set to one, but the irq core ignores it for this case.
2063 *
2064 * If only one interrupt is available or 'write_queue' == 0, combine
2065 * write and read queues.
2066 *
2067 * If 'write_queues' > 0, ensure it leaves room for at least one read
2068 * queue.
3b6592f7 2069 */
612b7286
ML		 2070 if (!nrirqs) {
2071 nrirqs = 1;
2072 nr_read_queues = 0;
2073 } else if (nrirqs == 1 || !write_queues) {
2074 nr_read_queues = 0;
2075 } else if (write_queues >= nrirqs) {
2076 nr_read_queues = 1;
3b6592f7 2077 } else {
612b7286 2078 nr_read_queues = nrirqs - write_queues;
3b6592f7 2079 }
612b7286
ML		 2080
2081 dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2082 affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2083 dev->io_queues[HCTX_TYPE_READ] = nr_read_queues;
2084 affd->set_size[HCTX_TYPE_READ] = nr_read_queues;
2085 affd->nr_sets = nr_read_queues ? 2 : 1;
3b6592f7
JA		 2086}
2087
6451fe73 2088static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues)
3b6592f7
JA		 2089{
2090 struct pci_dev *pdev = to_pci_dev(dev->dev);
3b6592f7 2091 struct irq_affinity affd = {
9cfef55b 2092 .pre_vectors = 1,
612b7286
ML		 2093 .calc_sets = nvme_calc_irq_sets,
2094 .priv = dev,
3b6592f7 2095 };
6451fe73
JA		 2096 unsigned int irq_queues, this_p_queues;
2097
2098 /*
2099 * Poll queues don't need interrupts, but we need at least one IO
2100 * queue left over for non-polled IO.
2101 */
2102 this_p_queues = poll_queues;
2103 if (this_p_queues >= nr_io_queues) {
2104 this_p_queues = nr_io_queues - 1;
2105 irq_queues = 1;
2106 } else {
c45b1fa2 2107 irq_queues = nr_io_queues - this_p_queues + 1;
6451fe73
JA		 2108 }
2109 dev->io_queues[HCTX_TYPE_POLL] = this_p_queues;
3b6592f7 2110
612b7286
ML		 2111 /* Initialize for the single interrupt case */
2112 dev->io_queues[HCTX_TYPE_DEFAULT] = 1;
2113 dev->io_queues[HCTX_TYPE_READ] = 0;
3b6592f7 2114
612b7286
ML		 2115 return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues,
2116 PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd);
3b6592f7
JA		 2117}
2118
8fae268b
KB		 2119static void nvme_disable_io_queues(struct nvme_dev *dev)
2120{
2121 if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq))
2122 __nvme_disable_io_queues(dev, nvme_admin_delete_cq);
2123}
2124
8d85fce7 2125static int nvme_setup_io_queues(struct nvme_dev *dev)
b60503ba 2126{
147b27e4 2127 struct nvme_queue *adminq = &dev->queues[0];
e75ec752 2128 struct pci_dev *pdev = to_pci_dev(dev->dev);
97f6ef64
XY		 2129 int result, nr_io_queues;
2130 unsigned long size;
b60503ba 2131
3b6592f7 2132 nr_io_queues = max_io_queues();
9a0be7ab
CH		 2133 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
2134 if (result < 0)
1b23484b 2135 return result;
9a0be7ab 2136
f5fa90dc 2137 if (nr_io_queues == 0)
a5229050 2138 return 0;
4e224106
CH		 2139
2140 clear_bit(NVMEQ_ENABLED, &adminq->flags);
b60503ba 2141
0f238ff5 2142 if (dev->cmb_use_sqes) {
8ffaadf7
JD		 2143 result = nvme_cmb_qdepth(dev, nr_io_queues,
2144 sizeof(struct nvme_command));
2145 if (result > 0)
2146 dev->q_depth = result;
2147 else
0f238ff5 2148 dev->cmb_use_sqes = false;
8ffaadf7
JD		 2149 }
2150
97f6ef64
XY		 2151 do {
2152 size = db_bar_size(dev, nr_io_queues);
2153 result = nvme_remap_bar(dev, size);
2154 if (!result)
2155 break;
2156 if (!--nr_io_queues)
2157 return -ENOMEM;
2158 } while (1);
2159 adminq->q_db = dev->dbs;
f1938f6e 2160
8fae268b 2161 retry:
9d713c2b 2162 /* Deregister the admin queue's interrupt */
0ff199cb 2163 pci_free_irq(pdev, 0, adminq);
9d713c2b 2164
e32efbfc
JA		 2165 /*
2166 * If we enable msix early due to not intx, disable it again before
2167 * setting up the full range we need.
2168 */
dca51e78 2169 pci_free_irq_vectors(pdev);
3b6592f7
JA		 2170
2171 result = nvme_setup_irqs(dev, nr_io_queues);
22b55601 2172 if (result <= 0)
dca51e78 2173 return -EIO;
3b6592f7 2174
22b55601 2175 dev->num_vecs = result;
4b04cc6a 2176 result = max(result - 1, 1);
e20ba6e1 2177 dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL];
fa08a396 2178
063a8096
MW		 2179 /*
2180 * Should investigate if there's a performance win from allocating
2181 * more queues than interrupt vectors; it might allow the submission
2182 * path to scale better, even if the receive path is limited by the
2183 * number of interrupts.
2184 */
dca51e78 2185 result = queue_request_irq(adminq);
7c349dde 2186 if (result)
d4875622 2187 return result;
4e224106 2188 set_bit(NVMEQ_ENABLED, &adminq->flags);
8fae268b
KB		 2189
2190 result = nvme_create_io_queues(dev);
2191 if (result || dev->online_queues < 2)
2192 return result;
2193
2194 if (dev->online_queues - 1 < dev->max_qid) {
2195 nr_io_queues = dev->online_queues - 1;
2196 nvme_disable_io_queues(dev);
2197 nvme_suspend_io_queues(dev);
2198 goto retry;
2199 }
2200 dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n",
2201 dev->io_queues[HCTX_TYPE_DEFAULT],
2202 dev->io_queues[HCTX_TYPE_READ],
2203 dev->io_queues[HCTX_TYPE_POLL]);
2204 return 0;
b60503ba
MW		 2205}
2206
2a842aca 2207static void nvme_del_queue_end(struct request *req, blk_status_t error)
a5768aa8 2208{
db3cbfff 2209 struct nvme_queue *nvmeq = req->end_io_data;
b5875222 2210
db3cbfff 2211 blk_mq_free_request(req);
d1ed6aa1 2212 complete(&nvmeq->delete_done);
a5768aa8
KB		 2213}
2214
2a842aca 2215static void nvme_del_cq_end(struct request *req, blk_status_t error)
a5768aa8 2216{
db3cbfff 2217 struct nvme_queue *nvmeq = req->end_io_data;
a5768aa8 2218
d1ed6aa1
CH		 2219 if (error)
2220 set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
db3cbfff
KB		 2221
2222 nvme_del_queue_end(req, error);
a5768aa8
KB		 2223}
2224
db3cbfff 2225static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
bda4e0fb 2226{
db3cbfff
KB		 2227 struct request_queue *q = nvmeq->dev->ctrl.admin_q;
2228 struct request *req;
2229 struct nvme_command cmd;
bda4e0fb 2230
db3cbfff
KB		 2231 memset(&cmd, 0, sizeof(cmd));
2232 cmd.delete_queue.opcode = opcode;
2233 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
bda4e0fb 2234
eb71f435 2235 req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
db3cbfff
KB		 2236 if (IS_ERR(req))
2237 return PTR_ERR(req);
bda4e0fb 2238
db3cbfff
KB		 2239 req->timeout = ADMIN_TIMEOUT;
2240 req->end_io_data = nvmeq;
2241
d1ed6aa1 2242 init_completion(&nvmeq->delete_done);
db3cbfff
KB		 2243 blk_execute_rq_nowait(q, NULL, req, false,
2244 opcode == nvme_admin_delete_cq ?
2245 nvme_del_cq_end : nvme_del_queue_end);
2246 return 0;
bda4e0fb
KB		 2247}
2248
8fae268b 2249static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode)
a5768aa8 2250{
5271edd4 2251 int nr_queues = dev->online_queues - 1, sent = 0;
db3cbfff 2252 unsigned long timeout;
a5768aa8 2253
db3cbfff 2254 retry:
5271edd4
CH		 2255 timeout = ADMIN_TIMEOUT;
2256 while (nr_queues > 0) {
2257 if (nvme_delete_queue(&dev->queues[nr_queues], opcode))
2258 break;
2259 nr_queues--;
2260 sent++;
db3cbfff 2261 }
d1ed6aa1
CH		 2262 while (sent) {
2263 struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent];
2264
2265 timeout = wait_for_completion_io_timeout(&nvmeq->delete_done,
5271edd4
CH		 2266 timeout);
2267 if (timeout == 0)
2268 return false;
d1ed6aa1
CH		 2269
2270 /* handle any remaining CQEs */
2271 if (opcode == nvme_admin_delete_cq &&
2272 !test_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags))
2273 nvme_poll_irqdisable(nvmeq, -1);
2274
2275 sent--;
5271edd4
CH		 2276 if (nr_queues)
2277 goto retry;
2278 }
2279 return true;
a5768aa8
KB		 2280}
2281
422ef0c7 2282/*
2b1b7e78 2283 * return error value only when tagset allocation failed
422ef0c7 2284 */
8d85fce7 2285static int nvme_dev_add(struct nvme_dev *dev)
b60503ba 2286{
2b1b7e78
JW		 2287 int ret;
2288
5bae7f73 2289 if (!dev->ctrl.tagset) {
376f7ef8 2290 dev->tagset.ops = &nvme_mq_ops;
ffe7704d 2291 dev->tagset.nr_hw_queues = dev->online_queues - 1;
ed92ad37
CH		 2292 dev->tagset.nr_maps = 2; /* default + read */
2293 if (dev->io_queues[HCTX_TYPE_POLL])
2294 dev->tagset.nr_maps++;
ffe7704d
KB		 2295 dev->tagset.timeout = NVME_IO_TIMEOUT;
2296 dev->tagset.numa_node = dev_to_node(dev->dev);
2297 dev->tagset.queue_depth =
a4aea562 2298 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
d43f1ccf 2299 dev->tagset.cmd_size = sizeof(struct nvme_iod);
ffe7704d
KB		 2300 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2301 dev->tagset.driver_data = dev;
b60503ba 2302
2b1b7e78
JW		 2303 ret = blk_mq_alloc_tag_set(&dev->tagset);
2304 if (ret) {
2305 dev_warn(dev->ctrl.device,
2306 "IO queues tagset allocation failed %d\n", ret);
2307 return ret;
2308 }
5bae7f73 2309 dev->ctrl.tagset = &dev->tagset;
f9f38e33
HK		 2310
2311 nvme_dbbuf_set(dev);
949928c1
KB		 2312 } else {
2313 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2314
2315 /* Free previously allocated queues that are no longer usable */
2316 nvme_free_queues(dev, dev->online_queues);
ffe7704d 2317 }
949928c1 2318
e1e5e564 2319 return 0;
b60503ba
MW		 2320}
2321
b00a726a 2322static int nvme_pci_enable(struct nvme_dev *dev)
0877cb0d 2323{
b00a726a 2324 int result = -ENOMEM;
e75ec752 2325 struct pci_dev *pdev = to_pci_dev(dev->dev);
0877cb0d
KB		 2326
2327 if (pci_enable_device_mem(pdev))
2328 return result;
2329
0877cb0d 2330 pci_set_master(pdev);
0877cb0d 2331
e75ec752
CH		 2332 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) &&
2333 dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32)))
052d0efa 2334 goto disable;
0877cb0d 2335
7a67cbea 2336 if (readl(dev->bar + NVME_REG_CSTS) == -1) {
0e53d180 2337 result = -ENODEV;
b00a726a 2338 goto disable;
0e53d180 2339 }
e32efbfc
JA		 2340
2341 /*
a5229050
KB		 2342 * Some devices and/or platforms don't advertise or work with INTx
2343 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2344 * adjust this later.
e32efbfc 2345 */
dca51e78
CH		 2346 result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
2347 if (result < 0)
2348 return result;
e32efbfc 2349
20d0dfe6 2350 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
7a67cbea 2351
20d0dfe6 2352 dev->q_depth = min_t(int, NVME_CAP_MQES(dev->ctrl.cap) + 1,
b27c1e68 2353 io_queue_depth);
20d0dfe6 2354 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
7a67cbea 2355 dev->dbs = dev->bar + 4096;
1f390c1f
SG		 2356
2357 /*
2358 * Temporary fix for the Apple controller found in the MacBook8,1 and
2359 * some MacBook7,1 to avoid controller resets and data loss.
2360 */
2361 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
2362 dev->q_depth = 2;
9bdcfb10
CH		 2363 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
2364 "set queue depth=%u to work around controller resets\n",
1f390c1f 2365 dev->q_depth);
d554b5e1
MP		 2366 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2367 (pdev->device == 0xa821 || pdev->device == 0xa822) &&
20d0dfe6 2368 NVME_CAP_MQES(dev->ctrl.cap) == 0) {
d554b5e1
MP		 2369 dev->q_depth = 64;
2370 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2371 "set queue depth=%u\n", dev->q_depth);
1f390c1f
SG		 2372 }
2373
f65efd6d 2374 nvme_map_cmb(dev);
202021c1 2375
a0a3408e
KB		 2376 pci_enable_pcie_error_reporting(pdev);
2377 pci_save_state(pdev);
0877cb0d
KB		 2378 return 0;
2379
2380 disable:
0877cb0d
KB		 2381 pci_disable_device(pdev);
2382 return result;
2383}
2384
2385static void nvme_dev_unmap(struct nvme_dev *dev)
b00a726a
KB		 2386{
2387 if (dev->bar)
2388 iounmap(dev->bar);
a1f447b3 2389 pci_release_mem_regions(to_pci_dev(dev->dev));
b00a726a
KB		 2390}
2391
2392static void nvme_pci_disable(struct nvme_dev *dev)
0877cb0d 2393{
e75ec752
CH		 2394 struct pci_dev *pdev = to_pci_dev(dev->dev);
2395
dca51e78 2396 pci_free_irq_vectors(pdev);
0877cb0d 2397
a0a3408e
KB		 2398 if (pci_is_enabled(pdev)) {
2399 pci_disable_pcie_error_reporting(pdev);
e75ec752 2400 pci_disable_device(pdev);
4d115420 2401 }
4d115420
KB		 2402}
2403
a5cdb68c 2404static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
b60503ba 2405{
302ad8cc
KB		 2406 bool dead = true;
2407 struct pci_dev *pdev = to_pci_dev(dev->dev);
22404274 2408
77bf25ea 2409 mutex_lock(&dev->shutdown_lock);
302ad8cc
KB		 2410 if (pci_is_enabled(pdev)) {
2411 u32 csts = readl(dev->bar + NVME_REG_CSTS);
2412
ebef7368
KB		 2413 if (dev->ctrl.state == NVME_CTRL_LIVE ||
2414 dev->ctrl.state == NVME_CTRL_RESETTING)
302ad8cc
KB		 2415 nvme_start_freeze(&dev->ctrl);
2416 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
2417 pdev->error_state != pci_channel_io_normal);
c9d3bf88 2418 }
c21377f8 2419
302ad8cc
KB		 2420 /*
2421 * Give the controller a chance to complete all entered requests if
2422 * doing a safe shutdown.
2423 */
87ad72a5
CH		 2424 if (!dead) {
2425 if (shutdown)
2426 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
9a915a5b
JW		 2427 }
2428
2429 nvme_stop_queues(&dev->ctrl);
87ad72a5 2430
64ee0ac0 2431 if (!dead && dev->ctrl.queue_count > 0) {
8fae268b 2432 nvme_disable_io_queues(dev);
a5cdb68c 2433 nvme_disable_admin_queue(dev, shutdown);
4d115420 2434 }
8fae268b
KB		 2435 nvme_suspend_io_queues(dev);
2436 nvme_suspend_queue(&dev->queues[0]);
b00a726a 2437 nvme_pci_disable(dev);
07836e65 2438
e1958e65
ML		 2439 blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
2440 blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
302ad8cc
KB		 2441
2442 /*
2443 * The driver will not be starting up queues again if shutting down so
2444 * must flush all entered requests to their failed completion to avoid
2445 * deadlocking blk-mq hot-cpu notifier.
2446 */
c8e9e9b7 2447 if (shutdown) {
302ad8cc 2448 nvme_start_queues(&dev->ctrl);
c8e9e9b7
KB		 2449 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q))
2450 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
2451 }
77bf25ea 2452 mutex_unlock(&dev->shutdown_lock);
b60503ba
MW		 2453}
2454
091b6092
MW		 2455static int nvme_setup_prp_pools(struct nvme_dev *dev)
2456{
e75ec752 2457 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
091b6092
MW		 2458 PAGE_SIZE, PAGE_SIZE, 0);
2459 if (!dev->prp_page_pool)
2460 return -ENOMEM;
2461
99802a7a 2462 /* Optimisation for I/Os between 4k and 128k */
e75ec752 2463 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
99802a7a
MW		 2464 256, 256, 0);
2465 if (!dev->prp_small_pool) {
2466 dma_pool_destroy(dev->prp_page_pool);
2467 return -ENOMEM;
2468 }
091b6092
MW		 2469 return 0;
2470}
2471
2472static void nvme_release_prp_pools(struct nvme_dev *dev)
2473{
2474 dma_pool_destroy(dev->prp_page_pool);
99802a7a 2475 dma_pool_destroy(dev->prp_small_pool);
091b6092
MW		 2476}
2477
1673f1f0 2478static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
5e82e952 2479{
1673f1f0 2480 struct nvme_dev *dev = to_nvme_dev(ctrl);
9ac27090 2481
f9f38e33 2482 nvme_dbbuf_dma_free(dev);
e75ec752 2483 put_device(dev->dev);
4af0e21c
KB		 2484 if (dev->tagset.tags)
2485 blk_mq_free_tag_set(&dev->tagset);
1c63dc66
CH		 2486 if (dev->ctrl.admin_q)
2487 blk_put_queue(dev->ctrl.admin_q);
5e82e952 2488 kfree(dev->queues);
e286bcfc 2489 free_opal_dev(dev->ctrl.opal_dev);
943e942e 2490 mempool_destroy(dev->iod_mempool);
5e82e952
KB		 2491 kfree(dev);
2492}
2493
f58944e2
KB		 2494static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status)
2495{
237045fc 2496 dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status);
f58944e2 2497
d22524a4 2498 nvme_get_ctrl(&dev->ctrl);
69d9a99c 2499 nvme_dev_disable(dev, false);
9f9cafc1 2500 nvme_kill_queues(&dev->ctrl);
03e0f3a6 2501 if (!queue_work(nvme_wq, &dev->remove_work))
f58944e2
KB		 2502 nvme_put_ctrl(&dev->ctrl);
2503}
2504
fd634f41 2505static void nvme_reset_work(struct work_struct *work)
5e82e952 2506{
d86c4d8e
CH		 2507 struct nvme_dev *dev =
2508 container_of(work, struct nvme_dev, ctrl.reset_work);
a98e58e5 2509 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
f58944e2 2510 int result = -ENODEV;
2b1b7e78 2511 enum nvme_ctrl_state new_state = NVME_CTRL_LIVE;
5e82e952 2512
82b057ca 2513 if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING))
fd634f41 2514 goto out;
5e82e952 2515
fd634f41
CH		 2516 /*
2517 * If we're called to reset a live controller first shut it down before
2518 * moving on.
2519 */
b00a726a 2520 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
a5cdb68c 2521 nvme_dev_disable(dev, false);
5e82e952 2522
5c959d73 2523 mutex_lock(&dev->shutdown_lock);
b00a726a 2524 result = nvme_pci_enable(dev);
f0b50732 2525 if (result)
4726bcf3 2526 goto out_unlock;
f0b50732 2527
01ad0990 2528 result = nvme_pci_configure_admin_queue(dev);
f0b50732 2529 if (result)
4726bcf3 2530 goto out_unlock;
f0b50732 2531
0fb59cbc
KB		 2532 result = nvme_alloc_admin_tags(dev);
2533 if (result)
4726bcf3 2534 goto out_unlock;
b9afca3e 2535
943e942e
JA		 2536 /*
2537 * Limit the max command size to prevent iod->sg allocations going
2538 * over a single page.
2539 */
2540 dev->ctrl.max_hw_sectors = NVME_MAX_KB_SZ << 1;
2541 dev->ctrl.max_segments = NVME_MAX_SEGS;
5c959d73
KB		 2542 mutex_unlock(&dev->shutdown_lock);
2543
2544 /*
2545 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
2546 * initializing procedure here.
2547 */
2548 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
2549 dev_warn(dev->ctrl.device,
2550 "failed to mark controller CONNECTING\n");
2551 goto out;
2552 }
943e942e 2553
ce4541f4
CH		 2554 result = nvme_init_identify(&dev->ctrl);
2555 if (result)
f58944e2 2556 goto out;
ce4541f4 2557
e286bcfc
SB		 2558 if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
2559 if (!dev->ctrl.opal_dev)
2560 dev->ctrl.opal_dev =
2561 init_opal_dev(&dev->ctrl, &nvme_sec_submit);
2562 else if (was_suspend)
2563 opal_unlock_from_suspend(dev->ctrl.opal_dev);
2564 } else {
2565 free_opal_dev(dev->ctrl.opal_dev);
2566 dev->ctrl.opal_dev = NULL;
4f1244c8 2567 }
a98e58e5 2568
f9f38e33
HK		 2569 if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) {
2570 result = nvme_dbbuf_dma_alloc(dev);
2571 if (result)
2572 dev_warn(dev->dev,
2573 "unable to allocate dma for dbbuf\n");
2574 }
2575
9620cfba
CH		 2576 if (dev->ctrl.hmpre) {
2577 result = nvme_setup_host_mem(dev);
2578 if (result < 0)
2579 goto out;
2580 }
87ad72a5 2581
f0b50732 2582 result = nvme_setup_io_queues(dev);
badc34d4 2583 if (result)
f58944e2 2584 goto out;
f0b50732 2585
2659e57b
CH		 2586 /*
2587 * Keep the controller around but remove all namespaces if we don't have
2588 * any working I/O queue.
2589 */
3cf519b5 2590 if (dev->online_queues < 2) {
1b3c47c1 2591 dev_warn(dev->ctrl.device, "IO queues not created\n");
3b24774e 2592 nvme_kill_queues(&dev->ctrl);
5bae7f73 2593 nvme_remove_namespaces(&dev->ctrl);
2b1b7e78 2594 new_state = NVME_CTRL_ADMIN_ONLY;
3cf519b5 2595 } else {
25646264 2596 nvme_start_queues(&dev->ctrl);
302ad8cc 2597 nvme_wait_freeze(&dev->ctrl);
2b1b7e78
JW		 2598 /* hit this only when allocate tagset fails */
2599 if (nvme_dev_add(dev))
2600 new_state = NVME_CTRL_ADMIN_ONLY;
302ad8cc 2601 nvme_unfreeze(&dev->ctrl);
3cf519b5
CH		 2602 }
2603
2b1b7e78
JW		 2604 /*
2605 * If only admin queue live, keep it to do further investigation or
2606 * recovery.
2607 */
2608 if (!nvme_change_ctrl_state(&dev->ctrl, new_state)) {
2609 dev_warn(dev->ctrl.device,
2610 "failed to mark controller state %d\n", new_state);
bb8d261e
CH		 2611 goto out;
2612 }
92911a55 2613
d09f2b45 2614 nvme_start_ctrl(&dev->ctrl);
3cf519b5 2615 return;
f0b50732 2616
4726bcf3
KB		 2617 out_unlock:
2618 mutex_unlock(&dev->shutdown_lock);
3cf519b5 2619 out:
f58944e2 2620 nvme_remove_dead_ctrl(dev, result);
f0b50732
KB		 2621}
2622
5c8809e6 2623static void nvme_remove_dead_ctrl_work(struct work_struct *work)
9a6b9458 2624{
5c8809e6 2625 struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
e75ec752 2626 struct pci_dev *pdev = to_pci_dev(dev->dev);
9a6b9458
KB		 2627
2628 if (pci_get_drvdata(pdev))
921920ab 2629 device_release_driver(&pdev->dev);
1673f1f0 2630 nvme_put_ctrl(&dev->ctrl);
9a6b9458
KB		 2631}
2632
1c63dc66 2633static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
9ca97374 2634{
1c63dc66 2635 *val = readl(to_nvme_dev(ctrl)->bar + off);
90667892 2636 return 0;
9ca97374
TH		 2637}
2638
5fd4ce1b 2639static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
4cc06521 2640{
5fd4ce1b
CH		 2641 writel(val, to_nvme_dev(ctrl)->bar + off);
2642 return 0;
2643}
4cc06521 2644
7fd8930f
CH		 2645static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2646{
2647 *val = readq(to_nvme_dev(ctrl)->bar + off);
2648 return 0;
4cc06521
KB		 2649}
2650
97c12223
KB		 2651static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
2652{
2653 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2654
2655 return snprintf(buf, size, "%s", dev_name(&pdev->dev));
2656}
2657
1c63dc66 2658static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
1a353d85 2659 .name = "pcie",
e439bb12 2660 .module = THIS_MODULE,
e0596ab2
LG		 2661 .flags = NVME_F_METADATA_SUPPORTED |
2662 NVME_F_PCI_P2PDMA,
1c63dc66 2663 .reg_read32 = nvme_pci_reg_read32,
5fd4ce1b 2664 .reg_write32 = nvme_pci_reg_write32,
7fd8930f 2665 .reg_read64 = nvme_pci_reg_read64,
1673f1f0 2666 .free_ctrl = nvme_pci_free_ctrl,
f866fc42 2667 .submit_async_event = nvme_pci_submit_async_event,
97c12223 2668 .get_address = nvme_pci_get_address,
1c63dc66 2669};
4cc06521 2670
b00a726a
KB		 2671static int nvme_dev_map(struct nvme_dev *dev)
2672{
b00a726a
KB		 2673 struct pci_dev *pdev = to_pci_dev(dev->dev);
2674
a1f447b3 2675 if (pci_request_mem_regions(pdev, "nvme"))
b00a726a
KB		 2676 return -ENODEV;
2677
97f6ef64 2678 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
b00a726a
KB		 2679 goto release;
2680
9fa196e7 2681 return 0;
b00a726a 2682 release:
9fa196e7
MG		 2683 pci_release_mem_regions(pdev);
2684 return -ENODEV;
b00a726a
KB		 2685}
2686
8427bbc2 2687static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
ff5350a8
AL		 2688{
2689 if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
2690 /*
2691 * Several Samsung devices seem to drop off the PCIe bus
2692 * randomly when APST is on and uses the deepest sleep state.
2693 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2694 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2695 * 950 PRO 256GB", but it seems to be restricted to two Dell
2696 * laptops.
2697 */
2698 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
2699 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
2700 dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
2701 return NVME_QUIRK_NO_DEEPEST_PS;
8427bbc2
KHF		 2702 } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
2703 /*
2704 * Samsung SSD 960 EVO drops off the PCIe bus after system
467c77d4
JJ		 2705 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
2706 * within few minutes after bootup on a Coffee Lake board -
2707 * ASUS PRIME Z370-A
8427bbc2
KHF		 2708 */
2709 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
467c77d4
JJ		 2710 (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") ||
2711 dmi_match(DMI_BOARD_NAME, "PRIME Z370-A")))
8427bbc2 2712 return NVME_QUIRK_NO_APST;
ff5350a8
AL		 2713 }
2714
2715 return 0;
2716}
2717
18119775
KB		 2718static void nvme_async_probe(void *data, async_cookie_t cookie)
2719{
2720 struct nvme_dev *dev = data;
80f513b5 2721
18119775
KB		 2722 nvme_reset_ctrl_sync(&dev->ctrl);
2723 flush_work(&dev->ctrl.scan_work);
80f513b5 2724 nvme_put_ctrl(&dev->ctrl);
18119775
KB		 2725}
2726
8d85fce7 2727static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
b60503ba 2728{
a4aea562 2729 int node, result = -ENOMEM;
b60503ba 2730 struct nvme_dev *dev;
ff5350a8 2731 unsigned long quirks = id->driver_data;
943e942e 2732 size_t alloc_size;
b60503ba 2733
a4aea562
MB		 2734 node = dev_to_node(&pdev->dev);
2735 if (node == NUMA_NO_NODE)
2fa84351 2736 set_dev_node(&pdev->dev, first_memory_node);
a4aea562
MB		 2737
2738 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
b60503ba
MW		 2739 if (!dev)
2740 return -ENOMEM;
147b27e4 2741
3b6592f7
JA		 2742 dev->queues = kcalloc_node(max_queue_count(), sizeof(struct nvme_queue),
2743 GFP_KERNEL, node);
b60503ba
MW		 2744 if (!dev->queues)
2745 goto free;
2746
e75ec752 2747 dev->dev = get_device(&pdev->dev);
9a6b9458 2748 pci_set_drvdata(pdev, dev);
1c63dc66 2749
b00a726a
KB		 2750 result = nvme_dev_map(dev);
2751 if (result)
b00c9b7a 2752 goto put_pci;
b00a726a 2753
d86c4d8e 2754 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
5c8809e6 2755 INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
77bf25ea 2756 mutex_init(&dev->shutdown_lock);
b60503ba 2757
091b6092
MW		 2758 result = nvme_setup_prp_pools(dev);
2759 if (result)
b00c9b7a 2760 goto unmap;
4cc06521 2761
8427bbc2 2762 quirks |= check_vendor_combination_bug(pdev);
ff5350a8 2763
943e942e
JA		 2764 /*
2765 * Double check that our mempool alloc size will cover the biggest
2766 * command we support.
2767 */
2768 alloc_size = nvme_pci_iod_alloc_size(dev, NVME_MAX_KB_SZ,
2769 NVME_MAX_SEGS, true);
2770 WARN_ON_ONCE(alloc_size > PAGE_SIZE);
2771
2772 dev->iod_mempool = mempool_create_node(1, mempool_kmalloc,
2773 mempool_kfree,
2774 (void *) alloc_size,
2775 GFP_KERNEL, node);
2776 if (!dev->iod_mempool) {
2777 result = -ENOMEM;
2778 goto release_pools;
2779 }
2780
b6e44b4c
KB		 2781 result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
2782 quirks);
2783 if (result)
2784 goto release_mempool;
2785
1b3c47c1
SG		 2786 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
2787
80f513b5 2788 nvme_get_ctrl(&dev->ctrl);
18119775 2789 async_schedule(nvme_async_probe, dev);
4caff8fc 2790
b60503ba
MW		 2791 return 0;
2792
b6e44b4c
KB		 2793 release_mempool:
2794 mempool_destroy(dev->iod_mempool);
0877cb0d 2795 release_pools:
091b6092 2796 nvme_release_prp_pools(dev);
b00c9b7a
CJ		 2797 unmap:
2798 nvme_dev_unmap(dev);
a96d4f5c 2799 put_pci:
e75ec752 2800 put_device(dev->dev);
b60503ba
MW		 2801 free:
2802 kfree(dev->queues);
b60503ba
MW		 2803 kfree(dev);
2804 return result;
2805}
2806
775755ed 2807static void nvme_reset_prepare(struct pci_dev *pdev)
f0d54a54 2808{
a6739479 2809 struct nvme_dev *dev = pci_get_drvdata(pdev);
f263fbb8 2810 nvme_dev_disable(dev, false);
775755ed 2811}
f0d54a54 2812
775755ed
CH		 2813static void nvme_reset_done(struct pci_dev *pdev)
2814{
f263fbb8 2815 struct nvme_dev *dev = pci_get_drvdata(pdev);
79c48ccf 2816 nvme_reset_ctrl_sync(&dev->ctrl);
f0d54a54
KB		 2817}
2818
09ece142
KB		 2819static void nvme_shutdown(struct pci_dev *pdev)
2820{
2821 struct nvme_dev *dev = pci_get_drvdata(pdev);
a5cdb68c 2822 nvme_dev_disable(dev, true);
09ece142
KB		 2823}
2824
f58944e2
KB		 2825/*
2826 * The driver's remove may be called on a device in a partially initialized
2827 * state. This function must not have any dependencies on the device state in
2828 * order to proceed.
2829 */
8d85fce7 2830static void nvme_remove(struct pci_dev *pdev)
b60503ba
MW		 2831{
2832 struct nvme_dev *dev = pci_get_drvdata(pdev);
9a6b9458 2833
bb8d261e 2834 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
9a6b9458 2835 pci_set_drvdata(pdev, NULL);
0ff9d4e1 2836
6db28eda 2837 if (!pci_device_is_present(pdev)) {
0ff9d4e1 2838 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
1d39e692 2839 nvme_dev_disable(dev, true);
cb4bfda6 2840 nvme_dev_remove_admin(dev);
6db28eda 2841 }
0ff9d4e1 2842
d86c4d8e 2843 flush_work(&dev->ctrl.reset_work);
d09f2b45
SG		 2844 nvme_stop_ctrl(&dev->ctrl);
2845 nvme_remove_namespaces(&dev->ctrl);
a5cdb68c 2846 nvme_dev_disable(dev, true);
9fe5c59f 2847 nvme_release_cmb(dev);
87ad72a5 2848 nvme_free_host_mem(dev);
a4aea562 2849 nvme_dev_remove_admin(dev);
a1a5ef99 2850 nvme_free_queues(dev, 0);
d09f2b45 2851 nvme_uninit_ctrl(&dev->ctrl);
9a6b9458 2852 nvme_release_prp_pools(dev);
b00a726a 2853 nvme_dev_unmap(dev);
1673f1f0 2854 nvme_put_ctrl(&dev->ctrl);
b60503ba
MW		 2855}
2856
671a6018 2857#ifdef CONFIG_PM_SLEEP
cd638946
KB		 2858static int nvme_suspend(struct device *dev)
2859{
2860 struct pci_dev *pdev = to_pci_dev(dev);
2861 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2862
a5cdb68c 2863 nvme_dev_disable(ndev, true);
cd638946
KB		 2864 return 0;
2865}
2866
2867static int nvme_resume(struct device *dev)
2868{
2869 struct pci_dev *pdev = to_pci_dev(dev);
2870 struct nvme_dev *ndev = pci_get_drvdata(pdev);
cd638946 2871
d86c4d8e 2872 nvme_reset_ctrl(&ndev->ctrl);
9a6b9458 2873 return 0;
cd638946 2874}
671a6018 2875#endif
cd638946
KB		 2876
2877static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
b60503ba 2878
a0a3408e
KB		 2879static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
2880 pci_channel_state_t state)
2881{
2882 struct nvme_dev *dev = pci_get_drvdata(pdev);
2883
2884 /*
2885 * A frozen channel requires a reset. When detected, this method will
2886 * shutdown the controller to quiesce. The controller will be restarted
2887 * after the slot reset through driver's slot_reset callback.
2888 */
a0a3408e
KB		 2889 switch (state) {
2890 case pci_channel_io_normal:
2891 return PCI_ERS_RESULT_CAN_RECOVER;
2892 case pci_channel_io_frozen:
d011fb31
KB		 2893 dev_warn(dev->ctrl.device,
2894 "frozen state error detected, reset controller\n");
a5cdb68c 2895 nvme_dev_disable(dev, false);
a0a3408e
KB		 2896 return PCI_ERS_RESULT_NEED_RESET;
2897 case pci_channel_io_perm_failure:
d011fb31
KB		 2898 dev_warn(dev->ctrl.device,
2899 "failure state error detected, request disconnect\n");
a0a3408e
KB		 2900 return PCI_ERS_RESULT_DISCONNECT;
2901 }
2902 return PCI_ERS_RESULT_NEED_RESET;
2903}
2904
2905static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
2906{
2907 struct nvme_dev *dev = pci_get_drvdata(pdev);
2908
1b3c47c1 2909 dev_info(dev->ctrl.device, "restart after slot reset\n");
a0a3408e 2910 pci_restore_state(pdev);
d86c4d8e 2911 nvme_reset_ctrl(&dev->ctrl);
a0a3408e
KB		 2912 return PCI_ERS_RESULT_RECOVERED;
2913}
2914
2915static void nvme_error_resume(struct pci_dev *pdev)
2916{
72cd4cc2
KB		 2917 struct nvme_dev *dev = pci_get_drvdata(pdev);
2918
2919 flush_work(&dev->ctrl.reset_work);
a0a3408e
KB		 2920}
2921
1d352035 2922static const struct pci_error_handlers nvme_err_handler = {
b60503ba 2923 .error_detected = nvme_error_detected,
b60503ba
MW		 2924 .slot_reset = nvme_slot_reset,
2925 .resume = nvme_error_resume,
775755ed
CH		 2926 .reset_prepare = nvme_reset_prepare,
2927 .reset_done = nvme_reset_done,
b60503ba
MW		 2928};
2929
6eb0d698 2930static const struct pci_device_id nvme_id_table[] = {
106198ed 2931 { PCI_VDEVICE(INTEL, 0x0953),
08095e70 2932 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 2933 NVME_QUIRK_DEALLOCATE_ZEROES, },
99466e70
KB		 2934 { PCI_VDEVICE(INTEL, 0x0a53),
2935 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 2936 NVME_QUIRK_DEALLOCATE_ZEROES, },
99466e70
KB		 2937 { PCI_VDEVICE(INTEL, 0x0a54),
2938 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 2939 NVME_QUIRK_DEALLOCATE_ZEROES, },
f99cb7af
DWF		 2940 { PCI_VDEVICE(INTEL, 0x0a55),
2941 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2942 NVME_QUIRK_DEALLOCATE_ZEROES, },
50af47d0 2943 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */
9abd68ef
JA		 2944 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
2945 NVME_QUIRK_MEDIUM_PRIO_SQ },
6299358d
JD		 2946 { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */
2947 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
540c801c 2948 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */
7b210e4e
CH		 2949 .driver_data = NVME_QUIRK_IDENTIFY_CNS |
2950 NVME_QUIRK_DISABLE_WRITE_ZEROES, },
0302ae60
MP		 2951 { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */
2952 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
54adc010
GP		 2953 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
2954 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
8c97eecc
JL		 2955 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */
2956 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
015282c9
WW		 2957 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
2958 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
d554b5e1
MP		 2959 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */
2960 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2961 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */
2962 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
608cc4b1
CH		 2963 { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */
2964 .driver_data = NVME_QUIRK_LIGHTNVM, },
2965 { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */
2966 .driver_data = NVME_QUIRK_LIGHTNVM, },
ea48e877
WX		 2967 { PCI_DEVICE(0x1d1d, 0x2601), /* CNEX Granby */
2968 .driver_data = NVME_QUIRK_LIGHTNVM, },
b60503ba 2969 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
c74dc780 2970 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) },
124298bd 2971 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
b60503ba
MW		 2972 { 0, }
2973};
2974MODULE_DEVICE_TABLE(pci, nvme_id_table);
2975
2976static struct pci_driver nvme_driver = {
2977 .name = "nvme",
2978 .id_table = nvme_id_table,
2979 .probe = nvme_probe,
8d85fce7 2980 .remove = nvme_remove,
09ece142 2981 .shutdown = nvme_shutdown,
cd638946
KB		 2982 .driver = {
2983 .pm = &nvme_dev_pm_ops,
2984 },
74d986ab 2985 .sriov_configure = pci_sriov_configure_simple,
b60503ba
MW		 2986 .err_handler = &nvme_err_handler,
2987};
2988
2989static int __init nvme_init(void)
2990{
612b7286 2991 BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2);
9a6327d2 2992 return pci_register_driver(&nvme_driver);
b60503ba
MW		 2993}
2994
2995static void __exit nvme_exit(void)
2996{
2997 pci_unregister_driver(&nvme_driver);
03e0f3a6 2998 flush_workqueue(nvme_wq);
21bd78bc 2999 _nvme_check_size();
b60503ba
MW		 3000}
3001
3002MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3003MODULE_LICENSE("GPL");
c78b4713 3004MODULE_VERSION("1.0");
b60503ba
MW		 3005module_init(nvme_init);
3006module_exit(nvme_exit);
Linux 6.x block layer and io_uring tree(s)