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NVMe: add blk polling support
[linux-2.6-block.git] / drivers / nvme / host / pci.c
CommitLineData
b60503ba
MW		 1/*
2 * NVM Express device driver
6eb0d698 3 * Copyright (c) 2011-2014, Intel Corporation.
b60503ba
MW		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
b60503ba
MW		 13 */
14
8de05535 15#include <linux/bitops.h>
b60503ba 16#include <linux/blkdev.h>
a4aea562 17#include <linux/blk-mq.h>
42f61420 18#include <linux/cpu.h>
fd63e9ce 19#include <linux/delay.h>
b60503ba
MW		 20#include <linux/errno.h>
21#include <linux/fs.h>
22#include <linux/genhd.h>
4cc09e2d 23#include <linux/hdreg.h>
5aff9382 24#include <linux/idr.h>
b60503ba
MW		 25#include <linux/init.h>
26#include <linux/interrupt.h>
27#include <linux/io.h>
28#include <linux/kdev_t.h>
1fa6aead 29#include <linux/kthread.h>
b60503ba 30#include <linux/kernel.h>
a5768aa8 31#include <linux/list_sort.h>
b60503ba
MW		 32#include <linux/mm.h>
33#include <linux/module.h>
34#include <linux/moduleparam.h>
35#include <linux/pci.h>
be7b6275 36#include <linux/poison.h>
c3bfe717 37#include <linux/ptrace.h>
b60503ba
MW		 38#include <linux/sched.h>
39#include <linux/slab.h>
e1e5e564 40#include <linux/t10-pi.h>
b60503ba 41#include <linux/types.h>
1d277a63 42#include <linux/pr.h>
5d0f6131 43#include <scsi/sg.h>
797a796a 44#include <asm-generic/io-64-nonatomic-lo-hi.h>
1d277a63 45#include <asm/unaligned.h>
797a796a 46
9d99a8dd 47#include <uapi/linux/nvme_ioctl.h>
f11bb3e2
CH		 48#include "nvme.h"
49
b3fffdef 50#define NVME_MINORS (1U << MINORBITS)
9d43cf64 51#define NVME_Q_DEPTH 1024
d31af0a3 52#define NVME_AQ_DEPTH 256
b60503ba
MW		 53#define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
54#define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
9d43cf64 55#define ADMIN_TIMEOUT (admin_timeout * HZ)
2484f407 56#define SHUTDOWN_TIMEOUT (shutdown_timeout * HZ)
9d43cf64
KB		 57
58static unsigned char admin_timeout = 60;
59module_param(admin_timeout, byte, 0644);
60MODULE_PARM_DESC(admin_timeout, "timeout in seconds for admin commands");
b60503ba 61
bd67608a
MW		 62unsigned char nvme_io_timeout = 30;
63module_param_named(io_timeout, nvme_io_timeout, byte, 0644);
b355084a 64MODULE_PARM_DESC(io_timeout, "timeout in seconds for I/O");
b60503ba 65
2484f407
DM		 66static unsigned char shutdown_timeout = 5;
67module_param(shutdown_timeout, byte, 0644);
68MODULE_PARM_DESC(shutdown_timeout, "timeout in seconds for controller shutdown");
69
b60503ba
MW		 70static int nvme_major;
71module_param(nvme_major, int, 0);
72
b3fffdef
KB		 73static int nvme_char_major;
74module_param(nvme_char_major, int, 0);
75
58ffacb5
MW		 76static int use_threaded_interrupts;
77module_param(use_threaded_interrupts, int, 0);
78
8ffaadf7
JD		 79static bool use_cmb_sqes = true;
80module_param(use_cmb_sqes, bool, 0644);
81MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
82
1fa6aead
MW		 83static DEFINE_SPINLOCK(dev_list_lock);
84static LIST_HEAD(dev_list);
85static struct task_struct *nvme_thread;
9a6b9458 86static struct workqueue_struct *nvme_workq;
b9afca3e 87static wait_queue_head_t nvme_kthread_wait;
1fa6aead 88
b3fffdef
KB		 89static struct class *nvme_class;
90
90667892 91static int __nvme_reset(struct nvme_dev *dev);
4cc06521 92static int nvme_reset(struct nvme_dev *dev);
a0fa9647 93static void nvme_process_cq(struct nvme_queue *nvmeq);
3cf519b5 94static void nvme_dead_ctrl(struct nvme_dev *dev);
d4b4ff8e 95
4d115420
KB		 96struct async_cmd_info {
97 struct kthread_work work;
98 struct kthread_worker *worker;
a4aea562 99 struct request *req;
4d115420
KB		 100 u32 result;
101 int status;
102 void *ctx;
103};
1fa6aead 104
b60503ba
MW		 105/*
106 * An NVM Express queue. Each device has at least two (one for admin
107 * commands and one for I/O commands).
108 */
109struct nvme_queue {
110 struct device *q_dmadev;
091b6092 111 struct nvme_dev *dev;
3193f07b 112 char irqname[24]; /* nvme4294967295-65535\0 */
b60503ba
MW		 113 spinlock_t q_lock;
114 struct nvme_command *sq_cmds;
8ffaadf7 115 struct nvme_command __iomem *sq_cmds_io;
b60503ba 116 volatile struct nvme_completion *cqes;
42483228 117 struct blk_mq_tags **tags;
b60503ba
MW		 118 dma_addr_t sq_dma_addr;
119 dma_addr_t cq_dma_addr;
b60503ba
MW		 120 u32 __iomem *q_db;
121 u16 q_depth;
6222d172 122 s16 cq_vector;
b60503ba
MW		 123 u16 sq_head;
124 u16 sq_tail;
125 u16 cq_head;
c30341dc 126 u16 qid;
e9539f47
MW		 127 u8 cq_phase;
128 u8 cqe_seen;
4d115420 129 struct async_cmd_info cmdinfo;
b60503ba
MW		 130};
131
132/*
133 * Check we didin't inadvertently grow the command struct
134 */
135static inline void _nvme_check_size(void)
136{
137 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
138 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
139 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
140 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
141 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
f8ebf840 142 BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
c30341dc 143 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
b60503ba
MW		 144 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
145 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
146 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
147 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
6ecec745 148 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
b60503ba
MW		 149}
150
edd10d33 151typedef void (*nvme_completion_fn)(struct nvme_queue *, void *,
c2f5b650
MW		 152 struct nvme_completion *);
153
e85248e5 154struct nvme_cmd_info {
c2f5b650
MW		 155 nvme_completion_fn fn;
156 void *ctx;
c30341dc 157 int aborted;
a4aea562 158 struct nvme_queue *nvmeq;
ac3dd5bd 159 struct nvme_iod iod[0];
e85248e5
MW		 160};
161
ac3dd5bd
JA		 162/*
163 * Max size of iod being embedded in the request payload
164 */
165#define NVME_INT_PAGES 2
166#define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->page_size)
fda631ff 167#define NVME_INT_MASK 0x01
ac3dd5bd
JA		 168
169/*
170 * Will slightly overestimate the number of pages needed. This is OK
171 * as it only leads to a small amount of wasted memory for the lifetime of
172 * the I/O.
173 */
174static int nvme_npages(unsigned size, struct nvme_dev *dev)
175{
176 unsigned nprps = DIV_ROUND_UP(size + dev->page_size, dev->page_size);
177 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
178}
179
180static unsigned int nvme_cmd_size(struct nvme_dev *dev)
181{
182 unsigned int ret = sizeof(struct nvme_cmd_info);
183
184 ret += sizeof(struct nvme_iod);
185 ret += sizeof(__le64 *) * nvme_npages(NVME_INT_BYTES(dev), dev);
186 ret += sizeof(struct scatterlist) * NVME_INT_PAGES;
187
188 return ret;
189}
190
a4aea562
MB		 191static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
192 unsigned int hctx_idx)
e85248e5 193{
a4aea562
MB		 194 struct nvme_dev *dev = data;
195 struct nvme_queue *nvmeq = dev->queues[0];
196
42483228
KB		 197 WARN_ON(hctx_idx != 0);
198 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
199 WARN_ON(nvmeq->tags);
200
a4aea562 201 hctx->driver_data = nvmeq;
42483228 202 nvmeq->tags = &dev->admin_tagset.tags[0];
a4aea562 203 return 0;
e85248e5
MW		 204}
205
4af0e21c
KB		 206static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
207{
208 struct nvme_queue *nvmeq = hctx->driver_data;
209
210 nvmeq->tags = NULL;
211}
212
a4aea562
MB		 213static int nvme_admin_init_request(void *data, struct request *req,
214 unsigned int hctx_idx, unsigned int rq_idx,
215 unsigned int numa_node)
22404274 216{
a4aea562
MB		 217 struct nvme_dev *dev = data;
218 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
219 struct nvme_queue *nvmeq = dev->queues[0];
220
221 BUG_ON(!nvmeq);
222 cmd->nvmeq = nvmeq;
223 return 0;
22404274
KB		 224}
225
a4aea562
MB		 226static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
227 unsigned int hctx_idx)
b60503ba 228{
a4aea562 229 struct nvme_dev *dev = data;
42483228 230 struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
a4aea562 231
42483228
KB		 232 if (!nvmeq->tags)
233 nvmeq->tags = &dev->tagset.tags[hctx_idx];
b60503ba 234
42483228 235 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
a4aea562
MB		 236 hctx->driver_data = nvmeq;
237 return 0;
b60503ba
MW		 238}
239
a4aea562
MB		 240static int nvme_init_request(void *data, struct request *req,
241 unsigned int hctx_idx, unsigned int rq_idx,
242 unsigned int numa_node)
b60503ba 243{
a4aea562
MB		 244 struct nvme_dev *dev = data;
245 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
246 struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
247
248 BUG_ON(!nvmeq);
249 cmd->nvmeq = nvmeq;
250 return 0;
251}
252
253static void nvme_set_info(struct nvme_cmd_info *cmd, void *ctx,
254 nvme_completion_fn handler)
255{
256 cmd->fn = handler;
257 cmd->ctx = ctx;
258 cmd->aborted = 0;
c917dfe5 259 blk_mq_start_request(blk_mq_rq_from_pdu(cmd));
b60503ba
MW		 260}
261
ac3dd5bd
JA		 262static void *iod_get_private(struct nvme_iod *iod)
263{
264 return (void *) (iod->private & ~0x1UL);
265}
266
267/*
268 * If bit 0 is set, the iod is embedded in the request payload.
269 */
270static bool iod_should_kfree(struct nvme_iod *iod)
271{
fda631ff 272 return (iod->private & NVME_INT_MASK) == 0;
ac3dd5bd
JA		 273}
274
c2f5b650
MW		 275/* Special values must be less than 0x1000 */
276#define CMD_CTX_BASE ((void *)POISON_POINTER_DELTA)
d2d87034
MW		 277#define CMD_CTX_CANCELLED (0x30C + CMD_CTX_BASE)
278#define CMD_CTX_COMPLETED (0x310 + CMD_CTX_BASE)
279#define CMD_CTX_INVALID (0x314 + CMD_CTX_BASE)
be7b6275 280
edd10d33 281static void special_completion(struct nvme_queue *nvmeq, void *ctx,
c2f5b650
MW		 282 struct nvme_completion *cqe)
283{
284 if (ctx == CMD_CTX_CANCELLED)
285 return;
c2f5b650 286 if (ctx == CMD_CTX_COMPLETED) {
edd10d33 287 dev_warn(nvmeq->q_dmadev,
c2f5b650
MW		 288 "completed id %d twice on queue %d\n",
289 cqe->command_id, le16_to_cpup(&cqe->sq_id));
290 return;
291 }
292 if (ctx == CMD_CTX_INVALID) {
edd10d33 293 dev_warn(nvmeq->q_dmadev,
c2f5b650
MW		 294 "invalid id %d completed on queue %d\n",
295 cqe->command_id, le16_to_cpup(&cqe->sq_id));
296 return;
297 }
edd10d33 298 dev_warn(nvmeq->q_dmadev, "Unknown special completion %p\n", ctx);
c2f5b650
MW		 299}
300
a4aea562 301static void *cancel_cmd_info(struct nvme_cmd_info *cmd, nvme_completion_fn *fn)
b60503ba 302{
c2f5b650 303 void *ctx;
b60503ba 304
859361a2 305 if (fn)
a4aea562
MB		 306 *fn = cmd->fn;
307 ctx = cmd->ctx;
308 cmd->fn = special_completion;
309 cmd->ctx = CMD_CTX_CANCELLED;
c2f5b650 310 return ctx;
b60503ba
MW		 311}
312
a4aea562
MB		 313static void async_req_completion(struct nvme_queue *nvmeq, void *ctx,
314 struct nvme_completion *cqe)
3c0cf138 315{
a4aea562
MB		 316 u32 result = le32_to_cpup(&cqe->result);
317 u16 status = le16_to_cpup(&cqe->status) >> 1;
318
319 if (status == NVME_SC_SUCCESS || status == NVME_SC_ABORT_REQ)
320 ++nvmeq->dev->event_limit;
a5768aa8
KB		 321 if (status != NVME_SC_SUCCESS)
322 return;
323
324 switch (result & 0xff07) {
325 case NVME_AER_NOTICE_NS_CHANGED:
326 dev_info(nvmeq->q_dmadev, "rescanning\n");
327 schedule_work(&nvmeq->dev->scan_work);
328 default:
329 dev_warn(nvmeq->q_dmadev, "async event result %08x\n", result);
330 }
b60503ba
MW		 331}
332
a4aea562
MB		 333static void abort_completion(struct nvme_queue *nvmeq, void *ctx,
334 struct nvme_completion *cqe)
5a92e700 335{
a4aea562
MB		 336 struct request *req = ctx;
337
338 u16 status = le16_to_cpup(&cqe->status) >> 1;
339 u32 result = le32_to_cpup(&cqe->result);
a51afb54 340
42483228 341 blk_mq_free_request(req);
a51afb54 342
a4aea562
MB		 343 dev_warn(nvmeq->q_dmadev, "Abort status:%x result:%x", status, result);
344 ++nvmeq->dev->abort_limit;
5a92e700
KB		 345}
346
a4aea562
MB		 347static void async_completion(struct nvme_queue *nvmeq, void *ctx,
348 struct nvme_completion *cqe)
b60503ba 349{
a4aea562
MB		 350 struct async_cmd_info *cmdinfo = ctx;
351 cmdinfo->result = le32_to_cpup(&cqe->result);
352 cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
353 queue_kthread_work(cmdinfo->worker, &cmdinfo->work);
42483228 354 blk_mq_free_request(cmdinfo->req);
b60503ba
MW		 355}
356
a4aea562
MB		 357static inline struct nvme_cmd_info *get_cmd_from_tag(struct nvme_queue *nvmeq,
358 unsigned int tag)
b60503ba 359{
42483228 360 struct request *req = blk_mq_tag_to_rq(*nvmeq->tags, tag);
a51afb54 361
a4aea562 362 return blk_mq_rq_to_pdu(req);
4f5099af
KB		 363}
364
a4aea562
MB		 365/*
366 * Called with local interrupts disabled and the q_lock held. May not sleep.
367 */
368static void *nvme_finish_cmd(struct nvme_queue *nvmeq, int tag,
369 nvme_completion_fn *fn)
4f5099af 370{
a4aea562
MB		 371 struct nvme_cmd_info *cmd = get_cmd_from_tag(nvmeq, tag);
372 void *ctx;
373 if (tag >= nvmeq->q_depth) {
374 *fn = special_completion;
375 return CMD_CTX_INVALID;
376 }
377 if (fn)
378 *fn = cmd->fn;
379 ctx = cmd->ctx;
380 cmd->fn = special_completion;
381 cmd->ctx = CMD_CTX_COMPLETED;
382 return ctx;
b60503ba
MW		 383}
384
385/**
714a7a22 386 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
b60503ba
MW		 387 * @nvmeq: The queue to use
388 * @cmd: The command to send
389 *
390 * Safe to use from interrupt context
391 */
e3f879bf
SB		 392static void __nvme_submit_cmd(struct nvme_queue *nvmeq,
393 struct nvme_command *cmd)
b60503ba 394{
a4aea562
MB		 395 u16 tail = nvmeq->sq_tail;
396
8ffaadf7
JD		 397 if (nvmeq->sq_cmds_io)
398 memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd));
399 else
400 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
401
b60503ba
MW		 402 if (++tail == nvmeq->q_depth)
403 tail = 0;
7547881d 404 writel(tail, nvmeq->q_db);
b60503ba 405 nvmeq->sq_tail = tail;
b60503ba
MW		 406}
407
e3f879bf 408static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
a4aea562
MB		 409{
410 unsigned long flags;
a4aea562 411 spin_lock_irqsave(&nvmeq->q_lock, flags);
e3f879bf 412 __nvme_submit_cmd(nvmeq, cmd);
a4aea562 413 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
a4aea562
MB		 414}
415
eca18b23 416static __le64 **iod_list(struct nvme_iod *iod)
e025344c 417{
eca18b23 418 return ((void *)iod) + iod->offset;
e025344c
SMM		 419}
420
ac3dd5bd
JA		 421static inline void iod_init(struct nvme_iod *iod, unsigned nbytes,
422 unsigned nseg, unsigned long private)
eca18b23 423{
ac3dd5bd
JA		 424 iod->private = private;
425 iod->offset = offsetof(struct nvme_iod, sg[nseg]);
426 iod->npages = -1;
427 iod->length = nbytes;
428 iod->nents = 0;
eca18b23 429}
b60503ba 430
eca18b23 431static struct nvme_iod *
ac3dd5bd
JA		 432__nvme_alloc_iod(unsigned nseg, unsigned bytes, struct nvme_dev *dev,
433 unsigned long priv, gfp_t gfp)
b60503ba 434{
eca18b23 435 struct nvme_iod *iod = kmalloc(sizeof(struct nvme_iod) +
ac3dd5bd 436 sizeof(__le64 *) * nvme_npages(bytes, dev) +
eca18b23
MW		 437 sizeof(struct scatterlist) * nseg, gfp);
438
ac3dd5bd
JA		 439 if (iod)
440 iod_init(iod, bytes, nseg, priv);
eca18b23
MW		 441
442 return iod;
b60503ba
MW		 443}
444
ac3dd5bd
JA		 445static struct nvme_iod *nvme_alloc_iod(struct request *rq, struct nvme_dev *dev,
446 gfp_t gfp)
447{
448 unsigned size = !(rq->cmd_flags & REQ_DISCARD) ? blk_rq_bytes(rq) :
449 sizeof(struct nvme_dsm_range);
ac3dd5bd
JA		 450 struct nvme_iod *iod;
451
452 if (rq->nr_phys_segments <= NVME_INT_PAGES &&
453 size <= NVME_INT_BYTES(dev)) {
454 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(rq);
455
456 iod = cmd->iod;
ac3dd5bd 457 iod_init(iod, size, rq->nr_phys_segments,
fda631ff 458 (unsigned long) rq | NVME_INT_MASK);
ac3dd5bd
JA		 459 return iod;
460 }
461
462 return __nvme_alloc_iod(rq->nr_phys_segments, size, dev,
463 (unsigned long) rq, gfp);
464}
465
d29ec824 466static void nvme_free_iod(struct nvme_dev *dev, struct nvme_iod *iod)
b60503ba 467{
1d090624 468 const int last_prp = dev->page_size / 8 - 1;
eca18b23
MW		 469 int i;
470 __le64 **list = iod_list(iod);
471 dma_addr_t prp_dma = iod->first_dma;
472
473 if (iod->npages == 0)
474 dma_pool_free(dev->prp_small_pool, list[0], prp_dma);
475 for (i = 0; i < iod->npages; i++) {
476 __le64 *prp_list = list[i];
477 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
478 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
479 prp_dma = next_prp_dma;
480 }
ac3dd5bd
JA		 481
482 if (iod_should_kfree(iod))
483 kfree(iod);
b60503ba
MW		 484}
485
b4ff9c8d
KB		 486static int nvme_error_status(u16 status)
487{
488 switch (status & 0x7ff) {
489 case NVME_SC_SUCCESS:
490 return 0;
491 case NVME_SC_CAP_EXCEEDED:
492 return -ENOSPC;
493 default:
494 return -EIO;
495 }
496}
497
52b68d7e 498#ifdef CONFIG_BLK_DEV_INTEGRITY
e1e5e564
KB		 499static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
500{
501 if (be32_to_cpu(pi->ref_tag) == v)
502 pi->ref_tag = cpu_to_be32(p);
503}
504
505static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
506{
507 if (be32_to_cpu(pi->ref_tag) == p)
508 pi->ref_tag = cpu_to_be32(v);
509}
510
511/**
512 * nvme_dif_remap - remaps ref tags to bip seed and physical lba
513 *
514 * The virtual start sector is the one that was originally submitted by the
515 * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical
516 * start sector may be different. Remap protection information to match the
517 * physical LBA on writes, and back to the original seed on reads.
518 *
519 * Type 0 and 3 do not have a ref tag, so no remapping required.
520 */
521static void nvme_dif_remap(struct request *req,
522 void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
523{
524 struct nvme_ns *ns = req->rq_disk->private_data;
525 struct bio_integrity_payload *bip;
526 struct t10_pi_tuple *pi;
527 void *p, *pmap;
528 u32 i, nlb, ts, phys, virt;
529
530 if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3)
531 return;
532
533 bip = bio_integrity(req->bio);
534 if (!bip)
535 return;
536
537 pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset;
e1e5e564
KB		 538
539 p = pmap;
540 virt = bip_get_seed(bip);
541 phys = nvme_block_nr(ns, blk_rq_pos(req));
542 nlb = (blk_rq_bytes(req) >> ns->lba_shift);
ac6fc48c 543 ts = ns->disk->queue->integrity.tuple_size;
e1e5e564
KB		 544
545 for (i = 0; i < nlb; i++, virt++, phys++) {
546 pi = (struct t10_pi_tuple *)p;
547 dif_swap(phys, virt, pi);
548 p += ts;
549 }
550 kunmap_atomic(pmap);
551}
552
52b68d7e
KB		 553static void nvme_init_integrity(struct nvme_ns *ns)
554{
555 struct blk_integrity integrity;
556
557 switch (ns->pi_type) {
558 case NVME_NS_DPS_PI_TYPE3:
0f8087ec 559 integrity.profile = &t10_pi_type3_crc;
52b68d7e
KB		 560 break;
561 case NVME_NS_DPS_PI_TYPE1:
562 case NVME_NS_DPS_PI_TYPE2:
0f8087ec 563 integrity.profile = &t10_pi_type1_crc;
52b68d7e
KB		 564 break;
565 default:
4125a09b 566 integrity.profile = NULL;
52b68d7e
KB		 567 break;
568 }
569 integrity.tuple_size = ns->ms;
570 blk_integrity_register(ns->disk, &integrity);
571 blk_queue_max_integrity_segments(ns->queue, 1);
572}
573#else /* CONFIG_BLK_DEV_INTEGRITY */
574static void nvme_dif_remap(struct request *req,
575 void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
576{
577}
578static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
579{
580}
581static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
582{
583}
584static void nvme_init_integrity(struct nvme_ns *ns)
585{
586}
587#endif
588
a4aea562 589static void req_completion(struct nvme_queue *nvmeq, void *ctx,
b60503ba
MW		 590 struct nvme_completion *cqe)
591{
eca18b23 592 struct nvme_iod *iod = ctx;
ac3dd5bd 593 struct request *req = iod_get_private(iod);
a4aea562 594 struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req);
b60503ba 595 u16 status = le16_to_cpup(&cqe->status) >> 1;
0dfc70c3 596 bool requeue = false;
81c04b94 597 int error = 0;
b60503ba 598
edd10d33 599 if (unlikely(status)) {
a4aea562
MB		 600 if (!(status & NVME_SC_DNR || blk_noretry_request(req))
601 && (jiffies - req->start_time) < req->timeout) {
c9d3bf88
KB		 602 unsigned long flags;
603
0dfc70c3 604 requeue = true;
a4aea562 605 blk_mq_requeue_request(req);
c9d3bf88
KB		 606 spin_lock_irqsave(req->q->queue_lock, flags);
607 if (!blk_queue_stopped(req->q))
608 blk_mq_kick_requeue_list(req->q);
609 spin_unlock_irqrestore(req->q->queue_lock, flags);
0dfc70c3 610 goto release_iod;
edd10d33 611 }
f4829a9b 612
d29ec824 613 if (req->cmd_type == REQ_TYPE_DRV_PRIV) {
17188bb4 614 if (cmd_rq->ctx == CMD_CTX_CANCELLED)
81c04b94
CH		 615 error = -EINTR;
616 else
617 error = status;
d29ec824 618 } else {
81c04b94 619 error = nvme_error_status(status);
d29ec824 620 }
f4829a9b
CH		 621 }
622
a0a931d6
KB		 623 if (req->cmd_type == REQ_TYPE_DRV_PRIV) {
624 u32 result = le32_to_cpup(&cqe->result);
625 req->special = (void *)(uintptr_t)result;
626 }
a4aea562
MB		 627
628 if (cmd_rq->aborted)
e75ec752 629 dev_warn(nvmeq->dev->dev,
a4aea562 630 "completing aborted command with status:%04x\n",
81c04b94 631 error);
a4aea562 632
0dfc70c3 633release_iod:
e1e5e564 634 if (iod->nents) {
e75ec752 635 dma_unmap_sg(nvmeq->dev->dev, iod->sg, iod->nents,
a4aea562 636 rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
e1e5e564
KB		 637 if (blk_integrity_rq(req)) {
638 if (!rq_data_dir(req))
639 nvme_dif_remap(req, nvme_dif_complete);
e75ec752 640 dma_unmap_sg(nvmeq->dev->dev, iod->meta_sg, 1,
e1e5e564
KB		 641 rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
642 }
643 }
edd10d33 644 nvme_free_iod(nvmeq->dev, iod);
3291fa57 645
0dfc70c3
KB		 646 if (likely(!requeue))
647 blk_mq_complete_request(req, error);
b60503ba
MW		 648}
649
184d2944 650/* length is in bytes. gfp flags indicates whether we may sleep. */
d29ec824
CH		 651static int nvme_setup_prps(struct nvme_dev *dev, struct nvme_iod *iod,
652 int total_len, gfp_t gfp)
ff22b54f 653{
99802a7a 654 struct dma_pool *pool;
eca18b23
MW		 655 int length = total_len;
656 struct scatterlist *sg = iod->sg;
ff22b54f
MW		 657 int dma_len = sg_dma_len(sg);
658 u64 dma_addr = sg_dma_address(sg);
f137e0f1
MI		 659 u32 page_size = dev->page_size;
660 int offset = dma_addr & (page_size - 1);
e025344c 661 __le64 *prp_list;
eca18b23 662 __le64 **list = iod_list(iod);
e025344c 663 dma_addr_t prp_dma;
eca18b23 664 int nprps, i;
ff22b54f 665
1d090624 666 length -= (page_size - offset);
ff22b54f 667 if (length <= 0)
eca18b23 668 return total_len;
ff22b54f 669
1d090624 670 dma_len -= (page_size - offset);
ff22b54f 671 if (dma_len) {
1d090624 672 dma_addr += (page_size - offset);
ff22b54f
MW		 673 } else {
674 sg = sg_next(sg);
675 dma_addr = sg_dma_address(sg);
676 dma_len = sg_dma_len(sg);
677 }
678
1d090624 679 if (length <= page_size) {
edd10d33 680 iod->first_dma = dma_addr;
eca18b23 681 return total_len;
e025344c
SMM		 682 }
683
1d090624 684 nprps = DIV_ROUND_UP(length, page_size);
99802a7a
MW		 685 if (nprps <= (256 / 8)) {
686 pool = dev->prp_small_pool;
eca18b23 687 iod->npages = 0;
99802a7a
MW		 688 } else {
689 pool = dev->prp_page_pool;
eca18b23 690 iod->npages = 1;
99802a7a
MW		 691 }
692
b77954cb
MW		 693 prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
694 if (!prp_list) {
edd10d33 695 iod->first_dma = dma_addr;
eca18b23 696 iod->npages = -1;
1d090624 697 return (total_len - length) + page_size;
b77954cb 698 }
eca18b23
MW		 699 list[0] = prp_list;
700 iod->first_dma = prp_dma;
e025344c
SMM		 701 i = 0;
702 for (;;) {
1d090624 703 if (i == page_size >> 3) {
e025344c 704 __le64 *old_prp_list = prp_list;
b77954cb 705 prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
eca18b23
MW		 706 if (!prp_list)
707 return total_len - length;
708 list[iod->npages++] = prp_list;
7523d834
MW		 709 prp_list[0] = old_prp_list[i - 1];
710 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
711 i = 1;
e025344c
SMM		 712 }
713 prp_list[i++] = cpu_to_le64(dma_addr);
1d090624
KB		 714 dma_len -= page_size;
715 dma_addr += page_size;
716 length -= page_size;
e025344c
SMM		 717 if (length <= 0)
718 break;
719 if (dma_len > 0)
720 continue;
721 BUG_ON(dma_len < 0);
722 sg = sg_next(sg);
723 dma_addr = sg_dma_address(sg);
724 dma_len = sg_dma_len(sg);
ff22b54f
MW		 725 }
726
eca18b23 727 return total_len;
ff22b54f
MW		 728}
729
d29ec824
CH		 730static void nvme_submit_priv(struct nvme_queue *nvmeq, struct request *req,
731 struct nvme_iod *iod)
732{
498c4394 733 struct nvme_command cmnd;
d29ec824 734
498c4394
JD		 735 memcpy(&cmnd, req->cmd, sizeof(cmnd));
736 cmnd.rw.command_id = req->tag;
d29ec824 737 if (req->nr_phys_segments) {
498c4394
JD		 738 cmnd.rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
739 cmnd.rw.prp2 = cpu_to_le64(iod->first_dma);
d29ec824
CH		 740 }
741
498c4394 742 __nvme_submit_cmd(nvmeq, &cmnd);
d29ec824
CH		 743}
744
a4aea562
MB		 745/*
746 * We reuse the small pool to allocate the 16-byte range here as it is not
747 * worth having a special pool for these or additional cases to handle freeing
748 * the iod.
749 */
750static void nvme_submit_discard(struct nvme_queue *nvmeq, struct nvme_ns *ns,
751 struct request *req, struct nvme_iod *iod)
0e5e4f0e 752{
edd10d33
KB		 753 struct nvme_dsm_range *range =
754 (struct nvme_dsm_range *)iod_list(iod)[0];
498c4394 755 struct nvme_command cmnd;
0e5e4f0e 756
0e5e4f0e 757 range->cattr = cpu_to_le32(0);
a4aea562
MB		 758 range->nlb = cpu_to_le32(blk_rq_bytes(req) >> ns->lba_shift);
759 range->slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
0e5e4f0e 760
498c4394
JD		 761 memset(&cmnd, 0, sizeof(cmnd));
762 cmnd.dsm.opcode = nvme_cmd_dsm;
763 cmnd.dsm.command_id = req->tag;
764 cmnd.dsm.nsid = cpu_to_le32(ns->ns_id);
765 cmnd.dsm.prp1 = cpu_to_le64(iod->first_dma);
766 cmnd.dsm.nr = 0;
767 cmnd.dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD);
0e5e4f0e 768
498c4394 769 __nvme_submit_cmd(nvmeq, &cmnd);
0e5e4f0e
KB		 770}
771
a4aea562 772static void nvme_submit_flush(struct nvme_queue *nvmeq, struct nvme_ns *ns,
00df5cb4
MW		 773 int cmdid)
774{
498c4394 775 struct nvme_command cmnd;
00df5cb4 776
498c4394
JD		 777 memset(&cmnd, 0, sizeof(cmnd));
778 cmnd.common.opcode = nvme_cmd_flush;
779 cmnd.common.command_id = cmdid;
780 cmnd.common.nsid = cpu_to_le32(ns->ns_id);
00df5cb4 781
498c4394 782 __nvme_submit_cmd(nvmeq, &cmnd);
00df5cb4
MW		 783}
784
a4aea562
MB		 785static int nvme_submit_iod(struct nvme_queue *nvmeq, struct nvme_iod *iod,
786 struct nvme_ns *ns)
b60503ba 787{
ac3dd5bd 788 struct request *req = iod_get_private(iod);
498c4394 789 struct nvme_command cmnd;
a4aea562
MB		 790 u16 control = 0;
791 u32 dsmgmt = 0;
00df5cb4 792
a4aea562 793 if (req->cmd_flags & REQ_FUA)
b60503ba 794 control |= NVME_RW_FUA;
a4aea562 795 if (req->cmd_flags & (REQ_FAILFAST_DEV | REQ_RAHEAD))
b60503ba
MW		 796 control |= NVME_RW_LR;
797
a4aea562 798 if (req->cmd_flags & REQ_RAHEAD)
b60503ba
MW		 799 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
800
498c4394
JD		 801 memset(&cmnd, 0, sizeof(cmnd));
802 cmnd.rw.opcode = (rq_data_dir(req) ? nvme_cmd_write : nvme_cmd_read);
803 cmnd.rw.command_id = req->tag;
804 cmnd.rw.nsid = cpu_to_le32(ns->ns_id);
805 cmnd.rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
806 cmnd.rw.prp2 = cpu_to_le64(iod->first_dma);
807 cmnd.rw.slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
808 cmnd.rw.length = cpu_to_le16((blk_rq_bytes(req) >> ns->lba_shift) - 1);
b60503ba 809
e19b127f 810 if (ns->ms) {
e1e5e564
KB		 811 switch (ns->pi_type) {
812 case NVME_NS_DPS_PI_TYPE3:
813 control |= NVME_RW_PRINFO_PRCHK_GUARD;
814 break;
815 case NVME_NS_DPS_PI_TYPE1:
816 case NVME_NS_DPS_PI_TYPE2:
817 control |= NVME_RW_PRINFO_PRCHK_GUARD |
818 NVME_RW_PRINFO_PRCHK_REF;
498c4394 819 cmnd.rw.reftag = cpu_to_le32(
e1e5e564
KB		 820 nvme_block_nr(ns, blk_rq_pos(req)));
821 break;
822 }
e19b127f
AP		 823 if (blk_integrity_rq(req))
824 cmnd.rw.metadata =
825 cpu_to_le64(sg_dma_address(iod->meta_sg));
826 else
827 control |= NVME_RW_PRINFO_PRACT;
828 }
e1e5e564 829
498c4394
JD		 830 cmnd.rw.control = cpu_to_le16(control);
831 cmnd.rw.dsmgmt = cpu_to_le32(dsmgmt);
b60503ba 832
498c4394 833 __nvme_submit_cmd(nvmeq, &cmnd);
b60503ba 834
1974b1ae 835 return 0;
edd10d33
KB		 836}
837
d29ec824
CH		 838/*
839 * NOTE: ns is NULL when called on the admin queue.
840 */
a4aea562
MB		 841static int nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
842 const struct blk_mq_queue_data *bd)
edd10d33 843{
a4aea562
MB		 844 struct nvme_ns *ns = hctx->queue->queuedata;
845 struct nvme_queue *nvmeq = hctx->driver_data;
d29ec824 846 struct nvme_dev *dev = nvmeq->dev;
a4aea562
MB		 847 struct request *req = bd->rq;
848 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
edd10d33 849 struct nvme_iod *iod;
a4aea562 850 enum dma_data_direction dma_dir;
edd10d33 851
e1e5e564
KB		 852 /*
853 * If formated with metadata, require the block layer provide a buffer
854 * unless this namespace is formated such that the metadata can be
855 * stripped/generated by the controller with PRACT=1.
856 */
d29ec824 857 if (ns && ns->ms && !blk_integrity_rq(req)) {
71feb364
KB		 858 if (!(ns->pi_type && ns->ms == 8) &&
859 req->cmd_type != REQ_TYPE_DRV_PRIV) {
f4829a9b 860 blk_mq_complete_request(req, -EFAULT);
e1e5e564
KB		 861 return BLK_MQ_RQ_QUEUE_OK;
862 }
863 }
864
d29ec824 865 iod = nvme_alloc_iod(req, dev, GFP_ATOMIC);
edd10d33 866 if (!iod)
fe54303e 867 return BLK_MQ_RQ_QUEUE_BUSY;
a4aea562 868
a4aea562 869 if (req->cmd_flags & REQ_DISCARD) {
edd10d33
KB		 870 void *range;
871 /*
872 * We reuse the small pool to allocate the 16-byte range here
873 * as it is not worth having a special pool for these or
874 * additional cases to handle freeing the iod.
875 */
d29ec824 876 range = dma_pool_alloc(dev->prp_small_pool, GFP_ATOMIC,
edd10d33 877 &iod->first_dma);
a4aea562 878 if (!range)
fe54303e 879 goto retry_cmd;
edd10d33
KB		 880 iod_list(iod)[0] = (__le64 *)range;
881 iod->npages = 0;
ac3dd5bd 882 } else if (req->nr_phys_segments) {
a4aea562
MB		 883 dma_dir = rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
884
ac3dd5bd 885 sg_init_table(iod->sg, req->nr_phys_segments);
a4aea562 886 iod->nents = blk_rq_map_sg(req->q, req, iod->sg);
fe54303e
JA		 887 if (!iod->nents)
888 goto error_cmd;
a4aea562
MB		 889
890 if (!dma_map_sg(nvmeq->q_dmadev, iod->sg, iod->nents, dma_dir))
fe54303e 891 goto retry_cmd;
a4aea562 892
fe54303e 893 if (blk_rq_bytes(req) !=
d29ec824
CH		 894 nvme_setup_prps(dev, iod, blk_rq_bytes(req), GFP_ATOMIC)) {
895 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
fe54303e
JA		 896 goto retry_cmd;
897 }
e1e5e564
KB		 898 if (blk_integrity_rq(req)) {
899 if (blk_rq_count_integrity_sg(req->q, req->bio) != 1)
900 goto error_cmd;
901
902 sg_init_table(iod->meta_sg, 1);
903 if (blk_rq_map_integrity_sg(
904 req->q, req->bio, iod->meta_sg) != 1)
905 goto error_cmd;
906
907 if (rq_data_dir(req))
908 nvme_dif_remap(req, nvme_dif_prep);
909
910 if (!dma_map_sg(nvmeq->q_dmadev, iod->meta_sg, 1, dma_dir))
911 goto error_cmd;
912 }
edd10d33 913 }
1974b1ae 914
9af8785a 915 nvme_set_info(cmd, iod, req_completion);
a4aea562 916 spin_lock_irq(&nvmeq->q_lock);
d29ec824
CH		 917 if (req->cmd_type == REQ_TYPE_DRV_PRIV)
918 nvme_submit_priv(nvmeq, req, iod);
919 else if (req->cmd_flags & REQ_DISCARD)
a4aea562
MB		 920 nvme_submit_discard(nvmeq, ns, req, iod);
921 else if (req->cmd_flags & REQ_FLUSH)
922 nvme_submit_flush(nvmeq, ns, req->tag);
923 else
924 nvme_submit_iod(nvmeq, iod, ns);
925
926 nvme_process_cq(nvmeq);
927 spin_unlock_irq(&nvmeq->q_lock);
928 return BLK_MQ_RQ_QUEUE_OK;
929
fe54303e 930 error_cmd:
d29ec824 931 nvme_free_iod(dev, iod);
fe54303e
JA		 932 return BLK_MQ_RQ_QUEUE_ERROR;
933 retry_cmd:
d29ec824 934 nvme_free_iod(dev, iod);
fe54303e 935 return BLK_MQ_RQ_QUEUE_BUSY;
b60503ba
MW		 936}
937
a0fa9647 938static void __nvme_process_cq(struct nvme_queue *nvmeq, unsigned int *tag)
b60503ba 939{
82123460 940 u16 head, phase;
b60503ba 941
b60503ba 942 head = nvmeq->cq_head;
82123460 943 phase = nvmeq->cq_phase;
b60503ba
MW		 944
945 for (;;) {
c2f5b650
MW		 946 void *ctx;
947 nvme_completion_fn fn;
b60503ba 948 struct nvme_completion cqe = nvmeq->cqes[head];
82123460 949 if ((le16_to_cpu(cqe.status) & 1) != phase)
b60503ba
MW		 950 break;
951 nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
952 if (++head == nvmeq->q_depth) {
953 head = 0;
82123460 954 phase = !phase;
b60503ba 955 }
a0fa9647
JA		 956 if (tag && *tag == cqe.command_id)
957 *tag = -1;
a4aea562 958 ctx = nvme_finish_cmd(nvmeq, cqe.command_id, &fn);
edd10d33 959 fn(nvmeq, ctx, &cqe);
b60503ba
MW		 960 }
961
962 /* If the controller ignores the cq head doorbell and continuously
963 * writes to the queue, it is theoretically possible to wrap around
964 * the queue twice and mistakenly return IRQ_NONE. Linux only
965 * requires that 0.1% of your interrupts are handled, so this isn't
966 * a big problem.
967 */
82123460 968 if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
a0fa9647 969 return;
b60503ba 970
b80d5ccc 971 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
b60503ba 972 nvmeq->cq_head = head;
82123460 973 nvmeq->cq_phase = phase;
b60503ba 974
e9539f47 975 nvmeq->cqe_seen = 1;
a0fa9647
JA		 976}
977
978static void nvme_process_cq(struct nvme_queue *nvmeq)
979{
980 __nvme_process_cq(nvmeq, NULL);
b60503ba
MW		 981}
982
983static irqreturn_t nvme_irq(int irq, void *data)
58ffacb5
MW		 984{
985 irqreturn_t result;
986 struct nvme_queue *nvmeq = data;
987 spin_lock(&nvmeq->q_lock);
e9539f47
MW		 988 nvme_process_cq(nvmeq);
989 result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE;
990 nvmeq->cqe_seen = 0;
58ffacb5
MW		 991 spin_unlock(&nvmeq->q_lock);
992 return result;
993}
994
995static irqreturn_t nvme_irq_check(int irq, void *data)
996{
997 struct nvme_queue *nvmeq = data;
998 struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head];
999 if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase)
1000 return IRQ_NONE;
1001 return IRQ_WAKE_THREAD;
1002}
1003
a0fa9647
JA		 1004static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag)
1005{
1006 struct nvme_queue *nvmeq = hctx->driver_data;
1007
1008 if ((le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) ==
1009 nvmeq->cq_phase) {
1010 spin_lock_irq(&nvmeq->q_lock);
1011 __nvme_process_cq(nvmeq, &tag);
1012 spin_unlock_irq(&nvmeq->q_lock);
1013
1014 if (tag == -1)
1015 return 1;
1016 }
1017
1018 return 0;
1019}
1020
b60503ba
MW		 1021/*
1022 * Returns 0 on success. If the result is negative, it's a Linux error code;
1023 * if the result is positive, it's an NVM Express status code
1024 */
d29ec824
CH		 1025int __nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
1026 void *buffer, void __user *ubuffer, unsigned bufflen,
1027 u32 *result, unsigned timeout)
b60503ba 1028{
d29ec824
CH		 1029 bool write = cmd->common.opcode & 1;
1030 struct bio *bio = NULL;
f705f837 1031 struct request *req;
d29ec824 1032 int ret;
b60503ba 1033
d29ec824 1034 req = blk_mq_alloc_request(q, write, GFP_KERNEL, false);
f705f837
CH		 1035 if (IS_ERR(req))
1036 return PTR_ERR(req);
b60503ba 1037
d29ec824 1038 req->cmd_type = REQ_TYPE_DRV_PRIV;
e112af0d 1039 req->cmd_flags |= REQ_FAILFAST_DRIVER;
d29ec824
CH		 1040 req->__data_len = 0;
1041 req->__sector = (sector_t) -1;
1042 req->bio = req->biotail = NULL;
b60503ba 1043
f4ff414a 1044 req->timeout = timeout ? timeout : ADMIN_TIMEOUT;
a4aea562 1045
d29ec824
CH		 1046 req->cmd = (unsigned char *)cmd;
1047 req->cmd_len = sizeof(struct nvme_command);
a0a931d6 1048 req->special = (void *)0;
b60503ba 1049
d29ec824
CH		 1050 if (buffer && bufflen) {
1051 ret = blk_rq_map_kern(q, req, buffer, bufflen, __GFP_WAIT);
1052 if (ret)
1053 goto out;
1054 } else if (ubuffer && bufflen) {
1055 ret = blk_rq_map_user(q, req, NULL, ubuffer, bufflen, __GFP_WAIT);
1056 if (ret)
1057 goto out;
1058 bio = req->bio;
1059 }
3c0cf138 1060
d29ec824
CH		 1061 blk_execute_rq(req->q, NULL, req, 0);
1062 if (bio)
1063 blk_rq_unmap_user(bio);
b60503ba 1064 if (result)
a0a931d6 1065 *result = (u32)(uintptr_t)req->special;
d29ec824
CH		 1066 ret = req->errors;
1067 out:
f705f837 1068 blk_mq_free_request(req);
d29ec824 1069 return ret;
f705f837
CH		 1070}
1071
d29ec824
CH		 1072int nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
1073 void *buffer, unsigned bufflen)
f705f837 1074{
d29ec824 1075 return __nvme_submit_sync_cmd(q, cmd, buffer, NULL, bufflen, NULL, 0);
b60503ba
MW		 1076}
1077
a4aea562
MB		 1078static int nvme_submit_async_admin_req(struct nvme_dev *dev)
1079{
1080 struct nvme_queue *nvmeq = dev->queues[0];
1081 struct nvme_command c;
1082 struct nvme_cmd_info *cmd_info;
1083 struct request *req;
1084
1efccc9d 1085 req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_ATOMIC, true);
9f173b33
DC		 1086 if (IS_ERR(req))
1087 return PTR_ERR(req);
a4aea562 1088
c917dfe5 1089 req->cmd_flags |= REQ_NO_TIMEOUT;
a4aea562 1090 cmd_info = blk_mq_rq_to_pdu(req);
1efccc9d 1091 nvme_set_info(cmd_info, NULL, async_req_completion);
a4aea562
MB		 1092
1093 memset(&c, 0, sizeof(c));
1094 c.common.opcode = nvme_admin_async_event;
1095 c.common.command_id = req->tag;
1096
42483228 1097 blk_mq_free_request(req);
e3f879bf
SB		 1098 __nvme_submit_cmd(nvmeq, &c);
1099 return 0;
a4aea562
MB		 1100}
1101
1102static int nvme_submit_admin_async_cmd(struct nvme_dev *dev,
4d115420
KB		 1103 struct nvme_command *cmd,
1104 struct async_cmd_info *cmdinfo, unsigned timeout)
1105{
a4aea562
MB		 1106 struct nvme_queue *nvmeq = dev->queues[0];
1107 struct request *req;
1108 struct nvme_cmd_info *cmd_rq;
4d115420 1109
a4aea562 1110 req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_KERNEL, false);
9f173b33
DC		 1111 if (IS_ERR(req))
1112 return PTR_ERR(req);
a4aea562
MB		 1113
1114 req->timeout = timeout;
1115 cmd_rq = blk_mq_rq_to_pdu(req);
1116 cmdinfo->req = req;
1117 nvme_set_info(cmd_rq, cmdinfo, async_completion);
4d115420 1118 cmdinfo->status = -EINTR;
a4aea562
MB		 1119
1120 cmd->common.command_id = req->tag;
1121
e3f879bf
SB		 1122 nvme_submit_cmd(nvmeq, cmd);
1123 return 0;
4d115420
KB		 1124}
1125
b60503ba
MW		 1126static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
1127{
b60503ba
MW		 1128 struct nvme_command c;
1129
1130 memset(&c, 0, sizeof(c));
1131 c.delete_queue.opcode = opcode;
1132 c.delete_queue.qid = cpu_to_le16(id);
1133
d29ec824 1134 return nvme_submit_sync_cmd(dev->admin_q, &c, NULL, 0);
b60503ba
MW		 1135}
1136
1137static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
1138 struct nvme_queue *nvmeq)
1139{
b60503ba
MW		 1140 struct nvme_command c;
1141 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
1142
d29ec824
CH		 1143 /*
1144 * Note: we (ab)use the fact the the prp fields survive if no data
1145 * is attached to the request.
1146 */
b60503ba
MW		 1147 memset(&c, 0, sizeof(c));
1148 c.create_cq.opcode = nvme_admin_create_cq;
1149 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1150 c.create_cq.cqid = cpu_to_le16(qid);
1151 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1152 c.create_cq.cq_flags = cpu_to_le16(flags);
1153 c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
1154
d29ec824 1155 return nvme_submit_sync_cmd(dev->admin_q, &c, NULL, 0);
b60503ba
MW		 1156}
1157
1158static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1159 struct nvme_queue *nvmeq)
1160{
b60503ba
MW		 1161 struct nvme_command c;
1162 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
1163
d29ec824
CH		 1164 /*
1165 * Note: we (ab)use the fact the the prp fields survive if no data
1166 * is attached to the request.
1167 */
b60503ba
MW		 1168 memset(&c, 0, sizeof(c));
1169 c.create_sq.opcode = nvme_admin_create_sq;
1170 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1171 c.create_sq.sqid = cpu_to_le16(qid);
1172 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1173 c.create_sq.sq_flags = cpu_to_le16(flags);
1174 c.create_sq.cqid = cpu_to_le16(qid);
1175
d29ec824 1176 return nvme_submit_sync_cmd(dev->admin_q, &c, NULL, 0);
b60503ba
MW		 1177}
1178
1179static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1180{
1181 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1182}
1183
1184static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1185{
1186 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1187}
1188
d29ec824 1189int nvme_identify_ctrl(struct nvme_dev *dev, struct nvme_id_ctrl **id)
bc5fc7e4 1190{
e44ac588 1191 struct nvme_command c = { };
d29ec824 1192 int error;
bc5fc7e4 1193
e44ac588
AM		 1194 /* gcc-4.4.4 (at least) has issues with initializers and anon unions */
1195 c.identify.opcode = nvme_admin_identify;
1196 c.identify.cns = cpu_to_le32(1);
1197
d29ec824
CH		 1198 *id = kmalloc(sizeof(struct nvme_id_ctrl), GFP_KERNEL);
1199 if (!*id)
1200 return -ENOMEM;
bc5fc7e4 1201
d29ec824
CH		 1202 error = nvme_submit_sync_cmd(dev->admin_q, &c, *id,
1203 sizeof(struct nvme_id_ctrl));
1204 if (error)
1205 kfree(*id);
1206 return error;
1207}
1208
1209int nvme_identify_ns(struct nvme_dev *dev, unsigned nsid,
1210 struct nvme_id_ns **id)
1211{
e44ac588 1212 struct nvme_command c = { };
d29ec824 1213 int error;
bc5fc7e4 1214
e44ac588
AM		 1215 /* gcc-4.4.4 (at least) has issues with initializers and anon unions */
1216 c.identify.opcode = nvme_admin_identify,
1217 c.identify.nsid = cpu_to_le32(nsid),
1218
d29ec824
CH		 1219 *id = kmalloc(sizeof(struct nvme_id_ns), GFP_KERNEL);
1220 if (!*id)
1221 return -ENOMEM;
1222
1223 error = nvme_submit_sync_cmd(dev->admin_q, &c, *id,
1224 sizeof(struct nvme_id_ns));
1225 if (error)
1226 kfree(*id);
1227 return error;
bc5fc7e4
MW		 1228}
1229
5d0f6131 1230int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid,
08df1e05 1231 dma_addr_t dma_addr, u32 *result)
bc5fc7e4
MW		 1232{
1233 struct nvme_command c;
1234
1235 memset(&c, 0, sizeof(c));
1236 c.features.opcode = nvme_admin_get_features;
a42cecce 1237 c.features.nsid = cpu_to_le32(nsid);
bc5fc7e4
MW		 1238 c.features.prp1 = cpu_to_le64(dma_addr);
1239 c.features.fid = cpu_to_le32(fid);
bc5fc7e4 1240
d29ec824
CH		 1241 return __nvme_submit_sync_cmd(dev->admin_q, &c, NULL, NULL, 0,
1242 result, 0);
df348139
MW		 1243}
1244
5d0f6131
VV		 1245int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11,
1246 dma_addr_t dma_addr, u32 *result)
df348139
MW		 1247{
1248 struct nvme_command c;
1249
1250 memset(&c, 0, sizeof(c));
1251 c.features.opcode = nvme_admin_set_features;
1252 c.features.prp1 = cpu_to_le64(dma_addr);
1253 c.features.fid = cpu_to_le32(fid);
1254 c.features.dword11 = cpu_to_le32(dword11);
1255
d29ec824
CH		 1256 return __nvme_submit_sync_cmd(dev->admin_q, &c, NULL, NULL, 0,
1257 result, 0);
1258}
1259
1260int nvme_get_log_page(struct nvme_dev *dev, struct nvme_smart_log **log)
1261{
e44ac588
AM		 1262 struct nvme_command c = { };
1263 int error;
1264
1265 c.common.opcode = nvme_admin_get_log_page,
1266 c.common.nsid = cpu_to_le32(0xFFFFFFFF),
1267 c.common.cdw10[0] = cpu_to_le32(
d29ec824
CH		 1268 (((sizeof(struct nvme_smart_log) / 4) - 1) << 16) |
1269 NVME_LOG_SMART),
d29ec824
CH		 1270
1271 *log = kmalloc(sizeof(struct nvme_smart_log), GFP_KERNEL);
1272 if (!*log)
1273 return -ENOMEM;
1274
1275 error = nvme_submit_sync_cmd(dev->admin_q, &c, *log,
1276 sizeof(struct nvme_smart_log));
1277 if (error)
1278 kfree(*log);
1279 return error;
bc5fc7e4
MW		 1280}
1281
c30341dc 1282/**
a4aea562 1283 * nvme_abort_req - Attempt aborting a request
c30341dc
KB		 1284 *
1285 * Schedule controller reset if the command was already aborted once before and
1286 * still hasn't been returned to the driver, or if this is the admin queue.
1287 */
a4aea562 1288static void nvme_abort_req(struct request *req)
c30341dc 1289{
a4aea562
MB		 1290 struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req);
1291 struct nvme_queue *nvmeq = cmd_rq->nvmeq;
c30341dc 1292 struct nvme_dev *dev = nvmeq->dev;
a4aea562
MB		 1293 struct request *abort_req;
1294 struct nvme_cmd_info *abort_cmd;
1295 struct nvme_command cmd;
c30341dc 1296
a4aea562 1297 if (!nvmeq->qid || cmd_rq->aborted) {
90667892
CH		 1298 spin_lock(&dev_list_lock);
1299 if (!__nvme_reset(dev)) {
1300 dev_warn(dev->dev,
1301 "I/O %d QID %d timeout, reset controller\n",
1302 req->tag, nvmeq->qid);
1303 }
1304 spin_unlock(&dev_list_lock);
c30341dc
KB		 1305 return;
1306 }
1307
1308 if (!dev->abort_limit)
1309 return;
1310
a4aea562
MB		 1311 abort_req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_ATOMIC,
1312 false);
9f173b33 1313 if (IS_ERR(abort_req))
c30341dc
KB		 1314 return;
1315
a4aea562
MB		 1316 abort_cmd = blk_mq_rq_to_pdu(abort_req);
1317 nvme_set_info(abort_cmd, abort_req, abort_completion);
1318
c30341dc
KB		 1319 memset(&cmd, 0, sizeof(cmd));
1320 cmd.abort.opcode = nvme_admin_abort_cmd;
a4aea562 1321 cmd.abort.cid = req->tag;
c30341dc 1322 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
a4aea562 1323 cmd.abort.command_id = abort_req->tag;
c30341dc
KB		 1324
1325 --dev->abort_limit;
a4aea562 1326 cmd_rq->aborted = 1;
c30341dc 1327
a4aea562 1328 dev_warn(nvmeq->q_dmadev, "Aborting I/O %d QID %d\n", req->tag,
c30341dc 1329 nvmeq->qid);
e3f879bf 1330 nvme_submit_cmd(dev->queues[0], &cmd);
c30341dc
KB		 1331}
1332
42483228 1333static void nvme_cancel_queue_ios(struct request *req, void *data, bool reserved)
a09115b2 1334{
a4aea562
MB		 1335 struct nvme_queue *nvmeq = data;
1336 void *ctx;
1337 nvme_completion_fn fn;
1338 struct nvme_cmd_info *cmd;
cef6a948
KB		 1339 struct nvme_completion cqe;
1340
1341 if (!blk_mq_request_started(req))
1342 return;
a09115b2 1343
a4aea562 1344 cmd = blk_mq_rq_to_pdu(req);
a09115b2 1345
a4aea562
MB		 1346 if (cmd->ctx == CMD_CTX_CANCELLED)
1347 return;
1348
cef6a948
KB		 1349 if (blk_queue_dying(req->q))
1350 cqe.status = cpu_to_le16((NVME_SC_ABORT_REQ | NVME_SC_DNR) << 1);
1351 else
1352 cqe.status = cpu_to_le16(NVME_SC_ABORT_REQ << 1);
1353
1354
a4aea562
MB		 1355 dev_warn(nvmeq->q_dmadev, "Cancelling I/O %d QID %d\n",
1356 req->tag, nvmeq->qid);
1357 ctx = cancel_cmd_info(cmd, &fn);
1358 fn(nvmeq, ctx, &cqe);
a09115b2
MW		 1359}
1360
a4aea562 1361static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
9e866774 1362{
a4aea562
MB		 1363 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
1364 struct nvme_queue *nvmeq = cmd->nvmeq;
1365
1366 dev_warn(nvmeq->q_dmadev, "Timeout I/O %d QID %d\n", req->tag,
1367 nvmeq->qid);
7a509a6b 1368 spin_lock_irq(&nvmeq->q_lock);
07836e65 1369 nvme_abort_req(req);
7a509a6b 1370 spin_unlock_irq(&nvmeq->q_lock);
a4aea562 1371
07836e65
KB		 1372 /*
1373 * The aborted req will be completed on receiving the abort req.
1374 * We enable the timer again. If hit twice, it'll cause a device reset,
1375 * as the device then is in a faulty state.
1376 */
1377 return BLK_EH_RESET_TIMER;
a4aea562 1378}
22404274 1379
a4aea562
MB		 1380static void nvme_free_queue(struct nvme_queue *nvmeq)
1381{
9e866774
MW		 1382 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1383 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
8ffaadf7
JD		 1384 if (nvmeq->sq_cmds)
1385 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
9e866774
MW		 1386 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1387 kfree(nvmeq);
1388}
1389
a1a5ef99 1390static void nvme_free_queues(struct nvme_dev *dev, int lowest)
22404274
KB		 1391{
1392 int i;
1393
a1a5ef99 1394 for (i = dev->queue_count - 1; i >= lowest; i--) {
a4aea562 1395 struct nvme_queue *nvmeq = dev->queues[i];
22404274 1396 dev->queue_count--;
a4aea562 1397 dev->queues[i] = NULL;
f435c282 1398 nvme_free_queue(nvmeq);
121c7ad4 1399 }
22404274
KB		 1400}
1401
4d115420
KB		 1402/**
1403 * nvme_suspend_queue - put queue into suspended state
1404 * @nvmeq - queue to suspend
4d115420
KB		 1405 */
1406static int nvme_suspend_queue(struct nvme_queue *nvmeq)
b60503ba 1407{
2b25d981 1408 int vector;
b60503ba 1409
a09115b2 1410 spin_lock_irq(&nvmeq->q_lock);
2b25d981
KB		 1411 if (nvmeq->cq_vector == -1) {
1412 spin_unlock_irq(&nvmeq->q_lock);
1413 return 1;
1414 }
1415 vector = nvmeq->dev->entry[nvmeq->cq_vector].vector;
42f61420 1416 nvmeq->dev->online_queues--;
2b25d981 1417 nvmeq->cq_vector = -1;
a09115b2
MW		 1418 spin_unlock_irq(&nvmeq->q_lock);
1419
6df3dbc8
KB		 1420 if (!nvmeq->qid && nvmeq->dev->admin_q)
1421 blk_mq_freeze_queue_start(nvmeq->dev->admin_q);
1422
aba2080f
MW		 1423 irq_set_affinity_hint(vector, NULL);
1424 free_irq(vector, nvmeq);
b60503ba 1425
4d115420
KB		 1426 return 0;
1427}
b60503ba 1428
4d115420
KB		 1429static void nvme_clear_queue(struct nvme_queue *nvmeq)
1430{
22404274 1431 spin_lock_irq(&nvmeq->q_lock);
42483228
KB		 1432 if (nvmeq->tags && *nvmeq->tags)
1433 blk_mq_all_tag_busy_iter(*nvmeq->tags, nvme_cancel_queue_ios, nvmeq);
22404274 1434 spin_unlock_irq(&nvmeq->q_lock);
b60503ba
MW		 1435}
1436
4d115420
KB		 1437static void nvme_disable_queue(struct nvme_dev *dev, int qid)
1438{
a4aea562 1439 struct nvme_queue *nvmeq = dev->queues[qid];
4d115420
KB		 1440
1441 if (!nvmeq)
1442 return;
1443 if (nvme_suspend_queue(nvmeq))
1444 return;
1445
0e53d180
KB		 1446 /* Don't tell the adapter to delete the admin queue.
1447 * Don't tell a removed adapter to delete IO queues. */
1448 if (qid && readl(&dev->bar->csts) != -1) {
b60503ba
MW		 1449 adapter_delete_sq(dev, qid);
1450 adapter_delete_cq(dev, qid);
1451 }
07836e65
KB		 1452
1453 spin_lock_irq(&nvmeq->q_lock);
1454 nvme_process_cq(nvmeq);
1455 spin_unlock_irq(&nvmeq->q_lock);
b60503ba
MW		 1456}
1457
8ffaadf7
JD		 1458static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1459 int entry_size)
1460{
1461 int q_depth = dev->q_depth;
1462 unsigned q_size_aligned = roundup(q_depth * entry_size, dev->page_size);
1463
1464 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
c45f5c99
JD		 1465 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
1466 mem_per_q = round_down(mem_per_q, dev->page_size);
1467 q_depth = div_u64(mem_per_q, entry_size);
8ffaadf7
JD		 1468
1469 /*
1470 * Ensure the reduced q_depth is above some threshold where it
1471 * would be better to map queues in system memory with the
1472 * original depth
1473 */
1474 if (q_depth < 64)
1475 return -ENOMEM;
1476 }
1477
1478 return q_depth;
1479}
1480
1481static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1482 int qid, int depth)
1483{
1484 if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz)) {
1485 unsigned offset = (qid - 1) *
1486 roundup(SQ_SIZE(depth), dev->page_size);
1487 nvmeq->sq_dma_addr = dev->cmb_dma_addr + offset;
1488 nvmeq->sq_cmds_io = dev->cmb + offset;
1489 } else {
1490 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
1491 &nvmeq->sq_dma_addr, GFP_KERNEL);
1492 if (!nvmeq->sq_cmds)
1493 return -ENOMEM;
1494 }
1495
1496 return 0;
1497}
1498
b60503ba 1499static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
2b25d981 1500 int depth)
b60503ba 1501{
a4aea562 1502 struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq), GFP_KERNEL);
b60503ba
MW		 1503 if (!nvmeq)
1504 return NULL;
1505
e75ec752 1506 nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth),
4d51abf9 1507 &nvmeq->cq_dma_addr, GFP_KERNEL);
b60503ba
MW		 1508 if (!nvmeq->cqes)
1509 goto free_nvmeq;
b60503ba 1510
8ffaadf7 1511 if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth))
b60503ba
MW		 1512 goto free_cqdma;
1513
e75ec752 1514 nvmeq->q_dmadev = dev->dev;
091b6092 1515 nvmeq->dev = dev;
3193f07b
MW		 1516 snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d",
1517 dev->instance, qid);
b60503ba
MW		 1518 spin_lock_init(&nvmeq->q_lock);
1519 nvmeq->cq_head = 0;
82123460 1520 nvmeq->cq_phase = 1;
b80d5ccc 1521 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
b60503ba 1522 nvmeq->q_depth = depth;
c30341dc 1523 nvmeq->qid = qid;
758dd7fd 1524 nvmeq->cq_vector = -1;
a4aea562 1525 dev->queues[qid] = nvmeq;
b60503ba 1526
36a7e993
JD		 1527 /* make sure queue descriptor is set before queue count, for kthread */
1528 mb();
1529 dev->queue_count++;
1530
b60503ba
MW		 1531 return nvmeq;
1532
1533 free_cqdma:
e75ec752 1534 dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes,
b60503ba
MW		 1535 nvmeq->cq_dma_addr);
1536 free_nvmeq:
1537 kfree(nvmeq);
1538 return NULL;
1539}
1540
3001082c
MW		 1541static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1542 const char *name)
1543{
58ffacb5
MW		 1544 if (use_threaded_interrupts)
1545 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
481e5bad 1546 nvme_irq_check, nvme_irq, IRQF_SHARED,
58ffacb5 1547 name, nvmeq);
3001082c 1548 return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
481e5bad 1549 IRQF_SHARED, name, nvmeq);
3001082c
MW		 1550}
1551
22404274 1552static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
b60503ba 1553{
22404274 1554 struct nvme_dev *dev = nvmeq->dev;
b60503ba 1555
7be50e93 1556 spin_lock_irq(&nvmeq->q_lock);
22404274
KB		 1557 nvmeq->sq_tail = 0;
1558 nvmeq->cq_head = 0;
1559 nvmeq->cq_phase = 1;
b80d5ccc 1560 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
22404274 1561 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
42f61420 1562 dev->online_queues++;
7be50e93 1563 spin_unlock_irq(&nvmeq->q_lock);
22404274
KB		 1564}
1565
1566static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1567{
1568 struct nvme_dev *dev = nvmeq->dev;
1569 int result;
3f85d50b 1570
2b25d981 1571 nvmeq->cq_vector = qid - 1;
b60503ba
MW		 1572 result = adapter_alloc_cq(dev, qid, nvmeq);
1573 if (result < 0)
22404274 1574 return result;
b60503ba
MW		 1575
1576 result = adapter_alloc_sq(dev, qid, nvmeq);
1577 if (result < 0)
1578 goto release_cq;
1579
3193f07b 1580 result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
b60503ba
MW		 1581 if (result < 0)
1582 goto release_sq;
1583
22404274 1584 nvme_init_queue(nvmeq, qid);
22404274 1585 return result;
b60503ba
MW		 1586
1587 release_sq:
1588 adapter_delete_sq(dev, qid);
1589 release_cq:
1590 adapter_delete_cq(dev, qid);
22404274 1591 return result;
b60503ba
MW		 1592}
1593
ba47e386
MW		 1594static int nvme_wait_ready(struct nvme_dev *dev, u64 cap, bool enabled)
1595{
1596 unsigned long timeout;
1597 u32 bit = enabled ? NVME_CSTS_RDY : 0;
1598
1599 timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
1600
1601 while ((readl(&dev->bar->csts) & NVME_CSTS_RDY) != bit) {
1602 msleep(100);
1603 if (fatal_signal_pending(current))
1604 return -EINTR;
1605 if (time_after(jiffies, timeout)) {
e75ec752 1606 dev_err(dev->dev,
27e8166c
MW		 1607 "Device not ready; aborting %s\n", enabled ?
1608 "initialisation" : "reset");
ba47e386
MW		 1609 return -ENODEV;
1610 }
1611 }
1612
1613 return 0;
1614}
1615
1616/*
1617 * If the device has been passed off to us in an enabled state, just clear
1618 * the enabled bit. The spec says we should set the 'shutdown notification
1619 * bits', but doing so may cause the device to complete commands to the
1620 * admin queue ... and we don't know what memory that might be pointing at!
1621 */
1622static int nvme_disable_ctrl(struct nvme_dev *dev, u64 cap)
1623{
01079522
DM		 1624 dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1625 dev->ctrl_config &= ~NVME_CC_ENABLE;
1626 writel(dev->ctrl_config, &dev->bar->cc);
44af146a 1627
ba47e386
MW		 1628 return nvme_wait_ready(dev, cap, false);
1629}
1630
1631static int nvme_enable_ctrl(struct nvme_dev *dev, u64 cap)
1632{
01079522
DM		 1633 dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1634 dev->ctrl_config |= NVME_CC_ENABLE;
1635 writel(dev->ctrl_config, &dev->bar->cc);
1636
ba47e386
MW		 1637 return nvme_wait_ready(dev, cap, true);
1638}
1639
1894d8f1
KB		 1640static int nvme_shutdown_ctrl(struct nvme_dev *dev)
1641{
1642 unsigned long timeout;
1894d8f1 1643
01079522
DM		 1644 dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1645 dev->ctrl_config |= NVME_CC_SHN_NORMAL;
1646
1647 writel(dev->ctrl_config, &dev->bar->cc);
1894d8f1 1648
2484f407 1649 timeout = SHUTDOWN_TIMEOUT + jiffies;
1894d8f1
KB		 1650 while ((readl(&dev->bar->csts) & NVME_CSTS_SHST_MASK) !=
1651 NVME_CSTS_SHST_CMPLT) {
1652 msleep(100);
1653 if (fatal_signal_pending(current))
1654 return -EINTR;
1655 if (time_after(jiffies, timeout)) {
e75ec752 1656 dev_err(dev->dev,
1894d8f1
KB		 1657 "Device shutdown incomplete; abort shutdown\n");
1658 return -ENODEV;
1659 }
1660 }
1661
1662 return 0;
1663}
1664
a4aea562 1665static struct blk_mq_ops nvme_mq_admin_ops = {
d29ec824 1666 .queue_rq = nvme_queue_rq,
a4aea562
MB		 1667 .map_queue = blk_mq_map_queue,
1668 .init_hctx = nvme_admin_init_hctx,
4af0e21c 1669 .exit_hctx = nvme_admin_exit_hctx,
a4aea562
MB		 1670 .init_request = nvme_admin_init_request,
1671 .timeout = nvme_timeout,
1672};
1673
1674static struct blk_mq_ops nvme_mq_ops = {
1675 .queue_rq = nvme_queue_rq,
1676 .map_queue = blk_mq_map_queue,
1677 .init_hctx = nvme_init_hctx,
1678 .init_request = nvme_init_request,
1679 .timeout = nvme_timeout,
a0fa9647 1680 .poll = nvme_poll,
a4aea562
MB		 1681};
1682
ea191d2f
KB		 1683static void nvme_dev_remove_admin(struct nvme_dev *dev)
1684{
1685 if (dev->admin_q && !blk_queue_dying(dev->admin_q)) {
1686 blk_cleanup_queue(dev->admin_q);
1687 blk_mq_free_tag_set(&dev->admin_tagset);
1688 }
1689}
1690
a4aea562
MB		 1691static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1692{
1693 if (!dev->admin_q) {
1694 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1695 dev->admin_tagset.nr_hw_queues = 1;
1696 dev->admin_tagset.queue_depth = NVME_AQ_DEPTH - 1;
1efccc9d 1697 dev->admin_tagset.reserved_tags = 1;
a4aea562 1698 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
e75ec752 1699 dev->admin_tagset.numa_node = dev_to_node(dev->dev);
ac3dd5bd 1700 dev->admin_tagset.cmd_size = nvme_cmd_size(dev);
a4aea562
MB		 1701 dev->admin_tagset.driver_data = dev;
1702
1703 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1704 return -ENOMEM;
1705
1706 dev->admin_q = blk_mq_init_queue(&dev->admin_tagset);
35b489d3 1707 if (IS_ERR(dev->admin_q)) {
a4aea562
MB		 1708 blk_mq_free_tag_set(&dev->admin_tagset);
1709 return -ENOMEM;
1710 }
ea191d2f
KB		 1711 if (!blk_get_queue(dev->admin_q)) {
1712 nvme_dev_remove_admin(dev);
4af0e21c 1713 dev->admin_q = NULL;
ea191d2f
KB		 1714 return -ENODEV;
1715 }
0fb59cbc
KB		 1716 } else
1717 blk_mq_unfreeze_queue(dev->admin_q);
a4aea562
MB		 1718
1719 return 0;
1720}
1721
8d85fce7 1722static int nvme_configure_admin_queue(struct nvme_dev *dev)
b60503ba 1723{
ba47e386 1724 int result;
b60503ba 1725 u32 aqa;
ba47e386 1726 u64 cap = readq(&dev->bar->cap);
b60503ba 1727 struct nvme_queue *nvmeq;
1d090624
KB		 1728 unsigned page_shift = PAGE_SHIFT;
1729 unsigned dev_page_min = NVME_CAP_MPSMIN(cap) + 12;
1730 unsigned dev_page_max = NVME_CAP_MPSMAX(cap) + 12;
1731
1732 if (page_shift < dev_page_min) {
e75ec752 1733 dev_err(dev->dev,
1d090624
KB		 1734 "Minimum device page size (%u) too large for "
1735 "host (%u)\n", 1 << dev_page_min,
1736 1 << page_shift);
1737 return -ENODEV;
1738 }
1739 if (page_shift > dev_page_max) {
e75ec752 1740 dev_info(dev->dev,
1d090624
KB		 1741 "Device maximum page size (%u) smaller than "
1742 "host (%u); enabling work-around\n",
1743 1 << dev_page_max, 1 << page_shift);
1744 page_shift = dev_page_max;
1745 }
b60503ba 1746
dfbac8c7
KB		 1747 dev->subsystem = readl(&dev->bar->vs) >= NVME_VS(1, 1) ?
1748 NVME_CAP_NSSRC(cap) : 0;
1749
1750 if (dev->subsystem && (readl(&dev->bar->csts) & NVME_CSTS_NSSRO))
1751 writel(NVME_CSTS_NSSRO, &dev->bar->csts);
1752
ba47e386
MW		 1753 result = nvme_disable_ctrl(dev, cap);
1754 if (result < 0)
1755 return result;
b60503ba 1756
a4aea562 1757 nvmeq = dev->queues[0];
cd638946 1758 if (!nvmeq) {
2b25d981 1759 nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
cd638946
KB		 1760 if (!nvmeq)
1761 return -ENOMEM;
cd638946 1762 }
b60503ba
MW		 1763
1764 aqa = nvmeq->q_depth - 1;
1765 aqa |= aqa << 16;
1766
1d090624
KB		 1767 dev->page_size = 1 << page_shift;
1768
01079522 1769 dev->ctrl_config = NVME_CC_CSS_NVM;
1d090624 1770 dev->ctrl_config |= (page_shift - 12) << NVME_CC_MPS_SHIFT;
b60503ba 1771 dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
7f53f9d2 1772 dev->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
b60503ba
MW		 1773
1774 writel(aqa, &dev->bar->aqa);
1775 writeq(nvmeq->sq_dma_addr, &dev->bar->asq);
1776 writeq(nvmeq->cq_dma_addr, &dev->bar->acq);
b60503ba 1777
ba47e386 1778 result = nvme_enable_ctrl(dev, cap);
025c557a 1779 if (result)
a4aea562
MB		 1780 goto free_nvmeq;
1781
2b25d981 1782 nvmeq->cq_vector = 0;
3193f07b 1783 result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
758dd7fd
JD		 1784 if (result) {
1785 nvmeq->cq_vector = -1;
0fb59cbc 1786 goto free_nvmeq;
758dd7fd 1787 }
025c557a 1788
b60503ba 1789 return result;
a4aea562 1790
a4aea562
MB		 1791 free_nvmeq:
1792 nvme_free_queues(dev, 0);
1793 return result;
b60503ba
MW		 1794}
1795
a53295b6
MW		 1796static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
1797{
1798 struct nvme_dev *dev = ns->dev;
a53295b6
MW		 1799 struct nvme_user_io io;
1800 struct nvme_command c;
d29ec824 1801 unsigned length, meta_len;
a67a9513 1802 int status, write;
a67a9513
KB		 1803 dma_addr_t meta_dma = 0;
1804 void *meta = NULL;
fec558b5 1805 void __user *metadata;
a53295b6
MW		 1806
1807 if (copy_from_user(&io, uio, sizeof(io)))
1808 return -EFAULT;
6c7d4945
MW		 1809
1810 switch (io.opcode) {
1811 case nvme_cmd_write:
1812 case nvme_cmd_read:
6bbf1acd 1813 case nvme_cmd_compare:
6413214c 1814 break;
6c7d4945 1815 default:
6bbf1acd 1816 return -EINVAL;
6c7d4945
MW		 1817 }
1818
d29ec824
CH		 1819 length = (io.nblocks + 1) << ns->lba_shift;
1820 meta_len = (io.nblocks + 1) * ns->ms;
835da3f9 1821 metadata = (void __user *)(uintptr_t)io.metadata;
d29ec824 1822 write = io.opcode & 1;
a53295b6 1823
71feb364
KB		 1824 if (ns->ext) {
1825 length += meta_len;
1826 meta_len = 0;
a67a9513
KB		 1827 }
1828 if (meta_len) {
d29ec824
CH		 1829 if (((io.metadata & 3) || !io.metadata) && !ns->ext)
1830 return -EINVAL;
1831
e75ec752 1832 meta = dma_alloc_coherent(dev->dev, meta_len,
a67a9513 1833 &meta_dma, GFP_KERNEL);
fec558b5 1834
a67a9513
KB		 1835 if (!meta) {
1836 status = -ENOMEM;
1837 goto unmap;
1838 }
1839 if (write) {
fec558b5 1840 if (copy_from_user(meta, metadata, meta_len)) {
a67a9513
KB		 1841 status = -EFAULT;
1842 goto unmap;
1843 }
1844 }
1845 }
1846
a53295b6
MW		 1847 memset(&c, 0, sizeof(c));
1848 c.rw.opcode = io.opcode;
1849 c.rw.flags = io.flags;
6c7d4945 1850 c.rw.nsid = cpu_to_le32(ns->ns_id);
a53295b6 1851 c.rw.slba = cpu_to_le64(io.slba);
6c7d4945 1852 c.rw.length = cpu_to_le16(io.nblocks);
a53295b6 1853 c.rw.control = cpu_to_le16(io.control);
1c9b5265
MW		 1854 c.rw.dsmgmt = cpu_to_le32(io.dsmgmt);
1855 c.rw.reftag = cpu_to_le32(io.reftag);
1856 c.rw.apptag = cpu_to_le16(io.apptag);
1857 c.rw.appmask = cpu_to_le16(io.appmask);
a67a9513 1858 c.rw.metadata = cpu_to_le64(meta_dma);
d29ec824
CH		 1859
1860 status = __nvme_submit_sync_cmd(ns->queue, &c, NULL,
835da3f9 1861 (void __user *)(uintptr_t)io.addr, length, NULL, 0);
f410c680 1862 unmap:
a67a9513
KB		 1863 if (meta) {
1864 if (status == NVME_SC_SUCCESS && !write) {
fec558b5 1865 if (copy_to_user(metadata, meta, meta_len))
a67a9513
KB		 1866 status = -EFAULT;
1867 }
e75ec752 1868 dma_free_coherent(dev->dev, meta_len, meta, meta_dma);
f410c680 1869 }
a53295b6
MW		 1870 return status;
1871}
1872
a4aea562
MB		 1873static int nvme_user_cmd(struct nvme_dev *dev, struct nvme_ns *ns,
1874 struct nvme_passthru_cmd __user *ucmd)
6ee44cdc 1875{
7963e521 1876 struct nvme_passthru_cmd cmd;
6ee44cdc 1877 struct nvme_command c;
d29ec824
CH		 1878 unsigned timeout = 0;
1879 int status;
6ee44cdc 1880
6bbf1acd
MW		 1881 if (!capable(CAP_SYS_ADMIN))
1882 return -EACCES;
1883 if (copy_from_user(&cmd, ucmd, sizeof(cmd)))
6ee44cdc 1884 return -EFAULT;
6ee44cdc
MW		 1885
1886 memset(&c, 0, sizeof(c));
6bbf1acd
MW		 1887 c.common.opcode = cmd.opcode;
1888 c.common.flags = cmd.flags;
1889 c.common.nsid = cpu_to_le32(cmd.nsid);
1890 c.common.cdw2[0] = cpu_to_le32(cmd.cdw2);
1891 c.common.cdw2[1] = cpu_to_le32(cmd.cdw3);
1892 c.common.cdw10[0] = cpu_to_le32(cmd.cdw10);
1893 c.common.cdw10[1] = cpu_to_le32(cmd.cdw11);
1894 c.common.cdw10[2] = cpu_to_le32(cmd.cdw12);
1895 c.common.cdw10[3] = cpu_to_le32(cmd.cdw13);
1896 c.common.cdw10[4] = cpu_to_le32(cmd.cdw14);
1897 c.common.cdw10[5] = cpu_to_le32(cmd.cdw15);
1898
d29ec824
CH		 1899 if (cmd.timeout_ms)
1900 timeout = msecs_to_jiffies(cmd.timeout_ms);
eca18b23 1901
f705f837 1902 status = __nvme_submit_sync_cmd(ns ? ns->queue : dev->admin_q, &c,
835da3f9 1903 NULL, (void __user *)(uintptr_t)cmd.addr, cmd.data_len,
d29ec824
CH		 1904 &cmd.result, timeout);
1905 if (status >= 0) {
1906 if (put_user(cmd.result, &ucmd->result))
1907 return -EFAULT;
6bbf1acd 1908 }
f4f117f6 1909
6ee44cdc
MW		 1910 return status;
1911}
1912
81f03fed
JD		 1913static int nvme_subsys_reset(struct nvme_dev *dev)
1914{
1915 if (!dev->subsystem)
1916 return -ENOTTY;
1917
1918 writel(0x4E564D65, &dev->bar->nssr); /* "NVMe" */
1919 return 0;
1920}
1921
b60503ba
MW		 1922static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd,
1923 unsigned long arg)
1924{
1925 struct nvme_ns *ns = bdev->bd_disk->private_data;
1926
1927 switch (cmd) {
6bbf1acd 1928 case NVME_IOCTL_ID:
c3bfe717 1929 force_successful_syscall_return();
6bbf1acd
MW		 1930 return ns->ns_id;
1931 case NVME_IOCTL_ADMIN_CMD:
a4aea562 1932 return nvme_user_cmd(ns->dev, NULL, (void __user *)arg);
7963e521 1933 case NVME_IOCTL_IO_CMD:
a4aea562 1934 return nvme_user_cmd(ns->dev, ns, (void __user *)arg);
a53295b6
MW		 1935 case NVME_IOCTL_SUBMIT_IO:
1936 return nvme_submit_io(ns, (void __user *)arg);
5d0f6131
VV		 1937 case SG_GET_VERSION_NUM:
1938 return nvme_sg_get_version_num((void __user *)arg);
1939 case SG_IO:
1940 return nvme_sg_io(ns, (void __user *)arg);
b60503ba
MW		 1941 default:
1942 return -ENOTTY;
1943 }
1944}
1945
320a3827
KB		 1946#ifdef CONFIG_COMPAT
1947static int nvme_compat_ioctl(struct block_device *bdev, fmode_t mode,
1948 unsigned int cmd, unsigned long arg)
1949{
320a3827
KB		 1950 switch (cmd) {
1951 case SG_IO:
e179729a 1952 return -ENOIOCTLCMD;
320a3827
KB		 1953 }
1954 return nvme_ioctl(bdev, mode, cmd, arg);
1955}
1956#else
1957#define nvme_compat_ioctl NULL
1958#endif
1959
5105aa55 1960static void nvme_free_dev(struct kref *kref);
188c3568
KB		 1961static void nvme_free_ns(struct kref *kref)
1962{
1963 struct nvme_ns *ns = container_of(kref, struct nvme_ns, kref);
1964
ca064085
MB		 1965 if (ns->type == NVME_NS_LIGHTNVM)
1966 nvme_nvm_unregister(ns->queue, ns->disk->disk_name);
1967
188c3568
KB		 1968 spin_lock(&dev_list_lock);
1969 ns->disk->private_data = NULL;
1970 spin_unlock(&dev_list_lock);
1971
5105aa55 1972 kref_put(&ns->dev->kref, nvme_free_dev);
188c3568
KB		 1973 put_disk(ns->disk);
1974 kfree(ns);
1975}
1976
9ac27090
KB		 1977static int nvme_open(struct block_device *bdev, fmode_t mode)
1978{
9e60352c
KB		 1979 int ret = 0;
1980 struct nvme_ns *ns;
9ac27090 1981
9e60352c
KB		 1982 spin_lock(&dev_list_lock);
1983 ns = bdev->bd_disk->private_data;
1984 if (!ns)
1985 ret = -ENXIO;
188c3568 1986 else if (!kref_get_unless_zero(&ns->kref))
9e60352c
KB		 1987 ret = -ENXIO;
1988 spin_unlock(&dev_list_lock);
1989
1990 return ret;
9ac27090
KB		 1991}
1992
9ac27090
KB		 1993static void nvme_release(struct gendisk *disk, fmode_t mode)
1994{
1995 struct nvme_ns *ns = disk->private_data;
188c3568 1996 kref_put(&ns->kref, nvme_free_ns);
9ac27090
KB		 1997}
1998
4cc09e2d
KB		 1999static int nvme_getgeo(struct block_device *bd, struct hd_geometry *geo)
2000{
2001 /* some standard values */
2002 geo->heads = 1 << 6;
2003 geo->sectors = 1 << 5;
2004 geo->cylinders = get_capacity(bd->bd_disk) >> 11;
2005 return 0;
2006}
2007
e1e5e564
KB		 2008static void nvme_config_discard(struct nvme_ns *ns)
2009{
2010 u32 logical_block_size = queue_logical_block_size(ns->queue);
2011 ns->queue->limits.discard_zeroes_data = 0;
2012 ns->queue->limits.discard_alignment = logical_block_size;
2013 ns->queue->limits.discard_granularity = logical_block_size;
2bb4cd5c 2014 blk_queue_max_discard_sectors(ns->queue, 0xffffffff);
e1e5e564
KB		 2015 queue_flag_set_unlocked(QUEUE_FLAG_DISCARD, ns->queue);
2016}
2017
1b9dbf7f
KB		 2018static int nvme_revalidate_disk(struct gendisk *disk)
2019{
2020 struct nvme_ns *ns = disk->private_data;
2021 struct nvme_dev *dev = ns->dev;
2022 struct nvme_id_ns *id;
a67a9513
KB		 2023 u8 lbaf, pi_type;
2024 u16 old_ms;
e1e5e564 2025 unsigned short bs;
1b9dbf7f 2026
d29ec824 2027 if (nvme_identify_ns(dev, ns->ns_id, &id)) {
a5768aa8
KB		 2028 dev_warn(dev->dev, "%s: Identify failure nvme%dn%d\n", __func__,
2029 dev->instance, ns->ns_id);
2030 return -ENODEV;
1b9dbf7f 2031 }
a5768aa8
KB		 2032 if (id->ncap == 0) {
2033 kfree(id);
2034 return -ENODEV;
e1e5e564 2035 }
1b9dbf7f 2036
ca064085
MB		 2037 if (nvme_nvm_ns_supported(ns, id) && ns->type != NVME_NS_LIGHTNVM) {
2038 if (nvme_nvm_register(ns->queue, disk->disk_name)) {
2039 dev_warn(dev->dev,
2040 "%s: LightNVM init failure\n", __func__);
2041 kfree(id);
2042 return -ENODEV;
2043 }
2044 ns->type = NVME_NS_LIGHTNVM;
2045 }
2046
e1e5e564
KB		 2047 old_ms = ns->ms;
2048 lbaf = id->flbas & NVME_NS_FLBAS_LBA_MASK;
1b9dbf7f 2049 ns->lba_shift = id->lbaf[lbaf].ds;
e1e5e564 2050 ns->ms = le16_to_cpu(id->lbaf[lbaf].ms);
a67a9513 2051 ns->ext = ns->ms && (id->flbas & NVME_NS_FLBAS_META_EXT);
e1e5e564
KB		 2052
2053 /*
2054 * If identify namespace failed, use default 512 byte block size so
2055 * block layer can use before failing read/write for 0 capacity.
2056 */
2057 if (ns->lba_shift == 0)
2058 ns->lba_shift = 9;
2059 bs = 1 << ns->lba_shift;
2060
2061 /* XXX: PI implementation requires metadata equal t10 pi tuple size */
2062 pi_type = ns->ms == sizeof(struct t10_pi_tuple) ?
2063 id->dps & NVME_NS_DPS_PI_MASK : 0;
2064
4cfc766e 2065 blk_mq_freeze_queue(disk->queue);
52b68d7e
KB		 2066 if (blk_get_integrity(disk) && (ns->pi_type != pi_type ||
2067 ns->ms != old_ms ||
e1e5e564 2068 bs != queue_logical_block_size(disk->queue) ||
a67a9513 2069 (ns->ms && ns->ext)))
e1e5e564
KB		 2070 blk_integrity_unregister(disk);
2071
2072 ns->pi_type = pi_type;
2073 blk_queue_logical_block_size(ns->queue, bs);
2074
25520d55 2075 if (ns->ms && !ns->ext)
e1e5e564
KB		 2076 nvme_init_integrity(ns);
2077
ca064085
MB		 2078 if ((ns->ms && !(ns->ms == 8 && ns->pi_type) &&
2079 !blk_get_integrity(disk)) ||
2080 ns->type == NVME_NS_LIGHTNVM)
e1e5e564
KB		 2081 set_capacity(disk, 0);
2082 else
2083 set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
2084
2085 if (dev->oncs & NVME_CTRL_ONCS_DSM)
2086 nvme_config_discard(ns);
4cfc766e 2087 blk_mq_unfreeze_queue(disk->queue);
1b9dbf7f 2088
d29ec824 2089 kfree(id);
1b9dbf7f
KB		 2090 return 0;
2091}
2092
1d277a63
KB		 2093static char nvme_pr_type(enum pr_type type)
2094{
2095 switch (type) {
2096 case PR_WRITE_EXCLUSIVE:
2097 return 1;
2098 case PR_EXCLUSIVE_ACCESS:
2099 return 2;
2100 case PR_WRITE_EXCLUSIVE_REG_ONLY:
2101 return 3;
2102 case PR_EXCLUSIVE_ACCESS_REG_ONLY:
2103 return 4;
2104 case PR_WRITE_EXCLUSIVE_ALL_REGS:
2105 return 5;
2106 case PR_EXCLUSIVE_ACCESS_ALL_REGS:
2107 return 6;
2108 default:
2109 return 0;
2110 }
2111};
2112
2113static int nvme_pr_command(struct block_device *bdev, u32 cdw10,
2114 u64 key, u64 sa_key, u8 op)
2115{
2116 struct nvme_ns *ns = bdev->bd_disk->private_data;
2117 struct nvme_command c;
2118 u8 data[16] = { 0, };
2119
2120 put_unaligned_le64(key, &data[0]);
2121 put_unaligned_le64(sa_key, &data[8]);
2122
2123 memset(&c, 0, sizeof(c));
2124 c.common.opcode = op;
a6dd1020
CH		 2125 c.common.nsid = cpu_to_le32(ns->ns_id);
2126 c.common.cdw10[0] = cpu_to_le32(cdw10);
1d277a63
KB		 2127
2128 return nvme_submit_sync_cmd(ns->queue, &c, data, 16);
2129}
2130
2131static int nvme_pr_register(struct block_device *bdev, u64 old,
2132 u64 new, unsigned flags)
2133{
2134 u32 cdw10;
2135
2136 if (flags & ~PR_FL_IGNORE_KEY)
2137 return -EOPNOTSUPP;
2138
2139 cdw10 = old ? 2 : 0;
2140 cdw10 |= (flags & PR_FL_IGNORE_KEY) ? 1 << 3 : 0;
2141 cdw10 |= (1 << 30) | (1 << 31); /* PTPL=1 */
2142 return nvme_pr_command(bdev, cdw10, old, new, nvme_cmd_resv_register);
2143}
2144
2145static int nvme_pr_reserve(struct block_device *bdev, u64 key,
2146 enum pr_type type, unsigned flags)
2147{
2148 u32 cdw10;
2149
2150 if (flags & ~PR_FL_IGNORE_KEY)
2151 return -EOPNOTSUPP;
2152
2153 cdw10 = nvme_pr_type(type) << 8;
2154 cdw10 |= ((flags & PR_FL_IGNORE_KEY) ? 1 << 3 : 0);
2155 return nvme_pr_command(bdev, cdw10, key, 0, nvme_cmd_resv_acquire);
2156}
2157
2158static int nvme_pr_preempt(struct block_device *bdev, u64 old, u64 new,
2159 enum pr_type type, bool abort)
2160{
2161 u32 cdw10 = nvme_pr_type(type) << 8 | abort ? 2 : 1;
2162 return nvme_pr_command(bdev, cdw10, old, new, nvme_cmd_resv_acquire);
2163}
2164
2165static int nvme_pr_clear(struct block_device *bdev, u64 key)
2166{
73fcf4e2 2167 u32 cdw10 = 1 | (key ? 1 << 3 : 0);
1d277a63
KB		 2168 return nvme_pr_command(bdev, cdw10, key, 0, nvme_cmd_resv_register);
2169}
2170
2171static int nvme_pr_release(struct block_device *bdev, u64 key, enum pr_type type)
2172{
2173 u32 cdw10 = nvme_pr_type(type) << 8 | key ? 1 << 3 : 0;
2174 return nvme_pr_command(bdev, cdw10, key, 0, nvme_cmd_resv_release);
2175}
2176
2177static const struct pr_ops nvme_pr_ops = {
2178 .pr_register = nvme_pr_register,
2179 .pr_reserve = nvme_pr_reserve,
2180 .pr_release = nvme_pr_release,
2181 .pr_preempt = nvme_pr_preempt,
2182 .pr_clear = nvme_pr_clear,
2183};
2184
b60503ba
MW		 2185static const struct block_device_operations nvme_fops = {
2186 .owner = THIS_MODULE,
2187 .ioctl = nvme_ioctl,
320a3827 2188 .compat_ioctl = nvme_compat_ioctl,
9ac27090
KB		 2189 .open = nvme_open,
2190 .release = nvme_release,
4cc09e2d 2191 .getgeo = nvme_getgeo,
1b9dbf7f 2192 .revalidate_disk= nvme_revalidate_disk,
1d277a63 2193 .pr_ops = &nvme_pr_ops,
b60503ba
MW		 2194};
2195
1fa6aead
MW		 2196static int nvme_kthread(void *data)
2197{
d4b4ff8e 2198 struct nvme_dev *dev, *next;
1fa6aead
MW		 2199
2200 while (!kthread_should_stop()) {
564a232c 2201 set_current_state(TASK_INTERRUPTIBLE);
1fa6aead 2202 spin_lock(&dev_list_lock);
d4b4ff8e 2203 list_for_each_entry_safe(dev, next, &dev_list, node) {
1fa6aead 2204 int i;
dfbac8c7
KB		 2205 u32 csts = readl(&dev->bar->csts);
2206
2207 if ((dev->subsystem && (csts & NVME_CSTS_NSSRO)) ||
2208 csts & NVME_CSTS_CFS) {
90667892
CH		 2209 if (!__nvme_reset(dev)) {
2210 dev_warn(dev->dev,
2211 "Failed status: %x, reset controller\n",
2212 readl(&dev->bar->csts));
2213 }
d4b4ff8e
KB		 2214 continue;
2215 }
1fa6aead 2216 for (i = 0; i < dev->queue_count; i++) {
a4aea562 2217 struct nvme_queue *nvmeq = dev->queues[i];
740216fc
MW		 2218 if (!nvmeq)
2219 continue;
1fa6aead 2220 spin_lock_irq(&nvmeq->q_lock);
bc57a0f7 2221 nvme_process_cq(nvmeq);
6fccf938
KB		 2222
2223 while ((i == 0) && (dev->event_limit > 0)) {
a4aea562 2224 if (nvme_submit_async_admin_req(dev))
6fccf938
KB		 2225 break;
2226 dev->event_limit--;
2227 }
1fa6aead
MW		 2228 spin_unlock_irq(&nvmeq->q_lock);
2229 }
2230 }
2231 spin_unlock(&dev_list_lock);
acb7aa0d 2232 schedule_timeout(round_jiffies_relative(HZ));
1fa6aead
MW		 2233 }
2234 return 0;
2235}
2236
e1e5e564 2237static void nvme_alloc_ns(struct nvme_dev *dev, unsigned nsid)
b60503ba
MW		 2238{
2239 struct nvme_ns *ns;
2240 struct gendisk *disk;
e75ec752 2241 int node = dev_to_node(dev->dev);
b60503ba 2242
a4aea562 2243 ns = kzalloc_node(sizeof(*ns), GFP_KERNEL, node);
b60503ba 2244 if (!ns)
e1e5e564
KB		 2245 return;
2246
a4aea562 2247 ns->queue = blk_mq_init_queue(&dev->tagset);
9f173b33 2248 if (IS_ERR(ns->queue))
b60503ba 2249 goto out_free_ns;
4eeb9215
MW		 2250 queue_flag_set_unlocked(QUEUE_FLAG_NOMERGES, ns->queue);
2251 queue_flag_set_unlocked(QUEUE_FLAG_NONROT, ns->queue);
b60503ba
MW		 2252 ns->dev = dev;
2253 ns->queue->queuedata = ns;
2254
a4aea562 2255 disk = alloc_disk_node(0, node);
b60503ba
MW		 2256 if (!disk)
2257 goto out_free_queue;
a4aea562 2258
188c3568 2259 kref_init(&ns->kref);
5aff9382 2260 ns->ns_id = nsid;
b60503ba 2261 ns->disk = disk;
e1e5e564
KB		 2262 ns->lba_shift = 9; /* set to a default value for 512 until disk is validated */
2263 list_add_tail(&ns->list, &dev->namespaces);
2264
e9ef4636 2265 blk_queue_logical_block_size(ns->queue, 1 << ns->lba_shift);
e824410f 2266 if (dev->max_hw_sectors) {
8fc23e03 2267 blk_queue_max_hw_sectors(ns->queue, dev->max_hw_sectors);
e824410f
KB		 2268 blk_queue_max_segments(ns->queue,
2269 ((dev->max_hw_sectors << 9) / dev->page_size) + 1);
2270 }
a4aea562
MB		 2271 if (dev->stripe_size)
2272 blk_queue_chunk_sectors(ns->queue, dev->stripe_size >> 9);
a7d2ce28
KB		 2273 if (dev->vwc & NVME_CTRL_VWC_PRESENT)
2274 blk_queue_flush(ns->queue, REQ_FLUSH | REQ_FUA);
03100aad 2275 blk_queue_virt_boundary(ns->queue, dev->page_size - 1);
b60503ba
MW		 2276
2277 disk->major = nvme_major;
469071a3 2278 disk->first_minor = 0;
b60503ba
MW		 2279 disk->fops = &nvme_fops;
2280 disk->private_data = ns;
2281 disk->queue = ns->queue;
b3fffdef 2282 disk->driverfs_dev = dev->device;
469071a3 2283 disk->flags = GENHD_FL_EXT_DEVT;
5aff9382 2284 sprintf(disk->disk_name, "nvme%dn%d", dev->instance, nsid);
b60503ba 2285
e1e5e564
KB		 2286 /*
2287 * Initialize capacity to 0 until we establish the namespace format and
2288 * setup integrity extentions if necessary. The revalidate_disk after
2289 * add_disk allows the driver to register with integrity if the format
2290 * requires it.
2291 */
2292 set_capacity(disk, 0);
a5768aa8
KB		 2293 if (nvme_revalidate_disk(ns->disk))
2294 goto out_free_disk;
2295
5105aa55 2296 kref_get(&dev->kref);
ca064085
MB		 2297 if (ns->type != NVME_NS_LIGHTNVM) {
2298 add_disk(ns->disk);
2299 if (ns->ms) {
2300 struct block_device *bd = bdget_disk(ns->disk, 0);
2301 if (!bd)
2302 return;
2303 if (blkdev_get(bd, FMODE_READ, NULL)) {
2304 bdput(bd);
2305 return;
2306 }
2307 blkdev_reread_part(bd);
2308 blkdev_put(bd, FMODE_READ);
7bee6074 2309 }
7bee6074 2310 }
e1e5e564 2311 return;
a5768aa8
KB		 2312 out_free_disk:
2313 kfree(disk);
2314 list_del(&ns->list);
b60503ba
MW		 2315 out_free_queue:
2316 blk_cleanup_queue(ns->queue);
2317 out_free_ns:
2318 kfree(ns);
b60503ba
MW		 2319}
2320
2659e57b
CH		 2321/*
2322 * Create I/O queues. Failing to create an I/O queue is not an issue,
2323 * we can continue with less than the desired amount of queues, and
2324 * even a controller without I/O queues an still be used to issue
2325 * admin commands. This might be useful to upgrade a buggy firmware
2326 * for example.
2327 */
42f61420
KB		 2328static void nvme_create_io_queues(struct nvme_dev *dev)
2329{
a4aea562 2330 unsigned i;
42f61420 2331
a4aea562 2332 for (i = dev->queue_count; i <= dev->max_qid; i++)
2b25d981 2333 if (!nvme_alloc_queue(dev, i, dev->q_depth))
42f61420
KB		 2334 break;
2335
a4aea562 2336 for (i = dev->online_queues; i <= dev->queue_count - 1; i++)
2659e57b
CH		 2337 if (nvme_create_queue(dev->queues[i], i)) {
2338 nvme_free_queues(dev, i);
42f61420 2339 break;
2659e57b 2340 }
42f61420
KB		 2341}
2342
b3b06812 2343static int set_queue_count(struct nvme_dev *dev, int count)
b60503ba
MW		 2344{
2345 int status;
2346 u32 result;
b3b06812 2347 u32 q_count = (count - 1) | ((count - 1) << 16);
b60503ba 2348
df348139 2349 status = nvme_set_features(dev, NVME_FEAT_NUM_QUEUES, q_count, 0,
bc5fc7e4 2350 &result);
27e8166c
MW		 2351 if (status < 0)
2352 return status;
2353 if (status > 0) {
e75ec752 2354 dev_err(dev->dev, "Could not set queue count (%d)\n", status);
badc34d4 2355 return 0;
27e8166c 2356 }
b60503ba
MW		 2357 return min(result & 0xffff, result >> 16) + 1;
2358}
2359
8ffaadf7
JD		 2360static void __iomem *nvme_map_cmb(struct nvme_dev *dev)
2361{
2362 u64 szu, size, offset;
2363 u32 cmbloc;
2364 resource_size_t bar_size;
2365 struct pci_dev *pdev = to_pci_dev(dev->dev);
2366 void __iomem *cmb;
2367 dma_addr_t dma_addr;
2368
2369 if (!use_cmb_sqes)
2370 return NULL;
2371
2372 dev->cmbsz = readl(&dev->bar->cmbsz);
2373 if (!(NVME_CMB_SZ(dev->cmbsz)))
2374 return NULL;
2375
2376 cmbloc = readl(&dev->bar->cmbloc);
2377
2378 szu = (u64)1 << (12 + 4 * NVME_CMB_SZU(dev->cmbsz));
2379 size = szu * NVME_CMB_SZ(dev->cmbsz);
2380 offset = szu * NVME_CMB_OFST(cmbloc);
2381 bar_size = pci_resource_len(pdev, NVME_CMB_BIR(cmbloc));
2382
2383 if (offset > bar_size)
2384 return NULL;
2385
2386 /*
2387 * Controllers may support a CMB size larger than their BAR,
2388 * for example, due to being behind a bridge. Reduce the CMB to
2389 * the reported size of the BAR
2390 */
2391 if (size > bar_size - offset)
2392 size = bar_size - offset;
2393
2394 dma_addr = pci_resource_start(pdev, NVME_CMB_BIR(cmbloc)) + offset;
2395 cmb = ioremap_wc(dma_addr, size);
2396 if (!cmb)
2397 return NULL;
2398
2399 dev->cmb_dma_addr = dma_addr;
2400 dev->cmb_size = size;
2401 return cmb;
2402}
2403
2404static inline void nvme_release_cmb(struct nvme_dev *dev)
2405{
2406 if (dev->cmb) {
2407 iounmap(dev->cmb);
2408 dev->cmb = NULL;
2409 }
2410}
2411
9d713c2b
KB		 2412static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
2413{
b80d5ccc 2414 return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride);
9d713c2b
KB		 2415}
2416
8d85fce7 2417static int nvme_setup_io_queues(struct nvme_dev *dev)
b60503ba 2418{
a4aea562 2419 struct nvme_queue *adminq = dev->queues[0];
e75ec752 2420 struct pci_dev *pdev = to_pci_dev(dev->dev);
42f61420 2421 int result, i, vecs, nr_io_queues, size;
b60503ba 2422
42f61420 2423 nr_io_queues = num_possible_cpus();
b348b7d5 2424 result = set_queue_count(dev, nr_io_queues);
badc34d4 2425 if (result <= 0)
1b23484b 2426 return result;
b348b7d5
MW		 2427 if (result < nr_io_queues)
2428 nr_io_queues = result;
b60503ba 2429
8ffaadf7
JD		 2430 if (dev->cmb && NVME_CMB_SQS(dev->cmbsz)) {
2431 result = nvme_cmb_qdepth(dev, nr_io_queues,
2432 sizeof(struct nvme_command));
2433 if (result > 0)
2434 dev->q_depth = result;
2435 else
2436 nvme_release_cmb(dev);
2437 }
2438
9d713c2b
KB		 2439 size = db_bar_size(dev, nr_io_queues);
2440 if (size > 8192) {
f1938f6e 2441 iounmap(dev->bar);
9d713c2b
KB		 2442 do {
2443 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
2444 if (dev->bar)
2445 break;
2446 if (!--nr_io_queues)
2447 return -ENOMEM;
2448 size = db_bar_size(dev, nr_io_queues);
2449 } while (1);
f1938f6e 2450 dev->dbs = ((void __iomem *)dev->bar) + 4096;
5a92e700 2451 adminq->q_db = dev->dbs;
f1938f6e
MW		 2452 }
2453
9d713c2b 2454 /* Deregister the admin queue's interrupt */
3193f07b 2455 free_irq(dev->entry[0].vector, adminq);
9d713c2b 2456
e32efbfc
JA		 2457 /*
2458 * If we enable msix early due to not intx, disable it again before
2459 * setting up the full range we need.
2460 */
2461 if (!pdev->irq)
2462 pci_disable_msix(pdev);
2463
be577fab 2464 for (i = 0; i < nr_io_queues; i++)
1b23484b 2465 dev->entry[i].entry = i;
be577fab
AG		 2466 vecs = pci_enable_msix_range(pdev, dev->entry, 1, nr_io_queues);
2467 if (vecs < 0) {
2468 vecs = pci_enable_msi_range(pdev, 1, min(nr_io_queues, 32));
2469 if (vecs < 0) {
2470 vecs = 1;
2471 } else {
2472 for (i = 0; i < vecs; i++)
2473 dev->entry[i].vector = i + pdev->irq;
fa08a396
RRG		 2474 }
2475 }
2476
063a8096
MW		 2477 /*
2478 * Should investigate if there's a performance win from allocating
2479 * more queues than interrupt vectors; it might allow the submission
2480 * path to scale better, even if the receive path is limited by the
2481 * number of interrupts.
2482 */
2483 nr_io_queues = vecs;
42f61420 2484 dev->max_qid = nr_io_queues;
063a8096 2485
3193f07b 2486 result = queue_request_irq(dev, adminq, adminq->irqname);
758dd7fd
JD		 2487 if (result) {
2488 adminq->cq_vector = -1;
22404274 2489 goto free_queues;
758dd7fd 2490 }
1b23484b 2491
cd638946 2492 /* Free previously allocated queues that are no longer usable */
42f61420 2493 nvme_free_queues(dev, nr_io_queues + 1);
a4aea562 2494 nvme_create_io_queues(dev);
9ecdc946 2495
22404274 2496 return 0;
b60503ba 2497
22404274 2498 free_queues:
a1a5ef99 2499 nvme_free_queues(dev, 1);
22404274 2500 return result;
b60503ba
MW		 2501}
2502
a5768aa8
KB		 2503static int ns_cmp(void *priv, struct list_head *a, struct list_head *b)
2504{
2505 struct nvme_ns *nsa = container_of(a, struct nvme_ns, list);
2506 struct nvme_ns *nsb = container_of(b, struct nvme_ns, list);
2507
2508 return nsa->ns_id - nsb->ns_id;
2509}
2510
2511static struct nvme_ns *nvme_find_ns(struct nvme_dev *dev, unsigned nsid)
2512{
2513 struct nvme_ns *ns;
2514
2515 list_for_each_entry(ns, &dev->namespaces, list) {
2516 if (ns->ns_id == nsid)
2517 return ns;
2518 if (ns->ns_id > nsid)
2519 break;
2520 }
2521 return NULL;
2522}
2523
2524static inline bool nvme_io_incapable(struct nvme_dev *dev)
2525{
2526 return (!dev->bar || readl(&dev->bar->csts) & NVME_CSTS_CFS ||
2527 dev->online_queues < 2);
2528}
2529
2530static void nvme_ns_remove(struct nvme_ns *ns)
2531{
2532 bool kill = nvme_io_incapable(ns->dev) && !blk_queue_dying(ns->queue);
2533
2534 if (kill)
2535 blk_set_queue_dying(ns->queue);
9609b994 2536 if (ns->disk->flags & GENHD_FL_UP)
a5768aa8 2537 del_gendisk(ns->disk);
a5768aa8
KB		 2538 if (kill || !blk_queue_dying(ns->queue)) {
2539 blk_mq_abort_requeue_list(ns->queue);
2540 blk_cleanup_queue(ns->queue);
5105aa55
KB		 2541 }
2542 list_del_init(&ns->list);
2543 kref_put(&ns->kref, nvme_free_ns);
a5768aa8
KB		 2544}
2545
2546static void nvme_scan_namespaces(struct nvme_dev *dev, unsigned nn)
2547{
2548 struct nvme_ns *ns, *next;
2549 unsigned i;
2550
2551 for (i = 1; i <= nn; i++) {
2552 ns = nvme_find_ns(dev, i);
2553 if (ns) {
5105aa55 2554 if (revalidate_disk(ns->disk))
a5768aa8 2555 nvme_ns_remove(ns);
a5768aa8
KB		 2556 } else
2557 nvme_alloc_ns(dev, i);
2558 }
2559 list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
5105aa55 2560 if (ns->ns_id > nn)
a5768aa8 2561 nvme_ns_remove(ns);
a5768aa8
KB		 2562 }
2563 list_sort(NULL, &dev->namespaces, ns_cmp);
2564}
2565
bda4e0fb
KB		 2566static void nvme_set_irq_hints(struct nvme_dev *dev)
2567{
2568 struct nvme_queue *nvmeq;
2569 int i;
2570
2571 for (i = 0; i < dev->online_queues; i++) {
2572 nvmeq = dev->queues[i];
2573
2574 if (!nvmeq->tags || !(*nvmeq->tags))
2575 continue;
2576
2577 irq_set_affinity_hint(dev->entry[nvmeq->cq_vector].vector,
2578 blk_mq_tags_cpumask(*nvmeq->tags));
2579 }
2580}
2581
a5768aa8
KB		 2582static void nvme_dev_scan(struct work_struct *work)
2583{
2584 struct nvme_dev *dev = container_of(work, struct nvme_dev, scan_work);
2585 struct nvme_id_ctrl *ctrl;
2586
2587 if (!dev->tagset.tags)
2588 return;
2589 if (nvme_identify_ctrl(dev, &ctrl))
2590 return;
2591 nvme_scan_namespaces(dev, le32_to_cpup(&ctrl->nn));
2592 kfree(ctrl);
bda4e0fb 2593 nvme_set_irq_hints(dev);
a5768aa8
KB		 2594}
2595
422ef0c7
MW		 2596/*
2597 * Return: error value if an error occurred setting up the queues or calling
2598 * Identify Device. 0 if these succeeded, even if adding some of the
2599 * namespaces failed. At the moment, these failures are silent. TBD which
2600 * failures should be reported.
2601 */
8d85fce7 2602static int nvme_dev_add(struct nvme_dev *dev)
b60503ba 2603{
e75ec752 2604 struct pci_dev *pdev = to_pci_dev(dev->dev);
c3bfe717 2605 int res;
51814232 2606 struct nvme_id_ctrl *ctrl;
159b67d7 2607 int shift = NVME_CAP_MPSMIN(readq(&dev->bar->cap)) + 12;
b60503ba 2608
d29ec824 2609 res = nvme_identify_ctrl(dev, &ctrl);
b60503ba 2610 if (res) {
e75ec752 2611 dev_err(dev->dev, "Identify Controller failed (%d)\n", res);
e1e5e564 2612 return -EIO;
b60503ba
MW		 2613 }
2614
0e5e4f0e 2615 dev->oncs = le16_to_cpup(&ctrl->oncs);
c30341dc 2616 dev->abort_limit = ctrl->acl + 1;
a7d2ce28 2617 dev->vwc = ctrl->vwc;
51814232
MW		 2618 memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn));
2619 memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn));
2620 memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr));
159b67d7 2621 if (ctrl->mdts)
8fc23e03 2622 dev->max_hw_sectors = 1 << (ctrl->mdts + shift - 9);
68608c26 2623 if ((pdev->vendor == PCI_VENDOR_ID_INTEL) &&
a4aea562
MB		 2624 (pdev->device == 0x0953) && ctrl->vs[3]) {
2625 unsigned int max_hw_sectors;
2626
159b67d7 2627 dev->stripe_size = 1 << (ctrl->vs[3] + shift);
a4aea562
MB		 2628 max_hw_sectors = dev->stripe_size >> (shift - 9);
2629 if (dev->max_hw_sectors) {
2630 dev->max_hw_sectors = min(max_hw_sectors,
2631 dev->max_hw_sectors);
2632 } else
2633 dev->max_hw_sectors = max_hw_sectors;
2634 }
d29ec824 2635 kfree(ctrl);
a4aea562 2636
ffe7704d
KB		 2637 if (!dev->tagset.tags) {
2638 dev->tagset.ops = &nvme_mq_ops;
2639 dev->tagset.nr_hw_queues = dev->online_queues - 1;
2640 dev->tagset.timeout = NVME_IO_TIMEOUT;
2641 dev->tagset.numa_node = dev_to_node(dev->dev);
2642 dev->tagset.queue_depth =
a4aea562 2643 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
ffe7704d
KB		 2644 dev->tagset.cmd_size = nvme_cmd_size(dev);
2645 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2646 dev->tagset.driver_data = dev;
b60503ba 2647
ffe7704d
KB		 2648 if (blk_mq_alloc_tag_set(&dev->tagset))
2649 return 0;
2650 }
a5768aa8 2651 schedule_work(&dev->scan_work);
e1e5e564 2652 return 0;
b60503ba
MW		 2653}
2654
0877cb0d
KB		 2655static int nvme_dev_map(struct nvme_dev *dev)
2656{
42f61420 2657 u64 cap;
0877cb0d 2658 int bars, result = -ENOMEM;
e75ec752 2659 struct pci_dev *pdev = to_pci_dev(dev->dev);
0877cb0d
KB		 2660
2661 if (pci_enable_device_mem(pdev))
2662 return result;
2663
2664 dev->entry[0].vector = pdev->irq;
2665 pci_set_master(pdev);
2666 bars = pci_select_bars(pdev, IORESOURCE_MEM);
be7837e8
JA		 2667 if (!bars)
2668 goto disable_pci;
2669
0877cb0d
KB		 2670 if (pci_request_selected_regions(pdev, bars, "nvme"))
2671 goto disable_pci;
2672
e75ec752
CH		 2673 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) &&
2674 dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32)))
052d0efa 2675 goto disable;
0877cb0d 2676
0877cb0d
KB		 2677 dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
2678 if (!dev->bar)
2679 goto disable;
e32efbfc 2680
0e53d180
KB		 2681 if (readl(&dev->bar->csts) == -1) {
2682 result = -ENODEV;
2683 goto unmap;
2684 }
e32efbfc
JA		 2685
2686 /*
2687 * Some devices don't advertse INTx interrupts, pre-enable a single
2688 * MSIX vec for setup. We'll adjust this later.
2689 */
2690 if (!pdev->irq) {
2691 result = pci_enable_msix(pdev, dev->entry, 1);
2692 if (result < 0)
2693 goto unmap;
2694 }
2695
42f61420
KB		 2696 cap = readq(&dev->bar->cap);
2697 dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH);
2698 dev->db_stride = 1 << NVME_CAP_STRIDE(cap);
0877cb0d 2699 dev->dbs = ((void __iomem *)dev->bar) + 4096;
8ffaadf7
JD		 2700 if (readl(&dev->bar->vs) >= NVME_VS(1, 2))
2701 dev->cmb = nvme_map_cmb(dev);
0877cb0d
KB		 2702
2703 return 0;
2704
0e53d180
KB		 2705 unmap:
2706 iounmap(dev->bar);
2707 dev->bar = NULL;
0877cb0d
KB		 2708 disable:
2709 pci_release_regions(pdev);
2710 disable_pci:
2711 pci_disable_device(pdev);
2712 return result;
2713}
2714
2715static void nvme_dev_unmap(struct nvme_dev *dev)
2716{
e75ec752
CH		 2717 struct pci_dev *pdev = to_pci_dev(dev->dev);
2718
2719 if (pdev->msi_enabled)
2720 pci_disable_msi(pdev);
2721 else if (pdev->msix_enabled)
2722 pci_disable_msix(pdev);
0877cb0d
KB		 2723
2724 if (dev->bar) {
2725 iounmap(dev->bar);
2726 dev->bar = NULL;
e75ec752 2727 pci_release_regions(pdev);
0877cb0d
KB		 2728 }
2729
e75ec752
CH		 2730 if (pci_is_enabled(pdev))
2731 pci_disable_device(pdev);
0877cb0d
KB		 2732}
2733
4d115420
KB		 2734struct nvme_delq_ctx {
2735 struct task_struct *waiter;
2736 struct kthread_worker *worker;
2737 atomic_t refcount;
2738};
2739
2740static void nvme_wait_dq(struct nvme_delq_ctx *dq, struct nvme_dev *dev)
2741{
2742 dq->waiter = current;
2743 mb();
2744
2745 for (;;) {
2746 set_current_state(TASK_KILLABLE);
2747 if (!atomic_read(&dq->refcount))
2748 break;
2749 if (!schedule_timeout(ADMIN_TIMEOUT) ||
2750 fatal_signal_pending(current)) {
0fb59cbc
KB		 2751 /*
2752 * Disable the controller first since we can't trust it
2753 * at this point, but leave the admin queue enabled
2754 * until all queue deletion requests are flushed.
2755 * FIXME: This may take a while if there are more h/w
2756 * queues than admin tags.
2757 */
4d115420 2758 set_current_state(TASK_RUNNING);
4d115420 2759 nvme_disable_ctrl(dev, readq(&dev->bar->cap));
0fb59cbc 2760 nvme_clear_queue(dev->queues[0]);
4d115420 2761 flush_kthread_worker(dq->worker);
0fb59cbc 2762 nvme_disable_queue(dev, 0);
4d115420
KB		 2763 return;
2764 }
2765 }
2766 set_current_state(TASK_RUNNING);
2767}
2768
2769static void nvme_put_dq(struct nvme_delq_ctx *dq)
2770{
2771 atomic_dec(&dq->refcount);
2772 if (dq->waiter)
2773 wake_up_process(dq->waiter);
2774}
2775
2776static struct nvme_delq_ctx *nvme_get_dq(struct nvme_delq_ctx *dq)
2777{
2778 atomic_inc(&dq->refcount);
2779 return dq;
2780}
2781
2782static void nvme_del_queue_end(struct nvme_queue *nvmeq)
2783{
2784 struct nvme_delq_ctx *dq = nvmeq->cmdinfo.ctx;
4d115420
KB		 2785 nvme_put_dq(dq);
2786}
2787
2788static int adapter_async_del_queue(struct nvme_queue *nvmeq, u8 opcode,
2789 kthread_work_func_t fn)
2790{
2791 struct nvme_command c;
2792
2793 memset(&c, 0, sizeof(c));
2794 c.delete_queue.opcode = opcode;
2795 c.delete_queue.qid = cpu_to_le16(nvmeq->qid);
2796
2797 init_kthread_work(&nvmeq->cmdinfo.work, fn);
a4aea562
MB		 2798 return nvme_submit_admin_async_cmd(nvmeq->dev, &c, &nvmeq->cmdinfo,
2799 ADMIN_TIMEOUT);
4d115420
KB		 2800}
2801
2802static void nvme_del_cq_work_handler(struct kthread_work *work)
2803{
2804 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2805 cmdinfo.work);
2806 nvme_del_queue_end(nvmeq);
2807}
2808
2809static int nvme_delete_cq(struct nvme_queue *nvmeq)
2810{
2811 return adapter_async_del_queue(nvmeq, nvme_admin_delete_cq,
2812 nvme_del_cq_work_handler);
2813}
2814
2815static void nvme_del_sq_work_handler(struct kthread_work *work)
2816{
2817 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2818 cmdinfo.work);
2819 int status = nvmeq->cmdinfo.status;
2820
2821 if (!status)
2822 status = nvme_delete_cq(nvmeq);
2823 if (status)
2824 nvme_del_queue_end(nvmeq);
2825}
2826
2827static int nvme_delete_sq(struct nvme_queue *nvmeq)
2828{
2829 return adapter_async_del_queue(nvmeq, nvme_admin_delete_sq,
2830 nvme_del_sq_work_handler);
2831}
2832
2833static void nvme_del_queue_start(struct kthread_work *work)
2834{
2835 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2836 cmdinfo.work);
4d115420
KB		 2837 if (nvme_delete_sq(nvmeq))
2838 nvme_del_queue_end(nvmeq);
2839}
2840
2841static void nvme_disable_io_queues(struct nvme_dev *dev)
2842{
2843 int i;
2844 DEFINE_KTHREAD_WORKER_ONSTACK(worker);
2845 struct nvme_delq_ctx dq;
2846 struct task_struct *kworker_task = kthread_run(kthread_worker_fn,
2847 &worker, "nvme%d", dev->instance);
2848
2849 if (IS_ERR(kworker_task)) {
e75ec752 2850 dev_err(dev->dev,
4d115420
KB		 2851 "Failed to create queue del task\n");
2852 for (i = dev->queue_count - 1; i > 0; i--)
2853 nvme_disable_queue(dev, i);
2854 return;
2855 }
2856
2857 dq.waiter = NULL;
2858 atomic_set(&dq.refcount, 0);
2859 dq.worker = &worker;
2860 for (i = dev->queue_count - 1; i > 0; i--) {
a4aea562 2861 struct nvme_queue *nvmeq = dev->queues[i];
4d115420
KB		 2862
2863 if (nvme_suspend_queue(nvmeq))
2864 continue;
2865 nvmeq->cmdinfo.ctx = nvme_get_dq(&dq);
2866 nvmeq->cmdinfo.worker = dq.worker;
2867 init_kthread_work(&nvmeq->cmdinfo.work, nvme_del_queue_start);
2868 queue_kthread_work(dq.worker, &nvmeq->cmdinfo.work);
2869 }
2870 nvme_wait_dq(&dq, dev);
2871 kthread_stop(kworker_task);
2872}
2873
b9afca3e
DM		 2874/*
2875* Remove the node from the device list and check
2876* for whether or not we need to stop the nvme_thread.
2877*/
2878static void nvme_dev_list_remove(struct nvme_dev *dev)
2879{
2880 struct task_struct *tmp = NULL;
2881
2882 spin_lock(&dev_list_lock);
2883 list_del_init(&dev->node);
2884 if (list_empty(&dev_list) && !IS_ERR_OR_NULL(nvme_thread)) {
2885 tmp = nvme_thread;
2886 nvme_thread = NULL;
2887 }
2888 spin_unlock(&dev_list_lock);
2889
2890 if (tmp)
2891 kthread_stop(tmp);
2892}
2893
c9d3bf88
KB		 2894static void nvme_freeze_queues(struct nvme_dev *dev)
2895{
2896 struct nvme_ns *ns;
2897
2898 list_for_each_entry(ns, &dev->namespaces, list) {
2899 blk_mq_freeze_queue_start(ns->queue);
2900
cddcd72b 2901 spin_lock_irq(ns->queue->queue_lock);
c9d3bf88 2902 queue_flag_set(QUEUE_FLAG_STOPPED, ns->queue);
cddcd72b 2903 spin_unlock_irq(ns->queue->queue_lock);
c9d3bf88
KB		 2904
2905 blk_mq_cancel_requeue_work(ns->queue);
2906 blk_mq_stop_hw_queues(ns->queue);
2907 }
2908}
2909
2910static void nvme_unfreeze_queues(struct nvme_dev *dev)
2911{
2912 struct nvme_ns *ns;
2913
2914 list_for_each_entry(ns, &dev->namespaces, list) {
2915 queue_flag_clear_unlocked(QUEUE_FLAG_STOPPED, ns->queue);
2916 blk_mq_unfreeze_queue(ns->queue);
2917 blk_mq_start_stopped_hw_queues(ns->queue, true);
2918 blk_mq_kick_requeue_list(ns->queue);
2919 }
2920}
2921
f0b50732 2922static void nvme_dev_shutdown(struct nvme_dev *dev)
b60503ba 2923{
22404274 2924 int i;
7c1b2450 2925 u32 csts = -1;
22404274 2926
b9afca3e 2927 nvme_dev_list_remove(dev);
1fa6aead 2928
c9d3bf88
KB		 2929 if (dev->bar) {
2930 nvme_freeze_queues(dev);
7c1b2450 2931 csts = readl(&dev->bar->csts);
c9d3bf88 2932 }
7c1b2450 2933 if (csts & NVME_CSTS_CFS || !(csts & NVME_CSTS_RDY)) {
4d115420 2934 for (i = dev->queue_count - 1; i >= 0; i--) {
a4aea562 2935 struct nvme_queue *nvmeq = dev->queues[i];
4d115420 2936 nvme_suspend_queue(nvmeq);
4d115420
KB		 2937 }
2938 } else {
2939 nvme_disable_io_queues(dev);
1894d8f1 2940 nvme_shutdown_ctrl(dev);
4d115420
KB		 2941 nvme_disable_queue(dev, 0);
2942 }
f0b50732 2943 nvme_dev_unmap(dev);
07836e65
KB		 2944
2945 for (i = dev->queue_count - 1; i >= 0; i--)
2946 nvme_clear_queue(dev->queues[i]);
f0b50732
KB		 2947}
2948
2949static void nvme_dev_remove(struct nvme_dev *dev)
2950{
5105aa55 2951 struct nvme_ns *ns, *next;
f0b50732 2952
5105aa55 2953 list_for_each_entry_safe(ns, next, &dev->namespaces, list)
a5768aa8 2954 nvme_ns_remove(ns);
b60503ba
MW		 2955}
2956
091b6092
MW		 2957static int nvme_setup_prp_pools(struct nvme_dev *dev)
2958{
e75ec752 2959 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
091b6092
MW		 2960 PAGE_SIZE, PAGE_SIZE, 0);
2961 if (!dev->prp_page_pool)
2962 return -ENOMEM;
2963
99802a7a 2964 /* Optimisation for I/Os between 4k and 128k */
e75ec752 2965 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
99802a7a
MW		 2966 256, 256, 0);
2967 if (!dev->prp_small_pool) {
2968 dma_pool_destroy(dev->prp_page_pool);
2969 return -ENOMEM;
2970 }
091b6092
MW		 2971 return 0;
2972}
2973
2974static void nvme_release_prp_pools(struct nvme_dev *dev)
2975{
2976 dma_pool_destroy(dev->prp_page_pool);
99802a7a 2977 dma_pool_destroy(dev->prp_small_pool);
091b6092
MW		 2978}
2979
cd58ad7d
QSA		 2980static DEFINE_IDA(nvme_instance_ida);
2981
2982static int nvme_set_instance(struct nvme_dev *dev)
b60503ba 2983{
cd58ad7d
QSA		 2984 int instance, error;
2985
2986 do {
2987 if (!ida_pre_get(&nvme_instance_ida, GFP_KERNEL))
2988 return -ENODEV;
2989
2990 spin_lock(&dev_list_lock);
2991 error = ida_get_new(&nvme_instance_ida, &instance);
2992 spin_unlock(&dev_list_lock);
2993 } while (error == -EAGAIN);
2994
2995 if (error)
2996 return -ENODEV;
2997
2998 dev->instance = instance;
2999 return 0;
b60503ba
MW		 3000}
3001
3002static void nvme_release_instance(struct nvme_dev *dev)
3003{
cd58ad7d
QSA		 3004 spin_lock(&dev_list_lock);
3005 ida_remove(&nvme_instance_ida, dev->instance);
3006 spin_unlock(&dev_list_lock);
b60503ba
MW		 3007}
3008
5e82e952
KB		 3009static void nvme_free_dev(struct kref *kref)
3010{
3011 struct nvme_dev *dev = container_of(kref, struct nvme_dev, kref);
9ac27090 3012
e75ec752 3013 put_device(dev->dev);
b3fffdef 3014 put_device(dev->device);
285dffc9 3015 nvme_release_instance(dev);
4af0e21c
KB		 3016 if (dev->tagset.tags)
3017 blk_mq_free_tag_set(&dev->tagset);
3018 if (dev->admin_q)
3019 blk_put_queue(dev->admin_q);
5e82e952
KB		 3020 kfree(dev->queues);
3021 kfree(dev->entry);
3022 kfree(dev);
3023}
3024
3025static int nvme_dev_open(struct inode *inode, struct file *f)
3026{
b3fffdef
KB		 3027 struct nvme_dev *dev;
3028 int instance = iminor(inode);
3029 int ret = -ENODEV;
3030
3031 spin_lock(&dev_list_lock);
3032 list_for_each_entry(dev, &dev_list, node) {
3033 if (dev->instance == instance) {
2e1d8448
KB		 3034 if (!dev->admin_q) {
3035 ret = -EWOULDBLOCK;
3036 break;
3037 }
b3fffdef
KB		 3038 if (!kref_get_unless_zero(&dev->kref))
3039 break;
3040 f->private_data = dev;
3041 ret = 0;
3042 break;
3043 }
3044 }
3045 spin_unlock(&dev_list_lock);
3046
3047 return ret;
5e82e952
KB		 3048}
3049
3050static int nvme_dev_release(struct inode *inode, struct file *f)
3051{
3052 struct nvme_dev *dev = f->private_data;
3053 kref_put(&dev->kref, nvme_free_dev);
3054 return 0;
3055}
3056
3057static long nvme_dev_ioctl(struct file *f, unsigned int cmd, unsigned long arg)
3058{
3059 struct nvme_dev *dev = f->private_data;
a4aea562
MB		 3060 struct nvme_ns *ns;
3061
5e82e952
KB		 3062 switch (cmd) {
3063 case NVME_IOCTL_ADMIN_CMD:
a4aea562 3064 return nvme_user_cmd(dev, NULL, (void __user *)arg);
7963e521 3065 case NVME_IOCTL_IO_CMD:
a4aea562
MB		 3066 if (list_empty(&dev->namespaces))
3067 return -ENOTTY;
3068 ns = list_first_entry(&dev->namespaces, struct nvme_ns, list);
3069 return nvme_user_cmd(dev, ns, (void __user *)arg);
4cc06521
KB		 3070 case NVME_IOCTL_RESET:
3071 dev_warn(dev->dev, "resetting controller\n");
3072 return nvme_reset(dev);
81f03fed
JD		 3073 case NVME_IOCTL_SUBSYS_RESET:
3074 return nvme_subsys_reset(dev);
5e82e952
KB		 3075 default:
3076 return -ENOTTY;
3077 }
3078}
3079
3080static const struct file_operations nvme_dev_fops = {
3081 .owner = THIS_MODULE,
3082 .open = nvme_dev_open,
3083 .release = nvme_dev_release,
3084 .unlocked_ioctl = nvme_dev_ioctl,
3085 .compat_ioctl = nvme_dev_ioctl,
3086};
3087
3cf519b5 3088static void nvme_probe_work(struct work_struct *work)
f0b50732 3089{
3cf519b5 3090 struct nvme_dev *dev = container_of(work, struct nvme_dev, probe_work);
b9afca3e 3091 bool start_thread = false;
3cf519b5 3092 int result;
f0b50732
KB		 3093
3094 result = nvme_dev_map(dev);
3095 if (result)
3cf519b5 3096 goto out;
f0b50732
KB		 3097
3098 result = nvme_configure_admin_queue(dev);
3099 if (result)
3100 goto unmap;
3101
3102 spin_lock(&dev_list_lock);
b9afca3e
DM		 3103 if (list_empty(&dev_list) && IS_ERR_OR_NULL(nvme_thread)) {
3104 start_thread = true;
3105 nvme_thread = NULL;
3106 }
f0b50732
KB		 3107 list_add(&dev->node, &dev_list);
3108 spin_unlock(&dev_list_lock);
3109
b9afca3e
DM		 3110 if (start_thread) {
3111 nvme_thread = kthread_run(nvme_kthread, NULL, "nvme");
387caa5a 3112 wake_up_all(&nvme_kthread_wait);
b9afca3e
DM		 3113 } else
3114 wait_event_killable(nvme_kthread_wait, nvme_thread);
3115
3116 if (IS_ERR_OR_NULL(nvme_thread)) {
3117 result = nvme_thread ? PTR_ERR(nvme_thread) : -EINTR;
3118 goto disable;
3119 }
a4aea562
MB		 3120
3121 nvme_init_queue(dev->queues[0], 0);
0fb59cbc
KB		 3122 result = nvme_alloc_admin_tags(dev);
3123 if (result)
3124 goto disable;
b9afca3e 3125
f0b50732 3126 result = nvme_setup_io_queues(dev);
badc34d4 3127 if (result)
0fb59cbc 3128 goto free_tags;
f0b50732 3129
1efccc9d 3130 dev->event_limit = 1;
3cf519b5 3131
2659e57b
CH		 3132 /*
3133 * Keep the controller around but remove all namespaces if we don't have
3134 * any working I/O queue.
3135 */
3cf519b5
CH		 3136 if (dev->online_queues < 2) {
3137 dev_warn(dev->dev, "IO queues not created\n");
3cf519b5
CH		 3138 nvme_dev_remove(dev);
3139 } else {
3140 nvme_unfreeze_queues(dev);
3141 nvme_dev_add(dev);
3142 }
3143
3144 return;
f0b50732 3145
0fb59cbc
KB		 3146 free_tags:
3147 nvme_dev_remove_admin(dev);
4af0e21c
KB		 3148 blk_put_queue(dev->admin_q);
3149 dev->admin_q = NULL;
3150 dev->queues[0]->tags = NULL;
f0b50732 3151 disable:
a1a5ef99 3152 nvme_disable_queue(dev, 0);
b9afca3e 3153 nvme_dev_list_remove(dev);
f0b50732
KB		 3154 unmap:
3155 nvme_dev_unmap(dev);
3cf519b5
CH		 3156 out:
3157 if (!work_busy(&dev->reset_work))
3158 nvme_dead_ctrl(dev);
f0b50732
KB		 3159}
3160
9a6b9458
KB		 3161static int nvme_remove_dead_ctrl(void *arg)
3162{
3163 struct nvme_dev *dev = (struct nvme_dev *)arg;
e75ec752 3164 struct pci_dev *pdev = to_pci_dev(dev->dev);
9a6b9458
KB		 3165
3166 if (pci_get_drvdata(pdev))
c81f4975 3167 pci_stop_and_remove_bus_device_locked(pdev);
9a6b9458
KB		 3168 kref_put(&dev->kref, nvme_free_dev);
3169 return 0;
3170}
3171
de3eff2b
KB		 3172static void nvme_dead_ctrl(struct nvme_dev *dev)
3173{
3174 dev_warn(dev->dev, "Device failed to resume\n");
3175 kref_get(&dev->kref);
3176 if (IS_ERR(kthread_run(nvme_remove_dead_ctrl, dev, "nvme%d",
3177 dev->instance))) {
3178 dev_err(dev->dev,
3179 "Failed to start controller remove task\n");
3180 kref_put(&dev->kref, nvme_free_dev);
3181 }
3182}
3183
77b50d9e 3184static void nvme_reset_work(struct work_struct *ws)
9a6b9458 3185{
77b50d9e 3186 struct nvme_dev *dev = container_of(ws, struct nvme_dev, reset_work);
ffe7704d
KB		 3187 bool in_probe = work_busy(&dev->probe_work);
3188
9a6b9458 3189 nvme_dev_shutdown(dev);
ffe7704d
KB		 3190
3191 /* Synchronize with device probe so that work will see failure status
3192 * and exit gracefully without trying to schedule another reset */
3193 flush_work(&dev->probe_work);
3194
3195 /* Fail this device if reset occured during probe to avoid
3196 * infinite initialization loops. */
3197 if (in_probe) {
de3eff2b 3198 nvme_dead_ctrl(dev);
ffe7704d 3199 return;
9a6b9458 3200 }
ffe7704d
KB		 3201 /* Schedule device resume asynchronously so the reset work is available
3202 * to cleanup errors that may occur during reinitialization */
3203 schedule_work(&dev->probe_work);
9a6b9458
KB		 3204}
3205
90667892 3206static int __nvme_reset(struct nvme_dev *dev)
9ca97374 3207{
90667892
CH		 3208 if (work_pending(&dev->reset_work))
3209 return -EBUSY;
3210 list_del_init(&dev->node);
3211 queue_work(nvme_workq, &dev->reset_work);
3212 return 0;
9ca97374
TH		 3213}
3214
4cc06521
KB		 3215static int nvme_reset(struct nvme_dev *dev)
3216{
90667892 3217 int ret;
4cc06521
KB		 3218
3219 if (!dev->admin_q || blk_queue_dying(dev->admin_q))
3220 return -ENODEV;
3221
3222 spin_lock(&dev_list_lock);
90667892 3223 ret = __nvme_reset(dev);
4cc06521
KB		 3224 spin_unlock(&dev_list_lock);
3225
3226 if (!ret) {
3227 flush_work(&dev->reset_work);
ffe7704d 3228 flush_work(&dev->probe_work);
4cc06521
KB		 3229 return 0;
3230 }
3231
3232 return ret;
3233}
3234
3235static ssize_t nvme_sysfs_reset(struct device *dev,
3236 struct device_attribute *attr, const char *buf,
3237 size_t count)
3238{
3239 struct nvme_dev *ndev = dev_get_drvdata(dev);
3240 int ret;
3241
3242 ret = nvme_reset(ndev);
3243 if (ret < 0)
3244 return ret;
3245
3246 return count;
3247}
3248static DEVICE_ATTR(reset_controller, S_IWUSR, NULL, nvme_sysfs_reset);
3249
8d85fce7 3250static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
b60503ba 3251{
a4aea562 3252 int node, result = -ENOMEM;
b60503ba
MW		 3253 struct nvme_dev *dev;
3254
a4aea562
MB		 3255 node = dev_to_node(&pdev->dev);
3256 if (node == NUMA_NO_NODE)
3257 set_dev_node(&pdev->dev, 0);
3258
3259 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
b60503ba
MW		 3260 if (!dev)
3261 return -ENOMEM;
a4aea562
MB		 3262 dev->entry = kzalloc_node(num_possible_cpus() * sizeof(*dev->entry),
3263 GFP_KERNEL, node);
b60503ba
MW		 3264 if (!dev->entry)
3265 goto free;
a4aea562
MB		 3266 dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *),
3267 GFP_KERNEL, node);
b60503ba
MW		 3268 if (!dev->queues)
3269 goto free;
3270
3271 INIT_LIST_HEAD(&dev->namespaces);
77b50d9e 3272 INIT_WORK(&dev->reset_work, nvme_reset_work);
e75ec752 3273 dev->dev = get_device(&pdev->dev);
9a6b9458 3274 pci_set_drvdata(pdev, dev);
cd58ad7d
QSA		 3275 result = nvme_set_instance(dev);
3276 if (result)
a96d4f5c 3277 goto put_pci;
b60503ba 3278
091b6092
MW		 3279 result = nvme_setup_prp_pools(dev);
3280 if (result)
0877cb0d 3281 goto release;
091b6092 3282
fb35e914 3283 kref_init(&dev->kref);
b3fffdef
KB		 3284 dev->device = device_create(nvme_class, &pdev->dev,
3285 MKDEV(nvme_char_major, dev->instance),
3286 dev, "nvme%d", dev->instance);
3287 if (IS_ERR(dev->device)) {
3288 result = PTR_ERR(dev->device);
2e1d8448 3289 goto release_pools;
b3fffdef
KB		 3290 }
3291 get_device(dev->device);
4cc06521
KB		 3292 dev_set_drvdata(dev->device, dev);
3293
3294 result = device_create_file(dev->device, &dev_attr_reset_controller);
3295 if (result)
3296 goto put_dev;
740216fc 3297
e6e96d73 3298 INIT_LIST_HEAD(&dev->node);
a5768aa8 3299 INIT_WORK(&dev->scan_work, nvme_dev_scan);
3cf519b5 3300 INIT_WORK(&dev->probe_work, nvme_probe_work);
2e1d8448 3301 schedule_work(&dev->probe_work);
b60503ba
MW		 3302 return 0;
3303
4cc06521
KB		 3304 put_dev:
3305 device_destroy(nvme_class, MKDEV(nvme_char_major, dev->instance));
3306 put_device(dev->device);
0877cb0d 3307 release_pools:
091b6092 3308 nvme_release_prp_pools(dev);
0877cb0d
KB		 3309 release:
3310 nvme_release_instance(dev);
a96d4f5c 3311 put_pci:
e75ec752 3312 put_device(dev->dev);
b60503ba
MW		 3313 free:
3314 kfree(dev->queues);
3315 kfree(dev->entry);
3316 kfree(dev);
3317 return result;
3318}
3319
f0d54a54
KB		 3320static void nvme_reset_notify(struct pci_dev *pdev, bool prepare)
3321{
a6739479 3322 struct nvme_dev *dev = pci_get_drvdata(pdev);
f0d54a54 3323
a6739479
KB		 3324 if (prepare)
3325 nvme_dev_shutdown(dev);
3326 else
0a7385ad 3327 schedule_work(&dev->probe_work);
f0d54a54
KB		 3328}
3329
09ece142
KB		 3330static void nvme_shutdown(struct pci_dev *pdev)
3331{
3332 struct nvme_dev *dev = pci_get_drvdata(pdev);
3333 nvme_dev_shutdown(dev);
3334}
3335
8d85fce7 3336static void nvme_remove(struct pci_dev *pdev)
b60503ba
MW		 3337{
3338 struct nvme_dev *dev = pci_get_drvdata(pdev);
9a6b9458
KB		 3339
3340 spin_lock(&dev_list_lock);
3341 list_del_init(&dev->node);
3342 spin_unlock(&dev_list_lock);
3343
3344 pci_set_drvdata(pdev, NULL);
2e1d8448 3345 flush_work(&dev->probe_work);
9a6b9458 3346 flush_work(&dev->reset_work);
a5768aa8 3347 flush_work(&dev->scan_work);
4cc06521 3348 device_remove_file(dev->device, &dev_attr_reset_controller);
c9d3bf88 3349 nvme_dev_remove(dev);
3399a3f7 3350 nvme_dev_shutdown(dev);
a4aea562 3351 nvme_dev_remove_admin(dev);
b3fffdef 3352 device_destroy(nvme_class, MKDEV(nvme_char_major, dev->instance));
a1a5ef99 3353 nvme_free_queues(dev, 0);
8ffaadf7 3354 nvme_release_cmb(dev);
9a6b9458 3355 nvme_release_prp_pools(dev);
5e82e952 3356 kref_put(&dev->kref, nvme_free_dev);
b60503ba
MW		 3357}
3358
3359/* These functions are yet to be implemented */
3360#define nvme_error_detected NULL
3361#define nvme_dump_registers NULL
3362#define nvme_link_reset NULL
3363#define nvme_slot_reset NULL
3364#define nvme_error_resume NULL
cd638946 3365
671a6018 3366#ifdef CONFIG_PM_SLEEP
cd638946
KB		 3367static int nvme_suspend(struct device *dev)
3368{
3369 struct pci_dev *pdev = to_pci_dev(dev);
3370 struct nvme_dev *ndev = pci_get_drvdata(pdev);
3371
3372 nvme_dev_shutdown(ndev);
3373 return 0;
3374}
3375
3376static int nvme_resume(struct device *dev)
3377{
3378 struct pci_dev *pdev = to_pci_dev(dev);
3379 struct nvme_dev *ndev = pci_get_drvdata(pdev);
cd638946 3380
0a7385ad 3381 schedule_work(&ndev->probe_work);
9a6b9458 3382 return 0;
cd638946 3383}
671a6018 3384#endif
cd638946
KB		 3385
3386static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
b60503ba 3387
1d352035 3388static const struct pci_error_handlers nvme_err_handler = {
b60503ba
MW		 3389 .error_detected = nvme_error_detected,
3390 .mmio_enabled = nvme_dump_registers,
3391 .link_reset = nvme_link_reset,
3392 .slot_reset = nvme_slot_reset,
3393 .resume = nvme_error_resume,
f0d54a54 3394 .reset_notify = nvme_reset_notify,
b60503ba
MW		 3395};
3396
3397/* Move to pci_ids.h later */
3398#define PCI_CLASS_STORAGE_EXPRESS 0x010802
3399
6eb0d698 3400static const struct pci_device_id nvme_id_table[] = {
b60503ba
MW		 3401 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
3402 { 0, }
3403};
3404MODULE_DEVICE_TABLE(pci, nvme_id_table);
3405
3406static struct pci_driver nvme_driver = {
3407 .name = "nvme",
3408 .id_table = nvme_id_table,
3409 .probe = nvme_probe,
8d85fce7 3410 .remove = nvme_remove,
09ece142 3411 .shutdown = nvme_shutdown,
cd638946
KB		 3412 .driver = {
3413 .pm = &nvme_dev_pm_ops,
3414 },
b60503ba
MW		 3415 .err_handler = &nvme_err_handler,
3416};
3417
3418static int __init nvme_init(void)
3419{
0ac13140 3420 int result;
1fa6aead 3421
b9afca3e 3422 init_waitqueue_head(&nvme_kthread_wait);
b60503ba 3423
9a6b9458
KB		 3424 nvme_workq = create_singlethread_workqueue("nvme");
3425 if (!nvme_workq)
b9afca3e 3426 return -ENOMEM;
9a6b9458 3427
5c42ea16
KB		 3428 result = register_blkdev(nvme_major, "nvme");
3429 if (result < 0)
9a6b9458 3430 goto kill_workq;
5c42ea16 3431 else if (result > 0)
0ac13140 3432 nvme_major = result;
b60503ba 3433
b3fffdef
KB		 3434 result = __register_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme",
3435 &nvme_dev_fops);
3436 if (result < 0)
3437 goto unregister_blkdev;
3438 else if (result > 0)
3439 nvme_char_major = result;
3440
3441 nvme_class = class_create(THIS_MODULE, "nvme");
c727040b
AK		 3442 if (IS_ERR(nvme_class)) {
3443 result = PTR_ERR(nvme_class);
b3fffdef 3444 goto unregister_chrdev;
c727040b 3445 }
b3fffdef 3446
f3db22fe
KB		 3447 result = pci_register_driver(&nvme_driver);
3448 if (result)
b3fffdef 3449 goto destroy_class;
1fa6aead 3450 return 0;
b60503ba 3451
b3fffdef
KB		 3452 destroy_class:
3453 class_destroy(nvme_class);
3454 unregister_chrdev:
3455 __unregister_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme");
1fa6aead 3456 unregister_blkdev:
b60503ba 3457 unregister_blkdev(nvme_major, "nvme");
9a6b9458
KB		 3458 kill_workq:
3459 destroy_workqueue(nvme_workq);
b60503ba
MW		 3460 return result;
3461}
3462
3463static void __exit nvme_exit(void)
3464{
3465 pci_unregister_driver(&nvme_driver);
3466 unregister_blkdev(nvme_major, "nvme");
9a6b9458 3467 destroy_workqueue(nvme_workq);
b3fffdef
KB		 3468 class_destroy(nvme_class);
3469 __unregister_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme");
b9afca3e 3470 BUG_ON(nvme_thread && !IS_ERR(nvme_thread));
21bd78bc 3471 _nvme_check_size();
b60503ba
MW		 3472}
3473
3474MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3475MODULE_LICENSE("GPL");
c78b4713 3476MODULE_VERSION("1.0");
b60503ba
MW		 3477module_init(nvme_init);
3478module_exit(nvme_exit);
Linux 6.x block layer and io_uring tree(s)