projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
block: mark flush request as IDLE when it is really finished
[linux-2.6-block.git] / drivers / nvme / host / pci.c
CommitLineData
5f37396d 1// SPDX-License-Identifier: GPL-2.0
b60503ba
MW		 2/*
3 * NVM Express device driver
6eb0d698 4 * Copyright (c) 2011-2014, Intel Corporation.
b60503ba
MW		 5 */
6
df4f9bc4 7#include <linux/acpi.h>
a0a3408e 8#include <linux/aer.h>
18119775 9#include <linux/async.h>
b60503ba 10#include <linux/blkdev.h>
a4aea562 11#include <linux/blk-mq.h>
dca51e78 12#include <linux/blk-mq-pci.h>
ff5350a8 13#include <linux/dmi.h>
b60503ba
MW		 14#include <linux/init.h>
15#include <linux/interrupt.h>
16#include <linux/io.h>
b60503ba
MW		 17#include <linux/mm.h>
18#include <linux/module.h>
77bf25ea 19#include <linux/mutex.h>
d0877473 20#include <linux/once.h>
b60503ba 21#include <linux/pci.h>
d916b1be 22#include <linux/suspend.h>
e1e5e564 23#include <linux/t10-pi.h>
b60503ba 24#include <linux/types.h>
2f8e2c87 25#include <linux/io-64-nonatomic-lo-hi.h>
a98e58e5 26#include <linux/sed-opal.h>
0f238ff5 27#include <linux/pci-p2pdma.h>
797a796a 28
604c01d5 29#include "trace.h"
f11bb3e2
CH		 30#include "nvme.h"
31
c1e0cc7e 32#define SQ_SIZE(q) ((q)->q_depth << (q)->sqes)
8a1d09a6 33#define CQ_SIZE(q) ((q)->q_depth * sizeof(struct nvme_completion))
c965809c 34
a7a7cbe3 35#define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc))
9d43cf64 36
943e942e
JA		 37/*
38 * These can be higher, but we need to ensure that any command doesn't
39 * require an sg allocation that needs more than a page of data.
40 */
41#define NVME_MAX_KB_SZ 4096
42#define NVME_MAX_SEGS 127
43
58ffacb5
MW		 44static int use_threaded_interrupts;
45module_param(use_threaded_interrupts, int, 0);
46
8ffaadf7 47static bool use_cmb_sqes = true;
69f4eb9f 48module_param(use_cmb_sqes, bool, 0444);
8ffaadf7
JD		 49MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
50
87ad72a5
CH		 51static unsigned int max_host_mem_size_mb = 128;
52module_param(max_host_mem_size_mb, uint, 0444);
53MODULE_PARM_DESC(max_host_mem_size_mb,
54 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
1fa6aead 55
a7a7cbe3
CK		 56static unsigned int sgl_threshold = SZ_32K;
57module_param(sgl_threshold, uint, 0644);
58MODULE_PARM_DESC(sgl_threshold,
59 "Use SGLs when average request segment size is larger or equal to "
60 "this size. Use 0 to disable SGLs.");
61
b27c1e68 62static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
63static const struct kernel_param_ops io_queue_depth_ops = {
64 .set = io_queue_depth_set,
61f3b896 65 .get = param_get_uint,
b27c1e68 66};
67
61f3b896 68static unsigned int io_queue_depth = 1024;
b27c1e68 69module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
70MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2");
71
9c9e76d5
WZ		 72static int io_queue_count_set(const char *val, const struct kernel_param *kp)
73{
74 unsigned int n;
75 int ret;
76
77 ret = kstrtouint(val, 10, &n);
78 if (ret != 0 || n > num_possible_cpus())
79 return -EINVAL;
80 return param_set_uint(val, kp);
81}
82
83static const struct kernel_param_ops io_queue_count_ops = {
84 .set = io_queue_count_set,
85 .get = param_get_uint,
86};
87
3f68baf7 88static unsigned int write_queues;
9c9e76d5 89module_param_cb(write_queues, &io_queue_count_ops, &write_queues, 0644);
3b6592f7
JA		 90MODULE_PARM_DESC(write_queues,
91 "Number of queues to use for writes. If not set, reads and writes "
92 "will share a queue set.");
93
3f68baf7 94static unsigned int poll_queues;
9c9e76d5 95module_param_cb(poll_queues, &io_queue_count_ops, &poll_queues, 0644);
4b04cc6a
JA		 96MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO.");
97
df4f9bc4
DB		 98static bool noacpi;
99module_param(noacpi, bool, 0444);
100MODULE_PARM_DESC(noacpi, "disable acpi bios quirks");
101
1c63dc66
CH		 102struct nvme_dev;
103struct nvme_queue;
b3fffdef 104
a5cdb68c 105static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
8fae268b 106static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode);
d4b4ff8e 107
1c63dc66
CH		 108/*
109 * Represents an NVM Express device. Each nvme_dev is a PCI function.
110 */
111struct nvme_dev {
147b27e4 112 struct nvme_queue *queues;
1c63dc66
CH		 113 struct blk_mq_tag_set tagset;
114 struct blk_mq_tag_set admin_tagset;
115 u32 __iomem *dbs;
116 struct device *dev;
117 struct dma_pool *prp_page_pool;
118 struct dma_pool *prp_small_pool;
1c63dc66
CH		 119 unsigned online_queues;
120 unsigned max_qid;
e20ba6e1 121 unsigned io_queues[HCTX_MAX_TYPES];
22b55601 122 unsigned int num_vecs;
7442ddce 123 u32 q_depth;
c1e0cc7e 124 int io_sqes;
1c63dc66 125 u32 db_stride;
1c63dc66 126 void __iomem *bar;
97f6ef64 127 unsigned long bar_mapped_size;
5c8809e6 128 struct work_struct remove_work;
77bf25ea 129 struct mutex shutdown_lock;
1c63dc66 130 bool subsystem;
1c63dc66 131 u64 cmb_size;
0f238ff5 132 bool cmb_use_sqes;
1c63dc66 133 u32 cmbsz;
202021c1 134 u32 cmbloc;
1c63dc66 135 struct nvme_ctrl ctrl;
d916b1be 136 u32 last_ps;
87ad72a5 137
943e942e
JA		 138 mempool_t *iod_mempool;
139
87ad72a5 140 /* shadow doorbell buffer support: */
f9f38e33
HK		 141 u32 *dbbuf_dbs;
142 dma_addr_t dbbuf_dbs_dma_addr;
143 u32 *dbbuf_eis;
144 dma_addr_t dbbuf_eis_dma_addr;
87ad72a5
CH		 145
146 /* host memory buffer support: */
147 u64 host_mem_size;
148 u32 nr_host_mem_descs;
4033f35d 149 dma_addr_t host_mem_descs_dma;
87ad72a5
CH		 150 struct nvme_host_mem_buf_desc *host_mem_descs;
151 void **host_mem_desc_bufs;
2a5bcfdd
WZ		 152 unsigned int nr_allocated_queues;
153 unsigned int nr_write_queues;
154 unsigned int nr_poll_queues;
4d115420 155};
1fa6aead 156
b27c1e68 157static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
158{
61f3b896 159 int ret;
7442ddce 160 u32 n;
b27c1e68 161
7442ddce 162 ret = kstrtou32(val, 10, &n);
b27c1e68 163 if (ret != 0 || n < 2)
164 return -EINVAL;
165
7442ddce 166 return param_set_uint(val, kp);
b27c1e68 167}
168
f9f38e33
HK		 169static inline unsigned int sq_idx(unsigned int qid, u32 stride)
170{
171 return qid * 2 * stride;
172}
173
174static inline unsigned int cq_idx(unsigned int qid, u32 stride)
175{
176 return (qid * 2 + 1) * stride;
177}
178
1c63dc66
CH		 179static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
180{
181 return container_of(ctrl, struct nvme_dev, ctrl);
182}
183
b60503ba
MW		 184/*
185 * An NVM Express queue. Each device has at least two (one for admin
186 * commands and one for I/O commands).
187 */
188struct nvme_queue {
091b6092 189 struct nvme_dev *dev;
1ab0cd69 190 spinlock_t sq_lock;
c1e0cc7e 191 void *sq_cmds;
3a7afd8e
CH		 192 /* only used for poll queues: */
193 spinlock_t cq_poll_lock ____cacheline_aligned_in_smp;
74943d45 194 struct nvme_completion *cqes;
b60503ba
MW		 195 dma_addr_t sq_dma_addr;
196 dma_addr_t cq_dma_addr;
b60503ba 197 u32 __iomem *q_db;
7442ddce 198 u32 q_depth;
7c349dde 199 u16 cq_vector;
b60503ba 200 u16 sq_tail;
38210800 201 u16 last_sq_tail;
b60503ba 202 u16 cq_head;
c30341dc 203 u16 qid;
e9539f47 204 u8 cq_phase;
c1e0cc7e 205 u8 sqes;
4e224106
CH		 206 unsigned long flags;
207#define NVMEQ_ENABLED 0
63223078 208#define NVMEQ_SQ_CMB 1
d1ed6aa1 209#define NVMEQ_DELETE_ERROR 2
7c349dde 210#define NVMEQ_POLLED 3
f9f38e33
HK		 211 u32 *dbbuf_sq_db;
212 u32 *dbbuf_cq_db;
213 u32 *dbbuf_sq_ei;
214 u32 *dbbuf_cq_ei;
d1ed6aa1 215 struct completion delete_done;
b60503ba
MW		 216};
217
71bd150c 218/*
9b048119
CH		 219 * The nvme_iod describes the data in an I/O.
220 *
221 * The sg pointer contains the list of PRP/SGL chunk allocations in addition
222 * to the actual struct scatterlist.
71bd150c
CH		 223 */
224struct nvme_iod {
d49187e9 225 struct nvme_request req;
f4800d6d 226 struct nvme_queue *nvmeq;
a7a7cbe3 227 bool use_sgl;
f4800d6d 228 int aborted;
71bd150c 229 int npages; /* In the PRP list. 0 means small pool in use */
71bd150c 230 int nents; /* Used in scatterlist */
71bd150c 231 dma_addr_t first_dma;
dff824b2 232 unsigned int dma_len; /* length of single DMA segment mapping */
783b94bd 233 dma_addr_t meta_dma;
f4800d6d 234 struct scatterlist *sg;
b60503ba
MW		 235};
236
2a5bcfdd 237static inline unsigned int nvme_dbbuf_size(struct nvme_dev *dev)
3b6592f7 238{
2a5bcfdd 239 return dev->nr_allocated_queues * 8 * dev->db_stride;
f9f38e33
HK		 240}
241
242static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
243{
2a5bcfdd 244 unsigned int mem_size = nvme_dbbuf_size(dev);
f9f38e33
HK		 245
246 if (dev->dbbuf_dbs)
247 return 0;
248
249 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
250 &dev->dbbuf_dbs_dma_addr,
251 GFP_KERNEL);
252 if (!dev->dbbuf_dbs)
253 return -ENOMEM;
254 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
255 &dev->dbbuf_eis_dma_addr,
256 GFP_KERNEL);
257 if (!dev->dbbuf_eis) {
258 dma_free_coherent(dev->dev, mem_size,
259 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
260 dev->dbbuf_dbs = NULL;
261 return -ENOMEM;
262 }
263
264 return 0;
265}
266
267static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
268{
2a5bcfdd 269 unsigned int mem_size = nvme_dbbuf_size(dev);
f9f38e33
HK		 270
271 if (dev->dbbuf_dbs) {
272 dma_free_coherent(dev->dev, mem_size,
273 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
274 dev->dbbuf_dbs = NULL;
275 }
276 if (dev->dbbuf_eis) {
277 dma_free_coherent(dev->dev, mem_size,
278 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
279 dev->dbbuf_eis = NULL;
280 }
281}
282
283static void nvme_dbbuf_init(struct nvme_dev *dev,
284 struct nvme_queue *nvmeq, int qid)
285{
286 if (!dev->dbbuf_dbs || !qid)
287 return;
288
289 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
290 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
291 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
292 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
293}
294
295static void nvme_dbbuf_set(struct nvme_dev *dev)
296{
297 struct nvme_command c;
298
299 if (!dev->dbbuf_dbs)
300 return;
301
302 memset(&c, 0, sizeof(c));
303 c.dbbuf.opcode = nvme_admin_dbbuf;
304 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
305 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
306
307 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
9bdcfb10 308 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
f9f38e33
HK		 309 /* Free memory and continue on */
310 nvme_dbbuf_dma_free(dev);
311 }
312}
313
314static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
315{
316 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
317}
318
319/* Update dbbuf and return true if an MMIO is required */
320static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
321 volatile u32 *dbbuf_ei)
322{
323 if (dbbuf_db) {
324 u16 old_value;
325
326 /*
327 * Ensure that the queue is written before updating
328 * the doorbell in memory
329 */
330 wmb();
331
332 old_value = *dbbuf_db;
333 *dbbuf_db = value;
334
f1ed3df2
MW		 335 /*
336 * Ensure that the doorbell is updated before reading the event
337 * index from memory. The controller needs to provide similar
338 * ordering to ensure the envent index is updated before reading
339 * the doorbell.
340 */
341 mb();
342
f9f38e33
HK		 343 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value))
344 return false;
345 }
346
347 return true;
b60503ba
MW		 348}
349
ac3dd5bd
JA		 350/*
351 * Will slightly overestimate the number of pages needed. This is OK
352 * as it only leads to a small amount of wasted memory for the lifetime of
353 * the I/O.
354 */
b13c6393 355static int nvme_pci_npages_prp(void)
ac3dd5bd 356{
b13c6393 357 unsigned nprps = DIV_ROUND_UP(NVME_MAX_KB_SZ + NVME_CTRL_PAGE_SIZE,
6c3c05b0 358 NVME_CTRL_PAGE_SIZE);
ac3dd5bd
JA		 359 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
360}
361
a7a7cbe3
CK		 362/*
363 * Calculates the number of pages needed for the SGL segments. For example a 4k
364 * page can accommodate 256 SGL descriptors.
365 */
b13c6393 366static int nvme_pci_npages_sgl(void)
ac3dd5bd 367{
b13c6393
CK		 368 return DIV_ROUND_UP(NVME_MAX_SEGS * sizeof(struct nvme_sgl_desc),
369 PAGE_SIZE);
f4800d6d 370}
ac3dd5bd 371
b13c6393 372static size_t nvme_pci_iod_alloc_size(void)
f4800d6d 373{
b13c6393 374 size_t npages = max(nvme_pci_npages_prp(), nvme_pci_npages_sgl());
a7a7cbe3 375
b13c6393
CK		 376 return sizeof(__le64 *) * npages +
377 sizeof(struct scatterlist) * NVME_MAX_SEGS;
f4800d6d 378}
ac3dd5bd 379
a4aea562
MB		 380static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
381 unsigned int hctx_idx)
e85248e5 382{
a4aea562 383 struct nvme_dev *dev = data;
147b27e4 384 struct nvme_queue *nvmeq = &dev->queues[0];
a4aea562 385
42483228
KB		 386 WARN_ON(hctx_idx != 0);
387 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
42483228 388
a4aea562
MB		 389 hctx->driver_data = nvmeq;
390 return 0;
e85248e5
MW		 391}
392
a4aea562
MB		 393static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
394 unsigned int hctx_idx)
b60503ba 395{
a4aea562 396 struct nvme_dev *dev = data;
147b27e4 397 struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
a4aea562 398
42483228 399 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
a4aea562
MB		 400 hctx->driver_data = nvmeq;
401 return 0;
b60503ba
MW		 402}
403
d6296d39
CH		 404static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req,
405 unsigned int hctx_idx, unsigned int numa_node)
b60503ba 406{
d6296d39 407 struct nvme_dev *dev = set->driver_data;
f4800d6d 408 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
0350815a 409 int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0;
147b27e4 410 struct nvme_queue *nvmeq = &dev->queues[queue_idx];
a4aea562
MB		 411
412 BUG_ON(!nvmeq);
f4800d6d 413 iod->nvmeq = nvmeq;
59e29ce6
SG		 414
415 nvme_req(req)->ctrl = &dev->ctrl;
a4aea562
MB		 416 return 0;
417}
418
3b6592f7
JA		 419static int queue_irq_offset(struct nvme_dev *dev)
420{
421 /* if we have more than 1 vec, admin queue offsets us by 1 */
422 if (dev->num_vecs > 1)
423 return 1;
424
425 return 0;
426}
427
dca51e78
CH		 428static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
429{
430 struct nvme_dev *dev = set->driver_data;
3b6592f7
JA		 431 int i, qoff, offset;
432
433 offset = queue_irq_offset(dev);
434 for (i = 0, qoff = 0; i < set->nr_maps; i++) {
435 struct blk_mq_queue_map *map = &set->map[i];
436
437 map->nr_queues = dev->io_queues[i];
438 if (!map->nr_queues) {
e20ba6e1 439 BUG_ON(i == HCTX_TYPE_DEFAULT);
7e849dd9 440 continue;
3b6592f7
JA		 441 }
442
4b04cc6a
JA		 443 /*
444 * The poll queue(s) doesn't have an IRQ (and hence IRQ
445 * affinity), so use the regular blk-mq cpu mapping
446 */
3b6592f7 447 map->queue_offset = qoff;
cb9e0e50 448 if (i != HCTX_TYPE_POLL && offset)
4b04cc6a
JA		 449 blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset);
450 else
451 blk_mq_map_queues(map);
3b6592f7
JA		 452 qoff += map->nr_queues;
453 offset += map->nr_queues;
454 }
455
456 return 0;
dca51e78
CH		 457}
458
38210800
KB		 459/*
460 * Write sq tail if we are asked to, or if the next command would wrap.
461 */
462static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq)
04f3eafd 463{
38210800
KB		 464 if (!write_sq) {
465 u16 next_tail = nvmeq->sq_tail + 1;
466
467 if (next_tail == nvmeq->q_depth)
468 next_tail = 0;
469 if (next_tail != nvmeq->last_sq_tail)
470 return;
471 }
472
04f3eafd
JA		 473 if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail,
474 nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei))
475 writel(nvmeq->sq_tail, nvmeq->q_db);
38210800 476 nvmeq->last_sq_tail = nvmeq->sq_tail;
04f3eafd
JA		 477}
478
b60503ba 479/**
90ea5ca4 480 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
b60503ba
MW		 481 * @nvmeq: The queue to use
482 * @cmd: The command to send
04f3eafd 483 * @write_sq: whether to write to the SQ doorbell
b60503ba 484 */
04f3eafd
JA		 485static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd,
486 bool write_sq)
b60503ba 487{
90ea5ca4 488 spin_lock(&nvmeq->sq_lock);
c1e0cc7e
BH		 489 memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes),
490 cmd, sizeof(*cmd));
90ea5ca4
CH		 491 if (++nvmeq->sq_tail == nvmeq->q_depth)
492 nvmeq->sq_tail = 0;
38210800 493 nvme_write_sq_db(nvmeq, write_sq);
04f3eafd
JA		 494 spin_unlock(&nvmeq->sq_lock);
495}
496
497static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx)
498{
499 struct nvme_queue *nvmeq = hctx->driver_data;
500
501 spin_lock(&nvmeq->sq_lock);
38210800
KB		 502 if (nvmeq->sq_tail != nvmeq->last_sq_tail)
503 nvme_write_sq_db(nvmeq, true);
90ea5ca4 504 spin_unlock(&nvmeq->sq_lock);
b60503ba
MW		 505}
506
a7a7cbe3 507static void **nvme_pci_iod_list(struct request *req)
b60503ba 508{
f4800d6d 509 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3 510 return (void **)(iod->sg + blk_rq_nr_phys_segments(req));
b60503ba
MW		 511}
512
955b1b5a
MI		 513static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req)
514{
515 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
20469a37 516 int nseg = blk_rq_nr_phys_segments(req);
955b1b5a
MI		 517 unsigned int avg_seg_size;
518
20469a37 519 avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
955b1b5a
MI		 520
521 if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1))))
522 return false;
523 if (!iod->nvmeq->qid)
524 return false;
525 if (!sgl_threshold || avg_seg_size < sgl_threshold)
526 return false;
527 return true;
528}
529
7fe07d14 530static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
b60503ba 531{
f4800d6d 532 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
6c3c05b0 533 const int last_prp = NVME_CTRL_PAGE_SIZE / sizeof(__le64) - 1;
a7a7cbe3 534 dma_addr_t dma_addr = iod->first_dma, next_dma_addr;
eca18b23 535 int i;
eca18b23 536
dff824b2 537 if (iod->dma_len) {
f2fa006f
IR		 538 dma_unmap_page(dev->dev, dma_addr, iod->dma_len,
539 rq_dma_dir(req));
dff824b2 540 return;
7fe07d14
CH		 541 }
542
dff824b2
CH		 543 WARN_ON_ONCE(!iod->nents);
544
7f73eac3
LG		 545 if (is_pci_p2pdma_page(sg_page(iod->sg)))
546 pci_p2pdma_unmap_sg(dev->dev, iod->sg, iod->nents,
547 rq_dma_dir(req));
548 else
dff824b2
CH		 549 dma_unmap_sg(dev->dev, iod->sg, iod->nents, rq_dma_dir(req));
550
551
eca18b23 552 if (iod->npages == 0)
a7a7cbe3
CK		 553 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0],
554 dma_addr);
555
eca18b23 556 for (i = 0; i < iod->npages; i++) {
a7a7cbe3
CK		 557 void *addr = nvme_pci_iod_list(req)[i];
558
559 if (iod->use_sgl) {
560 struct nvme_sgl_desc *sg_list = addr;
561
562 next_dma_addr =
563 le64_to_cpu((sg_list[SGES_PER_PAGE - 1]).addr);
564 } else {
565 __le64 *prp_list = addr;
566
567 next_dma_addr = le64_to_cpu(prp_list[last_prp]);
568 }
569
570 dma_pool_free(dev->prp_page_pool, addr, dma_addr);
571 dma_addr = next_dma_addr;
eca18b23 572 }
ac3dd5bd 573
d43f1ccf 574 mempool_free(iod->sg, dev->iod_mempool);
b4ff9c8d
KB		 575}
576
d0877473
KB		 577static void nvme_print_sgl(struct scatterlist *sgl, int nents)
578{
579 int i;
580 struct scatterlist *sg;
581
582 for_each_sg(sgl, sg, nents, i) {
583 dma_addr_t phys = sg_phys(sg);
584 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
585 "dma_address:%pad dma_length:%d\n",
586 i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
587 sg_dma_len(sg));
588 }
589}
590
a7a7cbe3
CK		 591static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
592 struct request *req, struct nvme_rw_command *cmnd)
ff22b54f 593{
f4800d6d 594 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
99802a7a 595 struct dma_pool *pool;
b131c61d 596 int length = blk_rq_payload_bytes(req);
eca18b23 597 struct scatterlist *sg = iod->sg;
ff22b54f
MW		 598 int dma_len = sg_dma_len(sg);
599 u64 dma_addr = sg_dma_address(sg);
6c3c05b0 600 int offset = dma_addr & (NVME_CTRL_PAGE_SIZE - 1);
e025344c 601 __le64 *prp_list;
a7a7cbe3 602 void **list = nvme_pci_iod_list(req);
e025344c 603 dma_addr_t prp_dma;
eca18b23 604 int nprps, i;
ff22b54f 605
6c3c05b0 606 length -= (NVME_CTRL_PAGE_SIZE - offset);
5228b328
JS		 607 if (length <= 0) {
608 iod->first_dma = 0;
a7a7cbe3 609 goto done;
5228b328 610 }
ff22b54f 611
6c3c05b0 612 dma_len -= (NVME_CTRL_PAGE_SIZE - offset);
ff22b54f 613 if (dma_len) {
6c3c05b0 614 dma_addr += (NVME_CTRL_PAGE_SIZE - offset);
ff22b54f
MW		 615 } else {
616 sg = sg_next(sg);
617 dma_addr = sg_dma_address(sg);
618 dma_len = sg_dma_len(sg);
619 }
620
6c3c05b0 621 if (length <= NVME_CTRL_PAGE_SIZE) {
edd10d33 622 iod->first_dma = dma_addr;
a7a7cbe3 623 goto done;
e025344c
SMM		 624 }
625
6c3c05b0 626 nprps = DIV_ROUND_UP(length, NVME_CTRL_PAGE_SIZE);
99802a7a
MW		 627 if (nprps <= (256 / 8)) {
628 pool = dev->prp_small_pool;
eca18b23 629 iod->npages = 0;
99802a7a
MW		 630 } else {
631 pool = dev->prp_page_pool;
eca18b23 632 iod->npages = 1;
99802a7a
MW		 633 }
634
69d2b571 635 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
b77954cb 636 if (!prp_list) {
edd10d33 637 iod->first_dma = dma_addr;
eca18b23 638 iod->npages = -1;
86eea289 639 return BLK_STS_RESOURCE;
b77954cb 640 }
eca18b23
MW		 641 list[0] = prp_list;
642 iod->first_dma = prp_dma;
e025344c
SMM		 643 i = 0;
644 for (;;) {
6c3c05b0 645 if (i == NVME_CTRL_PAGE_SIZE >> 3) {
e025344c 646 __le64 *old_prp_list = prp_list;
69d2b571 647 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
eca18b23 648 if (!prp_list)
86eea289 649 return BLK_STS_RESOURCE;
eca18b23 650 list[iod->npages++] = prp_list;
7523d834
MW		 651 prp_list[0] = old_prp_list[i - 1];
652 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
653 i = 1;
e025344c
SMM		 654 }
655 prp_list[i++] = cpu_to_le64(dma_addr);
6c3c05b0
CK		 656 dma_len -= NVME_CTRL_PAGE_SIZE;
657 dma_addr += NVME_CTRL_PAGE_SIZE;
658 length -= NVME_CTRL_PAGE_SIZE;
e025344c
SMM		 659 if (length <= 0)
660 break;
661 if (dma_len > 0)
662 continue;
86eea289
KB		 663 if (unlikely(dma_len < 0))
664 goto bad_sgl;
e025344c
SMM		 665 sg = sg_next(sg);
666 dma_addr = sg_dma_address(sg);
667 dma_len = sg_dma_len(sg);
ff22b54f
MW		 668 }
669
a7a7cbe3
CK		 670done:
671 cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
672 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
673
86eea289
KB		 674 return BLK_STS_OK;
675
676 bad_sgl:
d0877473
KB		 677 WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents),
678 "Invalid SGL for payload:%d nents:%d\n",
679 blk_rq_payload_bytes(req), iod->nents);
86eea289 680 return BLK_STS_IOERR;
ff22b54f
MW		 681}
682
a7a7cbe3
CK		 683static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
684 struct scatterlist *sg)
685{
686 sge->addr = cpu_to_le64(sg_dma_address(sg));
687 sge->length = cpu_to_le32(sg_dma_len(sg));
688 sge->type = NVME_SGL_FMT_DATA_DESC << 4;
689}
690
691static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
692 dma_addr_t dma_addr, int entries)
693{
694 sge->addr = cpu_to_le64(dma_addr);
695 if (entries < SGES_PER_PAGE) {
696 sge->length = cpu_to_le32(entries * sizeof(*sge));
697 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
698 } else {
699 sge->length = cpu_to_le32(PAGE_SIZE);
700 sge->type = NVME_SGL_FMT_SEG_DESC << 4;
701 }
702}
703
704static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
b0f2853b 705 struct request *req, struct nvme_rw_command *cmd, int entries)
a7a7cbe3
CK		 706{
707 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3
CK		 708 struct dma_pool *pool;
709 struct nvme_sgl_desc *sg_list;
710 struct scatterlist *sg = iod->sg;
a7a7cbe3 711 dma_addr_t sgl_dma;
b0f2853b 712 int i = 0;
a7a7cbe3 713
a7a7cbe3
CK		 714 /* setting the transfer type as SGL */
715 cmd->flags = NVME_CMD_SGL_METABUF;
716
b0f2853b 717 if (entries == 1) {
a7a7cbe3
CK		 718 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
719 return BLK_STS_OK;
720 }
721
722 if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
723 pool = dev->prp_small_pool;
724 iod->npages = 0;
725 } else {
726 pool = dev->prp_page_pool;
727 iod->npages = 1;
728 }
729
730 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
731 if (!sg_list) {
732 iod->npages = -1;
733 return BLK_STS_RESOURCE;
734 }
735
736 nvme_pci_iod_list(req)[0] = sg_list;
737 iod->first_dma = sgl_dma;
738
739 nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
740
741 do {
742 if (i == SGES_PER_PAGE) {
743 struct nvme_sgl_desc *old_sg_desc = sg_list;
744 struct nvme_sgl_desc *link = &old_sg_desc[i - 1];
745
746 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
747 if (!sg_list)
748 return BLK_STS_RESOURCE;
749
750 i = 0;
751 nvme_pci_iod_list(req)[iod->npages++] = sg_list;
752 sg_list[i++] = *link;
753 nvme_pci_sgl_set_seg(link, sgl_dma, entries);
754 }
755
756 nvme_pci_sgl_set_data(&sg_list[i++], sg);
a7a7cbe3 757 sg = sg_next(sg);
b0f2853b 758 } while (--entries > 0);
a7a7cbe3 759
a7a7cbe3
CK		 760 return BLK_STS_OK;
761}
762
dff824b2
CH		 763static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev,
764 struct request *req, struct nvme_rw_command *cmnd,
765 struct bio_vec *bv)
766{
767 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
6c3c05b0
CK		 768 unsigned int offset = bv->bv_offset & (NVME_CTRL_PAGE_SIZE - 1);
769 unsigned int first_prp_len = NVME_CTRL_PAGE_SIZE - offset;
dff824b2
CH		 770
771 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
772 if (dma_mapping_error(dev->dev, iod->first_dma))
773 return BLK_STS_RESOURCE;
774 iod->dma_len = bv->bv_len;
775
776 cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma);
777 if (bv->bv_len > first_prp_len)
778 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len);
359c1f88 779 return BLK_STS_OK;
dff824b2
CH		 780}
781
29791057
CH		 782static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev,
783 struct request *req, struct nvme_rw_command *cmnd,
784 struct bio_vec *bv)
785{
786 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
787
788 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
789 if (dma_mapping_error(dev->dev, iod->first_dma))
790 return BLK_STS_RESOURCE;
791 iod->dma_len = bv->bv_len;
792
049bf372 793 cmnd->flags = NVME_CMD_SGL_METABUF;
29791057
CH		 794 cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma);
795 cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len);
796 cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4;
359c1f88 797 return BLK_STS_OK;
29791057
CH		 798}
799
fc17b653 800static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
b131c61d 801 struct nvme_command *cmnd)
d29ec824 802{
f4800d6d 803 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
70479b71 804 blk_status_t ret = BLK_STS_RESOURCE;
b0f2853b 805 int nr_mapped;
d29ec824 806
dff824b2
CH		 807 if (blk_rq_nr_phys_segments(req) == 1) {
808 struct bio_vec bv = req_bvec(req);
809
810 if (!is_pci_p2pdma_page(bv.bv_page)) {
6c3c05b0 811 if (bv.bv_offset + bv.bv_len <= NVME_CTRL_PAGE_SIZE * 2)
dff824b2
CH		 812 return nvme_setup_prp_simple(dev, req,
813 &cmnd->rw, &bv);
29791057
CH		 814
815 if (iod->nvmeq->qid &&
816 dev->ctrl.sgls & ((1 << 0) | (1 << 1)))
817 return nvme_setup_sgl_simple(dev, req,
818 &cmnd->rw, &bv);
dff824b2
CH		 819 }
820 }
821
822 iod->dma_len = 0;
d43f1ccf
CH		 823 iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC);
824 if (!iod->sg)
825 return BLK_STS_RESOURCE;
f9d03f96 826 sg_init_table(iod->sg, blk_rq_nr_phys_segments(req));
70479b71 827 iod->nents = blk_rq_map_sg(req->q, req, iod->sg);
ba1ca37e
CH		 828 if (!iod->nents)
829 goto out;
d29ec824 830
e0596ab2 831 if (is_pci_p2pdma_page(sg_page(iod->sg)))
2b9f4bb2
LG		 832 nr_mapped = pci_p2pdma_map_sg_attrs(dev->dev, iod->sg,
833 iod->nents, rq_dma_dir(req), DMA_ATTR_NO_WARN);
e0596ab2
LG		 834 else
835 nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents,
70479b71 836 rq_dma_dir(req), DMA_ATTR_NO_WARN);
b0f2853b 837 if (!nr_mapped)
ba1ca37e 838 goto out;
d29ec824 839
70479b71 840 iod->use_sgl = nvme_pci_use_sgls(dev, req);
955b1b5a 841 if (iod->use_sgl)
b0f2853b 842 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped);
a7a7cbe3
CK		 843 else
844 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
4aedb705 845out:
86eea289 846 if (ret != BLK_STS_OK)
4aedb705
CH		 847 nvme_unmap_data(dev, req);
848 return ret;
849}
3045c0d0 850
4aedb705
CH		 851static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req,
852 struct nvme_command *cmnd)
853{
854 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
00df5cb4 855
4aedb705
CH		 856 iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req),
857 rq_dma_dir(req), 0);
858 if (dma_mapping_error(dev->dev, iod->meta_dma))
859 return BLK_STS_IOERR;
860 cmnd->rw.metadata = cpu_to_le64(iod->meta_dma);
359c1f88 861 return BLK_STS_OK;
00df5cb4
MW		 862}
863
d29ec824
CH		 864/*
865 * NOTE: ns is NULL when called on the admin queue.
866 */
fc17b653 867static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
a4aea562 868 const struct blk_mq_queue_data *bd)
edd10d33 869{
a4aea562
MB		 870 struct nvme_ns *ns = hctx->queue->queuedata;
871 struct nvme_queue *nvmeq = hctx->driver_data;
d29ec824 872 struct nvme_dev *dev = nvmeq->dev;
a4aea562 873 struct request *req = bd->rq;
9b048119 874 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
ba1ca37e 875 struct nvme_command cmnd;
ebe6d874 876 blk_status_t ret;
e1e5e564 877
9b048119
CH		 878 iod->aborted = 0;
879 iod->npages = -1;
880 iod->nents = 0;
881
d1f06f4a
JA		 882 /*
883 * We should not need to do this, but we're still using this to
884 * ensure we can drain requests on a dying queue.
885 */
4e224106 886 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
d1f06f4a
JA		 887 return BLK_STS_IOERR;
888
f9d03f96 889 ret = nvme_setup_cmd(ns, req, &cmnd);
fc17b653 890 if (ret)
f4800d6d 891 return ret;
a4aea562 892
fc17b653 893 if (blk_rq_nr_phys_segments(req)) {
b131c61d 894 ret = nvme_map_data(dev, req, &cmnd);
fc17b653 895 if (ret)
9b048119 896 goto out_free_cmd;
fc17b653 897 }
a4aea562 898
4aedb705
CH		 899 if (blk_integrity_rq(req)) {
900 ret = nvme_map_metadata(dev, req, &cmnd);
901 if (ret)
902 goto out_unmap_data;
903 }
904
aae239e1 905 blk_mq_start_request(req);
04f3eafd 906 nvme_submit_cmd(nvmeq, &cmnd, bd->last);
fc17b653 907 return BLK_STS_OK;
4aedb705
CH		 908out_unmap_data:
909 nvme_unmap_data(dev, req);
f9d03f96
CH		 910out_free_cmd:
911 nvme_cleanup_cmd(req);
ba1ca37e 912 return ret;
b60503ba 913}
e1e5e564 914
77f02a7a 915static void nvme_pci_complete_rq(struct request *req)
eee417b0 916{
f4800d6d 917 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
4aedb705 918 struct nvme_dev *dev = iod->nvmeq->dev;
a4aea562 919
4aedb705
CH		 920 if (blk_integrity_rq(req))
921 dma_unmap_page(dev->dev, iod->meta_dma,
922 rq_integrity_vec(req)->bv_len, rq_data_dir(req));
b15c592d 923 if (blk_rq_nr_phys_segments(req))
4aedb705 924 nvme_unmap_data(dev, req);
77f02a7a 925 nvme_complete_rq(req);
b60503ba
MW		 926}
927
d783e0bd 928/* We read the CQE phase first to check if the rest of the entry is valid */
750dde44 929static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq)
d783e0bd 930{
74943d45
KB		 931 struct nvme_completion *hcqe = &nvmeq->cqes[nvmeq->cq_head];
932
933 return (le16_to_cpu(READ_ONCE(hcqe->status)) & 1) == nvmeq->cq_phase;
d783e0bd
MR		 934}
935
eb281c82 936static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
b60503ba 937{
eb281c82 938 u16 head = nvmeq->cq_head;
adf68f21 939
397c699f
KB		 940 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
941 nvmeq->dbbuf_cq_ei))
942 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
eb281c82 943}
aae239e1 944
cfa27356
CH		 945static inline struct blk_mq_tags *nvme_queue_tagset(struct nvme_queue *nvmeq)
946{
947 if (!nvmeq->qid)
948 return nvmeq->dev->admin_tagset.tags[0];
949 return nvmeq->dev->tagset.tags[nvmeq->qid - 1];
950}
951
5cb525c8 952static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx)
83a12fb7 953{
74943d45 954 struct nvme_completion *cqe = &nvmeq->cqes[idx];
83a12fb7 955 struct request *req;
adf68f21 956
83a12fb7
SG		 957 /*
958 * AEN requests are special as they don't time out and can
959 * survive any kind of queue freeze and often don't respond to
960 * aborts. We don't even bother to allocate a struct request
961 * for them but rather special case them here.
962 */
58a8df67 963 if (unlikely(nvme_is_aen_req(nvmeq->qid, cqe->command_id))) {
83a12fb7
SG		 964 nvme_complete_async_event(&nvmeq->dev->ctrl,
965 cqe->status, &cqe->result);
a0fa9647 966 return;
83a12fb7 967 }
b60503ba 968
cfa27356 969 req = blk_mq_tag_to_rq(nvme_queue_tagset(nvmeq), cqe->command_id);
50b7c243
XT		 970 if (unlikely(!req)) {
971 dev_warn(nvmeq->dev->ctrl.device,
972 "invalid id %d completed on queue %d\n",
973 cqe->command_id, le16_to_cpu(cqe->sq_id));
974 return;
975 }
976
604c01d5 977 trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail);
2eb81a33 978 if (!nvme_try_complete_req(req, cqe->status, cqe->result))
ff029451 979 nvme_pci_complete_rq(req);
83a12fb7 980}
b60503ba 981
5cb525c8
JA		 982static inline void nvme_update_cq_head(struct nvme_queue *nvmeq)
983{
a8de6639
AD		 984 u16 tmp = nvmeq->cq_head + 1;
985
986 if (tmp == nvmeq->q_depth) {
5cb525c8 987 nvmeq->cq_head = 0;
e2a366a4 988 nvmeq->cq_phase ^= 1;
a8de6639
AD		 989 } else {
990 nvmeq->cq_head = tmp;
b60503ba 991 }
a0fa9647
JA		 992}
993
324b494c 994static inline int nvme_process_cq(struct nvme_queue *nvmeq)
a0fa9647 995{
1052b8ac 996 int found = 0;
b60503ba 997
1052b8ac 998 while (nvme_cqe_pending(nvmeq)) {
bf392a5d 999 found++;
b69e2ef2
KB		 1000 /*
1001 * load-load control dependency between phase and the rest of
1002 * the cqe requires a full read memory barrier
1003 */
1004 dma_rmb();
324b494c 1005 nvme_handle_cqe(nvmeq, nvmeq->cq_head);
5cb525c8 1006 nvme_update_cq_head(nvmeq);
920d13a8 1007 }
eb281c82 1008
324b494c 1009 if (found)
920d13a8 1010 nvme_ring_cq_doorbell(nvmeq);
5cb525c8 1011 return found;
b60503ba
MW		 1012}
1013
1014static irqreturn_t nvme_irq(int irq, void *data)
58ffacb5 1015{
58ffacb5 1016 struct nvme_queue *nvmeq = data;
68fa9dbe 1017 irqreturn_t ret = IRQ_NONE;
5cb525c8 1018
3a7afd8e
CH		 1019 /*
1020 * The rmb/wmb pair ensures we see all updates from a previous run of
1021 * the irq handler, even if that was on another CPU.
1022 */
1023 rmb();
324b494c
KB		 1024 if (nvme_process_cq(nvmeq))
1025 ret = IRQ_HANDLED;
3a7afd8e 1026 wmb();
5cb525c8 1027
68fa9dbe 1028 return ret;
58ffacb5
MW		 1029}
1030
1031static irqreturn_t nvme_irq_check(int irq, void *data)
1032{
1033 struct nvme_queue *nvmeq = data;
4e523547 1034
750dde44 1035 if (nvme_cqe_pending(nvmeq))
d783e0bd
MR		 1036 return IRQ_WAKE_THREAD;
1037 return IRQ_NONE;
58ffacb5
MW		 1038}
1039
0b2a8a9f 1040/*
fa059b85 1041 * Poll for completions for any interrupt driven queue
0b2a8a9f
CH		 1042 * Can be called from any context.
1043 */
fa059b85 1044static void nvme_poll_irqdisable(struct nvme_queue *nvmeq)
a0fa9647 1045{
3a7afd8e 1046 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
a0fa9647 1047
fa059b85 1048 WARN_ON_ONCE(test_bit(NVMEQ_POLLED, &nvmeq->flags));
442e19b7 1049
fa059b85
KB		 1050 disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1051 nvme_process_cq(nvmeq);
1052 enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
a0fa9647
JA		 1053}
1054
9743139c 1055static int nvme_poll(struct blk_mq_hw_ctx *hctx)
dabcefab
JA		 1056{
1057 struct nvme_queue *nvmeq = hctx->driver_data;
dabcefab
JA		 1058 bool found;
1059
1060 if (!nvme_cqe_pending(nvmeq))
1061 return 0;
1062
3a7afd8e 1063 spin_lock(&nvmeq->cq_poll_lock);
324b494c 1064 found = nvme_process_cq(nvmeq);
3a7afd8e 1065 spin_unlock(&nvmeq->cq_poll_lock);
dabcefab 1066
dabcefab
JA		 1067 return found;
1068}
1069
ad22c355 1070static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
b60503ba 1071{
f866fc42 1072 struct nvme_dev *dev = to_nvme_dev(ctrl);
147b27e4 1073 struct nvme_queue *nvmeq = &dev->queues[0];
a4aea562 1074 struct nvme_command c;
b60503ba 1075
a4aea562
MB		 1076 memset(&c, 0, sizeof(c));
1077 c.common.opcode = nvme_admin_async_event;
ad22c355 1078 c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
04f3eafd 1079 nvme_submit_cmd(nvmeq, &c, true);
f705f837
CH		 1080}
1081
b60503ba 1082static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
f705f837 1083{
b60503ba
MW		 1084 struct nvme_command c;
1085
1086 memset(&c, 0, sizeof(c));
1087 c.delete_queue.opcode = opcode;
1088 c.delete_queue.qid = cpu_to_le16(id);
1089
1c63dc66 1090 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1091}
1092
b60503ba 1093static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
a8e3e0bb 1094 struct nvme_queue *nvmeq, s16 vector)
b60503ba 1095{
b60503ba 1096 struct nvme_command c;
4b04cc6a
JA		 1097 int flags = NVME_QUEUE_PHYS_CONTIG;
1098
7c349dde 1099 if (!test_bit(NVMEQ_POLLED, &nvmeq->flags))
4b04cc6a 1100 flags |= NVME_CQ_IRQ_ENABLED;
b60503ba 1101
d29ec824 1102 /*
16772ae6 1103 * Note: we (ab)use the fact that the prp fields survive if no data
d29ec824
CH		 1104 * is attached to the request.
1105 */
b60503ba
MW		 1106 memset(&c, 0, sizeof(c));
1107 c.create_cq.opcode = nvme_admin_create_cq;
1108 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1109 c.create_cq.cqid = cpu_to_le16(qid);
1110 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1111 c.create_cq.cq_flags = cpu_to_le16(flags);
7c349dde 1112 c.create_cq.irq_vector = cpu_to_le16(vector);
b60503ba 1113
1c63dc66 1114 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1115}
1116
1117static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1118 struct nvme_queue *nvmeq)
1119{
9abd68ef 1120 struct nvme_ctrl *ctrl = &dev->ctrl;
b60503ba 1121 struct nvme_command c;
81c1cd98 1122 int flags = NVME_QUEUE_PHYS_CONTIG;
b60503ba 1123
9abd68ef
JA		 1124 /*
1125 * Some drives have a bug that auto-enables WRRU if MEDIUM isn't
1126 * set. Since URGENT priority is zeroes, it makes all queues
1127 * URGENT.
1128 */
1129 if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ)
1130 flags |= NVME_SQ_PRIO_MEDIUM;
1131
d29ec824 1132 /*
16772ae6 1133 * Note: we (ab)use the fact that the prp fields survive if no data
d29ec824
CH		 1134 * is attached to the request.
1135 */
b60503ba
MW		 1136 memset(&c, 0, sizeof(c));
1137 c.create_sq.opcode = nvme_admin_create_sq;
1138 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1139 c.create_sq.sqid = cpu_to_le16(qid);
1140 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1141 c.create_sq.sq_flags = cpu_to_le16(flags);
1142 c.create_sq.cqid = cpu_to_le16(qid);
1143
1c63dc66 1144 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1145}
1146
1147static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1148{
1149 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1150}
1151
1152static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1153{
1154 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1155}
1156
2a842aca 1157static void abort_endio(struct request *req, blk_status_t error)
bc5fc7e4 1158{
f4800d6d
CH		 1159 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1160 struct nvme_queue *nvmeq = iod->nvmeq;
e44ac588 1161
27fa9bc5
CH		 1162 dev_warn(nvmeq->dev->ctrl.device,
1163 "Abort status: 0x%x", nvme_req(req)->status);
e7a2a87d 1164 atomic_inc(&nvmeq->dev->ctrl.abort_limit);
e7a2a87d 1165 blk_mq_free_request(req);
bc5fc7e4
MW		 1166}
1167
b2a0eb1a
KB		 1168static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1169{
b2a0eb1a
KB		 1170 /* If true, indicates loss of adapter communication, possibly by a
1171 * NVMe Subsystem reset.
1172 */
1173 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1174
ad70062c
JW		 1175 /* If there is a reset/reinit ongoing, we shouldn't reset again. */
1176 switch (dev->ctrl.state) {
1177 case NVME_CTRL_RESETTING:
ad6a0a52 1178 case NVME_CTRL_CONNECTING:
b2a0eb1a 1179 return false;
ad70062c
JW		 1180 default:
1181 break;
1182 }
b2a0eb1a
KB		 1183
1184 /* We shouldn't reset unless the controller is on fatal error state
1185 * _or_ if we lost the communication with it.
1186 */
1187 if (!(csts & NVME_CSTS_CFS) && !nssro)
1188 return false;
1189
b2a0eb1a
KB		 1190 return true;
1191}
1192
1193static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1194{
1195 /* Read a config register to help see what died. */
1196 u16 pci_status;
1197 int result;
1198
1199 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1200 &pci_status);
1201 if (result == PCIBIOS_SUCCESSFUL)
1202 dev_warn(dev->ctrl.device,
1203 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1204 csts, pci_status);
1205 else
1206 dev_warn(dev->ctrl.device,
1207 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1208 csts, result);
1209}
1210
31c7c7d2 1211static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
c30341dc 1212{
f4800d6d
CH		 1213 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1214 struct nvme_queue *nvmeq = iod->nvmeq;
c30341dc 1215 struct nvme_dev *dev = nvmeq->dev;
a4aea562 1216 struct request *abort_req;
a4aea562 1217 struct nvme_command cmd;
b2a0eb1a
KB		 1218 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1219
651438bb
WX		 1220 /* If PCI error recovery process is happening, we cannot reset or
1221 * the recovery mechanism will surely fail.
1222 */
1223 mb();
1224 if (pci_channel_offline(to_pci_dev(dev->dev)))
1225 return BLK_EH_RESET_TIMER;
1226
b2a0eb1a
KB		 1227 /*
1228 * Reset immediately if the controller is failed
1229 */
1230 if (nvme_should_reset(dev, csts)) {
1231 nvme_warn_reset(dev, csts);
1232 nvme_dev_disable(dev, false);
d86c4d8e 1233 nvme_reset_ctrl(&dev->ctrl);
db8c48e4 1234 return BLK_EH_DONE;
b2a0eb1a 1235 }
c30341dc 1236
7776db1c
KB		 1237 /*
1238 * Did we miss an interrupt?
1239 */
fa059b85
KB		 1240 if (test_bit(NVMEQ_POLLED, &nvmeq->flags))
1241 nvme_poll(req->mq_hctx);
1242 else
1243 nvme_poll_irqdisable(nvmeq);
1244
bf392a5d 1245 if (blk_mq_request_completed(req)) {
7776db1c
KB		 1246 dev_warn(dev->ctrl.device,
1247 "I/O %d QID %d timeout, completion polled\n",
1248 req->tag, nvmeq->qid);
db8c48e4 1249 return BLK_EH_DONE;
7776db1c
KB		 1250 }
1251
31c7c7d2 1252 /*
fd634f41
CH		 1253 * Shutdown immediately if controller times out while starting. The
1254 * reset work will see the pci device disabled when it gets the forced
1255 * cancellation error. All outstanding requests are completed on
db8c48e4 1256 * shutdown, so we return BLK_EH_DONE.
fd634f41 1257 */
4244140d
KB		 1258 switch (dev->ctrl.state) {
1259 case NVME_CTRL_CONNECTING:
2036f726 1260 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
df561f66 1261 fallthrough;
2036f726 1262 case NVME_CTRL_DELETING:
b9cac43c 1263 dev_warn_ratelimited(dev->ctrl.device,
fd634f41
CH		 1264 "I/O %d QID %d timeout, disable controller\n",
1265 req->tag, nvmeq->qid);
27fa9bc5 1266 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
7ad92f65 1267 nvme_dev_disable(dev, true);
db8c48e4 1268 return BLK_EH_DONE;
39a9dd81
KB		 1269 case NVME_CTRL_RESETTING:
1270 return BLK_EH_RESET_TIMER;
4244140d
KB		 1271 default:
1272 break;
c30341dc
KB		 1273 }
1274
fd634f41 1275 /*
ee0d96d3
BW		 1276 * Shutdown the controller immediately and schedule a reset if the
1277 * command was already aborted once before and still hasn't been
1278 * returned to the driver, or if this is the admin queue.
31c7c7d2 1279 */
f4800d6d 1280 if (!nvmeq->qid || iod->aborted) {
1b3c47c1 1281 dev_warn(dev->ctrl.device,
e1569a16
KB		 1282 "I/O %d QID %d timeout, reset controller\n",
1283 req->tag, nvmeq->qid);
7ad92f65 1284 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
a5cdb68c 1285 nvme_dev_disable(dev, false);
d86c4d8e 1286 nvme_reset_ctrl(&dev->ctrl);
c30341dc 1287
db8c48e4 1288 return BLK_EH_DONE;
c30341dc 1289 }
c30341dc 1290
e7a2a87d 1291 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
6bf25d16 1292 atomic_inc(&dev->ctrl.abort_limit);
31c7c7d2 1293 return BLK_EH_RESET_TIMER;
6bf25d16 1294 }
7bf7d778 1295 iod->aborted = 1;
a4aea562 1296
c30341dc
KB		 1297 memset(&cmd, 0, sizeof(cmd));
1298 cmd.abort.opcode = nvme_admin_abort_cmd;
a4aea562 1299 cmd.abort.cid = req->tag;
c30341dc 1300 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
c30341dc 1301
1b3c47c1
SG		 1302 dev_warn(nvmeq->dev->ctrl.device,
1303 "I/O %d QID %d timeout, aborting\n",
1304 req->tag, nvmeq->qid);
e7a2a87d
CH		 1305
1306 abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
eb71f435 1307 BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
e7a2a87d
CH		 1308 if (IS_ERR(abort_req)) {
1309 atomic_inc(&dev->ctrl.abort_limit);
1310 return BLK_EH_RESET_TIMER;
1311 }
1312
1313 abort_req->timeout = ADMIN_TIMEOUT;
1314 abort_req->end_io_data = NULL;
1315 blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio);
c30341dc 1316
31c7c7d2
CH		 1317 /*
1318 * The aborted req will be completed on receiving the abort req.
1319 * We enable the timer again. If hit twice, it'll cause a device reset,
1320 * as the device then is in a faulty state.
1321 */
1322 return BLK_EH_RESET_TIMER;
c30341dc
KB		 1323}
1324
a4aea562
MB		 1325static void nvme_free_queue(struct nvme_queue *nvmeq)
1326{
8a1d09a6 1327 dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq),
9e866774 1328 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
63223078
CH		 1329 if (!nvmeq->sq_cmds)
1330 return;
0f238ff5 1331
63223078 1332 if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) {
88a041f4 1333 pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev),
8a1d09a6 1334 nvmeq->sq_cmds, SQ_SIZE(nvmeq));
63223078 1335 } else {
8a1d09a6 1336 dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq),
63223078 1337 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
0f238ff5 1338 }
9e866774
MW		 1339}
1340
a1a5ef99 1341static void nvme_free_queues(struct nvme_dev *dev, int lowest)
22404274
KB		 1342{
1343 int i;
1344
d858e5f0 1345 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
d858e5f0 1346 dev->ctrl.queue_count--;
147b27e4 1347 nvme_free_queue(&dev->queues[i]);
121c7ad4 1348 }
22404274
KB		 1349}
1350
4d115420
KB		 1351/**
1352 * nvme_suspend_queue - put queue into suspended state
40581d1a 1353 * @nvmeq: queue to suspend
4d115420
KB		 1354 */
1355static int nvme_suspend_queue(struct nvme_queue *nvmeq)
b60503ba 1356{
4e224106 1357 if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags))
2b25d981 1358 return 1;
a09115b2 1359
4e224106 1360 /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */
d1f06f4a 1361 mb();
a09115b2 1362
4e224106 1363 nvmeq->dev->online_queues--;
1c63dc66 1364 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
c81545f9 1365 blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q);
7c349dde
KB		 1366 if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags))
1367 pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq);
4d115420
KB		 1368 return 0;
1369}
b60503ba 1370
8fae268b
KB		 1371static void nvme_suspend_io_queues(struct nvme_dev *dev)
1372{
1373 int i;
1374
1375 for (i = dev->ctrl.queue_count - 1; i > 0; i--)
1376 nvme_suspend_queue(&dev->queues[i]);
1377}
1378
a5cdb68c 1379static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
4d115420 1380{
147b27e4 1381 struct nvme_queue *nvmeq = &dev->queues[0];
4d115420 1382
a5cdb68c
KB		 1383 if (shutdown)
1384 nvme_shutdown_ctrl(&dev->ctrl);
1385 else
b5b05048 1386 nvme_disable_ctrl(&dev->ctrl);
07836e65 1387
bf392a5d 1388 nvme_poll_irqdisable(nvmeq);
b60503ba
MW		 1389}
1390
fa46c6fb
KB		 1391/*
1392 * Called only on a device that has been disabled and after all other threads
9210c075
DZ		 1393 * that can check this device's completion queues have synced, except
1394 * nvme_poll(). This is the last chance for the driver to see a natural
1395 * completion before nvme_cancel_request() terminates all incomplete requests.
fa46c6fb
KB		 1396 */
1397static void nvme_reap_pending_cqes(struct nvme_dev *dev)
1398{
fa46c6fb
KB		 1399 int i;
1400
9210c075
DZ		 1401 for (i = dev->ctrl.queue_count - 1; i > 0; i--) {
1402 spin_lock(&dev->queues[i].cq_poll_lock);
324b494c 1403 nvme_process_cq(&dev->queues[i]);
9210c075
DZ		 1404 spin_unlock(&dev->queues[i].cq_poll_lock);
1405 }
fa46c6fb
KB		 1406}
1407
8ffaadf7
JD		 1408static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1409 int entry_size)
1410{
1411 int q_depth = dev->q_depth;
5fd4ce1b 1412 unsigned q_size_aligned = roundup(q_depth * entry_size,
6c3c05b0 1413 NVME_CTRL_PAGE_SIZE);
8ffaadf7
JD		 1414
1415 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
c45f5c99 1416 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
4e523547 1417
6c3c05b0 1418 mem_per_q = round_down(mem_per_q, NVME_CTRL_PAGE_SIZE);
c45f5c99 1419 q_depth = div_u64(mem_per_q, entry_size);
8ffaadf7
JD		 1420
1421 /*
1422 * Ensure the reduced q_depth is above some threshold where it
1423 * would be better to map queues in system memory with the
1424 * original depth
1425 */
1426 if (q_depth < 64)
1427 return -ENOMEM;
1428 }
1429
1430 return q_depth;
1431}
1432
1433static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
8a1d09a6 1434 int qid)
8ffaadf7 1435{
0f238ff5
LG		 1436 struct pci_dev *pdev = to_pci_dev(dev->dev);
1437
1438 if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
8a1d09a6 1439 nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq));
bfac8e9f
AM		 1440 if (nvmeq->sq_cmds) {
1441 nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev,
1442 nvmeq->sq_cmds);
1443 if (nvmeq->sq_dma_addr) {
1444 set_bit(NVMEQ_SQ_CMB, &nvmeq->flags);
1445 return 0;
1446 }
1447
8a1d09a6 1448 pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq));
63223078 1449 }
0f238ff5 1450 }
8ffaadf7 1451
8a1d09a6 1452 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq),
63223078 1453 &nvmeq->sq_dma_addr, GFP_KERNEL);
815c6704
KB		 1454 if (!nvmeq->sq_cmds)
1455 return -ENOMEM;
8ffaadf7
JD		 1456 return 0;
1457}
1458
a6ff7262 1459static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
b60503ba 1460{
147b27e4 1461 struct nvme_queue *nvmeq = &dev->queues[qid];
b60503ba 1462
62314e40
KB		 1463 if (dev->ctrl.queue_count > qid)
1464 return 0;
b60503ba 1465
c1e0cc7e 1466 nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES;
8a1d09a6
BH		 1467 nvmeq->q_depth = depth;
1468 nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq),
750afb08 1469 &nvmeq->cq_dma_addr, GFP_KERNEL);
b60503ba
MW		 1470 if (!nvmeq->cqes)
1471 goto free_nvmeq;
b60503ba 1472
8a1d09a6 1473 if (nvme_alloc_sq_cmds(dev, nvmeq, qid))
b60503ba
MW		 1474 goto free_cqdma;
1475
091b6092 1476 nvmeq->dev = dev;
1ab0cd69 1477 spin_lock_init(&nvmeq->sq_lock);
3a7afd8e 1478 spin_lock_init(&nvmeq->cq_poll_lock);
b60503ba 1479 nvmeq->cq_head = 0;
82123460 1480 nvmeq->cq_phase = 1;
b80d5ccc 1481 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
c30341dc 1482 nvmeq->qid = qid;
d858e5f0 1483 dev->ctrl.queue_count++;
36a7e993 1484
147b27e4 1485 return 0;
b60503ba
MW		 1486
1487 free_cqdma:
8a1d09a6
BH		 1488 dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes,
1489 nvmeq->cq_dma_addr);
b60503ba 1490 free_nvmeq:
147b27e4 1491 return -ENOMEM;
b60503ba
MW		 1492}
1493
dca51e78 1494static int queue_request_irq(struct nvme_queue *nvmeq)
3001082c 1495{
0ff199cb
CH		 1496 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1497 int nr = nvmeq->dev->ctrl.instance;
1498
1499 if (use_threaded_interrupts) {
1500 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1501 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1502 } else {
1503 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1504 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1505 }
3001082c
MW		 1506}
1507
22404274 1508static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
b60503ba 1509{
22404274 1510 struct nvme_dev *dev = nvmeq->dev;
b60503ba 1511
22404274 1512 nvmeq->sq_tail = 0;
38210800 1513 nvmeq->last_sq_tail = 0;
22404274
KB		 1514 nvmeq->cq_head = 0;
1515 nvmeq->cq_phase = 1;
b80d5ccc 1516 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
8a1d09a6 1517 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq));
f9f38e33 1518 nvme_dbbuf_init(dev, nvmeq, qid);
42f61420 1519 dev->online_queues++;
3a7afd8e 1520 wmb(); /* ensure the first interrupt sees the initialization */
22404274
KB		 1521}
1522
4b04cc6a 1523static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled)
22404274
KB		 1524{
1525 struct nvme_dev *dev = nvmeq->dev;
1526 int result;
7c349dde 1527 u16 vector = 0;
3f85d50b 1528
d1ed6aa1
CH		 1529 clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
1530
22b55601
KB		 1531 /*
1532 * A queue's vector matches the queue identifier unless the controller
1533 * has only one vector available.
1534 */
4b04cc6a
JA		 1535 if (!polled)
1536 vector = dev->num_vecs == 1 ? 0 : qid;
1537 else
7c349dde 1538 set_bit(NVMEQ_POLLED, &nvmeq->flags);
4b04cc6a 1539
a8e3e0bb 1540 result = adapter_alloc_cq(dev, qid, nvmeq, vector);
ded45505
KB		 1541 if (result)
1542 return result;
b60503ba
MW		 1543
1544 result = adapter_alloc_sq(dev, qid, nvmeq);
1545 if (result < 0)
ded45505 1546 return result;
c80b36cd 1547 if (result)
b60503ba
MW		 1548 goto release_cq;
1549
a8e3e0bb 1550 nvmeq->cq_vector = vector;
161b8be2 1551 nvme_init_queue(nvmeq, qid);
4b04cc6a 1552
7c349dde 1553 if (!polled) {
4b04cc6a
JA		 1554 result = queue_request_irq(nvmeq);
1555 if (result < 0)
1556 goto release_sq;
1557 }
b60503ba 1558
4e224106 1559 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
22404274 1560 return result;
b60503ba 1561
a8e3e0bb 1562release_sq:
f25a2dfc 1563 dev->online_queues--;
b60503ba 1564 adapter_delete_sq(dev, qid);
a8e3e0bb 1565release_cq:
b60503ba 1566 adapter_delete_cq(dev, qid);
22404274 1567 return result;
b60503ba
MW		 1568}
1569
f363b089 1570static const struct blk_mq_ops nvme_mq_admin_ops = {
d29ec824 1571 .queue_rq = nvme_queue_rq,
77f02a7a 1572 .complete = nvme_pci_complete_rq,
a4aea562 1573 .init_hctx = nvme_admin_init_hctx,
0350815a 1574 .init_request = nvme_init_request,
a4aea562
MB		 1575 .timeout = nvme_timeout,
1576};
1577
f363b089 1578static const struct blk_mq_ops nvme_mq_ops = {
376f7ef8
CH		 1579 .queue_rq = nvme_queue_rq,
1580 .complete = nvme_pci_complete_rq,
1581 .commit_rqs = nvme_commit_rqs,
1582 .init_hctx = nvme_init_hctx,
1583 .init_request = nvme_init_request,
1584 .map_queues = nvme_pci_map_queues,
1585 .timeout = nvme_timeout,
1586 .poll = nvme_poll,
dabcefab
JA		 1587};
1588
ea191d2f
KB		 1589static void nvme_dev_remove_admin(struct nvme_dev *dev)
1590{
1c63dc66 1591 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
69d9a99c
KB		 1592 /*
1593 * If the controller was reset during removal, it's possible
1594 * user requests may be waiting on a stopped queue. Start the
1595 * queue to flush these to completion.
1596 */
c81545f9 1597 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1c63dc66 1598 blk_cleanup_queue(dev->ctrl.admin_q);
ea191d2f
KB		 1599 blk_mq_free_tag_set(&dev->admin_tagset);
1600 }
1601}
1602
a4aea562
MB		 1603static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1604{
1c63dc66 1605 if (!dev->ctrl.admin_q) {
a4aea562
MB		 1606 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1607 dev->admin_tagset.nr_hw_queues = 1;
e3e9d50c 1608
38dabe21 1609 dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH;
a4aea562 1610 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
d4ec47f1 1611 dev->admin_tagset.numa_node = dev->ctrl.numa_node;
d43f1ccf 1612 dev->admin_tagset.cmd_size = sizeof(struct nvme_iod);
d3484991 1613 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED;
a4aea562
MB		 1614 dev->admin_tagset.driver_data = dev;
1615
1616 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1617 return -ENOMEM;
34b6c231 1618 dev->ctrl.admin_tagset = &dev->admin_tagset;
a4aea562 1619
1c63dc66
CH		 1620 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1621 if (IS_ERR(dev->ctrl.admin_q)) {
a4aea562
MB		 1622 blk_mq_free_tag_set(&dev->admin_tagset);
1623 return -ENOMEM;
1624 }
1c63dc66 1625 if (!blk_get_queue(dev->ctrl.admin_q)) {
ea191d2f 1626 nvme_dev_remove_admin(dev);
1c63dc66 1627 dev->ctrl.admin_q = NULL;
ea191d2f
KB		 1628 return -ENODEV;
1629 }
0fb59cbc 1630 } else
c81545f9 1631 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
a4aea562
MB		 1632
1633 return 0;
1634}
1635
97f6ef64
XY		 1636static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1637{
1638 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1639}
1640
1641static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1642{
1643 struct pci_dev *pdev = to_pci_dev(dev->dev);
1644
1645 if (size <= dev->bar_mapped_size)
1646 return 0;
1647 if (size > pci_resource_len(pdev, 0))
1648 return -ENOMEM;
1649 if (dev->bar)
1650 iounmap(dev->bar);
1651 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1652 if (!dev->bar) {
1653 dev->bar_mapped_size = 0;
1654 return -ENOMEM;
1655 }
1656 dev->bar_mapped_size = size;
1657 dev->dbs = dev->bar + NVME_REG_DBS;
1658
1659 return 0;
1660}
1661
01ad0990 1662static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
b60503ba 1663{
ba47e386 1664 int result;
b60503ba
MW		 1665 u32 aqa;
1666 struct nvme_queue *nvmeq;
1667
97f6ef64
XY		 1668 result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1669 if (result < 0)
1670 return result;
1671
8ef2074d 1672 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
20d0dfe6 1673 NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
dfbac8c7 1674
7a67cbea
CH		 1675 if (dev->subsystem &&
1676 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1677 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
dfbac8c7 1678
b5b05048 1679 result = nvme_disable_ctrl(&dev->ctrl);
ba47e386
MW		 1680 if (result < 0)
1681 return result;
b60503ba 1682
a6ff7262 1683 result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
147b27e4
SG		 1684 if (result)
1685 return result;
b60503ba 1686
635333e4
MG		 1687 dev->ctrl.numa_node = dev_to_node(dev->dev);
1688
147b27e4 1689 nvmeq = &dev->queues[0];
b60503ba
MW		 1690 aqa = nvmeq->q_depth - 1;
1691 aqa |= aqa << 16;
1692
7a67cbea
CH		 1693 writel(aqa, dev->bar + NVME_REG_AQA);
1694 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1695 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
b60503ba 1696
c0f2f45b 1697 result = nvme_enable_ctrl(&dev->ctrl);
025c557a 1698 if (result)
d4875622 1699 return result;
a4aea562 1700
2b25d981 1701 nvmeq->cq_vector = 0;
161b8be2 1702 nvme_init_queue(nvmeq, 0);
dca51e78 1703 result = queue_request_irq(nvmeq);
758dd7fd 1704 if (result) {
7c349dde 1705 dev->online_queues--;
d4875622 1706 return result;
758dd7fd 1707 }
025c557a 1708
4e224106 1709 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
b60503ba
MW		 1710 return result;
1711}
1712
749941f2 1713static int nvme_create_io_queues(struct nvme_dev *dev)
42f61420 1714{
4b04cc6a 1715 unsigned i, max, rw_queues;
749941f2 1716 int ret = 0;
42f61420 1717
d858e5f0 1718 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
a6ff7262 1719 if (nvme_alloc_queue(dev, i, dev->q_depth)) {
749941f2 1720 ret = -ENOMEM;
42f61420 1721 break;
749941f2
CH		 1722 }
1723 }
42f61420 1724
d858e5f0 1725 max = min(dev->max_qid, dev->ctrl.queue_count - 1);
e20ba6e1
CH		 1726 if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) {
1727 rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] +
1728 dev->io_queues[HCTX_TYPE_READ];
4b04cc6a
JA		 1729 } else {
1730 rw_queues = max;
1731 }
1732
949928c1 1733 for (i = dev->online_queues; i <= max; i++) {
4b04cc6a
JA		 1734 bool polled = i > rw_queues;
1735
1736 ret = nvme_create_queue(&dev->queues[i], i, polled);
d4875622 1737 if (ret)
42f61420 1738 break;
27e8166c 1739 }
749941f2
CH		 1740
1741 /*
1742 * Ignore failing Create SQ/CQ commands, we can continue with less
8adb8c14
MI		 1743 * than the desired amount of queues, and even a controller without
1744 * I/O queues can still be used to issue admin commands. This might
749941f2
CH		 1745 * be useful to upgrade a buggy firmware for example.
1746 */
1747 return ret >= 0 ? 0 : ret;
b60503ba
MW		 1748}
1749
202021c1
SB		 1750static ssize_t nvme_cmb_show(struct device *dev,
1751 struct device_attribute *attr,
1752 char *buf)
1753{
1754 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
1755
c965809c 1756 return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n",
202021c1
SB		 1757 ndev->cmbloc, ndev->cmbsz);
1758}
1759static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL);
1760
88de4598 1761static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
8ffaadf7 1762{
88de4598
CH		 1763 u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
1764
1765 return 1ULL << (12 + 4 * szu);
1766}
1767
1768static u32 nvme_cmb_size(struct nvme_dev *dev)
1769{
1770 return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
1771}
1772
f65efd6d 1773static void nvme_map_cmb(struct nvme_dev *dev)
8ffaadf7 1774{
88de4598 1775 u64 size, offset;
8ffaadf7
JD		 1776 resource_size_t bar_size;
1777 struct pci_dev *pdev = to_pci_dev(dev->dev);
8969f1f8 1778 int bar;
8ffaadf7 1779
9fe5c59f
KB		 1780 if (dev->cmb_size)
1781 return;
1782
7a67cbea 1783 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
f65efd6d
CH		 1784 if (!dev->cmbsz)
1785 return;
202021c1 1786 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
8ffaadf7 1787
88de4598
CH		 1788 size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
1789 offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
8969f1f8
CH		 1790 bar = NVME_CMB_BIR(dev->cmbloc);
1791 bar_size = pci_resource_len(pdev, bar);
8ffaadf7
JD		 1792
1793 if (offset > bar_size)
f65efd6d 1794 return;
8ffaadf7
JD		 1795
1796 /*
1797 * Controllers may support a CMB size larger than their BAR,
1798 * for example, due to being behind a bridge. Reduce the CMB to
1799 * the reported size of the BAR
1800 */
1801 if (size > bar_size - offset)
1802 size = bar_size - offset;
1803
0f238ff5
LG		 1804 if (pci_p2pdma_add_resource(pdev, bar, size, offset)) {
1805 dev_warn(dev->ctrl.device,
1806 "failed to register the CMB\n");
f65efd6d 1807 return;
0f238ff5
LG		 1808 }
1809
8ffaadf7 1810 dev->cmb_size = size;
0f238ff5
LG		 1811 dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS);
1812
1813 if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) ==
1814 (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS))
1815 pci_p2pmem_publish(pdev, true);
f65efd6d
CH		 1816
1817 if (sysfs_add_file_to_group(&dev->ctrl.device->kobj,
1818 &dev_attr_cmb.attr, NULL))
1819 dev_warn(dev->ctrl.device,
1820 "failed to add sysfs attribute for CMB\n");
8ffaadf7
JD		 1821}
1822
1823static inline void nvme_release_cmb(struct nvme_dev *dev)
1824{
0f238ff5 1825 if (dev->cmb_size) {
1c78f773
MG		 1826 sysfs_remove_file_from_group(&dev->ctrl.device->kobj,
1827 &dev_attr_cmb.attr, NULL);
0f238ff5 1828 dev->cmb_size = 0;
8ffaadf7
JD		 1829 }
1830}
1831
87ad72a5
CH		 1832static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1833{
6c3c05b0 1834 u32 host_mem_size = dev->host_mem_size >> NVME_CTRL_PAGE_SHIFT;
4033f35d 1835 u64 dma_addr = dev->host_mem_descs_dma;
87ad72a5 1836 struct nvme_command c;
87ad72a5
CH		 1837 int ret;
1838
87ad72a5
CH		 1839 memset(&c, 0, sizeof(c));
1840 c.features.opcode = nvme_admin_set_features;
1841 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1842 c.features.dword11 = cpu_to_le32(bits);
6c3c05b0 1843 c.features.dword12 = cpu_to_le32(host_mem_size);
87ad72a5
CH		 1844 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr));
1845 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr));
1846 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs);
1847
1848 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1849 if (ret) {
1850 dev_warn(dev->ctrl.device,
1851 "failed to set host mem (err %d, flags %#x).\n",
1852 ret, bits);
1853 }
87ad72a5
CH		 1854 return ret;
1855}
1856
1857static void nvme_free_host_mem(struct nvme_dev *dev)
1858{
1859 int i;
1860
1861 for (i = 0; i < dev->nr_host_mem_descs; i++) {
1862 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
6c3c05b0 1863 size_t size = le32_to_cpu(desc->size) * NVME_CTRL_PAGE_SIZE;
87ad72a5 1864
cc667f6d
LD		 1865 dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i],
1866 le64_to_cpu(desc->addr),
1867 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
87ad72a5
CH		 1868 }
1869
1870 kfree(dev->host_mem_desc_bufs);
1871 dev->host_mem_desc_bufs = NULL;
4033f35d
CH		 1872 dma_free_coherent(dev->dev,
1873 dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
1874 dev->host_mem_descs, dev->host_mem_descs_dma);
87ad72a5 1875 dev->host_mem_descs = NULL;
7e5dd57e 1876 dev->nr_host_mem_descs = 0;
87ad72a5
CH		 1877}
1878
92dc6895
CH		 1879static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
1880 u32 chunk_size)
9d713c2b 1881{
87ad72a5 1882 struct nvme_host_mem_buf_desc *descs;
92dc6895 1883 u32 max_entries, len;
4033f35d 1884 dma_addr_t descs_dma;
2ee0e4ed 1885 int i = 0;
87ad72a5 1886 void **bufs;
6fbcde66 1887 u64 size, tmp;
87ad72a5 1888
87ad72a5
CH		 1889 tmp = (preferred + chunk_size - 1);
1890 do_div(tmp, chunk_size);
1891 max_entries = tmp;
044a9df1
CH		 1892
1893 if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
1894 max_entries = dev->ctrl.hmmaxd;
1895
750afb08
LC		 1896 descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs),
1897 &descs_dma, GFP_KERNEL);
87ad72a5
CH		 1898 if (!descs)
1899 goto out;
1900
1901 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
1902 if (!bufs)
1903 goto out_free_descs;
1904
244a8fe4 1905 for (size = 0; size < preferred && i < max_entries; size += len) {
87ad72a5
CH		 1906 dma_addr_t dma_addr;
1907
50cdb7c6 1908 len = min_t(u64, chunk_size, preferred - size);
87ad72a5
CH		 1909 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
1910 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1911 if (!bufs[i])
1912 break;
1913
1914 descs[i].addr = cpu_to_le64(dma_addr);
6c3c05b0 1915 descs[i].size = cpu_to_le32(len / NVME_CTRL_PAGE_SIZE);
87ad72a5
CH		 1916 i++;
1917 }
1918
92dc6895 1919 if (!size)
87ad72a5 1920 goto out_free_bufs;
87ad72a5 1921
87ad72a5
CH		 1922 dev->nr_host_mem_descs = i;
1923 dev->host_mem_size = size;
1924 dev->host_mem_descs = descs;
4033f35d 1925 dev->host_mem_descs_dma = descs_dma;
87ad72a5
CH		 1926 dev->host_mem_desc_bufs = bufs;
1927 return 0;
1928
1929out_free_bufs:
1930 while (--i >= 0) {
6c3c05b0 1931 size_t size = le32_to_cpu(descs[i].size) * NVME_CTRL_PAGE_SIZE;
87ad72a5 1932
cc667f6d
LD		 1933 dma_free_attrs(dev->dev, size, bufs[i],
1934 le64_to_cpu(descs[i].addr),
1935 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
87ad72a5
CH		 1936 }
1937
1938 kfree(bufs);
1939out_free_descs:
4033f35d
CH		 1940 dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
1941 descs_dma);
87ad72a5 1942out:
87ad72a5
CH		 1943 dev->host_mem_descs = NULL;
1944 return -ENOMEM;
1945}
1946
92dc6895
CH		 1947static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
1948{
9dc54a0d
CK		 1949 u64 min_chunk = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
1950 u64 hmminds = max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
1951 u64 chunk_size;
92dc6895
CH		 1952
1953 /* start big and work our way down */
9dc54a0d 1954 for (chunk_size = min_chunk; chunk_size >= hmminds; chunk_size /= 2) {
92dc6895
CH		 1955 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
1956 if (!min || dev->host_mem_size >= min)
1957 return 0;
1958 nvme_free_host_mem(dev);
1959 }
1960 }
1961
1962 return -ENOMEM;
1963}
1964
9620cfba 1965static int nvme_setup_host_mem(struct nvme_dev *dev)
87ad72a5
CH		 1966{
1967 u64 max = (u64)max_host_mem_size_mb * SZ_1M;
1968 u64 preferred = (u64)dev->ctrl.hmpre * 4096;
1969 u64 min = (u64)dev->ctrl.hmmin * 4096;
1970 u32 enable_bits = NVME_HOST_MEM_ENABLE;
6fbcde66 1971 int ret;
87ad72a5
CH		 1972
1973 preferred = min(preferred, max);
1974 if (min > max) {
1975 dev_warn(dev->ctrl.device,
1976 "min host memory (%lld MiB) above limit (%d MiB).\n",
1977 min >> ilog2(SZ_1M), max_host_mem_size_mb);
1978 nvme_free_host_mem(dev);
9620cfba 1979 return 0;
87ad72a5
CH		 1980 }
1981
1982 /*
1983 * If we already have a buffer allocated check if we can reuse it.
1984 */
1985 if (dev->host_mem_descs) {
1986 if (dev->host_mem_size >= min)
1987 enable_bits |= NVME_HOST_MEM_RETURN;
1988 else
1989 nvme_free_host_mem(dev);
1990 }
1991
1992 if (!dev->host_mem_descs) {
92dc6895
CH		 1993 if (nvme_alloc_host_mem(dev, min, preferred)) {
1994 dev_warn(dev->ctrl.device,
1995 "failed to allocate host memory buffer.\n");
9620cfba 1996 return 0; /* controller must work without HMB */
92dc6895
CH		 1997 }
1998
1999 dev_info(dev->ctrl.device,
2000 "allocated %lld MiB host memory buffer.\n",
2001 dev->host_mem_size >> ilog2(SZ_1M));
87ad72a5
CH		 2002 }
2003
9620cfba
CH		 2004 ret = nvme_set_host_mem(dev, enable_bits);
2005 if (ret)
87ad72a5 2006 nvme_free_host_mem(dev);
9620cfba 2007 return ret;
9d713c2b
KB		 2008}
2009
612b7286
ML		 2010/*
2011 * nirqs is the number of interrupts available for write and read
2012 * queues. The core already reserved an interrupt for the admin queue.
2013 */
2014static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs)
3b6592f7 2015{
612b7286 2016 struct nvme_dev *dev = affd->priv;
2a5bcfdd 2017 unsigned int nr_read_queues, nr_write_queues = dev->nr_write_queues;
3b6592f7
JA		 2018
2019 /*
ee0d96d3 2020 * If there is no interrupt available for queues, ensure that
612b7286
ML		 2021 * the default queue is set to 1. The affinity set size is
2022 * also set to one, but the irq core ignores it for this case.
2023 *
2024 * If only one interrupt is available or 'write_queue' == 0, combine
2025 * write and read queues.
2026 *
2027 * If 'write_queues' > 0, ensure it leaves room for at least one read
2028 * queue.
3b6592f7 2029 */
612b7286
ML		 2030 if (!nrirqs) {
2031 nrirqs = 1;
2032 nr_read_queues = 0;
2a5bcfdd 2033 } else if (nrirqs == 1 || !nr_write_queues) {
612b7286 2034 nr_read_queues = 0;
2a5bcfdd 2035 } else if (nr_write_queues >= nrirqs) {
612b7286 2036 nr_read_queues = 1;
3b6592f7 2037 } else {
2a5bcfdd 2038 nr_read_queues = nrirqs - nr_write_queues;
3b6592f7 2039 }
612b7286
ML		 2040
2041 dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2042 affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2043 dev->io_queues[HCTX_TYPE_READ] = nr_read_queues;
2044 affd->set_size[HCTX_TYPE_READ] = nr_read_queues;
2045 affd->nr_sets = nr_read_queues ? 2 : 1;
3b6592f7
JA		 2046}
2047
6451fe73 2048static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues)
3b6592f7
JA		 2049{
2050 struct pci_dev *pdev = to_pci_dev(dev->dev);
3b6592f7 2051 struct irq_affinity affd = {
9cfef55b 2052 .pre_vectors = 1,
612b7286
ML		 2053 .calc_sets = nvme_calc_irq_sets,
2054 .priv = dev,
3b6592f7 2055 };
21cc2f3f 2056 unsigned int irq_queues, poll_queues;
6451fe73
JA		 2057
2058 /*
21cc2f3f
JX		 2059 * Poll queues don't need interrupts, but we need at least one I/O queue
2060 * left over for non-polled I/O.
6451fe73 2061 */
21cc2f3f
JX		 2062 poll_queues = min(dev->nr_poll_queues, nr_io_queues - 1);
2063 dev->io_queues[HCTX_TYPE_POLL] = poll_queues;
3b6592f7 2064
21cc2f3f
JX		 2065 /*
2066 * Initialize for the single interrupt case, will be updated in
2067 * nvme_calc_irq_sets().
2068 */
612b7286
ML		 2069 dev->io_queues[HCTX_TYPE_DEFAULT] = 1;
2070 dev->io_queues[HCTX_TYPE_READ] = 0;
3b6592f7 2071
66341331 2072 /*
21cc2f3f
JX		 2073 * We need interrupts for the admin queue and each non-polled I/O queue,
2074 * but some Apple controllers require all queues to use the first
2075 * vector.
66341331 2076 */
21cc2f3f
JX		 2077 irq_queues = 1;
2078 if (!(dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR))
2079 irq_queues += (nr_io_queues - poll_queues);
612b7286
ML		 2080 return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues,
2081 PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd);
3b6592f7
JA		 2082}
2083
8fae268b
KB		 2084static void nvme_disable_io_queues(struct nvme_dev *dev)
2085{
2086 if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq))
2087 __nvme_disable_io_queues(dev, nvme_admin_delete_cq);
2088}
2089
2a5bcfdd
WZ		 2090static unsigned int nvme_max_io_queues(struct nvme_dev *dev)
2091{
2092 return num_possible_cpus() + dev->nr_write_queues + dev->nr_poll_queues;
2093}
2094
8d85fce7 2095static int nvme_setup_io_queues(struct nvme_dev *dev)
b60503ba 2096{
147b27e4 2097 struct nvme_queue *adminq = &dev->queues[0];
e75ec752 2098 struct pci_dev *pdev = to_pci_dev(dev->dev);
2a5bcfdd 2099 unsigned int nr_io_queues;
97f6ef64 2100 unsigned long size;
2a5bcfdd 2101 int result;
b60503ba 2102
2a5bcfdd
WZ		 2103 /*
2104 * Sample the module parameters once at reset time so that we have
2105 * stable values to work with.
2106 */
2107 dev->nr_write_queues = write_queues;
2108 dev->nr_poll_queues = poll_queues;
d38e9f04
BH		 2109
2110 /*
2111 * If tags are shared with admin queue (Apple bug), then
2112 * make sure we only use one IO queue.
2113 */
2114 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2115 nr_io_queues = 1;
2a5bcfdd
WZ		 2116 else
2117 nr_io_queues = min(nvme_max_io_queues(dev),
2118 dev->nr_allocated_queues - 1);
d38e9f04 2119
9a0be7ab
CH		 2120 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
2121 if (result < 0)
1b23484b 2122 return result;
9a0be7ab 2123
f5fa90dc 2124 if (nr_io_queues == 0)
a5229050 2125 return 0;
4e224106
CH		 2126
2127 clear_bit(NVMEQ_ENABLED, &adminq->flags);
b60503ba 2128
0f238ff5 2129 if (dev->cmb_use_sqes) {
8ffaadf7
JD		 2130 result = nvme_cmb_qdepth(dev, nr_io_queues,
2131 sizeof(struct nvme_command));
2132 if (result > 0)
2133 dev->q_depth = result;
2134 else
0f238ff5 2135 dev->cmb_use_sqes = false;
8ffaadf7
JD		 2136 }
2137
97f6ef64
XY		 2138 do {
2139 size = db_bar_size(dev, nr_io_queues);
2140 result = nvme_remap_bar(dev, size);
2141 if (!result)
2142 break;
2143 if (!--nr_io_queues)
2144 return -ENOMEM;
2145 } while (1);
2146 adminq->q_db = dev->dbs;
f1938f6e 2147
8fae268b 2148 retry:
9d713c2b 2149 /* Deregister the admin queue's interrupt */
0ff199cb 2150 pci_free_irq(pdev, 0, adminq);
9d713c2b 2151
e32efbfc
JA		 2152 /*
2153 * If we enable msix early due to not intx, disable it again before
2154 * setting up the full range we need.
2155 */
dca51e78 2156 pci_free_irq_vectors(pdev);
3b6592f7
JA		 2157
2158 result = nvme_setup_irqs(dev, nr_io_queues);
22b55601 2159 if (result <= 0)
dca51e78 2160 return -EIO;
3b6592f7 2161
22b55601 2162 dev->num_vecs = result;
4b04cc6a 2163 result = max(result - 1, 1);
e20ba6e1 2164 dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL];
fa08a396 2165
063a8096
MW		 2166 /*
2167 * Should investigate if there's a performance win from allocating
2168 * more queues than interrupt vectors; it might allow the submission
2169 * path to scale better, even if the receive path is limited by the
2170 * number of interrupts.
2171 */
dca51e78 2172 result = queue_request_irq(adminq);
7c349dde 2173 if (result)
d4875622 2174 return result;
4e224106 2175 set_bit(NVMEQ_ENABLED, &adminq->flags);
8fae268b
KB		 2176
2177 result = nvme_create_io_queues(dev);
2178 if (result || dev->online_queues < 2)
2179 return result;
2180
2181 if (dev->online_queues - 1 < dev->max_qid) {
2182 nr_io_queues = dev->online_queues - 1;
2183 nvme_disable_io_queues(dev);
2184 nvme_suspend_io_queues(dev);
2185 goto retry;
2186 }
2187 dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n",
2188 dev->io_queues[HCTX_TYPE_DEFAULT],
2189 dev->io_queues[HCTX_TYPE_READ],
2190 dev->io_queues[HCTX_TYPE_POLL]);
2191 return 0;
b60503ba
MW		 2192}
2193
2a842aca 2194static void nvme_del_queue_end(struct request *req, blk_status_t error)
a5768aa8 2195{
db3cbfff 2196 struct nvme_queue *nvmeq = req->end_io_data;
b5875222 2197
db3cbfff 2198 blk_mq_free_request(req);
d1ed6aa1 2199 complete(&nvmeq->delete_done);
a5768aa8
KB		 2200}
2201
2a842aca 2202static void nvme_del_cq_end(struct request *req, blk_status_t error)
a5768aa8 2203{
db3cbfff 2204 struct nvme_queue *nvmeq = req->end_io_data;
a5768aa8 2205
d1ed6aa1
CH		 2206 if (error)
2207 set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
db3cbfff
KB		 2208
2209 nvme_del_queue_end(req, error);
a5768aa8
KB		 2210}
2211
db3cbfff 2212static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
bda4e0fb 2213{
db3cbfff
KB		 2214 struct request_queue *q = nvmeq->dev->ctrl.admin_q;
2215 struct request *req;
2216 struct nvme_command cmd;
bda4e0fb 2217
db3cbfff
KB		 2218 memset(&cmd, 0, sizeof(cmd));
2219 cmd.delete_queue.opcode = opcode;
2220 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
bda4e0fb 2221
eb71f435 2222 req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
db3cbfff
KB		 2223 if (IS_ERR(req))
2224 return PTR_ERR(req);
bda4e0fb 2225
db3cbfff
KB		 2226 req->timeout = ADMIN_TIMEOUT;
2227 req->end_io_data = nvmeq;
2228
d1ed6aa1 2229 init_completion(&nvmeq->delete_done);
db3cbfff
KB		 2230 blk_execute_rq_nowait(q, NULL, req, false,
2231 opcode == nvme_admin_delete_cq ?
2232 nvme_del_cq_end : nvme_del_queue_end);
2233 return 0;
bda4e0fb
KB		 2234}
2235
8fae268b 2236static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode)
a5768aa8 2237{
5271edd4 2238 int nr_queues = dev->online_queues - 1, sent = 0;
db3cbfff 2239 unsigned long timeout;
a5768aa8 2240
db3cbfff 2241 retry:
5271edd4
CH		 2242 timeout = ADMIN_TIMEOUT;
2243 while (nr_queues > 0) {
2244 if (nvme_delete_queue(&dev->queues[nr_queues], opcode))
2245 break;
2246 nr_queues--;
2247 sent++;
db3cbfff 2248 }
d1ed6aa1
CH		 2249 while (sent) {
2250 struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent];
2251
2252 timeout = wait_for_completion_io_timeout(&nvmeq->delete_done,
5271edd4
CH		 2253 timeout);
2254 if (timeout == 0)
2255 return false;
d1ed6aa1 2256
d1ed6aa1 2257 sent--;
5271edd4
CH		 2258 if (nr_queues)
2259 goto retry;
2260 }
2261 return true;
a5768aa8
KB		 2262}
2263
5d02a5c1 2264static void nvme_dev_add(struct nvme_dev *dev)
b60503ba 2265{
2b1b7e78
JW		 2266 int ret;
2267
5bae7f73 2268 if (!dev->ctrl.tagset) {
376f7ef8 2269 dev->tagset.ops = &nvme_mq_ops;
ffe7704d 2270 dev->tagset.nr_hw_queues = dev->online_queues - 1;
8fe34be1 2271 dev->tagset.nr_maps = 2; /* default + read */
ed92ad37
CH		 2272 if (dev->io_queues[HCTX_TYPE_POLL])
2273 dev->tagset.nr_maps++;
ffe7704d 2274 dev->tagset.timeout = NVME_IO_TIMEOUT;
d4ec47f1 2275 dev->tagset.numa_node = dev->ctrl.numa_node;
61f3b896
CK		 2276 dev->tagset.queue_depth = min_t(unsigned int, dev->q_depth,
2277 BLK_MQ_MAX_DEPTH) - 1;
d43f1ccf 2278 dev->tagset.cmd_size = sizeof(struct nvme_iod);
ffe7704d
KB		 2279 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2280 dev->tagset.driver_data = dev;
b60503ba 2281
d38e9f04
BH		 2282 /*
2283 * Some Apple controllers requires tags to be unique
2284 * across admin and IO queue, so reserve the first 32
2285 * tags of the IO queue.
2286 */
2287 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2288 dev->tagset.reserved_tags = NVME_AQ_DEPTH;
2289
2b1b7e78
JW		 2290 ret = blk_mq_alloc_tag_set(&dev->tagset);
2291 if (ret) {
2292 dev_warn(dev->ctrl.device,
2293 "IO queues tagset allocation failed %d\n", ret);
5d02a5c1 2294 return;
2b1b7e78 2295 }
5bae7f73 2296 dev->ctrl.tagset = &dev->tagset;
949928c1
KB		 2297 } else {
2298 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2299
2300 /* Free previously allocated queues that are no longer usable */
2301 nvme_free_queues(dev, dev->online_queues);
ffe7704d 2302 }
949928c1 2303
e8fd41bb 2304 nvme_dbbuf_set(dev);
b60503ba
MW		 2305}
2306
b00a726a 2307static int nvme_pci_enable(struct nvme_dev *dev)
0877cb0d 2308{
b00a726a 2309 int result = -ENOMEM;
e75ec752 2310 struct pci_dev *pdev = to_pci_dev(dev->dev);
0877cb0d
KB		 2311
2312 if (pci_enable_device_mem(pdev))
2313 return result;
2314
0877cb0d 2315 pci_set_master(pdev);
0877cb0d 2316
4fe06923 2317 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)))
052d0efa 2318 goto disable;
0877cb0d 2319
7a67cbea 2320 if (readl(dev->bar + NVME_REG_CSTS) == -1) {
0e53d180 2321 result = -ENODEV;
b00a726a 2322 goto disable;
0e53d180 2323 }
e32efbfc
JA		 2324
2325 /*
a5229050
KB		 2326 * Some devices and/or platforms don't advertise or work with INTx
2327 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2328 * adjust this later.
e32efbfc 2329 */
dca51e78
CH		 2330 result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
2331 if (result < 0)
2332 return result;
e32efbfc 2333
20d0dfe6 2334 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
7a67cbea 2335
7442ddce 2336 dev->q_depth = min_t(u32, NVME_CAP_MQES(dev->ctrl.cap) + 1,
b27c1e68 2337 io_queue_depth);
aa22c8e6 2338 dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */
20d0dfe6 2339 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
7a67cbea 2340 dev->dbs = dev->bar + 4096;
1f390c1f 2341
66341331
BH		 2342 /*
2343 * Some Apple controllers require a non-standard SQE size.
2344 * Interestingly they also seem to ignore the CC:IOSQES register
2345 * so we don't bother updating it here.
2346 */
2347 if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES)
2348 dev->io_sqes = 7;
2349 else
2350 dev->io_sqes = NVME_NVM_IOSQES;
1f390c1f
SG		 2351
2352 /*
2353 * Temporary fix for the Apple controller found in the MacBook8,1 and
2354 * some MacBook7,1 to avoid controller resets and data loss.
2355 */
2356 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
2357 dev->q_depth = 2;
9bdcfb10
CH		 2358 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
2359 "set queue depth=%u to work around controller resets\n",
1f390c1f 2360 dev->q_depth);
d554b5e1
MP		 2361 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2362 (pdev->device == 0xa821 || pdev->device == 0xa822) &&
20d0dfe6 2363 NVME_CAP_MQES(dev->ctrl.cap) == 0) {
d554b5e1
MP		 2364 dev->q_depth = 64;
2365 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2366 "set queue depth=%u\n", dev->q_depth);
1f390c1f
SG		 2367 }
2368
d38e9f04
BH		 2369 /*
2370 * Controllers with the shared tags quirk need the IO queue to be
2371 * big enough so that we get 32 tags for the admin queue
2372 */
2373 if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) &&
2374 (dev->q_depth < (NVME_AQ_DEPTH + 2))) {
2375 dev->q_depth = NVME_AQ_DEPTH + 2;
2376 dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n",
2377 dev->q_depth);
2378 }
2379
2380
f65efd6d 2381 nvme_map_cmb(dev);
202021c1 2382
a0a3408e
KB		 2383 pci_enable_pcie_error_reporting(pdev);
2384 pci_save_state(pdev);
0877cb0d
KB		 2385 return 0;
2386
2387 disable:
0877cb0d
KB		 2388 pci_disable_device(pdev);
2389 return result;
2390}
2391
2392static void nvme_dev_unmap(struct nvme_dev *dev)
b00a726a
KB		 2393{
2394 if (dev->bar)
2395 iounmap(dev->bar);
a1f447b3 2396 pci_release_mem_regions(to_pci_dev(dev->dev));
b00a726a
KB		 2397}
2398
2399static void nvme_pci_disable(struct nvme_dev *dev)
0877cb0d 2400{
e75ec752
CH		 2401 struct pci_dev *pdev = to_pci_dev(dev->dev);
2402
dca51e78 2403 pci_free_irq_vectors(pdev);
0877cb0d 2404
a0a3408e
KB		 2405 if (pci_is_enabled(pdev)) {
2406 pci_disable_pcie_error_reporting(pdev);
e75ec752 2407 pci_disable_device(pdev);
4d115420 2408 }
4d115420
KB		 2409}
2410
a5cdb68c 2411static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
b60503ba 2412{
e43269e6 2413 bool dead = true, freeze = false;
302ad8cc 2414 struct pci_dev *pdev = to_pci_dev(dev->dev);
22404274 2415
77bf25ea 2416 mutex_lock(&dev->shutdown_lock);
302ad8cc
KB		 2417 if (pci_is_enabled(pdev)) {
2418 u32 csts = readl(dev->bar + NVME_REG_CSTS);
2419
ebef7368 2420 if (dev->ctrl.state == NVME_CTRL_LIVE ||
e43269e6
KB		 2421 dev->ctrl.state == NVME_CTRL_RESETTING) {
2422 freeze = true;
302ad8cc 2423 nvme_start_freeze(&dev->ctrl);
e43269e6 2424 }
302ad8cc
KB		 2425 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
2426 pdev->error_state != pci_channel_io_normal);
c9d3bf88 2427 }
c21377f8 2428
302ad8cc
KB		 2429 /*
2430 * Give the controller a chance to complete all entered requests if
2431 * doing a safe shutdown.
2432 */
e43269e6
KB		 2433 if (!dead && shutdown && freeze)
2434 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
9a915a5b
JW		 2435
2436 nvme_stop_queues(&dev->ctrl);
87ad72a5 2437
64ee0ac0 2438 if (!dead && dev->ctrl.queue_count > 0) {
8fae268b 2439 nvme_disable_io_queues(dev);
a5cdb68c 2440 nvme_disable_admin_queue(dev, shutdown);
4d115420 2441 }
8fae268b
KB		 2442 nvme_suspend_io_queues(dev);
2443 nvme_suspend_queue(&dev->queues[0]);
b00a726a 2444 nvme_pci_disable(dev);
fa46c6fb 2445 nvme_reap_pending_cqes(dev);
07836e65 2446
e1958e65
ML		 2447 blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
2448 blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
622b8b68
ML		 2449 blk_mq_tagset_wait_completed_request(&dev->tagset);
2450 blk_mq_tagset_wait_completed_request(&dev->admin_tagset);
302ad8cc
KB		 2451
2452 /*
2453 * The driver will not be starting up queues again if shutting down so
2454 * must flush all entered requests to their failed completion to avoid
2455 * deadlocking blk-mq hot-cpu notifier.
2456 */
c8e9e9b7 2457 if (shutdown) {
302ad8cc 2458 nvme_start_queues(&dev->ctrl);
c8e9e9b7
KB		 2459 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q))
2460 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
2461 }
77bf25ea 2462 mutex_unlock(&dev->shutdown_lock);
b60503ba
MW		 2463}
2464
c1ac9a4b
KB		 2465static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown)
2466{
2467 if (!nvme_wait_reset(&dev->ctrl))
2468 return -EBUSY;
2469 nvme_dev_disable(dev, shutdown);
2470 return 0;
2471}
2472
091b6092
MW		 2473static int nvme_setup_prp_pools(struct nvme_dev *dev)
2474{
e75ec752 2475 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
c61b82c7
CH		 2476 NVME_CTRL_PAGE_SIZE,
2477 NVME_CTRL_PAGE_SIZE, 0);
091b6092
MW		 2478 if (!dev->prp_page_pool)
2479 return -ENOMEM;
2480
99802a7a 2481 /* Optimisation for I/Os between 4k and 128k */
e75ec752 2482 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
99802a7a
MW		 2483 256, 256, 0);
2484 if (!dev->prp_small_pool) {
2485 dma_pool_destroy(dev->prp_page_pool);
2486 return -ENOMEM;
2487 }
091b6092
MW		 2488 return 0;
2489}
2490
2491static void nvme_release_prp_pools(struct nvme_dev *dev)
2492{
2493 dma_pool_destroy(dev->prp_page_pool);
99802a7a 2494 dma_pool_destroy(dev->prp_small_pool);
091b6092
MW		 2495}
2496
770597ec
KB		 2497static void nvme_free_tagset(struct nvme_dev *dev)
2498{
2499 if (dev->tagset.tags)
2500 blk_mq_free_tag_set(&dev->tagset);
2501 dev->ctrl.tagset = NULL;
2502}
2503
1673f1f0 2504static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
5e82e952 2505{
1673f1f0 2506 struct nvme_dev *dev = to_nvme_dev(ctrl);
9ac27090 2507
f9f38e33 2508 nvme_dbbuf_dma_free(dev);
770597ec 2509 nvme_free_tagset(dev);
1c63dc66
CH		 2510 if (dev->ctrl.admin_q)
2511 blk_put_queue(dev->ctrl.admin_q);
e286bcfc 2512 free_opal_dev(dev->ctrl.opal_dev);
943e942e 2513 mempool_destroy(dev->iod_mempool);
253fd4ac
IR		 2514 put_device(dev->dev);
2515 kfree(dev->queues);
5e82e952
KB		 2516 kfree(dev);
2517}
2518
7c1ce408 2519static void nvme_remove_dead_ctrl(struct nvme_dev *dev)
f58944e2 2520{
c1ac9a4b
KB		 2521 /*
2522 * Set state to deleting now to avoid blocking nvme_wait_reset(), which
2523 * may be holding this pci_dev's device lock.
2524 */
2525 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
d22524a4 2526 nvme_get_ctrl(&dev->ctrl);
69d9a99c 2527 nvme_dev_disable(dev, false);
9f9cafc1 2528 nvme_kill_queues(&dev->ctrl);
03e0f3a6 2529 if (!queue_work(nvme_wq, &dev->remove_work))
f58944e2
KB		 2530 nvme_put_ctrl(&dev->ctrl);
2531}
2532
fd634f41 2533static void nvme_reset_work(struct work_struct *work)
5e82e952 2534{
d86c4d8e
CH		 2535 struct nvme_dev *dev =
2536 container_of(work, struct nvme_dev, ctrl.reset_work);
a98e58e5 2537 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
e71afda4 2538 int result;
5e82e952 2539
e71afda4
CK		 2540 if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING)) {
2541 result = -ENODEV;
fd634f41 2542 goto out;
e71afda4 2543 }
5e82e952 2544
fd634f41
CH		 2545 /*
2546 * If we're called to reset a live controller first shut it down before
2547 * moving on.
2548 */
b00a726a 2549 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
a5cdb68c 2550 nvme_dev_disable(dev, false);
d6135c3a 2551 nvme_sync_queues(&dev->ctrl);
5e82e952 2552
5c959d73 2553 mutex_lock(&dev->shutdown_lock);
b00a726a 2554 result = nvme_pci_enable(dev);
f0b50732 2555 if (result)
4726bcf3 2556 goto out_unlock;
f0b50732 2557
01ad0990 2558 result = nvme_pci_configure_admin_queue(dev);
f0b50732 2559 if (result)
4726bcf3 2560 goto out_unlock;
f0b50732 2561
0fb59cbc
KB		 2562 result = nvme_alloc_admin_tags(dev);
2563 if (result)
4726bcf3 2564 goto out_unlock;
b9afca3e 2565
943e942e
JA		 2566 /*
2567 * Limit the max command size to prevent iod->sg allocations going
2568 * over a single page.
2569 */
7637de31
CH		 2570 dev->ctrl.max_hw_sectors = min_t(u32,
2571 NVME_MAX_KB_SZ << 1, dma_max_mapping_size(dev->dev) >> 9);
943e942e 2572 dev->ctrl.max_segments = NVME_MAX_SEGS;
a48bc520
CH		 2573
2574 /*
2575 * Don't limit the IOMMU merged segment size.
2576 */
2577 dma_set_max_seg_size(dev->dev, 0xffffffff);
2578
5c959d73
KB		 2579 mutex_unlock(&dev->shutdown_lock);
2580
2581 /*
2582 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
2583 * initializing procedure here.
2584 */
2585 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
2586 dev_warn(dev->ctrl.device,
2587 "failed to mark controller CONNECTING\n");
cee6c269 2588 result = -EBUSY;
5c959d73
KB		 2589 goto out;
2590 }
943e942e 2591
95093350
MG		 2592 /*
2593 * We do not support an SGL for metadata (yet), so we are limited to a
2594 * single integrity segment for the separate metadata pointer.
2595 */
2596 dev->ctrl.max_integrity_segments = 1;
2597
ce4541f4
CH		 2598 result = nvme_init_identify(&dev->ctrl);
2599 if (result)
f58944e2 2600 goto out;
ce4541f4 2601
e286bcfc
SB		 2602 if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
2603 if (!dev->ctrl.opal_dev)
2604 dev->ctrl.opal_dev =
2605 init_opal_dev(&dev->ctrl, &nvme_sec_submit);
2606 else if (was_suspend)
2607 opal_unlock_from_suspend(dev->ctrl.opal_dev);
2608 } else {
2609 free_opal_dev(dev->ctrl.opal_dev);
2610 dev->ctrl.opal_dev = NULL;
4f1244c8 2611 }
a98e58e5 2612
f9f38e33
HK		 2613 if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) {
2614 result = nvme_dbbuf_dma_alloc(dev);
2615 if (result)
2616 dev_warn(dev->dev,
2617 "unable to allocate dma for dbbuf\n");
2618 }
2619
9620cfba
CH		 2620 if (dev->ctrl.hmpre) {
2621 result = nvme_setup_host_mem(dev);
2622 if (result < 0)
2623 goto out;
2624 }
87ad72a5 2625
f0b50732 2626 result = nvme_setup_io_queues(dev);
badc34d4 2627 if (result)
f58944e2 2628 goto out;
f0b50732 2629
2659e57b
CH		 2630 /*
2631 * Keep the controller around but remove all namespaces if we don't have
2632 * any working I/O queue.
2633 */
3cf519b5 2634 if (dev->online_queues < 2) {
1b3c47c1 2635 dev_warn(dev->ctrl.device, "IO queues not created\n");
3b24774e 2636 nvme_kill_queues(&dev->ctrl);
5bae7f73 2637 nvme_remove_namespaces(&dev->ctrl);
770597ec 2638 nvme_free_tagset(dev);
3cf519b5 2639 } else {
25646264 2640 nvme_start_queues(&dev->ctrl);
302ad8cc 2641 nvme_wait_freeze(&dev->ctrl);
5d02a5c1 2642 nvme_dev_add(dev);
302ad8cc 2643 nvme_unfreeze(&dev->ctrl);
3cf519b5
CH		 2644 }
2645
2b1b7e78
JW		 2646 /*
2647 * If only admin queue live, keep it to do further investigation or
2648 * recovery.
2649 */
5d02a5c1 2650 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
2b1b7e78 2651 dev_warn(dev->ctrl.device,
5d02a5c1 2652 "failed to mark controller live state\n");
e71afda4 2653 result = -ENODEV;
bb8d261e
CH		 2654 goto out;
2655 }
92911a55 2656
d09f2b45 2657 nvme_start_ctrl(&dev->ctrl);
3cf519b5 2658 return;
f0b50732 2659
4726bcf3
KB		 2660 out_unlock:
2661 mutex_unlock(&dev->shutdown_lock);
3cf519b5 2662 out:
7c1ce408
CK		 2663 if (result)
2664 dev_warn(dev->ctrl.device,
2665 "Removing after probe failure status: %d\n", result);
2666 nvme_remove_dead_ctrl(dev);
f0b50732
KB		 2667}
2668
5c8809e6 2669static void nvme_remove_dead_ctrl_work(struct work_struct *work)
9a6b9458 2670{
5c8809e6 2671 struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
e75ec752 2672 struct pci_dev *pdev = to_pci_dev(dev->dev);
9a6b9458
KB		 2673
2674 if (pci_get_drvdata(pdev))
921920ab 2675 device_release_driver(&pdev->dev);
1673f1f0 2676 nvme_put_ctrl(&dev->ctrl);
9a6b9458
KB		 2677}
2678
1c63dc66 2679static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
9ca97374 2680{
1c63dc66 2681 *val = readl(to_nvme_dev(ctrl)->bar + off);
90667892 2682 return 0;
9ca97374
TH		 2683}
2684
5fd4ce1b 2685static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
4cc06521 2686{
5fd4ce1b
CH		 2687 writel(val, to_nvme_dev(ctrl)->bar + off);
2688 return 0;
2689}
4cc06521 2690
7fd8930f
CH		 2691static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2692{
3a8ecc93 2693 *val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off);
7fd8930f 2694 return 0;
4cc06521
KB		 2695}
2696
97c12223
KB		 2697static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
2698{
2699 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2700
2db24e4a 2701 return snprintf(buf, size, "%s\n", dev_name(&pdev->dev));
97c12223
KB		 2702}
2703
1c63dc66 2704static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
1a353d85 2705 .name = "pcie",
e439bb12 2706 .module = THIS_MODULE,
e0596ab2
LG		 2707 .flags = NVME_F_METADATA_SUPPORTED |
2708 NVME_F_PCI_P2PDMA,
1c63dc66 2709 .reg_read32 = nvme_pci_reg_read32,
5fd4ce1b 2710 .reg_write32 = nvme_pci_reg_write32,
7fd8930f 2711 .reg_read64 = nvme_pci_reg_read64,
1673f1f0 2712 .free_ctrl = nvme_pci_free_ctrl,
f866fc42 2713 .submit_async_event = nvme_pci_submit_async_event,
97c12223 2714 .get_address = nvme_pci_get_address,
1c63dc66 2715};
4cc06521 2716
b00a726a
KB		 2717static int nvme_dev_map(struct nvme_dev *dev)
2718{
b00a726a
KB		 2719 struct pci_dev *pdev = to_pci_dev(dev->dev);
2720
a1f447b3 2721 if (pci_request_mem_regions(pdev, "nvme"))
b00a726a
KB		 2722 return -ENODEV;
2723
97f6ef64 2724 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
b00a726a
KB		 2725 goto release;
2726
9fa196e7 2727 return 0;
b00a726a 2728 release:
9fa196e7
MG		 2729 pci_release_mem_regions(pdev);
2730 return -ENODEV;
b00a726a
KB		 2731}
2732
8427bbc2 2733static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
ff5350a8
AL		 2734{
2735 if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
2736 /*
2737 * Several Samsung devices seem to drop off the PCIe bus
2738 * randomly when APST is on and uses the deepest sleep state.
2739 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2740 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2741 * 950 PRO 256GB", but it seems to be restricted to two Dell
2742 * laptops.
2743 */
2744 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
2745 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
2746 dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
2747 return NVME_QUIRK_NO_DEEPEST_PS;
8427bbc2
KHF		 2748 } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
2749 /*
2750 * Samsung SSD 960 EVO drops off the PCIe bus after system
467c77d4
JJ		 2751 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
2752 * within few minutes after bootup on a Coffee Lake board -
2753 * ASUS PRIME Z370-A
8427bbc2
KHF		 2754 */
2755 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
467c77d4
JJ		 2756 (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") ||
2757 dmi_match(DMI_BOARD_NAME, "PRIME Z370-A")))
8427bbc2 2758 return NVME_QUIRK_NO_APST;
1fae37ac
S		 2759 } else if ((pdev->vendor == 0x144d && (pdev->device == 0xa801 ||
2760 pdev->device == 0xa808 || pdev->device == 0xa809)) ||
2761 (pdev->vendor == 0x1e0f && pdev->device == 0x0001)) {
2762 /*
2763 * Forcing to use host managed nvme power settings for
2764 * lowest idle power with quick resume latency on
2765 * Samsung and Toshiba SSDs based on suspend behavior
2766 * on Coffee Lake board for LENOVO C640
2767 */
2768 if ((dmi_match(DMI_BOARD_VENDOR, "LENOVO")) &&
2769 dmi_match(DMI_BOARD_NAME, "LNVNB161216"))
2770 return NVME_QUIRK_SIMPLE_SUSPEND;
ff5350a8
AL		 2771 }
2772
2773 return 0;
2774}
2775
df4f9bc4
DB		 2776#ifdef CONFIG_ACPI
2777static bool nvme_acpi_storage_d3(struct pci_dev *dev)
2778{
2779 struct acpi_device *adev;
2780 struct pci_dev *root;
2781 acpi_handle handle;
2782 acpi_status status;
2783 u8 val;
2784
2785 /*
2786 * Look for _DSD property specifying that the storage device on the port
2787 * must use D3 to support deep platform power savings during
2788 * suspend-to-idle.
2789 */
2790 root = pcie_find_root_port(dev);
2791 if (!root)
2792 return false;
2793
2794 adev = ACPI_COMPANION(&root->dev);
2795 if (!adev)
2796 return false;
2797
2798 /*
2799 * The property is defined in the PXSX device for South complex ports
2800 * and in the PEGP device for North complex ports.
2801 */
2802 status = acpi_get_handle(adev->handle, "PXSX", &handle);
2803 if (ACPI_FAILURE(status)) {
2804 status = acpi_get_handle(adev->handle, "PEGP", &handle);
2805 if (ACPI_FAILURE(status))
2806 return false;
2807 }
2808
2809 if (acpi_bus_get_device(handle, &adev))
2810 return false;
2811
2812 if (fwnode_property_read_u8(acpi_fwnode_handle(adev), "StorageD3Enable",
2813 &val))
2814 return false;
2815 return val == 1;
2816}
2817#else
2818static inline bool nvme_acpi_storage_d3(struct pci_dev *dev)
2819{
2820 return false;
2821}
2822#endif /* CONFIG_ACPI */
2823
18119775
KB		 2824static void nvme_async_probe(void *data, async_cookie_t cookie)
2825{
2826 struct nvme_dev *dev = data;
80f513b5 2827
bd46a906 2828 flush_work(&dev->ctrl.reset_work);
18119775 2829 flush_work(&dev->ctrl.scan_work);
80f513b5 2830 nvme_put_ctrl(&dev->ctrl);
18119775
KB		 2831}
2832
8d85fce7 2833static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
b60503ba 2834{
a4aea562 2835 int node, result = -ENOMEM;
b60503ba 2836 struct nvme_dev *dev;
ff5350a8 2837 unsigned long quirks = id->driver_data;
943e942e 2838 size_t alloc_size;
b60503ba 2839
a4aea562
MB		 2840 node = dev_to_node(&pdev->dev);
2841 if (node == NUMA_NO_NODE)
2fa84351 2842 set_dev_node(&pdev->dev, first_memory_node);
a4aea562
MB		 2843
2844 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
b60503ba
MW		 2845 if (!dev)
2846 return -ENOMEM;
147b27e4 2847
2a5bcfdd
WZ		 2848 dev->nr_write_queues = write_queues;
2849 dev->nr_poll_queues = poll_queues;
2850 dev->nr_allocated_queues = nvme_max_io_queues(dev) + 1;
2851 dev->queues = kcalloc_node(dev->nr_allocated_queues,
2852 sizeof(struct nvme_queue), GFP_KERNEL, node);
b60503ba
MW		 2853 if (!dev->queues)
2854 goto free;
2855
e75ec752 2856 dev->dev = get_device(&pdev->dev);
9a6b9458 2857 pci_set_drvdata(pdev, dev);
1c63dc66 2858
b00a726a
KB		 2859 result = nvme_dev_map(dev);
2860 if (result)
b00c9b7a 2861 goto put_pci;
b00a726a 2862
d86c4d8e 2863 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
5c8809e6 2864 INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
77bf25ea 2865 mutex_init(&dev->shutdown_lock);
b60503ba 2866
091b6092
MW		 2867 result = nvme_setup_prp_pools(dev);
2868 if (result)
b00c9b7a 2869 goto unmap;
4cc06521 2870
8427bbc2 2871 quirks |= check_vendor_combination_bug(pdev);
ff5350a8 2872
df4f9bc4
DB		 2873 if (!noacpi && nvme_acpi_storage_d3(pdev)) {
2874 /*
2875 * Some systems use a bios work around to ask for D3 on
2876 * platforms that support kernel managed suspend.
2877 */
2878 dev_info(&pdev->dev,
2879 "platform quirk: setting simple suspend\n");
2880 quirks |= NVME_QUIRK_SIMPLE_SUSPEND;
2881 }
2882
943e942e
JA		 2883 /*
2884 * Double check that our mempool alloc size will cover the biggest
2885 * command we support.
2886 */
b13c6393 2887 alloc_size = nvme_pci_iod_alloc_size();
943e942e
JA		 2888 WARN_ON_ONCE(alloc_size > PAGE_SIZE);
2889
2890 dev->iod_mempool = mempool_create_node(1, mempool_kmalloc,
2891 mempool_kfree,
2892 (void *) alloc_size,
2893 GFP_KERNEL, node);
2894 if (!dev->iod_mempool) {
2895 result = -ENOMEM;
2896 goto release_pools;
2897 }
2898
b6e44b4c
KB		 2899 result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
2900 quirks);
2901 if (result)
2902 goto release_mempool;
2903
1b3c47c1
SG		 2904 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
2905
bd46a906 2906 nvme_reset_ctrl(&dev->ctrl);
18119775 2907 async_schedule(nvme_async_probe, dev);
4caff8fc 2908
b60503ba
MW		 2909 return 0;
2910
b6e44b4c
KB		 2911 release_mempool:
2912 mempool_destroy(dev->iod_mempool);
0877cb0d 2913 release_pools:
091b6092 2914 nvme_release_prp_pools(dev);
b00c9b7a
CJ		 2915 unmap:
2916 nvme_dev_unmap(dev);
a96d4f5c 2917 put_pci:
e75ec752 2918 put_device(dev->dev);
b60503ba
MW		 2919 free:
2920 kfree(dev->queues);
b60503ba
MW		 2921 kfree(dev);
2922 return result;
2923}
2924
775755ed 2925static void nvme_reset_prepare(struct pci_dev *pdev)
f0d54a54 2926{
a6739479 2927 struct nvme_dev *dev = pci_get_drvdata(pdev);
c1ac9a4b
KB		 2928
2929 /*
2930 * We don't need to check the return value from waiting for the reset
2931 * state as pci_dev device lock is held, making it impossible to race
2932 * with ->remove().
2933 */
2934 nvme_disable_prepare_reset(dev, false);
2935 nvme_sync_queues(&dev->ctrl);
775755ed 2936}
f0d54a54 2937
775755ed
CH		 2938static void nvme_reset_done(struct pci_dev *pdev)
2939{
f263fbb8 2940 struct nvme_dev *dev = pci_get_drvdata(pdev);
c1ac9a4b
KB		 2941
2942 if (!nvme_try_sched_reset(&dev->ctrl))
2943 flush_work(&dev->ctrl.reset_work);
f0d54a54
KB		 2944}
2945
09ece142
KB		 2946static void nvme_shutdown(struct pci_dev *pdev)
2947{
2948 struct nvme_dev *dev = pci_get_drvdata(pdev);
4e523547 2949
c1ac9a4b 2950 nvme_disable_prepare_reset(dev, true);
09ece142
KB		 2951}
2952
f58944e2
KB		 2953/*
2954 * The driver's remove may be called on a device in a partially initialized
2955 * state. This function must not have any dependencies on the device state in
2956 * order to proceed.
2957 */
8d85fce7 2958static void nvme_remove(struct pci_dev *pdev)
b60503ba
MW		 2959{
2960 struct nvme_dev *dev = pci_get_drvdata(pdev);
9a6b9458 2961
bb8d261e 2962 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
9a6b9458 2963 pci_set_drvdata(pdev, NULL);
0ff9d4e1 2964
6db28eda 2965 if (!pci_device_is_present(pdev)) {
0ff9d4e1 2966 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
1d39e692 2967 nvme_dev_disable(dev, true);
cb4bfda6 2968 nvme_dev_remove_admin(dev);
6db28eda 2969 }
0ff9d4e1 2970
d86c4d8e 2971 flush_work(&dev->ctrl.reset_work);
d09f2b45
SG		 2972 nvme_stop_ctrl(&dev->ctrl);
2973 nvme_remove_namespaces(&dev->ctrl);
a5cdb68c 2974 nvme_dev_disable(dev, true);
9fe5c59f 2975 nvme_release_cmb(dev);
87ad72a5 2976 nvme_free_host_mem(dev);
a4aea562 2977 nvme_dev_remove_admin(dev);
a1a5ef99 2978 nvme_free_queues(dev, 0);
9a6b9458 2979 nvme_release_prp_pools(dev);
b00a726a 2980 nvme_dev_unmap(dev);
726612b6 2981 nvme_uninit_ctrl(&dev->ctrl);
b60503ba
MW		 2982}
2983
671a6018 2984#ifdef CONFIG_PM_SLEEP
d916b1be
KB		 2985static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps)
2986{
2987 return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps);
2988}
2989
2990static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps)
2991{
2992 return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL);
2993}
2994
2995static int nvme_resume(struct device *dev)
2996{
2997 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
2998 struct nvme_ctrl *ctrl = &ndev->ctrl;
2999
4eaefe8c 3000 if (ndev->last_ps == U32_MAX ||
d916b1be 3001 nvme_set_power_state(ctrl, ndev->last_ps) != 0)
c1ac9a4b 3002 return nvme_try_sched_reset(&ndev->ctrl);
d916b1be
KB		 3003 return 0;
3004}
3005
cd638946
KB		 3006static int nvme_suspend(struct device *dev)
3007{
3008 struct pci_dev *pdev = to_pci_dev(dev);
3009 struct nvme_dev *ndev = pci_get_drvdata(pdev);
d916b1be
KB		 3010 struct nvme_ctrl *ctrl = &ndev->ctrl;
3011 int ret = -EBUSY;
3012
4eaefe8c
RW		 3013 ndev->last_ps = U32_MAX;
3014
d916b1be
KB		 3015 /*
3016 * The platform does not remove power for a kernel managed suspend so
3017 * use host managed nvme power settings for lowest idle power if
3018 * possible. This should have quicker resume latency than a full device
3019 * shutdown. But if the firmware is involved after the suspend or the
3020 * device does not support any non-default power states, shut down the
3021 * device fully.
4eaefe8c
RW		 3022 *
3023 * If ASPM is not enabled for the device, shut down the device and allow
3024 * the PCI bus layer to put it into D3 in order to take the PCIe link
3025 * down, so as to allow the platform to achieve its minimum low-power
3026 * state (which may not be possible if the link is up).
b97120b1
CH		 3027 *
3028 * If a host memory buffer is enabled, shut down the device as the NVMe
3029 * specification allows the device to access the host memory buffer in
3030 * host DRAM from all power states, but hosts will fail access to DRAM
3031 * during S3.
d916b1be 3032 */
4eaefe8c 3033 if (pm_suspend_via_firmware() || !ctrl->npss ||
cb32de1b 3034 !pcie_aspm_enabled(pdev) ||
b97120b1 3035 ndev->nr_host_mem_descs ||
c1ac9a4b
KB		 3036 (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND))
3037 return nvme_disable_prepare_reset(ndev, true);
d916b1be
KB		 3038
3039 nvme_start_freeze(ctrl);
3040 nvme_wait_freeze(ctrl);
3041 nvme_sync_queues(ctrl);
3042
5d02a5c1 3043 if (ctrl->state != NVME_CTRL_LIVE)
d916b1be
KB		 3044 goto unfreeze;
3045
d916b1be
KB		 3046 ret = nvme_get_power_state(ctrl, &ndev->last_ps);
3047 if (ret < 0)
3048 goto unfreeze;
3049
7cbb5c6f
ML		 3050 /*
3051 * A saved state prevents pci pm from generically controlling the
3052 * device's power. If we're using protocol specific settings, we don't
3053 * want pci interfering.
3054 */
3055 pci_save_state(pdev);
3056
d916b1be
KB		 3057 ret = nvme_set_power_state(ctrl, ctrl->npss);
3058 if (ret < 0)
3059 goto unfreeze;
3060
3061 if (ret) {
7cbb5c6f
ML		 3062 /* discard the saved state */
3063 pci_load_saved_state(pdev, NULL);
3064
d916b1be
KB		 3065 /*
3066 * Clearing npss forces a controller reset on resume. The
05d3046f 3067 * correct value will be rediscovered then.
d916b1be 3068 */
c1ac9a4b 3069 ret = nvme_disable_prepare_reset(ndev, true);
d916b1be 3070 ctrl->npss = 0;
d916b1be 3071 }
d916b1be
KB		 3072unfreeze:
3073 nvme_unfreeze(ctrl);
3074 return ret;
3075}
3076
3077static int nvme_simple_suspend(struct device *dev)
3078{
3079 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
4e523547 3080
c1ac9a4b 3081 return nvme_disable_prepare_reset(ndev, true);
cd638946
KB		 3082}
3083
d916b1be 3084static int nvme_simple_resume(struct device *dev)
cd638946
KB		 3085{
3086 struct pci_dev *pdev = to_pci_dev(dev);
3087 struct nvme_dev *ndev = pci_get_drvdata(pdev);
cd638946 3088
c1ac9a4b 3089 return nvme_try_sched_reset(&ndev->ctrl);
cd638946
KB		 3090}
3091
21774222 3092static const struct dev_pm_ops nvme_dev_pm_ops = {
d916b1be
KB		 3093 .suspend = nvme_suspend,
3094 .resume = nvme_resume,
3095 .freeze = nvme_simple_suspend,
3096 .thaw = nvme_simple_resume,
3097 .poweroff = nvme_simple_suspend,
3098 .restore = nvme_simple_resume,
3099};
3100#endif /* CONFIG_PM_SLEEP */
b60503ba 3101
a0a3408e
KB		 3102static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
3103 pci_channel_state_t state)
3104{
3105 struct nvme_dev *dev = pci_get_drvdata(pdev);
3106
3107 /*
3108 * A frozen channel requires a reset. When detected, this method will
3109 * shutdown the controller to quiesce. The controller will be restarted
3110 * after the slot reset through driver's slot_reset callback.
3111 */
a0a3408e
KB		 3112 switch (state) {
3113 case pci_channel_io_normal:
3114 return PCI_ERS_RESULT_CAN_RECOVER;
3115 case pci_channel_io_frozen:
d011fb31
KB		 3116 dev_warn(dev->ctrl.device,
3117 "frozen state error detected, reset controller\n");
a5cdb68c 3118 nvme_dev_disable(dev, false);
a0a3408e
KB		 3119 return PCI_ERS_RESULT_NEED_RESET;
3120 case pci_channel_io_perm_failure:
d011fb31
KB		 3121 dev_warn(dev->ctrl.device,
3122 "failure state error detected, request disconnect\n");
a0a3408e
KB		 3123 return PCI_ERS_RESULT_DISCONNECT;
3124 }
3125 return PCI_ERS_RESULT_NEED_RESET;
3126}
3127
3128static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
3129{
3130 struct nvme_dev *dev = pci_get_drvdata(pdev);
3131
1b3c47c1 3132 dev_info(dev->ctrl.device, "restart after slot reset\n");
a0a3408e 3133 pci_restore_state(pdev);
d86c4d8e 3134 nvme_reset_ctrl(&dev->ctrl);
a0a3408e
KB		 3135 return PCI_ERS_RESULT_RECOVERED;
3136}
3137
3138static void nvme_error_resume(struct pci_dev *pdev)
3139{
72cd4cc2
KB		 3140 struct nvme_dev *dev = pci_get_drvdata(pdev);
3141
3142 flush_work(&dev->ctrl.reset_work);
a0a3408e
KB		 3143}
3144
1d352035 3145static const struct pci_error_handlers nvme_err_handler = {
b60503ba 3146 .error_detected = nvme_error_detected,
b60503ba
MW		 3147 .slot_reset = nvme_slot_reset,
3148 .resume = nvme_error_resume,
775755ed
CH		 3149 .reset_prepare = nvme_reset_prepare,
3150 .reset_done = nvme_reset_done,
b60503ba
MW		 3151};
3152
6eb0d698 3153static const struct pci_device_id nvme_id_table[] = {
972b13e2 3154 { PCI_VDEVICE(INTEL, 0x0953), /* Intel 750/P3500/P3600/P3700 */
08095e70 3155 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 3156 NVME_QUIRK_DEALLOCATE_ZEROES, },
972b13e2 3157 { PCI_VDEVICE(INTEL, 0x0a53), /* Intel P3520 */
99466e70 3158 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 3159 NVME_QUIRK_DEALLOCATE_ZEROES, },
972b13e2 3160 { PCI_VDEVICE(INTEL, 0x0a54), /* Intel P4500/P4600 */
99466e70 3161 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 3162 NVME_QUIRK_DEALLOCATE_ZEROES, },
972b13e2 3163 { PCI_VDEVICE(INTEL, 0x0a55), /* Dell Express Flash P4600 */
f99cb7af
DWF		 3164 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3165 NVME_QUIRK_DEALLOCATE_ZEROES, },
50af47d0 3166 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */
9abd68ef 3167 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
6c6aa2f2 3168 NVME_QUIRK_MEDIUM_PRIO_SQ |
ce4cc313
DM		 3169 NVME_QUIRK_NO_TEMP_THRESH_CHANGE |
3170 NVME_QUIRK_DISABLE_WRITE_ZEROES, },
6299358d
JD		 3171 { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */
3172 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
540c801c 3173 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */
7b210e4e
CH		 3174 .driver_data = NVME_QUIRK_IDENTIFY_CNS |
3175 NVME_QUIRK_DISABLE_WRITE_ZEROES, },
5bedd3af
CH		 3176 { PCI_DEVICE(0x126f, 0x2263), /* Silicon Motion unidentified */
3177 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST, },
0302ae60
MP		 3178 { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */
3179 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
54adc010
GP		 3180 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
3181 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
8c97eecc
JL		 3182 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */
3183 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
015282c9
WW		 3184 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
3185 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
d554b5e1
MP		 3186 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */
3187 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3188 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */
3189 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
608cc4b1
CH		 3190 { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */
3191 .driver_data = NVME_QUIRK_LIGHTNVM, },
3192 { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */
3193 .driver_data = NVME_QUIRK_LIGHTNVM, },
ea48e877
WX		 3194 { PCI_DEVICE(0x1d1d, 0x2601), /* CNEX Granby */
3195 .driver_data = NVME_QUIRK_LIGHTNVM, },
08b903b5
MN		 3196 { PCI_DEVICE(0x10ec, 0x5762), /* ADATA SX6000LNP */
3197 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
f03e42c6
GC		 3198 { PCI_DEVICE(0x1cc1, 0x8201), /* ADATA SX8200PNP 512GB */
3199 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3200 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
5611ec2b
KHF		 3201 { PCI_DEVICE(0x1c5c, 0x1504), /* SK Hynix PC400 */
3202 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
02ca079c
KHF		 3203 { PCI_DEVICE(0x15b7, 0x2001), /* Sandisk Skyhawk */
3204 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
98f7b86a
AS		 3205 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001),
3206 .driver_data = NVME_QUIRK_SINGLE_VECTOR },
124298bd 3207 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
66341331
BH		 3208 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005),
3209 .driver_data = NVME_QUIRK_SINGLE_VECTOR |
d38e9f04
BH		 3210 NVME_QUIRK_128_BYTES_SQES |
3211 NVME_QUIRK_SHARED_TAGS },
0b85f59d
AS		 3212
3213 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
b60503ba
MW		 3214 { 0, }
3215};
3216MODULE_DEVICE_TABLE(pci, nvme_id_table);
3217
3218static struct pci_driver nvme_driver = {
3219 .name = "nvme",
3220 .id_table = nvme_id_table,
3221 .probe = nvme_probe,
8d85fce7 3222 .remove = nvme_remove,
09ece142 3223 .shutdown = nvme_shutdown,
d916b1be 3224#ifdef CONFIG_PM_SLEEP
cd638946
KB		 3225 .driver = {
3226 .pm = &nvme_dev_pm_ops,
3227 },
d916b1be 3228#endif
74d986ab 3229 .sriov_configure = pci_sriov_configure_simple,
b60503ba
MW		 3230 .err_handler = &nvme_err_handler,
3231};
3232
3233static int __init nvme_init(void)
3234{
81101540
CH		 3235 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
3236 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
3237 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
612b7286 3238 BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2);
17c33167 3239
9a6327d2 3240 return pci_register_driver(&nvme_driver);
b60503ba
MW		 3241}
3242
3243static void __exit nvme_exit(void)
3244{
3245 pci_unregister_driver(&nvme_driver);
03e0f3a6 3246 flush_workqueue(nvme_wq);
b60503ba
MW		 3247}
3248
3249MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3250MODULE_LICENSE("GPL");
c78b4713 3251MODULE_VERSION("1.0");
b60503ba
MW		 3252module_init(nvme_init);
3253module_exit(nvme_exit);
Linux 6.x block layer and io_uring tree(s)