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nvme-pci: shutdown on timeout during deletion
[linux-2.6-block.git] / drivers / nvme / host / pci.c
CommitLineData
5f37396d 1// SPDX-License-Identifier: GPL-2.0
b60503ba
MW		 2/*
3 * NVM Express device driver
6eb0d698 4 * Copyright (c) 2011-2014, Intel Corporation.
b60503ba
MW		 5 */
6
a0a3408e 7#include <linux/aer.h>
18119775 8#include <linux/async.h>
b60503ba 9#include <linux/blkdev.h>
a4aea562 10#include <linux/blk-mq.h>
dca51e78 11#include <linux/blk-mq-pci.h>
ff5350a8 12#include <linux/dmi.h>
b60503ba
MW		 13#include <linux/init.h>
14#include <linux/interrupt.h>
15#include <linux/io.h>
b60503ba
MW		 16#include <linux/mm.h>
17#include <linux/module.h>
77bf25ea 18#include <linux/mutex.h>
d0877473 19#include <linux/once.h>
b60503ba 20#include <linux/pci.h>
e1e5e564 21#include <linux/t10-pi.h>
b60503ba 22#include <linux/types.h>
2f8e2c87 23#include <linux/io-64-nonatomic-lo-hi.h>
a98e58e5 24#include <linux/sed-opal.h>
0f238ff5 25#include <linux/pci-p2pdma.h>
797a796a 26
604c01d5 27#include "trace.h"
f11bb3e2
CH		 28#include "nvme.h"
29
b60503ba
MW		 30#define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
31#define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
c965809c 32
a7a7cbe3 33#define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc))
9d43cf64 34
943e942e
JA		 35/*
36 * These can be higher, but we need to ensure that any command doesn't
37 * require an sg allocation that needs more than a page of data.
38 */
39#define NVME_MAX_KB_SZ 4096
40#define NVME_MAX_SEGS 127
41
58ffacb5
MW		 42static int use_threaded_interrupts;
43module_param(use_threaded_interrupts, int, 0);
44
8ffaadf7 45static bool use_cmb_sqes = true;
69f4eb9f 46module_param(use_cmb_sqes, bool, 0444);
8ffaadf7
JD		 47MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
48
87ad72a5
CH		 49static unsigned int max_host_mem_size_mb = 128;
50module_param(max_host_mem_size_mb, uint, 0444);
51MODULE_PARM_DESC(max_host_mem_size_mb,
52 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
1fa6aead 53
a7a7cbe3
CK		 54static unsigned int sgl_threshold = SZ_32K;
55module_param(sgl_threshold, uint, 0644);
56MODULE_PARM_DESC(sgl_threshold,
57 "Use SGLs when average request segment size is larger or equal to "
58 "this size. Use 0 to disable SGLs.");
59
b27c1e68 60static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
61static const struct kernel_param_ops io_queue_depth_ops = {
62 .set = io_queue_depth_set,
63 .get = param_get_int,
64};
65
66static int io_queue_depth = 1024;
67module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
68MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2");
69
3b6592f7
JA		 70static int queue_count_set(const char *val, const struct kernel_param *kp);
71static const struct kernel_param_ops queue_count_ops = {
72 .set = queue_count_set,
73 .get = param_get_int,
74};
75
76static int write_queues;
77module_param_cb(write_queues, &queue_count_ops, &write_queues, 0644);
78MODULE_PARM_DESC(write_queues,
79 "Number of queues to use for writes. If not set, reads and writes "
80 "will share a queue set.");
81
a4668d9b 82static int poll_queues = 0;
4b04cc6a
JA		 83module_param_cb(poll_queues, &queue_count_ops, &poll_queues, 0644);
84MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO.");
85
1c63dc66
CH		 86struct nvme_dev;
87struct nvme_queue;
b3fffdef 88
a5cdb68c 89static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
8fae268b 90static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode);
d4b4ff8e 91
1c63dc66
CH		 92/*
93 * Represents an NVM Express device. Each nvme_dev is a PCI function.
94 */
95struct nvme_dev {
147b27e4 96 struct nvme_queue *queues;
1c63dc66
CH		 97 struct blk_mq_tag_set tagset;
98 struct blk_mq_tag_set admin_tagset;
99 u32 __iomem *dbs;
100 struct device *dev;
101 struct dma_pool *prp_page_pool;
102 struct dma_pool *prp_small_pool;
1c63dc66
CH		 103 unsigned online_queues;
104 unsigned max_qid;
e20ba6e1 105 unsigned io_queues[HCTX_MAX_TYPES];
22b55601 106 unsigned int num_vecs;
1c63dc66
CH		 107 int q_depth;
108 u32 db_stride;
1c63dc66 109 void __iomem *bar;
97f6ef64 110 unsigned long bar_mapped_size;
5c8809e6 111 struct work_struct remove_work;
77bf25ea 112 struct mutex shutdown_lock;
1c63dc66 113 bool subsystem;
1c63dc66 114 u64 cmb_size;
0f238ff5 115 bool cmb_use_sqes;
1c63dc66 116 u32 cmbsz;
202021c1 117 u32 cmbloc;
1c63dc66 118 struct nvme_ctrl ctrl;
87ad72a5 119
943e942e
JA		 120 mempool_t *iod_mempool;
121
87ad72a5 122 /* shadow doorbell buffer support: */
f9f38e33
HK		 123 u32 *dbbuf_dbs;
124 dma_addr_t dbbuf_dbs_dma_addr;
125 u32 *dbbuf_eis;
126 dma_addr_t dbbuf_eis_dma_addr;
87ad72a5
CH		 127
128 /* host memory buffer support: */
129 u64 host_mem_size;
130 u32 nr_host_mem_descs;
4033f35d 131 dma_addr_t host_mem_descs_dma;
87ad72a5
CH		 132 struct nvme_host_mem_buf_desc *host_mem_descs;
133 void **host_mem_desc_bufs;
4d115420 134};
1fa6aead 135
b27c1e68 136static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
137{
138 int n = 0, ret;
139
140 ret = kstrtoint(val, 10, &n);
141 if (ret != 0 || n < 2)
142 return -EINVAL;
143
144 return param_set_int(val, kp);
145}
146
3b6592f7
JA		 147static int queue_count_set(const char *val, const struct kernel_param *kp)
148{
149 int n = 0, ret;
150
151 ret = kstrtoint(val, 10, &n);
e895fedf
BVA		 152 if (ret)
153 return ret;
3b6592f7
JA		 154 if (n > num_possible_cpus())
155 n = num_possible_cpus();
156
157 return param_set_int(val, kp);
158}
159
f9f38e33
HK		 160static inline unsigned int sq_idx(unsigned int qid, u32 stride)
161{
162 return qid * 2 * stride;
163}
164
165static inline unsigned int cq_idx(unsigned int qid, u32 stride)
166{
167 return (qid * 2 + 1) * stride;
168}
169
1c63dc66
CH		 170static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
171{
172 return container_of(ctrl, struct nvme_dev, ctrl);
173}
174
b60503ba
MW		 175/*
176 * An NVM Express queue. Each device has at least two (one for admin
177 * commands and one for I/O commands).
178 */
179struct nvme_queue {
091b6092 180 struct nvme_dev *dev;
1ab0cd69 181 spinlock_t sq_lock;
b60503ba 182 struct nvme_command *sq_cmds;
3a7afd8e
CH		 183 /* only used for poll queues: */
184 spinlock_t cq_poll_lock ____cacheline_aligned_in_smp;
b60503ba 185 volatile struct nvme_completion *cqes;
42483228 186 struct blk_mq_tags **tags;
b60503ba
MW		 187 dma_addr_t sq_dma_addr;
188 dma_addr_t cq_dma_addr;
b60503ba
MW		 189 u32 __iomem *q_db;
190 u16 q_depth;
7c349dde 191 u16 cq_vector;
b60503ba 192 u16 sq_tail;
04f3eafd 193 u16 last_sq_tail;
b60503ba 194 u16 cq_head;
68fa9dbe 195 u16 last_cq_head;
c30341dc 196 u16 qid;
e9539f47 197 u8 cq_phase;
4e224106
CH		 198 unsigned long flags;
199#define NVMEQ_ENABLED 0
63223078 200#define NVMEQ_SQ_CMB 1
d1ed6aa1 201#define NVMEQ_DELETE_ERROR 2
7c349dde 202#define NVMEQ_POLLED 3
f9f38e33
HK		 203 u32 *dbbuf_sq_db;
204 u32 *dbbuf_cq_db;
205 u32 *dbbuf_sq_ei;
206 u32 *dbbuf_cq_ei;
d1ed6aa1 207 struct completion delete_done;
b60503ba
MW		 208};
209
71bd150c 210/*
9b048119
CH		 211 * The nvme_iod describes the data in an I/O.
212 *
213 * The sg pointer contains the list of PRP/SGL chunk allocations in addition
214 * to the actual struct scatterlist.
71bd150c
CH		 215 */
216struct nvme_iod {
d49187e9 217 struct nvme_request req;
f4800d6d 218 struct nvme_queue *nvmeq;
a7a7cbe3 219 bool use_sgl;
f4800d6d 220 int aborted;
71bd150c 221 int npages; /* In the PRP list. 0 means small pool in use */
71bd150c 222 int nents; /* Used in scatterlist */
71bd150c 223 dma_addr_t first_dma;
dff824b2 224 unsigned int dma_len; /* length of single DMA segment mapping */
783b94bd 225 dma_addr_t meta_dma;
f4800d6d 226 struct scatterlist *sg;
b60503ba
MW		 227};
228
229/*
230 * Check we didin't inadvertently grow the command struct
231 */
232static inline void _nvme_check_size(void)
233{
234 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
235 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
236 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
237 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
238 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
f8ebf840 239 BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
c30341dc 240 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
b60503ba 241 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
0add5e8e
JT		 242 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != NVME_IDENTIFY_DATA_SIZE);
243 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != NVME_IDENTIFY_DATA_SIZE);
b60503ba 244 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
6ecec745 245 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
f9f38e33
HK		 246 BUILD_BUG_ON(sizeof(struct nvme_dbbuf) != 64);
247}
248
3b6592f7
JA		 249static unsigned int max_io_queues(void)
250{
4b04cc6a 251 return num_possible_cpus() + write_queues + poll_queues;
3b6592f7
JA		 252}
253
254static unsigned int max_queue_count(void)
255{
256 /* IO queues + admin queue */
257 return 1 + max_io_queues();
258}
259
f9f38e33
HK		 260static inline unsigned int nvme_dbbuf_size(u32 stride)
261{
3b6592f7 262 return (max_queue_count() * 8 * stride);
f9f38e33
HK		 263}
264
265static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
266{
267 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
268
269 if (dev->dbbuf_dbs)
270 return 0;
271
272 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
273 &dev->dbbuf_dbs_dma_addr,
274 GFP_KERNEL);
275 if (!dev->dbbuf_dbs)
276 return -ENOMEM;
277 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
278 &dev->dbbuf_eis_dma_addr,
279 GFP_KERNEL);
280 if (!dev->dbbuf_eis) {
281 dma_free_coherent(dev->dev, mem_size,
282 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
283 dev->dbbuf_dbs = NULL;
284 return -ENOMEM;
285 }
286
287 return 0;
288}
289
290static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
291{
292 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
293
294 if (dev->dbbuf_dbs) {
295 dma_free_coherent(dev->dev, mem_size,
296 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
297 dev->dbbuf_dbs = NULL;
298 }
299 if (dev->dbbuf_eis) {
300 dma_free_coherent(dev->dev, mem_size,
301 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
302 dev->dbbuf_eis = NULL;
303 }
304}
305
306static void nvme_dbbuf_init(struct nvme_dev *dev,
307 struct nvme_queue *nvmeq, int qid)
308{
309 if (!dev->dbbuf_dbs || !qid)
310 return;
311
312 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
313 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
314 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
315 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
316}
317
318static void nvme_dbbuf_set(struct nvme_dev *dev)
319{
320 struct nvme_command c;
321
322 if (!dev->dbbuf_dbs)
323 return;
324
325 memset(&c, 0, sizeof(c));
326 c.dbbuf.opcode = nvme_admin_dbbuf;
327 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
328 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
329
330 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
9bdcfb10 331 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
f9f38e33
HK		 332 /* Free memory and continue on */
333 nvme_dbbuf_dma_free(dev);
334 }
335}
336
337static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
338{
339 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
340}
341
342/* Update dbbuf and return true if an MMIO is required */
343static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
344 volatile u32 *dbbuf_ei)
345{
346 if (dbbuf_db) {
347 u16 old_value;
348
349 /*
350 * Ensure that the queue is written before updating
351 * the doorbell in memory
352 */
353 wmb();
354
355 old_value = *dbbuf_db;
356 *dbbuf_db = value;
357
f1ed3df2
MW		 358 /*
359 * Ensure that the doorbell is updated before reading the event
360 * index from memory. The controller needs to provide similar
361 * ordering to ensure the envent index is updated before reading
362 * the doorbell.
363 */
364 mb();
365
f9f38e33
HK		 366 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value))
367 return false;
368 }
369
370 return true;
b60503ba
MW		 371}
372
ac3dd5bd
JA		 373/*
374 * Will slightly overestimate the number of pages needed. This is OK
375 * as it only leads to a small amount of wasted memory for the lifetime of
376 * the I/O.
377 */
378static int nvme_npages(unsigned size, struct nvme_dev *dev)
379{
5fd4ce1b
CH		 380 unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size,
381 dev->ctrl.page_size);
ac3dd5bd
JA		 382 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
383}
384
a7a7cbe3
CK		 385/*
386 * Calculates the number of pages needed for the SGL segments. For example a 4k
387 * page can accommodate 256 SGL descriptors.
388 */
389static int nvme_pci_npages_sgl(unsigned int num_seg)
ac3dd5bd 390{
a7a7cbe3 391 return DIV_ROUND_UP(num_seg * sizeof(struct nvme_sgl_desc), PAGE_SIZE);
f4800d6d 392}
ac3dd5bd 393
a7a7cbe3
CK		 394static unsigned int nvme_pci_iod_alloc_size(struct nvme_dev *dev,
395 unsigned int size, unsigned int nseg, bool use_sgl)
f4800d6d 396{
a7a7cbe3
CK		 397 size_t alloc_size;
398
399 if (use_sgl)
400 alloc_size = sizeof(__le64 *) * nvme_pci_npages_sgl(nseg);
401 else
402 alloc_size = sizeof(__le64 *) * nvme_npages(size, dev);
403
404 return alloc_size + sizeof(struct scatterlist) * nseg;
f4800d6d 405}
ac3dd5bd 406
a4aea562
MB		 407static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
408 unsigned int hctx_idx)
e85248e5 409{
a4aea562 410 struct nvme_dev *dev = data;
147b27e4 411 struct nvme_queue *nvmeq = &dev->queues[0];
a4aea562 412
42483228
KB		 413 WARN_ON(hctx_idx != 0);
414 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
415 WARN_ON(nvmeq->tags);
416
a4aea562 417 hctx->driver_data = nvmeq;
42483228 418 nvmeq->tags = &dev->admin_tagset.tags[0];
a4aea562 419 return 0;
e85248e5
MW		 420}
421
4af0e21c
KB		 422static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
423{
424 struct nvme_queue *nvmeq = hctx->driver_data;
425
426 nvmeq->tags = NULL;
427}
428
a4aea562
MB		 429static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
430 unsigned int hctx_idx)
b60503ba 431{
a4aea562 432 struct nvme_dev *dev = data;
147b27e4 433 struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
a4aea562 434
42483228
KB		 435 if (!nvmeq->tags)
436 nvmeq->tags = &dev->tagset.tags[hctx_idx];
b60503ba 437
42483228 438 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
a4aea562
MB		 439 hctx->driver_data = nvmeq;
440 return 0;
b60503ba
MW		 441}
442
d6296d39
CH		 443static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req,
444 unsigned int hctx_idx, unsigned int numa_node)
b60503ba 445{
d6296d39 446 struct nvme_dev *dev = set->driver_data;
f4800d6d 447 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
0350815a 448 int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0;
147b27e4 449 struct nvme_queue *nvmeq = &dev->queues[queue_idx];
a4aea562
MB		 450
451 BUG_ON(!nvmeq);
f4800d6d 452 iod->nvmeq = nvmeq;
59e29ce6
SG		 453
454 nvme_req(req)->ctrl = &dev->ctrl;
a4aea562
MB		 455 return 0;
456}
457
3b6592f7
JA		 458static int queue_irq_offset(struct nvme_dev *dev)
459{
460 /* if we have more than 1 vec, admin queue offsets us by 1 */
461 if (dev->num_vecs > 1)
462 return 1;
463
464 return 0;
465}
466
dca51e78
CH		 467static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
468{
469 struct nvme_dev *dev = set->driver_data;
3b6592f7
JA		 470 int i, qoff, offset;
471
472 offset = queue_irq_offset(dev);
473 for (i = 0, qoff = 0; i < set->nr_maps; i++) {
474 struct blk_mq_queue_map *map = &set->map[i];
475
476 map->nr_queues = dev->io_queues[i];
477 if (!map->nr_queues) {
e20ba6e1 478 BUG_ON(i == HCTX_TYPE_DEFAULT);
7e849dd9 479 continue;
3b6592f7
JA		 480 }
481
4b04cc6a
JA		 482 /*
483 * The poll queue(s) doesn't have an IRQ (and hence IRQ
484 * affinity), so use the regular blk-mq cpu mapping
485 */
3b6592f7 486 map->queue_offset = qoff;
e20ba6e1 487 if (i != HCTX_TYPE_POLL)
4b04cc6a
JA		 488 blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset);
489 else
490 blk_mq_map_queues(map);
3b6592f7
JA		 491 qoff += map->nr_queues;
492 offset += map->nr_queues;
493 }
494
495 return 0;
dca51e78
CH		 496}
497
04f3eafd
JA		 498/*
499 * Write sq tail if we are asked to, or if the next command would wrap.
500 */
501static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq)
502{
503 if (!write_sq) {
504 u16 next_tail = nvmeq->sq_tail + 1;
505
506 if (next_tail == nvmeq->q_depth)
507 next_tail = 0;
508 if (next_tail != nvmeq->last_sq_tail)
509 return;
510 }
511
512 if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail,
513 nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei))
514 writel(nvmeq->sq_tail, nvmeq->q_db);
515 nvmeq->last_sq_tail = nvmeq->sq_tail;
516}
517
b60503ba 518/**
90ea5ca4 519 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
b60503ba
MW		 520 * @nvmeq: The queue to use
521 * @cmd: The command to send
04f3eafd 522 * @write_sq: whether to write to the SQ doorbell
b60503ba 523 */
04f3eafd
JA		 524static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd,
525 bool write_sq)
b60503ba 526{
90ea5ca4 527 spin_lock(&nvmeq->sq_lock);
0f238ff5 528 memcpy(&nvmeq->sq_cmds[nvmeq->sq_tail], cmd, sizeof(*cmd));
90ea5ca4
CH		 529 if (++nvmeq->sq_tail == nvmeq->q_depth)
530 nvmeq->sq_tail = 0;
04f3eafd
JA		 531 nvme_write_sq_db(nvmeq, write_sq);
532 spin_unlock(&nvmeq->sq_lock);
533}
534
535static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx)
536{
537 struct nvme_queue *nvmeq = hctx->driver_data;
538
539 spin_lock(&nvmeq->sq_lock);
540 if (nvmeq->sq_tail != nvmeq->last_sq_tail)
541 nvme_write_sq_db(nvmeq, true);
90ea5ca4 542 spin_unlock(&nvmeq->sq_lock);
b60503ba
MW		 543}
544
a7a7cbe3 545static void **nvme_pci_iod_list(struct request *req)
b60503ba 546{
f4800d6d 547 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3 548 return (void **)(iod->sg + blk_rq_nr_phys_segments(req));
b60503ba
MW		 549}
550
955b1b5a
MI		 551static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req)
552{
553 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
20469a37 554 int nseg = blk_rq_nr_phys_segments(req);
955b1b5a
MI		 555 unsigned int avg_seg_size;
556
20469a37
KB		 557 if (nseg == 0)
558 return false;
559
560 avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
955b1b5a
MI		 561
562 if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1))))
563 return false;
564 if (!iod->nvmeq->qid)
565 return false;
566 if (!sgl_threshold || avg_seg_size < sgl_threshold)
567 return false;
568 return true;
569}
570
7fe07d14 571static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
b60503ba 572{
f4800d6d 573 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
7fe07d14
CH		 574 enum dma_data_direction dma_dir = rq_data_dir(req) ?
575 DMA_TO_DEVICE : DMA_FROM_DEVICE;
a7a7cbe3
CK		 576 const int last_prp = dev->ctrl.page_size / sizeof(__le64) - 1;
577 dma_addr_t dma_addr = iod->first_dma, next_dma_addr;
eca18b23 578 int i;
eca18b23 579
dff824b2
CH		 580 if (iod->dma_len) {
581 dma_unmap_page(dev->dev, dma_addr, iod->dma_len, dma_dir);
582 return;
7fe07d14
CH		 583 }
584
dff824b2
CH		 585 WARN_ON_ONCE(!iod->nents);
586
587 /* P2PDMA requests do not need to be unmapped */
588 if (!is_pci_p2pdma_page(sg_page(iod->sg)))
589 dma_unmap_sg(dev->dev, iod->sg, iod->nents, rq_dma_dir(req));
590
591
eca18b23 592 if (iod->npages == 0)
a7a7cbe3
CK		 593 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0],
594 dma_addr);
595
eca18b23 596 for (i = 0; i < iod->npages; i++) {
a7a7cbe3
CK		 597 void *addr = nvme_pci_iod_list(req)[i];
598
599 if (iod->use_sgl) {
600 struct nvme_sgl_desc *sg_list = addr;
601
602 next_dma_addr =
603 le64_to_cpu((sg_list[SGES_PER_PAGE - 1]).addr);
604 } else {
605 __le64 *prp_list = addr;
606
607 next_dma_addr = le64_to_cpu(prp_list[last_prp]);
608 }
609
610 dma_pool_free(dev->prp_page_pool, addr, dma_addr);
611 dma_addr = next_dma_addr;
eca18b23 612 }
ac3dd5bd 613
d43f1ccf 614 mempool_free(iod->sg, dev->iod_mempool);
b4ff9c8d
KB		 615}
616
d0877473
KB		 617static void nvme_print_sgl(struct scatterlist *sgl, int nents)
618{
619 int i;
620 struct scatterlist *sg;
621
622 for_each_sg(sgl, sg, nents, i) {
623 dma_addr_t phys = sg_phys(sg);
624 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
625 "dma_address:%pad dma_length:%d\n",
626 i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
627 sg_dma_len(sg));
628 }
629}
630
a7a7cbe3
CK		 631static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
632 struct request *req, struct nvme_rw_command *cmnd)
ff22b54f 633{
f4800d6d 634 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
99802a7a 635 struct dma_pool *pool;
b131c61d 636 int length = blk_rq_payload_bytes(req);
eca18b23 637 struct scatterlist *sg = iod->sg;
ff22b54f
MW		 638 int dma_len = sg_dma_len(sg);
639 u64 dma_addr = sg_dma_address(sg);
5fd4ce1b 640 u32 page_size = dev->ctrl.page_size;
f137e0f1 641 int offset = dma_addr & (page_size - 1);
e025344c 642 __le64 *prp_list;
a7a7cbe3 643 void **list = nvme_pci_iod_list(req);
e025344c 644 dma_addr_t prp_dma;
eca18b23 645 int nprps, i;
ff22b54f 646
1d090624 647 length -= (page_size - offset);
5228b328
JS		 648 if (length <= 0) {
649 iod->first_dma = 0;
a7a7cbe3 650 goto done;
5228b328 651 }
ff22b54f 652
1d090624 653 dma_len -= (page_size - offset);
ff22b54f 654 if (dma_len) {
1d090624 655 dma_addr += (page_size - offset);
ff22b54f
MW		 656 } else {
657 sg = sg_next(sg);
658 dma_addr = sg_dma_address(sg);
659 dma_len = sg_dma_len(sg);
660 }
661
1d090624 662 if (length <= page_size) {
edd10d33 663 iod->first_dma = dma_addr;
a7a7cbe3 664 goto done;
e025344c
SMM		 665 }
666
1d090624 667 nprps = DIV_ROUND_UP(length, page_size);
99802a7a
MW		 668 if (nprps <= (256 / 8)) {
669 pool = dev->prp_small_pool;
eca18b23 670 iod->npages = 0;
99802a7a
MW		 671 } else {
672 pool = dev->prp_page_pool;
eca18b23 673 iod->npages = 1;
99802a7a
MW		 674 }
675
69d2b571 676 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
b77954cb 677 if (!prp_list) {
edd10d33 678 iod->first_dma = dma_addr;
eca18b23 679 iod->npages = -1;
86eea289 680 return BLK_STS_RESOURCE;
b77954cb 681 }
eca18b23
MW		 682 list[0] = prp_list;
683 iod->first_dma = prp_dma;
e025344c
SMM		 684 i = 0;
685 for (;;) {
1d090624 686 if (i == page_size >> 3) {
e025344c 687 __le64 *old_prp_list = prp_list;
69d2b571 688 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
eca18b23 689 if (!prp_list)
86eea289 690 return BLK_STS_RESOURCE;
eca18b23 691 list[iod->npages++] = prp_list;
7523d834
MW		 692 prp_list[0] = old_prp_list[i - 1];
693 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
694 i = 1;
e025344c
SMM		 695 }
696 prp_list[i++] = cpu_to_le64(dma_addr);
1d090624
KB		 697 dma_len -= page_size;
698 dma_addr += page_size;
699 length -= page_size;
e025344c
SMM		 700 if (length <= 0)
701 break;
702 if (dma_len > 0)
703 continue;
86eea289
KB		 704 if (unlikely(dma_len < 0))
705 goto bad_sgl;
e025344c
SMM		 706 sg = sg_next(sg);
707 dma_addr = sg_dma_address(sg);
708 dma_len = sg_dma_len(sg);
ff22b54f
MW		 709 }
710
a7a7cbe3
CK		 711done:
712 cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
713 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
714
86eea289
KB		 715 return BLK_STS_OK;
716
717 bad_sgl:
d0877473
KB		 718 WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents),
719 "Invalid SGL for payload:%d nents:%d\n",
720 blk_rq_payload_bytes(req), iod->nents);
86eea289 721 return BLK_STS_IOERR;
ff22b54f
MW		 722}
723
a7a7cbe3
CK		 724static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
725 struct scatterlist *sg)
726{
727 sge->addr = cpu_to_le64(sg_dma_address(sg));
728 sge->length = cpu_to_le32(sg_dma_len(sg));
729 sge->type = NVME_SGL_FMT_DATA_DESC << 4;
730}
731
732static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
733 dma_addr_t dma_addr, int entries)
734{
735 sge->addr = cpu_to_le64(dma_addr);
736 if (entries < SGES_PER_PAGE) {
737 sge->length = cpu_to_le32(entries * sizeof(*sge));
738 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
739 } else {
740 sge->length = cpu_to_le32(PAGE_SIZE);
741 sge->type = NVME_SGL_FMT_SEG_DESC << 4;
742 }
743}
744
745static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
b0f2853b 746 struct request *req, struct nvme_rw_command *cmd, int entries)
a7a7cbe3
CK		 747{
748 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3
CK		 749 struct dma_pool *pool;
750 struct nvme_sgl_desc *sg_list;
751 struct scatterlist *sg = iod->sg;
a7a7cbe3 752 dma_addr_t sgl_dma;
b0f2853b 753 int i = 0;
a7a7cbe3 754
a7a7cbe3
CK		 755 /* setting the transfer type as SGL */
756 cmd->flags = NVME_CMD_SGL_METABUF;
757
b0f2853b 758 if (entries == 1) {
a7a7cbe3
CK		 759 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
760 return BLK_STS_OK;
761 }
762
763 if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
764 pool = dev->prp_small_pool;
765 iod->npages = 0;
766 } else {
767 pool = dev->prp_page_pool;
768 iod->npages = 1;
769 }
770
771 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
772 if (!sg_list) {
773 iod->npages = -1;
774 return BLK_STS_RESOURCE;
775 }
776
777 nvme_pci_iod_list(req)[0] = sg_list;
778 iod->first_dma = sgl_dma;
779
780 nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
781
782 do {
783 if (i == SGES_PER_PAGE) {
784 struct nvme_sgl_desc *old_sg_desc = sg_list;
785 struct nvme_sgl_desc *link = &old_sg_desc[i - 1];
786
787 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
788 if (!sg_list)
789 return BLK_STS_RESOURCE;
790
791 i = 0;
792 nvme_pci_iod_list(req)[iod->npages++] = sg_list;
793 sg_list[i++] = *link;
794 nvme_pci_sgl_set_seg(link, sgl_dma, entries);
795 }
796
797 nvme_pci_sgl_set_data(&sg_list[i++], sg);
a7a7cbe3 798 sg = sg_next(sg);
b0f2853b 799 } while (--entries > 0);
a7a7cbe3 800
a7a7cbe3
CK		 801 return BLK_STS_OK;
802}
803
dff824b2
CH		 804static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev,
805 struct request *req, struct nvme_rw_command *cmnd,
806 struct bio_vec *bv)
807{
808 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
809 unsigned int first_prp_len = dev->ctrl.page_size - bv->bv_offset;
810
811 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
812 if (dma_mapping_error(dev->dev, iod->first_dma))
813 return BLK_STS_RESOURCE;
814 iod->dma_len = bv->bv_len;
815
816 cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma);
817 if (bv->bv_len > first_prp_len)
818 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len);
819 return 0;
820}
821
29791057
CH		 822static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev,
823 struct request *req, struct nvme_rw_command *cmnd,
824 struct bio_vec *bv)
825{
826 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
827
828 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
829 if (dma_mapping_error(dev->dev, iod->first_dma))
830 return BLK_STS_RESOURCE;
831 iod->dma_len = bv->bv_len;
832
049bf372 833 cmnd->flags = NVME_CMD_SGL_METABUF;
29791057
CH		 834 cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma);
835 cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len);
836 cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4;
837 return 0;
838}
839
fc17b653 840static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
b131c61d 841 struct nvme_command *cmnd)
d29ec824 842{
f4800d6d 843 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
70479b71 844 blk_status_t ret = BLK_STS_RESOURCE;
b0f2853b 845 int nr_mapped;
d29ec824 846
dff824b2
CH		 847 if (blk_rq_nr_phys_segments(req) == 1) {
848 struct bio_vec bv = req_bvec(req);
849
850 if (!is_pci_p2pdma_page(bv.bv_page)) {
851 if (bv.bv_offset + bv.bv_len <= dev->ctrl.page_size * 2)
852 return nvme_setup_prp_simple(dev, req,
853 &cmnd->rw, &bv);
29791057
CH		 854
855 if (iod->nvmeq->qid &&
856 dev->ctrl.sgls & ((1 << 0) | (1 << 1)))
857 return nvme_setup_sgl_simple(dev, req,
858 &cmnd->rw, &bv);
dff824b2
CH		 859 }
860 }
861
862 iod->dma_len = 0;
d43f1ccf
CH		 863 iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC);
864 if (!iod->sg)
865 return BLK_STS_RESOURCE;
f9d03f96 866 sg_init_table(iod->sg, blk_rq_nr_phys_segments(req));
70479b71 867 iod->nents = blk_rq_map_sg(req->q, req, iod->sg);
ba1ca37e
CH		 868 if (!iod->nents)
869 goto out;
d29ec824 870
e0596ab2
LG		 871 if (is_pci_p2pdma_page(sg_page(iod->sg)))
872 nr_mapped = pci_p2pdma_map_sg(dev->dev, iod->sg, iod->nents,
70479b71 873 rq_dma_dir(req));
e0596ab2
LG		 874 else
875 nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents,
70479b71 876 rq_dma_dir(req), DMA_ATTR_NO_WARN);
b0f2853b 877 if (!nr_mapped)
ba1ca37e 878 goto out;
d29ec824 879
70479b71 880 iod->use_sgl = nvme_pci_use_sgls(dev, req);
955b1b5a 881 if (iod->use_sgl)
b0f2853b 882 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped);
a7a7cbe3
CK		 883 else
884 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
4aedb705 885out:
86eea289 886 if (ret != BLK_STS_OK)
4aedb705
CH		 887 nvme_unmap_data(dev, req);
888 return ret;
889}
3045c0d0 890
4aedb705
CH		 891static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req,
892 struct nvme_command *cmnd)
893{
894 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
00df5cb4 895
4aedb705
CH		 896 iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req),
897 rq_dma_dir(req), 0);
898 if (dma_mapping_error(dev->dev, iod->meta_dma))
899 return BLK_STS_IOERR;
900 cmnd->rw.metadata = cpu_to_le64(iod->meta_dma);
901 return 0;
00df5cb4
MW		 902}
903
d29ec824
CH		 904/*
905 * NOTE: ns is NULL when called on the admin queue.
906 */
fc17b653 907static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
a4aea562 908 const struct blk_mq_queue_data *bd)
edd10d33 909{
a4aea562
MB		 910 struct nvme_ns *ns = hctx->queue->queuedata;
911 struct nvme_queue *nvmeq = hctx->driver_data;
d29ec824 912 struct nvme_dev *dev = nvmeq->dev;
a4aea562 913 struct request *req = bd->rq;
9b048119 914 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
ba1ca37e 915 struct nvme_command cmnd;
ebe6d874 916 blk_status_t ret;
e1e5e564 917
9b048119
CH		 918 iod->aborted = 0;
919 iod->npages = -1;
920 iod->nents = 0;
921
d1f06f4a
JA		 922 /*
923 * We should not need to do this, but we're still using this to
924 * ensure we can drain requests on a dying queue.
925 */
4e224106 926 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
d1f06f4a
JA		 927 return BLK_STS_IOERR;
928
f9d03f96 929 ret = nvme_setup_cmd(ns, req, &cmnd);
fc17b653 930 if (ret)
f4800d6d 931 return ret;
a4aea562 932
fc17b653 933 if (blk_rq_nr_phys_segments(req)) {
b131c61d 934 ret = nvme_map_data(dev, req, &cmnd);
fc17b653 935 if (ret)
9b048119 936 goto out_free_cmd;
fc17b653 937 }
a4aea562 938
4aedb705
CH		 939 if (blk_integrity_rq(req)) {
940 ret = nvme_map_metadata(dev, req, &cmnd);
941 if (ret)
942 goto out_unmap_data;
943 }
944
aae239e1 945 blk_mq_start_request(req);
04f3eafd 946 nvme_submit_cmd(nvmeq, &cmnd, bd->last);
fc17b653 947 return BLK_STS_OK;
4aedb705
CH		 948out_unmap_data:
949 nvme_unmap_data(dev, req);
f9d03f96
CH		 950out_free_cmd:
951 nvme_cleanup_cmd(req);
ba1ca37e 952 return ret;
b60503ba 953}
e1e5e564 954
77f02a7a 955static void nvme_pci_complete_rq(struct request *req)
eee417b0 956{
f4800d6d 957 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
4aedb705 958 struct nvme_dev *dev = iod->nvmeq->dev;
a4aea562 959
915f04c9 960 nvme_cleanup_cmd(req);
4aedb705
CH		 961 if (blk_integrity_rq(req))
962 dma_unmap_page(dev->dev, iod->meta_dma,
963 rq_integrity_vec(req)->bv_len, rq_data_dir(req));
b15c592d 964 if (blk_rq_nr_phys_segments(req))
4aedb705 965 nvme_unmap_data(dev, req);
77f02a7a 966 nvme_complete_rq(req);
b60503ba
MW		 967}
968
d783e0bd 969/* We read the CQE phase first to check if the rest of the entry is valid */
750dde44 970static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq)
d783e0bd 971{
750dde44
CH		 972 return (le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) ==
973 nvmeq->cq_phase;
d783e0bd
MR		 974}
975
eb281c82 976static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
b60503ba 977{
eb281c82 978 u16 head = nvmeq->cq_head;
adf68f21 979
397c699f
KB		 980 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
981 nvmeq->dbbuf_cq_ei))
982 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
eb281c82 983}
aae239e1 984
5cb525c8 985static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx)
83a12fb7 986{
5cb525c8 987 volatile struct nvme_completion *cqe = &nvmeq->cqes[idx];
83a12fb7 988 struct request *req;
adf68f21 989
83a12fb7
SG		 990 if (unlikely(cqe->command_id >= nvmeq->q_depth)) {
991 dev_warn(nvmeq->dev->ctrl.device,
992 "invalid id %d completed on queue %d\n",
993 cqe->command_id, le16_to_cpu(cqe->sq_id));
994 return;
b60503ba
MW		 995 }
996
83a12fb7
SG		 997 /*
998 * AEN requests are special as they don't time out and can
999 * survive any kind of queue freeze and often don't respond to
1000 * aborts. We don't even bother to allocate a struct request
1001 * for them but rather special case them here.
1002 */
1003 if (unlikely(nvmeq->qid == 0 &&
38dabe21 1004 cqe->command_id >= NVME_AQ_BLK_MQ_DEPTH)) {
83a12fb7
SG		 1005 nvme_complete_async_event(&nvmeq->dev->ctrl,
1006 cqe->status, &cqe->result);
a0fa9647 1007 return;
83a12fb7 1008 }
b60503ba 1009
83a12fb7 1010 req = blk_mq_tag_to_rq(*nvmeq->tags, cqe->command_id);
604c01d5 1011 trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail);
83a12fb7
SG		 1012 nvme_end_request(req, cqe->status, cqe->result);
1013}
b60503ba 1014
5cb525c8 1015static void nvme_complete_cqes(struct nvme_queue *nvmeq, u16 start, u16 end)
b60503ba 1016{
5cb525c8
JA		 1017 while (start != end) {
1018 nvme_handle_cqe(nvmeq, start);
1019 if (++start == nvmeq->q_depth)
1020 start = 0;
1021 }
1022}
adf68f21 1023
5cb525c8
JA		 1024static inline void nvme_update_cq_head(struct nvme_queue *nvmeq)
1025{
dcca1662 1026 if (nvmeq->cq_head == nvmeq->q_depth - 1) {
5cb525c8
JA		 1027 nvmeq->cq_head = 0;
1028 nvmeq->cq_phase = !nvmeq->cq_phase;
dcca1662
HY		 1029 } else {
1030 nvmeq->cq_head++;
b60503ba 1031 }
a0fa9647
JA		 1032}
1033
1052b8ac
JA		 1034static inline int nvme_process_cq(struct nvme_queue *nvmeq, u16 *start,
1035 u16 *end, unsigned int tag)
a0fa9647 1036{
1052b8ac 1037 int found = 0;
b60503ba 1038
5cb525c8 1039 *start = nvmeq->cq_head;
1052b8ac
JA		 1040 while (nvme_cqe_pending(nvmeq)) {
1041 if (tag == -1U || nvmeq->cqes[nvmeq->cq_head].command_id == tag)
1042 found++;
5cb525c8 1043 nvme_update_cq_head(nvmeq);
920d13a8 1044 }
5cb525c8 1045 *end = nvmeq->cq_head;
eb281c82 1046
5cb525c8 1047 if (*start != *end)
920d13a8 1048 nvme_ring_cq_doorbell(nvmeq);
5cb525c8 1049 return found;
b60503ba
MW		 1050}
1051
1052static irqreturn_t nvme_irq(int irq, void *data)
58ffacb5 1053{
58ffacb5 1054 struct nvme_queue *nvmeq = data;
68fa9dbe 1055 irqreturn_t ret = IRQ_NONE;
5cb525c8
JA		 1056 u16 start, end;
1057
3a7afd8e
CH		 1058 /*
1059 * The rmb/wmb pair ensures we see all updates from a previous run of
1060 * the irq handler, even if that was on another CPU.
1061 */
1062 rmb();
68fa9dbe
JA		 1063 if (nvmeq->cq_head != nvmeq->last_cq_head)
1064 ret = IRQ_HANDLED;
5cb525c8 1065 nvme_process_cq(nvmeq, &start, &end, -1);
68fa9dbe 1066 nvmeq->last_cq_head = nvmeq->cq_head;
3a7afd8e 1067 wmb();
5cb525c8 1068
68fa9dbe
JA		 1069 if (start != end) {
1070 nvme_complete_cqes(nvmeq, start, end);
1071 return IRQ_HANDLED;
1072 }
1073
1074 return ret;
58ffacb5
MW		 1075}
1076
1077static irqreturn_t nvme_irq_check(int irq, void *data)
1078{
1079 struct nvme_queue *nvmeq = data;
750dde44 1080 if (nvme_cqe_pending(nvmeq))
d783e0bd
MR		 1081 return IRQ_WAKE_THREAD;
1082 return IRQ_NONE;
58ffacb5
MW		 1083}
1084
0b2a8a9f
CH		 1085/*
1086 * Poll for completions any queue, including those not dedicated to polling.
1087 * Can be called from any context.
1088 */
1089static int nvme_poll_irqdisable(struct nvme_queue *nvmeq, unsigned int tag)
a0fa9647 1090{
3a7afd8e 1091 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
5cb525c8 1092 u16 start, end;
1052b8ac 1093 int found;
a0fa9647 1094
3a7afd8e
CH		 1095 /*
1096 * For a poll queue we need to protect against the polling thread
1097 * using the CQ lock. For normal interrupt driven threads we have
1098 * to disable the interrupt to avoid racing with it.
1099 */
7c349dde 1100 if (test_bit(NVMEQ_POLLED, &nvmeq->flags)) {
3a7afd8e 1101 spin_lock(&nvmeq->cq_poll_lock);
91a509f8 1102 found = nvme_process_cq(nvmeq, &start, &end, tag);
3a7afd8e 1103 spin_unlock(&nvmeq->cq_poll_lock);
91a509f8
CH		 1104 } else {
1105 disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1106 found = nvme_process_cq(nvmeq, &start, &end, tag);
3a7afd8e 1107 enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
91a509f8 1108 }
442e19b7 1109
5cb525c8 1110 nvme_complete_cqes(nvmeq, start, end);
442e19b7 1111 return found;
a0fa9647
JA		 1112}
1113
9743139c 1114static int nvme_poll(struct blk_mq_hw_ctx *hctx)
dabcefab
JA		 1115{
1116 struct nvme_queue *nvmeq = hctx->driver_data;
1117 u16 start, end;
1118 bool found;
1119
1120 if (!nvme_cqe_pending(nvmeq))
1121 return 0;
1122
3a7afd8e 1123 spin_lock(&nvmeq->cq_poll_lock);
9743139c 1124 found = nvme_process_cq(nvmeq, &start, &end, -1);
3a7afd8e 1125 spin_unlock(&nvmeq->cq_poll_lock);
dabcefab
JA		 1126
1127 nvme_complete_cqes(nvmeq, start, end);
1128 return found;
1129}
1130
ad22c355 1131static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
b60503ba 1132{
f866fc42 1133 struct nvme_dev *dev = to_nvme_dev(ctrl);
147b27e4 1134 struct nvme_queue *nvmeq = &dev->queues[0];
a4aea562 1135 struct nvme_command c;
b60503ba 1136
a4aea562
MB		 1137 memset(&c, 0, sizeof(c));
1138 c.common.opcode = nvme_admin_async_event;
ad22c355 1139 c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
04f3eafd 1140 nvme_submit_cmd(nvmeq, &c, true);
f705f837
CH		 1141}
1142
b60503ba 1143static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
f705f837 1144{
b60503ba
MW		 1145 struct nvme_command c;
1146
1147 memset(&c, 0, sizeof(c));
1148 c.delete_queue.opcode = opcode;
1149 c.delete_queue.qid = cpu_to_le16(id);
1150
1c63dc66 1151 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1152}
1153
b60503ba 1154static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
a8e3e0bb 1155 struct nvme_queue *nvmeq, s16 vector)
b60503ba 1156{
b60503ba 1157 struct nvme_command c;
4b04cc6a
JA		 1158 int flags = NVME_QUEUE_PHYS_CONTIG;
1159
7c349dde 1160 if (!test_bit(NVMEQ_POLLED, &nvmeq->flags))
4b04cc6a 1161 flags |= NVME_CQ_IRQ_ENABLED;
b60503ba 1162
d29ec824 1163 /*
16772ae6 1164 * Note: we (ab)use the fact that the prp fields survive if no data
d29ec824
CH		 1165 * is attached to the request.
1166 */
b60503ba
MW		 1167 memset(&c, 0, sizeof(c));
1168 c.create_cq.opcode = nvme_admin_create_cq;
1169 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1170 c.create_cq.cqid = cpu_to_le16(qid);
1171 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1172 c.create_cq.cq_flags = cpu_to_le16(flags);
7c349dde 1173 c.create_cq.irq_vector = cpu_to_le16(vector);
b60503ba 1174
1c63dc66 1175 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1176}
1177
1178static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1179 struct nvme_queue *nvmeq)
1180{
9abd68ef 1181 struct nvme_ctrl *ctrl = &dev->ctrl;
b60503ba 1182 struct nvme_command c;
81c1cd98 1183 int flags = NVME_QUEUE_PHYS_CONTIG;
b60503ba 1184
9abd68ef
JA		 1185 /*
1186 * Some drives have a bug that auto-enables WRRU if MEDIUM isn't
1187 * set. Since URGENT priority is zeroes, it makes all queues
1188 * URGENT.
1189 */
1190 if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ)
1191 flags |= NVME_SQ_PRIO_MEDIUM;
1192
d29ec824 1193 /*
16772ae6 1194 * Note: we (ab)use the fact that the prp fields survive if no data
d29ec824
CH		 1195 * is attached to the request.
1196 */
b60503ba
MW		 1197 memset(&c, 0, sizeof(c));
1198 c.create_sq.opcode = nvme_admin_create_sq;
1199 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1200 c.create_sq.sqid = cpu_to_le16(qid);
1201 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1202 c.create_sq.sq_flags = cpu_to_le16(flags);
1203 c.create_sq.cqid = cpu_to_le16(qid);
1204
1c63dc66 1205 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1206}
1207
1208static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1209{
1210 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1211}
1212
1213static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1214{
1215 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1216}
1217
2a842aca 1218static void abort_endio(struct request *req, blk_status_t error)
bc5fc7e4 1219{
f4800d6d
CH		 1220 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1221 struct nvme_queue *nvmeq = iod->nvmeq;
e44ac588 1222
27fa9bc5
CH		 1223 dev_warn(nvmeq->dev->ctrl.device,
1224 "Abort status: 0x%x", nvme_req(req)->status);
e7a2a87d 1225 atomic_inc(&nvmeq->dev->ctrl.abort_limit);
e7a2a87d 1226 blk_mq_free_request(req);
bc5fc7e4
MW		 1227}
1228
b2a0eb1a
KB		 1229static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1230{
1231
1232 /* If true, indicates loss of adapter communication, possibly by a
1233 * NVMe Subsystem reset.
1234 */
1235 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1236
ad70062c
JW		 1237 /* If there is a reset/reinit ongoing, we shouldn't reset again. */
1238 switch (dev->ctrl.state) {
1239 case NVME_CTRL_RESETTING:
ad6a0a52 1240 case NVME_CTRL_CONNECTING:
b2a0eb1a 1241 return false;
ad70062c
JW		 1242 default:
1243 break;
1244 }
b2a0eb1a
KB		 1245
1246 /* We shouldn't reset unless the controller is on fatal error state
1247 * _or_ if we lost the communication with it.
1248 */
1249 if (!(csts & NVME_CSTS_CFS) && !nssro)
1250 return false;
1251
b2a0eb1a
KB		 1252 return true;
1253}
1254
1255static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1256{
1257 /* Read a config register to help see what died. */
1258 u16 pci_status;
1259 int result;
1260
1261 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1262 &pci_status);
1263 if (result == PCIBIOS_SUCCESSFUL)
1264 dev_warn(dev->ctrl.device,
1265 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1266 csts, pci_status);
1267 else
1268 dev_warn(dev->ctrl.device,
1269 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1270 csts, result);
1271}
1272
31c7c7d2 1273static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
c30341dc 1274{
f4800d6d
CH		 1275 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1276 struct nvme_queue *nvmeq = iod->nvmeq;
c30341dc 1277 struct nvme_dev *dev = nvmeq->dev;
a4aea562 1278 struct request *abort_req;
a4aea562 1279 struct nvme_command cmd;
9dc1a38e 1280 bool shutdown = false;
b2a0eb1a
KB		 1281 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1282
651438bb
WX		 1283 /* If PCI error recovery process is happening, we cannot reset or
1284 * the recovery mechanism will surely fail.
1285 */
1286 mb();
1287 if (pci_channel_offline(to_pci_dev(dev->dev)))
1288 return BLK_EH_RESET_TIMER;
1289
b2a0eb1a
KB		 1290 /*
1291 * Reset immediately if the controller is failed
1292 */
1293 if (nvme_should_reset(dev, csts)) {
1294 nvme_warn_reset(dev, csts);
1295 nvme_dev_disable(dev, false);
d86c4d8e 1296 nvme_reset_ctrl(&dev->ctrl);
db8c48e4 1297 return BLK_EH_DONE;
b2a0eb1a 1298 }
c30341dc 1299
7776db1c
KB		 1300 /*
1301 * Did we miss an interrupt?
1302 */
0b2a8a9f 1303 if (nvme_poll_irqdisable(nvmeq, req->tag)) {
7776db1c
KB		 1304 dev_warn(dev->ctrl.device,
1305 "I/O %d QID %d timeout, completion polled\n",
1306 req->tag, nvmeq->qid);
db8c48e4 1307 return BLK_EH_DONE;
7776db1c
KB		 1308 }
1309
31c7c7d2 1310 /*
fd634f41
CH		 1311 * Shutdown immediately if controller times out while starting. The
1312 * reset work will see the pci device disabled when it gets the forced
1313 * cancellation error. All outstanding requests are completed on
db8c48e4 1314 * shutdown, so we return BLK_EH_DONE.
fd634f41 1315 */
4244140d 1316 switch (dev->ctrl.state) {
9dc1a38e
KB		 1317 case NVME_CTRL_DELETING:
1318 shutdown = true;
4244140d
KB		 1319 case NVME_CTRL_CONNECTING:
1320 case NVME_CTRL_RESETTING:
b9cac43c 1321 dev_warn_ratelimited(dev->ctrl.device,
fd634f41
CH		 1322 "I/O %d QID %d timeout, disable controller\n",
1323 req->tag, nvmeq->qid);
9dc1a38e 1324 nvme_dev_disable(dev, shutdown);
27fa9bc5 1325 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
db8c48e4 1326 return BLK_EH_DONE;
4244140d
KB		 1327 default:
1328 break;
c30341dc
KB		 1329 }
1330
fd634f41
CH		 1331 /*
1332 * Shutdown the controller immediately and schedule a reset if the
1333 * command was already aborted once before and still hasn't been
1334 * returned to the driver, or if this is the admin queue.
31c7c7d2 1335 */
f4800d6d 1336 if (!nvmeq->qid || iod->aborted) {
1b3c47c1 1337 dev_warn(dev->ctrl.device,
e1569a16
KB		 1338 "I/O %d QID %d timeout, reset controller\n",
1339 req->tag, nvmeq->qid);
a5cdb68c 1340 nvme_dev_disable(dev, false);
d86c4d8e 1341 nvme_reset_ctrl(&dev->ctrl);
c30341dc 1342
27fa9bc5 1343 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
db8c48e4 1344 return BLK_EH_DONE;
c30341dc 1345 }
c30341dc 1346
e7a2a87d 1347 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
6bf25d16 1348 atomic_inc(&dev->ctrl.abort_limit);
31c7c7d2 1349 return BLK_EH_RESET_TIMER;
6bf25d16 1350 }
7bf7d778 1351 iod->aborted = 1;
a4aea562 1352
c30341dc
KB		 1353 memset(&cmd, 0, sizeof(cmd));
1354 cmd.abort.opcode = nvme_admin_abort_cmd;
a4aea562 1355 cmd.abort.cid = req->tag;
c30341dc 1356 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
c30341dc 1357
1b3c47c1
SG		 1358 dev_warn(nvmeq->dev->ctrl.device,
1359 "I/O %d QID %d timeout, aborting\n",
1360 req->tag, nvmeq->qid);
e7a2a87d
CH		 1361
1362 abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
eb71f435 1363 BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
e7a2a87d
CH		 1364 if (IS_ERR(abort_req)) {
1365 atomic_inc(&dev->ctrl.abort_limit);
1366 return BLK_EH_RESET_TIMER;
1367 }
1368
1369 abort_req->timeout = ADMIN_TIMEOUT;
1370 abort_req->end_io_data = NULL;
1371 blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio);
c30341dc 1372
31c7c7d2
CH		 1373 /*
1374 * The aborted req will be completed on receiving the abort req.
1375 * We enable the timer again. If hit twice, it'll cause a device reset,
1376 * as the device then is in a faulty state.
1377 */
1378 return BLK_EH_RESET_TIMER;
c30341dc
KB		 1379}
1380
a4aea562
MB		 1381static void nvme_free_queue(struct nvme_queue *nvmeq)
1382{
88a041f4 1383 dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq->q_depth),
9e866774 1384 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
63223078
CH		 1385 if (!nvmeq->sq_cmds)
1386 return;
0f238ff5 1387
63223078 1388 if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) {
88a041f4 1389 pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev),
63223078
CH		 1390 nvmeq->sq_cmds, SQ_SIZE(nvmeq->q_depth));
1391 } else {
88a041f4 1392 dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq->q_depth),
63223078 1393 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
0f238ff5 1394 }
9e866774
MW		 1395}
1396
a1a5ef99 1397static void nvme_free_queues(struct nvme_dev *dev, int lowest)
22404274
KB		 1398{
1399 int i;
1400
d858e5f0 1401 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
d858e5f0 1402 dev->ctrl.queue_count--;
147b27e4 1403 nvme_free_queue(&dev->queues[i]);
121c7ad4 1404 }
22404274
KB		 1405}
1406
4d115420
KB		 1407/**
1408 * nvme_suspend_queue - put queue into suspended state
40581d1a 1409 * @nvmeq: queue to suspend
4d115420
KB		 1410 */
1411static int nvme_suspend_queue(struct nvme_queue *nvmeq)
b60503ba 1412{
4e224106 1413 if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags))
2b25d981 1414 return 1;
a09115b2 1415
4e224106 1416 /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */
d1f06f4a 1417 mb();
a09115b2 1418
4e224106 1419 nvmeq->dev->online_queues--;
1c63dc66 1420 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
c81545f9 1421 blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q);
7c349dde
KB		 1422 if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags))
1423 pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq);
4d115420
KB		 1424 return 0;
1425}
b60503ba 1426
8fae268b
KB		 1427static void nvme_suspend_io_queues(struct nvme_dev *dev)
1428{
1429 int i;
1430
1431 for (i = dev->ctrl.queue_count - 1; i > 0; i--)
1432 nvme_suspend_queue(&dev->queues[i]);
1433}
1434
a5cdb68c 1435static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
4d115420 1436{
147b27e4 1437 struct nvme_queue *nvmeq = &dev->queues[0];
4d115420 1438
a5cdb68c
KB		 1439 if (shutdown)
1440 nvme_shutdown_ctrl(&dev->ctrl);
1441 else
20d0dfe6 1442 nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap);
07836e65 1443
0b2a8a9f 1444 nvme_poll_irqdisable(nvmeq, -1);
b60503ba
MW		 1445}
1446
8ffaadf7
JD		 1447static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1448 int entry_size)
1449{
1450 int q_depth = dev->q_depth;
5fd4ce1b
CH		 1451 unsigned q_size_aligned = roundup(q_depth * entry_size,
1452 dev->ctrl.page_size);
8ffaadf7
JD		 1453
1454 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
c45f5c99 1455 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
5fd4ce1b 1456 mem_per_q = round_down(mem_per_q, dev->ctrl.page_size);
c45f5c99 1457 q_depth = div_u64(mem_per_q, entry_size);
8ffaadf7
JD		 1458
1459 /*
1460 * Ensure the reduced q_depth is above some threshold where it
1461 * would be better to map queues in system memory with the
1462 * original depth
1463 */
1464 if (q_depth < 64)
1465 return -ENOMEM;
1466 }
1467
1468 return q_depth;
1469}
1470
1471static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1472 int qid, int depth)
1473{
0f238ff5
LG		 1474 struct pci_dev *pdev = to_pci_dev(dev->dev);
1475
1476 if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
1477 nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(depth));
1478 nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev,
1479 nvmeq->sq_cmds);
63223078
CH		 1480 if (nvmeq->sq_dma_addr) {
1481 set_bit(NVMEQ_SQ_CMB, &nvmeq->flags);
1482 return 0;
1483 }
0f238ff5 1484 }
8ffaadf7 1485
63223078
CH		 1486 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
1487 &nvmeq->sq_dma_addr, GFP_KERNEL);
815c6704
KB		 1488 if (!nvmeq->sq_cmds)
1489 return -ENOMEM;
8ffaadf7
JD		 1490 return 0;
1491}
1492
a6ff7262 1493static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
b60503ba 1494{
147b27e4 1495 struct nvme_queue *nvmeq = &dev->queues[qid];
b60503ba 1496
62314e40
KB		 1497 if (dev->ctrl.queue_count > qid)
1498 return 0;
b60503ba 1499
750afb08
LC		 1500 nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(depth),
1501 &nvmeq->cq_dma_addr, GFP_KERNEL);
b60503ba
MW		 1502 if (!nvmeq->cqes)
1503 goto free_nvmeq;
b60503ba 1504
8ffaadf7 1505 if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth))
b60503ba
MW		 1506 goto free_cqdma;
1507
091b6092 1508 nvmeq->dev = dev;
1ab0cd69 1509 spin_lock_init(&nvmeq->sq_lock);
3a7afd8e 1510 spin_lock_init(&nvmeq->cq_poll_lock);
b60503ba 1511 nvmeq->cq_head = 0;
82123460 1512 nvmeq->cq_phase = 1;
b80d5ccc 1513 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
b60503ba 1514 nvmeq->q_depth = depth;
c30341dc 1515 nvmeq->qid = qid;
d858e5f0 1516 dev->ctrl.queue_count++;
36a7e993 1517
147b27e4 1518 return 0;
b60503ba
MW		 1519
1520 free_cqdma:
e75ec752 1521 dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes,
b60503ba
MW		 1522 nvmeq->cq_dma_addr);
1523 free_nvmeq:
147b27e4 1524 return -ENOMEM;
b60503ba
MW		 1525}
1526
dca51e78 1527static int queue_request_irq(struct nvme_queue *nvmeq)
3001082c 1528{
0ff199cb
CH		 1529 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1530 int nr = nvmeq->dev->ctrl.instance;
1531
1532 if (use_threaded_interrupts) {
1533 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1534 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1535 } else {
1536 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1537 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1538 }
3001082c
MW		 1539}
1540
22404274 1541static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
b60503ba 1542{
22404274 1543 struct nvme_dev *dev = nvmeq->dev;
b60503ba 1544
22404274 1545 nvmeq->sq_tail = 0;
04f3eafd 1546 nvmeq->last_sq_tail = 0;
22404274
KB		 1547 nvmeq->cq_head = 0;
1548 nvmeq->cq_phase = 1;
b80d5ccc 1549 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
22404274 1550 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
f9f38e33 1551 nvme_dbbuf_init(dev, nvmeq, qid);
42f61420 1552 dev->online_queues++;
3a7afd8e 1553 wmb(); /* ensure the first interrupt sees the initialization */
22404274
KB		 1554}
1555
4b04cc6a 1556static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled)
22404274
KB		 1557{
1558 struct nvme_dev *dev = nvmeq->dev;
1559 int result;
7c349dde 1560 u16 vector = 0;
3f85d50b 1561
d1ed6aa1
CH		 1562 clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
1563
22b55601
KB		 1564 /*
1565 * A queue's vector matches the queue identifier unless the controller
1566 * has only one vector available.
1567 */
4b04cc6a
JA		 1568 if (!polled)
1569 vector = dev->num_vecs == 1 ? 0 : qid;
1570 else
7c349dde 1571 set_bit(NVMEQ_POLLED, &nvmeq->flags);
4b04cc6a 1572
a8e3e0bb 1573 result = adapter_alloc_cq(dev, qid, nvmeq, vector);
ded45505
KB		 1574 if (result)
1575 return result;
b60503ba
MW		 1576
1577 result = adapter_alloc_sq(dev, qid, nvmeq);
1578 if (result < 0)
ded45505
KB		 1579 return result;
1580 else if (result)
b60503ba
MW		 1581 goto release_cq;
1582
a8e3e0bb 1583 nvmeq->cq_vector = vector;
161b8be2 1584 nvme_init_queue(nvmeq, qid);
4b04cc6a 1585
7c349dde
KB		 1586 if (!polled) {
1587 nvmeq->cq_vector = vector;
4b04cc6a
JA		 1588 result = queue_request_irq(nvmeq);
1589 if (result < 0)
1590 goto release_sq;
1591 }
b60503ba 1592
4e224106 1593 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
22404274 1594 return result;
b60503ba 1595
a8e3e0bb 1596release_sq:
f25a2dfc 1597 dev->online_queues--;
b60503ba 1598 adapter_delete_sq(dev, qid);
a8e3e0bb 1599release_cq:
b60503ba 1600 adapter_delete_cq(dev, qid);
22404274 1601 return result;
b60503ba
MW		 1602}
1603
f363b089 1604static const struct blk_mq_ops nvme_mq_admin_ops = {
d29ec824 1605 .queue_rq = nvme_queue_rq,
77f02a7a 1606 .complete = nvme_pci_complete_rq,
a4aea562 1607 .init_hctx = nvme_admin_init_hctx,
4af0e21c 1608 .exit_hctx = nvme_admin_exit_hctx,
0350815a 1609 .init_request = nvme_init_request,
a4aea562
MB		 1610 .timeout = nvme_timeout,
1611};
1612
f363b089 1613static const struct blk_mq_ops nvme_mq_ops = {
376f7ef8
CH		 1614 .queue_rq = nvme_queue_rq,
1615 .complete = nvme_pci_complete_rq,
1616 .commit_rqs = nvme_commit_rqs,
1617 .init_hctx = nvme_init_hctx,
1618 .init_request = nvme_init_request,
1619 .map_queues = nvme_pci_map_queues,
1620 .timeout = nvme_timeout,
1621 .poll = nvme_poll,
dabcefab
JA		 1622};
1623
ea191d2f
KB		 1624static void nvme_dev_remove_admin(struct nvme_dev *dev)
1625{
1c63dc66 1626 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
69d9a99c
KB		 1627 /*
1628 * If the controller was reset during removal, it's possible
1629 * user requests may be waiting on a stopped queue. Start the
1630 * queue to flush these to completion.
1631 */
c81545f9 1632 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1c63dc66 1633 blk_cleanup_queue(dev->ctrl.admin_q);
ea191d2f
KB		 1634 blk_mq_free_tag_set(&dev->admin_tagset);
1635 }
1636}
1637
a4aea562
MB		 1638static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1639{
1c63dc66 1640 if (!dev->ctrl.admin_q) {
a4aea562
MB		 1641 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1642 dev->admin_tagset.nr_hw_queues = 1;
e3e9d50c 1643
38dabe21 1644 dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH;
a4aea562 1645 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
e75ec752 1646 dev->admin_tagset.numa_node = dev_to_node(dev->dev);
d43f1ccf 1647 dev->admin_tagset.cmd_size = sizeof(struct nvme_iod);
d3484991 1648 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED;
a4aea562
MB		 1649 dev->admin_tagset.driver_data = dev;
1650
1651 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1652 return -ENOMEM;
34b6c231 1653 dev->ctrl.admin_tagset = &dev->admin_tagset;
a4aea562 1654
1c63dc66
CH		 1655 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1656 if (IS_ERR(dev->ctrl.admin_q)) {
a4aea562
MB		 1657 blk_mq_free_tag_set(&dev->admin_tagset);
1658 return -ENOMEM;
1659 }
1c63dc66 1660 if (!blk_get_queue(dev->ctrl.admin_q)) {
ea191d2f 1661 nvme_dev_remove_admin(dev);
1c63dc66 1662 dev->ctrl.admin_q = NULL;
ea191d2f
KB		 1663 return -ENODEV;
1664 }
0fb59cbc 1665 } else
c81545f9 1666 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
a4aea562
MB		 1667
1668 return 0;
1669}
1670
97f6ef64
XY		 1671static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1672{
1673 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1674}
1675
1676static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1677{
1678 struct pci_dev *pdev = to_pci_dev(dev->dev);
1679
1680 if (size <= dev->bar_mapped_size)
1681 return 0;
1682 if (size > pci_resource_len(pdev, 0))
1683 return -ENOMEM;
1684 if (dev->bar)
1685 iounmap(dev->bar);
1686 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1687 if (!dev->bar) {
1688 dev->bar_mapped_size = 0;
1689 return -ENOMEM;
1690 }
1691 dev->bar_mapped_size = size;
1692 dev->dbs = dev->bar + NVME_REG_DBS;
1693
1694 return 0;
1695}
1696
01ad0990 1697static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
b60503ba 1698{
ba47e386 1699 int result;
b60503ba
MW		 1700 u32 aqa;
1701 struct nvme_queue *nvmeq;
1702
97f6ef64
XY		 1703 result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1704 if (result < 0)
1705 return result;
1706
8ef2074d 1707 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
20d0dfe6 1708 NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
dfbac8c7 1709
7a67cbea
CH		 1710 if (dev->subsystem &&
1711 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1712 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
dfbac8c7 1713
20d0dfe6 1714 result = nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap);
ba47e386
MW		 1715 if (result < 0)
1716 return result;
b60503ba 1717
a6ff7262 1718 result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
147b27e4
SG		 1719 if (result)
1720 return result;
b60503ba 1721
147b27e4 1722 nvmeq = &dev->queues[0];
b60503ba
MW		 1723 aqa = nvmeq->q_depth - 1;
1724 aqa |= aqa << 16;
1725
7a67cbea
CH		 1726 writel(aqa, dev->bar + NVME_REG_AQA);
1727 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1728 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
b60503ba 1729
20d0dfe6 1730 result = nvme_enable_ctrl(&dev->ctrl, dev->ctrl.cap);
025c557a 1731 if (result)
d4875622 1732 return result;
a4aea562 1733
2b25d981 1734 nvmeq->cq_vector = 0;
161b8be2 1735 nvme_init_queue(nvmeq, 0);
dca51e78 1736 result = queue_request_irq(nvmeq);
758dd7fd 1737 if (result) {
7c349dde 1738 dev->online_queues--;
d4875622 1739 return result;
758dd7fd 1740 }
025c557a 1741
4e224106 1742 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
b60503ba
MW		 1743 return result;
1744}
1745
749941f2 1746static int nvme_create_io_queues(struct nvme_dev *dev)
42f61420 1747{
4b04cc6a 1748 unsigned i, max, rw_queues;
749941f2 1749 int ret = 0;
42f61420 1750
d858e5f0 1751 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
a6ff7262 1752 if (nvme_alloc_queue(dev, i, dev->q_depth)) {
749941f2 1753 ret = -ENOMEM;
42f61420 1754 break;
749941f2
CH		 1755 }
1756 }
42f61420 1757
d858e5f0 1758 max = min(dev->max_qid, dev->ctrl.queue_count - 1);
e20ba6e1
CH		 1759 if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) {
1760 rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] +
1761 dev->io_queues[HCTX_TYPE_READ];
4b04cc6a
JA		 1762 } else {
1763 rw_queues = max;
1764 }
1765
949928c1 1766 for (i = dev->online_queues; i <= max; i++) {
4b04cc6a
JA		 1767 bool polled = i > rw_queues;
1768
1769 ret = nvme_create_queue(&dev->queues[i], i, polled);
d4875622 1770 if (ret)
42f61420 1771 break;
27e8166c 1772 }
749941f2
CH		 1773
1774 /*
1775 * Ignore failing Create SQ/CQ commands, we can continue with less
8adb8c14
MI		 1776 * than the desired amount of queues, and even a controller without
1777 * I/O queues can still be used to issue admin commands. This might
749941f2
CH		 1778 * be useful to upgrade a buggy firmware for example.
1779 */
1780 return ret >= 0 ? 0 : ret;
b60503ba
MW		 1781}
1782
202021c1
SB		 1783static ssize_t nvme_cmb_show(struct device *dev,
1784 struct device_attribute *attr,
1785 char *buf)
1786{
1787 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
1788
c965809c 1789 return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n",
202021c1
SB		 1790 ndev->cmbloc, ndev->cmbsz);
1791}
1792static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL);
1793
88de4598 1794static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
8ffaadf7 1795{
88de4598
CH		 1796 u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
1797
1798 return 1ULL << (12 + 4 * szu);
1799}
1800
1801static u32 nvme_cmb_size(struct nvme_dev *dev)
1802{
1803 return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
1804}
1805
f65efd6d 1806static void nvme_map_cmb(struct nvme_dev *dev)
8ffaadf7 1807{
88de4598 1808 u64 size, offset;
8ffaadf7
JD		 1809 resource_size_t bar_size;
1810 struct pci_dev *pdev = to_pci_dev(dev->dev);
8969f1f8 1811 int bar;
8ffaadf7 1812
9fe5c59f
KB		 1813 if (dev->cmb_size)
1814 return;
1815
7a67cbea 1816 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
f65efd6d
CH		 1817 if (!dev->cmbsz)
1818 return;
202021c1 1819 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
8ffaadf7 1820
88de4598
CH		 1821 size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
1822 offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
8969f1f8
CH		 1823 bar = NVME_CMB_BIR(dev->cmbloc);
1824 bar_size = pci_resource_len(pdev, bar);
8ffaadf7
JD		 1825
1826 if (offset > bar_size)
f65efd6d 1827 return;
8ffaadf7
JD		 1828
1829 /*
1830 * Controllers may support a CMB size larger than their BAR,
1831 * for example, due to being behind a bridge. Reduce the CMB to
1832 * the reported size of the BAR
1833 */
1834 if (size > bar_size - offset)
1835 size = bar_size - offset;
1836
0f238ff5
LG		 1837 if (pci_p2pdma_add_resource(pdev, bar, size, offset)) {
1838 dev_warn(dev->ctrl.device,
1839 "failed to register the CMB\n");
f65efd6d 1840 return;
0f238ff5
LG		 1841 }
1842
8ffaadf7 1843 dev->cmb_size = size;
0f238ff5
LG		 1844 dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS);
1845
1846 if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) ==
1847 (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS))
1848 pci_p2pmem_publish(pdev, true);
f65efd6d
CH		 1849
1850 if (sysfs_add_file_to_group(&dev->ctrl.device->kobj,
1851 &dev_attr_cmb.attr, NULL))
1852 dev_warn(dev->ctrl.device,
1853 "failed to add sysfs attribute for CMB\n");
8ffaadf7
JD		 1854}
1855
1856static inline void nvme_release_cmb(struct nvme_dev *dev)
1857{
0f238ff5 1858 if (dev->cmb_size) {
1c78f773
MG		 1859 sysfs_remove_file_from_group(&dev->ctrl.device->kobj,
1860 &dev_attr_cmb.attr, NULL);
0f238ff5 1861 dev->cmb_size = 0;
8ffaadf7
JD		 1862 }
1863}
1864
87ad72a5
CH		 1865static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1866{
4033f35d 1867 u64 dma_addr = dev->host_mem_descs_dma;
87ad72a5 1868 struct nvme_command c;
87ad72a5
CH		 1869 int ret;
1870
87ad72a5
CH		 1871 memset(&c, 0, sizeof(c));
1872 c.features.opcode = nvme_admin_set_features;
1873 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1874 c.features.dword11 = cpu_to_le32(bits);
1875 c.features.dword12 = cpu_to_le32(dev->host_mem_size >>
1876 ilog2(dev->ctrl.page_size));
1877 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr));
1878 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr));
1879 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs);
1880
1881 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1882 if (ret) {
1883 dev_warn(dev->ctrl.device,
1884 "failed to set host mem (err %d, flags %#x).\n",
1885 ret, bits);
1886 }
87ad72a5
CH		 1887 return ret;
1888}
1889
1890static void nvme_free_host_mem(struct nvme_dev *dev)
1891{
1892 int i;
1893
1894 for (i = 0; i < dev->nr_host_mem_descs; i++) {
1895 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
1896 size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size;
1897
cc667f6d
LD		 1898 dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i],
1899 le64_to_cpu(desc->addr),
1900 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
87ad72a5
CH		 1901 }
1902
1903 kfree(dev->host_mem_desc_bufs);
1904 dev->host_mem_desc_bufs = NULL;
4033f35d
CH		 1905 dma_free_coherent(dev->dev,
1906 dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
1907 dev->host_mem_descs, dev->host_mem_descs_dma);
87ad72a5 1908 dev->host_mem_descs = NULL;
7e5dd57e 1909 dev->nr_host_mem_descs = 0;
87ad72a5
CH		 1910}
1911
92dc6895
CH		 1912static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
1913 u32 chunk_size)
9d713c2b 1914{
87ad72a5 1915 struct nvme_host_mem_buf_desc *descs;
92dc6895 1916 u32 max_entries, len;
4033f35d 1917 dma_addr_t descs_dma;
2ee0e4ed 1918 int i = 0;
87ad72a5 1919 void **bufs;
6fbcde66 1920 u64 size, tmp;
87ad72a5 1921
87ad72a5
CH		 1922 tmp = (preferred + chunk_size - 1);
1923 do_div(tmp, chunk_size);
1924 max_entries = tmp;
044a9df1
CH		 1925
1926 if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
1927 max_entries = dev->ctrl.hmmaxd;
1928
750afb08
LC		 1929 descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs),
1930 &descs_dma, GFP_KERNEL);
87ad72a5
CH		 1931 if (!descs)
1932 goto out;
1933
1934 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
1935 if (!bufs)
1936 goto out_free_descs;
1937
244a8fe4 1938 for (size = 0; size < preferred && i < max_entries; size += len) {
87ad72a5
CH		 1939 dma_addr_t dma_addr;
1940
50cdb7c6 1941 len = min_t(u64, chunk_size, preferred - size);
87ad72a5
CH		 1942 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
1943 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1944 if (!bufs[i])
1945 break;
1946
1947 descs[i].addr = cpu_to_le64(dma_addr);
1948 descs[i].size = cpu_to_le32(len / dev->ctrl.page_size);
1949 i++;
1950 }
1951
92dc6895 1952 if (!size)
87ad72a5 1953 goto out_free_bufs;
87ad72a5 1954
87ad72a5
CH		 1955 dev->nr_host_mem_descs = i;
1956 dev->host_mem_size = size;
1957 dev->host_mem_descs = descs;
4033f35d 1958 dev->host_mem_descs_dma = descs_dma;
87ad72a5
CH		 1959 dev->host_mem_desc_bufs = bufs;
1960 return 0;
1961
1962out_free_bufs:
1963 while (--i >= 0) {
1964 size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size;
1965
cc667f6d
LD		 1966 dma_free_attrs(dev->dev, size, bufs[i],
1967 le64_to_cpu(descs[i].addr),
1968 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
87ad72a5
CH		 1969 }
1970
1971 kfree(bufs);
1972out_free_descs:
4033f35d
CH		 1973 dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
1974 descs_dma);
87ad72a5 1975out:
87ad72a5
CH		 1976 dev->host_mem_descs = NULL;
1977 return -ENOMEM;
1978}
1979
92dc6895
CH		 1980static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
1981{
1982 u32 chunk_size;
1983
1984 /* start big and work our way down */
30f92d62 1985 for (chunk_size = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
044a9df1 1986 chunk_size >= max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
92dc6895
CH		 1987 chunk_size /= 2) {
1988 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
1989 if (!min || dev->host_mem_size >= min)
1990 return 0;
1991 nvme_free_host_mem(dev);
1992 }
1993 }
1994
1995 return -ENOMEM;
1996}
1997
9620cfba 1998static int nvme_setup_host_mem(struct nvme_dev *dev)
87ad72a5
CH		 1999{
2000 u64 max = (u64)max_host_mem_size_mb * SZ_1M;
2001 u64 preferred = (u64)dev->ctrl.hmpre * 4096;
2002 u64 min = (u64)dev->ctrl.hmmin * 4096;
2003 u32 enable_bits = NVME_HOST_MEM_ENABLE;
6fbcde66 2004 int ret;
87ad72a5
CH		 2005
2006 preferred = min(preferred, max);
2007 if (min > max) {
2008 dev_warn(dev->ctrl.device,
2009 "min host memory (%lld MiB) above limit (%d MiB).\n",
2010 min >> ilog2(SZ_1M), max_host_mem_size_mb);
2011 nvme_free_host_mem(dev);
9620cfba 2012 return 0;
87ad72a5
CH		 2013 }
2014
2015 /*
2016 * If we already have a buffer allocated check if we can reuse it.
2017 */
2018 if (dev->host_mem_descs) {
2019 if (dev->host_mem_size >= min)
2020 enable_bits |= NVME_HOST_MEM_RETURN;
2021 else
2022 nvme_free_host_mem(dev);
2023 }
2024
2025 if (!dev->host_mem_descs) {
92dc6895
CH		 2026 if (nvme_alloc_host_mem(dev, min, preferred)) {
2027 dev_warn(dev->ctrl.device,
2028 "failed to allocate host memory buffer.\n");
9620cfba 2029 return 0; /* controller must work without HMB */
92dc6895
CH		 2030 }
2031
2032 dev_info(dev->ctrl.device,
2033 "allocated %lld MiB host memory buffer.\n",
2034 dev->host_mem_size >> ilog2(SZ_1M));
87ad72a5
CH		 2035 }
2036
9620cfba
CH		 2037 ret = nvme_set_host_mem(dev, enable_bits);
2038 if (ret)
87ad72a5 2039 nvme_free_host_mem(dev);
9620cfba 2040 return ret;
9d713c2b
KB		 2041}
2042
612b7286
ML		 2043/*
2044 * nirqs is the number of interrupts available for write and read
2045 * queues. The core already reserved an interrupt for the admin queue.
2046 */
2047static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs)
3b6592f7 2048{
612b7286
ML		 2049 struct nvme_dev *dev = affd->priv;
2050 unsigned int nr_read_queues;
3b6592f7
JA		 2051
2052 /*
612b7286
ML		 2053 * If there is no interupt available for queues, ensure that
2054 * the default queue is set to 1. The affinity set size is
2055 * also set to one, but the irq core ignores it for this case.
2056 *
2057 * If only one interrupt is available or 'write_queue' == 0, combine
2058 * write and read queues.
2059 *
2060 * If 'write_queues' > 0, ensure it leaves room for at least one read
2061 * queue.
3b6592f7 2062 */
612b7286
ML		 2063 if (!nrirqs) {
2064 nrirqs = 1;
2065 nr_read_queues = 0;
2066 } else if (nrirqs == 1 || !write_queues) {
2067 nr_read_queues = 0;
2068 } else if (write_queues >= nrirqs) {
2069 nr_read_queues = 1;
3b6592f7 2070 } else {
612b7286 2071 nr_read_queues = nrirqs - write_queues;
3b6592f7 2072 }
612b7286
ML		 2073
2074 dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2075 affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2076 dev->io_queues[HCTX_TYPE_READ] = nr_read_queues;
2077 affd->set_size[HCTX_TYPE_READ] = nr_read_queues;
2078 affd->nr_sets = nr_read_queues ? 2 : 1;
3b6592f7
JA		 2079}
2080
6451fe73 2081static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues)
3b6592f7
JA		 2082{
2083 struct pci_dev *pdev = to_pci_dev(dev->dev);
3b6592f7 2084 struct irq_affinity affd = {
9cfef55b 2085 .pre_vectors = 1,
612b7286
ML		 2086 .calc_sets = nvme_calc_irq_sets,
2087 .priv = dev,
3b6592f7 2088 };
6451fe73
JA		 2089 unsigned int irq_queues, this_p_queues;
2090
2091 /*
2092 * Poll queues don't need interrupts, but we need at least one IO
2093 * queue left over for non-polled IO.
2094 */
2095 this_p_queues = poll_queues;
2096 if (this_p_queues >= nr_io_queues) {
2097 this_p_queues = nr_io_queues - 1;
2098 irq_queues = 1;
2099 } else {
c45b1fa2 2100 irq_queues = nr_io_queues - this_p_queues + 1;
6451fe73
JA		 2101 }
2102 dev->io_queues[HCTX_TYPE_POLL] = this_p_queues;
3b6592f7 2103
612b7286
ML		 2104 /* Initialize for the single interrupt case */
2105 dev->io_queues[HCTX_TYPE_DEFAULT] = 1;
2106 dev->io_queues[HCTX_TYPE_READ] = 0;
3b6592f7 2107
612b7286
ML		 2108 return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues,
2109 PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd);
3b6592f7
JA		 2110}
2111
8fae268b
KB		 2112static void nvme_disable_io_queues(struct nvme_dev *dev)
2113{
2114 if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq))
2115 __nvme_disable_io_queues(dev, nvme_admin_delete_cq);
2116}
2117
8d85fce7 2118static int nvme_setup_io_queues(struct nvme_dev *dev)
b60503ba 2119{
147b27e4 2120 struct nvme_queue *adminq = &dev->queues[0];
e75ec752 2121 struct pci_dev *pdev = to_pci_dev(dev->dev);
97f6ef64
XY		 2122 int result, nr_io_queues;
2123 unsigned long size;
b60503ba 2124
3b6592f7 2125 nr_io_queues = max_io_queues();
9a0be7ab
CH		 2126 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
2127 if (result < 0)
1b23484b 2128 return result;
9a0be7ab 2129
f5fa90dc 2130 if (nr_io_queues == 0)
a5229050 2131 return 0;
4e224106
CH		 2132
2133 clear_bit(NVMEQ_ENABLED, &adminq->flags);
b60503ba 2134
0f238ff5 2135 if (dev->cmb_use_sqes) {
8ffaadf7
JD		 2136 result = nvme_cmb_qdepth(dev, nr_io_queues,
2137 sizeof(struct nvme_command));
2138 if (result > 0)
2139 dev->q_depth = result;
2140 else
0f238ff5 2141 dev->cmb_use_sqes = false;
8ffaadf7
JD		 2142 }
2143
97f6ef64
XY		 2144 do {
2145 size = db_bar_size(dev, nr_io_queues);
2146 result = nvme_remap_bar(dev, size);
2147 if (!result)
2148 break;
2149 if (!--nr_io_queues)
2150 return -ENOMEM;
2151 } while (1);
2152 adminq->q_db = dev->dbs;
f1938f6e 2153
8fae268b 2154 retry:
9d713c2b 2155 /* Deregister the admin queue's interrupt */
0ff199cb 2156 pci_free_irq(pdev, 0, adminq);
9d713c2b 2157
e32efbfc
JA		 2158 /*
2159 * If we enable msix early due to not intx, disable it again before
2160 * setting up the full range we need.
2161 */
dca51e78 2162 pci_free_irq_vectors(pdev);
3b6592f7
JA		 2163
2164 result = nvme_setup_irqs(dev, nr_io_queues);
22b55601 2165 if (result <= 0)
dca51e78 2166 return -EIO;
3b6592f7 2167
22b55601 2168 dev->num_vecs = result;
4b04cc6a 2169 result = max(result - 1, 1);
e20ba6e1 2170 dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL];
fa08a396 2171
063a8096
MW		 2172 /*
2173 * Should investigate if there's a performance win from allocating
2174 * more queues than interrupt vectors; it might allow the submission
2175 * path to scale better, even if the receive path is limited by the
2176 * number of interrupts.
2177 */
dca51e78 2178 result = queue_request_irq(adminq);
7c349dde 2179 if (result)
d4875622 2180 return result;
4e224106 2181 set_bit(NVMEQ_ENABLED, &adminq->flags);
8fae268b
KB		 2182
2183 result = nvme_create_io_queues(dev);
2184 if (result || dev->online_queues < 2)
2185 return result;
2186
2187 if (dev->online_queues - 1 < dev->max_qid) {
2188 nr_io_queues = dev->online_queues - 1;
2189 nvme_disable_io_queues(dev);
2190 nvme_suspend_io_queues(dev);
2191 goto retry;
2192 }
2193 dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n",
2194 dev->io_queues[HCTX_TYPE_DEFAULT],
2195 dev->io_queues[HCTX_TYPE_READ],
2196 dev->io_queues[HCTX_TYPE_POLL]);
2197 return 0;
b60503ba
MW		 2198}
2199
2a842aca 2200static void nvme_del_queue_end(struct request *req, blk_status_t error)
a5768aa8 2201{
db3cbfff 2202 struct nvme_queue *nvmeq = req->end_io_data;
b5875222 2203
db3cbfff 2204 blk_mq_free_request(req);
d1ed6aa1 2205 complete(&nvmeq->delete_done);
a5768aa8
KB		 2206}
2207
2a842aca 2208static void nvme_del_cq_end(struct request *req, blk_status_t error)
a5768aa8 2209{
db3cbfff 2210 struct nvme_queue *nvmeq = req->end_io_data;
a5768aa8 2211
d1ed6aa1
CH		 2212 if (error)
2213 set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
db3cbfff
KB		 2214
2215 nvme_del_queue_end(req, error);
a5768aa8
KB		 2216}
2217
db3cbfff 2218static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
bda4e0fb 2219{
db3cbfff
KB		 2220 struct request_queue *q = nvmeq->dev->ctrl.admin_q;
2221 struct request *req;
2222 struct nvme_command cmd;
bda4e0fb 2223
db3cbfff
KB		 2224 memset(&cmd, 0, sizeof(cmd));
2225 cmd.delete_queue.opcode = opcode;
2226 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
bda4e0fb 2227
eb71f435 2228 req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
db3cbfff
KB		 2229 if (IS_ERR(req))
2230 return PTR_ERR(req);
bda4e0fb 2231
db3cbfff
KB		 2232 req->timeout = ADMIN_TIMEOUT;
2233 req->end_io_data = nvmeq;
2234
d1ed6aa1 2235 init_completion(&nvmeq->delete_done);
db3cbfff
KB		 2236 blk_execute_rq_nowait(q, NULL, req, false,
2237 opcode == nvme_admin_delete_cq ?
2238 nvme_del_cq_end : nvme_del_queue_end);
2239 return 0;
bda4e0fb
KB		 2240}
2241
8fae268b 2242static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode)
a5768aa8 2243{
5271edd4 2244 int nr_queues = dev->online_queues - 1, sent = 0;
db3cbfff 2245 unsigned long timeout;
a5768aa8 2246
db3cbfff 2247 retry:
5271edd4
CH		 2248 timeout = ADMIN_TIMEOUT;
2249 while (nr_queues > 0) {
2250 if (nvme_delete_queue(&dev->queues[nr_queues], opcode))
2251 break;
2252 nr_queues--;
2253 sent++;
db3cbfff 2254 }
d1ed6aa1
CH		 2255 while (sent) {
2256 struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent];
2257
2258 timeout = wait_for_completion_io_timeout(&nvmeq->delete_done,
5271edd4
CH		 2259 timeout);
2260 if (timeout == 0)
2261 return false;
d1ed6aa1
CH		 2262
2263 /* handle any remaining CQEs */
2264 if (opcode == nvme_admin_delete_cq &&
2265 !test_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags))
2266 nvme_poll_irqdisable(nvmeq, -1);
2267
2268 sent--;
5271edd4
CH		 2269 if (nr_queues)
2270 goto retry;
2271 }
2272 return true;
a5768aa8
KB		 2273}
2274
422ef0c7 2275/*
2b1b7e78 2276 * return error value only when tagset allocation failed
422ef0c7 2277 */
8d85fce7 2278static int nvme_dev_add(struct nvme_dev *dev)
b60503ba 2279{
2b1b7e78
JW		 2280 int ret;
2281
5bae7f73 2282 if (!dev->ctrl.tagset) {
376f7ef8 2283 dev->tagset.ops = &nvme_mq_ops;
ffe7704d 2284 dev->tagset.nr_hw_queues = dev->online_queues - 1;
ed92ad37
CH		 2285 dev->tagset.nr_maps = 2; /* default + read */
2286 if (dev->io_queues[HCTX_TYPE_POLL])
2287 dev->tagset.nr_maps++;
ffe7704d
KB		 2288 dev->tagset.timeout = NVME_IO_TIMEOUT;
2289 dev->tagset.numa_node = dev_to_node(dev->dev);
2290 dev->tagset.queue_depth =
a4aea562 2291 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
d43f1ccf 2292 dev->tagset.cmd_size = sizeof(struct nvme_iod);
ffe7704d
KB		 2293 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2294 dev->tagset.driver_data = dev;
b60503ba 2295
2b1b7e78
JW		 2296 ret = blk_mq_alloc_tag_set(&dev->tagset);
2297 if (ret) {
2298 dev_warn(dev->ctrl.device,
2299 "IO queues tagset allocation failed %d\n", ret);
2300 return ret;
2301 }
5bae7f73 2302 dev->ctrl.tagset = &dev->tagset;
f9f38e33
HK		 2303
2304 nvme_dbbuf_set(dev);
949928c1
KB		 2305 } else {
2306 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2307
2308 /* Free previously allocated queues that are no longer usable */
2309 nvme_free_queues(dev, dev->online_queues);
ffe7704d 2310 }
949928c1 2311
e1e5e564 2312 return 0;
b60503ba
MW		 2313}
2314
b00a726a 2315static int nvme_pci_enable(struct nvme_dev *dev)
0877cb0d 2316{
b00a726a 2317 int result = -ENOMEM;
e75ec752 2318 struct pci_dev *pdev = to_pci_dev(dev->dev);
0877cb0d
KB		 2319
2320 if (pci_enable_device_mem(pdev))
2321 return result;
2322
0877cb0d 2323 pci_set_master(pdev);
0877cb0d 2324
e75ec752
CH		 2325 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) &&
2326 dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32)))
052d0efa 2327 goto disable;
0877cb0d 2328
7a67cbea 2329 if (readl(dev->bar + NVME_REG_CSTS) == -1) {
0e53d180 2330 result = -ENODEV;
b00a726a 2331 goto disable;
0e53d180 2332 }
e32efbfc
JA		 2333
2334 /*
a5229050
KB		 2335 * Some devices and/or platforms don't advertise or work with INTx
2336 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2337 * adjust this later.
e32efbfc 2338 */
dca51e78
CH		 2339 result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
2340 if (result < 0)
2341 return result;
e32efbfc 2342
20d0dfe6 2343 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
7a67cbea 2344
20d0dfe6 2345 dev->q_depth = min_t(int, NVME_CAP_MQES(dev->ctrl.cap) + 1,
b27c1e68 2346 io_queue_depth);
20d0dfe6 2347 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
7a67cbea 2348 dev->dbs = dev->bar + 4096;
1f390c1f
SG		 2349
2350 /*
2351 * Temporary fix for the Apple controller found in the MacBook8,1 and
2352 * some MacBook7,1 to avoid controller resets and data loss.
2353 */
2354 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
2355 dev->q_depth = 2;
9bdcfb10
CH		 2356 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
2357 "set queue depth=%u to work around controller resets\n",
1f390c1f 2358 dev->q_depth);
d554b5e1
MP		 2359 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2360 (pdev->device == 0xa821 || pdev->device == 0xa822) &&
20d0dfe6 2361 NVME_CAP_MQES(dev->ctrl.cap) == 0) {
d554b5e1
MP		 2362 dev->q_depth = 64;
2363 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2364 "set queue depth=%u\n", dev->q_depth);
1f390c1f
SG		 2365 }
2366
f65efd6d 2367 nvme_map_cmb(dev);
202021c1 2368
a0a3408e
KB		 2369 pci_enable_pcie_error_reporting(pdev);
2370 pci_save_state(pdev);
0877cb0d
KB		 2371 return 0;
2372
2373 disable:
0877cb0d
KB		 2374 pci_disable_device(pdev);
2375 return result;
2376}
2377
2378static void nvme_dev_unmap(struct nvme_dev *dev)
b00a726a
KB		 2379{
2380 if (dev->bar)
2381 iounmap(dev->bar);
a1f447b3 2382 pci_release_mem_regions(to_pci_dev(dev->dev));
b00a726a
KB		 2383}
2384
2385static void nvme_pci_disable(struct nvme_dev *dev)
0877cb0d 2386{
e75ec752
CH		 2387 struct pci_dev *pdev = to_pci_dev(dev->dev);
2388
dca51e78 2389 pci_free_irq_vectors(pdev);
0877cb0d 2390
a0a3408e
KB		 2391 if (pci_is_enabled(pdev)) {
2392 pci_disable_pcie_error_reporting(pdev);
e75ec752 2393 pci_disable_device(pdev);
4d115420 2394 }
4d115420
KB		 2395}
2396
a5cdb68c 2397static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
b60503ba 2398{
302ad8cc
KB		 2399 bool dead = true;
2400 struct pci_dev *pdev = to_pci_dev(dev->dev);
22404274 2401
77bf25ea 2402 mutex_lock(&dev->shutdown_lock);
302ad8cc
KB		 2403 if (pci_is_enabled(pdev)) {
2404 u32 csts = readl(dev->bar + NVME_REG_CSTS);
2405
ebef7368
KB		 2406 if (dev->ctrl.state == NVME_CTRL_LIVE ||
2407 dev->ctrl.state == NVME_CTRL_RESETTING)
302ad8cc
KB		 2408 nvme_start_freeze(&dev->ctrl);
2409 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
2410 pdev->error_state != pci_channel_io_normal);
c9d3bf88 2411 }
c21377f8 2412
302ad8cc
KB		 2413 /*
2414 * Give the controller a chance to complete all entered requests if
2415 * doing a safe shutdown.
2416 */
87ad72a5
CH		 2417 if (!dead) {
2418 if (shutdown)
2419 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
9a915a5b
JW		 2420 }
2421
2422 nvme_stop_queues(&dev->ctrl);
87ad72a5 2423
64ee0ac0 2424 if (!dead && dev->ctrl.queue_count > 0) {
8fae268b 2425 nvme_disable_io_queues(dev);
a5cdb68c 2426 nvme_disable_admin_queue(dev, shutdown);
4d115420 2427 }
8fae268b
KB		 2428 nvme_suspend_io_queues(dev);
2429 nvme_suspend_queue(&dev->queues[0]);
b00a726a 2430 nvme_pci_disable(dev);
07836e65 2431
e1958e65
ML		 2432 blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
2433 blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
302ad8cc
KB		 2434
2435 /*
2436 * The driver will not be starting up queues again if shutting down so
2437 * must flush all entered requests to their failed completion to avoid
2438 * deadlocking blk-mq hot-cpu notifier.
2439 */
2440 if (shutdown)
2441 nvme_start_queues(&dev->ctrl);
77bf25ea 2442 mutex_unlock(&dev->shutdown_lock);
b60503ba
MW		 2443}
2444
091b6092
MW		 2445static int nvme_setup_prp_pools(struct nvme_dev *dev)
2446{
e75ec752 2447 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
091b6092
MW		 2448 PAGE_SIZE, PAGE_SIZE, 0);
2449 if (!dev->prp_page_pool)
2450 return -ENOMEM;
2451
99802a7a 2452 /* Optimisation for I/Os between 4k and 128k */
e75ec752 2453 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
99802a7a
MW		 2454 256, 256, 0);
2455 if (!dev->prp_small_pool) {
2456 dma_pool_destroy(dev->prp_page_pool);
2457 return -ENOMEM;
2458 }
091b6092
MW		 2459 return 0;
2460}
2461
2462static void nvme_release_prp_pools(struct nvme_dev *dev)
2463{
2464 dma_pool_destroy(dev->prp_page_pool);
99802a7a 2465 dma_pool_destroy(dev->prp_small_pool);
091b6092
MW		 2466}
2467
1673f1f0 2468static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
5e82e952 2469{
1673f1f0 2470 struct nvme_dev *dev = to_nvme_dev(ctrl);
9ac27090 2471
f9f38e33 2472 nvme_dbbuf_dma_free(dev);
e75ec752 2473 put_device(dev->dev);
4af0e21c
KB		 2474 if (dev->tagset.tags)
2475 blk_mq_free_tag_set(&dev->tagset);
1c63dc66
CH		 2476 if (dev->ctrl.admin_q)
2477 blk_put_queue(dev->ctrl.admin_q);
5e82e952 2478 kfree(dev->queues);
e286bcfc 2479 free_opal_dev(dev->ctrl.opal_dev);
943e942e 2480 mempool_destroy(dev->iod_mempool);
5e82e952
KB		 2481 kfree(dev);
2482}
2483
f58944e2
KB		 2484static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status)
2485{
237045fc 2486 dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status);
f58944e2 2487
d22524a4 2488 nvme_get_ctrl(&dev->ctrl);
69d9a99c 2489 nvme_dev_disable(dev, false);
9f9cafc1 2490 nvme_kill_queues(&dev->ctrl);
03e0f3a6 2491 if (!queue_work(nvme_wq, &dev->remove_work))
f58944e2
KB		 2492 nvme_put_ctrl(&dev->ctrl);
2493}
2494
fd634f41 2495static void nvme_reset_work(struct work_struct *work)
5e82e952 2496{
d86c4d8e
CH		 2497 struct nvme_dev *dev =
2498 container_of(work, struct nvme_dev, ctrl.reset_work);
a98e58e5 2499 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
f58944e2 2500 int result = -ENODEV;
2b1b7e78 2501 enum nvme_ctrl_state new_state = NVME_CTRL_LIVE;
5e82e952 2502
82b057ca 2503 if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING))
fd634f41 2504 goto out;
5e82e952 2505
fd634f41
CH		 2506 /*
2507 * If we're called to reset a live controller first shut it down before
2508 * moving on.
2509 */
b00a726a 2510 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
a5cdb68c 2511 nvme_dev_disable(dev, false);
5e82e952 2512
5c959d73 2513 mutex_lock(&dev->shutdown_lock);
b00a726a 2514 result = nvme_pci_enable(dev);
f0b50732 2515 if (result)
4726bcf3 2516 goto out_unlock;
f0b50732 2517
01ad0990 2518 result = nvme_pci_configure_admin_queue(dev);
f0b50732 2519 if (result)
4726bcf3 2520 goto out_unlock;
f0b50732 2521
0fb59cbc
KB		 2522 result = nvme_alloc_admin_tags(dev);
2523 if (result)
4726bcf3 2524 goto out_unlock;
b9afca3e 2525
943e942e
JA		 2526 /*
2527 * Limit the max command size to prevent iod->sg allocations going
2528 * over a single page.
2529 */
2530 dev->ctrl.max_hw_sectors = NVME_MAX_KB_SZ << 1;
2531 dev->ctrl.max_segments = NVME_MAX_SEGS;
5c959d73
KB		 2532 mutex_unlock(&dev->shutdown_lock);
2533
2534 /*
2535 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
2536 * initializing procedure here.
2537 */
2538 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
2539 dev_warn(dev->ctrl.device,
2540 "failed to mark controller CONNECTING\n");
2541 goto out;
2542 }
943e942e 2543
ce4541f4
CH		 2544 result = nvme_init_identify(&dev->ctrl);
2545 if (result)
f58944e2 2546 goto out;
ce4541f4 2547
e286bcfc
SB		 2548 if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
2549 if (!dev->ctrl.opal_dev)
2550 dev->ctrl.opal_dev =
2551 init_opal_dev(&dev->ctrl, &nvme_sec_submit);
2552 else if (was_suspend)
2553 opal_unlock_from_suspend(dev->ctrl.opal_dev);
2554 } else {
2555 free_opal_dev(dev->ctrl.opal_dev);
2556 dev->ctrl.opal_dev = NULL;
4f1244c8 2557 }
a98e58e5 2558
f9f38e33
HK		 2559 if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) {
2560 result = nvme_dbbuf_dma_alloc(dev);
2561 if (result)
2562 dev_warn(dev->dev,
2563 "unable to allocate dma for dbbuf\n");
2564 }
2565
9620cfba
CH		 2566 if (dev->ctrl.hmpre) {
2567 result = nvme_setup_host_mem(dev);
2568 if (result < 0)
2569 goto out;
2570 }
87ad72a5 2571
f0b50732 2572 result = nvme_setup_io_queues(dev);
badc34d4 2573 if (result)
f58944e2 2574 goto out;
f0b50732 2575
2659e57b
CH		 2576 /*
2577 * Keep the controller around but remove all namespaces if we don't have
2578 * any working I/O queue.
2579 */
3cf519b5 2580 if (dev->online_queues < 2) {
1b3c47c1 2581 dev_warn(dev->ctrl.device, "IO queues not created\n");
3b24774e 2582 nvme_kill_queues(&dev->ctrl);
5bae7f73 2583 nvme_remove_namespaces(&dev->ctrl);
2b1b7e78 2584 new_state = NVME_CTRL_ADMIN_ONLY;
3cf519b5 2585 } else {
25646264 2586 nvme_start_queues(&dev->ctrl);
302ad8cc 2587 nvme_wait_freeze(&dev->ctrl);
2b1b7e78
JW		 2588 /* hit this only when allocate tagset fails */
2589 if (nvme_dev_add(dev))
2590 new_state = NVME_CTRL_ADMIN_ONLY;
302ad8cc 2591 nvme_unfreeze(&dev->ctrl);
3cf519b5
CH		 2592 }
2593
2b1b7e78
JW		 2594 /*
2595 * If only admin queue live, keep it to do further investigation or
2596 * recovery.
2597 */
2598 if (!nvme_change_ctrl_state(&dev->ctrl, new_state)) {
2599 dev_warn(dev->ctrl.device,
2600 "failed to mark controller state %d\n", new_state);
bb8d261e
CH		 2601 goto out;
2602 }
92911a55 2603
d09f2b45 2604 nvme_start_ctrl(&dev->ctrl);
3cf519b5 2605 return;
f0b50732 2606
4726bcf3
KB		 2607 out_unlock:
2608 mutex_unlock(&dev->shutdown_lock);
3cf519b5 2609 out:
f58944e2 2610 nvme_remove_dead_ctrl(dev, result);
f0b50732
KB		 2611}
2612
5c8809e6 2613static void nvme_remove_dead_ctrl_work(struct work_struct *work)
9a6b9458 2614{
5c8809e6 2615 struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
e75ec752 2616 struct pci_dev *pdev = to_pci_dev(dev->dev);
9a6b9458
KB		 2617
2618 if (pci_get_drvdata(pdev))
921920ab 2619 device_release_driver(&pdev->dev);
1673f1f0 2620 nvme_put_ctrl(&dev->ctrl);
9a6b9458
KB		 2621}
2622
1c63dc66 2623static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
9ca97374 2624{
1c63dc66 2625 *val = readl(to_nvme_dev(ctrl)->bar + off);
90667892 2626 return 0;
9ca97374
TH		 2627}
2628
5fd4ce1b 2629static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
4cc06521 2630{
5fd4ce1b
CH		 2631 writel(val, to_nvme_dev(ctrl)->bar + off);
2632 return 0;
2633}
4cc06521 2634
7fd8930f
CH		 2635static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2636{
2637 *val = readq(to_nvme_dev(ctrl)->bar + off);
2638 return 0;
4cc06521
KB		 2639}
2640
97c12223
KB		 2641static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
2642{
2643 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2644
2645 return snprintf(buf, size, "%s", dev_name(&pdev->dev));
2646}
2647
1c63dc66 2648static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
1a353d85 2649 .name = "pcie",
e439bb12 2650 .module = THIS_MODULE,
e0596ab2
LG		 2651 .flags = NVME_F_METADATA_SUPPORTED |
2652 NVME_F_PCI_P2PDMA,
1c63dc66 2653 .reg_read32 = nvme_pci_reg_read32,
5fd4ce1b 2654 .reg_write32 = nvme_pci_reg_write32,
7fd8930f 2655 .reg_read64 = nvme_pci_reg_read64,
1673f1f0 2656 .free_ctrl = nvme_pci_free_ctrl,
f866fc42 2657 .submit_async_event = nvme_pci_submit_async_event,
97c12223 2658 .get_address = nvme_pci_get_address,
1c63dc66 2659};
4cc06521 2660
b00a726a
KB		 2661static int nvme_dev_map(struct nvme_dev *dev)
2662{
b00a726a
KB		 2663 struct pci_dev *pdev = to_pci_dev(dev->dev);
2664
a1f447b3 2665 if (pci_request_mem_regions(pdev, "nvme"))
b00a726a
KB		 2666 return -ENODEV;
2667
97f6ef64 2668 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
b00a726a
KB		 2669 goto release;
2670
9fa196e7 2671 return 0;
b00a726a 2672 release:
9fa196e7
MG		 2673 pci_release_mem_regions(pdev);
2674 return -ENODEV;
b00a726a
KB		 2675}
2676
8427bbc2 2677static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
ff5350a8
AL		 2678{
2679 if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
2680 /*
2681 * Several Samsung devices seem to drop off the PCIe bus
2682 * randomly when APST is on and uses the deepest sleep state.
2683 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2684 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2685 * 950 PRO 256GB", but it seems to be restricted to two Dell
2686 * laptops.
2687 */
2688 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
2689 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
2690 dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
2691 return NVME_QUIRK_NO_DEEPEST_PS;
8427bbc2
KHF		 2692 } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
2693 /*
2694 * Samsung SSD 960 EVO drops off the PCIe bus after system
467c77d4
JJ		 2695 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
2696 * within few minutes after bootup on a Coffee Lake board -
2697 * ASUS PRIME Z370-A
8427bbc2
KHF		 2698 */
2699 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
467c77d4
JJ		 2700 (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") ||
2701 dmi_match(DMI_BOARD_NAME, "PRIME Z370-A")))
8427bbc2 2702 return NVME_QUIRK_NO_APST;
ff5350a8
AL		 2703 }
2704
2705 return 0;
2706}
2707
18119775
KB		 2708static void nvme_async_probe(void *data, async_cookie_t cookie)
2709{
2710 struct nvme_dev *dev = data;
80f513b5 2711
18119775
KB		 2712 nvme_reset_ctrl_sync(&dev->ctrl);
2713 flush_work(&dev->ctrl.scan_work);
80f513b5 2714 nvme_put_ctrl(&dev->ctrl);
18119775
KB		 2715}
2716
8d85fce7 2717static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
b60503ba 2718{
a4aea562 2719 int node, result = -ENOMEM;
b60503ba 2720 struct nvme_dev *dev;
ff5350a8 2721 unsigned long quirks = id->driver_data;
943e942e 2722 size_t alloc_size;
b60503ba 2723
a4aea562
MB		 2724 node = dev_to_node(&pdev->dev);
2725 if (node == NUMA_NO_NODE)
2fa84351 2726 set_dev_node(&pdev->dev, first_memory_node);
a4aea562
MB		 2727
2728 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
b60503ba
MW		 2729 if (!dev)
2730 return -ENOMEM;
147b27e4 2731
3b6592f7
JA		 2732 dev->queues = kcalloc_node(max_queue_count(), sizeof(struct nvme_queue),
2733 GFP_KERNEL, node);
b60503ba
MW		 2734 if (!dev->queues)
2735 goto free;
2736
e75ec752 2737 dev->dev = get_device(&pdev->dev);
9a6b9458 2738 pci_set_drvdata(pdev, dev);
1c63dc66 2739
b00a726a
KB		 2740 result = nvme_dev_map(dev);
2741 if (result)
b00c9b7a 2742 goto put_pci;
b00a726a 2743
d86c4d8e 2744 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
5c8809e6 2745 INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
77bf25ea 2746 mutex_init(&dev->shutdown_lock);
b60503ba 2747
091b6092
MW		 2748 result = nvme_setup_prp_pools(dev);
2749 if (result)
b00c9b7a 2750 goto unmap;
4cc06521 2751
8427bbc2 2752 quirks |= check_vendor_combination_bug(pdev);
ff5350a8 2753
943e942e
JA		 2754 /*
2755 * Double check that our mempool alloc size will cover the biggest
2756 * command we support.
2757 */
2758 alloc_size = nvme_pci_iod_alloc_size(dev, NVME_MAX_KB_SZ,
2759 NVME_MAX_SEGS, true);
2760 WARN_ON_ONCE(alloc_size > PAGE_SIZE);
2761
2762 dev->iod_mempool = mempool_create_node(1, mempool_kmalloc,
2763 mempool_kfree,
2764 (void *) alloc_size,
2765 GFP_KERNEL, node);
2766 if (!dev->iod_mempool) {
2767 result = -ENOMEM;
2768 goto release_pools;
2769 }
2770
b6e44b4c
KB		 2771 result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
2772 quirks);
2773 if (result)
2774 goto release_mempool;
2775
1b3c47c1
SG		 2776 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
2777
80f513b5 2778 nvme_get_ctrl(&dev->ctrl);
18119775 2779 async_schedule(nvme_async_probe, dev);
4caff8fc 2780
b60503ba
MW		 2781 return 0;
2782
b6e44b4c
KB		 2783 release_mempool:
2784 mempool_destroy(dev->iod_mempool);
0877cb0d 2785 release_pools:
091b6092 2786 nvme_release_prp_pools(dev);
b00c9b7a
CJ		 2787 unmap:
2788 nvme_dev_unmap(dev);
a96d4f5c 2789 put_pci:
e75ec752 2790 put_device(dev->dev);
b60503ba
MW		 2791 free:
2792 kfree(dev->queues);
b60503ba
MW		 2793 kfree(dev);
2794 return result;
2795}
2796
775755ed 2797static void nvme_reset_prepare(struct pci_dev *pdev)
f0d54a54 2798{
a6739479 2799 struct nvme_dev *dev = pci_get_drvdata(pdev);
f263fbb8 2800 nvme_dev_disable(dev, false);
775755ed 2801}
f0d54a54 2802
775755ed
CH		 2803static void nvme_reset_done(struct pci_dev *pdev)
2804{
f263fbb8 2805 struct nvme_dev *dev = pci_get_drvdata(pdev);
79c48ccf 2806 nvme_reset_ctrl_sync(&dev->ctrl);
f0d54a54
KB		 2807}
2808
09ece142
KB		 2809static void nvme_shutdown(struct pci_dev *pdev)
2810{
2811 struct nvme_dev *dev = pci_get_drvdata(pdev);
a5cdb68c 2812 nvme_dev_disable(dev, true);
09ece142
KB		 2813}
2814
f58944e2
KB		 2815/*
2816 * The driver's remove may be called on a device in a partially initialized
2817 * state. This function must not have any dependencies on the device state in
2818 * order to proceed.
2819 */
8d85fce7 2820static void nvme_remove(struct pci_dev *pdev)
b60503ba
MW		 2821{
2822 struct nvme_dev *dev = pci_get_drvdata(pdev);
9a6b9458 2823
bb8d261e 2824 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
9a6b9458 2825 pci_set_drvdata(pdev, NULL);
0ff9d4e1 2826
6db28eda 2827 if (!pci_device_is_present(pdev)) {
0ff9d4e1 2828 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
1d39e692 2829 nvme_dev_disable(dev, true);
cb4bfda6 2830 nvme_dev_remove_admin(dev);
6db28eda 2831 }
0ff9d4e1 2832
d86c4d8e 2833 flush_work(&dev->ctrl.reset_work);
d09f2b45
SG		 2834 nvme_stop_ctrl(&dev->ctrl);
2835 nvme_remove_namespaces(&dev->ctrl);
a5cdb68c 2836 nvme_dev_disable(dev, true);
9fe5c59f 2837 nvme_release_cmb(dev);
87ad72a5 2838 nvme_free_host_mem(dev);
a4aea562 2839 nvme_dev_remove_admin(dev);
a1a5ef99 2840 nvme_free_queues(dev, 0);
d09f2b45 2841 nvme_uninit_ctrl(&dev->ctrl);
9a6b9458 2842 nvme_release_prp_pools(dev);
b00a726a 2843 nvme_dev_unmap(dev);
1673f1f0 2844 nvme_put_ctrl(&dev->ctrl);
b60503ba
MW		 2845}
2846
671a6018 2847#ifdef CONFIG_PM_SLEEP
cd638946
KB		 2848static int nvme_suspend(struct device *dev)
2849{
2850 struct pci_dev *pdev = to_pci_dev(dev);
2851 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2852
a5cdb68c 2853 nvme_dev_disable(ndev, true);
cd638946
KB		 2854 return 0;
2855}
2856
2857static int nvme_resume(struct device *dev)
2858{
2859 struct pci_dev *pdev = to_pci_dev(dev);
2860 struct nvme_dev *ndev = pci_get_drvdata(pdev);
cd638946 2861
d86c4d8e 2862 nvme_reset_ctrl(&ndev->ctrl);
9a6b9458 2863 return 0;
cd638946 2864}
671a6018 2865#endif
cd638946
KB		 2866
2867static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
b60503ba 2868
a0a3408e
KB		 2869static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
2870 pci_channel_state_t state)
2871{
2872 struct nvme_dev *dev = pci_get_drvdata(pdev);
2873
2874 /*
2875 * A frozen channel requires a reset. When detected, this method will
2876 * shutdown the controller to quiesce. The controller will be restarted
2877 * after the slot reset through driver's slot_reset callback.
2878 */
a0a3408e
KB		 2879 switch (state) {
2880 case pci_channel_io_normal:
2881 return PCI_ERS_RESULT_CAN_RECOVER;
2882 case pci_channel_io_frozen:
d011fb31
KB		 2883 dev_warn(dev->ctrl.device,
2884 "frozen state error detected, reset controller\n");
a5cdb68c 2885 nvme_dev_disable(dev, false);
a0a3408e
KB		 2886 return PCI_ERS_RESULT_NEED_RESET;
2887 case pci_channel_io_perm_failure:
d011fb31
KB		 2888 dev_warn(dev->ctrl.device,
2889 "failure state error detected, request disconnect\n");
a0a3408e
KB		 2890 return PCI_ERS_RESULT_DISCONNECT;
2891 }
2892 return PCI_ERS_RESULT_NEED_RESET;
2893}
2894
2895static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
2896{
2897 struct nvme_dev *dev = pci_get_drvdata(pdev);
2898
1b3c47c1 2899 dev_info(dev->ctrl.device, "restart after slot reset\n");
a0a3408e 2900 pci_restore_state(pdev);
d86c4d8e 2901 nvme_reset_ctrl(&dev->ctrl);
a0a3408e
KB		 2902 return PCI_ERS_RESULT_RECOVERED;
2903}
2904
2905static void nvme_error_resume(struct pci_dev *pdev)
2906{
72cd4cc2
KB		 2907 struct nvme_dev *dev = pci_get_drvdata(pdev);
2908
2909 flush_work(&dev->ctrl.reset_work);
a0a3408e
KB		 2910}
2911
1d352035 2912static const struct pci_error_handlers nvme_err_handler = {
b60503ba 2913 .error_detected = nvme_error_detected,
b60503ba
MW		 2914 .slot_reset = nvme_slot_reset,
2915 .resume = nvme_error_resume,
775755ed
CH		 2916 .reset_prepare = nvme_reset_prepare,
2917 .reset_done = nvme_reset_done,
b60503ba
MW		 2918};
2919
6eb0d698 2920static const struct pci_device_id nvme_id_table[] = {
106198ed 2921 { PCI_VDEVICE(INTEL, 0x0953),
08095e70 2922 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 2923 NVME_QUIRK_DEALLOCATE_ZEROES, },
99466e70
KB		 2924 { PCI_VDEVICE(INTEL, 0x0a53),
2925 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 2926 NVME_QUIRK_DEALLOCATE_ZEROES, },
99466e70
KB		 2927 { PCI_VDEVICE(INTEL, 0x0a54),
2928 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 2929 NVME_QUIRK_DEALLOCATE_ZEROES, },
f99cb7af
DWF		 2930 { PCI_VDEVICE(INTEL, 0x0a55),
2931 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2932 NVME_QUIRK_DEALLOCATE_ZEROES, },
50af47d0 2933 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */
9abd68ef
JA		 2934 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
2935 NVME_QUIRK_MEDIUM_PRIO_SQ },
6299358d
JD		 2936 { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */
2937 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
540c801c 2938 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */
7b210e4e
CH		 2939 .driver_data = NVME_QUIRK_IDENTIFY_CNS |
2940 NVME_QUIRK_DISABLE_WRITE_ZEROES, },
0302ae60
MP		 2941 { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */
2942 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
54adc010
GP		 2943 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
2944 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
8c97eecc
JL		 2945 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */
2946 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
015282c9
WW		 2947 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
2948 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
d554b5e1
MP		 2949 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */
2950 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2951 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */
2952 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
608cc4b1
CH		 2953 { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */
2954 .driver_data = NVME_QUIRK_LIGHTNVM, },
2955 { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */
2956 .driver_data = NVME_QUIRK_LIGHTNVM, },
ea48e877
WX		 2957 { PCI_DEVICE(0x1d1d, 0x2601), /* CNEX Granby */
2958 .driver_data = NVME_QUIRK_LIGHTNVM, },
b60503ba 2959 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
c74dc780 2960 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) },
124298bd 2961 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
b60503ba
MW		 2962 { 0, }
2963};
2964MODULE_DEVICE_TABLE(pci, nvme_id_table);
2965
2966static struct pci_driver nvme_driver = {
2967 .name = "nvme",
2968 .id_table = nvme_id_table,
2969 .probe = nvme_probe,
8d85fce7 2970 .remove = nvme_remove,
09ece142 2971 .shutdown = nvme_shutdown,
cd638946
KB		 2972 .driver = {
2973 .pm = &nvme_dev_pm_ops,
2974 },
74d986ab 2975 .sriov_configure = pci_sriov_configure_simple,
b60503ba
MW		 2976 .err_handler = &nvme_err_handler,
2977};
2978
2979static int __init nvme_init(void)
2980{
612b7286 2981 BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2);
9a6327d2 2982 return pci_register_driver(&nvme_driver);
b60503ba
MW		 2983}
2984
2985static void __exit nvme_exit(void)
2986{
2987 pci_unregister_driver(&nvme_driver);
03e0f3a6 2988 flush_workqueue(nvme_wq);
21bd78bc 2989 _nvme_check_size();
b60503ba
MW		 2990}
2991
2992MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2993MODULE_LICENSE("GPL");
c78b4713 2994MODULE_VERSION("1.0");
b60503ba
MW		 2995module_init(nvme_init);
2996module_exit(nvme_exit);
Linux 6.x block layer and io_uring tree(s)