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Merge tag 'nvme-6.2-2023-02-15' of git://git.infradead.org/nvme into block-6.2
[linux-2.6-block.git] / drivers / nvme / host / pci.c
CommitLineData
5f37396d 1// SPDX-License-Identifier: GPL-2.0
b60503ba
MW		 2/*
3 * NVM Express device driver
6eb0d698 4 * Copyright (c) 2011-2014, Intel Corporation.
b60503ba
MW		 5 */
6
df4f9bc4 7#include <linux/acpi.h>
a0a3408e 8#include <linux/aer.h>
18119775 9#include <linux/async.h>
b60503ba 10#include <linux/blkdev.h>
a4aea562 11#include <linux/blk-mq.h>
dca51e78 12#include <linux/blk-mq-pci.h>
fe45e630 13#include <linux/blk-integrity.h>
ff5350a8 14#include <linux/dmi.h>
b60503ba
MW		 15#include <linux/init.h>
16#include <linux/interrupt.h>
17#include <linux/io.h>
99722c8a 18#include <linux/kstrtox.h>
dc90f084 19#include <linux/memremap.h>
b60503ba
MW		 20#include <linux/mm.h>
21#include <linux/module.h>
77bf25ea 22#include <linux/mutex.h>
d0877473 23#include <linux/once.h>
b60503ba 24#include <linux/pci.h>
d916b1be 25#include <linux/suspend.h>
e1e5e564 26#include <linux/t10-pi.h>
b60503ba 27#include <linux/types.h>
2f8e2c87 28#include <linux/io-64-nonatomic-lo-hi.h>
20d3bb92 29#include <linux/io-64-nonatomic-hi-lo.h>
a98e58e5 30#include <linux/sed-opal.h>
0f238ff5 31#include <linux/pci-p2pdma.h>
797a796a 32
604c01d5 33#include "trace.h"
f11bb3e2
CH		 34#include "nvme.h"
35
c1e0cc7e 36#define SQ_SIZE(q) ((q)->q_depth << (q)->sqes)
8a1d09a6 37#define CQ_SIZE(q) ((q)->q_depth * sizeof(struct nvme_completion))
c965809c 38
84173423 39#define SGES_PER_PAGE (NVME_CTRL_PAGE_SIZE / sizeof(struct nvme_sgl_desc))
9d43cf64 40
943e942e
JA		 41/*
42 * These can be higher, but we need to ensure that any command doesn't
43 * require an sg allocation that needs more than a page of data.
44 */
45#define NVME_MAX_KB_SZ 4096
46#define NVME_MAX_SEGS 127
47
58ffacb5 48static int use_threaded_interrupts;
2e21e445 49module_param(use_threaded_interrupts, int, 0444);
58ffacb5 50
8ffaadf7 51static bool use_cmb_sqes = true;
69f4eb9f 52module_param(use_cmb_sqes, bool, 0444);
8ffaadf7
JD		 53MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
54
87ad72a5
CH		 55static unsigned int max_host_mem_size_mb = 128;
56module_param(max_host_mem_size_mb, uint, 0444);
57MODULE_PARM_DESC(max_host_mem_size_mb,
58 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
1fa6aead 59
a7a7cbe3
CK		 60static unsigned int sgl_threshold = SZ_32K;
61module_param(sgl_threshold, uint, 0644);
62MODULE_PARM_DESC(sgl_threshold,
63 "Use SGLs when average request segment size is larger or equal to "
64 "this size. Use 0 to disable SGLs.");
65
27453b45
SG		 66#define NVME_PCI_MIN_QUEUE_SIZE 2
67#define NVME_PCI_MAX_QUEUE_SIZE 4095
b27c1e68 68static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
69static const struct kernel_param_ops io_queue_depth_ops = {
70 .set = io_queue_depth_set,
61f3b896 71 .get = param_get_uint,
b27c1e68 72};
73
61f3b896 74static unsigned int io_queue_depth = 1024;
b27c1e68 75module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
27453b45 76MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2 and < 4096");
b27c1e68 77
9c9e76d5
WZ		 78static int io_queue_count_set(const char *val, const struct kernel_param *kp)
79{
80 unsigned int n;
81 int ret;
82
83 ret = kstrtouint(val, 10, &n);
84 if (ret != 0 || n > num_possible_cpus())
85 return -EINVAL;
86 return param_set_uint(val, kp);
87}
88
89static const struct kernel_param_ops io_queue_count_ops = {
90 .set = io_queue_count_set,
91 .get = param_get_uint,
92};
93
3f68baf7 94static unsigned int write_queues;
9c9e76d5 95module_param_cb(write_queues, &io_queue_count_ops, &write_queues, 0644);
3b6592f7
JA		 96MODULE_PARM_DESC(write_queues,
97 "Number of queues to use for writes. If not set, reads and writes "
98 "will share a queue set.");
99
3f68baf7 100static unsigned int poll_queues;
9c9e76d5 101module_param_cb(poll_queues, &io_queue_count_ops, &poll_queues, 0644);
4b04cc6a
JA		 102MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO.");
103
df4f9bc4
DB		 104static bool noacpi;
105module_param(noacpi, bool, 0444);
106MODULE_PARM_DESC(noacpi, "disable acpi bios quirks");
107
1c63dc66
CH		 108struct nvme_dev;
109struct nvme_queue;
b3fffdef 110
a5cdb68c 111static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
7d879c90 112static void nvme_delete_io_queues(struct nvme_dev *dev);
d4b4ff8e 113
1c63dc66
CH		 114/*
115 * Represents an NVM Express device. Each nvme_dev is a PCI function.
116 */
117struct nvme_dev {
147b27e4 118 struct nvme_queue *queues;
1c63dc66
CH		 119 struct blk_mq_tag_set tagset;
120 struct blk_mq_tag_set admin_tagset;
121 u32 __iomem *dbs;
122 struct device *dev;
123 struct dma_pool *prp_page_pool;
124 struct dma_pool *prp_small_pool;
1c63dc66
CH		 125 unsigned online_queues;
126 unsigned max_qid;
e20ba6e1 127 unsigned io_queues[HCTX_MAX_TYPES];
22b55601 128 unsigned int num_vecs;
7442ddce 129 u32 q_depth;
c1e0cc7e 130 int io_sqes;
1c63dc66 131 u32 db_stride;
1c63dc66 132 void __iomem *bar;
97f6ef64 133 unsigned long bar_mapped_size;
77bf25ea 134 struct mutex shutdown_lock;
1c63dc66 135 bool subsystem;
1c63dc66 136 u64 cmb_size;
0f238ff5 137 bool cmb_use_sqes;
1c63dc66 138 u32 cmbsz;
202021c1 139 u32 cmbloc;
1c63dc66 140 struct nvme_ctrl ctrl;
d916b1be 141 u32 last_ps;
a5df5e79 142 bool hmb;
87ad72a5 143
943e942e
JA		 144 mempool_t *iod_mempool;
145
87ad72a5 146 /* shadow doorbell buffer support: */
b5f96cb7 147 __le32 *dbbuf_dbs;
f9f38e33 148 dma_addr_t dbbuf_dbs_dma_addr;
b5f96cb7 149 __le32 *dbbuf_eis;
f9f38e33 150 dma_addr_t dbbuf_eis_dma_addr;
87ad72a5
CH		 151
152 /* host memory buffer support: */
153 u64 host_mem_size;
154 u32 nr_host_mem_descs;
4033f35d 155 dma_addr_t host_mem_descs_dma;
87ad72a5
CH		 156 struct nvme_host_mem_buf_desc *host_mem_descs;
157 void **host_mem_desc_bufs;
2a5bcfdd
WZ		 158 unsigned int nr_allocated_queues;
159 unsigned int nr_write_queues;
160 unsigned int nr_poll_queues;
4d115420 161};
1fa6aead 162
b27c1e68 163static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
164{
27453b45
SG		 165 return param_set_uint_minmax(val, kp, NVME_PCI_MIN_QUEUE_SIZE,
166 NVME_PCI_MAX_QUEUE_SIZE);
b27c1e68 167}
168
f9f38e33
HK		 169static inline unsigned int sq_idx(unsigned int qid, u32 stride)
170{
171 return qid * 2 * stride;
172}
173
174static inline unsigned int cq_idx(unsigned int qid, u32 stride)
175{
176 return (qid * 2 + 1) * stride;
177}
178
1c63dc66
CH		 179static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
180{
181 return container_of(ctrl, struct nvme_dev, ctrl);
182}
183
b60503ba
MW		 184/*
185 * An NVM Express queue. Each device has at least two (one for admin
186 * commands and one for I/O commands).
187 */
188struct nvme_queue {
091b6092 189 struct nvme_dev *dev;
1ab0cd69 190 spinlock_t sq_lock;
c1e0cc7e 191 void *sq_cmds;
3a7afd8e
CH		 192 /* only used for poll queues: */
193 spinlock_t cq_poll_lock ____cacheline_aligned_in_smp;
74943d45 194 struct nvme_completion *cqes;
b60503ba
MW		 195 dma_addr_t sq_dma_addr;
196 dma_addr_t cq_dma_addr;
b60503ba 197 u32 __iomem *q_db;
7442ddce 198 u32 q_depth;
7c349dde 199 u16 cq_vector;
b60503ba 200 u16 sq_tail;
38210800 201 u16 last_sq_tail;
b60503ba 202 u16 cq_head;
c30341dc 203 u16 qid;
e9539f47 204 u8 cq_phase;
c1e0cc7e 205 u8 sqes;
4e224106
CH		 206 unsigned long flags;
207#define NVMEQ_ENABLED 0
63223078 208#define NVMEQ_SQ_CMB 1
d1ed6aa1 209#define NVMEQ_DELETE_ERROR 2
7c349dde 210#define NVMEQ_POLLED 3
b5f96cb7
KJ		 211 __le32 *dbbuf_sq_db;
212 __le32 *dbbuf_cq_db;
213 __le32 *dbbuf_sq_ei;
214 __le32 *dbbuf_cq_ei;
d1ed6aa1 215 struct completion delete_done;
b60503ba
MW		 216};
217
71bd150c 218/*
9b048119
CH		 219 * The nvme_iod describes the data in an I/O.
220 *
221 * The sg pointer contains the list of PRP/SGL chunk allocations in addition
222 * to the actual struct scatterlist.
71bd150c
CH		 223 */
224struct nvme_iod {
d49187e9 225 struct nvme_request req;
af7fae85 226 struct nvme_command cmd;
a7a7cbe3 227 bool use_sgl;
52da4f3f 228 bool aborted;
c372cdd1
KB		 229 s8 nr_allocations; /* PRP list pool allocations. 0 means small
230 pool in use */
dff824b2 231 unsigned int dma_len; /* length of single DMA segment mapping */
c4c22c52 232 dma_addr_t first_dma;
783b94bd 233 dma_addr_t meta_dma;
91fb2b60 234 struct sg_table sgt;
b60503ba
MW		 235};
236
2a5bcfdd 237static inline unsigned int nvme_dbbuf_size(struct nvme_dev *dev)
3b6592f7 238{
2a5bcfdd 239 return dev->nr_allocated_queues * 8 * dev->db_stride;
f9f38e33
HK		 240}
241
65a54646 242static void nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
f9f38e33 243{
2a5bcfdd 244 unsigned int mem_size = nvme_dbbuf_size(dev);
f9f38e33 245
65a54646
CH		 246 if (!(dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP))
247 return;
248
58847f12
KB		 249 if (dev->dbbuf_dbs) {
250 /*
251 * Clear the dbbuf memory so the driver doesn't observe stale
252 * values from the previous instantiation.
253 */
254 memset(dev->dbbuf_dbs, 0, mem_size);
255 memset(dev->dbbuf_eis, 0, mem_size);
65a54646 256 return;
58847f12 257 }
f9f38e33
HK		 258
259 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
260 &dev->dbbuf_dbs_dma_addr,
261 GFP_KERNEL);
262 if (!dev->dbbuf_dbs)
65a54646 263 goto fail;
f9f38e33
HK		 264 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
265 &dev->dbbuf_eis_dma_addr,
266 GFP_KERNEL);
65a54646
CH		 267 if (!dev->dbbuf_eis)
268 goto fail_free_dbbuf_dbs;
269 return;
f9f38e33 270
65a54646
CH		 271fail_free_dbbuf_dbs:
272 dma_free_coherent(dev->dev, mem_size, dev->dbbuf_dbs,
273 dev->dbbuf_dbs_dma_addr);
274 dev->dbbuf_dbs = NULL;
275fail:
276 dev_warn(dev->dev, "unable to allocate dma for dbbuf\n");
f9f38e33
HK		 277}
278
279static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
280{
2a5bcfdd 281 unsigned int mem_size = nvme_dbbuf_size(dev);
f9f38e33
HK		 282
283 if (dev->dbbuf_dbs) {
284 dma_free_coherent(dev->dev, mem_size,
285 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
286 dev->dbbuf_dbs = NULL;
287 }
288 if (dev->dbbuf_eis) {
289 dma_free_coherent(dev->dev, mem_size,
290 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
291 dev->dbbuf_eis = NULL;
292 }
293}
294
295static void nvme_dbbuf_init(struct nvme_dev *dev,
296 struct nvme_queue *nvmeq, int qid)
297{
298 if (!dev->dbbuf_dbs || !qid)
299 return;
300
301 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
302 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
303 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
304 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
305}
306
0f0d2c87
MI		 307static void nvme_dbbuf_free(struct nvme_queue *nvmeq)
308{
309 if (!nvmeq->qid)
310 return;
311
312 nvmeq->dbbuf_sq_db = NULL;
313 nvmeq->dbbuf_cq_db = NULL;
314 nvmeq->dbbuf_sq_ei = NULL;
315 nvmeq->dbbuf_cq_ei = NULL;
316}
317
f9f38e33
HK		 318static void nvme_dbbuf_set(struct nvme_dev *dev)
319{
f66e2804 320 struct nvme_command c = { };
0f0d2c87 321 unsigned int i;
f9f38e33
HK		 322
323 if (!dev->dbbuf_dbs)
324 return;
325
f9f38e33
HK		 326 c.dbbuf.opcode = nvme_admin_dbbuf;
327 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
328 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
329
330 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
9bdcfb10 331 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
f9f38e33
HK		 332 /* Free memory and continue on */
333 nvme_dbbuf_dma_free(dev);
0f0d2c87
MI		 334
335 for (i = 1; i <= dev->online_queues; i++)
336 nvme_dbbuf_free(&dev->queues[i]);
f9f38e33
HK		 337 }
338}
339
340static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
341{
342 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
343}
344
345/* Update dbbuf and return true if an MMIO is required */
b5f96cb7
KJ		 346static bool nvme_dbbuf_update_and_check_event(u16 value, __le32 *dbbuf_db,
347 volatile __le32 *dbbuf_ei)
f9f38e33
HK		 348{
349 if (dbbuf_db) {
b5f96cb7 350 u16 old_value, event_idx;
f9f38e33
HK		 351
352 /*
353 * Ensure that the queue is written before updating
354 * the doorbell in memory
355 */
356 wmb();
357
b5f96cb7
KJ		 358 old_value = le32_to_cpu(*dbbuf_db);
359 *dbbuf_db = cpu_to_le32(value);
f9f38e33 360
f1ed3df2
MW		 361 /*
362 * Ensure that the doorbell is updated before reading the event
363 * index from memory. The controller needs to provide similar
364 * ordering to ensure the envent index is updated before reading
365 * the doorbell.
366 */
367 mb();
368
b5f96cb7
KJ		 369 event_idx = le32_to_cpu(*dbbuf_ei);
370 if (!nvme_dbbuf_need_event(event_idx, value, old_value))
f9f38e33
HK		 371 return false;
372 }
373
374 return true;
b60503ba
MW		 375}
376
ac3dd5bd
JA		 377/*
378 * Will slightly overestimate the number of pages needed. This is OK
379 * as it only leads to a small amount of wasted memory for the lifetime of
380 * the I/O.
381 */
b13c6393 382static int nvme_pci_npages_prp(void)
ac3dd5bd 383{
c89a529e
KB		 384 unsigned max_bytes = (NVME_MAX_KB_SZ * 1024) + NVME_CTRL_PAGE_SIZE;
385 unsigned nprps = DIV_ROUND_UP(max_bytes, NVME_CTRL_PAGE_SIZE);
84173423 386 return DIV_ROUND_UP(8 * nprps, NVME_CTRL_PAGE_SIZE - 8);
ac3dd5bd
JA		 387}
388
a7a7cbe3
CK		 389/*
390 * Calculates the number of pages needed for the SGL segments. For example a 4k
391 * page can accommodate 256 SGL descriptors.
392 */
b13c6393 393static int nvme_pci_npages_sgl(void)
ac3dd5bd 394{
b13c6393 395 return DIV_ROUND_UP(NVME_MAX_SEGS * sizeof(struct nvme_sgl_desc),
84173423 396 NVME_CTRL_PAGE_SIZE);
f4800d6d 397}
ac3dd5bd 398
a4aea562
MB		 399static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
400 unsigned int hctx_idx)
e85248e5 401{
0da7feaa 402 struct nvme_dev *dev = to_nvme_dev(data);
147b27e4 403 struct nvme_queue *nvmeq = &dev->queues[0];
a4aea562 404
42483228
KB		 405 WARN_ON(hctx_idx != 0);
406 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
42483228 407
a4aea562
MB		 408 hctx->driver_data = nvmeq;
409 return 0;
e85248e5
MW		 410}
411
a4aea562
MB		 412static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
413 unsigned int hctx_idx)
b60503ba 414{
0da7feaa 415 struct nvme_dev *dev = to_nvme_dev(data);
147b27e4 416 struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
a4aea562 417
42483228 418 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
a4aea562
MB		 419 hctx->driver_data = nvmeq;
420 return 0;
b60503ba
MW		 421}
422
e559398f
CH		 423static int nvme_pci_init_request(struct blk_mq_tag_set *set,
424 struct request *req, unsigned int hctx_idx,
425 unsigned int numa_node)
b60503ba 426{
0da7feaa 427 struct nvme_dev *dev = to_nvme_dev(set->driver_data);
f4800d6d 428 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
59e29ce6
SG		 429
430 nvme_req(req)->ctrl = &dev->ctrl;
f4b9e6c9 431 nvme_req(req)->cmd = &iod->cmd;
a4aea562
MB		 432 return 0;
433}
434
3b6592f7
JA		 435static int queue_irq_offset(struct nvme_dev *dev)
436{
437 /* if we have more than 1 vec, admin queue offsets us by 1 */
438 if (dev->num_vecs > 1)
439 return 1;
440
441 return 0;
442}
443
a4e1d0b7 444static void nvme_pci_map_queues(struct blk_mq_tag_set *set)
dca51e78 445{
0da7feaa 446 struct nvme_dev *dev = to_nvme_dev(set->driver_data);
3b6592f7
JA		 447 int i, qoff, offset;
448
449 offset = queue_irq_offset(dev);
450 for (i = 0, qoff = 0; i < set->nr_maps; i++) {
451 struct blk_mq_queue_map *map = &set->map[i];
452
453 map->nr_queues = dev->io_queues[i];
454 if (!map->nr_queues) {
e20ba6e1 455 BUG_ON(i == HCTX_TYPE_DEFAULT);
7e849dd9 456 continue;
3b6592f7
JA		 457 }
458
4b04cc6a
JA		 459 /*
460 * The poll queue(s) doesn't have an IRQ (and hence IRQ
461 * affinity), so use the regular blk-mq cpu mapping
462 */
3b6592f7 463 map->queue_offset = qoff;
cb9e0e50 464 if (i != HCTX_TYPE_POLL && offset)
4b04cc6a
JA		 465 blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset);
466 else
467 blk_mq_map_queues(map);
3b6592f7
JA		 468 qoff += map->nr_queues;
469 offset += map->nr_queues;
470 }
dca51e78
CH		 471}
472
38210800
KB		 473/*
474 * Write sq tail if we are asked to, or if the next command would wrap.
475 */
476static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq)
04f3eafd 477{
38210800
KB		 478 if (!write_sq) {
479 u16 next_tail = nvmeq->sq_tail + 1;
480
481 if (next_tail == nvmeq->q_depth)
482 next_tail = 0;
483 if (next_tail != nvmeq->last_sq_tail)
484 return;
485 }
486
04f3eafd
JA		 487 if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail,
488 nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei))
489 writel(nvmeq->sq_tail, nvmeq->q_db);
38210800 490 nvmeq->last_sq_tail = nvmeq->sq_tail;
04f3eafd
JA		 491}
492
3233b94c
JA		 493static inline void nvme_sq_copy_cmd(struct nvme_queue *nvmeq,
494 struct nvme_command *cmd)
b60503ba 495{
c1e0cc7e 496 memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes),
3233b94c 497 absolute_pointer(cmd), sizeof(*cmd));
90ea5ca4
CH		 498 if (++nvmeq->sq_tail == nvmeq->q_depth)
499 nvmeq->sq_tail = 0;
04f3eafd
JA		 500}
501
502static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx)
503{
504 struct nvme_queue *nvmeq = hctx->driver_data;
505
506 spin_lock(&nvmeq->sq_lock);
38210800
KB		 507 if (nvmeq->sq_tail != nvmeq->last_sq_tail)
508 nvme_write_sq_db(nvmeq, true);
90ea5ca4 509 spin_unlock(&nvmeq->sq_lock);
b60503ba
MW		 510}
511
a7a7cbe3 512static void **nvme_pci_iod_list(struct request *req)
b60503ba 513{
f4800d6d 514 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
91fb2b60 515 return (void **)(iod->sgt.sgl + blk_rq_nr_phys_segments(req));
b60503ba
MW		 516}
517
955b1b5a
MI		 518static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req)
519{
a53232cb 520 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
20469a37 521 int nseg = blk_rq_nr_phys_segments(req);
955b1b5a
MI		 522 unsigned int avg_seg_size;
523
20469a37 524 avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
955b1b5a 525
253a0b76 526 if (!nvme_ctrl_sgl_supported(&dev->ctrl))
955b1b5a 527 return false;
a53232cb 528 if (!nvmeq->qid)
955b1b5a
MI		 529 return false;
530 if (!sgl_threshold || avg_seg_size < sgl_threshold)
531 return false;
532 return true;
533}
534
9275c206 535static void nvme_free_prps(struct nvme_dev *dev, struct request *req)
b60503ba 536{
6c3c05b0 537 const int last_prp = NVME_CTRL_PAGE_SIZE / sizeof(__le64) - 1;
9275c206
CH		 538 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
539 dma_addr_t dma_addr = iod->first_dma;
eca18b23 540 int i;
eca18b23 541
c372cdd1 542 for (i = 0; i < iod->nr_allocations; i++) {
9275c206
CH		 543 __le64 *prp_list = nvme_pci_iod_list(req)[i];
544 dma_addr_t next_dma_addr = le64_to_cpu(prp_list[last_prp]);
545
546 dma_pool_free(dev->prp_page_pool, prp_list, dma_addr);
547 dma_addr = next_dma_addr;
7fe07d14 548 }
9275c206 549}
dff824b2 550
9275c206
CH		 551static void nvme_free_sgls(struct nvme_dev *dev, struct request *req)
552{
553 const int last_sg = SGES_PER_PAGE - 1;
554 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
555 dma_addr_t dma_addr = iod->first_dma;
556 int i;
dff824b2 557
c372cdd1 558 for (i = 0; i < iod->nr_allocations; i++) {
9275c206
CH		 559 struct nvme_sgl_desc *sg_list = nvme_pci_iod_list(req)[i];
560 dma_addr_t next_dma_addr = le64_to_cpu((sg_list[last_sg]).addr);
dff824b2 561
9275c206
CH		 562 dma_pool_free(dev->prp_page_pool, sg_list, dma_addr);
563 dma_addr = next_dma_addr;
564 }
9275c206 565}
a7a7cbe3 566
9275c206
CH		 567static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
568{
569 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3 570
9275c206
CH		 571 if (iod->dma_len) {
572 dma_unmap_page(dev->dev, iod->first_dma, iod->dma_len,
573 rq_dma_dir(req));
574 return;
eca18b23 575 }
ac3dd5bd 576
91fb2b60
LG		 577 WARN_ON_ONCE(!iod->sgt.nents);
578
579 dma_unmap_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req), 0);
9275c206 580
c372cdd1 581 if (iod->nr_allocations == 0)
9275c206
CH		 582 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0],
583 iod->first_dma);
584 else if (iod->use_sgl)
585 nvme_free_sgls(dev, req);
586 else
587 nvme_free_prps(dev, req);
91fb2b60 588 mempool_free(iod->sgt.sgl, dev->iod_mempool);
b4ff9c8d
KB		 589}
590
d0877473
KB		 591static void nvme_print_sgl(struct scatterlist *sgl, int nents)
592{
593 int i;
594 struct scatterlist *sg;
595
596 for_each_sg(sgl, sg, nents, i) {
597 dma_addr_t phys = sg_phys(sg);
598 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
599 "dma_address:%pad dma_length:%d\n",
600 i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
601 sg_dma_len(sg));
602 }
603}
604
a7a7cbe3
CK		 605static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
606 struct request *req, struct nvme_rw_command *cmnd)
ff22b54f 607{
f4800d6d 608 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
99802a7a 609 struct dma_pool *pool;
b131c61d 610 int length = blk_rq_payload_bytes(req);
91fb2b60 611 struct scatterlist *sg = iod->sgt.sgl;
ff22b54f
MW		 612 int dma_len = sg_dma_len(sg);
613 u64 dma_addr = sg_dma_address(sg);
6c3c05b0 614 int offset = dma_addr & (NVME_CTRL_PAGE_SIZE - 1);
e025344c 615 __le64 *prp_list;
a7a7cbe3 616 void **list = nvme_pci_iod_list(req);
e025344c 617 dma_addr_t prp_dma;
eca18b23 618 int nprps, i;
ff22b54f 619
6c3c05b0 620 length -= (NVME_CTRL_PAGE_SIZE - offset);
5228b328
JS		 621 if (length <= 0) {
622 iod->first_dma = 0;
a7a7cbe3 623 goto done;
5228b328 624 }
ff22b54f 625
6c3c05b0 626 dma_len -= (NVME_CTRL_PAGE_SIZE - offset);
ff22b54f 627 if (dma_len) {
6c3c05b0 628 dma_addr += (NVME_CTRL_PAGE_SIZE - offset);
ff22b54f
MW		 629 } else {
630 sg = sg_next(sg);
631 dma_addr = sg_dma_address(sg);
632 dma_len = sg_dma_len(sg);
633 }
634
6c3c05b0 635 if (length <= NVME_CTRL_PAGE_SIZE) {
edd10d33 636 iod->first_dma = dma_addr;
a7a7cbe3 637 goto done;
e025344c
SMM		 638 }
639
6c3c05b0 640 nprps = DIV_ROUND_UP(length, NVME_CTRL_PAGE_SIZE);
99802a7a
MW		 641 if (nprps <= (256 / 8)) {
642 pool = dev->prp_small_pool;
c372cdd1 643 iod->nr_allocations = 0;
99802a7a
MW		 644 } else {
645 pool = dev->prp_page_pool;
c372cdd1 646 iod->nr_allocations = 1;
99802a7a
MW		 647 }
648
69d2b571 649 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
b77954cb 650 if (!prp_list) {
c372cdd1 651 iod->nr_allocations = -1;
86eea289 652 return BLK_STS_RESOURCE;
b77954cb 653 }
eca18b23
MW		 654 list[0] = prp_list;
655 iod->first_dma = prp_dma;
e025344c
SMM		 656 i = 0;
657 for (;;) {
6c3c05b0 658 if (i == NVME_CTRL_PAGE_SIZE >> 3) {
e025344c 659 __le64 *old_prp_list = prp_list;
69d2b571 660 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
eca18b23 661 if (!prp_list)
fa073216 662 goto free_prps;
c372cdd1 663 list[iod->nr_allocations++] = prp_list;
7523d834
MW		 664 prp_list[0] = old_prp_list[i - 1];
665 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
666 i = 1;
e025344c
SMM		 667 }
668 prp_list[i++] = cpu_to_le64(dma_addr);
6c3c05b0
CK		 669 dma_len -= NVME_CTRL_PAGE_SIZE;
670 dma_addr += NVME_CTRL_PAGE_SIZE;
671 length -= NVME_CTRL_PAGE_SIZE;
e025344c
SMM		 672 if (length <= 0)
673 break;
674 if (dma_len > 0)
675 continue;
86eea289
KB		 676 if (unlikely(dma_len < 0))
677 goto bad_sgl;
e025344c
SMM		 678 sg = sg_next(sg);
679 dma_addr = sg_dma_address(sg);
680 dma_len = sg_dma_len(sg);
ff22b54f 681 }
a7a7cbe3 682done:
91fb2b60 683 cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sgt.sgl));
a7a7cbe3 684 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
86eea289 685 return BLK_STS_OK;
fa073216
CH		 686free_prps:
687 nvme_free_prps(dev, req);
688 return BLK_STS_RESOURCE;
689bad_sgl:
91fb2b60 690 WARN(DO_ONCE(nvme_print_sgl, iod->sgt.sgl, iod->sgt.nents),
d0877473 691 "Invalid SGL for payload:%d nents:%d\n",
91fb2b60 692 blk_rq_payload_bytes(req), iod->sgt.nents);
86eea289 693 return BLK_STS_IOERR;
ff22b54f
MW		 694}
695
a7a7cbe3
CK		 696static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
697 struct scatterlist *sg)
698{
699 sge->addr = cpu_to_le64(sg_dma_address(sg));
700 sge->length = cpu_to_le32(sg_dma_len(sg));
701 sge->type = NVME_SGL_FMT_DATA_DESC << 4;
702}
703
704static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
705 dma_addr_t dma_addr, int entries)
706{
707 sge->addr = cpu_to_le64(dma_addr);
708 if (entries < SGES_PER_PAGE) {
709 sge->length = cpu_to_le32(entries * sizeof(*sge));
710 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
711 } else {
84173423 712 sge->length = cpu_to_le32(NVME_CTRL_PAGE_SIZE);
a7a7cbe3
CK		 713 sge->type = NVME_SGL_FMT_SEG_DESC << 4;
714 }
715}
716
717static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
91fb2b60 718 struct request *req, struct nvme_rw_command *cmd)
a7a7cbe3
CK		 719{
720 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3
CK		 721 struct dma_pool *pool;
722 struct nvme_sgl_desc *sg_list;
91fb2b60
LG		 723 struct scatterlist *sg = iod->sgt.sgl;
724 unsigned int entries = iod->sgt.nents;
a7a7cbe3 725 dma_addr_t sgl_dma;
b0f2853b 726 int i = 0;
a7a7cbe3 727
a7a7cbe3
CK		 728 /* setting the transfer type as SGL */
729 cmd->flags = NVME_CMD_SGL_METABUF;
730
b0f2853b 731 if (entries == 1) {
a7a7cbe3
CK		 732 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
733 return BLK_STS_OK;
734 }
735
736 if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
737 pool = dev->prp_small_pool;
c372cdd1 738 iod->nr_allocations = 0;
a7a7cbe3
CK		 739 } else {
740 pool = dev->prp_page_pool;
c372cdd1 741 iod->nr_allocations = 1;
a7a7cbe3
CK		 742 }
743
744 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
745 if (!sg_list) {
c372cdd1 746 iod->nr_allocations = -1;
a7a7cbe3
CK		 747 return BLK_STS_RESOURCE;
748 }
749
750 nvme_pci_iod_list(req)[0] = sg_list;
751 iod->first_dma = sgl_dma;
752
753 nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
754
755 do {
756 if (i == SGES_PER_PAGE) {
757 struct nvme_sgl_desc *old_sg_desc = sg_list;
758 struct nvme_sgl_desc *link = &old_sg_desc[i - 1];
759
760 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
761 if (!sg_list)
fa073216 762 goto free_sgls;
a7a7cbe3
CK		 763
764 i = 0;
c372cdd1 765 nvme_pci_iod_list(req)[iod->nr_allocations++] = sg_list;
a7a7cbe3
CK		 766 sg_list[i++] = *link;
767 nvme_pci_sgl_set_seg(link, sgl_dma, entries);
768 }
769
770 nvme_pci_sgl_set_data(&sg_list[i++], sg);
a7a7cbe3 771 sg = sg_next(sg);
b0f2853b 772 } while (--entries > 0);
a7a7cbe3 773
a7a7cbe3 774 return BLK_STS_OK;
fa073216
CH		 775free_sgls:
776 nvme_free_sgls(dev, req);
777 return BLK_STS_RESOURCE;
a7a7cbe3
CK		 778}
779
dff824b2
CH		 780static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev,
781 struct request *req, struct nvme_rw_command *cmnd,
782 struct bio_vec *bv)
783{
784 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
6c3c05b0
CK		 785 unsigned int offset = bv->bv_offset & (NVME_CTRL_PAGE_SIZE - 1);
786 unsigned int first_prp_len = NVME_CTRL_PAGE_SIZE - offset;
dff824b2
CH		 787
788 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
789 if (dma_mapping_error(dev->dev, iod->first_dma))
790 return BLK_STS_RESOURCE;
791 iod->dma_len = bv->bv_len;
792
793 cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma);
794 if (bv->bv_len > first_prp_len)
795 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len);
a56ea614
LR		 796 else
797 cmnd->dptr.prp2 = 0;
359c1f88 798 return BLK_STS_OK;
dff824b2
CH		 799}
800
29791057
CH		 801static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev,
802 struct request *req, struct nvme_rw_command *cmnd,
803 struct bio_vec *bv)
804{
805 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
806
807 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
808 if (dma_mapping_error(dev->dev, iod->first_dma))
809 return BLK_STS_RESOURCE;
810 iod->dma_len = bv->bv_len;
811
049bf372 812 cmnd->flags = NVME_CMD_SGL_METABUF;
29791057
CH		 813 cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma);
814 cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len);
815 cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4;
359c1f88 816 return BLK_STS_OK;
29791057
CH		 817}
818
fc17b653 819static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
b131c61d 820 struct nvme_command *cmnd)
d29ec824 821{
f4800d6d 822 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
70479b71 823 blk_status_t ret = BLK_STS_RESOURCE;
91fb2b60 824 int rc;
d29ec824 825
dff824b2 826 if (blk_rq_nr_phys_segments(req) == 1) {
a53232cb 827 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
dff824b2
CH		 828 struct bio_vec bv = req_bvec(req);
829
830 if (!is_pci_p2pdma_page(bv.bv_page)) {
6c3c05b0 831 if (bv.bv_offset + bv.bv_len <= NVME_CTRL_PAGE_SIZE * 2)
dff824b2
CH		 832 return nvme_setup_prp_simple(dev, req,
833 &cmnd->rw, &bv);
29791057 834
a53232cb 835 if (nvmeq->qid && sgl_threshold &&
253a0b76 836 nvme_ctrl_sgl_supported(&dev->ctrl))
29791057
CH		 837 return nvme_setup_sgl_simple(dev, req,
838 &cmnd->rw, &bv);
dff824b2
CH		 839 }
840 }
841
842 iod->dma_len = 0;
91fb2b60
LG		 843 iod->sgt.sgl = mempool_alloc(dev->iod_mempool, GFP_ATOMIC);
844 if (!iod->sgt.sgl)
d43f1ccf 845 return BLK_STS_RESOURCE;
91fb2b60
LG		 846 sg_init_table(iod->sgt.sgl, blk_rq_nr_phys_segments(req));
847 iod->sgt.orig_nents = blk_rq_map_sg(req->q, req, iod->sgt.sgl);
848 if (!iod->sgt.orig_nents)
fa073216 849 goto out_free_sg;
d29ec824 850
91fb2b60
LG		 851 rc = dma_map_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req),
852 DMA_ATTR_NO_WARN);
853 if (rc) {
854 if (rc == -EREMOTEIO)
855 ret = BLK_STS_TARGET;
fa073216 856 goto out_free_sg;
91fb2b60 857 }
d29ec824 858
70479b71 859 iod->use_sgl = nvme_pci_use_sgls(dev, req);
955b1b5a 860 if (iod->use_sgl)
91fb2b60 861 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw);
a7a7cbe3
CK		 862 else
863 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
86eea289 864 if (ret != BLK_STS_OK)
fa073216
CH		 865 goto out_unmap_sg;
866 return BLK_STS_OK;
867
868out_unmap_sg:
91fb2b60 869 dma_unmap_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req), 0);
fa073216 870out_free_sg:
91fb2b60 871 mempool_free(iod->sgt.sgl, dev->iod_mempool);
4aedb705
CH		 872 return ret;
873}
3045c0d0 874
4aedb705
CH		 875static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req,
876 struct nvme_command *cmnd)
877{
878 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
00df5cb4 879
4aedb705
CH		 880 iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req),
881 rq_dma_dir(req), 0);
882 if (dma_mapping_error(dev->dev, iod->meta_dma))
883 return BLK_STS_IOERR;
884 cmnd->rw.metadata = cpu_to_le64(iod->meta_dma);
359c1f88 885 return BLK_STS_OK;
00df5cb4
MW		 886}
887
62451a2b 888static blk_status_t nvme_prep_rq(struct nvme_dev *dev, struct request *req)
edd10d33 889{
9b048119 890 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
ebe6d874 891 blk_status_t ret;
e1e5e564 892
52da4f3f 893 iod->aborted = false;
c372cdd1 894 iod->nr_allocations = -1;
91fb2b60 895 iod->sgt.nents = 0;
9b048119 896
62451a2b 897 ret = nvme_setup_cmd(req->q->queuedata, req);
fc17b653 898 if (ret)
f4800d6d 899 return ret;
a4aea562 900
fc17b653 901 if (blk_rq_nr_phys_segments(req)) {
62451a2b 902 ret = nvme_map_data(dev, req, &iod->cmd);
fc17b653 903 if (ret)
9b048119 904 goto out_free_cmd;
fc17b653 905 }
a4aea562 906
4aedb705 907 if (blk_integrity_rq(req)) {
62451a2b 908 ret = nvme_map_metadata(dev, req, &iod->cmd);
4aedb705
CH		 909 if (ret)
910 goto out_unmap_data;
911 }
912
6887fc64 913 nvme_start_request(req);
fc17b653 914 return BLK_STS_OK;
4aedb705
CH		 915out_unmap_data:
916 nvme_unmap_data(dev, req);
f9d03f96
CH		 917out_free_cmd:
918 nvme_cleanup_cmd(req);
ba1ca37e 919 return ret;
b60503ba 920}
e1e5e564 921
62451a2b
JA		 922/*
923 * NOTE: ns is NULL when called on the admin queue.
924 */
925static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
926 const struct blk_mq_queue_data *bd)
927{
928 struct nvme_queue *nvmeq = hctx->driver_data;
929 struct nvme_dev *dev = nvmeq->dev;
930 struct request *req = bd->rq;
931 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
932 blk_status_t ret;
933
934 /*
935 * We should not need to do this, but we're still using this to
936 * ensure we can drain requests on a dying queue.
937 */
938 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
939 return BLK_STS_IOERR;
940
941 if (unlikely(!nvme_check_ready(&dev->ctrl, req, true)))
942 return nvme_fail_nonready_command(&dev->ctrl, req);
943
944 ret = nvme_prep_rq(dev, req);
945 if (unlikely(ret))
946 return ret;
947 spin_lock(&nvmeq->sq_lock);
948 nvme_sq_copy_cmd(nvmeq, &iod->cmd);
949 nvme_write_sq_db(nvmeq, bd->last);
950 spin_unlock(&nvmeq->sq_lock);
951 return BLK_STS_OK;
952}
953
d62cbcf6
JA		 954static void nvme_submit_cmds(struct nvme_queue *nvmeq, struct request **rqlist)
955{
956 spin_lock(&nvmeq->sq_lock);
957 while (!rq_list_empty(*rqlist)) {
958 struct request *req = rq_list_pop(rqlist);
959 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
960
961 nvme_sq_copy_cmd(nvmeq, &iod->cmd);
962 }
963 nvme_write_sq_db(nvmeq, true);
964 spin_unlock(&nvmeq->sq_lock);
965}
966
967static bool nvme_prep_rq_batch(struct nvme_queue *nvmeq, struct request *req)
968{
969 /*
970 * We should not need to do this, but we're still using this to
971 * ensure we can drain requests on a dying queue.
972 */
973 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
974 return false;
975 if (unlikely(!nvme_check_ready(&nvmeq->dev->ctrl, req, true)))
976 return false;
977
978 req->mq_hctx->tags->rqs[req->tag] = req;
979 return nvme_prep_rq(nvmeq->dev, req) == BLK_STS_OK;
980}
981
982static void nvme_queue_rqs(struct request **rqlist)
983{
6bfec799 984 struct request *req, *next, *prev = NULL;
d62cbcf6
JA		 985 struct request *requeue_list = NULL;
986
6bfec799 987 rq_list_for_each_safe(rqlist, req, next) {
d62cbcf6
JA		 988 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
989
990 if (!nvme_prep_rq_batch(nvmeq, req)) {
991 /* detach 'req' and add to remainder list */
6bfec799
KB		 992 rq_list_move(rqlist, &requeue_list, req, prev);
993
994 req = prev;
995 if (!req)
996 continue;
d62cbcf6
JA		 997 }
998
6bfec799 999 if (!next || req->mq_hctx != next->mq_hctx) {
d62cbcf6 1000 /* detach rest of list, and submit */
6bfec799 1001 req->rq_next = NULL;
d62cbcf6 1002 nvme_submit_cmds(nvmeq, rqlist);
6bfec799
KB		 1003 *rqlist = next;
1004 prev = NULL;
1005 } else
1006 prev = req;
1007 }
d62cbcf6
JA		 1008
1009 *rqlist = requeue_list;
1010}
1011
c234a653 1012static __always_inline void nvme_pci_unmap_rq(struct request *req)
eee417b0 1013{
a53232cb
KB		 1014 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
1015 struct nvme_dev *dev = nvmeq->dev;
1016
1017 if (blk_integrity_rq(req)) {
1018 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a4aea562 1019
4aedb705
CH		 1020 dma_unmap_page(dev->dev, iod->meta_dma,
1021 rq_integrity_vec(req)->bv_len, rq_data_dir(req));
a53232cb
KB		 1022 }
1023
b15c592d 1024 if (blk_rq_nr_phys_segments(req))
4aedb705 1025 nvme_unmap_data(dev, req);
c234a653
JA		 1026}
1027
1028static void nvme_pci_complete_rq(struct request *req)
1029{
1030 nvme_pci_unmap_rq(req);
77f02a7a 1031 nvme_complete_rq(req);
b60503ba
MW		 1032}
1033
c234a653
JA		 1034static void nvme_pci_complete_batch(struct io_comp_batch *iob)
1035{
1036 nvme_complete_batch(iob, nvme_pci_unmap_rq);
1037}
1038
d783e0bd 1039/* We read the CQE phase first to check if the rest of the entry is valid */
750dde44 1040static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq)
d783e0bd 1041{
74943d45
KB		 1042 struct nvme_completion *hcqe = &nvmeq->cqes[nvmeq->cq_head];
1043
1044 return (le16_to_cpu(READ_ONCE(hcqe->status)) & 1) == nvmeq->cq_phase;
d783e0bd
MR		 1045}
1046
eb281c82 1047static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
b60503ba 1048{
eb281c82 1049 u16 head = nvmeq->cq_head;
adf68f21 1050
397c699f
KB		 1051 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
1052 nvmeq->dbbuf_cq_ei))
1053 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
eb281c82 1054}
aae239e1 1055
cfa27356
CH		 1056static inline struct blk_mq_tags *nvme_queue_tagset(struct nvme_queue *nvmeq)
1057{
1058 if (!nvmeq->qid)
1059 return nvmeq->dev->admin_tagset.tags[0];
1060 return nvmeq->dev->tagset.tags[nvmeq->qid - 1];
1061}
1062
c234a653
JA		 1063static inline void nvme_handle_cqe(struct nvme_queue *nvmeq,
1064 struct io_comp_batch *iob, u16 idx)
83a12fb7 1065{
74943d45 1066 struct nvme_completion *cqe = &nvmeq->cqes[idx];
62df8016 1067 __u16 command_id = READ_ONCE(cqe->command_id);
83a12fb7 1068 struct request *req;
adf68f21 1069
83a12fb7
SG		 1070 /*
1071 * AEN requests are special as they don't time out and can
1072 * survive any kind of queue freeze and often don't respond to
1073 * aborts. We don't even bother to allocate a struct request
1074 * for them but rather special case them here.
1075 */
62df8016 1076 if (unlikely(nvme_is_aen_req(nvmeq->qid, command_id))) {
83a12fb7
SG		 1077 nvme_complete_async_event(&nvmeq->dev->ctrl,
1078 cqe->status, &cqe->result);
a0fa9647 1079 return;
83a12fb7 1080 }
b60503ba 1081
e7006de6 1082 req = nvme_find_rq(nvme_queue_tagset(nvmeq), command_id);
50b7c243
XT		 1083 if (unlikely(!req)) {
1084 dev_warn(nvmeq->dev->ctrl.device,
1085 "invalid id %d completed on queue %d\n",
62df8016 1086 command_id, le16_to_cpu(cqe->sq_id));
50b7c243
XT		 1087 return;
1088 }
1089
604c01d5 1090 trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail);
c234a653
JA		 1091 if (!nvme_try_complete_req(req, cqe->status, cqe->result) &&
1092 !blk_mq_add_to_batch(req, iob, nvme_req(req)->status,
1093 nvme_pci_complete_batch))
ff029451 1094 nvme_pci_complete_rq(req);
83a12fb7 1095}
b60503ba 1096
5cb525c8
JA		 1097static inline void nvme_update_cq_head(struct nvme_queue *nvmeq)
1098{
a0aac973 1099 u32 tmp = nvmeq->cq_head + 1;
a8de6639
AD		 1100
1101 if (tmp == nvmeq->q_depth) {
5cb525c8 1102 nvmeq->cq_head = 0;
e2a366a4 1103 nvmeq->cq_phase ^= 1;
a8de6639
AD		 1104 } else {
1105 nvmeq->cq_head = tmp;
b60503ba 1106 }
a0fa9647
JA		 1107}
1108
c234a653
JA		 1109static inline int nvme_poll_cq(struct nvme_queue *nvmeq,
1110 struct io_comp_batch *iob)
a0fa9647 1111{
1052b8ac 1112 int found = 0;
b60503ba 1113
1052b8ac 1114 while (nvme_cqe_pending(nvmeq)) {
bf392a5d 1115 found++;
b69e2ef2
KB		 1116 /*
1117 * load-load control dependency between phase and the rest of
1118 * the cqe requires a full read memory barrier
1119 */
1120 dma_rmb();
c234a653 1121 nvme_handle_cqe(nvmeq, iob, nvmeq->cq_head);
5cb525c8 1122 nvme_update_cq_head(nvmeq);
920d13a8 1123 }
eb281c82 1124
324b494c 1125 if (found)
920d13a8 1126 nvme_ring_cq_doorbell(nvmeq);
5cb525c8 1127 return found;
b60503ba
MW		 1128}
1129
1130static irqreturn_t nvme_irq(int irq, void *data)
58ffacb5 1131{
58ffacb5 1132 struct nvme_queue *nvmeq = data;
4f502245 1133 DEFINE_IO_COMP_BATCH(iob);
5cb525c8 1134
4f502245
JA		 1135 if (nvme_poll_cq(nvmeq, &iob)) {
1136 if (!rq_list_empty(iob.req_list))
1137 nvme_pci_complete_batch(&iob);
05fae499 1138 return IRQ_HANDLED;
4f502245 1139 }
05fae499 1140 return IRQ_NONE;
58ffacb5
MW		 1141}
1142
1143static irqreturn_t nvme_irq_check(int irq, void *data)
1144{
1145 struct nvme_queue *nvmeq = data;
4e523547 1146
750dde44 1147 if (nvme_cqe_pending(nvmeq))
d783e0bd
MR		 1148 return IRQ_WAKE_THREAD;
1149 return IRQ_NONE;
58ffacb5
MW		 1150}
1151
0b2a8a9f 1152/*
fa059b85 1153 * Poll for completions for any interrupt driven queue
0b2a8a9f
CH		 1154 * Can be called from any context.
1155 */
fa059b85 1156static void nvme_poll_irqdisable(struct nvme_queue *nvmeq)
a0fa9647 1157{
3a7afd8e 1158 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
a0fa9647 1159
fa059b85 1160 WARN_ON_ONCE(test_bit(NVMEQ_POLLED, &nvmeq->flags));
442e19b7 1161
fa059b85 1162 disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
c234a653 1163 nvme_poll_cq(nvmeq, NULL);
fa059b85 1164 enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
a0fa9647
JA		 1165}
1166
5a72e899 1167static int nvme_poll(struct blk_mq_hw_ctx *hctx, struct io_comp_batch *iob)
dabcefab
JA		 1168{
1169 struct nvme_queue *nvmeq = hctx->driver_data;
dabcefab
JA		 1170 bool found;
1171
1172 if (!nvme_cqe_pending(nvmeq))
1173 return 0;
1174
3a7afd8e 1175 spin_lock(&nvmeq->cq_poll_lock);
c234a653 1176 found = nvme_poll_cq(nvmeq, iob);
3a7afd8e 1177 spin_unlock(&nvmeq->cq_poll_lock);
dabcefab 1178
dabcefab
JA		 1179 return found;
1180}
1181
ad22c355 1182static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
b60503ba 1183{
f866fc42 1184 struct nvme_dev *dev = to_nvme_dev(ctrl);
147b27e4 1185 struct nvme_queue *nvmeq = &dev->queues[0];
f66e2804 1186 struct nvme_command c = { };
b60503ba 1187
a4aea562 1188 c.common.opcode = nvme_admin_async_event;
ad22c355 1189 c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
3233b94c
JA		 1190
1191 spin_lock(&nvmeq->sq_lock);
1192 nvme_sq_copy_cmd(nvmeq, &c);
1193 nvme_write_sq_db(nvmeq, true);
1194 spin_unlock(&nvmeq->sq_lock);
f705f837
CH		 1195}
1196
b60503ba 1197static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
f705f837 1198{
f66e2804 1199 struct nvme_command c = { };
b60503ba 1200
b60503ba
MW		 1201 c.delete_queue.opcode = opcode;
1202 c.delete_queue.qid = cpu_to_le16(id);
1203
1c63dc66 1204 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1205}
1206
b60503ba 1207static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
a8e3e0bb 1208 struct nvme_queue *nvmeq, s16 vector)
b60503ba 1209{
f66e2804 1210 struct nvme_command c = { };
4b04cc6a
JA		 1211 int flags = NVME_QUEUE_PHYS_CONTIG;
1212
7c349dde 1213 if (!test_bit(NVMEQ_POLLED, &nvmeq->flags))
4b04cc6a 1214 flags |= NVME_CQ_IRQ_ENABLED;
b60503ba 1215
d29ec824 1216 /*
16772ae6 1217 * Note: we (ab)use the fact that the prp fields survive if no data
d29ec824
CH		 1218 * is attached to the request.
1219 */
b60503ba
MW		 1220 c.create_cq.opcode = nvme_admin_create_cq;
1221 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1222 c.create_cq.cqid = cpu_to_le16(qid);
1223 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1224 c.create_cq.cq_flags = cpu_to_le16(flags);
7c349dde 1225 c.create_cq.irq_vector = cpu_to_le16(vector);
b60503ba 1226
1c63dc66 1227 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1228}
1229
1230static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1231 struct nvme_queue *nvmeq)
1232{
9abd68ef 1233 struct nvme_ctrl *ctrl = &dev->ctrl;
f66e2804 1234 struct nvme_command c = { };
81c1cd98 1235 int flags = NVME_QUEUE_PHYS_CONTIG;
b60503ba 1236
9abd68ef
JA		 1237 /*
1238 * Some drives have a bug that auto-enables WRRU if MEDIUM isn't
1239 * set. Since URGENT priority is zeroes, it makes all queues
1240 * URGENT.
1241 */
1242 if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ)
1243 flags |= NVME_SQ_PRIO_MEDIUM;
1244
d29ec824 1245 /*
16772ae6 1246 * Note: we (ab)use the fact that the prp fields survive if no data
d29ec824
CH		 1247 * is attached to the request.
1248 */
b60503ba
MW		 1249 c.create_sq.opcode = nvme_admin_create_sq;
1250 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1251 c.create_sq.sqid = cpu_to_le16(qid);
1252 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1253 c.create_sq.sq_flags = cpu_to_le16(flags);
1254 c.create_sq.cqid = cpu_to_le16(qid);
1255
1c63dc66 1256 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1257}
1258
1259static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1260{
1261 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1262}
1263
1264static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1265{
1266 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1267}
1268
de671d61 1269static enum rq_end_io_ret abort_endio(struct request *req, blk_status_t error)
bc5fc7e4 1270{
a53232cb 1271 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
e44ac588 1272
27fa9bc5
CH		 1273 dev_warn(nvmeq->dev->ctrl.device,
1274 "Abort status: 0x%x", nvme_req(req)->status);
e7a2a87d 1275 atomic_inc(&nvmeq->dev->ctrl.abort_limit);
e7a2a87d 1276 blk_mq_free_request(req);
de671d61 1277 return RQ_END_IO_NONE;
bc5fc7e4
MW		 1278}
1279
b2a0eb1a
KB		 1280static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1281{
b2a0eb1a
KB		 1282 /* If true, indicates loss of adapter communication, possibly by a
1283 * NVMe Subsystem reset.
1284 */
1285 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1286
ad70062c
JW		 1287 /* If there is a reset/reinit ongoing, we shouldn't reset again. */
1288 switch (dev->ctrl.state) {
1289 case NVME_CTRL_RESETTING:
ad6a0a52 1290 case NVME_CTRL_CONNECTING:
b2a0eb1a 1291 return false;
ad70062c
JW		 1292 default:
1293 break;
1294 }
b2a0eb1a
KB		 1295
1296 /* We shouldn't reset unless the controller is on fatal error state
1297 * _or_ if we lost the communication with it.
1298 */
1299 if (!(csts & NVME_CSTS_CFS) && !nssro)
1300 return false;
1301
b2a0eb1a
KB		 1302 return true;
1303}
1304
1305static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1306{
1307 /* Read a config register to help see what died. */
1308 u16 pci_status;
1309 int result;
1310
1311 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1312 &pci_status);
1313 if (result == PCIBIOS_SUCCESSFUL)
1314 dev_warn(dev->ctrl.device,
1315 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1316 csts, pci_status);
1317 else
1318 dev_warn(dev->ctrl.device,
1319 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1320 csts, result);
4641a8e6
KB		 1321
1322 if (csts != ~0)
1323 return;
1324
1325 dev_warn(dev->ctrl.device,
1326 "Does your device have a faulty power saving mode enabled?\n");
1327 dev_warn(dev->ctrl.device,
1328 "Try \"nvme_core.default_ps_max_latency_us=0 pcie_aspm=off\" and report a bug\n");
b2a0eb1a
KB		 1329}
1330
9bdb4833 1331static enum blk_eh_timer_return nvme_timeout(struct request *req)
c30341dc 1332{
f4800d6d 1333 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a53232cb 1334 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
c30341dc 1335 struct nvme_dev *dev = nvmeq->dev;
a4aea562 1336 struct request *abort_req;
f66e2804 1337 struct nvme_command cmd = { };
b2a0eb1a
KB		 1338 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1339
651438bb
WX		 1340 /* If PCI error recovery process is happening, we cannot reset or
1341 * the recovery mechanism will surely fail.
1342 */
1343 mb();
1344 if (pci_channel_offline(to_pci_dev(dev->dev)))
1345 return BLK_EH_RESET_TIMER;
1346
b2a0eb1a
KB		 1347 /*
1348 * Reset immediately if the controller is failed
1349 */
1350 if (nvme_should_reset(dev, csts)) {
1351 nvme_warn_reset(dev, csts);
1352 nvme_dev_disable(dev, false);
d86c4d8e 1353 nvme_reset_ctrl(&dev->ctrl);
db8c48e4 1354 return BLK_EH_DONE;
b2a0eb1a 1355 }
c30341dc 1356
7776db1c
KB		 1357 /*
1358 * Did we miss an interrupt?
1359 */
fa059b85 1360 if (test_bit(NVMEQ_POLLED, &nvmeq->flags))
5a72e899 1361 nvme_poll(req->mq_hctx, NULL);
fa059b85
KB		 1362 else
1363 nvme_poll_irqdisable(nvmeq);
1364
1c584208 1365 if (blk_mq_rq_state(req) != MQ_RQ_IN_FLIGHT) {
7776db1c
KB		 1366 dev_warn(dev->ctrl.device,
1367 "I/O %d QID %d timeout, completion polled\n",
1368 req->tag, nvmeq->qid);
db8c48e4 1369 return BLK_EH_DONE;
7776db1c
KB		 1370 }
1371
31c7c7d2 1372 /*
fd634f41
CH		 1373 * Shutdown immediately if controller times out while starting. The
1374 * reset work will see the pci device disabled when it gets the forced
1375 * cancellation error. All outstanding requests are completed on
db8c48e4 1376 * shutdown, so we return BLK_EH_DONE.
fd634f41 1377 */
4244140d
KB		 1378 switch (dev->ctrl.state) {
1379 case NVME_CTRL_CONNECTING:
2036f726 1380 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
df561f66 1381 fallthrough;
2036f726 1382 case NVME_CTRL_DELETING:
b9cac43c 1383 dev_warn_ratelimited(dev->ctrl.device,
fd634f41
CH		 1384 "I/O %d QID %d timeout, disable controller\n",
1385 req->tag, nvmeq->qid);
27fa9bc5 1386 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
7ad92f65 1387 nvme_dev_disable(dev, true);
db8c48e4 1388 return BLK_EH_DONE;
39a9dd81
KB		 1389 case NVME_CTRL_RESETTING:
1390 return BLK_EH_RESET_TIMER;
4244140d
KB		 1391 default:
1392 break;
c30341dc
KB		 1393 }
1394
fd634f41 1395 /*
ee0d96d3
BW		 1396 * Shutdown the controller immediately and schedule a reset if the
1397 * command was already aborted once before and still hasn't been
1398 * returned to the driver, or if this is the admin queue.
31c7c7d2 1399 */
f4800d6d 1400 if (!nvmeq->qid || iod->aborted) {
1b3c47c1 1401 dev_warn(dev->ctrl.device,
e1569a16
KB		 1402 "I/O %d QID %d timeout, reset controller\n",
1403 req->tag, nvmeq->qid);
7ad92f65 1404 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
a5cdb68c 1405 nvme_dev_disable(dev, false);
d86c4d8e 1406 nvme_reset_ctrl(&dev->ctrl);
c30341dc 1407
db8c48e4 1408 return BLK_EH_DONE;
c30341dc 1409 }
c30341dc 1410
e7a2a87d 1411 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
6bf25d16 1412 atomic_inc(&dev->ctrl.abort_limit);
31c7c7d2 1413 return BLK_EH_RESET_TIMER;
6bf25d16 1414 }
52da4f3f 1415 iod->aborted = true;
a4aea562 1416
c30341dc 1417 cmd.abort.opcode = nvme_admin_abort_cmd;
85f74acf 1418 cmd.abort.cid = nvme_cid(req);
c30341dc 1419 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
c30341dc 1420
1b3c47c1 1421 dev_warn(nvmeq->dev->ctrl.device,
86141440
CH		 1422 "I/O %d (%s) QID %d timeout, aborting\n",
1423 req->tag,
1424 nvme_get_opcode_str(nvme_req(req)->cmd->common.opcode),
1425 nvmeq->qid);
e7a2a87d 1426
e559398f
CH		 1427 abort_req = blk_mq_alloc_request(dev->ctrl.admin_q, nvme_req_op(&cmd),
1428 BLK_MQ_REQ_NOWAIT);
e7a2a87d
CH		 1429 if (IS_ERR(abort_req)) {
1430 atomic_inc(&dev->ctrl.abort_limit);
1431 return BLK_EH_RESET_TIMER;
1432 }
e559398f 1433 nvme_init_request(abort_req, &cmd);
e7a2a87d 1434
e2e53086 1435 abort_req->end_io = abort_endio;
e7a2a87d 1436 abort_req->end_io_data = NULL;
e2e53086 1437 blk_execute_rq_nowait(abort_req, false);
c30341dc 1438
31c7c7d2
CH		 1439 /*
1440 * The aborted req will be completed on receiving the abort req.
1441 * We enable the timer again. If hit twice, it'll cause a device reset,
1442 * as the device then is in a faulty state.
1443 */
1444 return BLK_EH_RESET_TIMER;
c30341dc
KB		 1445}
1446
a4aea562
MB		 1447static void nvme_free_queue(struct nvme_queue *nvmeq)
1448{
8a1d09a6 1449 dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq),
9e866774 1450 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
63223078
CH		 1451 if (!nvmeq->sq_cmds)
1452 return;
0f238ff5 1453
63223078 1454 if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) {
88a041f4 1455 pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev),
8a1d09a6 1456 nvmeq->sq_cmds, SQ_SIZE(nvmeq));
63223078 1457 } else {
8a1d09a6 1458 dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq),
63223078 1459 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
0f238ff5 1460 }
9e866774
MW		 1461}
1462
a1a5ef99 1463static void nvme_free_queues(struct nvme_dev *dev, int lowest)
22404274
KB		 1464{
1465 int i;
1466
d858e5f0 1467 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
d858e5f0 1468 dev->ctrl.queue_count--;
147b27e4 1469 nvme_free_queue(&dev->queues[i]);
121c7ad4 1470 }
22404274
KB		 1471}
1472
10981f23 1473static void nvme_suspend_queue(struct nvme_dev *dev, unsigned int qid)
b60503ba 1474{
10981f23
CH		 1475 struct nvme_queue *nvmeq = &dev->queues[qid];
1476
4e224106 1477 if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags))
10981f23 1478 return;
a09115b2 1479
4e224106 1480 /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */
d1f06f4a 1481 mb();
a09115b2 1482
4e224106 1483 nvmeq->dev->online_queues--;
1c63dc66 1484 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
9f27bd70 1485 nvme_quiesce_admin_queue(&nvmeq->dev->ctrl);
7c349dde 1486 if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags))
10981f23 1487 pci_free_irq(to_pci_dev(dev->dev), nvmeq->cq_vector, nvmeq);
4d115420 1488}
b60503ba 1489
8fae268b
KB		 1490static void nvme_suspend_io_queues(struct nvme_dev *dev)
1491{
1492 int i;
1493
1494 for (i = dev->ctrl.queue_count - 1; i > 0; i--)
10981f23 1495 nvme_suspend_queue(dev, i);
b60503ba
MW		 1496}
1497
fa46c6fb
KB		 1498/*
1499 * Called only on a device that has been disabled and after all other threads
9210c075
DZ		 1500 * that can check this device's completion queues have synced, except
1501 * nvme_poll(). This is the last chance for the driver to see a natural
1502 * completion before nvme_cancel_request() terminates all incomplete requests.
fa46c6fb
KB		 1503 */
1504static void nvme_reap_pending_cqes(struct nvme_dev *dev)
1505{
fa46c6fb
KB		 1506 int i;
1507
9210c075
DZ		 1508 for (i = dev->ctrl.queue_count - 1; i > 0; i--) {
1509 spin_lock(&dev->queues[i].cq_poll_lock);
c234a653 1510 nvme_poll_cq(&dev->queues[i], NULL);
9210c075
DZ		 1511 spin_unlock(&dev->queues[i].cq_poll_lock);
1512 }
fa46c6fb
KB		 1513}
1514
8ffaadf7
JD		 1515static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1516 int entry_size)
1517{
1518 int q_depth = dev->q_depth;
5fd4ce1b 1519 unsigned q_size_aligned = roundup(q_depth * entry_size,
6c3c05b0 1520 NVME_CTRL_PAGE_SIZE);
8ffaadf7
JD		 1521
1522 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
c45f5c99 1523 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
4e523547 1524
6c3c05b0 1525 mem_per_q = round_down(mem_per_q, NVME_CTRL_PAGE_SIZE);
c45f5c99 1526 q_depth = div_u64(mem_per_q, entry_size);
8ffaadf7
JD		 1527
1528 /*
1529 * Ensure the reduced q_depth is above some threshold where it
1530 * would be better to map queues in system memory with the
1531 * original depth
1532 */
1533 if (q_depth < 64)
1534 return -ENOMEM;
1535 }
1536
1537 return q_depth;
1538}
1539
1540static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
8a1d09a6 1541 int qid)
8ffaadf7 1542{
0f238ff5
LG		 1543 struct pci_dev *pdev = to_pci_dev(dev->dev);
1544
1545 if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
8a1d09a6 1546 nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq));
bfac8e9f
AM		 1547 if (nvmeq->sq_cmds) {
1548 nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev,
1549 nvmeq->sq_cmds);
1550 if (nvmeq->sq_dma_addr) {
1551 set_bit(NVMEQ_SQ_CMB, &nvmeq->flags);
1552 return 0;
1553 }
1554
8a1d09a6 1555 pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq));
63223078 1556 }
0f238ff5 1557 }
8ffaadf7 1558
8a1d09a6 1559 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq),
63223078 1560 &nvmeq->sq_dma_addr, GFP_KERNEL);
815c6704
KB		 1561 if (!nvmeq->sq_cmds)
1562 return -ENOMEM;
8ffaadf7
JD		 1563 return 0;
1564}
1565
a6ff7262 1566static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
b60503ba 1567{
147b27e4 1568 struct nvme_queue *nvmeq = &dev->queues[qid];
b60503ba 1569
62314e40
KB		 1570 if (dev->ctrl.queue_count > qid)
1571 return 0;
b60503ba 1572
c1e0cc7e 1573 nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES;
8a1d09a6
BH		 1574 nvmeq->q_depth = depth;
1575 nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq),
750afb08 1576 &nvmeq->cq_dma_addr, GFP_KERNEL);
b60503ba
MW		 1577 if (!nvmeq->cqes)
1578 goto free_nvmeq;
b60503ba 1579
8a1d09a6 1580 if (nvme_alloc_sq_cmds(dev, nvmeq, qid))
b60503ba
MW		 1581 goto free_cqdma;
1582
091b6092 1583 nvmeq->dev = dev;
1ab0cd69 1584 spin_lock_init(&nvmeq->sq_lock);
3a7afd8e 1585 spin_lock_init(&nvmeq->cq_poll_lock);
b60503ba 1586 nvmeq->cq_head = 0;
82123460 1587 nvmeq->cq_phase = 1;
b80d5ccc 1588 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
c30341dc 1589 nvmeq->qid = qid;
d858e5f0 1590 dev->ctrl.queue_count++;
36a7e993 1591
147b27e4 1592 return 0;
b60503ba
MW		 1593
1594 free_cqdma:
8a1d09a6
BH		 1595 dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes,
1596 nvmeq->cq_dma_addr);
b60503ba 1597 free_nvmeq:
147b27e4 1598 return -ENOMEM;
b60503ba
MW		 1599}
1600
dca51e78 1601static int queue_request_irq(struct nvme_queue *nvmeq)
3001082c 1602{
0ff199cb
CH		 1603 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1604 int nr = nvmeq->dev->ctrl.instance;
1605
1606 if (use_threaded_interrupts) {
1607 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1608 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1609 } else {
1610 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1611 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1612 }
3001082c
MW		 1613}
1614
22404274 1615static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
b60503ba 1616{
22404274 1617 struct nvme_dev *dev = nvmeq->dev;
b60503ba 1618
22404274 1619 nvmeq->sq_tail = 0;
38210800 1620 nvmeq->last_sq_tail = 0;
22404274
KB		 1621 nvmeq->cq_head = 0;
1622 nvmeq->cq_phase = 1;
b80d5ccc 1623 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
8a1d09a6 1624 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq));
f9f38e33 1625 nvme_dbbuf_init(dev, nvmeq, qid);
42f61420 1626 dev->online_queues++;
3a7afd8e 1627 wmb(); /* ensure the first interrupt sees the initialization */
22404274
KB		 1628}
1629
e4b9852a
CC		 1630/*
1631 * Try getting shutdown_lock while setting up IO queues.
1632 */
1633static int nvme_setup_io_queues_trylock(struct nvme_dev *dev)
1634{
1635 /*
1636 * Give up if the lock is being held by nvme_dev_disable.
1637 */
1638 if (!mutex_trylock(&dev->shutdown_lock))
1639 return -ENODEV;
1640
1641 /*
1642 * Controller is in wrong state, fail early.
1643 */
1644 if (dev->ctrl.state != NVME_CTRL_CONNECTING) {
1645 mutex_unlock(&dev->shutdown_lock);
1646 return -ENODEV;
1647 }
1648
1649 return 0;
1650}
1651
4b04cc6a 1652static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled)
22404274
KB		 1653{
1654 struct nvme_dev *dev = nvmeq->dev;
1655 int result;
7c349dde 1656 u16 vector = 0;
3f85d50b 1657
d1ed6aa1
CH		 1658 clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
1659
22b55601
KB		 1660 /*
1661 * A queue's vector matches the queue identifier unless the controller
1662 * has only one vector available.
1663 */
4b04cc6a
JA		 1664 if (!polled)
1665 vector = dev->num_vecs == 1 ? 0 : qid;
1666 else
7c349dde 1667 set_bit(NVMEQ_POLLED, &nvmeq->flags);
4b04cc6a 1668
a8e3e0bb 1669 result = adapter_alloc_cq(dev, qid, nvmeq, vector);
ded45505
KB		 1670 if (result)
1671 return result;
b60503ba
MW		 1672
1673 result = adapter_alloc_sq(dev, qid, nvmeq);
1674 if (result < 0)
ded45505 1675 return result;
c80b36cd 1676 if (result)
b60503ba
MW		 1677 goto release_cq;
1678
a8e3e0bb 1679 nvmeq->cq_vector = vector;
4b04cc6a 1680
e4b9852a
CC		 1681 result = nvme_setup_io_queues_trylock(dev);
1682 if (result)
1683 return result;
1684 nvme_init_queue(nvmeq, qid);
7c349dde 1685 if (!polled) {
4b04cc6a
JA		 1686 result = queue_request_irq(nvmeq);
1687 if (result < 0)
1688 goto release_sq;
1689 }
b60503ba 1690
4e224106 1691 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
e4b9852a 1692 mutex_unlock(&dev->shutdown_lock);
22404274 1693 return result;
b60503ba 1694
a8e3e0bb 1695release_sq:
f25a2dfc 1696 dev->online_queues--;
e4b9852a 1697 mutex_unlock(&dev->shutdown_lock);
b60503ba 1698 adapter_delete_sq(dev, qid);
a8e3e0bb 1699release_cq:
b60503ba 1700 adapter_delete_cq(dev, qid);
22404274 1701 return result;
b60503ba
MW		 1702}
1703
f363b089 1704static const struct blk_mq_ops nvme_mq_admin_ops = {
d29ec824 1705 .queue_rq = nvme_queue_rq,
77f02a7a 1706 .complete = nvme_pci_complete_rq,
a4aea562 1707 .init_hctx = nvme_admin_init_hctx,
e559398f 1708 .init_request = nvme_pci_init_request,
a4aea562
MB		 1709 .timeout = nvme_timeout,
1710};
1711
f363b089 1712static const struct blk_mq_ops nvme_mq_ops = {
376f7ef8 1713 .queue_rq = nvme_queue_rq,
d62cbcf6 1714 .queue_rqs = nvme_queue_rqs,
376f7ef8
CH		 1715 .complete = nvme_pci_complete_rq,
1716 .commit_rqs = nvme_commit_rqs,
1717 .init_hctx = nvme_init_hctx,
e559398f 1718 .init_request = nvme_pci_init_request,
376f7ef8
CH		 1719 .map_queues = nvme_pci_map_queues,
1720 .timeout = nvme_timeout,
1721 .poll = nvme_poll,
dabcefab
JA		 1722};
1723
ea191d2f
KB		 1724static void nvme_dev_remove_admin(struct nvme_dev *dev)
1725{
1c63dc66 1726 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
69d9a99c
KB		 1727 /*
1728 * If the controller was reset during removal, it's possible
1729 * user requests may be waiting on a stopped queue. Start the
1730 * queue to flush these to completion.
1731 */
9f27bd70 1732 nvme_unquiesce_admin_queue(&dev->ctrl);
0da7feaa 1733 nvme_remove_admin_tag_set(&dev->ctrl);
ea191d2f
KB		 1734 }
1735}
1736
97f6ef64
XY		 1737static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1738{
1739 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1740}
1741
1742static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1743{
1744 struct pci_dev *pdev = to_pci_dev(dev->dev);
1745
1746 if (size <= dev->bar_mapped_size)
1747 return 0;
1748 if (size > pci_resource_len(pdev, 0))
1749 return -ENOMEM;
1750 if (dev->bar)
1751 iounmap(dev->bar);
1752 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1753 if (!dev->bar) {
1754 dev->bar_mapped_size = 0;
1755 return -ENOMEM;
1756 }
1757 dev->bar_mapped_size = size;
1758 dev->dbs = dev->bar + NVME_REG_DBS;
1759
1760 return 0;
1761}
1762
01ad0990 1763static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
b60503ba 1764{
ba47e386 1765 int result;
b60503ba
MW		 1766 u32 aqa;
1767 struct nvme_queue *nvmeq;
1768
97f6ef64
XY		 1769 result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1770 if (result < 0)
1771 return result;
1772
8ef2074d 1773 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
20d0dfe6 1774 NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
dfbac8c7 1775
7a67cbea
CH		 1776 if (dev->subsystem &&
1777 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1778 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
dfbac8c7 1779
285b6e9b
CH		 1780 /*
1781 * If the device has been passed off to us in an enabled state, just
1782 * clear the enabled bit. The spec says we should set the 'shutdown
1783 * notification bits', but doing so may cause the device to complete
1784 * commands to the admin queue ... and we don't know what memory that
1785 * might be pointing at!
1786 */
1787 result = nvme_disable_ctrl(&dev->ctrl, false);
ba47e386
MW		 1788 if (result < 0)
1789 return result;
b60503ba 1790
a6ff7262 1791 result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
147b27e4
SG		 1792 if (result)
1793 return result;
b60503ba 1794
635333e4
MG		 1795 dev->ctrl.numa_node = dev_to_node(dev->dev);
1796
147b27e4 1797 nvmeq = &dev->queues[0];
b60503ba
MW		 1798 aqa = nvmeq->q_depth - 1;
1799 aqa |= aqa << 16;
1800
7a67cbea
CH		 1801 writel(aqa, dev->bar + NVME_REG_AQA);
1802 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1803 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
b60503ba 1804
c0f2f45b 1805 result = nvme_enable_ctrl(&dev->ctrl);
025c557a 1806 if (result)
d4875622 1807 return result;
a4aea562 1808
2b25d981 1809 nvmeq->cq_vector = 0;
161b8be2 1810 nvme_init_queue(nvmeq, 0);
dca51e78 1811 result = queue_request_irq(nvmeq);
758dd7fd 1812 if (result) {
7c349dde 1813 dev->online_queues--;
d4875622 1814 return result;
758dd7fd 1815 }
025c557a 1816
4e224106 1817 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
b60503ba
MW		 1818 return result;
1819}
1820
749941f2 1821static int nvme_create_io_queues(struct nvme_dev *dev)
42f61420 1822{
4b04cc6a 1823 unsigned i, max, rw_queues;
749941f2 1824 int ret = 0;
42f61420 1825
d858e5f0 1826 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
a6ff7262 1827 if (nvme_alloc_queue(dev, i, dev->q_depth)) {
749941f2 1828 ret = -ENOMEM;
42f61420 1829 break;
749941f2
CH		 1830 }
1831 }
42f61420 1832
d858e5f0 1833 max = min(dev->max_qid, dev->ctrl.queue_count - 1);
e20ba6e1
CH		 1834 if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) {
1835 rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] +
1836 dev->io_queues[HCTX_TYPE_READ];
4b04cc6a
JA		 1837 } else {
1838 rw_queues = max;
1839 }
1840
949928c1 1841 for (i = dev->online_queues; i <= max; i++) {
4b04cc6a
JA		 1842 bool polled = i > rw_queues;
1843
1844 ret = nvme_create_queue(&dev->queues[i], i, polled);
d4875622 1845 if (ret)
42f61420 1846 break;
27e8166c 1847 }
749941f2
CH		 1848
1849 /*
1850 * Ignore failing Create SQ/CQ commands, we can continue with less
8adb8c14
MI		 1851 * than the desired amount of queues, and even a controller without
1852 * I/O queues can still be used to issue admin commands. This might
749941f2
CH		 1853 * be useful to upgrade a buggy firmware for example.
1854 */
1855 return ret >= 0 ? 0 : ret;
b60503ba
MW		 1856}
1857
88de4598 1858static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
8ffaadf7 1859{
88de4598
CH		 1860 u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
1861
1862 return 1ULL << (12 + 4 * szu);
1863}
1864
1865static u32 nvme_cmb_size(struct nvme_dev *dev)
1866{
1867 return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
1868}
1869
f65efd6d 1870static void nvme_map_cmb(struct nvme_dev *dev)
8ffaadf7 1871{
88de4598 1872 u64 size, offset;
8ffaadf7
JD		 1873 resource_size_t bar_size;
1874 struct pci_dev *pdev = to_pci_dev(dev->dev);
8969f1f8 1875 int bar;
8ffaadf7 1876
9fe5c59f
KB		 1877 if (dev->cmb_size)
1878 return;
1879
20d3bb92
KJ		 1880 if (NVME_CAP_CMBS(dev->ctrl.cap))
1881 writel(NVME_CMBMSC_CRE, dev->bar + NVME_REG_CMBMSC);
1882
7a67cbea 1883 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
f65efd6d
CH		 1884 if (!dev->cmbsz)
1885 return;
202021c1 1886 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
8ffaadf7 1887
88de4598
CH		 1888 size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
1889 offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
8969f1f8
CH		 1890 bar = NVME_CMB_BIR(dev->cmbloc);
1891 bar_size = pci_resource_len(pdev, bar);
8ffaadf7
JD		 1892
1893 if (offset > bar_size)
f65efd6d 1894 return;
8ffaadf7 1895
20d3bb92
KJ		 1896 /*
1897 * Tell the controller about the host side address mapping the CMB,
1898 * and enable CMB decoding for the NVMe 1.4+ scheme:
1899 */
1900 if (NVME_CAP_CMBS(dev->ctrl.cap)) {
1901 hi_lo_writeq(NVME_CMBMSC_CRE | NVME_CMBMSC_CMSE |
1902 (pci_bus_address(pdev, bar) + offset),
1903 dev->bar + NVME_REG_CMBMSC);
1904 }
1905
8ffaadf7
JD		 1906 /*
1907 * Controllers may support a CMB size larger than their BAR,
1908 * for example, due to being behind a bridge. Reduce the CMB to
1909 * the reported size of the BAR
1910 */
1911 if (size > bar_size - offset)
1912 size = bar_size - offset;
1913
0f238ff5
LG		 1914 if (pci_p2pdma_add_resource(pdev, bar, size, offset)) {
1915 dev_warn(dev->ctrl.device,
1916 "failed to register the CMB\n");
f65efd6d 1917 return;
0f238ff5
LG		 1918 }
1919
8ffaadf7 1920 dev->cmb_size = size;
0f238ff5
LG		 1921 dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS);
1922
1923 if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) ==
1924 (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS))
1925 pci_p2pmem_publish(pdev, true);
8ffaadf7
JD		 1926}
1927
87ad72a5
CH		 1928static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1929{
6c3c05b0 1930 u32 host_mem_size = dev->host_mem_size >> NVME_CTRL_PAGE_SHIFT;
4033f35d 1931 u64 dma_addr = dev->host_mem_descs_dma;
f66e2804 1932 struct nvme_command c = { };
87ad72a5
CH		 1933 int ret;
1934
87ad72a5
CH		 1935 c.features.opcode = nvme_admin_set_features;
1936 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1937 c.features.dword11 = cpu_to_le32(bits);
6c3c05b0 1938 c.features.dword12 = cpu_to_le32(host_mem_size);
87ad72a5
CH		 1939 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr));
1940 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr));
1941 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs);
1942
1943 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1944 if (ret) {
1945 dev_warn(dev->ctrl.device,
1946 "failed to set host mem (err %d, flags %#x).\n",
1947 ret, bits);
a5df5e79
KB		 1948 } else
1949 dev->hmb = bits & NVME_HOST_MEM_ENABLE;
1950
87ad72a5
CH		 1951 return ret;
1952}
1953
1954static void nvme_free_host_mem(struct nvme_dev *dev)
1955{
1956 int i;
1957
1958 for (i = 0; i < dev->nr_host_mem_descs; i++) {
1959 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
6c3c05b0 1960 size_t size = le32_to_cpu(desc->size) * NVME_CTRL_PAGE_SIZE;
87ad72a5 1961
cc667f6d
LD		 1962 dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i],
1963 le64_to_cpu(desc->addr),
1964 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
87ad72a5
CH		 1965 }
1966
1967 kfree(dev->host_mem_desc_bufs);
1968 dev->host_mem_desc_bufs = NULL;
4033f35d
CH		 1969 dma_free_coherent(dev->dev,
1970 dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
1971 dev->host_mem_descs, dev->host_mem_descs_dma);
87ad72a5 1972 dev->host_mem_descs = NULL;
7e5dd57e 1973 dev->nr_host_mem_descs = 0;
87ad72a5
CH		 1974}
1975
92dc6895
CH		 1976static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
1977 u32 chunk_size)
9d713c2b 1978{
87ad72a5 1979 struct nvme_host_mem_buf_desc *descs;
92dc6895 1980 u32 max_entries, len;
4033f35d 1981 dma_addr_t descs_dma;
2ee0e4ed 1982 int i = 0;
87ad72a5 1983 void **bufs;
6fbcde66 1984 u64 size, tmp;
87ad72a5 1985
87ad72a5
CH		 1986 tmp = (preferred + chunk_size - 1);
1987 do_div(tmp, chunk_size);
1988 max_entries = tmp;
044a9df1
CH		 1989
1990 if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
1991 max_entries = dev->ctrl.hmmaxd;
1992
750afb08
LC		 1993 descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs),
1994 &descs_dma, GFP_KERNEL);
87ad72a5
CH		 1995 if (!descs)
1996 goto out;
1997
1998 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
1999 if (!bufs)
2000 goto out_free_descs;
2001
244a8fe4 2002 for (size = 0; size < preferred && i < max_entries; size += len) {
87ad72a5
CH		 2003 dma_addr_t dma_addr;
2004
50cdb7c6 2005 len = min_t(u64, chunk_size, preferred - size);
87ad72a5
CH		 2006 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
2007 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
2008 if (!bufs[i])
2009 break;
2010
2011 descs[i].addr = cpu_to_le64(dma_addr);
6c3c05b0 2012 descs[i].size = cpu_to_le32(len / NVME_CTRL_PAGE_SIZE);
87ad72a5
CH		 2013 i++;
2014 }
2015
92dc6895 2016 if (!size)
87ad72a5 2017 goto out_free_bufs;
87ad72a5 2018
87ad72a5
CH		 2019 dev->nr_host_mem_descs = i;
2020 dev->host_mem_size = size;
2021 dev->host_mem_descs = descs;
4033f35d 2022 dev->host_mem_descs_dma = descs_dma;
87ad72a5
CH		 2023 dev->host_mem_desc_bufs = bufs;
2024 return 0;
2025
2026out_free_bufs:
2027 while (--i >= 0) {
6c3c05b0 2028 size_t size = le32_to_cpu(descs[i].size) * NVME_CTRL_PAGE_SIZE;
87ad72a5 2029
cc667f6d
LD		 2030 dma_free_attrs(dev->dev, size, bufs[i],
2031 le64_to_cpu(descs[i].addr),
2032 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
87ad72a5
CH		 2033 }
2034
2035 kfree(bufs);
2036out_free_descs:
4033f35d
CH		 2037 dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
2038 descs_dma);
87ad72a5 2039out:
87ad72a5
CH		 2040 dev->host_mem_descs = NULL;
2041 return -ENOMEM;
2042}
2043
92dc6895
CH		 2044static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
2045{
9dc54a0d
CK		 2046 u64 min_chunk = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
2047 u64 hmminds = max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
2048 u64 chunk_size;
92dc6895
CH		 2049
2050 /* start big and work our way down */
9dc54a0d 2051 for (chunk_size = min_chunk; chunk_size >= hmminds; chunk_size /= 2) {
92dc6895
CH		 2052 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
2053 if (!min || dev->host_mem_size >= min)
2054 return 0;
2055 nvme_free_host_mem(dev);
2056 }
2057 }
2058
2059 return -ENOMEM;
2060}
2061
9620cfba 2062static int nvme_setup_host_mem(struct nvme_dev *dev)
87ad72a5
CH		 2063{
2064 u64 max = (u64)max_host_mem_size_mb * SZ_1M;
2065 u64 preferred = (u64)dev->ctrl.hmpre * 4096;
2066 u64 min = (u64)dev->ctrl.hmmin * 4096;
2067 u32 enable_bits = NVME_HOST_MEM_ENABLE;
6fbcde66 2068 int ret;
87ad72a5 2069
acb71e53
CH		 2070 if (!dev->ctrl.hmpre)
2071 return 0;
2072
87ad72a5
CH		 2073 preferred = min(preferred, max);
2074 if (min > max) {
2075 dev_warn(dev->ctrl.device,
2076 "min host memory (%lld MiB) above limit (%d MiB).\n",
2077 min >> ilog2(SZ_1M), max_host_mem_size_mb);
2078 nvme_free_host_mem(dev);
9620cfba 2079 return 0;
87ad72a5
CH		 2080 }
2081
2082 /*
2083 * If we already have a buffer allocated check if we can reuse it.
2084 */
2085 if (dev->host_mem_descs) {
2086 if (dev->host_mem_size >= min)
2087 enable_bits |= NVME_HOST_MEM_RETURN;
2088 else
2089 nvme_free_host_mem(dev);
2090 }
2091
2092 if (!dev->host_mem_descs) {
92dc6895
CH		 2093 if (nvme_alloc_host_mem(dev, min, preferred)) {
2094 dev_warn(dev->ctrl.device,
2095 "failed to allocate host memory buffer.\n");
9620cfba 2096 return 0; /* controller must work without HMB */
92dc6895
CH		 2097 }
2098
2099 dev_info(dev->ctrl.device,
2100 "allocated %lld MiB host memory buffer.\n",
2101 dev->host_mem_size >> ilog2(SZ_1M));
87ad72a5
CH		 2102 }
2103
9620cfba
CH		 2104 ret = nvme_set_host_mem(dev, enable_bits);
2105 if (ret)
87ad72a5 2106 nvme_free_host_mem(dev);
9620cfba 2107 return ret;
9d713c2b
KB		 2108}
2109
0521905e
KB		 2110static ssize_t cmb_show(struct device *dev, struct device_attribute *attr,
2111 char *buf)
2112{
2113 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2114
2115 return sysfs_emit(buf, "cmbloc : x%08x\ncmbsz : x%08x\n",
2116 ndev->cmbloc, ndev->cmbsz);
2117}
2118static DEVICE_ATTR_RO(cmb);
2119
1751e97a
KB		 2120static ssize_t cmbloc_show(struct device *dev, struct device_attribute *attr,
2121 char *buf)
2122{
2123 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2124
2125 return sysfs_emit(buf, "%u\n", ndev->cmbloc);
2126}
2127static DEVICE_ATTR_RO(cmbloc);
2128
2129static ssize_t cmbsz_show(struct device *dev, struct device_attribute *attr,
2130 char *buf)
2131{
2132 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2133
2134 return sysfs_emit(buf, "%u\n", ndev->cmbsz);
2135}
2136static DEVICE_ATTR_RO(cmbsz);
2137
a5df5e79
KB		 2138static ssize_t hmb_show(struct device *dev, struct device_attribute *attr,
2139 char *buf)
2140{
2141 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2142
2143 return sysfs_emit(buf, "%d\n", ndev->hmb);
2144}
2145
2146static ssize_t hmb_store(struct device *dev, struct device_attribute *attr,
2147 const char *buf, size_t count)
2148{
2149 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2150 bool new;
2151 int ret;
2152
99722c8a 2153 if (kstrtobool(buf, &new) < 0)
a5df5e79
KB		 2154 return -EINVAL;
2155
2156 if (new == ndev->hmb)
2157 return count;
2158
2159 if (new) {
2160 ret = nvme_setup_host_mem(ndev);
2161 } else {
2162 ret = nvme_set_host_mem(ndev, 0);
2163 if (!ret)
2164 nvme_free_host_mem(ndev);
2165 }
2166
2167 if (ret < 0)
2168 return ret;
2169
2170 return count;
2171}
2172static DEVICE_ATTR_RW(hmb);
2173
0521905e
KB		 2174static umode_t nvme_pci_attrs_are_visible(struct kobject *kobj,
2175 struct attribute *a, int n)
2176{
2177 struct nvme_ctrl *ctrl =
2178 dev_get_drvdata(container_of(kobj, struct device, kobj));
2179 struct nvme_dev *dev = to_nvme_dev(ctrl);
2180
1751e97a
KB		 2181 if (a == &dev_attr_cmb.attr ||
2182 a == &dev_attr_cmbloc.attr ||
2183 a == &dev_attr_cmbsz.attr) {
2184 if (!dev->cmbsz)
2185 return 0;
2186 }
a5df5e79
KB		 2187 if (a == &dev_attr_hmb.attr && !ctrl->hmpre)
2188 return 0;
2189
0521905e
KB		 2190 return a->mode;
2191}
2192
2193static struct attribute *nvme_pci_attrs[] = {
2194 &dev_attr_cmb.attr,
1751e97a
KB		 2195 &dev_attr_cmbloc.attr,
2196 &dev_attr_cmbsz.attr,
a5df5e79 2197 &dev_attr_hmb.attr,
0521905e
KB		 2198 NULL,
2199};
2200
86adbf0c 2201static const struct attribute_group nvme_pci_dev_attrs_group = {
0521905e
KB		 2202 .attrs = nvme_pci_attrs,
2203 .is_visible = nvme_pci_attrs_are_visible,
2204};
2205
86adbf0c
CH		 2206static const struct attribute_group *nvme_pci_dev_attr_groups[] = {
2207 &nvme_dev_attrs_group,
2208 &nvme_pci_dev_attrs_group,
2209 NULL,
2210};
2211
612b7286
ML		 2212/*
2213 * nirqs is the number of interrupts available for write and read
2214 * queues. The core already reserved an interrupt for the admin queue.
2215 */
2216static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs)
3b6592f7 2217{
612b7286 2218 struct nvme_dev *dev = affd->priv;
2a5bcfdd 2219 unsigned int nr_read_queues, nr_write_queues = dev->nr_write_queues;
3b6592f7
JA		 2220
2221 /*
ee0d96d3 2222 * If there is no interrupt available for queues, ensure that
612b7286
ML		 2223 * the default queue is set to 1. The affinity set size is
2224 * also set to one, but the irq core ignores it for this case.
2225 *
2226 * If only one interrupt is available or 'write_queue' == 0, combine
2227 * write and read queues.
2228 *
2229 * If 'write_queues' > 0, ensure it leaves room for at least one read
2230 * queue.
3b6592f7 2231 */
612b7286
ML		 2232 if (!nrirqs) {
2233 nrirqs = 1;
2234 nr_read_queues = 0;
2a5bcfdd 2235 } else if (nrirqs == 1 || !nr_write_queues) {
612b7286 2236 nr_read_queues = 0;
2a5bcfdd 2237 } else if (nr_write_queues >= nrirqs) {
612b7286 2238 nr_read_queues = 1;
3b6592f7 2239 } else {
2a5bcfdd 2240 nr_read_queues = nrirqs - nr_write_queues;
3b6592f7 2241 }
612b7286
ML		 2242
2243 dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2244 affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2245 dev->io_queues[HCTX_TYPE_READ] = nr_read_queues;
2246 affd->set_size[HCTX_TYPE_READ] = nr_read_queues;
2247 affd->nr_sets = nr_read_queues ? 2 : 1;
3b6592f7
JA		 2248}
2249
6451fe73 2250static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues)
3b6592f7
JA		 2251{
2252 struct pci_dev *pdev = to_pci_dev(dev->dev);
3b6592f7 2253 struct irq_affinity affd = {
9cfef55b 2254 .pre_vectors = 1,
612b7286
ML		 2255 .calc_sets = nvme_calc_irq_sets,
2256 .priv = dev,
3b6592f7 2257 };
21cc2f3f 2258 unsigned int irq_queues, poll_queues;
6451fe73
JA		 2259
2260 /*
21cc2f3f
JX		 2261 * Poll queues don't need interrupts, but we need at least one I/O queue
2262 * left over for non-polled I/O.
6451fe73 2263 */
21cc2f3f
JX		 2264 poll_queues = min(dev->nr_poll_queues, nr_io_queues - 1);
2265 dev->io_queues[HCTX_TYPE_POLL] = poll_queues;
3b6592f7 2266
21cc2f3f
JX		 2267 /*
2268 * Initialize for the single interrupt case, will be updated in
2269 * nvme_calc_irq_sets().
2270 */
612b7286
ML		 2271 dev->io_queues[HCTX_TYPE_DEFAULT] = 1;
2272 dev->io_queues[HCTX_TYPE_READ] = 0;
3b6592f7 2273
66341331 2274 /*
21cc2f3f
JX		 2275 * We need interrupts for the admin queue and each non-polled I/O queue,
2276 * but some Apple controllers require all queues to use the first
2277 * vector.
66341331 2278 */
21cc2f3f
JX		 2279 irq_queues = 1;
2280 if (!(dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR))
2281 irq_queues += (nr_io_queues - poll_queues);
612b7286
ML		 2282 return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues,
2283 PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd);
3b6592f7
JA		 2284}
2285
2a5bcfdd
WZ		 2286static unsigned int nvme_max_io_queues(struct nvme_dev *dev)
2287{
e3aef095
NS		 2288 /*
2289 * If tags are shared with admin queue (Apple bug), then
2290 * make sure we only use one IO queue.
2291 */
2292 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2293 return 1;
2a5bcfdd
WZ		 2294 return num_possible_cpus() + dev->nr_write_queues + dev->nr_poll_queues;
2295}
2296
8d85fce7 2297static int nvme_setup_io_queues(struct nvme_dev *dev)
b60503ba 2298{
147b27e4 2299 struct nvme_queue *adminq = &dev->queues[0];
e75ec752 2300 struct pci_dev *pdev = to_pci_dev(dev->dev);
2a5bcfdd 2301 unsigned int nr_io_queues;
97f6ef64 2302 unsigned long size;
2a5bcfdd 2303 int result;
b60503ba 2304
2a5bcfdd
WZ		 2305 /*
2306 * Sample the module parameters once at reset time so that we have
2307 * stable values to work with.
2308 */
2309 dev->nr_write_queues = write_queues;
2310 dev->nr_poll_queues = poll_queues;
d38e9f04 2311
e3aef095 2312 nr_io_queues = dev->nr_allocated_queues - 1;
9a0be7ab
CH		 2313 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
2314 if (result < 0)
1b23484b 2315 return result;
9a0be7ab 2316
f5fa90dc 2317 if (nr_io_queues == 0)
a5229050 2318 return 0;
53dc180e 2319
e4b9852a
CC		 2320 /*
2321 * Free IRQ resources as soon as NVMEQ_ENABLED bit transitions
2322 * from set to unset. If there is a window to it is truely freed,
2323 * pci_free_irq_vectors() jumping into this window will crash.
2324 * And take lock to avoid racing with pci_free_irq_vectors() in
2325 * nvme_dev_disable() path.
2326 */
2327 result = nvme_setup_io_queues_trylock(dev);
2328 if (result)
2329 return result;
2330 if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags))
2331 pci_free_irq(pdev, 0, adminq);
b60503ba 2332
0f238ff5 2333 if (dev->cmb_use_sqes) {
8ffaadf7
JD		 2334 result = nvme_cmb_qdepth(dev, nr_io_queues,
2335 sizeof(struct nvme_command));
88d356ca 2336 if (result > 0) {
8ffaadf7 2337 dev->q_depth = result;
88d356ca
CH		 2338 dev->ctrl.sqsize = result - 1;
2339 } else {
0f238ff5 2340 dev->cmb_use_sqes = false;
88d356ca 2341 }
8ffaadf7
JD		 2342 }
2343
97f6ef64
XY		 2344 do {
2345 size = db_bar_size(dev, nr_io_queues);
2346 result = nvme_remap_bar(dev, size);
2347 if (!result)
2348 break;
e4b9852a
CC		 2349 if (!--nr_io_queues) {
2350 result = -ENOMEM;
2351 goto out_unlock;
2352 }
97f6ef64
XY		 2353 } while (1);
2354 adminq->q_db = dev->dbs;
f1938f6e 2355
8fae268b 2356 retry:
9d713c2b 2357 /* Deregister the admin queue's interrupt */
e4b9852a
CC		 2358 if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags))
2359 pci_free_irq(pdev, 0, adminq);
9d713c2b 2360
e32efbfc
JA		 2361 /*
2362 * If we enable msix early due to not intx, disable it again before
2363 * setting up the full range we need.
2364 */
dca51e78 2365 pci_free_irq_vectors(pdev);
3b6592f7
JA		 2366
2367 result = nvme_setup_irqs(dev, nr_io_queues);
e4b9852a
CC		 2368 if (result <= 0) {
2369 result = -EIO;
2370 goto out_unlock;
2371 }
3b6592f7 2372
22b55601 2373 dev->num_vecs = result;
4b04cc6a 2374 result = max(result - 1, 1);
e20ba6e1 2375 dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL];
fa08a396 2376
063a8096
MW		 2377 /*
2378 * Should investigate if there's a performance win from allocating
2379 * more queues than interrupt vectors; it might allow the submission
2380 * path to scale better, even if the receive path is limited by the
2381 * number of interrupts.
2382 */
dca51e78 2383 result = queue_request_irq(adminq);
7c349dde 2384 if (result)
e4b9852a 2385 goto out_unlock;
4e224106 2386 set_bit(NVMEQ_ENABLED, &adminq->flags);
e4b9852a 2387 mutex_unlock(&dev->shutdown_lock);
8fae268b
KB		 2388
2389 result = nvme_create_io_queues(dev);
2390 if (result || dev->online_queues < 2)
2391 return result;
2392
2393 if (dev->online_queues - 1 < dev->max_qid) {
2394 nr_io_queues = dev->online_queues - 1;
7d879c90 2395 nvme_delete_io_queues(dev);
e4b9852a
CC		 2396 result = nvme_setup_io_queues_trylock(dev);
2397 if (result)
2398 return result;
8fae268b
KB		 2399 nvme_suspend_io_queues(dev);
2400 goto retry;
2401 }
2402 dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n",
2403 dev->io_queues[HCTX_TYPE_DEFAULT],
2404 dev->io_queues[HCTX_TYPE_READ],
2405 dev->io_queues[HCTX_TYPE_POLL]);
2406 return 0;
e4b9852a
CC		 2407out_unlock:
2408 mutex_unlock(&dev->shutdown_lock);
2409 return result;
b60503ba
MW		 2410}
2411
de671d61
JA		 2412static enum rq_end_io_ret nvme_del_queue_end(struct request *req,
2413 blk_status_t error)
a5768aa8 2414{
db3cbfff 2415 struct nvme_queue *nvmeq = req->end_io_data;
b5875222 2416
db3cbfff 2417 blk_mq_free_request(req);
d1ed6aa1 2418 complete(&nvmeq->delete_done);
de671d61 2419 return RQ_END_IO_NONE;
a5768aa8
KB		 2420}
2421
de671d61
JA		 2422static enum rq_end_io_ret nvme_del_cq_end(struct request *req,
2423 blk_status_t error)
a5768aa8 2424{
db3cbfff 2425 struct nvme_queue *nvmeq = req->end_io_data;
a5768aa8 2426
d1ed6aa1
CH		 2427 if (error)
2428 set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
db3cbfff 2429
de671d61 2430 return nvme_del_queue_end(req, error);
a5768aa8
KB		 2431}
2432
db3cbfff 2433static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
bda4e0fb 2434{
db3cbfff
KB		 2435 struct request_queue *q = nvmeq->dev->ctrl.admin_q;
2436 struct request *req;
f66e2804 2437 struct nvme_command cmd = { };
bda4e0fb 2438
db3cbfff
KB		 2439 cmd.delete_queue.opcode = opcode;
2440 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
bda4e0fb 2441
e559398f 2442 req = blk_mq_alloc_request(q, nvme_req_op(&cmd), BLK_MQ_REQ_NOWAIT);
db3cbfff
KB		 2443 if (IS_ERR(req))
2444 return PTR_ERR(req);
e559398f 2445 nvme_init_request(req, &cmd);
bda4e0fb 2446
e2e53086
CH		 2447 if (opcode == nvme_admin_delete_cq)
2448 req->end_io = nvme_del_cq_end;
2449 else
2450 req->end_io = nvme_del_queue_end;
db3cbfff
KB		 2451 req->end_io_data = nvmeq;
2452
d1ed6aa1 2453 init_completion(&nvmeq->delete_done);
e2e53086 2454 blk_execute_rq_nowait(req, false);
db3cbfff 2455 return 0;
bda4e0fb
KB		 2456}
2457
7d879c90 2458static bool __nvme_delete_io_queues(struct nvme_dev *dev, u8 opcode)
a5768aa8 2459{
5271edd4 2460 int nr_queues = dev->online_queues - 1, sent = 0;
db3cbfff 2461 unsigned long timeout;
a5768aa8 2462
db3cbfff 2463 retry:
dc96f938 2464 timeout = NVME_ADMIN_TIMEOUT;
5271edd4
CH		 2465 while (nr_queues > 0) {
2466 if (nvme_delete_queue(&dev->queues[nr_queues], opcode))
2467 break;
2468 nr_queues--;
2469 sent++;
db3cbfff 2470 }
d1ed6aa1
CH		 2471 while (sent) {
2472 struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent];
2473
2474 timeout = wait_for_completion_io_timeout(&nvmeq->delete_done,
5271edd4
CH		 2475 timeout);
2476 if (timeout == 0)
2477 return false;
d1ed6aa1 2478
d1ed6aa1 2479 sent--;
5271edd4
CH		 2480 if (nr_queues)
2481 goto retry;
2482 }
2483 return true;
a5768aa8
KB		 2484}
2485
7d879c90 2486static void nvme_delete_io_queues(struct nvme_dev *dev)
b60503ba 2487{
7d879c90
CH		 2488 if (__nvme_delete_io_queues(dev, nvme_admin_delete_sq))
2489 __nvme_delete_io_queues(dev, nvme_admin_delete_cq);
2490}
2b1b7e78 2491
0da7feaa 2492static unsigned int nvme_pci_nr_maps(struct nvme_dev *dev)
b60503ba 2493{
2455a4b7 2494 if (dev->io_queues[HCTX_TYPE_POLL])
0da7feaa
CH		 2495 return 3;
2496 if (dev->io_queues[HCTX_TYPE_READ])
2497 return 2;
2498 return 1;
2455a4b7 2499}
949928c1 2500
2455a4b7
CH		 2501static void nvme_pci_update_nr_queues(struct nvme_dev *dev)
2502{
2503 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2504 /* free previously allocated queues that are no longer usable */
2505 nvme_free_queues(dev, dev->online_queues);
b60503ba
MW		 2506}
2507
b00a726a 2508static int nvme_pci_enable(struct nvme_dev *dev)
0877cb0d 2509{
b00a726a 2510 int result = -ENOMEM;
e75ec752 2511 struct pci_dev *pdev = to_pci_dev(dev->dev);
0877cb0d
KB		 2512
2513 if (pci_enable_device_mem(pdev))
2514 return result;
2515
0877cb0d 2516 pci_set_master(pdev);
0877cb0d 2517
7a67cbea 2518 if (readl(dev->bar + NVME_REG_CSTS) == -1) {
0e53d180 2519 result = -ENODEV;
b00a726a 2520 goto disable;
0e53d180 2521 }
e32efbfc
JA		 2522
2523 /*
a5229050
KB		 2524 * Some devices and/or platforms don't advertise or work with INTx
2525 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2526 * adjust this later.
e32efbfc 2527 */
dca51e78
CH		 2528 result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
2529 if (result < 0)
09113abf 2530 goto disable;
e32efbfc 2531
20d0dfe6 2532 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
7a67cbea 2533
7442ddce 2534 dev->q_depth = min_t(u32, NVME_CAP_MQES(dev->ctrl.cap) + 1,
b27c1e68 2535 io_queue_depth);
20d0dfe6 2536 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
7a67cbea 2537 dev->dbs = dev->bar + 4096;
1f390c1f 2538
66341331
BH		 2539 /*
2540 * Some Apple controllers require a non-standard SQE size.
2541 * Interestingly they also seem to ignore the CC:IOSQES register
2542 * so we don't bother updating it here.
2543 */
2544 if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES)
2545 dev->io_sqes = 7;
2546 else
2547 dev->io_sqes = NVME_NVM_IOSQES;
1f390c1f
SG		 2548
2549 /*
2550 * Temporary fix for the Apple controller found in the MacBook8,1 and
2551 * some MacBook7,1 to avoid controller resets and data loss.
2552 */
2553 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
2554 dev->q_depth = 2;
9bdcfb10
CH		 2555 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
2556 "set queue depth=%u to work around controller resets\n",
1f390c1f 2557 dev->q_depth);
d554b5e1
MP		 2558 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2559 (pdev->device == 0xa821 || pdev->device == 0xa822) &&
20d0dfe6 2560 NVME_CAP_MQES(dev->ctrl.cap) == 0) {
d554b5e1
MP		 2561 dev->q_depth = 64;
2562 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2563 "set queue depth=%u\n", dev->q_depth);
1f390c1f
SG		 2564 }
2565
d38e9f04
BH		 2566 /*
2567 * Controllers with the shared tags quirk need the IO queue to be
2568 * big enough so that we get 32 tags for the admin queue
2569 */
2570 if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) &&
2571 (dev->q_depth < (NVME_AQ_DEPTH + 2))) {
2572 dev->q_depth = NVME_AQ_DEPTH + 2;
2573 dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n",
2574 dev->q_depth);
2575 }
88d356ca 2576 dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */
d38e9f04 2577
f65efd6d 2578 nvme_map_cmb(dev);
202021c1 2579
a0a3408e
KB		 2580 pci_enable_pcie_error_reporting(pdev);
2581 pci_save_state(pdev);
a6ee7f19 2582
09113abf
TZ		 2583 result = nvme_pci_configure_admin_queue(dev);
2584 if (result)
2585 goto free_irq;
2586 return result;
0877cb0d 2587
09113abf
TZ		 2588 free_irq:
2589 pci_free_irq_vectors(pdev);
0877cb0d 2590 disable:
0877cb0d
KB		 2591 pci_disable_device(pdev);
2592 return result;
2593}
2594
2595static void nvme_dev_unmap(struct nvme_dev *dev)
b00a726a
KB		 2596{
2597 if (dev->bar)
2598 iounmap(dev->bar);
a1f447b3 2599 pci_release_mem_regions(to_pci_dev(dev->dev));
b00a726a
KB		 2600}
2601
68e81eba 2602static bool nvme_pci_ctrl_is_dead(struct nvme_dev *dev)
0877cb0d 2603{
e75ec752 2604 struct pci_dev *pdev = to_pci_dev(dev->dev);
68e81eba 2605 u32 csts;
e75ec752 2606
68e81eba
CH		 2607 if (!pci_is_enabled(pdev) || !pci_device_is_present(pdev))
2608 return true;
2609 if (pdev->error_state != pci_channel_io_normal)
2610 return true;
0877cb0d 2611
68e81eba
CH		 2612 csts = readl(dev->bar + NVME_REG_CSTS);
2613 return (csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY);
4d115420
KB		 2614}
2615
a5cdb68c 2616static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
b60503ba 2617{
302ad8cc 2618 struct pci_dev *pdev = to_pci_dev(dev->dev);
68e81eba 2619 bool dead;
22404274 2620
77bf25ea 2621 mutex_lock(&dev->shutdown_lock);
68e81eba
CH		 2622 dead = nvme_pci_ctrl_is_dead(dev);
2623 if (dev->ctrl.state == NVME_CTRL_LIVE ||
2624 dev->ctrl.state == NVME_CTRL_RESETTING) {
2625 if (pci_is_enabled(pdev))
302ad8cc 2626 nvme_start_freeze(&dev->ctrl);
68e81eba
CH		 2627 /*
2628 * Give the controller a chance to complete all entered requests
2629 * if doing a safe shutdown.
2630 */
2631 if (!dead && shutdown)
2632 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
c9d3bf88 2633 }
c21377f8 2634
9f27bd70 2635 nvme_quiesce_io_queues(&dev->ctrl);
87ad72a5 2636
64ee0ac0 2637 if (!dead && dev->ctrl.queue_count > 0) {
7d879c90 2638 nvme_delete_io_queues(dev);
47d42d22
CH		 2639 nvme_disable_ctrl(&dev->ctrl, shutdown);
2640 nvme_poll_irqdisable(&dev->queues[0]);
4d115420 2641 }
8fae268b 2642 nvme_suspend_io_queues(dev);
10981f23 2643 nvme_suspend_queue(dev, 0);
c80767f7
CH		 2644 pci_free_irq_vectors(pdev);
2645 if (pci_is_enabled(pdev)) {
2646 pci_disable_pcie_error_reporting(pdev);
2647 pci_disable_device(pdev);
2648 }
fa46c6fb 2649 nvme_reap_pending_cqes(dev);
07836e65 2650
1fcfca78
GL		 2651 nvme_cancel_tagset(&dev->ctrl);
2652 nvme_cancel_admin_tagset(&dev->ctrl);
302ad8cc
KB		 2653
2654 /*
2655 * The driver will not be starting up queues again if shutting down so
2656 * must flush all entered requests to their failed completion to avoid
2657 * deadlocking blk-mq hot-cpu notifier.
2658 */
c8e9e9b7 2659 if (shutdown) {
9f27bd70 2660 nvme_unquiesce_io_queues(&dev->ctrl);
c8e9e9b7 2661 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q))
9f27bd70 2662 nvme_unquiesce_admin_queue(&dev->ctrl);
c8e9e9b7 2663 }
77bf25ea 2664 mutex_unlock(&dev->shutdown_lock);
b60503ba
MW		 2665}
2666
c1ac9a4b
KB		 2667static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown)
2668{
2669 if (!nvme_wait_reset(&dev->ctrl))
2670 return -EBUSY;
2671 nvme_dev_disable(dev, shutdown);
2672 return 0;
2673}
2674
091b6092
MW		 2675static int nvme_setup_prp_pools(struct nvme_dev *dev)
2676{
e75ec752 2677 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
c61b82c7
CH		 2678 NVME_CTRL_PAGE_SIZE,
2679 NVME_CTRL_PAGE_SIZE, 0);
091b6092
MW		 2680 if (!dev->prp_page_pool)
2681 return -ENOMEM;
2682
99802a7a 2683 /* Optimisation for I/Os between 4k and 128k */
e75ec752 2684 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
99802a7a
MW		 2685 256, 256, 0);
2686 if (!dev->prp_small_pool) {
2687 dma_pool_destroy(dev->prp_page_pool);
2688 return -ENOMEM;
2689 }
091b6092
MW		 2690 return 0;
2691}
2692
2693static void nvme_release_prp_pools(struct nvme_dev *dev)
2694{
2695 dma_pool_destroy(dev->prp_page_pool);
99802a7a 2696 dma_pool_destroy(dev->prp_small_pool);
091b6092
MW		 2697}
2698
081a7d95
CH		 2699static int nvme_pci_alloc_iod_mempool(struct nvme_dev *dev)
2700{
2701 size_t npages = max(nvme_pci_npages_prp(), nvme_pci_npages_sgl());
2702 size_t alloc_size = sizeof(__le64 *) * npages +
2703 sizeof(struct scatterlist) * NVME_MAX_SEGS;
2704
2705 WARN_ON_ONCE(alloc_size > PAGE_SIZE);
2706 dev->iod_mempool = mempool_create_node(1,
2707 mempool_kmalloc, mempool_kfree,
2708 (void *)alloc_size, GFP_KERNEL,
2709 dev_to_node(dev->dev));
2710 if (!dev->iod_mempool)
2711 return -ENOMEM;
2712 return 0;
2713}
2714
770597ec
KB		 2715static void nvme_free_tagset(struct nvme_dev *dev)
2716{
2717 if (dev->tagset.tags)
0da7feaa 2718 nvme_remove_io_tag_set(&dev->ctrl);
770597ec
KB		 2719 dev->ctrl.tagset = NULL;
2720}
2721
2e87570b 2722/* pairs with nvme_pci_alloc_dev */
1673f1f0 2723static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
5e82e952 2724{
1673f1f0 2725 struct nvme_dev *dev = to_nvme_dev(ctrl);
9ac27090 2726
770597ec 2727 nvme_free_tagset(dev);
253fd4ac
IR		 2728 put_device(dev->dev);
2729 kfree(dev->queues);
5e82e952
KB		 2730 kfree(dev);
2731}
2732
fd634f41 2733static void nvme_reset_work(struct work_struct *work)
5e82e952 2734{
d86c4d8e
CH		 2735 struct nvme_dev *dev =
2736 container_of(work, struct nvme_dev, ctrl.reset_work);
a98e58e5 2737 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
e71afda4 2738 int result;
5e82e952 2739
7764656b
ZC		 2740 if (dev->ctrl.state != NVME_CTRL_RESETTING) {
2741 dev_warn(dev->ctrl.device, "ctrl state %d is not RESETTING\n",
2742 dev->ctrl.state);
8cb9f10b 2743 return;
e71afda4 2744 }
5e82e952 2745
fd634f41
CH		 2746 /*
2747 * If we're called to reset a live controller first shut it down before
2748 * moving on.
2749 */
b00a726a 2750 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
a5cdb68c 2751 nvme_dev_disable(dev, false);
d6135c3a 2752 nvme_sync_queues(&dev->ctrl);
5e82e952 2753
5c959d73 2754 mutex_lock(&dev->shutdown_lock);
b00a726a 2755 result = nvme_pci_enable(dev);
f0b50732 2756 if (result)
4726bcf3 2757 goto out_unlock;
9f27bd70 2758 nvme_unquiesce_admin_queue(&dev->ctrl);
5c959d73
KB		 2759 mutex_unlock(&dev->shutdown_lock);
2760
2761 /*
2762 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
2763 * initializing procedure here.
2764 */
2765 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
2766 dev_warn(dev->ctrl.device,
2767 "failed to mark controller CONNECTING\n");
cee6c269 2768 result = -EBUSY;
5c959d73
KB		 2769 goto out;
2770 }
943e942e 2771
94cc781f 2772 result = nvme_init_ctrl_finish(&dev->ctrl, was_suspend);
ce4541f4 2773 if (result)
f58944e2 2774 goto out;
ce4541f4 2775
65a54646 2776 nvme_dbbuf_dma_alloc(dev);
f9f38e33 2777
acb71e53
CH		 2778 result = nvme_setup_host_mem(dev);
2779 if (result < 0)
2780 goto out;
87ad72a5 2781
f0b50732 2782 result = nvme_setup_io_queues(dev);
badc34d4 2783 if (result)
f58944e2 2784 goto out;
f0b50732 2785
2659e57b 2786 /*
eac3ef26
CH		 2787 * Freeze and update the number of I/O queues as thos might have
2788 * changed. If there are no I/O queues left after this reset, keep the
2789 * controller around but remove all namespaces.
2659e57b 2790 */
eac3ef26 2791 if (dev->online_queues > 1) {
9f27bd70 2792 nvme_unquiesce_io_queues(&dev->ctrl);
302ad8cc 2793 nvme_wait_freeze(&dev->ctrl);
eac3ef26 2794 nvme_pci_update_nr_queues(dev);
2455a4b7 2795 nvme_dbbuf_set(dev);
302ad8cc 2796 nvme_unfreeze(&dev->ctrl);
3cf519b5 2797 } else {
eac3ef26
CH		 2798 dev_warn(dev->ctrl.device, "IO queues lost\n");
2799 nvme_mark_namespaces_dead(&dev->ctrl);
9f27bd70 2800 nvme_unquiesce_io_queues(&dev->ctrl);
eac3ef26
CH		 2801 nvme_remove_namespaces(&dev->ctrl);
2802 nvme_free_tagset(dev);
3cf519b5
CH		 2803 }
2804
2b1b7e78
JW		 2805 /*
2806 * If only admin queue live, keep it to do further investigation or
2807 * recovery.
2808 */
5d02a5c1 2809 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
2b1b7e78 2810 dev_warn(dev->ctrl.device,
5d02a5c1 2811 "failed to mark controller live state\n");
e71afda4 2812 result = -ENODEV;
bb8d261e
CH		 2813 goto out;
2814 }
92911a55 2815
d09f2b45 2816 nvme_start_ctrl(&dev->ctrl);
3cf519b5 2817 return;
f0b50732 2818
4726bcf3
KB		 2819 out_unlock:
2820 mutex_unlock(&dev->shutdown_lock);
3cf519b5 2821 out:
c7c16c5b
CH		 2822 /*
2823 * Set state to deleting now to avoid blocking nvme_wait_reset(), which
2824 * may be holding this pci_dev's device lock.
2825 */
2826 dev_warn(dev->ctrl.device, "Disabling device after reset failure: %d\n",
2827 result);
2828 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
2829 nvme_dev_disable(dev, true);
2830 nvme_mark_namespaces_dead(&dev->ctrl);
2831 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
9a6b9458
KB		 2832}
2833
1c63dc66 2834static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
9ca97374 2835{
1c63dc66 2836 *val = readl(to_nvme_dev(ctrl)->bar + off);
90667892 2837 return 0;
9ca97374
TH		 2838}
2839
5fd4ce1b 2840static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
4cc06521 2841{
5fd4ce1b
CH		 2842 writel(val, to_nvme_dev(ctrl)->bar + off);
2843 return 0;
2844}
4cc06521 2845
7fd8930f
CH		 2846static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2847{
3a8ecc93 2848 *val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off);
7fd8930f 2849 return 0;
4cc06521
KB		 2850}
2851
97c12223
KB		 2852static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
2853{
2854 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2855
2db24e4a 2856 return snprintf(buf, size, "%s\n", dev_name(&pdev->dev));
97c12223
KB		 2857}
2858
2f0dad17
KB		 2859static void nvme_pci_print_device_info(struct nvme_ctrl *ctrl)
2860{
2861 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2862 struct nvme_subsystem *subsys = ctrl->subsys;
2863
2864 dev_err(ctrl->device,
2865 "VID:DID %04x:%04x model:%.*s firmware:%.*s\n",
2866 pdev->vendor, pdev->device,
2867 nvme_strlen(subsys->model, sizeof(subsys->model)),
2868 subsys->model, nvme_strlen(subsys->firmware_rev,
2869 sizeof(subsys->firmware_rev)),
2870 subsys->firmware_rev);
2871}
2872
2f859441
LG		 2873static bool nvme_pci_supports_pci_p2pdma(struct nvme_ctrl *ctrl)
2874{
2875 struct nvme_dev *dev = to_nvme_dev(ctrl);
2876
2877 return dma_pci_p2pdma_supported(dev->dev);
2878}
2879
1c63dc66 2880static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
1a353d85 2881 .name = "pcie",
e439bb12 2882 .module = THIS_MODULE,
2f859441 2883 .flags = NVME_F_METADATA_SUPPORTED,
86adbf0c 2884 .dev_attr_groups = nvme_pci_dev_attr_groups,
1c63dc66 2885 .reg_read32 = nvme_pci_reg_read32,
5fd4ce1b 2886 .reg_write32 = nvme_pci_reg_write32,
7fd8930f 2887 .reg_read64 = nvme_pci_reg_read64,
1673f1f0 2888 .free_ctrl = nvme_pci_free_ctrl,
f866fc42 2889 .submit_async_event = nvme_pci_submit_async_event,
97c12223 2890 .get_address = nvme_pci_get_address,
2f0dad17 2891 .print_device_info = nvme_pci_print_device_info,
2f859441 2892 .supports_pci_p2pdma = nvme_pci_supports_pci_p2pdma,
1c63dc66 2893};
4cc06521 2894
b00a726a
KB		 2895static int nvme_dev_map(struct nvme_dev *dev)
2896{
b00a726a
KB		 2897 struct pci_dev *pdev = to_pci_dev(dev->dev);
2898
a1f447b3 2899 if (pci_request_mem_regions(pdev, "nvme"))
b00a726a
KB		 2900 return -ENODEV;
2901
97f6ef64 2902 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
b00a726a
KB		 2903 goto release;
2904
9fa196e7 2905 return 0;
b00a726a 2906 release:
9fa196e7
MG		 2907 pci_release_mem_regions(pdev);
2908 return -ENODEV;
b00a726a
KB		 2909}
2910
8427bbc2 2911static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
ff5350a8
AL		 2912{
2913 if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
2914 /*
2915 * Several Samsung devices seem to drop off the PCIe bus
2916 * randomly when APST is on and uses the deepest sleep state.
2917 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2918 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2919 * 950 PRO 256GB", but it seems to be restricted to two Dell
2920 * laptops.
2921 */
2922 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
2923 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
2924 dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
2925 return NVME_QUIRK_NO_DEEPEST_PS;
8427bbc2
KHF		 2926 } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
2927 /*
2928 * Samsung SSD 960 EVO drops off the PCIe bus after system
467c77d4
JJ		 2929 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
2930 * within few minutes after bootup on a Coffee Lake board -
2931 * ASUS PRIME Z370-A
8427bbc2
KHF		 2932 */
2933 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
467c77d4
JJ		 2934 (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") ||
2935 dmi_match(DMI_BOARD_NAME, "PRIME Z370-A")))
8427bbc2 2936 return NVME_QUIRK_NO_APST;
1fae37ac
S		 2937 } else if ((pdev->vendor == 0x144d && (pdev->device == 0xa801 ||
2938 pdev->device == 0xa808 || pdev->device == 0xa809)) ||
2939 (pdev->vendor == 0x1e0f && pdev->device == 0x0001)) {
2940 /*
2941 * Forcing to use host managed nvme power settings for
2942 * lowest idle power with quick resume latency on
2943 * Samsung and Toshiba SSDs based on suspend behavior
2944 * on Coffee Lake board for LENOVO C640
2945 */
2946 if ((dmi_match(DMI_BOARD_VENDOR, "LENOVO")) &&
2947 dmi_match(DMI_BOARD_NAME, "LNVNB161216"))
2948 return NVME_QUIRK_SIMPLE_SUSPEND;
ff5350a8
AL		 2949 }
2950
2951 return 0;
2952}
2953
2e87570b
CH		 2954static struct nvme_dev *nvme_pci_alloc_dev(struct pci_dev *pdev,
2955 const struct pci_device_id *id)
18119775 2956{
ff5350a8 2957 unsigned long quirks = id->driver_data;
2e87570b
CH		 2958 int node = dev_to_node(&pdev->dev);
2959 struct nvme_dev *dev;
2960 int ret = -ENOMEM;
b60503ba 2961
a4aea562 2962 if (node == NUMA_NO_NODE)
2fa84351 2963 set_dev_node(&pdev->dev, first_memory_node);
a4aea562
MB		 2964
2965 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
b60503ba 2966 if (!dev)
dc785d69 2967 return ERR_PTR(-ENOMEM);
2e87570b 2968 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
2e87570b 2969 mutex_init(&dev->shutdown_lock);
147b27e4 2970
2a5bcfdd
WZ		 2971 dev->nr_write_queues = write_queues;
2972 dev->nr_poll_queues = poll_queues;
2973 dev->nr_allocated_queues = nvme_max_io_queues(dev) + 1;
2974 dev->queues = kcalloc_node(dev->nr_allocated_queues,
2975 sizeof(struct nvme_queue), GFP_KERNEL, node);
b60503ba 2976 if (!dev->queues)
2e87570b 2977 goto out_free_dev;
b60503ba 2978
e75ec752 2979 dev->dev = get_device(&pdev->dev);
4cc06521 2980
8427bbc2 2981 quirks |= check_vendor_combination_bug(pdev);
2744d7a0 2982 if (!noacpi && acpi_storage_d3(&pdev->dev)) {
df4f9bc4
DB		 2983 /*
2984 * Some systems use a bios work around to ask for D3 on
2985 * platforms that support kernel managed suspend.
2986 */
2987 dev_info(&pdev->dev,
2988 "platform quirk: setting simple suspend\n");
2989 quirks |= NVME_QUIRK_SIMPLE_SUSPEND;
2990 }
2e87570b
CH		 2991 ret = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
2992 quirks);
2993 if (ret)
2994 goto out_put_device;
924bd96e
CH		 2995
2996 if (dev->ctrl.quirks & NVME_QUIRK_DMA_ADDRESS_BITS_48)
2997 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(48));
2998 else
2999 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
3f30a79c
CH		 3000 dma_set_min_align_mask(&pdev->dev, NVME_CTRL_PAGE_SIZE - 1);
3001 dma_set_max_seg_size(&pdev->dev, 0xffffffff);
df4f9bc4 3002
943e942e 3003 /*
3f30a79c
CH		 3004 * Limit the max command size to prevent iod->sg allocations going
3005 * over a single page.
943e942e 3006 */
3f30a79c
CH		 3007 dev->ctrl.max_hw_sectors = min_t(u32,
3008 NVME_MAX_KB_SZ << 1, dma_max_mapping_size(&pdev->dev) >> 9);
3009 dev->ctrl.max_segments = NVME_MAX_SEGS;
943e942e 3010
3f30a79c
CH		 3011 /*
3012 * There is no support for SGLs for metadata (yet), so we are limited to
3013 * a single integrity segment for the separate metadata pointer.
3014 */
3015 dev->ctrl.max_integrity_segments = 1;
2e87570b 3016 return dev;
df4f9bc4 3017
2e87570b
CH		 3018out_put_device:
3019 put_device(dev->dev);
3020 kfree(dev->queues);
3021out_free_dev:
3022 kfree(dev);
3023 return ERR_PTR(ret);
3024}
943e942e 3025
2e87570b
CH		 3026static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
3027{
3028 struct nvme_dev *dev;
3029 int result = -ENOMEM;
3030
3031 dev = nvme_pci_alloc_dev(pdev, id);
dc785d69
IC		 3032 if (IS_ERR(dev))
3033 return PTR_ERR(dev);
2e87570b
CH		 3034
3035 result = nvme_dev_map(dev);
b6e44b4c 3036 if (result)
2e87570b
CH		 3037 goto out_uninit_ctrl;
3038
3039 result = nvme_setup_prp_pools(dev);
081a7d95 3040 if (result)
2e87570b 3041 goto out_dev_unmap;
943e942e 3042
2e87570b 3043 result = nvme_pci_alloc_iod_mempool(dev);
b6e44b4c 3044 if (result)
2e87570b 3045 goto out_release_prp_pools;
b6e44b4c 3046
1b3c47c1
SG		 3047 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
3048
eac3ef26
CH		 3049 result = nvme_pci_enable(dev);
3050 if (result)
3051 goto out_release_iod_mempool;
3052
0da7feaa
CH		 3053 result = nvme_alloc_admin_tag_set(&dev->ctrl, &dev->admin_tagset,
3054 &nvme_mq_admin_ops, sizeof(struct nvme_iod));
eac3ef26
CH		 3055 if (result)
3056 goto out_disable;
3057
3058 /*
3059 * Mark the controller as connecting before sending admin commands to
3060 * allow the timeout handler to do the right thing.
3061 */
3062 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
3063 dev_warn(dev->ctrl.device,
3064 "failed to mark controller CONNECTING\n");
3065 result = -EBUSY;
3066 goto out_disable;
3067 }
3068
3069 result = nvme_init_ctrl_finish(&dev->ctrl, false);
3070 if (result)
3071 goto out_disable;
3072
3073 nvme_dbbuf_dma_alloc(dev);
3074
3075 result = nvme_setup_host_mem(dev);
3076 if (result < 0)
3077 goto out_disable;
3078
3079 result = nvme_setup_io_queues(dev);
3080 if (result)
3081 goto out_disable;
4caff8fc 3082
eac3ef26 3083 if (dev->online_queues > 1) {
0da7feaa
CH		 3084 nvme_alloc_io_tag_set(&dev->ctrl, &dev->tagset, &nvme_mq_ops,
3085 nvme_pci_nr_maps(dev), sizeof(struct nvme_iod));
eac3ef26 3086 nvme_dbbuf_set(dev);
eac3ef26
CH		 3087 }
3088
0da7feaa
CH		 3089 if (!dev->ctrl.tagset)
3090 dev_warn(dev->ctrl.device, "IO queues not created\n");
3091
eac3ef26
CH		 3092 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
3093 dev_warn(dev->ctrl.device,
3094 "failed to mark controller live state\n");
3095 result = -ENODEV;
3096 goto out_disable;
3097 }
3098
2e87570b 3099 pci_set_drvdata(pdev, dev);
1b3c47c1 3100
eac3ef26
CH		 3101 nvme_start_ctrl(&dev->ctrl);
3102 nvme_put_ctrl(&dev->ctrl);
5a5754a4 3103 flush_work(&dev->ctrl.scan_work);
b60503ba
MW		 3104 return 0;
3105
eac3ef26
CH		 3106out_disable:
3107 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
3108 nvme_dev_disable(dev, true);
3109 nvme_free_host_mem(dev);
3110 nvme_dev_remove_admin(dev);
3111 nvme_dbbuf_dma_free(dev);
3112 nvme_free_queues(dev, 0);
3113out_release_iod_mempool:
b6e44b4c 3114 mempool_destroy(dev->iod_mempool);
2e87570b 3115out_release_prp_pools:
091b6092 3116 nvme_release_prp_pools(dev);
2e87570b 3117out_dev_unmap:
b00c9b7a 3118 nvme_dev_unmap(dev);
2e87570b
CH		 3119out_uninit_ctrl:
3120 nvme_uninit_ctrl(&dev->ctrl);
b60503ba
MW		 3121 return result;
3122}
3123
775755ed 3124static void nvme_reset_prepare(struct pci_dev *pdev)
f0d54a54 3125{
a6739479 3126 struct nvme_dev *dev = pci_get_drvdata(pdev);
c1ac9a4b
KB		 3127
3128 /*
3129 * We don't need to check the return value from waiting for the reset
3130 * state as pci_dev device lock is held, making it impossible to race
3131 * with ->remove().
3132 */
3133 nvme_disable_prepare_reset(dev, false);
3134 nvme_sync_queues(&dev->ctrl);
775755ed 3135}
f0d54a54 3136
775755ed
CH		 3137static void nvme_reset_done(struct pci_dev *pdev)
3138{
f263fbb8 3139 struct nvme_dev *dev = pci_get_drvdata(pdev);
c1ac9a4b
KB		 3140
3141 if (!nvme_try_sched_reset(&dev->ctrl))
3142 flush_work(&dev->ctrl.reset_work);
f0d54a54
KB		 3143}
3144
09ece142
KB		 3145static void nvme_shutdown(struct pci_dev *pdev)
3146{
3147 struct nvme_dev *dev = pci_get_drvdata(pdev);
4e523547 3148
c1ac9a4b 3149 nvme_disable_prepare_reset(dev, true);
09ece142
KB		 3150}
3151
f58944e2
KB		 3152/*
3153 * The driver's remove may be called on a device in a partially initialized
3154 * state. This function must not have any dependencies on the device state in
3155 * order to proceed.
3156 */
8d85fce7 3157static void nvme_remove(struct pci_dev *pdev)
b60503ba
MW		 3158{
3159 struct nvme_dev *dev = pci_get_drvdata(pdev);
9a6b9458 3160
bb8d261e 3161 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
9a6b9458 3162 pci_set_drvdata(pdev, NULL);
0ff9d4e1 3163
6db28eda 3164 if (!pci_device_is_present(pdev)) {
0ff9d4e1 3165 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
1d39e692 3166 nvme_dev_disable(dev, true);
6db28eda 3167 }
0ff9d4e1 3168
d86c4d8e 3169 flush_work(&dev->ctrl.reset_work);
d09f2b45
SG		 3170 nvme_stop_ctrl(&dev->ctrl);
3171 nvme_remove_namespaces(&dev->ctrl);
a5cdb68c 3172 nvme_dev_disable(dev, true);
87ad72a5 3173 nvme_free_host_mem(dev);
a4aea562 3174 nvme_dev_remove_admin(dev);
c11b7716 3175 nvme_dbbuf_dma_free(dev);
a1a5ef99 3176 nvme_free_queues(dev, 0);
c11b7716 3177 mempool_destroy(dev->iod_mempool);
9a6b9458 3178 nvme_release_prp_pools(dev);
b00a726a 3179 nvme_dev_unmap(dev);
726612b6 3180 nvme_uninit_ctrl(&dev->ctrl);
b60503ba
MW		 3181}
3182
671a6018 3183#ifdef CONFIG_PM_SLEEP
d916b1be
KB		 3184static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps)
3185{
3186 return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps);
3187}
3188
3189static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps)
3190{
3191 return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL);
3192}
3193
3194static int nvme_resume(struct device *dev)
3195{
3196 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
3197 struct nvme_ctrl *ctrl = &ndev->ctrl;
3198
4eaefe8c 3199 if (ndev->last_ps == U32_MAX ||
d916b1be 3200 nvme_set_power_state(ctrl, ndev->last_ps) != 0)
e5ad96f3
KB		 3201 goto reset;
3202 if (ctrl->hmpre && nvme_setup_host_mem(ndev))
3203 goto reset;
3204
d916b1be 3205 return 0;
e5ad96f3
KB		 3206reset:
3207 return nvme_try_sched_reset(ctrl);
d916b1be
KB		 3208}
3209
cd638946
KB		 3210static int nvme_suspend(struct device *dev)
3211{
3212 struct pci_dev *pdev = to_pci_dev(dev);
3213 struct nvme_dev *ndev = pci_get_drvdata(pdev);
d916b1be
KB		 3214 struct nvme_ctrl *ctrl = &ndev->ctrl;
3215 int ret = -EBUSY;
3216
4eaefe8c
RW		 3217 ndev->last_ps = U32_MAX;
3218
d916b1be
KB		 3219 /*
3220 * The platform does not remove power for a kernel managed suspend so
3221 * use host managed nvme power settings for lowest idle power if
3222 * possible. This should have quicker resume latency than a full device
3223 * shutdown. But if the firmware is involved after the suspend or the
3224 * device does not support any non-default power states, shut down the
3225 * device fully.
4eaefe8c
RW		 3226 *
3227 * If ASPM is not enabled for the device, shut down the device and allow
3228 * the PCI bus layer to put it into D3 in order to take the PCIe link
3229 * down, so as to allow the platform to achieve its minimum low-power
3230 * state (which may not be possible if the link is up).
d916b1be 3231 */
4eaefe8c 3232 if (pm_suspend_via_firmware() || !ctrl->npss ||
cb32de1b 3233 !pcie_aspm_enabled(pdev) ||
c1ac9a4b
KB		 3234 (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND))
3235 return nvme_disable_prepare_reset(ndev, true);
d916b1be
KB		 3236
3237 nvme_start_freeze(ctrl);
3238 nvme_wait_freeze(ctrl);
3239 nvme_sync_queues(ctrl);
3240
5d02a5c1 3241 if (ctrl->state != NVME_CTRL_LIVE)
d916b1be
KB		 3242 goto unfreeze;
3243
e5ad96f3
KB		 3244 /*
3245 * Host memory access may not be successful in a system suspend state,
3246 * but the specification allows the controller to access memory in a
3247 * non-operational power state.
3248 */
3249 if (ndev->hmb) {
3250 ret = nvme_set_host_mem(ndev, 0);
3251 if (ret < 0)
3252 goto unfreeze;
3253 }
3254
d916b1be
KB		 3255 ret = nvme_get_power_state(ctrl, &ndev->last_ps);
3256 if (ret < 0)
3257 goto unfreeze;
3258
7cbb5c6f
ML		 3259 /*
3260 * A saved state prevents pci pm from generically controlling the
3261 * device's power. If we're using protocol specific settings, we don't
3262 * want pci interfering.
3263 */
3264 pci_save_state(pdev);
3265
d916b1be
KB		 3266 ret = nvme_set_power_state(ctrl, ctrl->npss);
3267 if (ret < 0)
3268 goto unfreeze;
3269
3270 if (ret) {
7cbb5c6f
ML		 3271 /* discard the saved state */
3272 pci_load_saved_state(pdev, NULL);
3273
d916b1be
KB		 3274 /*
3275 * Clearing npss forces a controller reset on resume. The
05d3046f 3276 * correct value will be rediscovered then.
d916b1be 3277 */
c1ac9a4b 3278 ret = nvme_disable_prepare_reset(ndev, true);
d916b1be 3279 ctrl->npss = 0;
d916b1be 3280 }
d916b1be
KB		 3281unfreeze:
3282 nvme_unfreeze(ctrl);
3283 return ret;
3284}
3285
3286static int nvme_simple_suspend(struct device *dev)
3287{
3288 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
4e523547 3289
c1ac9a4b 3290 return nvme_disable_prepare_reset(ndev, true);
cd638946
KB		 3291}
3292
d916b1be 3293static int nvme_simple_resume(struct device *dev)
cd638946
KB		 3294{
3295 struct pci_dev *pdev = to_pci_dev(dev);
3296 struct nvme_dev *ndev = pci_get_drvdata(pdev);
cd638946 3297
c1ac9a4b 3298 return nvme_try_sched_reset(&ndev->ctrl);
cd638946
KB		 3299}
3300
21774222 3301static const struct dev_pm_ops nvme_dev_pm_ops = {
d916b1be
KB		 3302 .suspend = nvme_suspend,
3303 .resume = nvme_resume,
3304 .freeze = nvme_simple_suspend,
3305 .thaw = nvme_simple_resume,
3306 .poweroff = nvme_simple_suspend,
3307 .restore = nvme_simple_resume,
3308};
3309#endif /* CONFIG_PM_SLEEP */
b60503ba 3310
a0a3408e
KB		 3311static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
3312 pci_channel_state_t state)
3313{
3314 struct nvme_dev *dev = pci_get_drvdata(pdev);
3315
3316 /*
3317 * A frozen channel requires a reset. When detected, this method will
3318 * shutdown the controller to quiesce. The controller will be restarted
3319 * after the slot reset through driver's slot_reset callback.
3320 */
a0a3408e
KB		 3321 switch (state) {
3322 case pci_channel_io_normal:
3323 return PCI_ERS_RESULT_CAN_RECOVER;
3324 case pci_channel_io_frozen:
d011fb31
KB		 3325 dev_warn(dev->ctrl.device,
3326 "frozen state error detected, reset controller\n");
a5cdb68c 3327 nvme_dev_disable(dev, false);
a0a3408e
KB		 3328 return PCI_ERS_RESULT_NEED_RESET;
3329 case pci_channel_io_perm_failure:
d011fb31
KB		 3330 dev_warn(dev->ctrl.device,
3331 "failure state error detected, request disconnect\n");
a0a3408e
KB		 3332 return PCI_ERS_RESULT_DISCONNECT;
3333 }
3334 return PCI_ERS_RESULT_NEED_RESET;
3335}
3336
3337static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
3338{
3339 struct nvme_dev *dev = pci_get_drvdata(pdev);
3340
1b3c47c1 3341 dev_info(dev->ctrl.device, "restart after slot reset\n");
a0a3408e 3342 pci_restore_state(pdev);
d86c4d8e 3343 nvme_reset_ctrl(&dev->ctrl);
a0a3408e
KB		 3344 return PCI_ERS_RESULT_RECOVERED;
3345}
3346
3347static void nvme_error_resume(struct pci_dev *pdev)
3348{
72cd4cc2
KB		 3349 struct nvme_dev *dev = pci_get_drvdata(pdev);
3350
3351 flush_work(&dev->ctrl.reset_work);
a0a3408e
KB		 3352}
3353
1d352035 3354static const struct pci_error_handlers nvme_err_handler = {
b60503ba 3355 .error_detected = nvme_error_detected,
b60503ba
MW		 3356 .slot_reset = nvme_slot_reset,
3357 .resume = nvme_error_resume,
775755ed
CH		 3358 .reset_prepare = nvme_reset_prepare,
3359 .reset_done = nvme_reset_done,
b60503ba
MW		 3360};
3361
6eb0d698 3362static const struct pci_device_id nvme_id_table[] = {
972b13e2 3363 { PCI_VDEVICE(INTEL, 0x0953), /* Intel 750/P3500/P3600/P3700 */
08095e70 3364 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 3365 NVME_QUIRK_DEALLOCATE_ZEROES, },
972b13e2 3366 { PCI_VDEVICE(INTEL, 0x0a53), /* Intel P3520 */
99466e70 3367 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 3368 NVME_QUIRK_DEALLOCATE_ZEROES, },
972b13e2 3369 { PCI_VDEVICE(INTEL, 0x0a54), /* Intel P4500/P4600 */
99466e70 3370 .driver_data = NVME_QUIRK_STRIPE_SIZE |
25e58af4
WZ		 3371 NVME_QUIRK_DEALLOCATE_ZEROES |
3372 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
972b13e2 3373 { PCI_VDEVICE(INTEL, 0x0a55), /* Dell Express Flash P4600 */
f99cb7af
DWF		 3374 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3375 NVME_QUIRK_DEALLOCATE_ZEROES, },
50af47d0 3376 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */
9abd68ef 3377 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
6c6aa2f2 3378 NVME_QUIRK_MEDIUM_PRIO_SQ |
ce4cc313
DM		 3379 NVME_QUIRK_NO_TEMP_THRESH_CHANGE |
3380 NVME_QUIRK_DISABLE_WRITE_ZEROES, },
6299358d
JD		 3381 { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */
3382 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
540c801c 3383 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */
7b210e4e 3384 .driver_data = NVME_QUIRK_IDENTIFY_CNS |
66dd346b
CH		 3385 NVME_QUIRK_DISABLE_WRITE_ZEROES |
3386 NVME_QUIRK_BOGUS_NID, },
3387 { PCI_VDEVICE(REDHAT, 0x0010), /* Qemu emulated controller */
3388 .driver_data = NVME_QUIRK_BOGUS_NID, },
5bedd3af 3389 { PCI_DEVICE(0x126f, 0x2263), /* Silicon Motion unidentified */
c98a8793
KB		 3390 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST |
3391 NVME_QUIRK_BOGUS_NID, },
0302ae60 3392 { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */
5e112d3f
JE		 3393 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
3394 NVME_QUIRK_NO_NS_DESC_LIST, },
54adc010
GP		 3395 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
3396 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
8c97eecc
JL		 3397 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */
3398 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
015282c9
WW		 3399 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
3400 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
d554b5e1
MP		 3401 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */
3402 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3403 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */
7ee5c78c 3404 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
abbb5f59 3405 NVME_QUIRK_DISABLE_WRITE_ZEROES|
7ee5c78c 3406 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
2cf7a77e
KB		 3407 { PCI_DEVICE(0x1987, 0x5012), /* Phison E12 */
3408 .driver_data = NVME_QUIRK_BOGUS_NID, },
c9e95c39 3409 { PCI_DEVICE(0x1987, 0x5016), /* Phison E16 */
73029c9b
KB		 3410 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN |
3411 NVME_QUIRK_BOGUS_NID, },
d14c2731
TH		 3412 { PCI_DEVICE(0x1987, 0x5019), /* phison E19 */
3413 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3414 { PCI_DEVICE(0x1987, 0x5021), /* Phison E21 */
3415 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
6e6a6828
PT		 3416 { PCI_DEVICE(0x1b4b, 0x1092), /* Lexar 256 GB SSD */
3417 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST |
3418 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
e1c70d79
LVS		 3419 { PCI_DEVICE(0x1cc1, 0x33f8), /* ADATA IM2P33F8ABR1 1 TB */
3420 .driver_data = NVME_QUIRK_BOGUS_NID, },
08b903b5 3421 { PCI_DEVICE(0x10ec, 0x5762), /* ADATA SX6000LNP */
1629de0e
PG		 3422 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN |
3423 NVME_QUIRK_BOGUS_NID, },
5f69f009
DW		 3424 { PCI_DEVICE(0x10ec, 0x5763), /* ADATA SX6000PNP */
3425 .driver_data = NVME_QUIRK_BOGUS_NID, },
f03e42c6
GC		 3426 { PCI_DEVICE(0x1cc1, 0x8201), /* ADATA SX8200PNP 512GB */
3427 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3428 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
41f38043
LS		 3429 { PCI_DEVICE(0x1344, 0x5407), /* Micron Technology Inc NVMe SSD */
3430 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN },
d5ceb4d1
BH		 3431 { PCI_DEVICE(0x1344, 0x6001), /* Micron Nitro NVMe */
3432 .driver_data = NVME_QUIRK_BOGUS_NID, },
5611ec2b
KHF		 3433 { PCI_DEVICE(0x1c5c, 0x1504), /* SK Hynix PC400 */
3434 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
c4f01a77
KB		 3435 { PCI_DEVICE(0x1c5c, 0x174a), /* SK Hynix P31 SSD */
3436 .driver_data = NVME_QUIRK_BOGUS_NID, },
02ca079c
KHF		 3437 { PCI_DEVICE(0x15b7, 0x2001), /* Sandisk Skyhawk */
3438 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
89919929
CK		 3439 { PCI_DEVICE(0x1d97, 0x2263), /* SPCC */
3440 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
43047e08 3441 { PCI_DEVICE(0x144d, 0xa80b), /* Samsung PM9B1 256G and 512G */
3442 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3443 { PCI_DEVICE(0x144d, 0xa809), /* Samsung MZALQ256HBJD 256G */
3444 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3445 { PCI_DEVICE(0x1cc4, 0x6303), /* UMIS RPJTJ512MGE1QDY 512G */
3446 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3447 { PCI_DEVICE(0x1cc4, 0x6302), /* UMIS RPJTJ256MGE1QDY 256G */
3448 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
dc22c1c0
ZB		 3449 { PCI_DEVICE(0x2646, 0x2262), /* KINGSTON SKC2000 NVMe SSD */
3450 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
538e4a8c
TL		 3451 { PCI_DEVICE(0x2646, 0x2263), /* KINGSTON A2000 NVMe SSD */
3452 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
ac9b57d4
XL		 3453 { PCI_DEVICE(0x2646, 0x5018), /* KINGSTON OM8SFP4xxxxP OS21012 NVMe SSD */
3454 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3455 { PCI_DEVICE(0x2646, 0x5016), /* KINGSTON OM3PGP4xxxxP OS21011 NVMe SSD */
3456 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3457 { PCI_DEVICE(0x2646, 0x501A), /* KINGSTON OM8PGP4xxxxP OS21005 NVMe SSD */
3458 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3459 { PCI_DEVICE(0x2646, 0x501B), /* KINGSTON OM8PGP4xxxxQ OS21005 NVMe SSD */
3460 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3461 { PCI_DEVICE(0x2646, 0x501E), /* KINGSTON OM3PGP4xxxxQ OS21011 NVMe SSD */
3462 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
8d6e38f6
TDF		 3463 { PCI_DEVICE(0x1f40, 0x5236), /* Netac Technologies Co. NV7000 NVMe SSD */
3464 .driver_data = NVME_QUIRK_BOGUS_NID, },
70ce3455
CH		 3465 { PCI_DEVICE(0x1e4B, 0x1001), /* MAXIO MAP1001 */
3466 .driver_data = NVME_QUIRK_BOGUS_NID, },
a98a945b
CH		 3467 { PCI_DEVICE(0x1e4B, 0x1002), /* MAXIO MAP1002 */
3468 .driver_data = NVME_QUIRK_BOGUS_NID, },
3469 { PCI_DEVICE(0x1e4B, 0x1202), /* MAXIO MAP1202 */
3470 .driver_data = NVME_QUIRK_BOGUS_NID, },
3765fad5
SR		 3471 { PCI_DEVICE(0x1cc1, 0x5350), /* ADATA XPG GAMMIX S50 */
3472 .driver_data = NVME_QUIRK_BOGUS_NID, },
f37527a0
DK		 3473 { PCI_DEVICE(0x1dbe, 0x5236), /* ADATA XPG GAMMIX S70 */
3474 .driver_data = NVME_QUIRK_BOGUS_NID, },
d5d3c100
XR		 3475 { PCI_DEVICE(0x1e49, 0x0021), /* ZHITAI TiPro5000 NVMe SSD */
3476 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
6b961bce
NW		 3477 { PCI_DEVICE(0x1e49, 0x0041), /* ZHITAI TiPro7000 NVMe SSD */
3478 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
d6c52fa3
TG		 3479 { PCI_DEVICE(0xc0a9, 0x540a), /* Crucial P2 */
3480 .driver_data = NVME_QUIRK_BOGUS_NID, },
200dccd0
SA		 3481 { PCI_DEVICE(0x1d97, 0x2263), /* Lexar NM610 */
3482 .driver_data = NVME_QUIRK_BOGUS_NID, },
80b26240
A		 3483 { PCI_DEVICE(0x1d97, 0x2269), /* Lexar NM760 */
3484 .driver_data = NVME_QUIRK_BOGUS_NID, },
4bdf2603
FS		 3485 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0061),
3486 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3487 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0065),
3488 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3489 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x8061),
3490 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3491 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd00),
3492 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3493 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd01),
3494 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3495 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd02),
3496 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
98f7b86a
AS		 3497 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001),
3498 .driver_data = NVME_QUIRK_SINGLE_VECTOR },
124298bd 3499 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
66341331
BH		 3500 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005),
3501 .driver_data = NVME_QUIRK_SINGLE_VECTOR |
d38e9f04 3502 NVME_QUIRK_128_BYTES_SQES |
a2941f6a 3503 NVME_QUIRK_SHARED_TAGS |
453116a4
HM		 3504 NVME_QUIRK_SKIP_CID_GEN |
3505 NVME_QUIRK_IDENTIFY_CNS },
0b85f59d 3506 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
b60503ba
MW		 3507 { 0, }
3508};
3509MODULE_DEVICE_TABLE(pci, nvme_id_table);
3510
3511static struct pci_driver nvme_driver = {
3512 .name = "nvme",
3513 .id_table = nvme_id_table,
3514 .probe = nvme_probe,
8d85fce7 3515 .remove = nvme_remove,
09ece142 3516 .shutdown = nvme_shutdown,
cd638946 3517 .driver = {
eac3ef26
CH		 3518 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
3519#ifdef CONFIG_PM_SLEEP
3520 .pm = &nvme_dev_pm_ops,
d916b1be 3521#endif
eac3ef26 3522 },
74d986ab 3523 .sriov_configure = pci_sriov_configure_simple,
b60503ba
MW		 3524 .err_handler = &nvme_err_handler,
3525};
3526
3527static int __init nvme_init(void)
3528{
81101540
CH		 3529 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
3530 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
3531 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
612b7286 3532 BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2);
c372cdd1
KB		 3533 BUILD_BUG_ON(DIV_ROUND_UP(nvme_pci_npages_prp(), NVME_CTRL_PAGE_SIZE) >
3534 S8_MAX);
17c33167 3535
9a6327d2 3536 return pci_register_driver(&nvme_driver);
b60503ba
MW		 3537}
3538
3539static void __exit nvme_exit(void)
3540{
3541 pci_unregister_driver(&nvme_driver);
03e0f3a6 3542 flush_workqueue(nvme_wq);
b60503ba
MW		 3543}
3544
3545MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3546MODULE_LICENSE("GPL");
c78b4713 3547MODULE_VERSION("1.0");
b60503ba
MW		 3548module_init(nvme_init);
3549module_exit(nvme_exit);
Linux 6.x block layer and io_uring tree(s)