nvme-pci: remap BAR0 to cover admin CQ doorbell for large stride
[linux-2.6-block.git] / drivers / nvme / host / pci.c
CommitLineData
b60503ba
MW
1/*
2 * NVM Express device driver
6eb0d698 3 * Copyright (c) 2011-2014, Intel Corporation.
b60503ba
MW
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
b60503ba
MW
13 */
14
a0a3408e 15#include <linux/aer.h>
8de05535 16#include <linux/bitops.h>
b60503ba 17#include <linux/blkdev.h>
a4aea562 18#include <linux/blk-mq.h>
dca51e78 19#include <linux/blk-mq-pci.h>
42f61420 20#include <linux/cpu.h>
fd63e9ce 21#include <linux/delay.h>
ff5350a8 22#include <linux/dmi.h>
b60503ba
MW
23#include <linux/errno.h>
24#include <linux/fs.h>
25#include <linux/genhd.h>
4cc09e2d 26#include <linux/hdreg.h>
5aff9382 27#include <linux/idr.h>
b60503ba
MW
28#include <linux/init.h>
29#include <linux/interrupt.h>
30#include <linux/io.h>
31#include <linux/kdev_t.h>
32#include <linux/kernel.h>
33#include <linux/mm.h>
34#include <linux/module.h>
35#include <linux/moduleparam.h>
77bf25ea 36#include <linux/mutex.h>
b60503ba 37#include <linux/pci.h>
be7b6275 38#include <linux/poison.h>
c3bfe717 39#include <linux/ptrace.h>
b60503ba
MW
40#include <linux/sched.h>
41#include <linux/slab.h>
e1e5e564 42#include <linux/t10-pi.h>
2d55cd5f 43#include <linux/timer.h>
b60503ba 44#include <linux/types.h>
2f8e2c87 45#include <linux/io-64-nonatomic-lo-hi.h>
1d277a63 46#include <asm/unaligned.h>
a98e58e5 47#include <linux/sed-opal.h>
797a796a 48
f11bb3e2
CH
49#include "nvme.h"
50
9d43cf64 51#define NVME_Q_DEPTH 1024
d31af0a3 52#define NVME_AQ_DEPTH 256
b60503ba
MW
53#define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
54#define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
c965809c 55
adf68f21
CH
56/*
57 * We handle AEN commands ourselves and don't even let the
58 * block layer know about them.
59 */
f866fc42 60#define NVME_AQ_BLKMQ_DEPTH (NVME_AQ_DEPTH - NVME_NR_AERS)
9d43cf64 61
58ffacb5
MW
62static int use_threaded_interrupts;
63module_param(use_threaded_interrupts, int, 0);
64
8ffaadf7
JD
65static bool use_cmb_sqes = true;
66module_param(use_cmb_sqes, bool, 0644);
67MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
68
87ad72a5
CH
69static unsigned int max_host_mem_size_mb = 128;
70module_param(max_host_mem_size_mb, uint, 0444);
71MODULE_PARM_DESC(max_host_mem_size_mb,
72 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
73
1c63dc66
CH
74struct nvme_dev;
75struct nvme_queue;
b3fffdef 76
4cc06521 77static int nvme_reset(struct nvme_dev *dev);
a0fa9647 78static void nvme_process_cq(struct nvme_queue *nvmeq);
a5cdb68c 79static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
d4b4ff8e 80
1c63dc66
CH
81/*
82 * Represents an NVM Express device. Each nvme_dev is a PCI function.
83 */
84struct nvme_dev {
1c63dc66
CH
85 struct nvme_queue **queues;
86 struct blk_mq_tag_set tagset;
87 struct blk_mq_tag_set admin_tagset;
88 u32 __iomem *dbs;
89 struct device *dev;
90 struct dma_pool *prp_page_pool;
91 struct dma_pool *prp_small_pool;
92 unsigned queue_count;
93 unsigned online_queues;
94 unsigned max_qid;
95 int q_depth;
96 u32 db_stride;
1c63dc66 97 void __iomem *bar;
97f6ef64 98 unsigned long bar_mapped_size;
1c63dc66 99 struct work_struct reset_work;
5c8809e6 100 struct work_struct remove_work;
2d55cd5f 101 struct timer_list watchdog_timer;
77bf25ea 102 struct mutex shutdown_lock;
1c63dc66 103 bool subsystem;
1c63dc66
CH
104 void __iomem *cmb;
105 dma_addr_t cmb_dma_addr;
106 u64 cmb_size;
107 u32 cmbsz;
202021c1 108 u32 cmbloc;
1c63dc66 109 struct nvme_ctrl ctrl;
db3cbfff 110 struct completion ioq_wait;
87ad72a5
CH
111
112 /* shadow doorbell buffer support: */
f9f38e33
HK
113 u32 *dbbuf_dbs;
114 dma_addr_t dbbuf_dbs_dma_addr;
115 u32 *dbbuf_eis;
116 dma_addr_t dbbuf_eis_dma_addr;
87ad72a5
CH
117
118 /* host memory buffer support: */
119 u64 host_mem_size;
120 u32 nr_host_mem_descs;
121 struct nvme_host_mem_buf_desc *host_mem_descs;
122 void **host_mem_desc_bufs;
4d115420 123};
1fa6aead 124
f9f38e33
HK
125static inline unsigned int sq_idx(unsigned int qid, u32 stride)
126{
127 return qid * 2 * stride;
128}
129
130static inline unsigned int cq_idx(unsigned int qid, u32 stride)
131{
132 return (qid * 2 + 1) * stride;
133}
134
1c63dc66
CH
135static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
136{
137 return container_of(ctrl, struct nvme_dev, ctrl);
138}
139
b60503ba
MW
140/*
141 * An NVM Express queue. Each device has at least two (one for admin
142 * commands and one for I/O commands).
143 */
144struct nvme_queue {
145 struct device *q_dmadev;
091b6092 146 struct nvme_dev *dev;
b60503ba
MW
147 spinlock_t q_lock;
148 struct nvme_command *sq_cmds;
8ffaadf7 149 struct nvme_command __iomem *sq_cmds_io;
b60503ba 150 volatile struct nvme_completion *cqes;
42483228 151 struct blk_mq_tags **tags;
b60503ba
MW
152 dma_addr_t sq_dma_addr;
153 dma_addr_t cq_dma_addr;
b60503ba
MW
154 u32 __iomem *q_db;
155 u16 q_depth;
6222d172 156 s16 cq_vector;
b60503ba
MW
157 u16 sq_tail;
158 u16 cq_head;
c30341dc 159 u16 qid;
e9539f47
MW
160 u8 cq_phase;
161 u8 cqe_seen;
f9f38e33
HK
162 u32 *dbbuf_sq_db;
163 u32 *dbbuf_cq_db;
164 u32 *dbbuf_sq_ei;
165 u32 *dbbuf_cq_ei;
b60503ba
MW
166};
167
71bd150c
CH
168/*
169 * The nvme_iod describes the data in an I/O, including the list of PRP
170 * entries. You can't see it in this data structure because C doesn't let
f4800d6d 171 * me express that. Use nvme_init_iod to ensure there's enough space
71bd150c
CH
172 * allocated to store the PRP list.
173 */
174struct nvme_iod {
d49187e9 175 struct nvme_request req;
f4800d6d
CH
176 struct nvme_queue *nvmeq;
177 int aborted;
71bd150c 178 int npages; /* In the PRP list. 0 means small pool in use */
71bd150c
CH
179 int nents; /* Used in scatterlist */
180 int length; /* Of data, in bytes */
181 dma_addr_t first_dma;
bf684057 182 struct scatterlist meta_sg; /* metadata requires single contiguous buffer */
f4800d6d
CH
183 struct scatterlist *sg;
184 struct scatterlist inline_sg[0];
b60503ba
MW
185};
186
187/*
188 * Check we didin't inadvertently grow the command struct
189 */
190static inline void _nvme_check_size(void)
191{
192 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
193 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
194 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
195 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
196 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
f8ebf840 197 BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
c30341dc 198 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
b60503ba
MW
199 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
200 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
201 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
202 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
6ecec745 203 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
f9f38e33
HK
204 BUILD_BUG_ON(sizeof(struct nvme_dbbuf) != 64);
205}
206
207static inline unsigned int nvme_dbbuf_size(u32 stride)
208{
209 return ((num_possible_cpus() + 1) * 8 * stride);
210}
211
212static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
213{
214 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
215
216 if (dev->dbbuf_dbs)
217 return 0;
218
219 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
220 &dev->dbbuf_dbs_dma_addr,
221 GFP_KERNEL);
222 if (!dev->dbbuf_dbs)
223 return -ENOMEM;
224 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
225 &dev->dbbuf_eis_dma_addr,
226 GFP_KERNEL);
227 if (!dev->dbbuf_eis) {
228 dma_free_coherent(dev->dev, mem_size,
229 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
230 dev->dbbuf_dbs = NULL;
231 return -ENOMEM;
232 }
233
234 return 0;
235}
236
237static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
238{
239 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
240
241 if (dev->dbbuf_dbs) {
242 dma_free_coherent(dev->dev, mem_size,
243 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
244 dev->dbbuf_dbs = NULL;
245 }
246 if (dev->dbbuf_eis) {
247 dma_free_coherent(dev->dev, mem_size,
248 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
249 dev->dbbuf_eis = NULL;
250 }
251}
252
253static void nvme_dbbuf_init(struct nvme_dev *dev,
254 struct nvme_queue *nvmeq, int qid)
255{
256 if (!dev->dbbuf_dbs || !qid)
257 return;
258
259 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
260 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
261 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
262 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
263}
264
265static void nvme_dbbuf_set(struct nvme_dev *dev)
266{
267 struct nvme_command c;
268
269 if (!dev->dbbuf_dbs)
270 return;
271
272 memset(&c, 0, sizeof(c));
273 c.dbbuf.opcode = nvme_admin_dbbuf;
274 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
275 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
276
277 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
9bdcfb10 278 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
f9f38e33
HK
279 /* Free memory and continue on */
280 nvme_dbbuf_dma_free(dev);
281 }
282}
283
284static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
285{
286 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
287}
288
289/* Update dbbuf and return true if an MMIO is required */
290static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
291 volatile u32 *dbbuf_ei)
292{
293 if (dbbuf_db) {
294 u16 old_value;
295
296 /*
297 * Ensure that the queue is written before updating
298 * the doorbell in memory
299 */
300 wmb();
301
302 old_value = *dbbuf_db;
303 *dbbuf_db = value;
304
305 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value))
306 return false;
307 }
308
309 return true;
b60503ba
MW
310}
311
ac3dd5bd
JA
312/*
313 * Max size of iod being embedded in the request payload
314 */
315#define NVME_INT_PAGES 2
5fd4ce1b 316#define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size)
ac3dd5bd
JA
317
318/*
319 * Will slightly overestimate the number of pages needed. This is OK
320 * as it only leads to a small amount of wasted memory for the lifetime of
321 * the I/O.
322 */
323static int nvme_npages(unsigned size, struct nvme_dev *dev)
324{
5fd4ce1b
CH
325 unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size,
326 dev->ctrl.page_size);
ac3dd5bd
JA
327 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
328}
329
f4800d6d
CH
330static unsigned int nvme_iod_alloc_size(struct nvme_dev *dev,
331 unsigned int size, unsigned int nseg)
ac3dd5bd 332{
f4800d6d
CH
333 return sizeof(__le64 *) * nvme_npages(size, dev) +
334 sizeof(struct scatterlist) * nseg;
335}
ac3dd5bd 336
f4800d6d
CH
337static unsigned int nvme_cmd_size(struct nvme_dev *dev)
338{
339 return sizeof(struct nvme_iod) +
340 nvme_iod_alloc_size(dev, NVME_INT_BYTES(dev), NVME_INT_PAGES);
ac3dd5bd
JA
341}
342
a4aea562
MB
343static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
344 unsigned int hctx_idx)
e85248e5 345{
a4aea562
MB
346 struct nvme_dev *dev = data;
347 struct nvme_queue *nvmeq = dev->queues[0];
348
42483228
KB
349 WARN_ON(hctx_idx != 0);
350 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
351 WARN_ON(nvmeq->tags);
352
a4aea562 353 hctx->driver_data = nvmeq;
42483228 354 nvmeq->tags = &dev->admin_tagset.tags[0];
a4aea562 355 return 0;
e85248e5
MW
356}
357
4af0e21c
KB
358static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
359{
360 struct nvme_queue *nvmeq = hctx->driver_data;
361
362 nvmeq->tags = NULL;
363}
364
d6296d39
CH
365static int nvme_admin_init_request(struct blk_mq_tag_set *set,
366 struct request *req, unsigned int hctx_idx,
367 unsigned int numa_node)
22404274 368{
d6296d39 369 struct nvme_dev *dev = set->driver_data;
f4800d6d 370 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a4aea562
MB
371 struct nvme_queue *nvmeq = dev->queues[0];
372
373 BUG_ON(!nvmeq);
f4800d6d 374 iod->nvmeq = nvmeq;
a4aea562 375 return 0;
22404274
KB
376}
377
a4aea562
MB
378static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
379 unsigned int hctx_idx)
b60503ba 380{
a4aea562 381 struct nvme_dev *dev = data;
42483228 382 struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
a4aea562 383
42483228
KB
384 if (!nvmeq->tags)
385 nvmeq->tags = &dev->tagset.tags[hctx_idx];
b60503ba 386
42483228 387 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
a4aea562
MB
388 hctx->driver_data = nvmeq;
389 return 0;
b60503ba
MW
390}
391
d6296d39
CH
392static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req,
393 unsigned int hctx_idx, unsigned int numa_node)
b60503ba 394{
d6296d39 395 struct nvme_dev *dev = set->driver_data;
f4800d6d 396 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a4aea562
MB
397 struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
398
399 BUG_ON(!nvmeq);
f4800d6d 400 iod->nvmeq = nvmeq;
a4aea562
MB
401 return 0;
402}
403
dca51e78
CH
404static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
405{
406 struct nvme_dev *dev = set->driver_data;
407
408 return blk_mq_pci_map_queues(set, to_pci_dev(dev->dev));
409}
410
b60503ba 411/**
adf68f21 412 * __nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
b60503ba
MW
413 * @nvmeq: The queue to use
414 * @cmd: The command to send
415 *
416 * Safe to use from interrupt context
417 */
e3f879bf
SB
418static void __nvme_submit_cmd(struct nvme_queue *nvmeq,
419 struct nvme_command *cmd)
b60503ba 420{
a4aea562
MB
421 u16 tail = nvmeq->sq_tail;
422
8ffaadf7
JD
423 if (nvmeq->sq_cmds_io)
424 memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd));
425 else
426 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
427
b60503ba
MW
428 if (++tail == nvmeq->q_depth)
429 tail = 0;
f9f38e33
HK
430 if (nvme_dbbuf_update_and_check_event(tail, nvmeq->dbbuf_sq_db,
431 nvmeq->dbbuf_sq_ei))
432 writel(tail, nvmeq->q_db);
b60503ba 433 nvmeq->sq_tail = tail;
b60503ba
MW
434}
435
f4800d6d 436static __le64 **iod_list(struct request *req)
b60503ba 437{
f4800d6d 438 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
f9d03f96 439 return (__le64 **)(iod->sg + blk_rq_nr_phys_segments(req));
b60503ba
MW
440}
441
fc17b653 442static blk_status_t nvme_init_iod(struct request *rq, struct nvme_dev *dev)
ac3dd5bd 443{
f4800d6d 444 struct nvme_iod *iod = blk_mq_rq_to_pdu(rq);
f9d03f96 445 int nseg = blk_rq_nr_phys_segments(rq);
b131c61d 446 unsigned int size = blk_rq_payload_bytes(rq);
ac3dd5bd 447
f4800d6d
CH
448 if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) {
449 iod->sg = kmalloc(nvme_iod_alloc_size(dev, size, nseg), GFP_ATOMIC);
450 if (!iod->sg)
fc17b653 451 return BLK_STS_RESOURCE;
f4800d6d
CH
452 } else {
453 iod->sg = iod->inline_sg;
ac3dd5bd
JA
454 }
455
f4800d6d
CH
456 iod->aborted = 0;
457 iod->npages = -1;
458 iod->nents = 0;
459 iod->length = size;
f80ec966 460
fc17b653 461 return BLK_STS_OK;
ac3dd5bd
JA
462}
463
f4800d6d 464static void nvme_free_iod(struct nvme_dev *dev, struct request *req)
b60503ba 465{
f4800d6d 466 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
5fd4ce1b 467 const int last_prp = dev->ctrl.page_size / 8 - 1;
eca18b23 468 int i;
f4800d6d 469 __le64 **list = iod_list(req);
eca18b23
MW
470 dma_addr_t prp_dma = iod->first_dma;
471
472 if (iod->npages == 0)
473 dma_pool_free(dev->prp_small_pool, list[0], prp_dma);
474 for (i = 0; i < iod->npages; i++) {
475 __le64 *prp_list = list[i];
476 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
477 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
478 prp_dma = next_prp_dma;
479 }
ac3dd5bd 480
f4800d6d
CH
481 if (iod->sg != iod->inline_sg)
482 kfree(iod->sg);
b4ff9c8d
KB
483}
484
52b68d7e 485#ifdef CONFIG_BLK_DEV_INTEGRITY
e1e5e564
KB
486static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
487{
488 if (be32_to_cpu(pi->ref_tag) == v)
489 pi->ref_tag = cpu_to_be32(p);
490}
491
492static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
493{
494 if (be32_to_cpu(pi->ref_tag) == p)
495 pi->ref_tag = cpu_to_be32(v);
496}
497
498/**
499 * nvme_dif_remap - remaps ref tags to bip seed and physical lba
500 *
501 * The virtual start sector is the one that was originally submitted by the
502 * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical
503 * start sector may be different. Remap protection information to match the
504 * physical LBA on writes, and back to the original seed on reads.
505 *
506 * Type 0 and 3 do not have a ref tag, so no remapping required.
507 */
508static void nvme_dif_remap(struct request *req,
509 void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
510{
511 struct nvme_ns *ns = req->rq_disk->private_data;
512 struct bio_integrity_payload *bip;
513 struct t10_pi_tuple *pi;
514 void *p, *pmap;
515 u32 i, nlb, ts, phys, virt;
516
517 if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3)
518 return;
519
520 bip = bio_integrity(req->bio);
521 if (!bip)
522 return;
523
524 pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset;
e1e5e564
KB
525
526 p = pmap;
527 virt = bip_get_seed(bip);
528 phys = nvme_block_nr(ns, blk_rq_pos(req));
529 nlb = (blk_rq_bytes(req) >> ns->lba_shift);
ac6fc48c 530 ts = ns->disk->queue->integrity.tuple_size;
e1e5e564
KB
531
532 for (i = 0; i < nlb; i++, virt++, phys++) {
533 pi = (struct t10_pi_tuple *)p;
534 dif_swap(phys, virt, pi);
535 p += ts;
536 }
537 kunmap_atomic(pmap);
538}
52b68d7e
KB
539#else /* CONFIG_BLK_DEV_INTEGRITY */
540static void nvme_dif_remap(struct request *req,
541 void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
542{
543}
544static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
545{
546}
547static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
548{
549}
52b68d7e
KB
550#endif
551
b131c61d 552static bool nvme_setup_prps(struct nvme_dev *dev, struct request *req)
ff22b54f 553{
f4800d6d 554 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
99802a7a 555 struct dma_pool *pool;
b131c61d 556 int length = blk_rq_payload_bytes(req);
eca18b23 557 struct scatterlist *sg = iod->sg;
ff22b54f
MW
558 int dma_len = sg_dma_len(sg);
559 u64 dma_addr = sg_dma_address(sg);
5fd4ce1b 560 u32 page_size = dev->ctrl.page_size;
f137e0f1 561 int offset = dma_addr & (page_size - 1);
e025344c 562 __le64 *prp_list;
f4800d6d 563 __le64 **list = iod_list(req);
e025344c 564 dma_addr_t prp_dma;
eca18b23 565 int nprps, i;
ff22b54f 566
1d090624 567 length -= (page_size - offset);
ff22b54f 568 if (length <= 0)
69d2b571 569 return true;
ff22b54f 570
1d090624 571 dma_len -= (page_size - offset);
ff22b54f 572 if (dma_len) {
1d090624 573 dma_addr += (page_size - offset);
ff22b54f
MW
574 } else {
575 sg = sg_next(sg);
576 dma_addr = sg_dma_address(sg);
577 dma_len = sg_dma_len(sg);
578 }
579
1d090624 580 if (length <= page_size) {
edd10d33 581 iod->first_dma = dma_addr;
69d2b571 582 return true;
e025344c
SMM
583 }
584
1d090624 585 nprps = DIV_ROUND_UP(length, page_size);
99802a7a
MW
586 if (nprps <= (256 / 8)) {
587 pool = dev->prp_small_pool;
eca18b23 588 iod->npages = 0;
99802a7a
MW
589 } else {
590 pool = dev->prp_page_pool;
eca18b23 591 iod->npages = 1;
99802a7a
MW
592 }
593
69d2b571 594 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
b77954cb 595 if (!prp_list) {
edd10d33 596 iod->first_dma = dma_addr;
eca18b23 597 iod->npages = -1;
69d2b571 598 return false;
b77954cb 599 }
eca18b23
MW
600 list[0] = prp_list;
601 iod->first_dma = prp_dma;
e025344c
SMM
602 i = 0;
603 for (;;) {
1d090624 604 if (i == page_size >> 3) {
e025344c 605 __le64 *old_prp_list = prp_list;
69d2b571 606 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
eca18b23 607 if (!prp_list)
69d2b571 608 return false;
eca18b23 609 list[iod->npages++] = prp_list;
7523d834
MW
610 prp_list[0] = old_prp_list[i - 1];
611 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
612 i = 1;
e025344c
SMM
613 }
614 prp_list[i++] = cpu_to_le64(dma_addr);
1d090624
KB
615 dma_len -= page_size;
616 dma_addr += page_size;
617 length -= page_size;
e025344c
SMM
618 if (length <= 0)
619 break;
620 if (dma_len > 0)
621 continue;
622 BUG_ON(dma_len < 0);
623 sg = sg_next(sg);
624 dma_addr = sg_dma_address(sg);
625 dma_len = sg_dma_len(sg);
ff22b54f
MW
626 }
627
69d2b571 628 return true;
ff22b54f
MW
629}
630
fc17b653 631static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
b131c61d 632 struct nvme_command *cmnd)
d29ec824 633{
f4800d6d 634 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
ba1ca37e
CH
635 struct request_queue *q = req->q;
636 enum dma_data_direction dma_dir = rq_data_dir(req) ?
637 DMA_TO_DEVICE : DMA_FROM_DEVICE;
fc17b653 638 blk_status_t ret = BLK_STS_IOERR;
d29ec824 639
f9d03f96 640 sg_init_table(iod->sg, blk_rq_nr_phys_segments(req));
ba1ca37e
CH
641 iod->nents = blk_rq_map_sg(q, req, iod->sg);
642 if (!iod->nents)
643 goto out;
d29ec824 644
fc17b653 645 ret = BLK_STS_RESOURCE;
2b6b535d
MFO
646 if (!dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, dma_dir,
647 DMA_ATTR_NO_WARN))
ba1ca37e 648 goto out;
d29ec824 649
b131c61d 650 if (!nvme_setup_prps(dev, req))
ba1ca37e 651 goto out_unmap;
0e5e4f0e 652
fc17b653 653 ret = BLK_STS_IOERR;
ba1ca37e
CH
654 if (blk_integrity_rq(req)) {
655 if (blk_rq_count_integrity_sg(q, req->bio) != 1)
656 goto out_unmap;
0e5e4f0e 657
bf684057
CH
658 sg_init_table(&iod->meta_sg, 1);
659 if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1)
ba1ca37e 660 goto out_unmap;
0e5e4f0e 661
ba1ca37e
CH
662 if (rq_data_dir(req))
663 nvme_dif_remap(req, nvme_dif_prep);
0e5e4f0e 664
bf684057 665 if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir))
ba1ca37e 666 goto out_unmap;
d29ec824 667 }
00df5cb4 668
eb793e2c
CH
669 cmnd->rw.dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
670 cmnd->rw.dptr.prp2 = cpu_to_le64(iod->first_dma);
ba1ca37e 671 if (blk_integrity_rq(req))
bf684057 672 cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg));
fc17b653 673 return BLK_STS_OK;
00df5cb4 674
ba1ca37e
CH
675out_unmap:
676 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
677out:
678 return ret;
00df5cb4
MW
679}
680
f4800d6d 681static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
b60503ba 682{
f4800d6d 683 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
d4f6c3ab
CH
684 enum dma_data_direction dma_dir = rq_data_dir(req) ?
685 DMA_TO_DEVICE : DMA_FROM_DEVICE;
686
687 if (iod->nents) {
688 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
689 if (blk_integrity_rq(req)) {
690 if (!rq_data_dir(req))
691 nvme_dif_remap(req, nvme_dif_complete);
bf684057 692 dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir);
e1e5e564 693 }
e19b127f 694 }
e1e5e564 695
f9d03f96 696 nvme_cleanup_cmd(req);
f4800d6d 697 nvme_free_iod(dev, req);
d4f6c3ab 698}
b60503ba 699
d29ec824
CH
700/*
701 * NOTE: ns is NULL when called on the admin queue.
702 */
fc17b653 703static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
a4aea562 704 const struct blk_mq_queue_data *bd)
edd10d33 705{
a4aea562
MB
706 struct nvme_ns *ns = hctx->queue->queuedata;
707 struct nvme_queue *nvmeq = hctx->driver_data;
d29ec824 708 struct nvme_dev *dev = nvmeq->dev;
a4aea562 709 struct request *req = bd->rq;
ba1ca37e 710 struct nvme_command cmnd;
fc17b653 711 blk_status_t ret = BLK_STS_OK;
edd10d33 712
e1e5e564
KB
713 /*
714 * If formated with metadata, require the block layer provide a buffer
715 * unless this namespace is formated such that the metadata can be
716 * stripped/generated by the controller with PRACT=1.
717 */
d29ec824 718 if (ns && ns->ms && !blk_integrity_rq(req)) {
71feb364 719 if (!(ns->pi_type && ns->ms == 8) &&
fc17b653
CH
720 !blk_rq_is_passthrough(req))
721 return BLK_STS_NOTSUPP;
e1e5e564
KB
722 }
723
f9d03f96 724 ret = nvme_setup_cmd(ns, req, &cmnd);
fc17b653 725 if (ret)
f4800d6d 726 return ret;
a4aea562 727
b131c61d 728 ret = nvme_init_iod(req, dev);
fc17b653 729 if (ret)
f9d03f96 730 goto out_free_cmd;
a4aea562 731
fc17b653 732 if (blk_rq_nr_phys_segments(req)) {
b131c61d 733 ret = nvme_map_data(dev, req, &cmnd);
fc17b653
CH
734 if (ret)
735 goto out_cleanup_iod;
736 }
a4aea562 737
aae239e1 738 blk_mq_start_request(req);
a4aea562 739
ba1ca37e 740 spin_lock_irq(&nvmeq->q_lock);
ae1fba20 741 if (unlikely(nvmeq->cq_vector < 0)) {
fc17b653 742 ret = BLK_STS_IOERR;
ae1fba20 743 spin_unlock_irq(&nvmeq->q_lock);
f9d03f96 744 goto out_cleanup_iod;
ae1fba20 745 }
ba1ca37e 746 __nvme_submit_cmd(nvmeq, &cmnd);
a4aea562
MB
747 nvme_process_cq(nvmeq);
748 spin_unlock_irq(&nvmeq->q_lock);
fc17b653 749 return BLK_STS_OK;
f9d03f96 750out_cleanup_iod:
f4800d6d 751 nvme_free_iod(dev, req);
f9d03f96
CH
752out_free_cmd:
753 nvme_cleanup_cmd(req);
ba1ca37e 754 return ret;
b60503ba 755}
e1e5e564 756
77f02a7a 757static void nvme_pci_complete_rq(struct request *req)
eee417b0 758{
f4800d6d 759 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a4aea562 760
77f02a7a
CH
761 nvme_unmap_data(iod->nvmeq->dev, req);
762 nvme_complete_rq(req);
b60503ba
MW
763}
764
d783e0bd
MR
765/* We read the CQE phase first to check if the rest of the entry is valid */
766static inline bool nvme_cqe_valid(struct nvme_queue *nvmeq, u16 head,
767 u16 phase)
768{
769 return (le16_to_cpu(nvmeq->cqes[head].status) & 1) == phase;
770}
771
a0fa9647 772static void __nvme_process_cq(struct nvme_queue *nvmeq, unsigned int *tag)
b60503ba 773{
82123460 774 u16 head, phase;
b60503ba 775
b60503ba 776 head = nvmeq->cq_head;
82123460 777 phase = nvmeq->cq_phase;
b60503ba 778
d783e0bd 779 while (nvme_cqe_valid(nvmeq, head, phase)) {
b60503ba 780 struct nvme_completion cqe = nvmeq->cqes[head];
eee417b0 781 struct request *req;
adf68f21 782
b60503ba
MW
783 if (++head == nvmeq->q_depth) {
784 head = 0;
82123460 785 phase = !phase;
b60503ba 786 }
adf68f21 787
a0fa9647
JA
788 if (tag && *tag == cqe.command_id)
789 *tag = -1;
adf68f21 790
aae239e1 791 if (unlikely(cqe.command_id >= nvmeq->q_depth)) {
1b3c47c1 792 dev_warn(nvmeq->dev->ctrl.device,
aae239e1
CH
793 "invalid id %d completed on queue %d\n",
794 cqe.command_id, le16_to_cpu(cqe.sq_id));
795 continue;
796 }
797
adf68f21
CH
798 /*
799 * AEN requests are special as they don't time out and can
800 * survive any kind of queue freeze and often don't respond to
801 * aborts. We don't even bother to allocate a struct request
802 * for them but rather special case them here.
803 */
804 if (unlikely(nvmeq->qid == 0 &&
805 cqe.command_id >= NVME_AQ_BLKMQ_DEPTH)) {
7bf58533
CH
806 nvme_complete_async_event(&nvmeq->dev->ctrl,
807 cqe.status, &cqe.result);
adf68f21
CH
808 continue;
809 }
810
eee417b0 811 req = blk_mq_tag_to_rq(*nvmeq->tags, cqe.command_id);
27fa9bc5 812 nvme_end_request(req, cqe.status, cqe.result);
b60503ba
MW
813 }
814
82123460 815 if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
a0fa9647 816 return;
b60503ba 817
604e8c8d 818 if (likely(nvmeq->cq_vector >= 0))
f9f38e33
HK
819 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
820 nvmeq->dbbuf_cq_ei))
821 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
b60503ba 822 nvmeq->cq_head = head;
82123460 823 nvmeq->cq_phase = phase;
b60503ba 824
e9539f47 825 nvmeq->cqe_seen = 1;
a0fa9647
JA
826}
827
828static void nvme_process_cq(struct nvme_queue *nvmeq)
829{
830 __nvme_process_cq(nvmeq, NULL);
b60503ba
MW
831}
832
833static irqreturn_t nvme_irq(int irq, void *data)
58ffacb5
MW
834{
835 irqreturn_t result;
836 struct nvme_queue *nvmeq = data;
837 spin_lock(&nvmeq->q_lock);
e9539f47
MW
838 nvme_process_cq(nvmeq);
839 result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE;
840 nvmeq->cqe_seen = 0;
58ffacb5
MW
841 spin_unlock(&nvmeq->q_lock);
842 return result;
843}
844
845static irqreturn_t nvme_irq_check(int irq, void *data)
846{
847 struct nvme_queue *nvmeq = data;
d783e0bd
MR
848 if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase))
849 return IRQ_WAKE_THREAD;
850 return IRQ_NONE;
58ffacb5
MW
851}
852
7776db1c 853static int __nvme_poll(struct nvme_queue *nvmeq, unsigned int tag)
a0fa9647 854{
d783e0bd 855 if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase)) {
a0fa9647
JA
856 spin_lock_irq(&nvmeq->q_lock);
857 __nvme_process_cq(nvmeq, &tag);
858 spin_unlock_irq(&nvmeq->q_lock);
859
860 if (tag == -1)
861 return 1;
862 }
863
864 return 0;
865}
866
7776db1c
KB
867static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag)
868{
869 struct nvme_queue *nvmeq = hctx->driver_data;
870
871 return __nvme_poll(nvmeq, tag);
872}
873
f866fc42 874static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl, int aer_idx)
b60503ba 875{
f866fc42 876 struct nvme_dev *dev = to_nvme_dev(ctrl);
9396dec9 877 struct nvme_queue *nvmeq = dev->queues[0];
a4aea562 878 struct nvme_command c;
b60503ba 879
a4aea562
MB
880 memset(&c, 0, sizeof(c));
881 c.common.opcode = nvme_admin_async_event;
f866fc42 882 c.common.command_id = NVME_AQ_BLKMQ_DEPTH + aer_idx;
3c0cf138 883
9396dec9 884 spin_lock_irq(&nvmeq->q_lock);
f866fc42 885 __nvme_submit_cmd(nvmeq, &c);
9396dec9 886 spin_unlock_irq(&nvmeq->q_lock);
f705f837
CH
887}
888
b60503ba 889static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
f705f837 890{
b60503ba
MW
891 struct nvme_command c;
892
893 memset(&c, 0, sizeof(c));
894 c.delete_queue.opcode = opcode;
895 c.delete_queue.qid = cpu_to_le16(id);
896
1c63dc66 897 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW
898}
899
b60503ba
MW
900static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
901 struct nvme_queue *nvmeq)
902{
b60503ba
MW
903 struct nvme_command c;
904 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
905
d29ec824
CH
906 /*
907 * Note: we (ab)use the fact the the prp fields survive if no data
908 * is attached to the request.
909 */
b60503ba
MW
910 memset(&c, 0, sizeof(c));
911 c.create_cq.opcode = nvme_admin_create_cq;
912 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
913 c.create_cq.cqid = cpu_to_le16(qid);
914 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
915 c.create_cq.cq_flags = cpu_to_le16(flags);
916 c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
917
1c63dc66 918 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW
919}
920
921static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
922 struct nvme_queue *nvmeq)
923{
b60503ba 924 struct nvme_command c;
81c1cd98 925 int flags = NVME_QUEUE_PHYS_CONTIG;
b60503ba 926
d29ec824
CH
927 /*
928 * Note: we (ab)use the fact the the prp fields survive if no data
929 * is attached to the request.
930 */
b60503ba
MW
931 memset(&c, 0, sizeof(c));
932 c.create_sq.opcode = nvme_admin_create_sq;
933 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
934 c.create_sq.sqid = cpu_to_le16(qid);
935 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
936 c.create_sq.sq_flags = cpu_to_le16(flags);
937 c.create_sq.cqid = cpu_to_le16(qid);
938
1c63dc66 939 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW
940}
941
942static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
943{
944 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
945}
946
947static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
948{
949 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
950}
951
2a842aca 952static void abort_endio(struct request *req, blk_status_t error)
bc5fc7e4 953{
f4800d6d
CH
954 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
955 struct nvme_queue *nvmeq = iod->nvmeq;
e44ac588 956
27fa9bc5
CH
957 dev_warn(nvmeq->dev->ctrl.device,
958 "Abort status: 0x%x", nvme_req(req)->status);
e7a2a87d 959 atomic_inc(&nvmeq->dev->ctrl.abort_limit);
e7a2a87d 960 blk_mq_free_request(req);
bc5fc7e4
MW
961}
962
31c7c7d2 963static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
c30341dc 964{
f4800d6d
CH
965 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
966 struct nvme_queue *nvmeq = iod->nvmeq;
c30341dc 967 struct nvme_dev *dev = nvmeq->dev;
a4aea562 968 struct request *abort_req;
a4aea562 969 struct nvme_command cmd;
c30341dc 970
7776db1c
KB
971 /*
972 * Did we miss an interrupt?
973 */
974 if (__nvme_poll(nvmeq, req->tag)) {
975 dev_warn(dev->ctrl.device,
976 "I/O %d QID %d timeout, completion polled\n",
977 req->tag, nvmeq->qid);
978 return BLK_EH_HANDLED;
979 }
980
31c7c7d2 981 /*
fd634f41
CH
982 * Shutdown immediately if controller times out while starting. The
983 * reset work will see the pci device disabled when it gets the forced
984 * cancellation error. All outstanding requests are completed on
985 * shutdown, so we return BLK_EH_HANDLED.
986 */
bb8d261e 987 if (dev->ctrl.state == NVME_CTRL_RESETTING) {
1b3c47c1 988 dev_warn(dev->ctrl.device,
fd634f41
CH
989 "I/O %d QID %d timeout, disable controller\n",
990 req->tag, nvmeq->qid);
a5cdb68c 991 nvme_dev_disable(dev, false);
27fa9bc5 992 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
fd634f41 993 return BLK_EH_HANDLED;
c30341dc
KB
994 }
995
fd634f41
CH
996 /*
997 * Shutdown the controller immediately and schedule a reset if the
998 * command was already aborted once before and still hasn't been
999 * returned to the driver, or if this is the admin queue.
31c7c7d2 1000 */
f4800d6d 1001 if (!nvmeq->qid || iod->aborted) {
1b3c47c1 1002 dev_warn(dev->ctrl.device,
e1569a16
KB
1003 "I/O %d QID %d timeout, reset controller\n",
1004 req->tag, nvmeq->qid);
a5cdb68c 1005 nvme_dev_disable(dev, false);
c5f6ce97 1006 nvme_reset(dev);
c30341dc 1007
e1569a16
KB
1008 /*
1009 * Mark the request as handled, since the inline shutdown
1010 * forces all outstanding requests to complete.
1011 */
27fa9bc5 1012 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
e1569a16 1013 return BLK_EH_HANDLED;
c30341dc 1014 }
c30341dc 1015
e7a2a87d 1016 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
6bf25d16 1017 atomic_inc(&dev->ctrl.abort_limit);
31c7c7d2 1018 return BLK_EH_RESET_TIMER;
6bf25d16 1019 }
7bf7d778 1020 iod->aborted = 1;
a4aea562 1021
c30341dc
KB
1022 memset(&cmd, 0, sizeof(cmd));
1023 cmd.abort.opcode = nvme_admin_abort_cmd;
a4aea562 1024 cmd.abort.cid = req->tag;
c30341dc 1025 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
c30341dc 1026
1b3c47c1
SG
1027 dev_warn(nvmeq->dev->ctrl.device,
1028 "I/O %d QID %d timeout, aborting\n",
1029 req->tag, nvmeq->qid);
e7a2a87d
CH
1030
1031 abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
eb71f435 1032 BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
e7a2a87d
CH
1033 if (IS_ERR(abort_req)) {
1034 atomic_inc(&dev->ctrl.abort_limit);
1035 return BLK_EH_RESET_TIMER;
1036 }
1037
1038 abort_req->timeout = ADMIN_TIMEOUT;
1039 abort_req->end_io_data = NULL;
1040 blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio);
c30341dc 1041
31c7c7d2
CH
1042 /*
1043 * The aborted req will be completed on receiving the abort req.
1044 * We enable the timer again. If hit twice, it'll cause a device reset,
1045 * as the device then is in a faulty state.
1046 */
1047 return BLK_EH_RESET_TIMER;
c30341dc
KB
1048}
1049
a4aea562
MB
1050static void nvme_free_queue(struct nvme_queue *nvmeq)
1051{
9e866774
MW
1052 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1053 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
8ffaadf7
JD
1054 if (nvmeq->sq_cmds)
1055 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
9e866774
MW
1056 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1057 kfree(nvmeq);
1058}
1059
a1a5ef99 1060static void nvme_free_queues(struct nvme_dev *dev, int lowest)
22404274
KB
1061{
1062 int i;
1063
a1a5ef99 1064 for (i = dev->queue_count - 1; i >= lowest; i--) {
a4aea562 1065 struct nvme_queue *nvmeq = dev->queues[i];
22404274 1066 dev->queue_count--;
a4aea562 1067 dev->queues[i] = NULL;
f435c282 1068 nvme_free_queue(nvmeq);
121c7ad4 1069 }
22404274
KB
1070}
1071
4d115420
KB
1072/**
1073 * nvme_suspend_queue - put queue into suspended state
1074 * @nvmeq - queue to suspend
4d115420
KB
1075 */
1076static int nvme_suspend_queue(struct nvme_queue *nvmeq)
b60503ba 1077{
2b25d981 1078 int vector;
b60503ba 1079
a09115b2 1080 spin_lock_irq(&nvmeq->q_lock);
2b25d981
KB
1081 if (nvmeq->cq_vector == -1) {
1082 spin_unlock_irq(&nvmeq->q_lock);
1083 return 1;
1084 }
0ff199cb 1085 vector = nvmeq->cq_vector;
42f61420 1086 nvmeq->dev->online_queues--;
2b25d981 1087 nvmeq->cq_vector = -1;
a09115b2
MW
1088 spin_unlock_irq(&nvmeq->q_lock);
1089
1c63dc66 1090 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
25646264 1091 blk_mq_stop_hw_queues(nvmeq->dev->ctrl.admin_q);
6df3dbc8 1092
0ff199cb 1093 pci_free_irq(to_pci_dev(nvmeq->dev->dev), vector, nvmeq);
b60503ba 1094
4d115420
KB
1095 return 0;
1096}
b60503ba 1097
a5cdb68c 1098static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
4d115420 1099{
a5cdb68c 1100 struct nvme_queue *nvmeq = dev->queues[0];
4d115420
KB
1101
1102 if (!nvmeq)
1103 return;
1104 if (nvme_suspend_queue(nvmeq))
1105 return;
1106
a5cdb68c
KB
1107 if (shutdown)
1108 nvme_shutdown_ctrl(&dev->ctrl);
1109 else
1110 nvme_disable_ctrl(&dev->ctrl, lo_hi_readq(
1111 dev->bar + NVME_REG_CAP));
07836e65
KB
1112
1113 spin_lock_irq(&nvmeq->q_lock);
1114 nvme_process_cq(nvmeq);
1115 spin_unlock_irq(&nvmeq->q_lock);
b60503ba
MW
1116}
1117
8ffaadf7
JD
1118static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1119 int entry_size)
1120{
1121 int q_depth = dev->q_depth;
5fd4ce1b
CH
1122 unsigned q_size_aligned = roundup(q_depth * entry_size,
1123 dev->ctrl.page_size);
8ffaadf7
JD
1124
1125 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
c45f5c99 1126 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
5fd4ce1b 1127 mem_per_q = round_down(mem_per_q, dev->ctrl.page_size);
c45f5c99 1128 q_depth = div_u64(mem_per_q, entry_size);
8ffaadf7
JD
1129
1130 /*
1131 * Ensure the reduced q_depth is above some threshold where it
1132 * would be better to map queues in system memory with the
1133 * original depth
1134 */
1135 if (q_depth < 64)
1136 return -ENOMEM;
1137 }
1138
1139 return q_depth;
1140}
1141
1142static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1143 int qid, int depth)
1144{
1145 if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz)) {
5fd4ce1b
CH
1146 unsigned offset = (qid - 1) * roundup(SQ_SIZE(depth),
1147 dev->ctrl.page_size);
8ffaadf7
JD
1148 nvmeq->sq_dma_addr = dev->cmb_dma_addr + offset;
1149 nvmeq->sq_cmds_io = dev->cmb + offset;
1150 } else {
1151 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
1152 &nvmeq->sq_dma_addr, GFP_KERNEL);
1153 if (!nvmeq->sq_cmds)
1154 return -ENOMEM;
1155 }
1156
1157 return 0;
1158}
1159
b60503ba 1160static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
d3af3ecd 1161 int depth, int node)
b60503ba 1162{
d3af3ecd
SL
1163 struct nvme_queue *nvmeq = kzalloc_node(sizeof(*nvmeq), GFP_KERNEL,
1164 node);
b60503ba
MW
1165 if (!nvmeq)
1166 return NULL;
1167
e75ec752 1168 nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth),
4d51abf9 1169 &nvmeq->cq_dma_addr, GFP_KERNEL);
b60503ba
MW
1170 if (!nvmeq->cqes)
1171 goto free_nvmeq;
b60503ba 1172
8ffaadf7 1173 if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth))
b60503ba
MW
1174 goto free_cqdma;
1175
e75ec752 1176 nvmeq->q_dmadev = dev->dev;
091b6092 1177 nvmeq->dev = dev;
b60503ba
MW
1178 spin_lock_init(&nvmeq->q_lock);
1179 nvmeq->cq_head = 0;
82123460 1180 nvmeq->cq_phase = 1;
b80d5ccc 1181 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
b60503ba 1182 nvmeq->q_depth = depth;
c30341dc 1183 nvmeq->qid = qid;
758dd7fd 1184 nvmeq->cq_vector = -1;
a4aea562 1185 dev->queues[qid] = nvmeq;
36a7e993
JD
1186 dev->queue_count++;
1187
b60503ba
MW
1188 return nvmeq;
1189
1190 free_cqdma:
e75ec752 1191 dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes,
b60503ba
MW
1192 nvmeq->cq_dma_addr);
1193 free_nvmeq:
1194 kfree(nvmeq);
1195 return NULL;
1196}
1197
dca51e78 1198static int queue_request_irq(struct nvme_queue *nvmeq)
3001082c 1199{
0ff199cb
CH
1200 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1201 int nr = nvmeq->dev->ctrl.instance;
1202
1203 if (use_threaded_interrupts) {
1204 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1205 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1206 } else {
1207 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1208 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1209 }
3001082c
MW
1210}
1211
22404274 1212static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
b60503ba 1213{
22404274 1214 struct nvme_dev *dev = nvmeq->dev;
b60503ba 1215
7be50e93 1216 spin_lock_irq(&nvmeq->q_lock);
22404274
KB
1217 nvmeq->sq_tail = 0;
1218 nvmeq->cq_head = 0;
1219 nvmeq->cq_phase = 1;
b80d5ccc 1220 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
22404274 1221 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
f9f38e33 1222 nvme_dbbuf_init(dev, nvmeq, qid);
42f61420 1223 dev->online_queues++;
7be50e93 1224 spin_unlock_irq(&nvmeq->q_lock);
22404274
KB
1225}
1226
1227static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1228{
1229 struct nvme_dev *dev = nvmeq->dev;
1230 int result;
3f85d50b 1231
2b25d981 1232 nvmeq->cq_vector = qid - 1;
b60503ba
MW
1233 result = adapter_alloc_cq(dev, qid, nvmeq);
1234 if (result < 0)
22404274 1235 return result;
b60503ba
MW
1236
1237 result = adapter_alloc_sq(dev, qid, nvmeq);
1238 if (result < 0)
1239 goto release_cq;
1240
dca51e78 1241 result = queue_request_irq(nvmeq);
b60503ba
MW
1242 if (result < 0)
1243 goto release_sq;
1244
22404274 1245 nvme_init_queue(nvmeq, qid);
22404274 1246 return result;
b60503ba
MW
1247
1248 release_sq:
1249 adapter_delete_sq(dev, qid);
1250 release_cq:
1251 adapter_delete_cq(dev, qid);
22404274 1252 return result;
b60503ba
MW
1253}
1254
f363b089 1255static const struct blk_mq_ops nvme_mq_admin_ops = {
d29ec824 1256 .queue_rq = nvme_queue_rq,
77f02a7a 1257 .complete = nvme_pci_complete_rq,
a4aea562 1258 .init_hctx = nvme_admin_init_hctx,
4af0e21c 1259 .exit_hctx = nvme_admin_exit_hctx,
a4aea562
MB
1260 .init_request = nvme_admin_init_request,
1261 .timeout = nvme_timeout,
1262};
1263
f363b089 1264static const struct blk_mq_ops nvme_mq_ops = {
a4aea562 1265 .queue_rq = nvme_queue_rq,
77f02a7a 1266 .complete = nvme_pci_complete_rq,
a4aea562
MB
1267 .init_hctx = nvme_init_hctx,
1268 .init_request = nvme_init_request,
dca51e78 1269 .map_queues = nvme_pci_map_queues,
a4aea562 1270 .timeout = nvme_timeout,
a0fa9647 1271 .poll = nvme_poll,
a4aea562
MB
1272};
1273
ea191d2f
KB
1274static void nvme_dev_remove_admin(struct nvme_dev *dev)
1275{
1c63dc66 1276 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
69d9a99c
KB
1277 /*
1278 * If the controller was reset during removal, it's possible
1279 * user requests may be waiting on a stopped queue. Start the
1280 * queue to flush these to completion.
1281 */
1282 blk_mq_start_stopped_hw_queues(dev->ctrl.admin_q, true);
1c63dc66 1283 blk_cleanup_queue(dev->ctrl.admin_q);
ea191d2f
KB
1284 blk_mq_free_tag_set(&dev->admin_tagset);
1285 }
1286}
1287
a4aea562
MB
1288static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1289{
1c63dc66 1290 if (!dev->ctrl.admin_q) {
a4aea562
MB
1291 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1292 dev->admin_tagset.nr_hw_queues = 1;
e3e9d50c
KB
1293
1294 /*
1295 * Subtract one to leave an empty queue entry for 'Full Queue'
1296 * condition. See NVM-Express 1.2 specification, section 4.1.2.
1297 */
1298 dev->admin_tagset.queue_depth = NVME_AQ_BLKMQ_DEPTH - 1;
a4aea562 1299 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
e75ec752 1300 dev->admin_tagset.numa_node = dev_to_node(dev->dev);
ac3dd5bd 1301 dev->admin_tagset.cmd_size = nvme_cmd_size(dev);
d3484991 1302 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED;
a4aea562
MB
1303 dev->admin_tagset.driver_data = dev;
1304
1305 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1306 return -ENOMEM;
1307
1c63dc66
CH
1308 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1309 if (IS_ERR(dev->ctrl.admin_q)) {
a4aea562
MB
1310 blk_mq_free_tag_set(&dev->admin_tagset);
1311 return -ENOMEM;
1312 }
1c63dc66 1313 if (!blk_get_queue(dev->ctrl.admin_q)) {
ea191d2f 1314 nvme_dev_remove_admin(dev);
1c63dc66 1315 dev->ctrl.admin_q = NULL;
ea191d2f
KB
1316 return -ENODEV;
1317 }
0fb59cbc 1318 } else
25646264 1319 blk_mq_start_stopped_hw_queues(dev->ctrl.admin_q, true);
a4aea562
MB
1320
1321 return 0;
1322}
1323
97f6ef64
XY
1324static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1325{
1326 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1327}
1328
1329static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1330{
1331 struct pci_dev *pdev = to_pci_dev(dev->dev);
1332
1333 if (size <= dev->bar_mapped_size)
1334 return 0;
1335 if (size > pci_resource_len(pdev, 0))
1336 return -ENOMEM;
1337 if (dev->bar)
1338 iounmap(dev->bar);
1339 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1340 if (!dev->bar) {
1341 dev->bar_mapped_size = 0;
1342 return -ENOMEM;
1343 }
1344 dev->bar_mapped_size = size;
1345 dev->dbs = dev->bar + NVME_REG_DBS;
1346
1347 return 0;
1348}
1349
8d85fce7 1350static int nvme_configure_admin_queue(struct nvme_dev *dev)
b60503ba 1351{
ba47e386 1352 int result;
b60503ba 1353 u32 aqa;
7a67cbea 1354 u64 cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
b60503ba
MW
1355 struct nvme_queue *nvmeq;
1356
97f6ef64
XY
1357 result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1358 if (result < 0)
1359 return result;
1360
8ef2074d 1361 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
dfbac8c7
KB
1362 NVME_CAP_NSSRC(cap) : 0;
1363
7a67cbea
CH
1364 if (dev->subsystem &&
1365 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1366 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
dfbac8c7 1367
5fd4ce1b 1368 result = nvme_disable_ctrl(&dev->ctrl, cap);
ba47e386
MW
1369 if (result < 0)
1370 return result;
b60503ba 1371
a4aea562 1372 nvmeq = dev->queues[0];
cd638946 1373 if (!nvmeq) {
d3af3ecd
SL
1374 nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH,
1375 dev_to_node(dev->dev));
cd638946
KB
1376 if (!nvmeq)
1377 return -ENOMEM;
cd638946 1378 }
b60503ba
MW
1379
1380 aqa = nvmeq->q_depth - 1;
1381 aqa |= aqa << 16;
1382
7a67cbea
CH
1383 writel(aqa, dev->bar + NVME_REG_AQA);
1384 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1385 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
b60503ba 1386
5fd4ce1b 1387 result = nvme_enable_ctrl(&dev->ctrl, cap);
025c557a 1388 if (result)
d4875622 1389 return result;
a4aea562 1390
2b25d981 1391 nvmeq->cq_vector = 0;
dca51e78 1392 result = queue_request_irq(nvmeq);
758dd7fd
JD
1393 if (result) {
1394 nvmeq->cq_vector = -1;
d4875622 1395 return result;
758dd7fd 1396 }
025c557a 1397
b60503ba
MW
1398 return result;
1399}
1400
c875a709
GP
1401static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1402{
1403
1404 /* If true, indicates loss of adapter communication, possibly by a
1405 * NVMe Subsystem reset.
1406 */
1407 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1408
1409 /* If there is a reset ongoing, we shouldn't reset again. */
82b057ca 1410 if (dev->ctrl.state == NVME_CTRL_RESETTING)
c875a709
GP
1411 return false;
1412
1413 /* We shouldn't reset unless the controller is on fatal error state
1414 * _or_ if we lost the communication with it.
1415 */
1416 if (!(csts & NVME_CSTS_CFS) && !nssro)
1417 return false;
1418
1419 /* If PCI error recovery process is happening, we cannot reset or
1420 * the recovery mechanism will surely fail.
1421 */
1422 if (pci_channel_offline(to_pci_dev(dev->dev)))
1423 return false;
1424
1425 return true;
1426}
1427
d2a61918
AL
1428static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1429{
1430 /* Read a config register to help see what died. */
1431 u16 pci_status;
1432 int result;
1433
1434 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1435 &pci_status);
1436 if (result == PCIBIOS_SUCCESSFUL)
9bdcfb10 1437 dev_warn(dev->ctrl.device,
d2a61918
AL
1438 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1439 csts, pci_status);
1440 else
9bdcfb10 1441 dev_warn(dev->ctrl.device,
d2a61918
AL
1442 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1443 csts, result);
1444}
1445
2d55cd5f 1446static void nvme_watchdog_timer(unsigned long data)
1fa6aead 1447{
2d55cd5f
CH
1448 struct nvme_dev *dev = (struct nvme_dev *)data;
1449 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1fa6aead 1450
c875a709
GP
1451 /* Skip controllers under certain specific conditions. */
1452 if (nvme_should_reset(dev, csts)) {
c5f6ce97 1453 if (!nvme_reset(dev))
d2a61918 1454 nvme_warn_reset(dev, csts);
2d55cd5f 1455 return;
1fa6aead 1456 }
2d55cd5f
CH
1457
1458 mod_timer(&dev->watchdog_timer, round_jiffies(jiffies + HZ));
1fa6aead
MW
1459}
1460
749941f2 1461static int nvme_create_io_queues(struct nvme_dev *dev)
42f61420 1462{
949928c1 1463 unsigned i, max;
749941f2 1464 int ret = 0;
42f61420 1465
749941f2 1466 for (i = dev->queue_count; i <= dev->max_qid; i++) {
d3af3ecd
SL
1467 /* vector == qid - 1, match nvme_create_queue */
1468 if (!nvme_alloc_queue(dev, i, dev->q_depth,
1469 pci_irq_get_node(to_pci_dev(dev->dev), i - 1))) {
749941f2 1470 ret = -ENOMEM;
42f61420 1471 break;
749941f2
CH
1472 }
1473 }
42f61420 1474
949928c1
KB
1475 max = min(dev->max_qid, dev->queue_count - 1);
1476 for (i = dev->online_queues; i <= max; i++) {
749941f2 1477 ret = nvme_create_queue(dev->queues[i], i);
d4875622 1478 if (ret)
42f61420 1479 break;
27e8166c 1480 }
749941f2
CH
1481
1482 /*
1483 * Ignore failing Create SQ/CQ commands, we can continue with less
1484 * than the desired aount of queues, and even a controller without
1485 * I/O queues an still be used to issue admin commands. This might
1486 * be useful to upgrade a buggy firmware for example.
1487 */
1488 return ret >= 0 ? 0 : ret;
b60503ba
MW
1489}
1490
202021c1
SB
1491static ssize_t nvme_cmb_show(struct device *dev,
1492 struct device_attribute *attr,
1493 char *buf)
1494{
1495 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
1496
c965809c 1497 return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n",
202021c1
SB
1498 ndev->cmbloc, ndev->cmbsz);
1499}
1500static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL);
1501
8ffaadf7
JD
1502static void __iomem *nvme_map_cmb(struct nvme_dev *dev)
1503{
1504 u64 szu, size, offset;
8ffaadf7
JD
1505 resource_size_t bar_size;
1506 struct pci_dev *pdev = to_pci_dev(dev->dev);
1507 void __iomem *cmb;
1508 dma_addr_t dma_addr;
1509
7a67cbea 1510 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
8ffaadf7
JD
1511 if (!(NVME_CMB_SZ(dev->cmbsz)))
1512 return NULL;
202021c1 1513 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
8ffaadf7 1514
202021c1
SB
1515 if (!use_cmb_sqes)
1516 return NULL;
8ffaadf7
JD
1517
1518 szu = (u64)1 << (12 + 4 * NVME_CMB_SZU(dev->cmbsz));
1519 size = szu * NVME_CMB_SZ(dev->cmbsz);
202021c1
SB
1520 offset = szu * NVME_CMB_OFST(dev->cmbloc);
1521 bar_size = pci_resource_len(pdev, NVME_CMB_BIR(dev->cmbloc));
8ffaadf7
JD
1522
1523 if (offset > bar_size)
1524 return NULL;
1525
1526 /*
1527 * Controllers may support a CMB size larger than their BAR,
1528 * for example, due to being behind a bridge. Reduce the CMB to
1529 * the reported size of the BAR
1530 */
1531 if (size > bar_size - offset)
1532 size = bar_size - offset;
1533
202021c1 1534 dma_addr = pci_resource_start(pdev, NVME_CMB_BIR(dev->cmbloc)) + offset;
8ffaadf7
JD
1535 cmb = ioremap_wc(dma_addr, size);
1536 if (!cmb)
1537 return NULL;
1538
1539 dev->cmb_dma_addr = dma_addr;
1540 dev->cmb_size = size;
1541 return cmb;
1542}
1543
1544static inline void nvme_release_cmb(struct nvme_dev *dev)
1545{
1546 if (dev->cmb) {
1547 iounmap(dev->cmb);
1548 dev->cmb = NULL;
f63572df
JD
1549 if (dev->cmbsz) {
1550 sysfs_remove_file_from_group(&dev->ctrl.device->kobj,
1551 &dev_attr_cmb.attr, NULL);
1552 dev->cmbsz = 0;
1553 }
8ffaadf7
JD
1554 }
1555}
1556
87ad72a5
CH
1557static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1558{
1559 size_t len = dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs);
1560 struct nvme_command c;
1561 u64 dma_addr;
1562 int ret;
1563
1564 dma_addr = dma_map_single(dev->dev, dev->host_mem_descs, len,
1565 DMA_TO_DEVICE);
1566 if (dma_mapping_error(dev->dev, dma_addr))
1567 return -ENOMEM;
1568
1569 memset(&c, 0, sizeof(c));
1570 c.features.opcode = nvme_admin_set_features;
1571 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1572 c.features.dword11 = cpu_to_le32(bits);
1573 c.features.dword12 = cpu_to_le32(dev->host_mem_size >>
1574 ilog2(dev->ctrl.page_size));
1575 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr));
1576 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr));
1577 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs);
1578
1579 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1580 if (ret) {
1581 dev_warn(dev->ctrl.device,
1582 "failed to set host mem (err %d, flags %#x).\n",
1583 ret, bits);
1584 }
1585 dma_unmap_single(dev->dev, dma_addr, len, DMA_TO_DEVICE);
1586 return ret;
1587}
1588
1589static void nvme_free_host_mem(struct nvme_dev *dev)
1590{
1591 int i;
1592
1593 for (i = 0; i < dev->nr_host_mem_descs; i++) {
1594 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
1595 size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size;
1596
1597 dma_free_coherent(dev->dev, size, dev->host_mem_desc_bufs[i],
1598 le64_to_cpu(desc->addr));
1599 }
1600
1601 kfree(dev->host_mem_desc_bufs);
1602 dev->host_mem_desc_bufs = NULL;
1603 kfree(dev->host_mem_descs);
1604 dev->host_mem_descs = NULL;
1605}
1606
1607static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
1608{
1609 struct nvme_host_mem_buf_desc *descs;
1610 u32 chunk_size, max_entries, i = 0;
1611 void **bufs;
1612 u64 size, tmp;
1613
1614 /* start big and work our way down */
1615 chunk_size = min(preferred, (u64)PAGE_SIZE << MAX_ORDER);
1616retry:
1617 tmp = (preferred + chunk_size - 1);
1618 do_div(tmp, chunk_size);
1619 max_entries = tmp;
1620 descs = kcalloc(max_entries, sizeof(*descs), GFP_KERNEL);
1621 if (!descs)
1622 goto out;
1623
1624 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
1625 if (!bufs)
1626 goto out_free_descs;
1627
1628 for (size = 0; size < preferred; size += chunk_size) {
1629 u32 len = min_t(u64, chunk_size, preferred - size);
1630 dma_addr_t dma_addr;
1631
1632 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
1633 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1634 if (!bufs[i])
1635 break;
1636
1637 descs[i].addr = cpu_to_le64(dma_addr);
1638 descs[i].size = cpu_to_le32(len / dev->ctrl.page_size);
1639 i++;
1640 }
1641
1642 if (!size || (min && size < min)) {
1643 dev_warn(dev->ctrl.device,
1644 "failed to allocate host memory buffer.\n");
1645 goto out_free_bufs;
1646 }
1647
1648 dev_info(dev->ctrl.device,
1649 "allocated %lld MiB host memory buffer.\n",
1650 size >> ilog2(SZ_1M));
1651 dev->nr_host_mem_descs = i;
1652 dev->host_mem_size = size;
1653 dev->host_mem_descs = descs;
1654 dev->host_mem_desc_bufs = bufs;
1655 return 0;
1656
1657out_free_bufs:
1658 while (--i >= 0) {
1659 size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size;
1660
1661 dma_free_coherent(dev->dev, size, bufs[i],
1662 le64_to_cpu(descs[i].addr));
1663 }
1664
1665 kfree(bufs);
1666out_free_descs:
1667 kfree(descs);
1668out:
1669 /* try a smaller chunk size if we failed early */
1670 if (chunk_size >= PAGE_SIZE * 2 && (i == 0 || size < min)) {
1671 chunk_size /= 2;
1672 goto retry;
1673 }
1674 dev->host_mem_descs = NULL;
1675 return -ENOMEM;
1676}
1677
1678static void nvme_setup_host_mem(struct nvme_dev *dev)
1679{
1680 u64 max = (u64)max_host_mem_size_mb * SZ_1M;
1681 u64 preferred = (u64)dev->ctrl.hmpre * 4096;
1682 u64 min = (u64)dev->ctrl.hmmin * 4096;
1683 u32 enable_bits = NVME_HOST_MEM_ENABLE;
1684
1685 preferred = min(preferred, max);
1686 if (min > max) {
1687 dev_warn(dev->ctrl.device,
1688 "min host memory (%lld MiB) above limit (%d MiB).\n",
1689 min >> ilog2(SZ_1M), max_host_mem_size_mb);
1690 nvme_free_host_mem(dev);
1691 return;
1692 }
1693
1694 /*
1695 * If we already have a buffer allocated check if we can reuse it.
1696 */
1697 if (dev->host_mem_descs) {
1698 if (dev->host_mem_size >= min)
1699 enable_bits |= NVME_HOST_MEM_RETURN;
1700 else
1701 nvme_free_host_mem(dev);
1702 }
1703
1704 if (!dev->host_mem_descs) {
1705 if (nvme_alloc_host_mem(dev, min, preferred))
1706 return;
1707 }
1708
1709 if (nvme_set_host_mem(dev, enable_bits))
1710 nvme_free_host_mem(dev);
1711}
1712
8d85fce7 1713static int nvme_setup_io_queues(struct nvme_dev *dev)
b60503ba 1714{
a4aea562 1715 struct nvme_queue *adminq = dev->queues[0];
e75ec752 1716 struct pci_dev *pdev = to_pci_dev(dev->dev);
97f6ef64
XY
1717 int result, nr_io_queues;
1718 unsigned long size;
b60503ba 1719
2800b8e7 1720 nr_io_queues = num_online_cpus();
9a0be7ab
CH
1721 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
1722 if (result < 0)
1b23484b 1723 return result;
9a0be7ab 1724
f5fa90dc 1725 if (nr_io_queues == 0)
a5229050 1726 return 0;
b60503ba 1727
8ffaadf7
JD
1728 if (dev->cmb && NVME_CMB_SQS(dev->cmbsz)) {
1729 result = nvme_cmb_qdepth(dev, nr_io_queues,
1730 sizeof(struct nvme_command));
1731 if (result > 0)
1732 dev->q_depth = result;
1733 else
1734 nvme_release_cmb(dev);
1735 }
1736
97f6ef64
XY
1737 do {
1738 size = db_bar_size(dev, nr_io_queues);
1739 result = nvme_remap_bar(dev, size);
1740 if (!result)
1741 break;
1742 if (!--nr_io_queues)
1743 return -ENOMEM;
1744 } while (1);
1745 adminq->q_db = dev->dbs;
f1938f6e 1746
9d713c2b 1747 /* Deregister the admin queue's interrupt */
0ff199cb 1748 pci_free_irq(pdev, 0, adminq);
9d713c2b 1749
e32efbfc
JA
1750 /*
1751 * If we enable msix early due to not intx, disable it again before
1752 * setting up the full range we need.
1753 */
dca51e78
CH
1754 pci_free_irq_vectors(pdev);
1755 nr_io_queues = pci_alloc_irq_vectors(pdev, 1, nr_io_queues,
1756 PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY);
1757 if (nr_io_queues <= 0)
1758 return -EIO;
1759 dev->max_qid = nr_io_queues;
fa08a396 1760
063a8096
MW
1761 /*
1762 * Should investigate if there's a performance win from allocating
1763 * more queues than interrupt vectors; it might allow the submission
1764 * path to scale better, even if the receive path is limited by the
1765 * number of interrupts.
1766 */
063a8096 1767
dca51e78 1768 result = queue_request_irq(adminq);
758dd7fd
JD
1769 if (result) {
1770 adminq->cq_vector = -1;
d4875622 1771 return result;
758dd7fd 1772 }
749941f2 1773 return nvme_create_io_queues(dev);
b60503ba
MW
1774}
1775
2a842aca 1776static void nvme_del_queue_end(struct request *req, blk_status_t error)
a5768aa8 1777{
db3cbfff 1778 struct nvme_queue *nvmeq = req->end_io_data;
b5875222 1779
db3cbfff
KB
1780 blk_mq_free_request(req);
1781 complete(&nvmeq->dev->ioq_wait);
a5768aa8
KB
1782}
1783
2a842aca 1784static void nvme_del_cq_end(struct request *req, blk_status_t error)
a5768aa8 1785{
db3cbfff 1786 struct nvme_queue *nvmeq = req->end_io_data;
a5768aa8 1787
db3cbfff
KB
1788 if (!error) {
1789 unsigned long flags;
1790
2e39e0f6
ML
1791 /*
1792 * We might be called with the AQ q_lock held
1793 * and the I/O queue q_lock should always
1794 * nest inside the AQ one.
1795 */
1796 spin_lock_irqsave_nested(&nvmeq->q_lock, flags,
1797 SINGLE_DEPTH_NESTING);
db3cbfff
KB
1798 nvme_process_cq(nvmeq);
1799 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
a5768aa8 1800 }
db3cbfff
KB
1801
1802 nvme_del_queue_end(req, error);
a5768aa8
KB
1803}
1804
db3cbfff 1805static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
bda4e0fb 1806{
db3cbfff
KB
1807 struct request_queue *q = nvmeq->dev->ctrl.admin_q;
1808 struct request *req;
1809 struct nvme_command cmd;
bda4e0fb 1810
db3cbfff
KB
1811 memset(&cmd, 0, sizeof(cmd));
1812 cmd.delete_queue.opcode = opcode;
1813 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
bda4e0fb 1814
eb71f435 1815 req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
db3cbfff
KB
1816 if (IS_ERR(req))
1817 return PTR_ERR(req);
bda4e0fb 1818
db3cbfff
KB
1819 req->timeout = ADMIN_TIMEOUT;
1820 req->end_io_data = nvmeq;
1821
1822 blk_execute_rq_nowait(q, NULL, req, false,
1823 opcode == nvme_admin_delete_cq ?
1824 nvme_del_cq_end : nvme_del_queue_end);
1825 return 0;
bda4e0fb
KB
1826}
1827
70659060 1828static void nvme_disable_io_queues(struct nvme_dev *dev, int queues)
a5768aa8 1829{
70659060 1830 int pass;
db3cbfff
KB
1831 unsigned long timeout;
1832 u8 opcode = nvme_admin_delete_sq;
a5768aa8 1833
db3cbfff 1834 for (pass = 0; pass < 2; pass++) {
014a0d60 1835 int sent = 0, i = queues;
db3cbfff
KB
1836
1837 reinit_completion(&dev->ioq_wait);
1838 retry:
1839 timeout = ADMIN_TIMEOUT;
c21377f8
GKB
1840 for (; i > 0; i--, sent++)
1841 if (nvme_delete_queue(dev->queues[i], opcode))
db3cbfff 1842 break;
c21377f8 1843
db3cbfff
KB
1844 while (sent--) {
1845 timeout = wait_for_completion_io_timeout(&dev->ioq_wait, timeout);
1846 if (timeout == 0)
1847 return;
1848 if (i)
1849 goto retry;
1850 }
1851 opcode = nvme_admin_delete_cq;
1852 }
a5768aa8
KB
1853}
1854
422ef0c7
MW
1855/*
1856 * Return: error value if an error occurred setting up the queues or calling
1857 * Identify Device. 0 if these succeeded, even if adding some of the
1858 * namespaces failed. At the moment, these failures are silent. TBD which
1859 * failures should be reported.
1860 */
8d85fce7 1861static int nvme_dev_add(struct nvme_dev *dev)
b60503ba 1862{
5bae7f73 1863 if (!dev->ctrl.tagset) {
ffe7704d
KB
1864 dev->tagset.ops = &nvme_mq_ops;
1865 dev->tagset.nr_hw_queues = dev->online_queues - 1;
1866 dev->tagset.timeout = NVME_IO_TIMEOUT;
1867 dev->tagset.numa_node = dev_to_node(dev->dev);
1868 dev->tagset.queue_depth =
a4aea562 1869 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
ffe7704d
KB
1870 dev->tagset.cmd_size = nvme_cmd_size(dev);
1871 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
1872 dev->tagset.driver_data = dev;
b60503ba 1873
ffe7704d
KB
1874 if (blk_mq_alloc_tag_set(&dev->tagset))
1875 return 0;
5bae7f73 1876 dev->ctrl.tagset = &dev->tagset;
f9f38e33
HK
1877
1878 nvme_dbbuf_set(dev);
949928c1
KB
1879 } else {
1880 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
1881
1882 /* Free previously allocated queues that are no longer usable */
1883 nvme_free_queues(dev, dev->online_queues);
ffe7704d 1884 }
949928c1 1885
e1e5e564 1886 return 0;
b60503ba
MW
1887}
1888
b00a726a 1889static int nvme_pci_enable(struct nvme_dev *dev)
0877cb0d 1890{
42f61420 1891 u64 cap;
b00a726a 1892 int result = -ENOMEM;
e75ec752 1893 struct pci_dev *pdev = to_pci_dev(dev->dev);
0877cb0d
KB
1894
1895 if (pci_enable_device_mem(pdev))
1896 return result;
1897
0877cb0d 1898 pci_set_master(pdev);
0877cb0d 1899
e75ec752
CH
1900 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) &&
1901 dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32)))
052d0efa 1902 goto disable;
0877cb0d 1903
7a67cbea 1904 if (readl(dev->bar + NVME_REG_CSTS) == -1) {
0e53d180 1905 result = -ENODEV;
b00a726a 1906 goto disable;
0e53d180 1907 }
e32efbfc
JA
1908
1909 /*
a5229050
KB
1910 * Some devices and/or platforms don't advertise or work with INTx
1911 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
1912 * adjust this later.
e32efbfc 1913 */
dca51e78
CH
1914 result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
1915 if (result < 0)
1916 return result;
e32efbfc 1917
7a67cbea
CH
1918 cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
1919
42f61420
KB
1920 dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH);
1921 dev->db_stride = 1 << NVME_CAP_STRIDE(cap);
7a67cbea 1922 dev->dbs = dev->bar + 4096;
1f390c1f
SG
1923
1924 /*
1925 * Temporary fix for the Apple controller found in the MacBook8,1 and
1926 * some MacBook7,1 to avoid controller resets and data loss.
1927 */
1928 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
1929 dev->q_depth = 2;
9bdcfb10
CH
1930 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
1931 "set queue depth=%u to work around controller resets\n",
1f390c1f
SG
1932 dev->q_depth);
1933 }
1934
202021c1
SB
1935 /*
1936 * CMBs can currently only exist on >=1.2 PCIe devices. We only
1937 * populate sysfs if a CMB is implemented. Note that we add the
1938 * CMB attribute to the nvme_ctrl kobj which removes the need to remove
1939 * it on exit. Since nvme_dev_attrs_group has no name we can pass
1940 * NULL as final argument to sysfs_add_file_to_group.
1941 */
1942
8ef2074d 1943 if (readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 2, 0)) {
8ffaadf7 1944 dev->cmb = nvme_map_cmb(dev);
0877cb0d 1945
202021c1
SB
1946 if (dev->cmbsz) {
1947 if (sysfs_add_file_to_group(&dev->ctrl.device->kobj,
1948 &dev_attr_cmb.attr, NULL))
9bdcfb10 1949 dev_warn(dev->ctrl.device,
202021c1
SB
1950 "failed to add sysfs attribute for CMB\n");
1951 }
1952 }
1953
a0a3408e
KB
1954 pci_enable_pcie_error_reporting(pdev);
1955 pci_save_state(pdev);
0877cb0d
KB
1956 return 0;
1957
1958 disable:
0877cb0d
KB
1959 pci_disable_device(pdev);
1960 return result;
1961}
1962
1963static void nvme_dev_unmap(struct nvme_dev *dev)
b00a726a
KB
1964{
1965 if (dev->bar)
1966 iounmap(dev->bar);
a1f447b3 1967 pci_release_mem_regions(to_pci_dev(dev->dev));
b00a726a
KB
1968}
1969
1970static void nvme_pci_disable(struct nvme_dev *dev)
0877cb0d 1971{
e75ec752
CH
1972 struct pci_dev *pdev = to_pci_dev(dev->dev);
1973
f63572df 1974 nvme_release_cmb(dev);
dca51e78 1975 pci_free_irq_vectors(pdev);
0877cb0d 1976
a0a3408e
KB
1977 if (pci_is_enabled(pdev)) {
1978 pci_disable_pcie_error_reporting(pdev);
e75ec752 1979 pci_disable_device(pdev);
4d115420 1980 }
4d115420
KB
1981}
1982
a5cdb68c 1983static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
b60503ba 1984{
70659060 1985 int i, queues;
302ad8cc
KB
1986 bool dead = true;
1987 struct pci_dev *pdev = to_pci_dev(dev->dev);
22404274 1988
2d55cd5f 1989 del_timer_sync(&dev->watchdog_timer);
1fa6aead 1990
77bf25ea 1991 mutex_lock(&dev->shutdown_lock);
302ad8cc
KB
1992 if (pci_is_enabled(pdev)) {
1993 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1994
1995 if (dev->ctrl.state == NVME_CTRL_LIVE)
1996 nvme_start_freeze(&dev->ctrl);
1997 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
1998 pdev->error_state != pci_channel_io_normal);
c9d3bf88 1999 }
c21377f8 2000
302ad8cc
KB
2001 /*
2002 * Give the controller a chance to complete all entered requests if
2003 * doing a safe shutdown.
2004 */
87ad72a5
CH
2005 if (!dead) {
2006 if (shutdown)
2007 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
2008
2009 /*
2010 * If the controller is still alive tell it to stop using the
2011 * host memory buffer. In theory the shutdown / reset should
2012 * make sure that it doesn't access the host memoery anymore,
2013 * but I'd rather be safe than sorry..
2014 */
2015 if (dev->host_mem_descs)
2016 nvme_set_host_mem(dev, 0);
2017
2018 }
302ad8cc
KB
2019 nvme_stop_queues(&dev->ctrl);
2020
70659060 2021 queues = dev->online_queues - 1;
c21377f8
GKB
2022 for (i = dev->queue_count - 1; i > 0; i--)
2023 nvme_suspend_queue(dev->queues[i]);
2024
302ad8cc 2025 if (dead) {
82469c59
GKB
2026 /* A device might become IO incapable very soon during
2027 * probe, before the admin queue is configured. Thus,
2028 * queue_count can be 0 here.
2029 */
2030 if (dev->queue_count)
2031 nvme_suspend_queue(dev->queues[0]);
4d115420 2032 } else {
70659060 2033 nvme_disable_io_queues(dev, queues);
a5cdb68c 2034 nvme_disable_admin_queue(dev, shutdown);
4d115420 2035 }
b00a726a 2036 nvme_pci_disable(dev);
07836e65 2037
e1958e65
ML
2038 blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
2039 blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
302ad8cc
KB
2040
2041 /*
2042 * The driver will not be starting up queues again if shutting down so
2043 * must flush all entered requests to their failed completion to avoid
2044 * deadlocking blk-mq hot-cpu notifier.
2045 */
2046 if (shutdown)
2047 nvme_start_queues(&dev->ctrl);
77bf25ea 2048 mutex_unlock(&dev->shutdown_lock);
b60503ba
MW
2049}
2050
091b6092
MW
2051static int nvme_setup_prp_pools(struct nvme_dev *dev)
2052{
e75ec752 2053 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
091b6092
MW
2054 PAGE_SIZE, PAGE_SIZE, 0);
2055 if (!dev->prp_page_pool)
2056 return -ENOMEM;
2057
99802a7a 2058 /* Optimisation for I/Os between 4k and 128k */
e75ec752 2059 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
99802a7a
MW
2060 256, 256, 0);
2061 if (!dev->prp_small_pool) {
2062 dma_pool_destroy(dev->prp_page_pool);
2063 return -ENOMEM;
2064 }
091b6092
MW
2065 return 0;
2066}
2067
2068static void nvme_release_prp_pools(struct nvme_dev *dev)
2069{
2070 dma_pool_destroy(dev->prp_page_pool);
99802a7a 2071 dma_pool_destroy(dev->prp_small_pool);
091b6092
MW
2072}
2073
1673f1f0 2074static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
5e82e952 2075{
1673f1f0 2076 struct nvme_dev *dev = to_nvme_dev(ctrl);
9ac27090 2077
f9f38e33 2078 nvme_dbbuf_dma_free(dev);
e75ec752 2079 put_device(dev->dev);
4af0e21c
KB
2080 if (dev->tagset.tags)
2081 blk_mq_free_tag_set(&dev->tagset);
1c63dc66
CH
2082 if (dev->ctrl.admin_q)
2083 blk_put_queue(dev->ctrl.admin_q);
5e82e952 2084 kfree(dev->queues);
e286bcfc 2085 free_opal_dev(dev->ctrl.opal_dev);
5e82e952
KB
2086 kfree(dev);
2087}
2088
f58944e2
KB
2089static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status)
2090{
237045fc 2091 dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status);
f58944e2
KB
2092
2093 kref_get(&dev->ctrl.kref);
69d9a99c 2094 nvme_dev_disable(dev, false);
f58944e2
KB
2095 if (!schedule_work(&dev->remove_work))
2096 nvme_put_ctrl(&dev->ctrl);
2097}
2098
fd634f41 2099static void nvme_reset_work(struct work_struct *work)
5e82e952 2100{
fd634f41 2101 struct nvme_dev *dev = container_of(work, struct nvme_dev, reset_work);
a98e58e5 2102 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
f58944e2 2103 int result = -ENODEV;
5e82e952 2104
82b057ca 2105 if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING))
fd634f41 2106 goto out;
5e82e952 2107
fd634f41
CH
2108 /*
2109 * If we're called to reset a live controller first shut it down before
2110 * moving on.
2111 */
b00a726a 2112 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
a5cdb68c 2113 nvme_dev_disable(dev, false);
5e82e952 2114
b00a726a 2115 result = nvme_pci_enable(dev);
f0b50732 2116 if (result)
3cf519b5 2117 goto out;
f0b50732
KB
2118
2119 result = nvme_configure_admin_queue(dev);
2120 if (result)
f58944e2 2121 goto out;
f0b50732 2122
a4aea562 2123 nvme_init_queue(dev->queues[0], 0);
0fb59cbc
KB
2124 result = nvme_alloc_admin_tags(dev);
2125 if (result)
f58944e2 2126 goto out;
b9afca3e 2127
ce4541f4
CH
2128 result = nvme_init_identify(&dev->ctrl);
2129 if (result)
f58944e2 2130 goto out;
ce4541f4 2131
e286bcfc
SB
2132 if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
2133 if (!dev->ctrl.opal_dev)
2134 dev->ctrl.opal_dev =
2135 init_opal_dev(&dev->ctrl, &nvme_sec_submit);
2136 else if (was_suspend)
2137 opal_unlock_from_suspend(dev->ctrl.opal_dev);
2138 } else {
2139 free_opal_dev(dev->ctrl.opal_dev);
2140 dev->ctrl.opal_dev = NULL;
4f1244c8 2141 }
a98e58e5 2142
f9f38e33
HK
2143 if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) {
2144 result = nvme_dbbuf_dma_alloc(dev);
2145 if (result)
2146 dev_warn(dev->dev,
2147 "unable to allocate dma for dbbuf\n");
2148 }
2149
87ad72a5
CH
2150 if (dev->ctrl.hmpre)
2151 nvme_setup_host_mem(dev);
2152
f0b50732 2153 result = nvme_setup_io_queues(dev);
badc34d4 2154 if (result)
f58944e2 2155 goto out;
f0b50732 2156
21f033f7
KB
2157 /*
2158 * A controller that can not execute IO typically requires user
2159 * intervention to correct. For such degraded controllers, the driver
2160 * should not submit commands the user did not request, so skip
2161 * registering for asynchronous event notification on this condition.
2162 */
f866fc42
CH
2163 if (dev->online_queues > 1)
2164 nvme_queue_async_events(&dev->ctrl);
3cf519b5 2165
2d55cd5f 2166 mod_timer(&dev->watchdog_timer, round_jiffies(jiffies + HZ));
3cf519b5 2167
2659e57b
CH
2168 /*
2169 * Keep the controller around but remove all namespaces if we don't have
2170 * any working I/O queue.
2171 */
3cf519b5 2172 if (dev->online_queues < 2) {
1b3c47c1 2173 dev_warn(dev->ctrl.device, "IO queues not created\n");
3b24774e 2174 nvme_kill_queues(&dev->ctrl);
5bae7f73 2175 nvme_remove_namespaces(&dev->ctrl);
3cf519b5 2176 } else {
25646264 2177 nvme_start_queues(&dev->ctrl);
302ad8cc 2178 nvme_wait_freeze(&dev->ctrl);
3cf519b5 2179 nvme_dev_add(dev);
302ad8cc 2180 nvme_unfreeze(&dev->ctrl);
3cf519b5
CH
2181 }
2182
bb8d261e
CH
2183 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
2184 dev_warn(dev->ctrl.device, "failed to mark controller live\n");
2185 goto out;
2186 }
92911a55
CH
2187
2188 if (dev->online_queues > 1)
5955be21 2189 nvme_queue_scan(&dev->ctrl);
3cf519b5 2190 return;
f0b50732 2191
3cf519b5 2192 out:
f58944e2 2193 nvme_remove_dead_ctrl(dev, result);
f0b50732
KB
2194}
2195
5c8809e6 2196static void nvme_remove_dead_ctrl_work(struct work_struct *work)
9a6b9458 2197{
5c8809e6 2198 struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
e75ec752 2199 struct pci_dev *pdev = to_pci_dev(dev->dev);
9a6b9458 2200
69d9a99c 2201 nvme_kill_queues(&dev->ctrl);
9a6b9458 2202 if (pci_get_drvdata(pdev))
921920ab 2203 device_release_driver(&pdev->dev);
1673f1f0 2204 nvme_put_ctrl(&dev->ctrl);
9a6b9458
KB
2205}
2206
4cc06521 2207static int nvme_reset(struct nvme_dev *dev)
9a6b9458 2208{
1c63dc66 2209 if (!dev->ctrl.admin_q || blk_queue_dying(dev->ctrl.admin_q))
4cc06521 2210 return -ENODEV;
82b057ca
RP
2211 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_RESETTING))
2212 return -EBUSY;
9a6327d2 2213 if (!queue_work(nvme_wq, &dev->reset_work))
846cc05f 2214 return -EBUSY;
846cc05f 2215 return 0;
9a6b9458
KB
2216}
2217
1c63dc66 2218static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
9ca97374 2219{
1c63dc66 2220 *val = readl(to_nvme_dev(ctrl)->bar + off);
90667892 2221 return 0;
9ca97374
TH
2222}
2223
5fd4ce1b 2224static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
4cc06521 2225{
5fd4ce1b
CH
2226 writel(val, to_nvme_dev(ctrl)->bar + off);
2227 return 0;
2228}
4cc06521 2229
7fd8930f
CH
2230static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2231{
2232 *val = readq(to_nvme_dev(ctrl)->bar + off);
2233 return 0;
4cc06521
KB
2234}
2235
f3ca80fc
CH
2236static int nvme_pci_reset_ctrl(struct nvme_ctrl *ctrl)
2237{
c5f6ce97
KB
2238 struct nvme_dev *dev = to_nvme_dev(ctrl);
2239 int ret = nvme_reset(dev);
2240
2241 if (!ret)
2242 flush_work(&dev->reset_work);
2243 return ret;
4cc06521 2244}
f3ca80fc 2245
1c63dc66 2246static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
1a353d85 2247 .name = "pcie",
e439bb12 2248 .module = THIS_MODULE,
c81bfba9 2249 .flags = NVME_F_METADATA_SUPPORTED,
1c63dc66 2250 .reg_read32 = nvme_pci_reg_read32,
5fd4ce1b 2251 .reg_write32 = nvme_pci_reg_write32,
7fd8930f 2252 .reg_read64 = nvme_pci_reg_read64,
f3ca80fc 2253 .reset_ctrl = nvme_pci_reset_ctrl,
1673f1f0 2254 .free_ctrl = nvme_pci_free_ctrl,
f866fc42 2255 .submit_async_event = nvme_pci_submit_async_event,
1c63dc66 2256};
4cc06521 2257
b00a726a
KB
2258static int nvme_dev_map(struct nvme_dev *dev)
2259{
b00a726a
KB
2260 struct pci_dev *pdev = to_pci_dev(dev->dev);
2261
a1f447b3 2262 if (pci_request_mem_regions(pdev, "nvme"))
b00a726a
KB
2263 return -ENODEV;
2264
97f6ef64 2265 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
b00a726a
KB
2266 goto release;
2267
9fa196e7 2268 return 0;
b00a726a 2269 release:
9fa196e7
MG
2270 pci_release_mem_regions(pdev);
2271 return -ENODEV;
b00a726a
KB
2272}
2273
ff5350a8
AL
2274static unsigned long check_dell_samsung_bug(struct pci_dev *pdev)
2275{
2276 if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
2277 /*
2278 * Several Samsung devices seem to drop off the PCIe bus
2279 * randomly when APST is on and uses the deepest sleep state.
2280 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2281 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2282 * 950 PRO 256GB", but it seems to be restricted to two Dell
2283 * laptops.
2284 */
2285 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
2286 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
2287 dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
2288 return NVME_QUIRK_NO_DEEPEST_PS;
2289 }
2290
2291 return 0;
2292}
2293
8d85fce7 2294static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
b60503ba 2295{
a4aea562 2296 int node, result = -ENOMEM;
b60503ba 2297 struct nvme_dev *dev;
ff5350a8 2298 unsigned long quirks = id->driver_data;
b60503ba 2299
a4aea562
MB
2300 node = dev_to_node(&pdev->dev);
2301 if (node == NUMA_NO_NODE)
2fa84351 2302 set_dev_node(&pdev->dev, first_memory_node);
a4aea562
MB
2303
2304 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
b60503ba
MW
2305 if (!dev)
2306 return -ENOMEM;
a4aea562
MB
2307 dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *),
2308 GFP_KERNEL, node);
b60503ba
MW
2309 if (!dev->queues)
2310 goto free;
2311
e75ec752 2312 dev->dev = get_device(&pdev->dev);
9a6b9458 2313 pci_set_drvdata(pdev, dev);
1c63dc66 2314
b00a726a
KB
2315 result = nvme_dev_map(dev);
2316 if (result)
2317 goto free;
2318
f3ca80fc 2319 INIT_WORK(&dev->reset_work, nvme_reset_work);
5c8809e6 2320 INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
2d55cd5f
CH
2321 setup_timer(&dev->watchdog_timer, nvme_watchdog_timer,
2322 (unsigned long)dev);
77bf25ea 2323 mutex_init(&dev->shutdown_lock);
db3cbfff 2324 init_completion(&dev->ioq_wait);
b60503ba 2325
091b6092
MW
2326 result = nvme_setup_prp_pools(dev);
2327 if (result)
a96d4f5c 2328 goto put_pci;
4cc06521 2329
ff5350a8
AL
2330 quirks |= check_dell_samsung_bug(pdev);
2331
f3ca80fc 2332 result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
ff5350a8 2333 quirks);
4cc06521 2334 if (result)
2e1d8448 2335 goto release_pools;
740216fc 2336
82b057ca 2337 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_RESETTING);
1b3c47c1
SG
2338 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
2339
9a6327d2 2340 queue_work(nvme_wq, &dev->reset_work);
b60503ba
MW
2341 return 0;
2342
0877cb0d 2343 release_pools:
091b6092 2344 nvme_release_prp_pools(dev);
a96d4f5c 2345 put_pci:
e75ec752 2346 put_device(dev->dev);
b00a726a 2347 nvme_dev_unmap(dev);
b60503ba
MW
2348 free:
2349 kfree(dev->queues);
b60503ba
MW
2350 kfree(dev);
2351 return result;
2352}
2353
f0d54a54
KB
2354static void nvme_reset_notify(struct pci_dev *pdev, bool prepare)
2355{
a6739479 2356 struct nvme_dev *dev = pci_get_drvdata(pdev);
f0d54a54 2357
a6739479 2358 if (prepare)
a5cdb68c 2359 nvme_dev_disable(dev, false);
a6739479 2360 else
c5f6ce97 2361 nvme_reset(dev);
f0d54a54
KB
2362}
2363
09ece142
KB
2364static void nvme_shutdown(struct pci_dev *pdev)
2365{
2366 struct nvme_dev *dev = pci_get_drvdata(pdev);
a5cdb68c 2367 nvme_dev_disable(dev, true);
09ece142
KB
2368}
2369
f58944e2
KB
2370/*
2371 * The driver's remove may be called on a device in a partially initialized
2372 * state. This function must not have any dependencies on the device state in
2373 * order to proceed.
2374 */
8d85fce7 2375static void nvme_remove(struct pci_dev *pdev)
b60503ba
MW
2376{
2377 struct nvme_dev *dev = pci_get_drvdata(pdev);
9a6b9458 2378
bb8d261e
CH
2379 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
2380
82b057ca 2381 cancel_work_sync(&dev->reset_work);
9a6b9458 2382 pci_set_drvdata(pdev, NULL);
0ff9d4e1 2383
6db28eda 2384 if (!pci_device_is_present(pdev)) {
0ff9d4e1 2385 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
6db28eda
KB
2386 nvme_dev_disable(dev, false);
2387 }
0ff9d4e1 2388
9bf2b972 2389 flush_work(&dev->reset_work);
53029b04 2390 nvme_uninit_ctrl(&dev->ctrl);
a5cdb68c 2391 nvme_dev_disable(dev, true);
87ad72a5 2392 nvme_free_host_mem(dev);
a4aea562 2393 nvme_dev_remove_admin(dev);
a1a5ef99 2394 nvme_free_queues(dev, 0);
9a6b9458 2395 nvme_release_prp_pools(dev);
b00a726a 2396 nvme_dev_unmap(dev);
1673f1f0 2397 nvme_put_ctrl(&dev->ctrl);
b60503ba
MW
2398}
2399
13880f5b
KB
2400static int nvme_pci_sriov_configure(struct pci_dev *pdev, int numvfs)
2401{
2402 int ret = 0;
2403
2404 if (numvfs == 0) {
2405 if (pci_vfs_assigned(pdev)) {
2406 dev_warn(&pdev->dev,
2407 "Cannot disable SR-IOV VFs while assigned\n");
2408 return -EPERM;
2409 }
2410 pci_disable_sriov(pdev);
2411 return 0;
2412 }
2413
2414 ret = pci_enable_sriov(pdev, numvfs);
2415 return ret ? ret : numvfs;
2416}
2417
671a6018 2418#ifdef CONFIG_PM_SLEEP
cd638946
KB
2419static int nvme_suspend(struct device *dev)
2420{
2421 struct pci_dev *pdev = to_pci_dev(dev);
2422 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2423
a5cdb68c 2424 nvme_dev_disable(ndev, true);
cd638946
KB
2425 return 0;
2426}
2427
2428static int nvme_resume(struct device *dev)
2429{
2430 struct pci_dev *pdev = to_pci_dev(dev);
2431 struct nvme_dev *ndev = pci_get_drvdata(pdev);
cd638946 2432
c5f6ce97 2433 nvme_reset(ndev);
9a6b9458 2434 return 0;
cd638946 2435}
671a6018 2436#endif
cd638946
KB
2437
2438static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
b60503ba 2439
a0a3408e
KB
2440static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
2441 pci_channel_state_t state)
2442{
2443 struct nvme_dev *dev = pci_get_drvdata(pdev);
2444
2445 /*
2446 * A frozen channel requires a reset. When detected, this method will
2447 * shutdown the controller to quiesce. The controller will be restarted
2448 * after the slot reset through driver's slot_reset callback.
2449 */
a0a3408e
KB
2450 switch (state) {
2451 case pci_channel_io_normal:
2452 return PCI_ERS_RESULT_CAN_RECOVER;
2453 case pci_channel_io_frozen:
d011fb31
KB
2454 dev_warn(dev->ctrl.device,
2455 "frozen state error detected, reset controller\n");
a5cdb68c 2456 nvme_dev_disable(dev, false);
a0a3408e
KB
2457 return PCI_ERS_RESULT_NEED_RESET;
2458 case pci_channel_io_perm_failure:
d011fb31
KB
2459 dev_warn(dev->ctrl.device,
2460 "failure state error detected, request disconnect\n");
a0a3408e
KB
2461 return PCI_ERS_RESULT_DISCONNECT;
2462 }
2463 return PCI_ERS_RESULT_NEED_RESET;
2464}
2465
2466static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
2467{
2468 struct nvme_dev *dev = pci_get_drvdata(pdev);
2469
1b3c47c1 2470 dev_info(dev->ctrl.device, "restart after slot reset\n");
a0a3408e 2471 pci_restore_state(pdev);
c5f6ce97 2472 nvme_reset(dev);
a0a3408e
KB
2473 return PCI_ERS_RESULT_RECOVERED;
2474}
2475
2476static void nvme_error_resume(struct pci_dev *pdev)
2477{
2478 pci_cleanup_aer_uncorrect_error_status(pdev);
2479}
2480
1d352035 2481static const struct pci_error_handlers nvme_err_handler = {
b60503ba 2482 .error_detected = nvme_error_detected,
b60503ba
MW
2483 .slot_reset = nvme_slot_reset,
2484 .resume = nvme_error_resume,
f0d54a54 2485 .reset_notify = nvme_reset_notify,
b60503ba
MW
2486};
2487
6eb0d698 2488static const struct pci_device_id nvme_id_table[] = {
106198ed 2489 { PCI_VDEVICE(INTEL, 0x0953),
08095e70 2490 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 2491 NVME_QUIRK_DEALLOCATE_ZEROES, },
99466e70
KB
2492 { PCI_VDEVICE(INTEL, 0x0a53),
2493 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 2494 NVME_QUIRK_DEALLOCATE_ZEROES, },
99466e70
KB
2495 { PCI_VDEVICE(INTEL, 0x0a54),
2496 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 2497 NVME_QUIRK_DEALLOCATE_ZEROES, },
50af47d0
AL
2498 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */
2499 .driver_data = NVME_QUIRK_NO_DEEPEST_PS },
540c801c
KB
2500 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */
2501 .driver_data = NVME_QUIRK_IDENTIFY_CNS, },
54adc010
GP
2502 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
2503 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
015282c9
WW
2504 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
2505 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
b60503ba 2506 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
c74dc780 2507 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) },
124298bd 2508 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
b60503ba
MW
2509 { 0, }
2510};
2511MODULE_DEVICE_TABLE(pci, nvme_id_table);
2512
2513static struct pci_driver nvme_driver = {
2514 .name = "nvme",
2515 .id_table = nvme_id_table,
2516 .probe = nvme_probe,
8d85fce7 2517 .remove = nvme_remove,
09ece142 2518 .shutdown = nvme_shutdown,
cd638946
KB
2519 .driver = {
2520 .pm = &nvme_dev_pm_ops,
2521 },
13880f5b 2522 .sriov_configure = nvme_pci_sriov_configure,
b60503ba
MW
2523 .err_handler = &nvme_err_handler,
2524};
2525
2526static int __init nvme_init(void)
2527{
9a6327d2 2528 return pci_register_driver(&nvme_driver);
b60503ba
MW
2529}
2530
2531static void __exit nvme_exit(void)
2532{
2533 pci_unregister_driver(&nvme_driver);
21bd78bc 2534 _nvme_check_size();
b60503ba
MW
2535}
2536
2537MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2538MODULE_LICENSE("GPL");
c78b4713 2539MODULE_VERSION("1.0");
b60503ba
MW
2540module_init(nvme_init);
2541module_exit(nvme_exit);