Commit | Line | Data |
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b60503ba MW |
1 | /* |
2 | * NVM Express device driver | |
6eb0d698 | 3 | * Copyright (c) 2011-2014, Intel Corporation. |
b60503ba MW |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
b60503ba MW |
13 | */ |
14 | ||
a0a3408e | 15 | #include <linux/aer.h> |
8de05535 | 16 | #include <linux/bitops.h> |
b60503ba | 17 | #include <linux/blkdev.h> |
a4aea562 | 18 | #include <linux/blk-mq.h> |
42f61420 | 19 | #include <linux/cpu.h> |
fd63e9ce | 20 | #include <linux/delay.h> |
b60503ba MW |
21 | #include <linux/errno.h> |
22 | #include <linux/fs.h> | |
23 | #include <linux/genhd.h> | |
4cc09e2d | 24 | #include <linux/hdreg.h> |
5aff9382 | 25 | #include <linux/idr.h> |
b60503ba MW |
26 | #include <linux/init.h> |
27 | #include <linux/interrupt.h> | |
28 | #include <linux/io.h> | |
29 | #include <linux/kdev_t.h> | |
30 | #include <linux/kernel.h> | |
31 | #include <linux/mm.h> | |
32 | #include <linux/module.h> | |
33 | #include <linux/moduleparam.h> | |
77bf25ea | 34 | #include <linux/mutex.h> |
b60503ba | 35 | #include <linux/pci.h> |
be7b6275 | 36 | #include <linux/poison.h> |
c3bfe717 | 37 | #include <linux/ptrace.h> |
b60503ba MW |
38 | #include <linux/sched.h> |
39 | #include <linux/slab.h> | |
e1e5e564 | 40 | #include <linux/t10-pi.h> |
2d55cd5f | 41 | #include <linux/timer.h> |
b60503ba | 42 | #include <linux/types.h> |
2f8e2c87 | 43 | #include <linux/io-64-nonatomic-lo-hi.h> |
1d277a63 | 44 | #include <asm/unaligned.h> |
797a796a | 45 | |
f11bb3e2 CH |
46 | #include "nvme.h" |
47 | ||
9d43cf64 | 48 | #define NVME_Q_DEPTH 1024 |
d31af0a3 | 49 | #define NVME_AQ_DEPTH 256 |
b60503ba MW |
50 | #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command)) |
51 | #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion)) | |
adf68f21 CH |
52 | |
53 | /* | |
54 | * We handle AEN commands ourselves and don't even let the | |
55 | * block layer know about them. | |
56 | */ | |
f866fc42 | 57 | #define NVME_AQ_BLKMQ_DEPTH (NVME_AQ_DEPTH - NVME_NR_AERS) |
9d43cf64 | 58 | |
58ffacb5 MW |
59 | static int use_threaded_interrupts; |
60 | module_param(use_threaded_interrupts, int, 0); | |
61 | ||
8ffaadf7 JD |
62 | static bool use_cmb_sqes = true; |
63 | module_param(use_cmb_sqes, bool, 0644); | |
64 | MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes"); | |
65 | ||
9a6b9458 | 66 | static struct workqueue_struct *nvme_workq; |
1fa6aead | 67 | |
1c63dc66 CH |
68 | struct nvme_dev; |
69 | struct nvme_queue; | |
b3fffdef | 70 | |
4cc06521 | 71 | static int nvme_reset(struct nvme_dev *dev); |
a0fa9647 | 72 | static void nvme_process_cq(struct nvme_queue *nvmeq); |
a5cdb68c | 73 | static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown); |
d4b4ff8e | 74 | |
1c63dc66 CH |
75 | /* |
76 | * Represents an NVM Express device. Each nvme_dev is a PCI function. | |
77 | */ | |
78 | struct nvme_dev { | |
1c63dc66 CH |
79 | struct nvme_queue **queues; |
80 | struct blk_mq_tag_set tagset; | |
81 | struct blk_mq_tag_set admin_tagset; | |
82 | u32 __iomem *dbs; | |
83 | struct device *dev; | |
84 | struct dma_pool *prp_page_pool; | |
85 | struct dma_pool *prp_small_pool; | |
86 | unsigned queue_count; | |
87 | unsigned online_queues; | |
88 | unsigned max_qid; | |
89 | int q_depth; | |
90 | u32 db_stride; | |
1c63dc66 CH |
91 | struct msix_entry *entry; |
92 | void __iomem *bar; | |
1c63dc66 | 93 | struct work_struct reset_work; |
5c8809e6 | 94 | struct work_struct remove_work; |
2d55cd5f | 95 | struct timer_list watchdog_timer; |
77bf25ea | 96 | struct mutex shutdown_lock; |
1c63dc66 | 97 | bool subsystem; |
1c63dc66 CH |
98 | void __iomem *cmb; |
99 | dma_addr_t cmb_dma_addr; | |
100 | u64 cmb_size; | |
101 | u32 cmbsz; | |
1c63dc66 | 102 | struct nvme_ctrl ctrl; |
db3cbfff | 103 | struct completion ioq_wait; |
4d115420 | 104 | }; |
1fa6aead | 105 | |
1c63dc66 CH |
106 | static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl) |
107 | { | |
108 | return container_of(ctrl, struct nvme_dev, ctrl); | |
109 | } | |
110 | ||
b60503ba MW |
111 | /* |
112 | * An NVM Express queue. Each device has at least two (one for admin | |
113 | * commands and one for I/O commands). | |
114 | */ | |
115 | struct nvme_queue { | |
116 | struct device *q_dmadev; | |
091b6092 | 117 | struct nvme_dev *dev; |
3193f07b | 118 | char irqname[24]; /* nvme4294967295-65535\0 */ |
b60503ba MW |
119 | spinlock_t q_lock; |
120 | struct nvme_command *sq_cmds; | |
8ffaadf7 | 121 | struct nvme_command __iomem *sq_cmds_io; |
b60503ba | 122 | volatile struct nvme_completion *cqes; |
42483228 | 123 | struct blk_mq_tags **tags; |
b60503ba MW |
124 | dma_addr_t sq_dma_addr; |
125 | dma_addr_t cq_dma_addr; | |
b60503ba MW |
126 | u32 __iomem *q_db; |
127 | u16 q_depth; | |
6222d172 | 128 | s16 cq_vector; |
b60503ba MW |
129 | u16 sq_tail; |
130 | u16 cq_head; | |
c30341dc | 131 | u16 qid; |
e9539f47 MW |
132 | u8 cq_phase; |
133 | u8 cqe_seen; | |
b60503ba MW |
134 | }; |
135 | ||
71bd150c CH |
136 | /* |
137 | * The nvme_iod describes the data in an I/O, including the list of PRP | |
138 | * entries. You can't see it in this data structure because C doesn't let | |
f4800d6d | 139 | * me express that. Use nvme_init_iod to ensure there's enough space |
71bd150c CH |
140 | * allocated to store the PRP list. |
141 | */ | |
142 | struct nvme_iod { | |
f4800d6d CH |
143 | struct nvme_queue *nvmeq; |
144 | int aborted; | |
71bd150c | 145 | int npages; /* In the PRP list. 0 means small pool in use */ |
71bd150c CH |
146 | int nents; /* Used in scatterlist */ |
147 | int length; /* Of data, in bytes */ | |
148 | dma_addr_t first_dma; | |
bf684057 | 149 | struct scatterlist meta_sg; /* metadata requires single contiguous buffer */ |
f4800d6d CH |
150 | struct scatterlist *sg; |
151 | struct scatterlist inline_sg[0]; | |
b60503ba MW |
152 | }; |
153 | ||
154 | /* | |
155 | * Check we didin't inadvertently grow the command struct | |
156 | */ | |
157 | static inline void _nvme_check_size(void) | |
158 | { | |
159 | BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64); | |
160 | BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); | |
161 | BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); | |
162 | BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); | |
163 | BUILD_BUG_ON(sizeof(struct nvme_features) != 64); | |
f8ebf840 | 164 | BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64); |
c30341dc | 165 | BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64); |
b60503ba MW |
166 | BUILD_BUG_ON(sizeof(struct nvme_command) != 64); |
167 | BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096); | |
168 | BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096); | |
169 | BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64); | |
6ecec745 | 170 | BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512); |
b60503ba MW |
171 | } |
172 | ||
ac3dd5bd JA |
173 | /* |
174 | * Max size of iod being embedded in the request payload | |
175 | */ | |
176 | #define NVME_INT_PAGES 2 | |
5fd4ce1b | 177 | #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size) |
ac3dd5bd JA |
178 | |
179 | /* | |
180 | * Will slightly overestimate the number of pages needed. This is OK | |
181 | * as it only leads to a small amount of wasted memory for the lifetime of | |
182 | * the I/O. | |
183 | */ | |
184 | static int nvme_npages(unsigned size, struct nvme_dev *dev) | |
185 | { | |
5fd4ce1b CH |
186 | unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size, |
187 | dev->ctrl.page_size); | |
ac3dd5bd JA |
188 | return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); |
189 | } | |
190 | ||
f4800d6d CH |
191 | static unsigned int nvme_iod_alloc_size(struct nvme_dev *dev, |
192 | unsigned int size, unsigned int nseg) | |
ac3dd5bd | 193 | { |
f4800d6d CH |
194 | return sizeof(__le64 *) * nvme_npages(size, dev) + |
195 | sizeof(struct scatterlist) * nseg; | |
196 | } | |
ac3dd5bd | 197 | |
f4800d6d CH |
198 | static unsigned int nvme_cmd_size(struct nvme_dev *dev) |
199 | { | |
200 | return sizeof(struct nvme_iod) + | |
201 | nvme_iod_alloc_size(dev, NVME_INT_BYTES(dev), NVME_INT_PAGES); | |
ac3dd5bd JA |
202 | } |
203 | ||
a4aea562 MB |
204 | static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, |
205 | unsigned int hctx_idx) | |
e85248e5 | 206 | { |
a4aea562 MB |
207 | struct nvme_dev *dev = data; |
208 | struct nvme_queue *nvmeq = dev->queues[0]; | |
209 | ||
42483228 KB |
210 | WARN_ON(hctx_idx != 0); |
211 | WARN_ON(dev->admin_tagset.tags[0] != hctx->tags); | |
212 | WARN_ON(nvmeq->tags); | |
213 | ||
a4aea562 | 214 | hctx->driver_data = nvmeq; |
42483228 | 215 | nvmeq->tags = &dev->admin_tagset.tags[0]; |
a4aea562 | 216 | return 0; |
e85248e5 MW |
217 | } |
218 | ||
4af0e21c KB |
219 | static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx) |
220 | { | |
221 | struct nvme_queue *nvmeq = hctx->driver_data; | |
222 | ||
223 | nvmeq->tags = NULL; | |
224 | } | |
225 | ||
a4aea562 MB |
226 | static int nvme_admin_init_request(void *data, struct request *req, |
227 | unsigned int hctx_idx, unsigned int rq_idx, | |
228 | unsigned int numa_node) | |
22404274 | 229 | { |
a4aea562 | 230 | struct nvme_dev *dev = data; |
f4800d6d | 231 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
a4aea562 MB |
232 | struct nvme_queue *nvmeq = dev->queues[0]; |
233 | ||
234 | BUG_ON(!nvmeq); | |
f4800d6d | 235 | iod->nvmeq = nvmeq; |
a4aea562 | 236 | return 0; |
22404274 KB |
237 | } |
238 | ||
a4aea562 MB |
239 | static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, |
240 | unsigned int hctx_idx) | |
b60503ba | 241 | { |
a4aea562 | 242 | struct nvme_dev *dev = data; |
42483228 | 243 | struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1]; |
a4aea562 | 244 | |
42483228 KB |
245 | if (!nvmeq->tags) |
246 | nvmeq->tags = &dev->tagset.tags[hctx_idx]; | |
b60503ba | 247 | |
42483228 | 248 | WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags); |
a4aea562 MB |
249 | hctx->driver_data = nvmeq; |
250 | return 0; | |
b60503ba MW |
251 | } |
252 | ||
a4aea562 MB |
253 | static int nvme_init_request(void *data, struct request *req, |
254 | unsigned int hctx_idx, unsigned int rq_idx, | |
255 | unsigned int numa_node) | |
b60503ba | 256 | { |
a4aea562 | 257 | struct nvme_dev *dev = data; |
f4800d6d | 258 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
a4aea562 MB |
259 | struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1]; |
260 | ||
261 | BUG_ON(!nvmeq); | |
f4800d6d | 262 | iod->nvmeq = nvmeq; |
a4aea562 MB |
263 | return 0; |
264 | } | |
265 | ||
b60503ba | 266 | /** |
adf68f21 | 267 | * __nvme_submit_cmd() - Copy a command into a queue and ring the doorbell |
b60503ba MW |
268 | * @nvmeq: The queue to use |
269 | * @cmd: The command to send | |
270 | * | |
271 | * Safe to use from interrupt context | |
272 | */ | |
e3f879bf SB |
273 | static void __nvme_submit_cmd(struct nvme_queue *nvmeq, |
274 | struct nvme_command *cmd) | |
b60503ba | 275 | { |
a4aea562 MB |
276 | u16 tail = nvmeq->sq_tail; |
277 | ||
8ffaadf7 JD |
278 | if (nvmeq->sq_cmds_io) |
279 | memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd)); | |
280 | else | |
281 | memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd)); | |
282 | ||
b60503ba MW |
283 | if (++tail == nvmeq->q_depth) |
284 | tail = 0; | |
7547881d | 285 | writel(tail, nvmeq->q_db); |
b60503ba | 286 | nvmeq->sq_tail = tail; |
b60503ba MW |
287 | } |
288 | ||
f4800d6d | 289 | static __le64 **iod_list(struct request *req) |
b60503ba | 290 | { |
f4800d6d CH |
291 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
292 | return (__le64 **)(iod->sg + req->nr_phys_segments); | |
b60503ba MW |
293 | } |
294 | ||
58b45602 ML |
295 | static int nvme_init_iod(struct request *rq, unsigned size, |
296 | struct nvme_dev *dev) | |
ac3dd5bd | 297 | { |
f4800d6d CH |
298 | struct nvme_iod *iod = blk_mq_rq_to_pdu(rq); |
299 | int nseg = rq->nr_phys_segments; | |
ac3dd5bd | 300 | |
f4800d6d CH |
301 | if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) { |
302 | iod->sg = kmalloc(nvme_iod_alloc_size(dev, size, nseg), GFP_ATOMIC); | |
303 | if (!iod->sg) | |
304 | return BLK_MQ_RQ_QUEUE_BUSY; | |
305 | } else { | |
306 | iod->sg = iod->inline_sg; | |
ac3dd5bd JA |
307 | } |
308 | ||
f4800d6d CH |
309 | iod->aborted = 0; |
310 | iod->npages = -1; | |
311 | iod->nents = 0; | |
312 | iod->length = size; | |
f80ec966 KB |
313 | |
314 | if (!(rq->cmd_flags & REQ_DONTPREP)) { | |
315 | rq->retries = 0; | |
316 | rq->cmd_flags |= REQ_DONTPREP; | |
317 | } | |
f4800d6d | 318 | return 0; |
ac3dd5bd JA |
319 | } |
320 | ||
f4800d6d | 321 | static void nvme_free_iod(struct nvme_dev *dev, struct request *req) |
b60503ba | 322 | { |
f4800d6d | 323 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
5fd4ce1b | 324 | const int last_prp = dev->ctrl.page_size / 8 - 1; |
eca18b23 | 325 | int i; |
f4800d6d | 326 | __le64 **list = iod_list(req); |
eca18b23 MW |
327 | dma_addr_t prp_dma = iod->first_dma; |
328 | ||
6904242d | 329 | nvme_cleanup_cmd(req); |
03b5929e | 330 | |
eca18b23 MW |
331 | if (iod->npages == 0) |
332 | dma_pool_free(dev->prp_small_pool, list[0], prp_dma); | |
333 | for (i = 0; i < iod->npages; i++) { | |
334 | __le64 *prp_list = list[i]; | |
335 | dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]); | |
336 | dma_pool_free(dev->prp_page_pool, prp_list, prp_dma); | |
337 | prp_dma = next_prp_dma; | |
338 | } | |
ac3dd5bd | 339 | |
f4800d6d CH |
340 | if (iod->sg != iod->inline_sg) |
341 | kfree(iod->sg); | |
b4ff9c8d KB |
342 | } |
343 | ||
52b68d7e | 344 | #ifdef CONFIG_BLK_DEV_INTEGRITY |
e1e5e564 KB |
345 | static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi) |
346 | { | |
347 | if (be32_to_cpu(pi->ref_tag) == v) | |
348 | pi->ref_tag = cpu_to_be32(p); | |
349 | } | |
350 | ||
351 | static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi) | |
352 | { | |
353 | if (be32_to_cpu(pi->ref_tag) == p) | |
354 | pi->ref_tag = cpu_to_be32(v); | |
355 | } | |
356 | ||
357 | /** | |
358 | * nvme_dif_remap - remaps ref tags to bip seed and physical lba | |
359 | * | |
360 | * The virtual start sector is the one that was originally submitted by the | |
361 | * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical | |
362 | * start sector may be different. Remap protection information to match the | |
363 | * physical LBA on writes, and back to the original seed on reads. | |
364 | * | |
365 | * Type 0 and 3 do not have a ref tag, so no remapping required. | |
366 | */ | |
367 | static void nvme_dif_remap(struct request *req, | |
368 | void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi)) | |
369 | { | |
370 | struct nvme_ns *ns = req->rq_disk->private_data; | |
371 | struct bio_integrity_payload *bip; | |
372 | struct t10_pi_tuple *pi; | |
373 | void *p, *pmap; | |
374 | u32 i, nlb, ts, phys, virt; | |
375 | ||
376 | if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3) | |
377 | return; | |
378 | ||
379 | bip = bio_integrity(req->bio); | |
380 | if (!bip) | |
381 | return; | |
382 | ||
383 | pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset; | |
e1e5e564 KB |
384 | |
385 | p = pmap; | |
386 | virt = bip_get_seed(bip); | |
387 | phys = nvme_block_nr(ns, blk_rq_pos(req)); | |
388 | nlb = (blk_rq_bytes(req) >> ns->lba_shift); | |
ac6fc48c | 389 | ts = ns->disk->queue->integrity.tuple_size; |
e1e5e564 KB |
390 | |
391 | for (i = 0; i < nlb; i++, virt++, phys++) { | |
392 | pi = (struct t10_pi_tuple *)p; | |
393 | dif_swap(phys, virt, pi); | |
394 | p += ts; | |
395 | } | |
396 | kunmap_atomic(pmap); | |
397 | } | |
52b68d7e KB |
398 | #else /* CONFIG_BLK_DEV_INTEGRITY */ |
399 | static void nvme_dif_remap(struct request *req, | |
400 | void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi)) | |
401 | { | |
402 | } | |
403 | static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi) | |
404 | { | |
405 | } | |
406 | static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi) | |
407 | { | |
408 | } | |
52b68d7e KB |
409 | #endif |
410 | ||
f4800d6d | 411 | static bool nvme_setup_prps(struct nvme_dev *dev, struct request *req, |
69d2b571 | 412 | int total_len) |
ff22b54f | 413 | { |
f4800d6d | 414 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
99802a7a | 415 | struct dma_pool *pool; |
eca18b23 MW |
416 | int length = total_len; |
417 | struct scatterlist *sg = iod->sg; | |
ff22b54f MW |
418 | int dma_len = sg_dma_len(sg); |
419 | u64 dma_addr = sg_dma_address(sg); | |
5fd4ce1b | 420 | u32 page_size = dev->ctrl.page_size; |
f137e0f1 | 421 | int offset = dma_addr & (page_size - 1); |
e025344c | 422 | __le64 *prp_list; |
f4800d6d | 423 | __le64 **list = iod_list(req); |
e025344c | 424 | dma_addr_t prp_dma; |
eca18b23 | 425 | int nprps, i; |
ff22b54f | 426 | |
1d090624 | 427 | length -= (page_size - offset); |
ff22b54f | 428 | if (length <= 0) |
69d2b571 | 429 | return true; |
ff22b54f | 430 | |
1d090624 | 431 | dma_len -= (page_size - offset); |
ff22b54f | 432 | if (dma_len) { |
1d090624 | 433 | dma_addr += (page_size - offset); |
ff22b54f MW |
434 | } else { |
435 | sg = sg_next(sg); | |
436 | dma_addr = sg_dma_address(sg); | |
437 | dma_len = sg_dma_len(sg); | |
438 | } | |
439 | ||
1d090624 | 440 | if (length <= page_size) { |
edd10d33 | 441 | iod->first_dma = dma_addr; |
69d2b571 | 442 | return true; |
e025344c SMM |
443 | } |
444 | ||
1d090624 | 445 | nprps = DIV_ROUND_UP(length, page_size); |
99802a7a MW |
446 | if (nprps <= (256 / 8)) { |
447 | pool = dev->prp_small_pool; | |
eca18b23 | 448 | iod->npages = 0; |
99802a7a MW |
449 | } else { |
450 | pool = dev->prp_page_pool; | |
eca18b23 | 451 | iod->npages = 1; |
99802a7a MW |
452 | } |
453 | ||
69d2b571 | 454 | prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); |
b77954cb | 455 | if (!prp_list) { |
edd10d33 | 456 | iod->first_dma = dma_addr; |
eca18b23 | 457 | iod->npages = -1; |
69d2b571 | 458 | return false; |
b77954cb | 459 | } |
eca18b23 MW |
460 | list[0] = prp_list; |
461 | iod->first_dma = prp_dma; | |
e025344c SMM |
462 | i = 0; |
463 | for (;;) { | |
1d090624 | 464 | if (i == page_size >> 3) { |
e025344c | 465 | __le64 *old_prp_list = prp_list; |
69d2b571 | 466 | prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); |
eca18b23 | 467 | if (!prp_list) |
69d2b571 | 468 | return false; |
eca18b23 | 469 | list[iod->npages++] = prp_list; |
7523d834 MW |
470 | prp_list[0] = old_prp_list[i - 1]; |
471 | old_prp_list[i - 1] = cpu_to_le64(prp_dma); | |
472 | i = 1; | |
e025344c SMM |
473 | } |
474 | prp_list[i++] = cpu_to_le64(dma_addr); | |
1d090624 KB |
475 | dma_len -= page_size; |
476 | dma_addr += page_size; | |
477 | length -= page_size; | |
e025344c SMM |
478 | if (length <= 0) |
479 | break; | |
480 | if (dma_len > 0) | |
481 | continue; | |
482 | BUG_ON(dma_len < 0); | |
483 | sg = sg_next(sg); | |
484 | dma_addr = sg_dma_address(sg); | |
485 | dma_len = sg_dma_len(sg); | |
ff22b54f MW |
486 | } |
487 | ||
69d2b571 | 488 | return true; |
ff22b54f MW |
489 | } |
490 | ||
f4800d6d | 491 | static int nvme_map_data(struct nvme_dev *dev, struct request *req, |
03b5929e | 492 | unsigned size, struct nvme_command *cmnd) |
d29ec824 | 493 | { |
f4800d6d | 494 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
ba1ca37e CH |
495 | struct request_queue *q = req->q; |
496 | enum dma_data_direction dma_dir = rq_data_dir(req) ? | |
497 | DMA_TO_DEVICE : DMA_FROM_DEVICE; | |
498 | int ret = BLK_MQ_RQ_QUEUE_ERROR; | |
d29ec824 | 499 | |
ba1ca37e CH |
500 | sg_init_table(iod->sg, req->nr_phys_segments); |
501 | iod->nents = blk_rq_map_sg(q, req, iod->sg); | |
502 | if (!iod->nents) | |
503 | goto out; | |
d29ec824 | 504 | |
ba1ca37e CH |
505 | ret = BLK_MQ_RQ_QUEUE_BUSY; |
506 | if (!dma_map_sg(dev->dev, iod->sg, iod->nents, dma_dir)) | |
507 | goto out; | |
d29ec824 | 508 | |
03b5929e | 509 | if (!nvme_setup_prps(dev, req, size)) |
ba1ca37e | 510 | goto out_unmap; |
0e5e4f0e | 511 | |
ba1ca37e CH |
512 | ret = BLK_MQ_RQ_QUEUE_ERROR; |
513 | if (blk_integrity_rq(req)) { | |
514 | if (blk_rq_count_integrity_sg(q, req->bio) != 1) | |
515 | goto out_unmap; | |
0e5e4f0e | 516 | |
bf684057 CH |
517 | sg_init_table(&iod->meta_sg, 1); |
518 | if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1) | |
ba1ca37e | 519 | goto out_unmap; |
0e5e4f0e | 520 | |
ba1ca37e CH |
521 | if (rq_data_dir(req)) |
522 | nvme_dif_remap(req, nvme_dif_prep); | |
0e5e4f0e | 523 | |
bf684057 | 524 | if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir)) |
ba1ca37e | 525 | goto out_unmap; |
d29ec824 | 526 | } |
00df5cb4 | 527 | |
eb793e2c CH |
528 | cmnd->rw.dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg)); |
529 | cmnd->rw.dptr.prp2 = cpu_to_le64(iod->first_dma); | |
ba1ca37e | 530 | if (blk_integrity_rq(req)) |
bf684057 | 531 | cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg)); |
ba1ca37e | 532 | return BLK_MQ_RQ_QUEUE_OK; |
00df5cb4 | 533 | |
ba1ca37e CH |
534 | out_unmap: |
535 | dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); | |
536 | out: | |
537 | return ret; | |
00df5cb4 MW |
538 | } |
539 | ||
f4800d6d | 540 | static void nvme_unmap_data(struct nvme_dev *dev, struct request *req) |
b60503ba | 541 | { |
f4800d6d | 542 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
d4f6c3ab CH |
543 | enum dma_data_direction dma_dir = rq_data_dir(req) ? |
544 | DMA_TO_DEVICE : DMA_FROM_DEVICE; | |
545 | ||
546 | if (iod->nents) { | |
547 | dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); | |
548 | if (blk_integrity_rq(req)) { | |
549 | if (!rq_data_dir(req)) | |
550 | nvme_dif_remap(req, nvme_dif_complete); | |
bf684057 | 551 | dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir); |
e1e5e564 | 552 | } |
e19b127f | 553 | } |
e1e5e564 | 554 | |
f4800d6d | 555 | nvme_free_iod(dev, req); |
d4f6c3ab | 556 | } |
b60503ba | 557 | |
d29ec824 CH |
558 | /* |
559 | * NOTE: ns is NULL when called on the admin queue. | |
560 | */ | |
a4aea562 MB |
561 | static int nvme_queue_rq(struct blk_mq_hw_ctx *hctx, |
562 | const struct blk_mq_queue_data *bd) | |
edd10d33 | 563 | { |
a4aea562 MB |
564 | struct nvme_ns *ns = hctx->queue->queuedata; |
565 | struct nvme_queue *nvmeq = hctx->driver_data; | |
d29ec824 | 566 | struct nvme_dev *dev = nvmeq->dev; |
a4aea562 | 567 | struct request *req = bd->rq; |
ba1ca37e | 568 | struct nvme_command cmnd; |
58b45602 | 569 | unsigned map_len; |
ba1ca37e | 570 | int ret = BLK_MQ_RQ_QUEUE_OK; |
edd10d33 | 571 | |
e1e5e564 KB |
572 | /* |
573 | * If formated with metadata, require the block layer provide a buffer | |
574 | * unless this namespace is formated such that the metadata can be | |
575 | * stripped/generated by the controller with PRACT=1. | |
576 | */ | |
d29ec824 | 577 | if (ns && ns->ms && !blk_integrity_rq(req)) { |
71feb364 KB |
578 | if (!(ns->pi_type && ns->ms == 8) && |
579 | req->cmd_type != REQ_TYPE_DRV_PRIV) { | |
eee417b0 | 580 | blk_mq_end_request(req, -EFAULT); |
e1e5e564 KB |
581 | return BLK_MQ_RQ_QUEUE_OK; |
582 | } | |
583 | } | |
584 | ||
58b45602 ML |
585 | map_len = nvme_map_len(req); |
586 | ret = nvme_init_iod(req, map_len, dev); | |
f4800d6d CH |
587 | if (ret) |
588 | return ret; | |
a4aea562 | 589 | |
8093f7ca | 590 | ret = nvme_setup_cmd(ns, req, &cmnd); |
03b5929e ML |
591 | if (ret) |
592 | goto out; | |
a4aea562 | 593 | |
03b5929e ML |
594 | if (req->nr_phys_segments) |
595 | ret = nvme_map_data(dev, req, map_len, &cmnd); | |
a4aea562 | 596 | |
ba1ca37e CH |
597 | if (ret) |
598 | goto out; | |
a4aea562 | 599 | |
ba1ca37e | 600 | cmnd.common.command_id = req->tag; |
aae239e1 | 601 | blk_mq_start_request(req); |
a4aea562 | 602 | |
ba1ca37e | 603 | spin_lock_irq(&nvmeq->q_lock); |
ae1fba20 | 604 | if (unlikely(nvmeq->cq_vector < 0)) { |
69d9a99c KB |
605 | if (ns && !test_bit(NVME_NS_DEAD, &ns->flags)) |
606 | ret = BLK_MQ_RQ_QUEUE_BUSY; | |
607 | else | |
608 | ret = BLK_MQ_RQ_QUEUE_ERROR; | |
ae1fba20 KB |
609 | spin_unlock_irq(&nvmeq->q_lock); |
610 | goto out; | |
611 | } | |
ba1ca37e | 612 | __nvme_submit_cmd(nvmeq, &cmnd); |
a4aea562 MB |
613 | nvme_process_cq(nvmeq); |
614 | spin_unlock_irq(&nvmeq->q_lock); | |
615 | return BLK_MQ_RQ_QUEUE_OK; | |
ba1ca37e | 616 | out: |
f4800d6d | 617 | nvme_free_iod(dev, req); |
ba1ca37e | 618 | return ret; |
b60503ba | 619 | } |
e1e5e564 | 620 | |
eee417b0 CH |
621 | static void nvme_complete_rq(struct request *req) |
622 | { | |
f4800d6d CH |
623 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
624 | struct nvme_dev *dev = iod->nvmeq->dev; | |
eee417b0 | 625 | int error = 0; |
e1e5e564 | 626 | |
f4800d6d | 627 | nvme_unmap_data(dev, req); |
e1e5e564 | 628 | |
eee417b0 CH |
629 | if (unlikely(req->errors)) { |
630 | if (nvme_req_needs_retry(req, req->errors)) { | |
f80ec966 | 631 | req->retries++; |
eee417b0 CH |
632 | nvme_requeue_req(req); |
633 | return; | |
e1e5e564 | 634 | } |
1974b1ae | 635 | |
eee417b0 CH |
636 | if (req->cmd_type == REQ_TYPE_DRV_PRIV) |
637 | error = req->errors; | |
638 | else | |
639 | error = nvme_error_status(req->errors); | |
640 | } | |
a4aea562 | 641 | |
f4800d6d | 642 | if (unlikely(iod->aborted)) { |
1b3c47c1 | 643 | dev_warn(dev->ctrl.device, |
eee417b0 CH |
644 | "completing aborted command with status: %04x\n", |
645 | req->errors); | |
646 | } | |
a4aea562 | 647 | |
eee417b0 | 648 | blk_mq_end_request(req, error); |
b60503ba MW |
649 | } |
650 | ||
d783e0bd MR |
651 | /* We read the CQE phase first to check if the rest of the entry is valid */ |
652 | static inline bool nvme_cqe_valid(struct nvme_queue *nvmeq, u16 head, | |
653 | u16 phase) | |
654 | { | |
655 | return (le16_to_cpu(nvmeq->cqes[head].status) & 1) == phase; | |
656 | } | |
657 | ||
a0fa9647 | 658 | static void __nvme_process_cq(struct nvme_queue *nvmeq, unsigned int *tag) |
b60503ba | 659 | { |
82123460 | 660 | u16 head, phase; |
b60503ba | 661 | |
b60503ba | 662 | head = nvmeq->cq_head; |
82123460 | 663 | phase = nvmeq->cq_phase; |
b60503ba | 664 | |
d783e0bd | 665 | while (nvme_cqe_valid(nvmeq, head, phase)) { |
b60503ba | 666 | struct nvme_completion cqe = nvmeq->cqes[head]; |
eee417b0 | 667 | struct request *req; |
adf68f21 | 668 | |
b60503ba MW |
669 | if (++head == nvmeq->q_depth) { |
670 | head = 0; | |
82123460 | 671 | phase = !phase; |
b60503ba | 672 | } |
adf68f21 | 673 | |
a0fa9647 JA |
674 | if (tag && *tag == cqe.command_id) |
675 | *tag = -1; | |
adf68f21 | 676 | |
aae239e1 | 677 | if (unlikely(cqe.command_id >= nvmeq->q_depth)) { |
1b3c47c1 | 678 | dev_warn(nvmeq->dev->ctrl.device, |
aae239e1 CH |
679 | "invalid id %d completed on queue %d\n", |
680 | cqe.command_id, le16_to_cpu(cqe.sq_id)); | |
681 | continue; | |
682 | } | |
683 | ||
adf68f21 CH |
684 | /* |
685 | * AEN requests are special as they don't time out and can | |
686 | * survive any kind of queue freeze and often don't respond to | |
687 | * aborts. We don't even bother to allocate a struct request | |
688 | * for them but rather special case them here. | |
689 | */ | |
690 | if (unlikely(nvmeq->qid == 0 && | |
691 | cqe.command_id >= NVME_AQ_BLKMQ_DEPTH)) { | |
f866fc42 | 692 | nvme_complete_async_event(&nvmeq->dev->ctrl, &cqe); |
adf68f21 CH |
693 | continue; |
694 | } | |
695 | ||
eee417b0 | 696 | req = blk_mq_tag_to_rq(*nvmeq->tags, cqe.command_id); |
1cb3cce5 CH |
697 | if (req->cmd_type == REQ_TYPE_DRV_PRIV && req->special) |
698 | memcpy(req->special, &cqe, sizeof(cqe)); | |
d783e0bd | 699 | blk_mq_complete_request(req, le16_to_cpu(cqe.status) >> 1); |
eee417b0 | 700 | |
b60503ba MW |
701 | } |
702 | ||
703 | /* If the controller ignores the cq head doorbell and continuously | |
704 | * writes to the queue, it is theoretically possible to wrap around | |
705 | * the queue twice and mistakenly return IRQ_NONE. Linux only | |
706 | * requires that 0.1% of your interrupts are handled, so this isn't | |
707 | * a big problem. | |
708 | */ | |
82123460 | 709 | if (head == nvmeq->cq_head && phase == nvmeq->cq_phase) |
a0fa9647 | 710 | return; |
b60503ba | 711 | |
604e8c8d KB |
712 | if (likely(nvmeq->cq_vector >= 0)) |
713 | writel(head, nvmeq->q_db + nvmeq->dev->db_stride); | |
b60503ba | 714 | nvmeq->cq_head = head; |
82123460 | 715 | nvmeq->cq_phase = phase; |
b60503ba | 716 | |
e9539f47 | 717 | nvmeq->cqe_seen = 1; |
a0fa9647 JA |
718 | } |
719 | ||
720 | static void nvme_process_cq(struct nvme_queue *nvmeq) | |
721 | { | |
722 | __nvme_process_cq(nvmeq, NULL); | |
b60503ba MW |
723 | } |
724 | ||
725 | static irqreturn_t nvme_irq(int irq, void *data) | |
58ffacb5 MW |
726 | { |
727 | irqreturn_t result; | |
728 | struct nvme_queue *nvmeq = data; | |
729 | spin_lock(&nvmeq->q_lock); | |
e9539f47 MW |
730 | nvme_process_cq(nvmeq); |
731 | result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE; | |
732 | nvmeq->cqe_seen = 0; | |
58ffacb5 MW |
733 | spin_unlock(&nvmeq->q_lock); |
734 | return result; | |
735 | } | |
736 | ||
737 | static irqreturn_t nvme_irq_check(int irq, void *data) | |
738 | { | |
739 | struct nvme_queue *nvmeq = data; | |
d783e0bd MR |
740 | if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase)) |
741 | return IRQ_WAKE_THREAD; | |
742 | return IRQ_NONE; | |
58ffacb5 MW |
743 | } |
744 | ||
a0fa9647 JA |
745 | static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag) |
746 | { | |
747 | struct nvme_queue *nvmeq = hctx->driver_data; | |
748 | ||
d783e0bd | 749 | if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase)) { |
a0fa9647 JA |
750 | spin_lock_irq(&nvmeq->q_lock); |
751 | __nvme_process_cq(nvmeq, &tag); | |
752 | spin_unlock_irq(&nvmeq->q_lock); | |
753 | ||
754 | if (tag == -1) | |
755 | return 1; | |
756 | } | |
757 | ||
758 | return 0; | |
759 | } | |
760 | ||
f866fc42 | 761 | static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl, int aer_idx) |
b60503ba | 762 | { |
f866fc42 | 763 | struct nvme_dev *dev = to_nvme_dev(ctrl); |
9396dec9 | 764 | struct nvme_queue *nvmeq = dev->queues[0]; |
a4aea562 | 765 | struct nvme_command c; |
b60503ba | 766 | |
a4aea562 MB |
767 | memset(&c, 0, sizeof(c)); |
768 | c.common.opcode = nvme_admin_async_event; | |
f866fc42 | 769 | c.common.command_id = NVME_AQ_BLKMQ_DEPTH + aer_idx; |
3c0cf138 | 770 | |
9396dec9 | 771 | spin_lock_irq(&nvmeq->q_lock); |
f866fc42 | 772 | __nvme_submit_cmd(nvmeq, &c); |
9396dec9 | 773 | spin_unlock_irq(&nvmeq->q_lock); |
f705f837 CH |
774 | } |
775 | ||
b60503ba | 776 | static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) |
f705f837 | 777 | { |
b60503ba MW |
778 | struct nvme_command c; |
779 | ||
780 | memset(&c, 0, sizeof(c)); | |
781 | c.delete_queue.opcode = opcode; | |
782 | c.delete_queue.qid = cpu_to_le16(id); | |
783 | ||
1c63dc66 | 784 | return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); |
b60503ba MW |
785 | } |
786 | ||
b60503ba MW |
787 | static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, |
788 | struct nvme_queue *nvmeq) | |
789 | { | |
b60503ba MW |
790 | struct nvme_command c; |
791 | int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED; | |
792 | ||
d29ec824 CH |
793 | /* |
794 | * Note: we (ab)use the fact the the prp fields survive if no data | |
795 | * is attached to the request. | |
796 | */ | |
b60503ba MW |
797 | memset(&c, 0, sizeof(c)); |
798 | c.create_cq.opcode = nvme_admin_create_cq; | |
799 | c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); | |
800 | c.create_cq.cqid = cpu_to_le16(qid); | |
801 | c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); | |
802 | c.create_cq.cq_flags = cpu_to_le16(flags); | |
803 | c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector); | |
804 | ||
1c63dc66 | 805 | return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); |
b60503ba MW |
806 | } |
807 | ||
808 | static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, | |
809 | struct nvme_queue *nvmeq) | |
810 | { | |
b60503ba MW |
811 | struct nvme_command c; |
812 | int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM; | |
813 | ||
d29ec824 CH |
814 | /* |
815 | * Note: we (ab)use the fact the the prp fields survive if no data | |
816 | * is attached to the request. | |
817 | */ | |
b60503ba MW |
818 | memset(&c, 0, sizeof(c)); |
819 | c.create_sq.opcode = nvme_admin_create_sq; | |
820 | c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); | |
821 | c.create_sq.sqid = cpu_to_le16(qid); | |
822 | c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); | |
823 | c.create_sq.sq_flags = cpu_to_le16(flags); | |
824 | c.create_sq.cqid = cpu_to_le16(qid); | |
825 | ||
1c63dc66 | 826 | return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); |
b60503ba MW |
827 | } |
828 | ||
829 | static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) | |
830 | { | |
831 | return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); | |
832 | } | |
833 | ||
834 | static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) | |
835 | { | |
836 | return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); | |
837 | } | |
838 | ||
e7a2a87d | 839 | static void abort_endio(struct request *req, int error) |
bc5fc7e4 | 840 | { |
f4800d6d CH |
841 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
842 | struct nvme_queue *nvmeq = iod->nvmeq; | |
e7a2a87d | 843 | u16 status = req->errors; |
e44ac588 | 844 | |
1cb3cce5 | 845 | dev_warn(nvmeq->dev->ctrl.device, "Abort status: 0x%x", status); |
e7a2a87d | 846 | atomic_inc(&nvmeq->dev->ctrl.abort_limit); |
e7a2a87d | 847 | blk_mq_free_request(req); |
bc5fc7e4 MW |
848 | } |
849 | ||
31c7c7d2 | 850 | static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved) |
c30341dc | 851 | { |
f4800d6d CH |
852 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
853 | struct nvme_queue *nvmeq = iod->nvmeq; | |
c30341dc | 854 | struct nvme_dev *dev = nvmeq->dev; |
a4aea562 | 855 | struct request *abort_req; |
a4aea562 | 856 | struct nvme_command cmd; |
c30341dc | 857 | |
31c7c7d2 | 858 | /* |
fd634f41 CH |
859 | * Shutdown immediately if controller times out while starting. The |
860 | * reset work will see the pci device disabled when it gets the forced | |
861 | * cancellation error. All outstanding requests are completed on | |
862 | * shutdown, so we return BLK_EH_HANDLED. | |
863 | */ | |
bb8d261e | 864 | if (dev->ctrl.state == NVME_CTRL_RESETTING) { |
1b3c47c1 | 865 | dev_warn(dev->ctrl.device, |
fd634f41 CH |
866 | "I/O %d QID %d timeout, disable controller\n", |
867 | req->tag, nvmeq->qid); | |
a5cdb68c | 868 | nvme_dev_disable(dev, false); |
fd634f41 CH |
869 | req->errors = NVME_SC_CANCELLED; |
870 | return BLK_EH_HANDLED; | |
c30341dc KB |
871 | } |
872 | ||
fd634f41 CH |
873 | /* |
874 | * Shutdown the controller immediately and schedule a reset if the | |
875 | * command was already aborted once before and still hasn't been | |
876 | * returned to the driver, or if this is the admin queue. | |
31c7c7d2 | 877 | */ |
f4800d6d | 878 | if (!nvmeq->qid || iod->aborted) { |
1b3c47c1 | 879 | dev_warn(dev->ctrl.device, |
e1569a16 KB |
880 | "I/O %d QID %d timeout, reset controller\n", |
881 | req->tag, nvmeq->qid); | |
a5cdb68c | 882 | nvme_dev_disable(dev, false); |
e1569a16 | 883 | queue_work(nvme_workq, &dev->reset_work); |
c30341dc | 884 | |
e1569a16 KB |
885 | /* |
886 | * Mark the request as handled, since the inline shutdown | |
887 | * forces all outstanding requests to complete. | |
888 | */ | |
889 | req->errors = NVME_SC_CANCELLED; | |
890 | return BLK_EH_HANDLED; | |
c30341dc | 891 | } |
c30341dc | 892 | |
f4800d6d | 893 | iod->aborted = 1; |
c30341dc | 894 | |
e7a2a87d | 895 | if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) { |
6bf25d16 | 896 | atomic_inc(&dev->ctrl.abort_limit); |
31c7c7d2 | 897 | return BLK_EH_RESET_TIMER; |
6bf25d16 | 898 | } |
a4aea562 | 899 | |
c30341dc KB |
900 | memset(&cmd, 0, sizeof(cmd)); |
901 | cmd.abort.opcode = nvme_admin_abort_cmd; | |
a4aea562 | 902 | cmd.abort.cid = req->tag; |
c30341dc | 903 | cmd.abort.sqid = cpu_to_le16(nvmeq->qid); |
c30341dc | 904 | |
1b3c47c1 SG |
905 | dev_warn(nvmeq->dev->ctrl.device, |
906 | "I/O %d QID %d timeout, aborting\n", | |
907 | req->tag, nvmeq->qid); | |
e7a2a87d CH |
908 | |
909 | abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd, | |
eb71f435 | 910 | BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); |
e7a2a87d CH |
911 | if (IS_ERR(abort_req)) { |
912 | atomic_inc(&dev->ctrl.abort_limit); | |
913 | return BLK_EH_RESET_TIMER; | |
914 | } | |
915 | ||
916 | abort_req->timeout = ADMIN_TIMEOUT; | |
917 | abort_req->end_io_data = NULL; | |
918 | blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio); | |
c30341dc | 919 | |
31c7c7d2 CH |
920 | /* |
921 | * The aborted req will be completed on receiving the abort req. | |
922 | * We enable the timer again. If hit twice, it'll cause a device reset, | |
923 | * as the device then is in a faulty state. | |
924 | */ | |
925 | return BLK_EH_RESET_TIMER; | |
c30341dc KB |
926 | } |
927 | ||
a4aea562 MB |
928 | static void nvme_free_queue(struct nvme_queue *nvmeq) |
929 | { | |
9e866774 MW |
930 | dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth), |
931 | (void *)nvmeq->cqes, nvmeq->cq_dma_addr); | |
8ffaadf7 JD |
932 | if (nvmeq->sq_cmds) |
933 | dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth), | |
9e866774 MW |
934 | nvmeq->sq_cmds, nvmeq->sq_dma_addr); |
935 | kfree(nvmeq); | |
936 | } | |
937 | ||
a1a5ef99 | 938 | static void nvme_free_queues(struct nvme_dev *dev, int lowest) |
22404274 KB |
939 | { |
940 | int i; | |
941 | ||
a1a5ef99 | 942 | for (i = dev->queue_count - 1; i >= lowest; i--) { |
a4aea562 | 943 | struct nvme_queue *nvmeq = dev->queues[i]; |
22404274 | 944 | dev->queue_count--; |
a4aea562 | 945 | dev->queues[i] = NULL; |
f435c282 | 946 | nvme_free_queue(nvmeq); |
121c7ad4 | 947 | } |
22404274 KB |
948 | } |
949 | ||
4d115420 KB |
950 | /** |
951 | * nvme_suspend_queue - put queue into suspended state | |
952 | * @nvmeq - queue to suspend | |
4d115420 KB |
953 | */ |
954 | static int nvme_suspend_queue(struct nvme_queue *nvmeq) | |
b60503ba | 955 | { |
2b25d981 | 956 | int vector; |
b60503ba | 957 | |
a09115b2 | 958 | spin_lock_irq(&nvmeq->q_lock); |
2b25d981 KB |
959 | if (nvmeq->cq_vector == -1) { |
960 | spin_unlock_irq(&nvmeq->q_lock); | |
961 | return 1; | |
962 | } | |
963 | vector = nvmeq->dev->entry[nvmeq->cq_vector].vector; | |
42f61420 | 964 | nvmeq->dev->online_queues--; |
2b25d981 | 965 | nvmeq->cq_vector = -1; |
a09115b2 MW |
966 | spin_unlock_irq(&nvmeq->q_lock); |
967 | ||
1c63dc66 | 968 | if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q) |
25646264 | 969 | blk_mq_stop_hw_queues(nvmeq->dev->ctrl.admin_q); |
6df3dbc8 | 970 | |
aba2080f MW |
971 | irq_set_affinity_hint(vector, NULL); |
972 | free_irq(vector, nvmeq); | |
b60503ba | 973 | |
4d115420 KB |
974 | return 0; |
975 | } | |
b60503ba | 976 | |
a5cdb68c | 977 | static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown) |
4d115420 | 978 | { |
a5cdb68c | 979 | struct nvme_queue *nvmeq = dev->queues[0]; |
4d115420 KB |
980 | |
981 | if (!nvmeq) | |
982 | return; | |
983 | if (nvme_suspend_queue(nvmeq)) | |
984 | return; | |
985 | ||
a5cdb68c KB |
986 | if (shutdown) |
987 | nvme_shutdown_ctrl(&dev->ctrl); | |
988 | else | |
989 | nvme_disable_ctrl(&dev->ctrl, lo_hi_readq( | |
990 | dev->bar + NVME_REG_CAP)); | |
07836e65 KB |
991 | |
992 | spin_lock_irq(&nvmeq->q_lock); | |
993 | nvme_process_cq(nvmeq); | |
994 | spin_unlock_irq(&nvmeq->q_lock); | |
b60503ba MW |
995 | } |
996 | ||
8ffaadf7 JD |
997 | static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues, |
998 | int entry_size) | |
999 | { | |
1000 | int q_depth = dev->q_depth; | |
5fd4ce1b CH |
1001 | unsigned q_size_aligned = roundup(q_depth * entry_size, |
1002 | dev->ctrl.page_size); | |
8ffaadf7 JD |
1003 | |
1004 | if (q_size_aligned * nr_io_queues > dev->cmb_size) { | |
c45f5c99 | 1005 | u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues); |
5fd4ce1b | 1006 | mem_per_q = round_down(mem_per_q, dev->ctrl.page_size); |
c45f5c99 | 1007 | q_depth = div_u64(mem_per_q, entry_size); |
8ffaadf7 JD |
1008 | |
1009 | /* | |
1010 | * Ensure the reduced q_depth is above some threshold where it | |
1011 | * would be better to map queues in system memory with the | |
1012 | * original depth | |
1013 | */ | |
1014 | if (q_depth < 64) | |
1015 | return -ENOMEM; | |
1016 | } | |
1017 | ||
1018 | return q_depth; | |
1019 | } | |
1020 | ||
1021 | static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq, | |
1022 | int qid, int depth) | |
1023 | { | |
1024 | if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz)) { | |
5fd4ce1b CH |
1025 | unsigned offset = (qid - 1) * roundup(SQ_SIZE(depth), |
1026 | dev->ctrl.page_size); | |
8ffaadf7 JD |
1027 | nvmeq->sq_dma_addr = dev->cmb_dma_addr + offset; |
1028 | nvmeq->sq_cmds_io = dev->cmb + offset; | |
1029 | } else { | |
1030 | nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth), | |
1031 | &nvmeq->sq_dma_addr, GFP_KERNEL); | |
1032 | if (!nvmeq->sq_cmds) | |
1033 | return -ENOMEM; | |
1034 | } | |
1035 | ||
1036 | return 0; | |
1037 | } | |
1038 | ||
b60503ba | 1039 | static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid, |
2b25d981 | 1040 | int depth) |
b60503ba | 1041 | { |
a4aea562 | 1042 | struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq), GFP_KERNEL); |
b60503ba MW |
1043 | if (!nvmeq) |
1044 | return NULL; | |
1045 | ||
e75ec752 | 1046 | nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth), |
4d51abf9 | 1047 | &nvmeq->cq_dma_addr, GFP_KERNEL); |
b60503ba MW |
1048 | if (!nvmeq->cqes) |
1049 | goto free_nvmeq; | |
b60503ba | 1050 | |
8ffaadf7 | 1051 | if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth)) |
b60503ba MW |
1052 | goto free_cqdma; |
1053 | ||
e75ec752 | 1054 | nvmeq->q_dmadev = dev->dev; |
091b6092 | 1055 | nvmeq->dev = dev; |
3193f07b | 1056 | snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d", |
1c63dc66 | 1057 | dev->ctrl.instance, qid); |
b60503ba MW |
1058 | spin_lock_init(&nvmeq->q_lock); |
1059 | nvmeq->cq_head = 0; | |
82123460 | 1060 | nvmeq->cq_phase = 1; |
b80d5ccc | 1061 | nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; |
b60503ba | 1062 | nvmeq->q_depth = depth; |
c30341dc | 1063 | nvmeq->qid = qid; |
758dd7fd | 1064 | nvmeq->cq_vector = -1; |
a4aea562 | 1065 | dev->queues[qid] = nvmeq; |
36a7e993 JD |
1066 | dev->queue_count++; |
1067 | ||
b60503ba MW |
1068 | return nvmeq; |
1069 | ||
1070 | free_cqdma: | |
e75ec752 | 1071 | dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes, |
b60503ba MW |
1072 | nvmeq->cq_dma_addr); |
1073 | free_nvmeq: | |
1074 | kfree(nvmeq); | |
1075 | return NULL; | |
1076 | } | |
1077 | ||
3001082c MW |
1078 | static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq, |
1079 | const char *name) | |
1080 | { | |
58ffacb5 MW |
1081 | if (use_threaded_interrupts) |
1082 | return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector, | |
481e5bad | 1083 | nvme_irq_check, nvme_irq, IRQF_SHARED, |
58ffacb5 | 1084 | name, nvmeq); |
3001082c | 1085 | return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq, |
481e5bad | 1086 | IRQF_SHARED, name, nvmeq); |
3001082c MW |
1087 | } |
1088 | ||
22404274 | 1089 | static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) |
b60503ba | 1090 | { |
22404274 | 1091 | struct nvme_dev *dev = nvmeq->dev; |
b60503ba | 1092 | |
7be50e93 | 1093 | spin_lock_irq(&nvmeq->q_lock); |
22404274 KB |
1094 | nvmeq->sq_tail = 0; |
1095 | nvmeq->cq_head = 0; | |
1096 | nvmeq->cq_phase = 1; | |
b80d5ccc | 1097 | nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; |
22404274 | 1098 | memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth)); |
42f61420 | 1099 | dev->online_queues++; |
7be50e93 | 1100 | spin_unlock_irq(&nvmeq->q_lock); |
22404274 KB |
1101 | } |
1102 | ||
1103 | static int nvme_create_queue(struct nvme_queue *nvmeq, int qid) | |
1104 | { | |
1105 | struct nvme_dev *dev = nvmeq->dev; | |
1106 | int result; | |
3f85d50b | 1107 | |
2b25d981 | 1108 | nvmeq->cq_vector = qid - 1; |
b60503ba MW |
1109 | result = adapter_alloc_cq(dev, qid, nvmeq); |
1110 | if (result < 0) | |
22404274 | 1111 | return result; |
b60503ba MW |
1112 | |
1113 | result = adapter_alloc_sq(dev, qid, nvmeq); | |
1114 | if (result < 0) | |
1115 | goto release_cq; | |
1116 | ||
3193f07b | 1117 | result = queue_request_irq(dev, nvmeq, nvmeq->irqname); |
b60503ba MW |
1118 | if (result < 0) |
1119 | goto release_sq; | |
1120 | ||
22404274 | 1121 | nvme_init_queue(nvmeq, qid); |
22404274 | 1122 | return result; |
b60503ba MW |
1123 | |
1124 | release_sq: | |
1125 | adapter_delete_sq(dev, qid); | |
1126 | release_cq: | |
1127 | adapter_delete_cq(dev, qid); | |
22404274 | 1128 | return result; |
b60503ba MW |
1129 | } |
1130 | ||
a4aea562 | 1131 | static struct blk_mq_ops nvme_mq_admin_ops = { |
d29ec824 | 1132 | .queue_rq = nvme_queue_rq, |
eee417b0 | 1133 | .complete = nvme_complete_rq, |
a4aea562 | 1134 | .init_hctx = nvme_admin_init_hctx, |
4af0e21c | 1135 | .exit_hctx = nvme_admin_exit_hctx, |
a4aea562 MB |
1136 | .init_request = nvme_admin_init_request, |
1137 | .timeout = nvme_timeout, | |
1138 | }; | |
1139 | ||
1140 | static struct blk_mq_ops nvme_mq_ops = { | |
1141 | .queue_rq = nvme_queue_rq, | |
eee417b0 | 1142 | .complete = nvme_complete_rq, |
a4aea562 MB |
1143 | .init_hctx = nvme_init_hctx, |
1144 | .init_request = nvme_init_request, | |
1145 | .timeout = nvme_timeout, | |
a0fa9647 | 1146 | .poll = nvme_poll, |
a4aea562 MB |
1147 | }; |
1148 | ||
ea191d2f KB |
1149 | static void nvme_dev_remove_admin(struct nvme_dev *dev) |
1150 | { | |
1c63dc66 | 1151 | if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) { |
69d9a99c KB |
1152 | /* |
1153 | * If the controller was reset during removal, it's possible | |
1154 | * user requests may be waiting on a stopped queue. Start the | |
1155 | * queue to flush these to completion. | |
1156 | */ | |
1157 | blk_mq_start_stopped_hw_queues(dev->ctrl.admin_q, true); | |
1c63dc66 | 1158 | blk_cleanup_queue(dev->ctrl.admin_q); |
ea191d2f KB |
1159 | blk_mq_free_tag_set(&dev->admin_tagset); |
1160 | } | |
1161 | } | |
1162 | ||
a4aea562 MB |
1163 | static int nvme_alloc_admin_tags(struct nvme_dev *dev) |
1164 | { | |
1c63dc66 | 1165 | if (!dev->ctrl.admin_q) { |
a4aea562 MB |
1166 | dev->admin_tagset.ops = &nvme_mq_admin_ops; |
1167 | dev->admin_tagset.nr_hw_queues = 1; | |
e3e9d50c KB |
1168 | |
1169 | /* | |
1170 | * Subtract one to leave an empty queue entry for 'Full Queue' | |
1171 | * condition. See NVM-Express 1.2 specification, section 4.1.2. | |
1172 | */ | |
1173 | dev->admin_tagset.queue_depth = NVME_AQ_BLKMQ_DEPTH - 1; | |
a4aea562 | 1174 | dev->admin_tagset.timeout = ADMIN_TIMEOUT; |
e75ec752 | 1175 | dev->admin_tagset.numa_node = dev_to_node(dev->dev); |
ac3dd5bd | 1176 | dev->admin_tagset.cmd_size = nvme_cmd_size(dev); |
a4aea562 MB |
1177 | dev->admin_tagset.driver_data = dev; |
1178 | ||
1179 | if (blk_mq_alloc_tag_set(&dev->admin_tagset)) | |
1180 | return -ENOMEM; | |
1181 | ||
1c63dc66 CH |
1182 | dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset); |
1183 | if (IS_ERR(dev->ctrl.admin_q)) { | |
a4aea562 MB |
1184 | blk_mq_free_tag_set(&dev->admin_tagset); |
1185 | return -ENOMEM; | |
1186 | } | |
1c63dc66 | 1187 | if (!blk_get_queue(dev->ctrl.admin_q)) { |
ea191d2f | 1188 | nvme_dev_remove_admin(dev); |
1c63dc66 | 1189 | dev->ctrl.admin_q = NULL; |
ea191d2f KB |
1190 | return -ENODEV; |
1191 | } | |
0fb59cbc | 1192 | } else |
25646264 | 1193 | blk_mq_start_stopped_hw_queues(dev->ctrl.admin_q, true); |
a4aea562 MB |
1194 | |
1195 | return 0; | |
1196 | } | |
1197 | ||
8d85fce7 | 1198 | static int nvme_configure_admin_queue(struct nvme_dev *dev) |
b60503ba | 1199 | { |
ba47e386 | 1200 | int result; |
b60503ba | 1201 | u32 aqa; |
7a67cbea | 1202 | u64 cap = lo_hi_readq(dev->bar + NVME_REG_CAP); |
b60503ba MW |
1203 | struct nvme_queue *nvmeq; |
1204 | ||
7a67cbea | 1205 | dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1) ? |
dfbac8c7 KB |
1206 | NVME_CAP_NSSRC(cap) : 0; |
1207 | ||
7a67cbea CH |
1208 | if (dev->subsystem && |
1209 | (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO)) | |
1210 | writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS); | |
dfbac8c7 | 1211 | |
5fd4ce1b | 1212 | result = nvme_disable_ctrl(&dev->ctrl, cap); |
ba47e386 MW |
1213 | if (result < 0) |
1214 | return result; | |
b60503ba | 1215 | |
a4aea562 | 1216 | nvmeq = dev->queues[0]; |
cd638946 | 1217 | if (!nvmeq) { |
2b25d981 | 1218 | nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH); |
cd638946 KB |
1219 | if (!nvmeq) |
1220 | return -ENOMEM; | |
cd638946 | 1221 | } |
b60503ba MW |
1222 | |
1223 | aqa = nvmeq->q_depth - 1; | |
1224 | aqa |= aqa << 16; | |
1225 | ||
7a67cbea CH |
1226 | writel(aqa, dev->bar + NVME_REG_AQA); |
1227 | lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ); | |
1228 | lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ); | |
b60503ba | 1229 | |
5fd4ce1b | 1230 | result = nvme_enable_ctrl(&dev->ctrl, cap); |
025c557a | 1231 | if (result) |
a4aea562 MB |
1232 | goto free_nvmeq; |
1233 | ||
2b25d981 | 1234 | nvmeq->cq_vector = 0; |
3193f07b | 1235 | result = queue_request_irq(dev, nvmeq, nvmeq->irqname); |
758dd7fd JD |
1236 | if (result) { |
1237 | nvmeq->cq_vector = -1; | |
0fb59cbc | 1238 | goto free_nvmeq; |
758dd7fd | 1239 | } |
025c557a | 1240 | |
b60503ba | 1241 | return result; |
a4aea562 | 1242 | |
a4aea562 MB |
1243 | free_nvmeq: |
1244 | nvme_free_queues(dev, 0); | |
1245 | return result; | |
b60503ba MW |
1246 | } |
1247 | ||
c875a709 GP |
1248 | static bool nvme_should_reset(struct nvme_dev *dev, u32 csts) |
1249 | { | |
1250 | ||
1251 | /* If true, indicates loss of adapter communication, possibly by a | |
1252 | * NVMe Subsystem reset. | |
1253 | */ | |
1254 | bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO); | |
1255 | ||
1256 | /* If there is a reset ongoing, we shouldn't reset again. */ | |
1257 | if (work_busy(&dev->reset_work)) | |
1258 | return false; | |
1259 | ||
1260 | /* We shouldn't reset unless the controller is on fatal error state | |
1261 | * _or_ if we lost the communication with it. | |
1262 | */ | |
1263 | if (!(csts & NVME_CSTS_CFS) && !nssro) | |
1264 | return false; | |
1265 | ||
1266 | /* If PCI error recovery process is happening, we cannot reset or | |
1267 | * the recovery mechanism will surely fail. | |
1268 | */ | |
1269 | if (pci_channel_offline(to_pci_dev(dev->dev))) | |
1270 | return false; | |
1271 | ||
1272 | return true; | |
1273 | } | |
1274 | ||
2d55cd5f | 1275 | static void nvme_watchdog_timer(unsigned long data) |
1fa6aead | 1276 | { |
2d55cd5f CH |
1277 | struct nvme_dev *dev = (struct nvme_dev *)data; |
1278 | u32 csts = readl(dev->bar + NVME_REG_CSTS); | |
1fa6aead | 1279 | |
c875a709 GP |
1280 | /* Skip controllers under certain specific conditions. */ |
1281 | if (nvme_should_reset(dev, csts)) { | |
1282 | if (queue_work(nvme_workq, &dev->reset_work)) | |
2d55cd5f CH |
1283 | dev_warn(dev->dev, |
1284 | "Failed status: 0x%x, reset controller.\n", | |
1285 | csts); | |
2d55cd5f | 1286 | return; |
1fa6aead | 1287 | } |
2d55cd5f CH |
1288 | |
1289 | mod_timer(&dev->watchdog_timer, round_jiffies(jiffies + HZ)); | |
1fa6aead MW |
1290 | } |
1291 | ||
749941f2 | 1292 | static int nvme_create_io_queues(struct nvme_dev *dev) |
42f61420 | 1293 | { |
949928c1 | 1294 | unsigned i, max; |
749941f2 | 1295 | int ret = 0; |
42f61420 | 1296 | |
749941f2 CH |
1297 | for (i = dev->queue_count; i <= dev->max_qid; i++) { |
1298 | if (!nvme_alloc_queue(dev, i, dev->q_depth)) { | |
1299 | ret = -ENOMEM; | |
42f61420 | 1300 | break; |
749941f2 CH |
1301 | } |
1302 | } | |
42f61420 | 1303 | |
949928c1 KB |
1304 | max = min(dev->max_qid, dev->queue_count - 1); |
1305 | for (i = dev->online_queues; i <= max; i++) { | |
749941f2 CH |
1306 | ret = nvme_create_queue(dev->queues[i], i); |
1307 | if (ret) { | |
2659e57b | 1308 | nvme_free_queues(dev, i); |
42f61420 | 1309 | break; |
2659e57b | 1310 | } |
27e8166c | 1311 | } |
749941f2 CH |
1312 | |
1313 | /* | |
1314 | * Ignore failing Create SQ/CQ commands, we can continue with less | |
1315 | * than the desired aount of queues, and even a controller without | |
1316 | * I/O queues an still be used to issue admin commands. This might | |
1317 | * be useful to upgrade a buggy firmware for example. | |
1318 | */ | |
1319 | return ret >= 0 ? 0 : ret; | |
b60503ba MW |
1320 | } |
1321 | ||
8ffaadf7 JD |
1322 | static void __iomem *nvme_map_cmb(struct nvme_dev *dev) |
1323 | { | |
1324 | u64 szu, size, offset; | |
1325 | u32 cmbloc; | |
1326 | resource_size_t bar_size; | |
1327 | struct pci_dev *pdev = to_pci_dev(dev->dev); | |
1328 | void __iomem *cmb; | |
1329 | dma_addr_t dma_addr; | |
1330 | ||
1331 | if (!use_cmb_sqes) | |
1332 | return NULL; | |
1333 | ||
7a67cbea | 1334 | dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ); |
8ffaadf7 JD |
1335 | if (!(NVME_CMB_SZ(dev->cmbsz))) |
1336 | return NULL; | |
1337 | ||
7a67cbea | 1338 | cmbloc = readl(dev->bar + NVME_REG_CMBLOC); |
8ffaadf7 JD |
1339 | |
1340 | szu = (u64)1 << (12 + 4 * NVME_CMB_SZU(dev->cmbsz)); | |
1341 | size = szu * NVME_CMB_SZ(dev->cmbsz); | |
1342 | offset = szu * NVME_CMB_OFST(cmbloc); | |
1343 | bar_size = pci_resource_len(pdev, NVME_CMB_BIR(cmbloc)); | |
1344 | ||
1345 | if (offset > bar_size) | |
1346 | return NULL; | |
1347 | ||
1348 | /* | |
1349 | * Controllers may support a CMB size larger than their BAR, | |
1350 | * for example, due to being behind a bridge. Reduce the CMB to | |
1351 | * the reported size of the BAR | |
1352 | */ | |
1353 | if (size > bar_size - offset) | |
1354 | size = bar_size - offset; | |
1355 | ||
1356 | dma_addr = pci_resource_start(pdev, NVME_CMB_BIR(cmbloc)) + offset; | |
1357 | cmb = ioremap_wc(dma_addr, size); | |
1358 | if (!cmb) | |
1359 | return NULL; | |
1360 | ||
1361 | dev->cmb_dma_addr = dma_addr; | |
1362 | dev->cmb_size = size; | |
1363 | return cmb; | |
1364 | } | |
1365 | ||
1366 | static inline void nvme_release_cmb(struct nvme_dev *dev) | |
1367 | { | |
1368 | if (dev->cmb) { | |
1369 | iounmap(dev->cmb); | |
1370 | dev->cmb = NULL; | |
1371 | } | |
1372 | } | |
1373 | ||
9d713c2b KB |
1374 | static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) |
1375 | { | |
b80d5ccc | 1376 | return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride); |
9d713c2b KB |
1377 | } |
1378 | ||
8d85fce7 | 1379 | static int nvme_setup_io_queues(struct nvme_dev *dev) |
b60503ba | 1380 | { |
a4aea562 | 1381 | struct nvme_queue *adminq = dev->queues[0]; |
e75ec752 | 1382 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
42f61420 | 1383 | int result, i, vecs, nr_io_queues, size; |
b60503ba | 1384 | |
2800b8e7 | 1385 | nr_io_queues = num_online_cpus(); |
9a0be7ab CH |
1386 | result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues); |
1387 | if (result < 0) | |
1b23484b | 1388 | return result; |
9a0be7ab | 1389 | |
f5fa90dc | 1390 | if (nr_io_queues == 0) |
a5229050 | 1391 | return 0; |
b60503ba | 1392 | |
8ffaadf7 JD |
1393 | if (dev->cmb && NVME_CMB_SQS(dev->cmbsz)) { |
1394 | result = nvme_cmb_qdepth(dev, nr_io_queues, | |
1395 | sizeof(struct nvme_command)); | |
1396 | if (result > 0) | |
1397 | dev->q_depth = result; | |
1398 | else | |
1399 | nvme_release_cmb(dev); | |
1400 | } | |
1401 | ||
9d713c2b KB |
1402 | size = db_bar_size(dev, nr_io_queues); |
1403 | if (size > 8192) { | |
f1938f6e | 1404 | iounmap(dev->bar); |
9d713c2b KB |
1405 | do { |
1406 | dev->bar = ioremap(pci_resource_start(pdev, 0), size); | |
1407 | if (dev->bar) | |
1408 | break; | |
1409 | if (!--nr_io_queues) | |
1410 | return -ENOMEM; | |
1411 | size = db_bar_size(dev, nr_io_queues); | |
1412 | } while (1); | |
7a67cbea | 1413 | dev->dbs = dev->bar + 4096; |
5a92e700 | 1414 | adminq->q_db = dev->dbs; |
f1938f6e MW |
1415 | } |
1416 | ||
9d713c2b | 1417 | /* Deregister the admin queue's interrupt */ |
3193f07b | 1418 | free_irq(dev->entry[0].vector, adminq); |
9d713c2b | 1419 | |
e32efbfc JA |
1420 | /* |
1421 | * If we enable msix early due to not intx, disable it again before | |
1422 | * setting up the full range we need. | |
1423 | */ | |
a5229050 KB |
1424 | if (pdev->msi_enabled) |
1425 | pci_disable_msi(pdev); | |
1426 | else if (pdev->msix_enabled) | |
e32efbfc JA |
1427 | pci_disable_msix(pdev); |
1428 | ||
be577fab | 1429 | for (i = 0; i < nr_io_queues; i++) |
1b23484b | 1430 | dev->entry[i].entry = i; |
be577fab AG |
1431 | vecs = pci_enable_msix_range(pdev, dev->entry, 1, nr_io_queues); |
1432 | if (vecs < 0) { | |
1433 | vecs = pci_enable_msi_range(pdev, 1, min(nr_io_queues, 32)); | |
1434 | if (vecs < 0) { | |
1435 | vecs = 1; | |
1436 | } else { | |
1437 | for (i = 0; i < vecs; i++) | |
1438 | dev->entry[i].vector = i + pdev->irq; | |
fa08a396 RRG |
1439 | } |
1440 | } | |
1441 | ||
063a8096 MW |
1442 | /* |
1443 | * Should investigate if there's a performance win from allocating | |
1444 | * more queues than interrupt vectors; it might allow the submission | |
1445 | * path to scale better, even if the receive path is limited by the | |
1446 | * number of interrupts. | |
1447 | */ | |
1448 | nr_io_queues = vecs; | |
42f61420 | 1449 | dev->max_qid = nr_io_queues; |
063a8096 | 1450 | |
3193f07b | 1451 | result = queue_request_irq(dev, adminq, adminq->irqname); |
758dd7fd JD |
1452 | if (result) { |
1453 | adminq->cq_vector = -1; | |
22404274 | 1454 | goto free_queues; |
758dd7fd | 1455 | } |
749941f2 | 1456 | return nvme_create_io_queues(dev); |
b60503ba | 1457 | |
22404274 | 1458 | free_queues: |
a1a5ef99 | 1459 | nvme_free_queues(dev, 1); |
22404274 | 1460 | return result; |
b60503ba MW |
1461 | } |
1462 | ||
5955be21 | 1463 | static void nvme_pci_post_scan(struct nvme_ctrl *ctrl) |
a5768aa8 | 1464 | { |
5955be21 | 1465 | struct nvme_dev *dev = to_nvme_dev(ctrl); |
bda4e0fb KB |
1466 | struct nvme_queue *nvmeq; |
1467 | int i; | |
a5768aa8 | 1468 | |
bda4e0fb KB |
1469 | for (i = 0; i < dev->online_queues; i++) { |
1470 | nvmeq = dev->queues[i]; | |
a5768aa8 | 1471 | |
bda4e0fb KB |
1472 | if (!nvmeq->tags || !(*nvmeq->tags)) |
1473 | continue; | |
a5768aa8 | 1474 | |
bda4e0fb KB |
1475 | irq_set_affinity_hint(dev->entry[nvmeq->cq_vector].vector, |
1476 | blk_mq_tags_cpumask(*nvmeq->tags)); | |
a5768aa8 | 1477 | } |
a5768aa8 KB |
1478 | } |
1479 | ||
db3cbfff | 1480 | static void nvme_del_queue_end(struct request *req, int error) |
a5768aa8 | 1481 | { |
db3cbfff | 1482 | struct nvme_queue *nvmeq = req->end_io_data; |
b5875222 | 1483 | |
db3cbfff KB |
1484 | blk_mq_free_request(req); |
1485 | complete(&nvmeq->dev->ioq_wait); | |
a5768aa8 KB |
1486 | } |
1487 | ||
db3cbfff | 1488 | static void nvme_del_cq_end(struct request *req, int error) |
a5768aa8 | 1489 | { |
db3cbfff | 1490 | struct nvme_queue *nvmeq = req->end_io_data; |
a5768aa8 | 1491 | |
db3cbfff KB |
1492 | if (!error) { |
1493 | unsigned long flags; | |
1494 | ||
2e39e0f6 ML |
1495 | /* |
1496 | * We might be called with the AQ q_lock held | |
1497 | * and the I/O queue q_lock should always | |
1498 | * nest inside the AQ one. | |
1499 | */ | |
1500 | spin_lock_irqsave_nested(&nvmeq->q_lock, flags, | |
1501 | SINGLE_DEPTH_NESTING); | |
db3cbfff KB |
1502 | nvme_process_cq(nvmeq); |
1503 | spin_unlock_irqrestore(&nvmeq->q_lock, flags); | |
a5768aa8 | 1504 | } |
db3cbfff KB |
1505 | |
1506 | nvme_del_queue_end(req, error); | |
a5768aa8 KB |
1507 | } |
1508 | ||
db3cbfff | 1509 | static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode) |
bda4e0fb | 1510 | { |
db3cbfff KB |
1511 | struct request_queue *q = nvmeq->dev->ctrl.admin_q; |
1512 | struct request *req; | |
1513 | struct nvme_command cmd; | |
bda4e0fb | 1514 | |
db3cbfff KB |
1515 | memset(&cmd, 0, sizeof(cmd)); |
1516 | cmd.delete_queue.opcode = opcode; | |
1517 | cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid); | |
bda4e0fb | 1518 | |
eb71f435 | 1519 | req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); |
db3cbfff KB |
1520 | if (IS_ERR(req)) |
1521 | return PTR_ERR(req); | |
bda4e0fb | 1522 | |
db3cbfff KB |
1523 | req->timeout = ADMIN_TIMEOUT; |
1524 | req->end_io_data = nvmeq; | |
1525 | ||
1526 | blk_execute_rq_nowait(q, NULL, req, false, | |
1527 | opcode == nvme_admin_delete_cq ? | |
1528 | nvme_del_cq_end : nvme_del_queue_end); | |
1529 | return 0; | |
bda4e0fb KB |
1530 | } |
1531 | ||
db3cbfff | 1532 | static void nvme_disable_io_queues(struct nvme_dev *dev) |
a5768aa8 | 1533 | { |
014a0d60 | 1534 | int pass, queues = dev->online_queues - 1; |
db3cbfff KB |
1535 | unsigned long timeout; |
1536 | u8 opcode = nvme_admin_delete_sq; | |
a5768aa8 | 1537 | |
db3cbfff | 1538 | for (pass = 0; pass < 2; pass++) { |
014a0d60 | 1539 | int sent = 0, i = queues; |
db3cbfff KB |
1540 | |
1541 | reinit_completion(&dev->ioq_wait); | |
1542 | retry: | |
1543 | timeout = ADMIN_TIMEOUT; | |
c21377f8 GKB |
1544 | for (; i > 0; i--, sent++) |
1545 | if (nvme_delete_queue(dev->queues[i], opcode)) | |
db3cbfff | 1546 | break; |
c21377f8 | 1547 | |
db3cbfff KB |
1548 | while (sent--) { |
1549 | timeout = wait_for_completion_io_timeout(&dev->ioq_wait, timeout); | |
1550 | if (timeout == 0) | |
1551 | return; | |
1552 | if (i) | |
1553 | goto retry; | |
1554 | } | |
1555 | opcode = nvme_admin_delete_cq; | |
1556 | } | |
a5768aa8 KB |
1557 | } |
1558 | ||
422ef0c7 MW |
1559 | /* |
1560 | * Return: error value if an error occurred setting up the queues or calling | |
1561 | * Identify Device. 0 if these succeeded, even if adding some of the | |
1562 | * namespaces failed. At the moment, these failures are silent. TBD which | |
1563 | * failures should be reported. | |
1564 | */ | |
8d85fce7 | 1565 | static int nvme_dev_add(struct nvme_dev *dev) |
b60503ba | 1566 | { |
5bae7f73 | 1567 | if (!dev->ctrl.tagset) { |
ffe7704d KB |
1568 | dev->tagset.ops = &nvme_mq_ops; |
1569 | dev->tagset.nr_hw_queues = dev->online_queues - 1; | |
1570 | dev->tagset.timeout = NVME_IO_TIMEOUT; | |
1571 | dev->tagset.numa_node = dev_to_node(dev->dev); | |
1572 | dev->tagset.queue_depth = | |
a4aea562 | 1573 | min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1; |
ffe7704d KB |
1574 | dev->tagset.cmd_size = nvme_cmd_size(dev); |
1575 | dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE; | |
1576 | dev->tagset.driver_data = dev; | |
b60503ba | 1577 | |
ffe7704d KB |
1578 | if (blk_mq_alloc_tag_set(&dev->tagset)) |
1579 | return 0; | |
5bae7f73 | 1580 | dev->ctrl.tagset = &dev->tagset; |
949928c1 KB |
1581 | } else { |
1582 | blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1); | |
1583 | ||
1584 | /* Free previously allocated queues that are no longer usable */ | |
1585 | nvme_free_queues(dev, dev->online_queues); | |
ffe7704d | 1586 | } |
949928c1 | 1587 | |
e1e5e564 | 1588 | return 0; |
b60503ba MW |
1589 | } |
1590 | ||
b00a726a | 1591 | static int nvme_pci_enable(struct nvme_dev *dev) |
0877cb0d | 1592 | { |
42f61420 | 1593 | u64 cap; |
b00a726a | 1594 | int result = -ENOMEM; |
e75ec752 | 1595 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
0877cb0d KB |
1596 | |
1597 | if (pci_enable_device_mem(pdev)) | |
1598 | return result; | |
1599 | ||
0877cb0d | 1600 | pci_set_master(pdev); |
0877cb0d | 1601 | |
e75ec752 CH |
1602 | if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) && |
1603 | dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32))) | |
052d0efa | 1604 | goto disable; |
0877cb0d | 1605 | |
7a67cbea | 1606 | if (readl(dev->bar + NVME_REG_CSTS) == -1) { |
0e53d180 | 1607 | result = -ENODEV; |
b00a726a | 1608 | goto disable; |
0e53d180 | 1609 | } |
e32efbfc JA |
1610 | |
1611 | /* | |
a5229050 KB |
1612 | * Some devices and/or platforms don't advertise or work with INTx |
1613 | * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll | |
1614 | * adjust this later. | |
e32efbfc | 1615 | */ |
a5229050 KB |
1616 | if (pci_enable_msix(pdev, dev->entry, 1)) { |
1617 | pci_enable_msi(pdev); | |
1618 | dev->entry[0].vector = pdev->irq; | |
1619 | } | |
1620 | ||
1621 | if (!dev->entry[0].vector) { | |
1622 | result = -ENODEV; | |
1623 | goto disable; | |
e32efbfc JA |
1624 | } |
1625 | ||
7a67cbea CH |
1626 | cap = lo_hi_readq(dev->bar + NVME_REG_CAP); |
1627 | ||
42f61420 KB |
1628 | dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH); |
1629 | dev->db_stride = 1 << NVME_CAP_STRIDE(cap); | |
7a67cbea | 1630 | dev->dbs = dev->bar + 4096; |
1f390c1f SG |
1631 | |
1632 | /* | |
1633 | * Temporary fix for the Apple controller found in the MacBook8,1 and | |
1634 | * some MacBook7,1 to avoid controller resets and data loss. | |
1635 | */ | |
1636 | if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) { | |
1637 | dev->q_depth = 2; | |
1638 | dev_warn(dev->dev, "detected Apple NVMe controller, set " | |
1639 | "queue depth=%u to work around controller resets\n", | |
1640 | dev->q_depth); | |
1641 | } | |
1642 | ||
7a67cbea | 1643 | if (readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 2)) |
8ffaadf7 | 1644 | dev->cmb = nvme_map_cmb(dev); |
0877cb0d | 1645 | |
a0a3408e KB |
1646 | pci_enable_pcie_error_reporting(pdev); |
1647 | pci_save_state(pdev); | |
0877cb0d KB |
1648 | return 0; |
1649 | ||
1650 | disable: | |
0877cb0d KB |
1651 | pci_disable_device(pdev); |
1652 | return result; | |
1653 | } | |
1654 | ||
1655 | static void nvme_dev_unmap(struct nvme_dev *dev) | |
b00a726a KB |
1656 | { |
1657 | if (dev->bar) | |
1658 | iounmap(dev->bar); | |
a1f447b3 | 1659 | pci_release_mem_regions(to_pci_dev(dev->dev)); |
b00a726a KB |
1660 | } |
1661 | ||
1662 | static void nvme_pci_disable(struct nvme_dev *dev) | |
0877cb0d | 1663 | { |
e75ec752 CH |
1664 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
1665 | ||
1666 | if (pdev->msi_enabled) | |
1667 | pci_disable_msi(pdev); | |
1668 | else if (pdev->msix_enabled) | |
1669 | pci_disable_msix(pdev); | |
0877cb0d | 1670 | |
a0a3408e KB |
1671 | if (pci_is_enabled(pdev)) { |
1672 | pci_disable_pcie_error_reporting(pdev); | |
e75ec752 | 1673 | pci_disable_device(pdev); |
4d115420 | 1674 | } |
4d115420 KB |
1675 | } |
1676 | ||
a5cdb68c | 1677 | static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown) |
b60503ba | 1678 | { |
22404274 | 1679 | int i; |
7c1b2450 | 1680 | u32 csts = -1; |
22404274 | 1681 | |
2d55cd5f | 1682 | del_timer_sync(&dev->watchdog_timer); |
1fa6aead | 1683 | |
77bf25ea | 1684 | mutex_lock(&dev->shutdown_lock); |
b00a726a | 1685 | if (pci_is_enabled(to_pci_dev(dev->dev))) { |
25646264 | 1686 | nvme_stop_queues(&dev->ctrl); |
7a67cbea | 1687 | csts = readl(dev->bar + NVME_REG_CSTS); |
c9d3bf88 | 1688 | } |
c21377f8 GKB |
1689 | |
1690 | for (i = dev->queue_count - 1; i > 0; i--) | |
1691 | nvme_suspend_queue(dev->queues[i]); | |
1692 | ||
7c1b2450 | 1693 | if (csts & NVME_CSTS_CFS || !(csts & NVME_CSTS_RDY)) { |
c21377f8 | 1694 | nvme_suspend_queue(dev->queues[0]); |
4d115420 KB |
1695 | } else { |
1696 | nvme_disable_io_queues(dev); | |
a5cdb68c | 1697 | nvme_disable_admin_queue(dev, shutdown); |
4d115420 | 1698 | } |
b00a726a | 1699 | nvme_pci_disable(dev); |
07836e65 | 1700 | |
e1958e65 ML |
1701 | blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl); |
1702 | blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl); | |
77bf25ea | 1703 | mutex_unlock(&dev->shutdown_lock); |
b60503ba MW |
1704 | } |
1705 | ||
091b6092 MW |
1706 | static int nvme_setup_prp_pools(struct nvme_dev *dev) |
1707 | { | |
e75ec752 | 1708 | dev->prp_page_pool = dma_pool_create("prp list page", dev->dev, |
091b6092 MW |
1709 | PAGE_SIZE, PAGE_SIZE, 0); |
1710 | if (!dev->prp_page_pool) | |
1711 | return -ENOMEM; | |
1712 | ||
99802a7a | 1713 | /* Optimisation for I/Os between 4k and 128k */ |
e75ec752 | 1714 | dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev, |
99802a7a MW |
1715 | 256, 256, 0); |
1716 | if (!dev->prp_small_pool) { | |
1717 | dma_pool_destroy(dev->prp_page_pool); | |
1718 | return -ENOMEM; | |
1719 | } | |
091b6092 MW |
1720 | return 0; |
1721 | } | |
1722 | ||
1723 | static void nvme_release_prp_pools(struct nvme_dev *dev) | |
1724 | { | |
1725 | dma_pool_destroy(dev->prp_page_pool); | |
99802a7a | 1726 | dma_pool_destroy(dev->prp_small_pool); |
091b6092 MW |
1727 | } |
1728 | ||
1673f1f0 | 1729 | static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl) |
5e82e952 | 1730 | { |
1673f1f0 | 1731 | struct nvme_dev *dev = to_nvme_dev(ctrl); |
9ac27090 | 1732 | |
e75ec752 | 1733 | put_device(dev->dev); |
4af0e21c KB |
1734 | if (dev->tagset.tags) |
1735 | blk_mq_free_tag_set(&dev->tagset); | |
1c63dc66 CH |
1736 | if (dev->ctrl.admin_q) |
1737 | blk_put_queue(dev->ctrl.admin_q); | |
5e82e952 KB |
1738 | kfree(dev->queues); |
1739 | kfree(dev->entry); | |
1740 | kfree(dev); | |
1741 | } | |
1742 | ||
f58944e2 KB |
1743 | static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status) |
1744 | { | |
237045fc | 1745 | dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status); |
f58944e2 KB |
1746 | |
1747 | kref_get(&dev->ctrl.kref); | |
69d9a99c | 1748 | nvme_dev_disable(dev, false); |
f58944e2 KB |
1749 | if (!schedule_work(&dev->remove_work)) |
1750 | nvme_put_ctrl(&dev->ctrl); | |
1751 | } | |
1752 | ||
fd634f41 | 1753 | static void nvme_reset_work(struct work_struct *work) |
5e82e952 | 1754 | { |
fd634f41 | 1755 | struct nvme_dev *dev = container_of(work, struct nvme_dev, reset_work); |
f58944e2 | 1756 | int result = -ENODEV; |
5e82e952 | 1757 | |
bb8d261e | 1758 | if (WARN_ON(dev->ctrl.state == NVME_CTRL_RESETTING)) |
fd634f41 | 1759 | goto out; |
5e82e952 | 1760 | |
fd634f41 CH |
1761 | /* |
1762 | * If we're called to reset a live controller first shut it down before | |
1763 | * moving on. | |
1764 | */ | |
b00a726a | 1765 | if (dev->ctrl.ctrl_config & NVME_CC_ENABLE) |
a5cdb68c | 1766 | nvme_dev_disable(dev, false); |
5e82e952 | 1767 | |
bb8d261e | 1768 | if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_RESETTING)) |
9bf2b972 KB |
1769 | goto out; |
1770 | ||
b00a726a | 1771 | result = nvme_pci_enable(dev); |
f0b50732 | 1772 | if (result) |
3cf519b5 | 1773 | goto out; |
f0b50732 KB |
1774 | |
1775 | result = nvme_configure_admin_queue(dev); | |
1776 | if (result) | |
f58944e2 | 1777 | goto out; |
f0b50732 | 1778 | |
a4aea562 | 1779 | nvme_init_queue(dev->queues[0], 0); |
0fb59cbc KB |
1780 | result = nvme_alloc_admin_tags(dev); |
1781 | if (result) | |
f58944e2 | 1782 | goto out; |
b9afca3e | 1783 | |
ce4541f4 CH |
1784 | result = nvme_init_identify(&dev->ctrl); |
1785 | if (result) | |
f58944e2 | 1786 | goto out; |
ce4541f4 | 1787 | |
f0b50732 | 1788 | result = nvme_setup_io_queues(dev); |
badc34d4 | 1789 | if (result) |
f58944e2 | 1790 | goto out; |
f0b50732 | 1791 | |
21f033f7 KB |
1792 | /* |
1793 | * A controller that can not execute IO typically requires user | |
1794 | * intervention to correct. For such degraded controllers, the driver | |
1795 | * should not submit commands the user did not request, so skip | |
1796 | * registering for asynchronous event notification on this condition. | |
1797 | */ | |
f866fc42 CH |
1798 | if (dev->online_queues > 1) |
1799 | nvme_queue_async_events(&dev->ctrl); | |
3cf519b5 | 1800 | |
2d55cd5f | 1801 | mod_timer(&dev->watchdog_timer, round_jiffies(jiffies + HZ)); |
3cf519b5 | 1802 | |
2659e57b CH |
1803 | /* |
1804 | * Keep the controller around but remove all namespaces if we don't have | |
1805 | * any working I/O queue. | |
1806 | */ | |
3cf519b5 | 1807 | if (dev->online_queues < 2) { |
1b3c47c1 | 1808 | dev_warn(dev->ctrl.device, "IO queues not created\n"); |
3b24774e | 1809 | nvme_kill_queues(&dev->ctrl); |
5bae7f73 | 1810 | nvme_remove_namespaces(&dev->ctrl); |
3cf519b5 | 1811 | } else { |
25646264 | 1812 | nvme_start_queues(&dev->ctrl); |
3cf519b5 CH |
1813 | nvme_dev_add(dev); |
1814 | } | |
1815 | ||
bb8d261e CH |
1816 | if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) { |
1817 | dev_warn(dev->ctrl.device, "failed to mark controller live\n"); | |
1818 | goto out; | |
1819 | } | |
92911a55 CH |
1820 | |
1821 | if (dev->online_queues > 1) | |
5955be21 | 1822 | nvme_queue_scan(&dev->ctrl); |
3cf519b5 | 1823 | return; |
f0b50732 | 1824 | |
3cf519b5 | 1825 | out: |
f58944e2 | 1826 | nvme_remove_dead_ctrl(dev, result); |
f0b50732 KB |
1827 | } |
1828 | ||
5c8809e6 | 1829 | static void nvme_remove_dead_ctrl_work(struct work_struct *work) |
9a6b9458 | 1830 | { |
5c8809e6 | 1831 | struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work); |
e75ec752 | 1832 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
9a6b9458 | 1833 | |
69d9a99c | 1834 | nvme_kill_queues(&dev->ctrl); |
9a6b9458 | 1835 | if (pci_get_drvdata(pdev)) |
921920ab | 1836 | device_release_driver(&pdev->dev); |
1673f1f0 | 1837 | nvme_put_ctrl(&dev->ctrl); |
9a6b9458 KB |
1838 | } |
1839 | ||
4cc06521 | 1840 | static int nvme_reset(struct nvme_dev *dev) |
9a6b9458 | 1841 | { |
1c63dc66 | 1842 | if (!dev->ctrl.admin_q || blk_queue_dying(dev->ctrl.admin_q)) |
4cc06521 | 1843 | return -ENODEV; |
ffe7704d | 1844 | |
846cc05f CH |
1845 | if (!queue_work(nvme_workq, &dev->reset_work)) |
1846 | return -EBUSY; | |
ffe7704d | 1847 | |
846cc05f | 1848 | flush_work(&dev->reset_work); |
846cc05f | 1849 | return 0; |
9a6b9458 KB |
1850 | } |
1851 | ||
1c63dc66 | 1852 | static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val) |
9ca97374 | 1853 | { |
1c63dc66 | 1854 | *val = readl(to_nvme_dev(ctrl)->bar + off); |
90667892 | 1855 | return 0; |
9ca97374 TH |
1856 | } |
1857 | ||
5fd4ce1b | 1858 | static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val) |
4cc06521 | 1859 | { |
5fd4ce1b CH |
1860 | writel(val, to_nvme_dev(ctrl)->bar + off); |
1861 | return 0; | |
1862 | } | |
4cc06521 | 1863 | |
7fd8930f CH |
1864 | static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val) |
1865 | { | |
1866 | *val = readq(to_nvme_dev(ctrl)->bar + off); | |
1867 | return 0; | |
4cc06521 KB |
1868 | } |
1869 | ||
f3ca80fc CH |
1870 | static int nvme_pci_reset_ctrl(struct nvme_ctrl *ctrl) |
1871 | { | |
1872 | return nvme_reset(to_nvme_dev(ctrl)); | |
4cc06521 | 1873 | } |
f3ca80fc | 1874 | |
1c63dc66 | 1875 | static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = { |
1a353d85 | 1876 | .name = "pcie", |
e439bb12 | 1877 | .module = THIS_MODULE, |
1c63dc66 | 1878 | .reg_read32 = nvme_pci_reg_read32, |
5fd4ce1b | 1879 | .reg_write32 = nvme_pci_reg_write32, |
7fd8930f | 1880 | .reg_read64 = nvme_pci_reg_read64, |
f3ca80fc | 1881 | .reset_ctrl = nvme_pci_reset_ctrl, |
1673f1f0 | 1882 | .free_ctrl = nvme_pci_free_ctrl, |
5955be21 | 1883 | .post_scan = nvme_pci_post_scan, |
f866fc42 | 1884 | .submit_async_event = nvme_pci_submit_async_event, |
1c63dc66 | 1885 | }; |
4cc06521 | 1886 | |
b00a726a KB |
1887 | static int nvme_dev_map(struct nvme_dev *dev) |
1888 | { | |
b00a726a KB |
1889 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
1890 | ||
a1f447b3 | 1891 | if (pci_request_mem_regions(pdev, "nvme")) |
b00a726a KB |
1892 | return -ENODEV; |
1893 | ||
1894 | dev->bar = ioremap(pci_resource_start(pdev, 0), 8192); | |
1895 | if (!dev->bar) | |
1896 | goto release; | |
1897 | ||
1898 | return 0; | |
1899 | release: | |
a1f447b3 | 1900 | pci_release_mem_regions(pdev); |
b00a726a KB |
1901 | return -ENODEV; |
1902 | } | |
1903 | ||
8d85fce7 | 1904 | static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) |
b60503ba | 1905 | { |
a4aea562 | 1906 | int node, result = -ENOMEM; |
b60503ba MW |
1907 | struct nvme_dev *dev; |
1908 | ||
a4aea562 MB |
1909 | node = dev_to_node(&pdev->dev); |
1910 | if (node == NUMA_NO_NODE) | |
2fa84351 | 1911 | set_dev_node(&pdev->dev, first_memory_node); |
a4aea562 MB |
1912 | |
1913 | dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); | |
b60503ba MW |
1914 | if (!dev) |
1915 | return -ENOMEM; | |
a4aea562 MB |
1916 | dev->entry = kzalloc_node(num_possible_cpus() * sizeof(*dev->entry), |
1917 | GFP_KERNEL, node); | |
b60503ba MW |
1918 | if (!dev->entry) |
1919 | goto free; | |
a4aea562 MB |
1920 | dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *), |
1921 | GFP_KERNEL, node); | |
b60503ba MW |
1922 | if (!dev->queues) |
1923 | goto free; | |
1924 | ||
e75ec752 | 1925 | dev->dev = get_device(&pdev->dev); |
9a6b9458 | 1926 | pci_set_drvdata(pdev, dev); |
1c63dc66 | 1927 | |
b00a726a KB |
1928 | result = nvme_dev_map(dev); |
1929 | if (result) | |
1930 | goto free; | |
1931 | ||
f3ca80fc | 1932 | INIT_WORK(&dev->reset_work, nvme_reset_work); |
5c8809e6 | 1933 | INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work); |
2d55cd5f CH |
1934 | setup_timer(&dev->watchdog_timer, nvme_watchdog_timer, |
1935 | (unsigned long)dev); | |
77bf25ea | 1936 | mutex_init(&dev->shutdown_lock); |
db3cbfff | 1937 | init_completion(&dev->ioq_wait); |
b60503ba | 1938 | |
091b6092 MW |
1939 | result = nvme_setup_prp_pools(dev); |
1940 | if (result) | |
a96d4f5c | 1941 | goto put_pci; |
4cc06521 | 1942 | |
f3ca80fc CH |
1943 | result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops, |
1944 | id->driver_data); | |
4cc06521 | 1945 | if (result) |
2e1d8448 | 1946 | goto release_pools; |
740216fc | 1947 | |
1b3c47c1 SG |
1948 | dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev)); |
1949 | ||
92f7a162 | 1950 | queue_work(nvme_workq, &dev->reset_work); |
b60503ba MW |
1951 | return 0; |
1952 | ||
0877cb0d | 1953 | release_pools: |
091b6092 | 1954 | nvme_release_prp_pools(dev); |
a96d4f5c | 1955 | put_pci: |
e75ec752 | 1956 | put_device(dev->dev); |
b00a726a | 1957 | nvme_dev_unmap(dev); |
b60503ba MW |
1958 | free: |
1959 | kfree(dev->queues); | |
1960 | kfree(dev->entry); | |
1961 | kfree(dev); | |
1962 | return result; | |
1963 | } | |
1964 | ||
f0d54a54 KB |
1965 | static void nvme_reset_notify(struct pci_dev *pdev, bool prepare) |
1966 | { | |
a6739479 | 1967 | struct nvme_dev *dev = pci_get_drvdata(pdev); |
f0d54a54 | 1968 | |
a6739479 | 1969 | if (prepare) |
a5cdb68c | 1970 | nvme_dev_disable(dev, false); |
a6739479 | 1971 | else |
92f7a162 | 1972 | queue_work(nvme_workq, &dev->reset_work); |
f0d54a54 KB |
1973 | } |
1974 | ||
09ece142 KB |
1975 | static void nvme_shutdown(struct pci_dev *pdev) |
1976 | { | |
1977 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
a5cdb68c | 1978 | nvme_dev_disable(dev, true); |
09ece142 KB |
1979 | } |
1980 | ||
f58944e2 KB |
1981 | /* |
1982 | * The driver's remove may be called on a device in a partially initialized | |
1983 | * state. This function must not have any dependencies on the device state in | |
1984 | * order to proceed. | |
1985 | */ | |
8d85fce7 | 1986 | static void nvme_remove(struct pci_dev *pdev) |
b60503ba MW |
1987 | { |
1988 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
9a6b9458 | 1989 | |
bb8d261e CH |
1990 | nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); |
1991 | ||
9a6b9458 | 1992 | pci_set_drvdata(pdev, NULL); |
0ff9d4e1 KB |
1993 | |
1994 | if (!pci_device_is_present(pdev)) | |
1995 | nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD); | |
1996 | ||
9bf2b972 | 1997 | flush_work(&dev->reset_work); |
53029b04 | 1998 | nvme_uninit_ctrl(&dev->ctrl); |
a5cdb68c | 1999 | nvme_dev_disable(dev, true); |
a4aea562 | 2000 | nvme_dev_remove_admin(dev); |
a1a5ef99 | 2001 | nvme_free_queues(dev, 0); |
8ffaadf7 | 2002 | nvme_release_cmb(dev); |
9a6b9458 | 2003 | nvme_release_prp_pools(dev); |
b00a726a | 2004 | nvme_dev_unmap(dev); |
1673f1f0 | 2005 | nvme_put_ctrl(&dev->ctrl); |
b60503ba MW |
2006 | } |
2007 | ||
13880f5b KB |
2008 | static int nvme_pci_sriov_configure(struct pci_dev *pdev, int numvfs) |
2009 | { | |
2010 | int ret = 0; | |
2011 | ||
2012 | if (numvfs == 0) { | |
2013 | if (pci_vfs_assigned(pdev)) { | |
2014 | dev_warn(&pdev->dev, | |
2015 | "Cannot disable SR-IOV VFs while assigned\n"); | |
2016 | return -EPERM; | |
2017 | } | |
2018 | pci_disable_sriov(pdev); | |
2019 | return 0; | |
2020 | } | |
2021 | ||
2022 | ret = pci_enable_sriov(pdev, numvfs); | |
2023 | return ret ? ret : numvfs; | |
2024 | } | |
2025 | ||
671a6018 | 2026 | #ifdef CONFIG_PM_SLEEP |
cd638946 KB |
2027 | static int nvme_suspend(struct device *dev) |
2028 | { | |
2029 | struct pci_dev *pdev = to_pci_dev(dev); | |
2030 | struct nvme_dev *ndev = pci_get_drvdata(pdev); | |
2031 | ||
a5cdb68c | 2032 | nvme_dev_disable(ndev, true); |
cd638946 KB |
2033 | return 0; |
2034 | } | |
2035 | ||
2036 | static int nvme_resume(struct device *dev) | |
2037 | { | |
2038 | struct pci_dev *pdev = to_pci_dev(dev); | |
2039 | struct nvme_dev *ndev = pci_get_drvdata(pdev); | |
cd638946 | 2040 | |
92f7a162 | 2041 | queue_work(nvme_workq, &ndev->reset_work); |
9a6b9458 | 2042 | return 0; |
cd638946 | 2043 | } |
671a6018 | 2044 | #endif |
cd638946 KB |
2045 | |
2046 | static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume); | |
b60503ba | 2047 | |
a0a3408e KB |
2048 | static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev, |
2049 | pci_channel_state_t state) | |
2050 | { | |
2051 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
2052 | ||
2053 | /* | |
2054 | * A frozen channel requires a reset. When detected, this method will | |
2055 | * shutdown the controller to quiesce. The controller will be restarted | |
2056 | * after the slot reset through driver's slot_reset callback. | |
2057 | */ | |
a0a3408e KB |
2058 | switch (state) { |
2059 | case pci_channel_io_normal: | |
2060 | return PCI_ERS_RESULT_CAN_RECOVER; | |
2061 | case pci_channel_io_frozen: | |
d011fb31 KB |
2062 | dev_warn(dev->ctrl.device, |
2063 | "frozen state error detected, reset controller\n"); | |
a5cdb68c | 2064 | nvme_dev_disable(dev, false); |
a0a3408e KB |
2065 | return PCI_ERS_RESULT_NEED_RESET; |
2066 | case pci_channel_io_perm_failure: | |
d011fb31 KB |
2067 | dev_warn(dev->ctrl.device, |
2068 | "failure state error detected, request disconnect\n"); | |
a0a3408e KB |
2069 | return PCI_ERS_RESULT_DISCONNECT; |
2070 | } | |
2071 | return PCI_ERS_RESULT_NEED_RESET; | |
2072 | } | |
2073 | ||
2074 | static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev) | |
2075 | { | |
2076 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
2077 | ||
1b3c47c1 | 2078 | dev_info(dev->ctrl.device, "restart after slot reset\n"); |
a0a3408e KB |
2079 | pci_restore_state(pdev); |
2080 | queue_work(nvme_workq, &dev->reset_work); | |
2081 | return PCI_ERS_RESULT_RECOVERED; | |
2082 | } | |
2083 | ||
2084 | static void nvme_error_resume(struct pci_dev *pdev) | |
2085 | { | |
2086 | pci_cleanup_aer_uncorrect_error_status(pdev); | |
2087 | } | |
2088 | ||
1d352035 | 2089 | static const struct pci_error_handlers nvme_err_handler = { |
b60503ba | 2090 | .error_detected = nvme_error_detected, |
b60503ba MW |
2091 | .slot_reset = nvme_slot_reset, |
2092 | .resume = nvme_error_resume, | |
f0d54a54 | 2093 | .reset_notify = nvme_reset_notify, |
b60503ba MW |
2094 | }; |
2095 | ||
2096 | /* Move to pci_ids.h later */ | |
2097 | #define PCI_CLASS_STORAGE_EXPRESS 0x010802 | |
2098 | ||
6eb0d698 | 2099 | static const struct pci_device_id nvme_id_table[] = { |
106198ed | 2100 | { PCI_VDEVICE(INTEL, 0x0953), |
08095e70 KB |
2101 | .driver_data = NVME_QUIRK_STRIPE_SIZE | |
2102 | NVME_QUIRK_DISCARD_ZEROES, }, | |
99466e70 KB |
2103 | { PCI_VDEVICE(INTEL, 0x0a53), |
2104 | .driver_data = NVME_QUIRK_STRIPE_SIZE | | |
2105 | NVME_QUIRK_DISCARD_ZEROES, }, | |
2106 | { PCI_VDEVICE(INTEL, 0x0a54), | |
2107 | .driver_data = NVME_QUIRK_STRIPE_SIZE | | |
2108 | NVME_QUIRK_DISCARD_ZEROES, }, | |
540c801c KB |
2109 | { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */ |
2110 | .driver_data = NVME_QUIRK_IDENTIFY_CNS, }, | |
54adc010 GP |
2111 | { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */ |
2112 | .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, | |
b60503ba | 2113 | { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, |
c74dc780 | 2114 | { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) }, |
b60503ba MW |
2115 | { 0, } |
2116 | }; | |
2117 | MODULE_DEVICE_TABLE(pci, nvme_id_table); | |
2118 | ||
2119 | static struct pci_driver nvme_driver = { | |
2120 | .name = "nvme", | |
2121 | .id_table = nvme_id_table, | |
2122 | .probe = nvme_probe, | |
8d85fce7 | 2123 | .remove = nvme_remove, |
09ece142 | 2124 | .shutdown = nvme_shutdown, |
cd638946 KB |
2125 | .driver = { |
2126 | .pm = &nvme_dev_pm_ops, | |
2127 | }, | |
13880f5b | 2128 | .sriov_configure = nvme_pci_sriov_configure, |
b60503ba MW |
2129 | .err_handler = &nvme_err_handler, |
2130 | }; | |
2131 | ||
2132 | static int __init nvme_init(void) | |
2133 | { | |
0ac13140 | 2134 | int result; |
1fa6aead | 2135 | |
92f7a162 | 2136 | nvme_workq = alloc_workqueue("nvme", WQ_UNBOUND | WQ_MEM_RECLAIM, 0); |
9a6b9458 | 2137 | if (!nvme_workq) |
b9afca3e | 2138 | return -ENOMEM; |
9a6b9458 | 2139 | |
f3db22fe KB |
2140 | result = pci_register_driver(&nvme_driver); |
2141 | if (result) | |
576d55d6 | 2142 | destroy_workqueue(nvme_workq); |
b60503ba MW |
2143 | return result; |
2144 | } | |
2145 | ||
2146 | static void __exit nvme_exit(void) | |
2147 | { | |
2148 | pci_unregister_driver(&nvme_driver); | |
9a6b9458 | 2149 | destroy_workqueue(nvme_workq); |
21bd78bc | 2150 | _nvme_check_size(); |
b60503ba MW |
2151 | } |
2152 | ||
2153 | MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); | |
2154 | MODULE_LICENSE("GPL"); | |
c78b4713 | 2155 | MODULE_VERSION("1.0"); |
b60503ba MW |
2156 | module_init(nvme_init); |
2157 | module_exit(nvme_exit); |