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nvme-pci: put the admin queue in nvme_dev_remove_admin
[linux-2.6-block.git] / drivers / nvme / host / pci.c
CommitLineData
5f37396d 1// SPDX-License-Identifier: GPL-2.0
b60503ba
MW		 2/*
3 * NVM Express device driver
6eb0d698 4 * Copyright (c) 2011-2014, Intel Corporation.
b60503ba
MW		 5 */
6
df4f9bc4 7#include <linux/acpi.h>
a0a3408e 8#include <linux/aer.h>
18119775 9#include <linux/async.h>
b60503ba 10#include <linux/blkdev.h>
a4aea562 11#include <linux/blk-mq.h>
dca51e78 12#include <linux/blk-mq-pci.h>
fe45e630 13#include <linux/blk-integrity.h>
ff5350a8 14#include <linux/dmi.h>
b60503ba
MW		 15#include <linux/init.h>
16#include <linux/interrupt.h>
17#include <linux/io.h>
dc90f084 18#include <linux/memremap.h>
b60503ba
MW		 19#include <linux/mm.h>
20#include <linux/module.h>
77bf25ea 21#include <linux/mutex.h>
d0877473 22#include <linux/once.h>
b60503ba 23#include <linux/pci.h>
d916b1be 24#include <linux/suspend.h>
e1e5e564 25#include <linux/t10-pi.h>
b60503ba 26#include <linux/types.h>
2f8e2c87 27#include <linux/io-64-nonatomic-lo-hi.h>
20d3bb92 28#include <linux/io-64-nonatomic-hi-lo.h>
a98e58e5 29#include <linux/sed-opal.h>
0f238ff5 30#include <linux/pci-p2pdma.h>
797a796a 31
604c01d5 32#include "trace.h"
f11bb3e2
CH		 33#include "nvme.h"
34
c1e0cc7e 35#define SQ_SIZE(q) ((q)->q_depth << (q)->sqes)
8a1d09a6 36#define CQ_SIZE(q) ((q)->q_depth * sizeof(struct nvme_completion))
c965809c 37
a7a7cbe3 38#define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc))
9d43cf64 39
943e942e
JA		 40/*
41 * These can be higher, but we need to ensure that any command doesn't
42 * require an sg allocation that needs more than a page of data.
43 */
44#define NVME_MAX_KB_SZ 4096
45#define NVME_MAX_SEGS 127
46
58ffacb5 47static int use_threaded_interrupts;
2e21e445 48module_param(use_threaded_interrupts, int, 0444);
58ffacb5 49
8ffaadf7 50static bool use_cmb_sqes = true;
69f4eb9f 51module_param(use_cmb_sqes, bool, 0444);
8ffaadf7
JD		 52MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
53
87ad72a5
CH		 54static unsigned int max_host_mem_size_mb = 128;
55module_param(max_host_mem_size_mb, uint, 0444);
56MODULE_PARM_DESC(max_host_mem_size_mb,
57 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
1fa6aead 58
a7a7cbe3
CK		 59static unsigned int sgl_threshold = SZ_32K;
60module_param(sgl_threshold, uint, 0644);
61MODULE_PARM_DESC(sgl_threshold,
62 "Use SGLs when average request segment size is larger or equal to "
63 "this size. Use 0 to disable SGLs.");
64
27453b45
SG		 65#define NVME_PCI_MIN_QUEUE_SIZE 2
66#define NVME_PCI_MAX_QUEUE_SIZE 4095
b27c1e68 67static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
68static const struct kernel_param_ops io_queue_depth_ops = {
69 .set = io_queue_depth_set,
61f3b896 70 .get = param_get_uint,
b27c1e68 71};
72
61f3b896 73static unsigned int io_queue_depth = 1024;
b27c1e68 74module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
27453b45 75MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2 and < 4096");
b27c1e68 76
9c9e76d5
WZ		 77static int io_queue_count_set(const char *val, const struct kernel_param *kp)
78{
79 unsigned int n;
80 int ret;
81
82 ret = kstrtouint(val, 10, &n);
83 if (ret != 0 || n > num_possible_cpus())
84 return -EINVAL;
85 return param_set_uint(val, kp);
86}
87
88static const struct kernel_param_ops io_queue_count_ops = {
89 .set = io_queue_count_set,
90 .get = param_get_uint,
91};
92
3f68baf7 93static unsigned int write_queues;
9c9e76d5 94module_param_cb(write_queues, &io_queue_count_ops, &write_queues, 0644);
3b6592f7
JA		 95MODULE_PARM_DESC(write_queues,
96 "Number of queues to use for writes. If not set, reads and writes "
97 "will share a queue set.");
98
3f68baf7 99static unsigned int poll_queues;
9c9e76d5 100module_param_cb(poll_queues, &io_queue_count_ops, &poll_queues, 0644);
4b04cc6a
JA		 101MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO.");
102
df4f9bc4
DB		 103static bool noacpi;
104module_param(noacpi, bool, 0444);
105MODULE_PARM_DESC(noacpi, "disable acpi bios quirks");
106
1c63dc66
CH		 107struct nvme_dev;
108struct nvme_queue;
b3fffdef 109
a5cdb68c 110static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
8fae268b 111static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode);
d4b4ff8e 112
1c63dc66
CH		 113/*
114 * Represents an NVM Express device. Each nvme_dev is a PCI function.
115 */
116struct nvme_dev {
147b27e4 117 struct nvme_queue *queues;
1c63dc66
CH		 118 struct blk_mq_tag_set tagset;
119 struct blk_mq_tag_set admin_tagset;
120 u32 __iomem *dbs;
121 struct device *dev;
122 struct dma_pool *prp_page_pool;
123 struct dma_pool *prp_small_pool;
1c63dc66
CH		 124 unsigned online_queues;
125 unsigned max_qid;
e20ba6e1 126 unsigned io_queues[HCTX_MAX_TYPES];
22b55601 127 unsigned int num_vecs;
7442ddce 128 u32 q_depth;
c1e0cc7e 129 int io_sqes;
1c63dc66 130 u32 db_stride;
1c63dc66 131 void __iomem *bar;
97f6ef64 132 unsigned long bar_mapped_size;
5c8809e6 133 struct work_struct remove_work;
77bf25ea 134 struct mutex shutdown_lock;
1c63dc66 135 bool subsystem;
1c63dc66 136 u64 cmb_size;
0f238ff5 137 bool cmb_use_sqes;
1c63dc66 138 u32 cmbsz;
202021c1 139 u32 cmbloc;
1c63dc66 140 struct nvme_ctrl ctrl;
d916b1be 141 u32 last_ps;
a5df5e79 142 bool hmb;
87ad72a5 143
943e942e
JA		 144 mempool_t *iod_mempool;
145
87ad72a5 146 /* shadow doorbell buffer support: */
f9f38e33
HK		 147 u32 *dbbuf_dbs;
148 dma_addr_t dbbuf_dbs_dma_addr;
149 u32 *dbbuf_eis;
150 dma_addr_t dbbuf_eis_dma_addr;
87ad72a5
CH		 151
152 /* host memory buffer support: */
153 u64 host_mem_size;
154 u32 nr_host_mem_descs;
4033f35d 155 dma_addr_t host_mem_descs_dma;
87ad72a5
CH		 156 struct nvme_host_mem_buf_desc *host_mem_descs;
157 void **host_mem_desc_bufs;
2a5bcfdd
WZ		 158 unsigned int nr_allocated_queues;
159 unsigned int nr_write_queues;
160 unsigned int nr_poll_queues;
4d115420 161};
1fa6aead 162
b27c1e68 163static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
164{
27453b45
SG		 165 return param_set_uint_minmax(val, kp, NVME_PCI_MIN_QUEUE_SIZE,
166 NVME_PCI_MAX_QUEUE_SIZE);
b27c1e68 167}
168
f9f38e33
HK		 169static inline unsigned int sq_idx(unsigned int qid, u32 stride)
170{
171 return qid * 2 * stride;
172}
173
174static inline unsigned int cq_idx(unsigned int qid, u32 stride)
175{
176 return (qid * 2 + 1) * stride;
177}
178
1c63dc66
CH		 179static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
180{
181 return container_of(ctrl, struct nvme_dev, ctrl);
182}
183
b60503ba
MW		 184/*
185 * An NVM Express queue. Each device has at least two (one for admin
186 * commands and one for I/O commands).
187 */
188struct nvme_queue {
091b6092 189 struct nvme_dev *dev;
1ab0cd69 190 spinlock_t sq_lock;
c1e0cc7e 191 void *sq_cmds;
3a7afd8e
CH		 192 /* only used for poll queues: */
193 spinlock_t cq_poll_lock ____cacheline_aligned_in_smp;
74943d45 194 struct nvme_completion *cqes;
b60503ba
MW		 195 dma_addr_t sq_dma_addr;
196 dma_addr_t cq_dma_addr;
b60503ba 197 u32 __iomem *q_db;
7442ddce 198 u32 q_depth;
7c349dde 199 u16 cq_vector;
b60503ba 200 u16 sq_tail;
38210800 201 u16 last_sq_tail;
b60503ba 202 u16 cq_head;
c30341dc 203 u16 qid;
e9539f47 204 u8 cq_phase;
c1e0cc7e 205 u8 sqes;
4e224106
CH		 206 unsigned long flags;
207#define NVMEQ_ENABLED 0
63223078 208#define NVMEQ_SQ_CMB 1
d1ed6aa1 209#define NVMEQ_DELETE_ERROR 2
7c349dde 210#define NVMEQ_POLLED 3
f9f38e33
HK		 211 u32 *dbbuf_sq_db;
212 u32 *dbbuf_cq_db;
213 u32 *dbbuf_sq_ei;
214 u32 *dbbuf_cq_ei;
d1ed6aa1 215 struct completion delete_done;
b60503ba
MW		 216};
217
71bd150c 218/*
9b048119
CH		 219 * The nvme_iod describes the data in an I/O.
220 *
221 * The sg pointer contains the list of PRP/SGL chunk allocations in addition
222 * to the actual struct scatterlist.
71bd150c
CH		 223 */
224struct nvme_iod {
d49187e9 225 struct nvme_request req;
af7fae85 226 struct nvme_command cmd;
a7a7cbe3 227 bool use_sgl;
52da4f3f 228 bool aborted;
c372cdd1
KB		 229 s8 nr_allocations; /* PRP list pool allocations. 0 means small
230 pool in use */
dff824b2 231 unsigned int dma_len; /* length of single DMA segment mapping */
c4c22c52 232 dma_addr_t first_dma;
783b94bd 233 dma_addr_t meta_dma;
91fb2b60 234 struct sg_table sgt;
b60503ba
MW		 235};
236
2a5bcfdd 237static inline unsigned int nvme_dbbuf_size(struct nvme_dev *dev)
3b6592f7 238{
2a5bcfdd 239 return dev->nr_allocated_queues * 8 * dev->db_stride;
f9f38e33
HK		 240}
241
242static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
243{
2a5bcfdd 244 unsigned int mem_size = nvme_dbbuf_size(dev);
f9f38e33 245
58847f12
KB		 246 if (dev->dbbuf_dbs) {
247 /*
248 * Clear the dbbuf memory so the driver doesn't observe stale
249 * values from the previous instantiation.
250 */
251 memset(dev->dbbuf_dbs, 0, mem_size);
252 memset(dev->dbbuf_eis, 0, mem_size);
f9f38e33 253 return 0;
58847f12 254 }
f9f38e33
HK		 255
256 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
257 &dev->dbbuf_dbs_dma_addr,
258 GFP_KERNEL);
259 if (!dev->dbbuf_dbs)
260 return -ENOMEM;
261 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
262 &dev->dbbuf_eis_dma_addr,
263 GFP_KERNEL);
264 if (!dev->dbbuf_eis) {
265 dma_free_coherent(dev->dev, mem_size,
266 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
267 dev->dbbuf_dbs = NULL;
268 return -ENOMEM;
269 }
270
271 return 0;
272}
273
274static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
275{
2a5bcfdd 276 unsigned int mem_size = nvme_dbbuf_size(dev);
f9f38e33
HK		 277
278 if (dev->dbbuf_dbs) {
279 dma_free_coherent(dev->dev, mem_size,
280 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
281 dev->dbbuf_dbs = NULL;
282 }
283 if (dev->dbbuf_eis) {
284 dma_free_coherent(dev->dev, mem_size,
285 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
286 dev->dbbuf_eis = NULL;
287 }
288}
289
290static void nvme_dbbuf_init(struct nvme_dev *dev,
291 struct nvme_queue *nvmeq, int qid)
292{
293 if (!dev->dbbuf_dbs || !qid)
294 return;
295
296 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
297 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
298 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
299 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
300}
301
0f0d2c87
MI		 302static void nvme_dbbuf_free(struct nvme_queue *nvmeq)
303{
304 if (!nvmeq->qid)
305 return;
306
307 nvmeq->dbbuf_sq_db = NULL;
308 nvmeq->dbbuf_cq_db = NULL;
309 nvmeq->dbbuf_sq_ei = NULL;
310 nvmeq->dbbuf_cq_ei = NULL;
311}
312
f9f38e33
HK		 313static void nvme_dbbuf_set(struct nvme_dev *dev)
314{
f66e2804 315 struct nvme_command c = { };
0f0d2c87 316 unsigned int i;
f9f38e33
HK		 317
318 if (!dev->dbbuf_dbs)
319 return;
320
f9f38e33
HK		 321 c.dbbuf.opcode = nvme_admin_dbbuf;
322 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
323 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
324
325 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
9bdcfb10 326 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
f9f38e33
HK		 327 /* Free memory and continue on */
328 nvme_dbbuf_dma_free(dev);
0f0d2c87
MI		 329
330 for (i = 1; i <= dev->online_queues; i++)
331 nvme_dbbuf_free(&dev->queues[i]);
f9f38e33
HK		 332 }
333}
334
335static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
336{
337 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
338}
339
340/* Update dbbuf and return true if an MMIO is required */
341static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
342 volatile u32 *dbbuf_ei)
343{
344 if (dbbuf_db) {
345 u16 old_value;
346
347 /*
348 * Ensure that the queue is written before updating
349 * the doorbell in memory
350 */
351 wmb();
352
353 old_value = *dbbuf_db;
354 *dbbuf_db = value;
355
f1ed3df2
MW		 356 /*
357 * Ensure that the doorbell is updated before reading the event
358 * index from memory. The controller needs to provide similar
359 * ordering to ensure the envent index is updated before reading
360 * the doorbell.
361 */
362 mb();
363
f9f38e33
HK		 364 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value))
365 return false;
366 }
367
368 return true;
b60503ba
MW		 369}
370
ac3dd5bd
JA		 371/*
372 * Will slightly overestimate the number of pages needed. This is OK
373 * as it only leads to a small amount of wasted memory for the lifetime of
374 * the I/O.
375 */
b13c6393 376static int nvme_pci_npages_prp(void)
ac3dd5bd 377{
b13c6393 378 unsigned nprps = DIV_ROUND_UP(NVME_MAX_KB_SZ + NVME_CTRL_PAGE_SIZE,
6c3c05b0 379 NVME_CTRL_PAGE_SIZE);
ac3dd5bd
JA		 380 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
381}
382
a7a7cbe3
CK		 383/*
384 * Calculates the number of pages needed for the SGL segments. For example a 4k
385 * page can accommodate 256 SGL descriptors.
386 */
b13c6393 387static int nvme_pci_npages_sgl(void)
ac3dd5bd 388{
b13c6393
CK		 389 return DIV_ROUND_UP(NVME_MAX_SEGS * sizeof(struct nvme_sgl_desc),
390 PAGE_SIZE);
f4800d6d 391}
ac3dd5bd 392
b13c6393 393static size_t nvme_pci_iod_alloc_size(void)
f4800d6d 394{
b13c6393 395 size_t npages = max(nvme_pci_npages_prp(), nvme_pci_npages_sgl());
a7a7cbe3 396
b13c6393
CK		 397 return sizeof(__le64 *) * npages +
398 sizeof(struct scatterlist) * NVME_MAX_SEGS;
f4800d6d 399}
ac3dd5bd 400
a4aea562
MB		 401static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
402 unsigned int hctx_idx)
e85248e5 403{
a4aea562 404 struct nvme_dev *dev = data;
147b27e4 405 struct nvme_queue *nvmeq = &dev->queues[0];
a4aea562 406
42483228
KB		 407 WARN_ON(hctx_idx != 0);
408 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
42483228 409
a4aea562
MB		 410 hctx->driver_data = nvmeq;
411 return 0;
e85248e5
MW		 412}
413
a4aea562
MB		 414static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
415 unsigned int hctx_idx)
b60503ba 416{
a4aea562 417 struct nvme_dev *dev = data;
147b27e4 418 struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
a4aea562 419
42483228 420 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
a4aea562
MB		 421 hctx->driver_data = nvmeq;
422 return 0;
b60503ba
MW		 423}
424
e559398f
CH		 425static int nvme_pci_init_request(struct blk_mq_tag_set *set,
426 struct request *req, unsigned int hctx_idx,
427 unsigned int numa_node)
b60503ba 428{
d6296d39 429 struct nvme_dev *dev = set->driver_data;
f4800d6d 430 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
59e29ce6
SG		 431
432 nvme_req(req)->ctrl = &dev->ctrl;
f4b9e6c9 433 nvme_req(req)->cmd = &iod->cmd;
a4aea562
MB		 434 return 0;
435}
436
3b6592f7
JA		 437static int queue_irq_offset(struct nvme_dev *dev)
438{
439 /* if we have more than 1 vec, admin queue offsets us by 1 */
440 if (dev->num_vecs > 1)
441 return 1;
442
443 return 0;
444}
445
a4e1d0b7 446static void nvme_pci_map_queues(struct blk_mq_tag_set *set)
dca51e78
CH		 447{
448 struct nvme_dev *dev = set->driver_data;
3b6592f7
JA		 449 int i, qoff, offset;
450
451 offset = queue_irq_offset(dev);
452 for (i = 0, qoff = 0; i < set->nr_maps; i++) {
453 struct blk_mq_queue_map *map = &set->map[i];
454
455 map->nr_queues = dev->io_queues[i];
456 if (!map->nr_queues) {
e20ba6e1 457 BUG_ON(i == HCTX_TYPE_DEFAULT);
7e849dd9 458 continue;
3b6592f7
JA		 459 }
460
4b04cc6a
JA		 461 /*
462 * The poll queue(s) doesn't have an IRQ (and hence IRQ
463 * affinity), so use the regular blk-mq cpu mapping
464 */
3b6592f7 465 map->queue_offset = qoff;
cb9e0e50 466 if (i != HCTX_TYPE_POLL && offset)
4b04cc6a
JA		 467 blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset);
468 else
469 blk_mq_map_queues(map);
3b6592f7
JA		 470 qoff += map->nr_queues;
471 offset += map->nr_queues;
472 }
dca51e78
CH		 473}
474
38210800
KB		 475/*
476 * Write sq tail if we are asked to, or if the next command would wrap.
477 */
478static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq)
04f3eafd 479{
38210800
KB		 480 if (!write_sq) {
481 u16 next_tail = nvmeq->sq_tail + 1;
482
483 if (next_tail == nvmeq->q_depth)
484 next_tail = 0;
485 if (next_tail != nvmeq->last_sq_tail)
486 return;
487 }
488
04f3eafd
JA		 489 if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail,
490 nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei))
491 writel(nvmeq->sq_tail, nvmeq->q_db);
38210800 492 nvmeq->last_sq_tail = nvmeq->sq_tail;
04f3eafd
JA		 493}
494
3233b94c
JA		 495static inline void nvme_sq_copy_cmd(struct nvme_queue *nvmeq,
496 struct nvme_command *cmd)
b60503ba 497{
c1e0cc7e 498 memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes),
3233b94c 499 absolute_pointer(cmd), sizeof(*cmd));
90ea5ca4
CH		 500 if (++nvmeq->sq_tail == nvmeq->q_depth)
501 nvmeq->sq_tail = 0;
04f3eafd
JA		 502}
503
504static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx)
505{
506 struct nvme_queue *nvmeq = hctx->driver_data;
507
508 spin_lock(&nvmeq->sq_lock);
38210800
KB		 509 if (nvmeq->sq_tail != nvmeq->last_sq_tail)
510 nvme_write_sq_db(nvmeq, true);
90ea5ca4 511 spin_unlock(&nvmeq->sq_lock);
b60503ba
MW		 512}
513
a7a7cbe3 514static void **nvme_pci_iod_list(struct request *req)
b60503ba 515{
f4800d6d 516 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
91fb2b60 517 return (void **)(iod->sgt.sgl + blk_rq_nr_phys_segments(req));
b60503ba
MW		 518}
519
955b1b5a
MI		 520static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req)
521{
a53232cb 522 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
20469a37 523 int nseg = blk_rq_nr_phys_segments(req);
955b1b5a
MI		 524 unsigned int avg_seg_size;
525
20469a37 526 avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
955b1b5a 527
253a0b76 528 if (!nvme_ctrl_sgl_supported(&dev->ctrl))
955b1b5a 529 return false;
a53232cb 530 if (!nvmeq->qid)
955b1b5a
MI		 531 return false;
532 if (!sgl_threshold || avg_seg_size < sgl_threshold)
533 return false;
534 return true;
535}
536
9275c206 537static void nvme_free_prps(struct nvme_dev *dev, struct request *req)
b60503ba 538{
6c3c05b0 539 const int last_prp = NVME_CTRL_PAGE_SIZE / sizeof(__le64) - 1;
9275c206
CH		 540 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
541 dma_addr_t dma_addr = iod->first_dma;
eca18b23 542 int i;
eca18b23 543
c372cdd1 544 for (i = 0; i < iod->nr_allocations; i++) {
9275c206
CH		 545 __le64 *prp_list = nvme_pci_iod_list(req)[i];
546 dma_addr_t next_dma_addr = le64_to_cpu(prp_list[last_prp]);
547
548 dma_pool_free(dev->prp_page_pool, prp_list, dma_addr);
549 dma_addr = next_dma_addr;
7fe07d14 550 }
9275c206 551}
dff824b2 552
9275c206
CH		 553static void nvme_free_sgls(struct nvme_dev *dev, struct request *req)
554{
555 const int last_sg = SGES_PER_PAGE - 1;
556 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
557 dma_addr_t dma_addr = iod->first_dma;
558 int i;
dff824b2 559
c372cdd1 560 for (i = 0; i < iod->nr_allocations; i++) {
9275c206
CH		 561 struct nvme_sgl_desc *sg_list = nvme_pci_iod_list(req)[i];
562 dma_addr_t next_dma_addr = le64_to_cpu((sg_list[last_sg]).addr);
dff824b2 563
9275c206
CH		 564 dma_pool_free(dev->prp_page_pool, sg_list, dma_addr);
565 dma_addr = next_dma_addr;
566 }
9275c206 567}
a7a7cbe3 568
9275c206
CH		 569static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
570{
571 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3 572
9275c206
CH		 573 if (iod->dma_len) {
574 dma_unmap_page(dev->dev, iod->first_dma, iod->dma_len,
575 rq_dma_dir(req));
576 return;
eca18b23 577 }
ac3dd5bd 578
91fb2b60
LG		 579 WARN_ON_ONCE(!iod->sgt.nents);
580
581 dma_unmap_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req), 0);
9275c206 582
c372cdd1 583 if (iod->nr_allocations == 0)
9275c206
CH		 584 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0],
585 iod->first_dma);
586 else if (iod->use_sgl)
587 nvme_free_sgls(dev, req);
588 else
589 nvme_free_prps(dev, req);
91fb2b60 590 mempool_free(iod->sgt.sgl, dev->iod_mempool);
b4ff9c8d
KB		 591}
592
d0877473
KB		 593static void nvme_print_sgl(struct scatterlist *sgl, int nents)
594{
595 int i;
596 struct scatterlist *sg;
597
598 for_each_sg(sgl, sg, nents, i) {
599 dma_addr_t phys = sg_phys(sg);
600 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
601 "dma_address:%pad dma_length:%d\n",
602 i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
603 sg_dma_len(sg));
604 }
605}
606
a7a7cbe3
CK		 607static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
608 struct request *req, struct nvme_rw_command *cmnd)
ff22b54f 609{
f4800d6d 610 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
99802a7a 611 struct dma_pool *pool;
b131c61d 612 int length = blk_rq_payload_bytes(req);
91fb2b60 613 struct scatterlist *sg = iod->sgt.sgl;
ff22b54f
MW		 614 int dma_len = sg_dma_len(sg);
615 u64 dma_addr = sg_dma_address(sg);
6c3c05b0 616 int offset = dma_addr & (NVME_CTRL_PAGE_SIZE - 1);
e025344c 617 __le64 *prp_list;
a7a7cbe3 618 void **list = nvme_pci_iod_list(req);
e025344c 619 dma_addr_t prp_dma;
eca18b23 620 int nprps, i;
ff22b54f 621
6c3c05b0 622 length -= (NVME_CTRL_PAGE_SIZE - offset);
5228b328
JS		 623 if (length <= 0) {
624 iod->first_dma = 0;
a7a7cbe3 625 goto done;
5228b328 626 }
ff22b54f 627
6c3c05b0 628 dma_len -= (NVME_CTRL_PAGE_SIZE - offset);
ff22b54f 629 if (dma_len) {
6c3c05b0 630 dma_addr += (NVME_CTRL_PAGE_SIZE - offset);
ff22b54f
MW		 631 } else {
632 sg = sg_next(sg);
633 dma_addr = sg_dma_address(sg);
634 dma_len = sg_dma_len(sg);
635 }
636
6c3c05b0 637 if (length <= NVME_CTRL_PAGE_SIZE) {
edd10d33 638 iod->first_dma = dma_addr;
a7a7cbe3 639 goto done;
e025344c
SMM		 640 }
641
6c3c05b0 642 nprps = DIV_ROUND_UP(length, NVME_CTRL_PAGE_SIZE);
99802a7a
MW		 643 if (nprps <= (256 / 8)) {
644 pool = dev->prp_small_pool;
c372cdd1 645 iod->nr_allocations = 0;
99802a7a
MW		 646 } else {
647 pool = dev->prp_page_pool;
c372cdd1 648 iod->nr_allocations = 1;
99802a7a
MW		 649 }
650
69d2b571 651 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
b77954cb 652 if (!prp_list) {
c372cdd1 653 iod->nr_allocations = -1;
86eea289 654 return BLK_STS_RESOURCE;
b77954cb 655 }
eca18b23
MW		 656 list[0] = prp_list;
657 iod->first_dma = prp_dma;
e025344c
SMM		 658 i = 0;
659 for (;;) {
6c3c05b0 660 if (i == NVME_CTRL_PAGE_SIZE >> 3) {
e025344c 661 __le64 *old_prp_list = prp_list;
69d2b571 662 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
eca18b23 663 if (!prp_list)
fa073216 664 goto free_prps;
c372cdd1 665 list[iod->nr_allocations++] = prp_list;
7523d834
MW		 666 prp_list[0] = old_prp_list[i - 1];
667 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
668 i = 1;
e025344c
SMM		 669 }
670 prp_list[i++] = cpu_to_le64(dma_addr);
6c3c05b0
CK		 671 dma_len -= NVME_CTRL_PAGE_SIZE;
672 dma_addr += NVME_CTRL_PAGE_SIZE;
673 length -= NVME_CTRL_PAGE_SIZE;
e025344c
SMM		 674 if (length <= 0)
675 break;
676 if (dma_len > 0)
677 continue;
86eea289
KB		 678 if (unlikely(dma_len < 0))
679 goto bad_sgl;
e025344c
SMM		 680 sg = sg_next(sg);
681 dma_addr = sg_dma_address(sg);
682 dma_len = sg_dma_len(sg);
ff22b54f 683 }
a7a7cbe3 684done:
91fb2b60 685 cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sgt.sgl));
a7a7cbe3 686 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
86eea289 687 return BLK_STS_OK;
fa073216
CH		 688free_prps:
689 nvme_free_prps(dev, req);
690 return BLK_STS_RESOURCE;
691bad_sgl:
91fb2b60 692 WARN(DO_ONCE(nvme_print_sgl, iod->sgt.sgl, iod->sgt.nents),
d0877473 693 "Invalid SGL for payload:%d nents:%d\n",
91fb2b60 694 blk_rq_payload_bytes(req), iod->sgt.nents);
86eea289 695 return BLK_STS_IOERR;
ff22b54f
MW		 696}
697
a7a7cbe3
CK		 698static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
699 struct scatterlist *sg)
700{
701 sge->addr = cpu_to_le64(sg_dma_address(sg));
702 sge->length = cpu_to_le32(sg_dma_len(sg));
703 sge->type = NVME_SGL_FMT_DATA_DESC << 4;
704}
705
706static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
707 dma_addr_t dma_addr, int entries)
708{
709 sge->addr = cpu_to_le64(dma_addr);
710 if (entries < SGES_PER_PAGE) {
711 sge->length = cpu_to_le32(entries * sizeof(*sge));
712 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
713 } else {
714 sge->length = cpu_to_le32(PAGE_SIZE);
715 sge->type = NVME_SGL_FMT_SEG_DESC << 4;
716 }
717}
718
719static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
91fb2b60 720 struct request *req, struct nvme_rw_command *cmd)
a7a7cbe3
CK		 721{
722 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3
CK		 723 struct dma_pool *pool;
724 struct nvme_sgl_desc *sg_list;
91fb2b60
LG		 725 struct scatterlist *sg = iod->sgt.sgl;
726 unsigned int entries = iod->sgt.nents;
a7a7cbe3 727 dma_addr_t sgl_dma;
b0f2853b 728 int i = 0;
a7a7cbe3 729
a7a7cbe3
CK		 730 /* setting the transfer type as SGL */
731 cmd->flags = NVME_CMD_SGL_METABUF;
732
b0f2853b 733 if (entries == 1) {
a7a7cbe3
CK		 734 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
735 return BLK_STS_OK;
736 }
737
738 if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
739 pool = dev->prp_small_pool;
c372cdd1 740 iod->nr_allocations = 0;
a7a7cbe3
CK		 741 } else {
742 pool = dev->prp_page_pool;
c372cdd1 743 iod->nr_allocations = 1;
a7a7cbe3
CK		 744 }
745
746 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
747 if (!sg_list) {
c372cdd1 748 iod->nr_allocations = -1;
a7a7cbe3
CK		 749 return BLK_STS_RESOURCE;
750 }
751
752 nvme_pci_iod_list(req)[0] = sg_list;
753 iod->first_dma = sgl_dma;
754
755 nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
756
757 do {
758 if (i == SGES_PER_PAGE) {
759 struct nvme_sgl_desc *old_sg_desc = sg_list;
760 struct nvme_sgl_desc *link = &old_sg_desc[i - 1];
761
762 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
763 if (!sg_list)
fa073216 764 goto free_sgls;
a7a7cbe3
CK		 765
766 i = 0;
c372cdd1 767 nvme_pci_iod_list(req)[iod->nr_allocations++] = sg_list;
a7a7cbe3
CK		 768 sg_list[i++] = *link;
769 nvme_pci_sgl_set_seg(link, sgl_dma, entries);
770 }
771
772 nvme_pci_sgl_set_data(&sg_list[i++], sg);
a7a7cbe3 773 sg = sg_next(sg);
b0f2853b 774 } while (--entries > 0);
a7a7cbe3 775
a7a7cbe3 776 return BLK_STS_OK;
fa073216
CH		 777free_sgls:
778 nvme_free_sgls(dev, req);
779 return BLK_STS_RESOURCE;
a7a7cbe3
CK		 780}
781
dff824b2
CH		 782static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev,
783 struct request *req, struct nvme_rw_command *cmnd,
784 struct bio_vec *bv)
785{
786 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
6c3c05b0
CK		 787 unsigned int offset = bv->bv_offset & (NVME_CTRL_PAGE_SIZE - 1);
788 unsigned int first_prp_len = NVME_CTRL_PAGE_SIZE - offset;
dff824b2
CH		 789
790 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
791 if (dma_mapping_error(dev->dev, iod->first_dma))
792 return BLK_STS_RESOURCE;
793 iod->dma_len = bv->bv_len;
794
795 cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma);
796 if (bv->bv_len > first_prp_len)
797 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len);
359c1f88 798 return BLK_STS_OK;
dff824b2
CH		 799}
800
29791057
CH		 801static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev,
802 struct request *req, struct nvme_rw_command *cmnd,
803 struct bio_vec *bv)
804{
805 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
806
807 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
808 if (dma_mapping_error(dev->dev, iod->first_dma))
809 return BLK_STS_RESOURCE;
810 iod->dma_len = bv->bv_len;
811
049bf372 812 cmnd->flags = NVME_CMD_SGL_METABUF;
29791057
CH		 813 cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma);
814 cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len);
815 cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4;
359c1f88 816 return BLK_STS_OK;
29791057
CH		 817}
818
fc17b653 819static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
b131c61d 820 struct nvme_command *cmnd)
d29ec824 821{
f4800d6d 822 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
70479b71 823 blk_status_t ret = BLK_STS_RESOURCE;
91fb2b60 824 int rc;
d29ec824 825
dff824b2 826 if (blk_rq_nr_phys_segments(req) == 1) {
a53232cb 827 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
dff824b2
CH		 828 struct bio_vec bv = req_bvec(req);
829
830 if (!is_pci_p2pdma_page(bv.bv_page)) {
6c3c05b0 831 if (bv.bv_offset + bv.bv_len <= NVME_CTRL_PAGE_SIZE * 2)
dff824b2
CH		 832 return nvme_setup_prp_simple(dev, req,
833 &cmnd->rw, &bv);
29791057 834
a53232cb 835 if (nvmeq->qid && sgl_threshold &&
253a0b76 836 nvme_ctrl_sgl_supported(&dev->ctrl))
29791057
CH		 837 return nvme_setup_sgl_simple(dev, req,
838 &cmnd->rw, &bv);
dff824b2
CH		 839 }
840 }
841
842 iod->dma_len = 0;
91fb2b60
LG		 843 iod->sgt.sgl = mempool_alloc(dev->iod_mempool, GFP_ATOMIC);
844 if (!iod->sgt.sgl)
d43f1ccf 845 return BLK_STS_RESOURCE;
91fb2b60
LG		 846 sg_init_table(iod->sgt.sgl, blk_rq_nr_phys_segments(req));
847 iod->sgt.orig_nents = blk_rq_map_sg(req->q, req, iod->sgt.sgl);
848 if (!iod->sgt.orig_nents)
fa073216 849 goto out_free_sg;
d29ec824 850
91fb2b60
LG		 851 rc = dma_map_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req),
852 DMA_ATTR_NO_WARN);
853 if (rc) {
854 if (rc == -EREMOTEIO)
855 ret = BLK_STS_TARGET;
fa073216 856 goto out_free_sg;
91fb2b60 857 }
d29ec824 858
70479b71 859 iod->use_sgl = nvme_pci_use_sgls(dev, req);
955b1b5a 860 if (iod->use_sgl)
91fb2b60 861 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw);
a7a7cbe3
CK		 862 else
863 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
86eea289 864 if (ret != BLK_STS_OK)
fa073216
CH		 865 goto out_unmap_sg;
866 return BLK_STS_OK;
867
868out_unmap_sg:
91fb2b60 869 dma_unmap_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req), 0);
fa073216 870out_free_sg:
91fb2b60 871 mempool_free(iod->sgt.sgl, dev->iod_mempool);
4aedb705
CH		 872 return ret;
873}
3045c0d0 874
4aedb705
CH		 875static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req,
876 struct nvme_command *cmnd)
877{
878 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
00df5cb4 879
4aedb705
CH		 880 iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req),
881 rq_dma_dir(req), 0);
882 if (dma_mapping_error(dev->dev, iod->meta_dma))
883 return BLK_STS_IOERR;
884 cmnd->rw.metadata = cpu_to_le64(iod->meta_dma);
359c1f88 885 return BLK_STS_OK;
00df5cb4
MW		 886}
887
62451a2b 888static blk_status_t nvme_prep_rq(struct nvme_dev *dev, struct request *req)
edd10d33 889{
9b048119 890 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
ebe6d874 891 blk_status_t ret;
e1e5e564 892
52da4f3f 893 iod->aborted = false;
c372cdd1 894 iod->nr_allocations = -1;
91fb2b60 895 iod->sgt.nents = 0;
9b048119 896
62451a2b 897 ret = nvme_setup_cmd(req->q->queuedata, req);
fc17b653 898 if (ret)
f4800d6d 899 return ret;
a4aea562 900
fc17b653 901 if (blk_rq_nr_phys_segments(req)) {
62451a2b 902 ret = nvme_map_data(dev, req, &iod->cmd);
fc17b653 903 if (ret)
9b048119 904 goto out_free_cmd;
fc17b653 905 }
a4aea562 906
4aedb705 907 if (blk_integrity_rq(req)) {
62451a2b 908 ret = nvme_map_metadata(dev, req, &iod->cmd);
4aedb705
CH		 909 if (ret)
910 goto out_unmap_data;
911 }
912
aae239e1 913 blk_mq_start_request(req);
fc17b653 914 return BLK_STS_OK;
4aedb705
CH		 915out_unmap_data:
916 nvme_unmap_data(dev, req);
f9d03f96
CH		 917out_free_cmd:
918 nvme_cleanup_cmd(req);
ba1ca37e 919 return ret;
b60503ba 920}
e1e5e564 921
62451a2b
JA		 922/*
923 * NOTE: ns is NULL when called on the admin queue.
924 */
925static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
926 const struct blk_mq_queue_data *bd)
927{
928 struct nvme_queue *nvmeq = hctx->driver_data;
929 struct nvme_dev *dev = nvmeq->dev;
930 struct request *req = bd->rq;
931 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
932 blk_status_t ret;
933
934 /*
935 * We should not need to do this, but we're still using this to
936 * ensure we can drain requests on a dying queue.
937 */
938 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
939 return BLK_STS_IOERR;
940
941 if (unlikely(!nvme_check_ready(&dev->ctrl, req, true)))
942 return nvme_fail_nonready_command(&dev->ctrl, req);
943
944 ret = nvme_prep_rq(dev, req);
945 if (unlikely(ret))
946 return ret;
947 spin_lock(&nvmeq->sq_lock);
948 nvme_sq_copy_cmd(nvmeq, &iod->cmd);
949 nvme_write_sq_db(nvmeq, bd->last);
950 spin_unlock(&nvmeq->sq_lock);
951 return BLK_STS_OK;
952}
953
d62cbcf6
JA		 954static void nvme_submit_cmds(struct nvme_queue *nvmeq, struct request **rqlist)
955{
956 spin_lock(&nvmeq->sq_lock);
957 while (!rq_list_empty(*rqlist)) {
958 struct request *req = rq_list_pop(rqlist);
959 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
960
961 nvme_sq_copy_cmd(nvmeq, &iod->cmd);
962 }
963 nvme_write_sq_db(nvmeq, true);
964 spin_unlock(&nvmeq->sq_lock);
965}
966
967static bool nvme_prep_rq_batch(struct nvme_queue *nvmeq, struct request *req)
968{
969 /*
970 * We should not need to do this, but we're still using this to
971 * ensure we can drain requests on a dying queue.
972 */
973 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
974 return false;
975 if (unlikely(!nvme_check_ready(&nvmeq->dev->ctrl, req, true)))
976 return false;
977
978 req->mq_hctx->tags->rqs[req->tag] = req;
979 return nvme_prep_rq(nvmeq->dev, req) == BLK_STS_OK;
980}
981
982static void nvme_queue_rqs(struct request **rqlist)
983{
6bfec799 984 struct request *req, *next, *prev = NULL;
d62cbcf6
JA		 985 struct request *requeue_list = NULL;
986
6bfec799 987 rq_list_for_each_safe(rqlist, req, next) {
d62cbcf6
JA		 988 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
989
990 if (!nvme_prep_rq_batch(nvmeq, req)) {
991 /* detach 'req' and add to remainder list */
6bfec799
KB		 992 rq_list_move(rqlist, &requeue_list, req, prev);
993
994 req = prev;
995 if (!req)
996 continue;
d62cbcf6
JA		 997 }
998
6bfec799 999 if (!next || req->mq_hctx != next->mq_hctx) {
d62cbcf6 1000 /* detach rest of list, and submit */
6bfec799 1001 req->rq_next = NULL;
d62cbcf6 1002 nvme_submit_cmds(nvmeq, rqlist);
6bfec799
KB		 1003 *rqlist = next;
1004 prev = NULL;
1005 } else
1006 prev = req;
1007 }
d62cbcf6
JA		 1008
1009 *rqlist = requeue_list;
1010}
1011
c234a653 1012static __always_inline void nvme_pci_unmap_rq(struct request *req)
eee417b0 1013{
a53232cb
KB		 1014 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
1015 struct nvme_dev *dev = nvmeq->dev;
1016
1017 if (blk_integrity_rq(req)) {
1018 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a4aea562 1019
4aedb705
CH		 1020 dma_unmap_page(dev->dev, iod->meta_dma,
1021 rq_integrity_vec(req)->bv_len, rq_data_dir(req));
a53232cb
KB		 1022 }
1023
b15c592d 1024 if (blk_rq_nr_phys_segments(req))
4aedb705 1025 nvme_unmap_data(dev, req);
c234a653
JA		 1026}
1027
1028static void nvme_pci_complete_rq(struct request *req)
1029{
1030 nvme_pci_unmap_rq(req);
77f02a7a 1031 nvme_complete_rq(req);
b60503ba
MW		 1032}
1033
c234a653
JA		 1034static void nvme_pci_complete_batch(struct io_comp_batch *iob)
1035{
1036 nvme_complete_batch(iob, nvme_pci_unmap_rq);
1037}
1038
d783e0bd 1039/* We read the CQE phase first to check if the rest of the entry is valid */
750dde44 1040static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq)
d783e0bd 1041{
74943d45
KB		 1042 struct nvme_completion *hcqe = &nvmeq->cqes[nvmeq->cq_head];
1043
1044 return (le16_to_cpu(READ_ONCE(hcqe->status)) & 1) == nvmeq->cq_phase;
d783e0bd
MR		 1045}
1046
eb281c82 1047static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
b60503ba 1048{
eb281c82 1049 u16 head = nvmeq->cq_head;
adf68f21 1050
397c699f
KB		 1051 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
1052 nvmeq->dbbuf_cq_ei))
1053 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
eb281c82 1054}
aae239e1 1055
cfa27356
CH		 1056static inline struct blk_mq_tags *nvme_queue_tagset(struct nvme_queue *nvmeq)
1057{
1058 if (!nvmeq->qid)
1059 return nvmeq->dev->admin_tagset.tags[0];
1060 return nvmeq->dev->tagset.tags[nvmeq->qid - 1];
1061}
1062
c234a653
JA		 1063static inline void nvme_handle_cqe(struct nvme_queue *nvmeq,
1064 struct io_comp_batch *iob, u16 idx)
83a12fb7 1065{
74943d45 1066 struct nvme_completion *cqe = &nvmeq->cqes[idx];
62df8016 1067 __u16 command_id = READ_ONCE(cqe->command_id);
83a12fb7 1068 struct request *req;
adf68f21 1069
83a12fb7
SG		 1070 /*
1071 * AEN requests are special as they don't time out and can
1072 * survive any kind of queue freeze and often don't respond to
1073 * aborts. We don't even bother to allocate a struct request
1074 * for them but rather special case them here.
1075 */
62df8016 1076 if (unlikely(nvme_is_aen_req(nvmeq->qid, command_id))) {
83a12fb7
SG		 1077 nvme_complete_async_event(&nvmeq->dev->ctrl,
1078 cqe->status, &cqe->result);
a0fa9647 1079 return;
83a12fb7 1080 }
b60503ba 1081
e7006de6 1082 req = nvme_find_rq(nvme_queue_tagset(nvmeq), command_id);
50b7c243
XT		 1083 if (unlikely(!req)) {
1084 dev_warn(nvmeq->dev->ctrl.device,
1085 "invalid id %d completed on queue %d\n",
62df8016 1086 command_id, le16_to_cpu(cqe->sq_id));
50b7c243
XT		 1087 return;
1088 }
1089
604c01d5 1090 trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail);
c234a653
JA		 1091 if (!nvme_try_complete_req(req, cqe->status, cqe->result) &&
1092 !blk_mq_add_to_batch(req, iob, nvme_req(req)->status,
1093 nvme_pci_complete_batch))
ff029451 1094 nvme_pci_complete_rq(req);
83a12fb7 1095}
b60503ba 1096
5cb525c8
JA		 1097static inline void nvme_update_cq_head(struct nvme_queue *nvmeq)
1098{
a0aac973 1099 u32 tmp = nvmeq->cq_head + 1;
a8de6639
AD		 1100
1101 if (tmp == nvmeq->q_depth) {
5cb525c8 1102 nvmeq->cq_head = 0;
e2a366a4 1103 nvmeq->cq_phase ^= 1;
a8de6639
AD		 1104 } else {
1105 nvmeq->cq_head = tmp;
b60503ba 1106 }
a0fa9647
JA		 1107}
1108
c234a653
JA		 1109static inline int nvme_poll_cq(struct nvme_queue *nvmeq,
1110 struct io_comp_batch *iob)
a0fa9647 1111{
1052b8ac 1112 int found = 0;
b60503ba 1113
1052b8ac 1114 while (nvme_cqe_pending(nvmeq)) {
bf392a5d 1115 found++;
b69e2ef2
KB		 1116 /*
1117 * load-load control dependency between phase and the rest of
1118 * the cqe requires a full read memory barrier
1119 */
1120 dma_rmb();
c234a653 1121 nvme_handle_cqe(nvmeq, iob, nvmeq->cq_head);
5cb525c8 1122 nvme_update_cq_head(nvmeq);
920d13a8 1123 }
eb281c82 1124
324b494c 1125 if (found)
920d13a8 1126 nvme_ring_cq_doorbell(nvmeq);
5cb525c8 1127 return found;
b60503ba
MW		 1128}
1129
1130static irqreturn_t nvme_irq(int irq, void *data)
58ffacb5 1131{
58ffacb5 1132 struct nvme_queue *nvmeq = data;
4f502245 1133 DEFINE_IO_COMP_BATCH(iob);
5cb525c8 1134
4f502245
JA		 1135 if (nvme_poll_cq(nvmeq, &iob)) {
1136 if (!rq_list_empty(iob.req_list))
1137 nvme_pci_complete_batch(&iob);
05fae499 1138 return IRQ_HANDLED;
4f502245 1139 }
05fae499 1140 return IRQ_NONE;
58ffacb5
MW		 1141}
1142
1143static irqreturn_t nvme_irq_check(int irq, void *data)
1144{
1145 struct nvme_queue *nvmeq = data;
4e523547 1146
750dde44 1147 if (nvme_cqe_pending(nvmeq))
d783e0bd
MR		 1148 return IRQ_WAKE_THREAD;
1149 return IRQ_NONE;
58ffacb5
MW		 1150}
1151
0b2a8a9f 1152/*
fa059b85 1153 * Poll for completions for any interrupt driven queue
0b2a8a9f
CH		 1154 * Can be called from any context.
1155 */
fa059b85 1156static void nvme_poll_irqdisable(struct nvme_queue *nvmeq)
a0fa9647 1157{
3a7afd8e 1158 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
a0fa9647 1159
fa059b85 1160 WARN_ON_ONCE(test_bit(NVMEQ_POLLED, &nvmeq->flags));
442e19b7 1161
fa059b85 1162 disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
c234a653 1163 nvme_poll_cq(nvmeq, NULL);
fa059b85 1164 enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
a0fa9647
JA		 1165}
1166
5a72e899 1167static int nvme_poll(struct blk_mq_hw_ctx *hctx, struct io_comp_batch *iob)
dabcefab
JA		 1168{
1169 struct nvme_queue *nvmeq = hctx->driver_data;
dabcefab
JA		 1170 bool found;
1171
1172 if (!nvme_cqe_pending(nvmeq))
1173 return 0;
1174
3a7afd8e 1175 spin_lock(&nvmeq->cq_poll_lock);
c234a653 1176 found = nvme_poll_cq(nvmeq, iob);
3a7afd8e 1177 spin_unlock(&nvmeq->cq_poll_lock);
dabcefab 1178
dabcefab
JA		 1179 return found;
1180}
1181
ad22c355 1182static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
b60503ba 1183{
f866fc42 1184 struct nvme_dev *dev = to_nvme_dev(ctrl);
147b27e4 1185 struct nvme_queue *nvmeq = &dev->queues[0];
f66e2804 1186 struct nvme_command c = { };
b60503ba 1187
a4aea562 1188 c.common.opcode = nvme_admin_async_event;
ad22c355 1189 c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
3233b94c
JA		 1190
1191 spin_lock(&nvmeq->sq_lock);
1192 nvme_sq_copy_cmd(nvmeq, &c);
1193 nvme_write_sq_db(nvmeq, true);
1194 spin_unlock(&nvmeq->sq_lock);
f705f837
CH		 1195}
1196
b60503ba 1197static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
f705f837 1198{
f66e2804 1199 struct nvme_command c = { };
b60503ba 1200
b60503ba
MW		 1201 c.delete_queue.opcode = opcode;
1202 c.delete_queue.qid = cpu_to_le16(id);
1203
1c63dc66 1204 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1205}
1206
b60503ba 1207static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
a8e3e0bb 1208 struct nvme_queue *nvmeq, s16 vector)
b60503ba 1209{
f66e2804 1210 struct nvme_command c = { };
4b04cc6a
JA		 1211 int flags = NVME_QUEUE_PHYS_CONTIG;
1212
7c349dde 1213 if (!test_bit(NVMEQ_POLLED, &nvmeq->flags))
4b04cc6a 1214 flags |= NVME_CQ_IRQ_ENABLED;
b60503ba 1215
d29ec824 1216 /*
16772ae6 1217 * Note: we (ab)use the fact that the prp fields survive if no data
d29ec824
CH		 1218 * is attached to the request.
1219 */
b60503ba
MW		 1220 c.create_cq.opcode = nvme_admin_create_cq;
1221 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1222 c.create_cq.cqid = cpu_to_le16(qid);
1223 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1224 c.create_cq.cq_flags = cpu_to_le16(flags);
7c349dde 1225 c.create_cq.irq_vector = cpu_to_le16(vector);
b60503ba 1226
1c63dc66 1227 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1228}
1229
1230static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1231 struct nvme_queue *nvmeq)
1232{
9abd68ef 1233 struct nvme_ctrl *ctrl = &dev->ctrl;
f66e2804 1234 struct nvme_command c = { };
81c1cd98 1235 int flags = NVME_QUEUE_PHYS_CONTIG;
b60503ba 1236
9abd68ef
JA		 1237 /*
1238 * Some drives have a bug that auto-enables WRRU if MEDIUM isn't
1239 * set. Since URGENT priority is zeroes, it makes all queues
1240 * URGENT.
1241 */
1242 if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ)
1243 flags |= NVME_SQ_PRIO_MEDIUM;
1244
d29ec824 1245 /*
16772ae6 1246 * Note: we (ab)use the fact that the prp fields survive if no data
d29ec824
CH		 1247 * is attached to the request.
1248 */
b60503ba
MW		 1249 c.create_sq.opcode = nvme_admin_create_sq;
1250 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1251 c.create_sq.sqid = cpu_to_le16(qid);
1252 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1253 c.create_sq.sq_flags = cpu_to_le16(flags);
1254 c.create_sq.cqid = cpu_to_le16(qid);
1255
1c63dc66 1256 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1257}
1258
1259static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1260{
1261 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1262}
1263
1264static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1265{
1266 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1267}
1268
de671d61 1269static enum rq_end_io_ret abort_endio(struct request *req, blk_status_t error)
bc5fc7e4 1270{
a53232cb 1271 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
e44ac588 1272
27fa9bc5
CH		 1273 dev_warn(nvmeq->dev->ctrl.device,
1274 "Abort status: 0x%x", nvme_req(req)->status);
e7a2a87d 1275 atomic_inc(&nvmeq->dev->ctrl.abort_limit);
e7a2a87d 1276 blk_mq_free_request(req);
de671d61 1277 return RQ_END_IO_NONE;
bc5fc7e4
MW		 1278}
1279
b2a0eb1a
KB		 1280static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1281{
b2a0eb1a
KB		 1282 /* If true, indicates loss of adapter communication, possibly by a
1283 * NVMe Subsystem reset.
1284 */
1285 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1286
ad70062c
JW		 1287 /* If there is a reset/reinit ongoing, we shouldn't reset again. */
1288 switch (dev->ctrl.state) {
1289 case NVME_CTRL_RESETTING:
ad6a0a52 1290 case NVME_CTRL_CONNECTING:
b2a0eb1a 1291 return false;
ad70062c
JW		 1292 default:
1293 break;
1294 }
b2a0eb1a
KB		 1295
1296 /* We shouldn't reset unless the controller is on fatal error state
1297 * _or_ if we lost the communication with it.
1298 */
1299 if (!(csts & NVME_CSTS_CFS) && !nssro)
1300 return false;
1301
b2a0eb1a
KB		 1302 return true;
1303}
1304
1305static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1306{
1307 /* Read a config register to help see what died. */
1308 u16 pci_status;
1309 int result;
1310
1311 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1312 &pci_status);
1313 if (result == PCIBIOS_SUCCESSFUL)
1314 dev_warn(dev->ctrl.device,
1315 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1316 csts, pci_status);
1317 else
1318 dev_warn(dev->ctrl.device,
1319 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1320 csts, result);
4641a8e6
KB		 1321
1322 if (csts != ~0)
1323 return;
1324
1325 dev_warn(dev->ctrl.device,
1326 "Does your device have a faulty power saving mode enabled?\n");
1327 dev_warn(dev->ctrl.device,
1328 "Try \"nvme_core.default_ps_max_latency_us=0 pcie_aspm=off\" and report a bug\n");
b2a0eb1a
KB		 1329}
1330
9bdb4833 1331static enum blk_eh_timer_return nvme_timeout(struct request *req)
c30341dc 1332{
f4800d6d 1333 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a53232cb 1334 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
c30341dc 1335 struct nvme_dev *dev = nvmeq->dev;
a4aea562 1336 struct request *abort_req;
f66e2804 1337 struct nvme_command cmd = { };
b2a0eb1a
KB		 1338 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1339
651438bb
WX		 1340 /* If PCI error recovery process is happening, we cannot reset or
1341 * the recovery mechanism will surely fail.
1342 */
1343 mb();
1344 if (pci_channel_offline(to_pci_dev(dev->dev)))
1345 return BLK_EH_RESET_TIMER;
1346
b2a0eb1a
KB		 1347 /*
1348 * Reset immediately if the controller is failed
1349 */
1350 if (nvme_should_reset(dev, csts)) {
1351 nvme_warn_reset(dev, csts);
1352 nvme_dev_disable(dev, false);
d86c4d8e 1353 nvme_reset_ctrl(&dev->ctrl);
db8c48e4 1354 return BLK_EH_DONE;
b2a0eb1a 1355 }
c30341dc 1356
7776db1c
KB		 1357 /*
1358 * Did we miss an interrupt?
1359 */
fa059b85 1360 if (test_bit(NVMEQ_POLLED, &nvmeq->flags))
5a72e899 1361 nvme_poll(req->mq_hctx, NULL);
fa059b85
KB		 1362 else
1363 nvme_poll_irqdisable(nvmeq);
1364
bf392a5d 1365 if (blk_mq_request_completed(req)) {
7776db1c
KB		 1366 dev_warn(dev->ctrl.device,
1367 "I/O %d QID %d timeout, completion polled\n",
1368 req->tag, nvmeq->qid);
db8c48e4 1369 return BLK_EH_DONE;
7776db1c
KB		 1370 }
1371
31c7c7d2 1372 /*
fd634f41
CH		 1373 * Shutdown immediately if controller times out while starting. The
1374 * reset work will see the pci device disabled when it gets the forced
1375 * cancellation error. All outstanding requests are completed on
db8c48e4 1376 * shutdown, so we return BLK_EH_DONE.
fd634f41 1377 */
4244140d
KB		 1378 switch (dev->ctrl.state) {
1379 case NVME_CTRL_CONNECTING:
2036f726 1380 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
df561f66 1381 fallthrough;
2036f726 1382 case NVME_CTRL_DELETING:
b9cac43c 1383 dev_warn_ratelimited(dev->ctrl.device,
fd634f41
CH		 1384 "I/O %d QID %d timeout, disable controller\n",
1385 req->tag, nvmeq->qid);
27fa9bc5 1386 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
7ad92f65 1387 nvme_dev_disable(dev, true);
db8c48e4 1388 return BLK_EH_DONE;
39a9dd81
KB		 1389 case NVME_CTRL_RESETTING:
1390 return BLK_EH_RESET_TIMER;
4244140d
KB		 1391 default:
1392 break;
c30341dc
KB		 1393 }
1394
fd634f41 1395 /*
ee0d96d3
BW		 1396 * Shutdown the controller immediately and schedule a reset if the
1397 * command was already aborted once before and still hasn't been
1398 * returned to the driver, or if this is the admin queue.
31c7c7d2 1399 */
f4800d6d 1400 if (!nvmeq->qid || iod->aborted) {
1b3c47c1 1401 dev_warn(dev->ctrl.device,
e1569a16
KB		 1402 "I/O %d QID %d timeout, reset controller\n",
1403 req->tag, nvmeq->qid);
7ad92f65 1404 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
a5cdb68c 1405 nvme_dev_disable(dev, false);
d86c4d8e 1406 nvme_reset_ctrl(&dev->ctrl);
c30341dc 1407
db8c48e4 1408 return BLK_EH_DONE;
c30341dc 1409 }
c30341dc 1410
e7a2a87d 1411 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
6bf25d16 1412 atomic_inc(&dev->ctrl.abort_limit);
31c7c7d2 1413 return BLK_EH_RESET_TIMER;
6bf25d16 1414 }
52da4f3f 1415 iod->aborted = true;
a4aea562 1416
c30341dc 1417 cmd.abort.opcode = nvme_admin_abort_cmd;
85f74acf 1418 cmd.abort.cid = nvme_cid(req);
c30341dc 1419 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
c30341dc 1420
1b3c47c1 1421 dev_warn(nvmeq->dev->ctrl.device,
86141440
CH		 1422 "I/O %d (%s) QID %d timeout, aborting\n",
1423 req->tag,
1424 nvme_get_opcode_str(nvme_req(req)->cmd->common.opcode),
1425 nvmeq->qid);
e7a2a87d 1426
e559398f
CH		 1427 abort_req = blk_mq_alloc_request(dev->ctrl.admin_q, nvme_req_op(&cmd),
1428 BLK_MQ_REQ_NOWAIT);
e7a2a87d
CH		 1429 if (IS_ERR(abort_req)) {
1430 atomic_inc(&dev->ctrl.abort_limit);
1431 return BLK_EH_RESET_TIMER;
1432 }
e559398f 1433 nvme_init_request(abort_req, &cmd);
e7a2a87d 1434
e2e53086 1435 abort_req->end_io = abort_endio;
e7a2a87d 1436 abort_req->end_io_data = NULL;
128126a7 1437 abort_req->rq_flags |= RQF_QUIET;
e2e53086 1438 blk_execute_rq_nowait(abort_req, false);
c30341dc 1439
31c7c7d2
CH		 1440 /*
1441 * The aborted req will be completed on receiving the abort req.
1442 * We enable the timer again. If hit twice, it'll cause a device reset,
1443 * as the device then is in a faulty state.
1444 */
1445 return BLK_EH_RESET_TIMER;
c30341dc
KB		 1446}
1447
a4aea562
MB		 1448static void nvme_free_queue(struct nvme_queue *nvmeq)
1449{
8a1d09a6 1450 dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq),
9e866774 1451 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
63223078
CH		 1452 if (!nvmeq->sq_cmds)
1453 return;
0f238ff5 1454
63223078 1455 if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) {
88a041f4 1456 pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev),
8a1d09a6 1457 nvmeq->sq_cmds, SQ_SIZE(nvmeq));
63223078 1458 } else {
8a1d09a6 1459 dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq),
63223078 1460 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
0f238ff5 1461 }
9e866774
MW		 1462}
1463
a1a5ef99 1464static void nvme_free_queues(struct nvme_dev *dev, int lowest)
22404274
KB		 1465{
1466 int i;
1467
d858e5f0 1468 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
d858e5f0 1469 dev->ctrl.queue_count--;
147b27e4 1470 nvme_free_queue(&dev->queues[i]);
121c7ad4 1471 }
22404274
KB		 1472}
1473
4d115420
KB		 1474/**
1475 * nvme_suspend_queue - put queue into suspended state
40581d1a 1476 * @nvmeq: queue to suspend
4d115420
KB		 1477 */
1478static int nvme_suspend_queue(struct nvme_queue *nvmeq)
b60503ba 1479{
4e224106 1480 if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags))
2b25d981 1481 return 1;
a09115b2 1482
4e224106 1483 /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */
d1f06f4a 1484 mb();
a09115b2 1485
4e224106 1486 nvmeq->dev->online_queues--;
1c63dc66 1487 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
6ca1d902 1488 nvme_stop_admin_queue(&nvmeq->dev->ctrl);
7c349dde
KB		 1489 if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags))
1490 pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq);
4d115420
KB		 1491 return 0;
1492}
b60503ba 1493
8fae268b
KB		 1494static void nvme_suspend_io_queues(struct nvme_dev *dev)
1495{
1496 int i;
1497
1498 for (i = dev->ctrl.queue_count - 1; i > 0; i--)
1499 nvme_suspend_queue(&dev->queues[i]);
1500}
1501
a5cdb68c 1502static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
4d115420 1503{
147b27e4 1504 struct nvme_queue *nvmeq = &dev->queues[0];
4d115420 1505
a5cdb68c
KB		 1506 if (shutdown)
1507 nvme_shutdown_ctrl(&dev->ctrl);
1508 else
b5b05048 1509 nvme_disable_ctrl(&dev->ctrl);
07836e65 1510
bf392a5d 1511 nvme_poll_irqdisable(nvmeq);
b60503ba
MW		 1512}
1513
fa46c6fb
KB		 1514/*
1515 * Called only on a device that has been disabled and after all other threads
9210c075
DZ		 1516 * that can check this device's completion queues have synced, except
1517 * nvme_poll(). This is the last chance for the driver to see a natural
1518 * completion before nvme_cancel_request() terminates all incomplete requests.
fa46c6fb
KB		 1519 */
1520static void nvme_reap_pending_cqes(struct nvme_dev *dev)
1521{
fa46c6fb
KB		 1522 int i;
1523
9210c075
DZ		 1524 for (i = dev->ctrl.queue_count - 1; i > 0; i--) {
1525 spin_lock(&dev->queues[i].cq_poll_lock);
c234a653 1526 nvme_poll_cq(&dev->queues[i], NULL);
9210c075
DZ		 1527 spin_unlock(&dev->queues[i].cq_poll_lock);
1528 }
fa46c6fb
KB		 1529}
1530
8ffaadf7
JD		 1531static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1532 int entry_size)
1533{
1534 int q_depth = dev->q_depth;
5fd4ce1b 1535 unsigned q_size_aligned = roundup(q_depth * entry_size,
6c3c05b0 1536 NVME_CTRL_PAGE_SIZE);
8ffaadf7
JD		 1537
1538 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
c45f5c99 1539 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
4e523547 1540
6c3c05b0 1541 mem_per_q = round_down(mem_per_q, NVME_CTRL_PAGE_SIZE);
c45f5c99 1542 q_depth = div_u64(mem_per_q, entry_size);
8ffaadf7
JD		 1543
1544 /*
1545 * Ensure the reduced q_depth is above some threshold where it
1546 * would be better to map queues in system memory with the
1547 * original depth
1548 */
1549 if (q_depth < 64)
1550 return -ENOMEM;
1551 }
1552
1553 return q_depth;
1554}
1555
1556static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
8a1d09a6 1557 int qid)
8ffaadf7 1558{
0f238ff5
LG		 1559 struct pci_dev *pdev = to_pci_dev(dev->dev);
1560
1561 if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
8a1d09a6 1562 nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq));
bfac8e9f
AM		 1563 if (nvmeq->sq_cmds) {
1564 nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev,
1565 nvmeq->sq_cmds);
1566 if (nvmeq->sq_dma_addr) {
1567 set_bit(NVMEQ_SQ_CMB, &nvmeq->flags);
1568 return 0;
1569 }
1570
8a1d09a6 1571 pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq));
63223078 1572 }
0f238ff5 1573 }
8ffaadf7 1574
8a1d09a6 1575 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq),
63223078 1576 &nvmeq->sq_dma_addr, GFP_KERNEL);
815c6704
KB		 1577 if (!nvmeq->sq_cmds)
1578 return -ENOMEM;
8ffaadf7
JD		 1579 return 0;
1580}
1581
a6ff7262 1582static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
b60503ba 1583{
147b27e4 1584 struct nvme_queue *nvmeq = &dev->queues[qid];
b60503ba 1585
62314e40
KB		 1586 if (dev->ctrl.queue_count > qid)
1587 return 0;
b60503ba 1588
c1e0cc7e 1589 nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES;
8a1d09a6
BH		 1590 nvmeq->q_depth = depth;
1591 nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq),
750afb08 1592 &nvmeq->cq_dma_addr, GFP_KERNEL);
b60503ba
MW		 1593 if (!nvmeq->cqes)
1594 goto free_nvmeq;
b60503ba 1595
8a1d09a6 1596 if (nvme_alloc_sq_cmds(dev, nvmeq, qid))
b60503ba
MW		 1597 goto free_cqdma;
1598
091b6092 1599 nvmeq->dev = dev;
1ab0cd69 1600 spin_lock_init(&nvmeq->sq_lock);
3a7afd8e 1601 spin_lock_init(&nvmeq->cq_poll_lock);
b60503ba 1602 nvmeq->cq_head = 0;
82123460 1603 nvmeq->cq_phase = 1;
b80d5ccc 1604 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
c30341dc 1605 nvmeq->qid = qid;
d858e5f0 1606 dev->ctrl.queue_count++;
36a7e993 1607
147b27e4 1608 return 0;
b60503ba
MW		 1609
1610 free_cqdma:
8a1d09a6
BH		 1611 dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes,
1612 nvmeq->cq_dma_addr);
b60503ba 1613 free_nvmeq:
147b27e4 1614 return -ENOMEM;
b60503ba
MW		 1615}
1616
dca51e78 1617static int queue_request_irq(struct nvme_queue *nvmeq)
3001082c 1618{
0ff199cb
CH		 1619 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1620 int nr = nvmeq->dev->ctrl.instance;
1621
1622 if (use_threaded_interrupts) {
1623 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1624 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1625 } else {
1626 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1627 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1628 }
3001082c
MW		 1629}
1630
22404274 1631static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
b60503ba 1632{
22404274 1633 struct nvme_dev *dev = nvmeq->dev;
b60503ba 1634
22404274 1635 nvmeq->sq_tail = 0;
38210800 1636 nvmeq->last_sq_tail = 0;
22404274
KB		 1637 nvmeq->cq_head = 0;
1638 nvmeq->cq_phase = 1;
b80d5ccc 1639 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
8a1d09a6 1640 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq));
f9f38e33 1641 nvme_dbbuf_init(dev, nvmeq, qid);
42f61420 1642 dev->online_queues++;
3a7afd8e 1643 wmb(); /* ensure the first interrupt sees the initialization */
22404274
KB		 1644}
1645
e4b9852a
CC		 1646/*
1647 * Try getting shutdown_lock while setting up IO queues.
1648 */
1649static int nvme_setup_io_queues_trylock(struct nvme_dev *dev)
1650{
1651 /*
1652 * Give up if the lock is being held by nvme_dev_disable.
1653 */
1654 if (!mutex_trylock(&dev->shutdown_lock))
1655 return -ENODEV;
1656
1657 /*
1658 * Controller is in wrong state, fail early.
1659 */
1660 if (dev->ctrl.state != NVME_CTRL_CONNECTING) {
1661 mutex_unlock(&dev->shutdown_lock);
1662 return -ENODEV;
1663 }
1664
1665 return 0;
1666}
1667
4b04cc6a 1668static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled)
22404274
KB		 1669{
1670 struct nvme_dev *dev = nvmeq->dev;
1671 int result;
7c349dde 1672 u16 vector = 0;
3f85d50b 1673
d1ed6aa1
CH		 1674 clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
1675
22b55601
KB		 1676 /*
1677 * A queue's vector matches the queue identifier unless the controller
1678 * has only one vector available.
1679 */
4b04cc6a
JA		 1680 if (!polled)
1681 vector = dev->num_vecs == 1 ? 0 : qid;
1682 else
7c349dde 1683 set_bit(NVMEQ_POLLED, &nvmeq->flags);
4b04cc6a 1684
a8e3e0bb 1685 result = adapter_alloc_cq(dev, qid, nvmeq, vector);
ded45505
KB		 1686 if (result)
1687 return result;
b60503ba
MW		 1688
1689 result = adapter_alloc_sq(dev, qid, nvmeq);
1690 if (result < 0)
ded45505 1691 return result;
c80b36cd 1692 if (result)
b60503ba
MW		 1693 goto release_cq;
1694
a8e3e0bb 1695 nvmeq->cq_vector = vector;
4b04cc6a 1696
e4b9852a
CC		 1697 result = nvme_setup_io_queues_trylock(dev);
1698 if (result)
1699 return result;
1700 nvme_init_queue(nvmeq, qid);
7c349dde 1701 if (!polled) {
4b04cc6a
JA		 1702 result = queue_request_irq(nvmeq);
1703 if (result < 0)
1704 goto release_sq;
1705 }
b60503ba 1706
4e224106 1707 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
e4b9852a 1708 mutex_unlock(&dev->shutdown_lock);
22404274 1709 return result;
b60503ba 1710
a8e3e0bb 1711release_sq:
f25a2dfc 1712 dev->online_queues--;
e4b9852a 1713 mutex_unlock(&dev->shutdown_lock);
b60503ba 1714 adapter_delete_sq(dev, qid);
a8e3e0bb 1715release_cq:
b60503ba 1716 adapter_delete_cq(dev, qid);
22404274 1717 return result;
b60503ba
MW		 1718}
1719
f363b089 1720static const struct blk_mq_ops nvme_mq_admin_ops = {
d29ec824 1721 .queue_rq = nvme_queue_rq,
77f02a7a 1722 .complete = nvme_pci_complete_rq,
a4aea562 1723 .init_hctx = nvme_admin_init_hctx,
e559398f 1724 .init_request = nvme_pci_init_request,
a4aea562
MB		 1725 .timeout = nvme_timeout,
1726};
1727
f363b089 1728static const struct blk_mq_ops nvme_mq_ops = {
376f7ef8 1729 .queue_rq = nvme_queue_rq,
d62cbcf6 1730 .queue_rqs = nvme_queue_rqs,
376f7ef8
CH		 1731 .complete = nvme_pci_complete_rq,
1732 .commit_rqs = nvme_commit_rqs,
1733 .init_hctx = nvme_init_hctx,
e559398f 1734 .init_request = nvme_pci_init_request,
376f7ef8
CH		 1735 .map_queues = nvme_pci_map_queues,
1736 .timeout = nvme_timeout,
1737 .poll = nvme_poll,
dabcefab
JA		 1738};
1739
ea191d2f
KB		 1740static void nvme_dev_remove_admin(struct nvme_dev *dev)
1741{
1c63dc66 1742 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
69d9a99c
KB		 1743 /*
1744 * If the controller was reset during removal, it's possible
1745 * user requests may be waiting on a stopped queue. Start the
1746 * queue to flush these to completion.
1747 */
6ca1d902 1748 nvme_start_admin_queue(&dev->ctrl);
6f8191fd 1749 blk_mq_destroy_queue(dev->ctrl.admin_q);
96ef1be5 1750 blk_put_queue(dev->ctrl.admin_q);
ea191d2f
KB		 1751 blk_mq_free_tag_set(&dev->admin_tagset);
1752 }
1753}
1754
f91b727c 1755static int nvme_pci_alloc_admin_tag_set(struct nvme_dev *dev)
a4aea562 1756{
f91b727c 1757 struct blk_mq_tag_set *set = &dev->admin_tagset;
e3e9d50c 1758
f91b727c
CH		 1759 set->ops = &nvme_mq_admin_ops;
1760 set->nr_hw_queues = 1;
a4aea562 1761
f91b727c
CH		 1762 set->queue_depth = NVME_AQ_MQ_TAG_DEPTH;
1763 set->timeout = NVME_ADMIN_TIMEOUT;
1764 set->numa_node = dev->ctrl.numa_node;
1765 set->cmd_size = sizeof(struct nvme_iod);
1766 set->flags = BLK_MQ_F_NO_SCHED;
1767 set->driver_data = dev;
a4aea562 1768
f91b727c
CH		 1769 if (blk_mq_alloc_tag_set(set))
1770 return -ENOMEM;
1771 dev->ctrl.admin_tagset = set;
a4aea562 1772
f91b727c
CH		 1773 dev->ctrl.admin_q = blk_mq_init_queue(set);
1774 if (IS_ERR(dev->ctrl.admin_q)) {
1775 blk_mq_free_tag_set(set);
1776 dev->ctrl.admin_q = NULL;
1777 return -ENOMEM;
1778 }
a4aea562
MB		 1779 return 0;
1780}
1781
97f6ef64
XY		 1782static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1783{
1784 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1785}
1786
1787static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1788{
1789 struct pci_dev *pdev = to_pci_dev(dev->dev);
1790
1791 if (size <= dev->bar_mapped_size)
1792 return 0;
1793 if (size > pci_resource_len(pdev, 0))
1794 return -ENOMEM;
1795 if (dev->bar)
1796 iounmap(dev->bar);
1797 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1798 if (!dev->bar) {
1799 dev->bar_mapped_size = 0;
1800 return -ENOMEM;
1801 }
1802 dev->bar_mapped_size = size;
1803 dev->dbs = dev->bar + NVME_REG_DBS;
1804
1805 return 0;
1806}
1807
01ad0990 1808static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
b60503ba 1809{
ba47e386 1810 int result;
b60503ba
MW		 1811 u32 aqa;
1812 struct nvme_queue *nvmeq;
1813
97f6ef64
XY		 1814 result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1815 if (result < 0)
1816 return result;
1817
8ef2074d 1818 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
20d0dfe6 1819 NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
dfbac8c7 1820
7a67cbea
CH		 1821 if (dev->subsystem &&
1822 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1823 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
dfbac8c7 1824
b5b05048 1825 result = nvme_disable_ctrl(&dev->ctrl);
ba47e386
MW		 1826 if (result < 0)
1827 return result;
b60503ba 1828
a6ff7262 1829 result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
147b27e4
SG		 1830 if (result)
1831 return result;
b60503ba 1832
635333e4
MG		 1833 dev->ctrl.numa_node = dev_to_node(dev->dev);
1834
147b27e4 1835 nvmeq = &dev->queues[0];
b60503ba
MW		 1836 aqa = nvmeq->q_depth - 1;
1837 aqa |= aqa << 16;
1838
7a67cbea
CH		 1839 writel(aqa, dev->bar + NVME_REG_AQA);
1840 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1841 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
b60503ba 1842
c0f2f45b 1843 result = nvme_enable_ctrl(&dev->ctrl);
025c557a 1844 if (result)
d4875622 1845 return result;
a4aea562 1846
2b25d981 1847 nvmeq->cq_vector = 0;
161b8be2 1848 nvme_init_queue(nvmeq, 0);
dca51e78 1849 result = queue_request_irq(nvmeq);
758dd7fd 1850 if (result) {
7c349dde 1851 dev->online_queues--;
d4875622 1852 return result;
758dd7fd 1853 }
025c557a 1854
4e224106 1855 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
b60503ba
MW		 1856 return result;
1857}
1858
749941f2 1859static int nvme_create_io_queues(struct nvme_dev *dev)
42f61420 1860{
4b04cc6a 1861 unsigned i, max, rw_queues;
749941f2 1862 int ret = 0;
42f61420 1863
d858e5f0 1864 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
a6ff7262 1865 if (nvme_alloc_queue(dev, i, dev->q_depth)) {
749941f2 1866 ret = -ENOMEM;
42f61420 1867 break;
749941f2
CH		 1868 }
1869 }
42f61420 1870
d858e5f0 1871 max = min(dev->max_qid, dev->ctrl.queue_count - 1);
e20ba6e1
CH		 1872 if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) {
1873 rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] +
1874 dev->io_queues[HCTX_TYPE_READ];
4b04cc6a
JA		 1875 } else {
1876 rw_queues = max;
1877 }
1878
949928c1 1879 for (i = dev->online_queues; i <= max; i++) {
4b04cc6a
JA		 1880 bool polled = i > rw_queues;
1881
1882 ret = nvme_create_queue(&dev->queues[i], i, polled);
d4875622 1883 if (ret)
42f61420 1884 break;
27e8166c 1885 }
749941f2
CH		 1886
1887 /*
1888 * Ignore failing Create SQ/CQ commands, we can continue with less
8adb8c14
MI		 1889 * than the desired amount of queues, and even a controller without
1890 * I/O queues can still be used to issue admin commands. This might
749941f2
CH		 1891 * be useful to upgrade a buggy firmware for example.
1892 */
1893 return ret >= 0 ? 0 : ret;
b60503ba
MW		 1894}
1895
88de4598 1896static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
8ffaadf7 1897{
88de4598
CH		 1898 u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
1899
1900 return 1ULL << (12 + 4 * szu);
1901}
1902
1903static u32 nvme_cmb_size(struct nvme_dev *dev)
1904{
1905 return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
1906}
1907
f65efd6d 1908static void nvme_map_cmb(struct nvme_dev *dev)
8ffaadf7 1909{
88de4598 1910 u64 size, offset;
8ffaadf7
JD		 1911 resource_size_t bar_size;
1912 struct pci_dev *pdev = to_pci_dev(dev->dev);
8969f1f8 1913 int bar;
8ffaadf7 1914
9fe5c59f
KB		 1915 if (dev->cmb_size)
1916 return;
1917
20d3bb92
KJ		 1918 if (NVME_CAP_CMBS(dev->ctrl.cap))
1919 writel(NVME_CMBMSC_CRE, dev->bar + NVME_REG_CMBMSC);
1920
7a67cbea 1921 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
f65efd6d
CH		 1922 if (!dev->cmbsz)
1923 return;
202021c1 1924 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
8ffaadf7 1925
88de4598
CH		 1926 size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
1927 offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
8969f1f8
CH		 1928 bar = NVME_CMB_BIR(dev->cmbloc);
1929 bar_size = pci_resource_len(pdev, bar);
8ffaadf7
JD		 1930
1931 if (offset > bar_size)
f65efd6d 1932 return;
8ffaadf7 1933
20d3bb92
KJ		 1934 /*
1935 * Tell the controller about the host side address mapping the CMB,
1936 * and enable CMB decoding for the NVMe 1.4+ scheme:
1937 */
1938 if (NVME_CAP_CMBS(dev->ctrl.cap)) {
1939 hi_lo_writeq(NVME_CMBMSC_CRE | NVME_CMBMSC_CMSE |
1940 (pci_bus_address(pdev, bar) + offset),
1941 dev->bar + NVME_REG_CMBMSC);
1942 }
1943
8ffaadf7
JD		 1944 /*
1945 * Controllers may support a CMB size larger than their BAR,
1946 * for example, due to being behind a bridge. Reduce the CMB to
1947 * the reported size of the BAR
1948 */
1949 if (size > bar_size - offset)
1950 size = bar_size - offset;
1951
0f238ff5
LG		 1952 if (pci_p2pdma_add_resource(pdev, bar, size, offset)) {
1953 dev_warn(dev->ctrl.device,
1954 "failed to register the CMB\n");
f65efd6d 1955 return;
0f238ff5
LG		 1956 }
1957
8ffaadf7 1958 dev->cmb_size = size;
0f238ff5
LG		 1959 dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS);
1960
1961 if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) ==
1962 (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS))
1963 pci_p2pmem_publish(pdev, true);
8ffaadf7
JD		 1964}
1965
87ad72a5
CH		 1966static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1967{
6c3c05b0 1968 u32 host_mem_size = dev->host_mem_size >> NVME_CTRL_PAGE_SHIFT;
4033f35d 1969 u64 dma_addr = dev->host_mem_descs_dma;
f66e2804 1970 struct nvme_command c = { };
87ad72a5
CH		 1971 int ret;
1972
87ad72a5
CH		 1973 c.features.opcode = nvme_admin_set_features;
1974 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1975 c.features.dword11 = cpu_to_le32(bits);
6c3c05b0 1976 c.features.dword12 = cpu_to_le32(host_mem_size);
87ad72a5
CH		 1977 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr));
1978 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr));
1979 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs);
1980
1981 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1982 if (ret) {
1983 dev_warn(dev->ctrl.device,
1984 "failed to set host mem (err %d, flags %#x).\n",
1985 ret, bits);
a5df5e79
KB		 1986 } else
1987 dev->hmb = bits & NVME_HOST_MEM_ENABLE;
1988
87ad72a5
CH		 1989 return ret;
1990}
1991
1992static void nvme_free_host_mem(struct nvme_dev *dev)
1993{
1994 int i;
1995
1996 for (i = 0; i < dev->nr_host_mem_descs; i++) {
1997 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
6c3c05b0 1998 size_t size = le32_to_cpu(desc->size) * NVME_CTRL_PAGE_SIZE;
87ad72a5 1999
cc667f6d
LD		 2000 dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i],
2001 le64_to_cpu(desc->addr),
2002 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
87ad72a5
CH		 2003 }
2004
2005 kfree(dev->host_mem_desc_bufs);
2006 dev->host_mem_desc_bufs = NULL;
4033f35d
CH		 2007 dma_free_coherent(dev->dev,
2008 dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
2009 dev->host_mem_descs, dev->host_mem_descs_dma);
87ad72a5 2010 dev->host_mem_descs = NULL;
7e5dd57e 2011 dev->nr_host_mem_descs = 0;
87ad72a5
CH		 2012}
2013
92dc6895
CH		 2014static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
2015 u32 chunk_size)
9d713c2b 2016{
87ad72a5 2017 struct nvme_host_mem_buf_desc *descs;
92dc6895 2018 u32 max_entries, len;
4033f35d 2019 dma_addr_t descs_dma;
2ee0e4ed 2020 int i = 0;
87ad72a5 2021 void **bufs;
6fbcde66 2022 u64 size, tmp;
87ad72a5 2023
87ad72a5
CH		 2024 tmp = (preferred + chunk_size - 1);
2025 do_div(tmp, chunk_size);
2026 max_entries = tmp;
044a9df1
CH		 2027
2028 if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
2029 max_entries = dev->ctrl.hmmaxd;
2030
750afb08
LC		 2031 descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs),
2032 &descs_dma, GFP_KERNEL);
87ad72a5
CH		 2033 if (!descs)
2034 goto out;
2035
2036 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
2037 if (!bufs)
2038 goto out_free_descs;
2039
244a8fe4 2040 for (size = 0; size < preferred && i < max_entries; size += len) {
87ad72a5
CH		 2041 dma_addr_t dma_addr;
2042
50cdb7c6 2043 len = min_t(u64, chunk_size, preferred - size);
87ad72a5
CH		 2044 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
2045 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
2046 if (!bufs[i])
2047 break;
2048
2049 descs[i].addr = cpu_to_le64(dma_addr);
6c3c05b0 2050 descs[i].size = cpu_to_le32(len / NVME_CTRL_PAGE_SIZE);
87ad72a5
CH		 2051 i++;
2052 }
2053
92dc6895 2054 if (!size)
87ad72a5 2055 goto out_free_bufs;
87ad72a5 2056
87ad72a5
CH		 2057 dev->nr_host_mem_descs = i;
2058 dev->host_mem_size = size;
2059 dev->host_mem_descs = descs;
4033f35d 2060 dev->host_mem_descs_dma = descs_dma;
87ad72a5
CH		 2061 dev->host_mem_desc_bufs = bufs;
2062 return 0;
2063
2064out_free_bufs:
2065 while (--i >= 0) {
6c3c05b0 2066 size_t size = le32_to_cpu(descs[i].size) * NVME_CTRL_PAGE_SIZE;
87ad72a5 2067
cc667f6d
LD		 2068 dma_free_attrs(dev->dev, size, bufs[i],
2069 le64_to_cpu(descs[i].addr),
2070 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
87ad72a5
CH		 2071 }
2072
2073 kfree(bufs);
2074out_free_descs:
4033f35d
CH		 2075 dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
2076 descs_dma);
87ad72a5 2077out:
87ad72a5
CH		 2078 dev->host_mem_descs = NULL;
2079 return -ENOMEM;
2080}
2081
92dc6895
CH		 2082static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
2083{
9dc54a0d
CK		 2084 u64 min_chunk = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
2085 u64 hmminds = max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
2086 u64 chunk_size;
92dc6895
CH		 2087
2088 /* start big and work our way down */
9dc54a0d 2089 for (chunk_size = min_chunk; chunk_size >= hmminds; chunk_size /= 2) {
92dc6895
CH		 2090 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
2091 if (!min || dev->host_mem_size >= min)
2092 return 0;
2093 nvme_free_host_mem(dev);
2094 }
2095 }
2096
2097 return -ENOMEM;
2098}
2099
9620cfba 2100static int nvme_setup_host_mem(struct nvme_dev *dev)
87ad72a5
CH		 2101{
2102 u64 max = (u64)max_host_mem_size_mb * SZ_1M;
2103 u64 preferred = (u64)dev->ctrl.hmpre * 4096;
2104 u64 min = (u64)dev->ctrl.hmmin * 4096;
2105 u32 enable_bits = NVME_HOST_MEM_ENABLE;
6fbcde66 2106 int ret;
87ad72a5
CH		 2107
2108 preferred = min(preferred, max);
2109 if (min > max) {
2110 dev_warn(dev->ctrl.device,
2111 "min host memory (%lld MiB) above limit (%d MiB).\n",
2112 min >> ilog2(SZ_1M), max_host_mem_size_mb);
2113 nvme_free_host_mem(dev);
9620cfba 2114 return 0;
87ad72a5
CH		 2115 }
2116
2117 /*
2118 * If we already have a buffer allocated check if we can reuse it.
2119 */
2120 if (dev->host_mem_descs) {
2121 if (dev->host_mem_size >= min)
2122 enable_bits |= NVME_HOST_MEM_RETURN;
2123 else
2124 nvme_free_host_mem(dev);
2125 }
2126
2127 if (!dev->host_mem_descs) {
92dc6895
CH		 2128 if (nvme_alloc_host_mem(dev, min, preferred)) {
2129 dev_warn(dev->ctrl.device,
2130 "failed to allocate host memory buffer.\n");
9620cfba 2131 return 0; /* controller must work without HMB */
92dc6895
CH		 2132 }
2133
2134 dev_info(dev->ctrl.device,
2135 "allocated %lld MiB host memory buffer.\n",
2136 dev->host_mem_size >> ilog2(SZ_1M));
87ad72a5
CH		 2137 }
2138
9620cfba
CH		 2139 ret = nvme_set_host_mem(dev, enable_bits);
2140 if (ret)
87ad72a5 2141 nvme_free_host_mem(dev);
9620cfba 2142 return ret;
9d713c2b
KB		 2143}
2144
0521905e
KB		 2145static ssize_t cmb_show(struct device *dev, struct device_attribute *attr,
2146 char *buf)
2147{
2148 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2149
2150 return sysfs_emit(buf, "cmbloc : x%08x\ncmbsz : x%08x\n",
2151 ndev->cmbloc, ndev->cmbsz);
2152}
2153static DEVICE_ATTR_RO(cmb);
2154
1751e97a
KB		 2155static ssize_t cmbloc_show(struct device *dev, struct device_attribute *attr,
2156 char *buf)
2157{
2158 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2159
2160 return sysfs_emit(buf, "%u\n", ndev->cmbloc);
2161}
2162static DEVICE_ATTR_RO(cmbloc);
2163
2164static ssize_t cmbsz_show(struct device *dev, struct device_attribute *attr,
2165 char *buf)
2166{
2167 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2168
2169 return sysfs_emit(buf, "%u\n", ndev->cmbsz);
2170}
2171static DEVICE_ATTR_RO(cmbsz);
2172
a5df5e79
KB		 2173static ssize_t hmb_show(struct device *dev, struct device_attribute *attr,
2174 char *buf)
2175{
2176 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2177
2178 return sysfs_emit(buf, "%d\n", ndev->hmb);
2179}
2180
2181static ssize_t hmb_store(struct device *dev, struct device_attribute *attr,
2182 const char *buf, size_t count)
2183{
2184 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2185 bool new;
2186 int ret;
2187
2188 if (strtobool(buf, &new) < 0)
2189 return -EINVAL;
2190
2191 if (new == ndev->hmb)
2192 return count;
2193
2194 if (new) {
2195 ret = nvme_setup_host_mem(ndev);
2196 } else {
2197 ret = nvme_set_host_mem(ndev, 0);
2198 if (!ret)
2199 nvme_free_host_mem(ndev);
2200 }
2201
2202 if (ret < 0)
2203 return ret;
2204
2205 return count;
2206}
2207static DEVICE_ATTR_RW(hmb);
2208
0521905e
KB		 2209static umode_t nvme_pci_attrs_are_visible(struct kobject *kobj,
2210 struct attribute *a, int n)
2211{
2212 struct nvme_ctrl *ctrl =
2213 dev_get_drvdata(container_of(kobj, struct device, kobj));
2214 struct nvme_dev *dev = to_nvme_dev(ctrl);
2215
1751e97a
KB		 2216 if (a == &dev_attr_cmb.attr ||
2217 a == &dev_attr_cmbloc.attr ||
2218 a == &dev_attr_cmbsz.attr) {
2219 if (!dev->cmbsz)
2220 return 0;
2221 }
a5df5e79
KB		 2222 if (a == &dev_attr_hmb.attr && !ctrl->hmpre)
2223 return 0;
2224
0521905e
KB		 2225 return a->mode;
2226}
2227
2228static struct attribute *nvme_pci_attrs[] = {
2229 &dev_attr_cmb.attr,
1751e97a
KB		 2230 &dev_attr_cmbloc.attr,
2231 &dev_attr_cmbsz.attr,
a5df5e79 2232 &dev_attr_hmb.attr,
0521905e
KB		 2233 NULL,
2234};
2235
86adbf0c 2236static const struct attribute_group nvme_pci_dev_attrs_group = {
0521905e
KB		 2237 .attrs = nvme_pci_attrs,
2238 .is_visible = nvme_pci_attrs_are_visible,
2239};
2240
86adbf0c
CH		 2241static const struct attribute_group *nvme_pci_dev_attr_groups[] = {
2242 &nvme_dev_attrs_group,
2243 &nvme_pci_dev_attrs_group,
2244 NULL,
2245};
2246
612b7286
ML		 2247/*
2248 * nirqs is the number of interrupts available for write and read
2249 * queues. The core already reserved an interrupt for the admin queue.
2250 */
2251static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs)
3b6592f7 2252{
612b7286 2253 struct nvme_dev *dev = affd->priv;
2a5bcfdd 2254 unsigned int nr_read_queues, nr_write_queues = dev->nr_write_queues;
3b6592f7
JA		 2255
2256 /*
ee0d96d3 2257 * If there is no interrupt available for queues, ensure that
612b7286
ML		 2258 * the default queue is set to 1. The affinity set size is
2259 * also set to one, but the irq core ignores it for this case.
2260 *
2261 * If only one interrupt is available or 'write_queue' == 0, combine
2262 * write and read queues.
2263 *
2264 * If 'write_queues' > 0, ensure it leaves room for at least one read
2265 * queue.
3b6592f7 2266 */
612b7286
ML		 2267 if (!nrirqs) {
2268 nrirqs = 1;
2269 nr_read_queues = 0;
2a5bcfdd 2270 } else if (nrirqs == 1 || !nr_write_queues) {
612b7286 2271 nr_read_queues = 0;
2a5bcfdd 2272 } else if (nr_write_queues >= nrirqs) {
612b7286 2273 nr_read_queues = 1;
3b6592f7 2274 } else {
2a5bcfdd 2275 nr_read_queues = nrirqs - nr_write_queues;
3b6592f7 2276 }
612b7286
ML		 2277
2278 dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2279 affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2280 dev->io_queues[HCTX_TYPE_READ] = nr_read_queues;
2281 affd->set_size[HCTX_TYPE_READ] = nr_read_queues;
2282 affd->nr_sets = nr_read_queues ? 2 : 1;
3b6592f7
JA		 2283}
2284
6451fe73 2285static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues)
3b6592f7
JA		 2286{
2287 struct pci_dev *pdev = to_pci_dev(dev->dev);
3b6592f7 2288 struct irq_affinity affd = {
9cfef55b 2289 .pre_vectors = 1,
612b7286
ML		 2290 .calc_sets = nvme_calc_irq_sets,
2291 .priv = dev,
3b6592f7 2292 };
21cc2f3f 2293 unsigned int irq_queues, poll_queues;
6451fe73
JA		 2294
2295 /*
21cc2f3f
JX		 2296 * Poll queues don't need interrupts, but we need at least one I/O queue
2297 * left over for non-polled I/O.
6451fe73 2298 */
21cc2f3f
JX		 2299 poll_queues = min(dev->nr_poll_queues, nr_io_queues - 1);
2300 dev->io_queues[HCTX_TYPE_POLL] = poll_queues;
3b6592f7 2301
21cc2f3f
JX		 2302 /*
2303 * Initialize for the single interrupt case, will be updated in
2304 * nvme_calc_irq_sets().
2305 */
612b7286
ML		 2306 dev->io_queues[HCTX_TYPE_DEFAULT] = 1;
2307 dev->io_queues[HCTX_TYPE_READ] = 0;
3b6592f7 2308
66341331 2309 /*
21cc2f3f
JX		 2310 * We need interrupts for the admin queue and each non-polled I/O queue,
2311 * but some Apple controllers require all queues to use the first
2312 * vector.
66341331 2313 */
21cc2f3f
JX		 2314 irq_queues = 1;
2315 if (!(dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR))
2316 irq_queues += (nr_io_queues - poll_queues);
612b7286
ML		 2317 return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues,
2318 PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd);
3b6592f7
JA		 2319}
2320
8fae268b
KB		 2321static void nvme_disable_io_queues(struct nvme_dev *dev)
2322{
2323 if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq))
2324 __nvme_disable_io_queues(dev, nvme_admin_delete_cq);
2325}
2326
2a5bcfdd
WZ		 2327static unsigned int nvme_max_io_queues(struct nvme_dev *dev)
2328{
e3aef095
NS		 2329 /*
2330 * If tags are shared with admin queue (Apple bug), then
2331 * make sure we only use one IO queue.
2332 */
2333 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2334 return 1;
2a5bcfdd
WZ		 2335 return num_possible_cpus() + dev->nr_write_queues + dev->nr_poll_queues;
2336}
2337
8d85fce7 2338static int nvme_setup_io_queues(struct nvme_dev *dev)
b60503ba 2339{
147b27e4 2340 struct nvme_queue *adminq = &dev->queues[0];
e75ec752 2341 struct pci_dev *pdev = to_pci_dev(dev->dev);
2a5bcfdd 2342 unsigned int nr_io_queues;
97f6ef64 2343 unsigned long size;
2a5bcfdd 2344 int result;
b60503ba 2345
2a5bcfdd
WZ		 2346 /*
2347 * Sample the module parameters once at reset time so that we have
2348 * stable values to work with.
2349 */
2350 dev->nr_write_queues = write_queues;
2351 dev->nr_poll_queues = poll_queues;
d38e9f04 2352
e3aef095 2353 nr_io_queues = dev->nr_allocated_queues - 1;
9a0be7ab
CH		 2354 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
2355 if (result < 0)
1b23484b 2356 return result;
9a0be7ab 2357
f5fa90dc 2358 if (nr_io_queues == 0)
a5229050 2359 return 0;
53dc180e 2360
e4b9852a
CC		 2361 /*
2362 * Free IRQ resources as soon as NVMEQ_ENABLED bit transitions
2363 * from set to unset. If there is a window to it is truely freed,
2364 * pci_free_irq_vectors() jumping into this window will crash.
2365 * And take lock to avoid racing with pci_free_irq_vectors() in
2366 * nvme_dev_disable() path.
2367 */
2368 result = nvme_setup_io_queues_trylock(dev);
2369 if (result)
2370 return result;
2371 if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags))
2372 pci_free_irq(pdev, 0, adminq);
b60503ba 2373
0f238ff5 2374 if (dev->cmb_use_sqes) {
8ffaadf7
JD		 2375 result = nvme_cmb_qdepth(dev, nr_io_queues,
2376 sizeof(struct nvme_command));
2377 if (result > 0)
2378 dev->q_depth = result;
2379 else
0f238ff5 2380 dev->cmb_use_sqes = false;
8ffaadf7
JD		 2381 }
2382
97f6ef64
XY		 2383 do {
2384 size = db_bar_size(dev, nr_io_queues);
2385 result = nvme_remap_bar(dev, size);
2386 if (!result)
2387 break;
e4b9852a
CC		 2388 if (!--nr_io_queues) {
2389 result = -ENOMEM;
2390 goto out_unlock;
2391 }
97f6ef64
XY		 2392 } while (1);
2393 adminq->q_db = dev->dbs;
f1938f6e 2394
8fae268b 2395 retry:
9d713c2b 2396 /* Deregister the admin queue's interrupt */
e4b9852a
CC		 2397 if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags))
2398 pci_free_irq(pdev, 0, adminq);
9d713c2b 2399
e32efbfc
JA		 2400 /*
2401 * If we enable msix early due to not intx, disable it again before
2402 * setting up the full range we need.
2403 */
dca51e78 2404 pci_free_irq_vectors(pdev);
3b6592f7
JA		 2405
2406 result = nvme_setup_irqs(dev, nr_io_queues);
e4b9852a
CC		 2407 if (result <= 0) {
2408 result = -EIO;
2409 goto out_unlock;
2410 }
3b6592f7 2411
22b55601 2412 dev->num_vecs = result;
4b04cc6a 2413 result = max(result - 1, 1);
e20ba6e1 2414 dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL];
fa08a396 2415
063a8096
MW		 2416 /*
2417 * Should investigate if there's a performance win from allocating
2418 * more queues than interrupt vectors; it might allow the submission
2419 * path to scale better, even if the receive path is limited by the
2420 * number of interrupts.
2421 */
dca51e78 2422 result = queue_request_irq(adminq);
7c349dde 2423 if (result)
e4b9852a 2424 goto out_unlock;
4e224106 2425 set_bit(NVMEQ_ENABLED, &adminq->flags);
e4b9852a 2426 mutex_unlock(&dev->shutdown_lock);
8fae268b
KB		 2427
2428 result = nvme_create_io_queues(dev);
2429 if (result || dev->online_queues < 2)
2430 return result;
2431
2432 if (dev->online_queues - 1 < dev->max_qid) {
2433 nr_io_queues = dev->online_queues - 1;
2434 nvme_disable_io_queues(dev);
e4b9852a
CC		 2435 result = nvme_setup_io_queues_trylock(dev);
2436 if (result)
2437 return result;
8fae268b
KB		 2438 nvme_suspend_io_queues(dev);
2439 goto retry;
2440 }
2441 dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n",
2442 dev->io_queues[HCTX_TYPE_DEFAULT],
2443 dev->io_queues[HCTX_TYPE_READ],
2444 dev->io_queues[HCTX_TYPE_POLL]);
2445 return 0;
e4b9852a
CC		 2446out_unlock:
2447 mutex_unlock(&dev->shutdown_lock);
2448 return result;
b60503ba
MW		 2449}
2450
de671d61
JA		 2451static enum rq_end_io_ret nvme_del_queue_end(struct request *req,
2452 blk_status_t error)
a5768aa8 2453{
db3cbfff 2454 struct nvme_queue *nvmeq = req->end_io_data;
b5875222 2455
db3cbfff 2456 blk_mq_free_request(req);
d1ed6aa1 2457 complete(&nvmeq->delete_done);
de671d61 2458 return RQ_END_IO_NONE;
a5768aa8
KB		 2459}
2460
de671d61
JA		 2461static enum rq_end_io_ret nvme_del_cq_end(struct request *req,
2462 blk_status_t error)
a5768aa8 2463{
db3cbfff 2464 struct nvme_queue *nvmeq = req->end_io_data;
a5768aa8 2465
d1ed6aa1
CH		 2466 if (error)
2467 set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
db3cbfff 2468
de671d61 2469 return nvme_del_queue_end(req, error);
a5768aa8
KB		 2470}
2471
db3cbfff 2472static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
bda4e0fb 2473{
db3cbfff
KB		 2474 struct request_queue *q = nvmeq->dev->ctrl.admin_q;
2475 struct request *req;
f66e2804 2476 struct nvme_command cmd = { };
bda4e0fb 2477
db3cbfff
KB		 2478 cmd.delete_queue.opcode = opcode;
2479 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
bda4e0fb 2480
e559398f 2481 req = blk_mq_alloc_request(q, nvme_req_op(&cmd), BLK_MQ_REQ_NOWAIT);
db3cbfff
KB		 2482 if (IS_ERR(req))
2483 return PTR_ERR(req);
e559398f 2484 nvme_init_request(req, &cmd);
bda4e0fb 2485
e2e53086
CH		 2486 if (opcode == nvme_admin_delete_cq)
2487 req->end_io = nvme_del_cq_end;
2488 else
2489 req->end_io = nvme_del_queue_end;
db3cbfff
KB		 2490 req->end_io_data = nvmeq;
2491
d1ed6aa1 2492 init_completion(&nvmeq->delete_done);
128126a7 2493 req->rq_flags |= RQF_QUIET;
e2e53086 2494 blk_execute_rq_nowait(req, false);
db3cbfff 2495 return 0;
bda4e0fb
KB		 2496}
2497
8fae268b 2498static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode)
a5768aa8 2499{
5271edd4 2500 int nr_queues = dev->online_queues - 1, sent = 0;
db3cbfff 2501 unsigned long timeout;
a5768aa8 2502
db3cbfff 2503 retry:
dc96f938 2504 timeout = NVME_ADMIN_TIMEOUT;
5271edd4
CH		 2505 while (nr_queues > 0) {
2506 if (nvme_delete_queue(&dev->queues[nr_queues], opcode))
2507 break;
2508 nr_queues--;
2509 sent++;
db3cbfff 2510 }
d1ed6aa1
CH		 2511 while (sent) {
2512 struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent];
2513
2514 timeout = wait_for_completion_io_timeout(&nvmeq->delete_done,
5271edd4
CH		 2515 timeout);
2516 if (timeout == 0)
2517 return false;
d1ed6aa1 2518
d1ed6aa1 2519 sent--;
5271edd4
CH		 2520 if (nr_queues)
2521 goto retry;
2522 }
2523 return true;
a5768aa8
KB		 2524}
2525
2455a4b7 2526static void nvme_pci_alloc_tag_set(struct nvme_dev *dev)
b60503ba 2527{
2455a4b7 2528 struct blk_mq_tag_set * set = &dev->tagset;
2b1b7e78
JW		 2529 int ret;
2530
2455a4b7
CH		 2531 set->ops = &nvme_mq_ops;
2532 set->nr_hw_queues = dev->online_queues - 1;
6ee742fa
KB		 2533 set->nr_maps = 1;
2534 if (dev->io_queues[HCTX_TYPE_READ])
2535 set->nr_maps = 2;
2455a4b7 2536 if (dev->io_queues[HCTX_TYPE_POLL])
6ee742fa 2537 set->nr_maps = 3;
2455a4b7
CH		 2538 set->timeout = NVME_IO_TIMEOUT;
2539 set->numa_node = dev->ctrl.numa_node;
2540 set->queue_depth = min_t(unsigned, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
2541 set->cmd_size = sizeof(struct nvme_iod);
2542 set->flags = BLK_MQ_F_SHOULD_MERGE;
2543 set->driver_data = dev;
d38e9f04 2544
2455a4b7
CH		 2545 /*
2546 * Some Apple controllers requires tags to be unique
2547 * across admin and IO queue, so reserve the first 32
2548 * tags of the IO queue.
2549 */
2550 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2551 set->reserved_tags = NVME_AQ_DEPTH;
949928c1 2552
2455a4b7
CH		 2553 ret = blk_mq_alloc_tag_set(set);
2554 if (ret) {
2555 dev_warn(dev->ctrl.device,
2556 "IO queues tagset allocation failed %d\n", ret);
2557 return;
ffe7704d 2558 }
2455a4b7
CH		 2559 dev->ctrl.tagset = set;
2560}
949928c1 2561
2455a4b7
CH		 2562static void nvme_pci_update_nr_queues(struct nvme_dev *dev)
2563{
2564 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2565 /* free previously allocated queues that are no longer usable */
2566 nvme_free_queues(dev, dev->online_queues);
b60503ba
MW		 2567}
2568
b00a726a 2569static int nvme_pci_enable(struct nvme_dev *dev)
0877cb0d 2570{
b00a726a 2571 int result = -ENOMEM;
e75ec752 2572 struct pci_dev *pdev = to_pci_dev(dev->dev);
4bdf2603 2573 int dma_address_bits = 64;
0877cb0d
KB		 2574
2575 if (pci_enable_device_mem(pdev))
2576 return result;
2577
0877cb0d 2578 pci_set_master(pdev);
0877cb0d 2579
4bdf2603
FS		 2580 if (dev->ctrl.quirks & NVME_QUIRK_DMA_ADDRESS_BITS_48)
2581 dma_address_bits = 48;
2582 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(dma_address_bits)))
052d0efa 2583 goto disable;
0877cb0d 2584
7a67cbea 2585 if (readl(dev->bar + NVME_REG_CSTS) == -1) {
0e53d180 2586 result = -ENODEV;
b00a726a 2587 goto disable;
0e53d180 2588 }
e32efbfc
JA		 2589
2590 /*
a5229050
KB		 2591 * Some devices and/or platforms don't advertise or work with INTx
2592 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2593 * adjust this later.
e32efbfc 2594 */
dca51e78
CH		 2595 result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
2596 if (result < 0)
2597 return result;
e32efbfc 2598
20d0dfe6 2599 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
7a67cbea 2600
7442ddce 2601 dev->q_depth = min_t(u32, NVME_CAP_MQES(dev->ctrl.cap) + 1,
b27c1e68 2602 io_queue_depth);
aa22c8e6 2603 dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */
20d0dfe6 2604 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
7a67cbea 2605 dev->dbs = dev->bar + 4096;
1f390c1f 2606
66341331
BH		 2607 /*
2608 * Some Apple controllers require a non-standard SQE size.
2609 * Interestingly they also seem to ignore the CC:IOSQES register
2610 * so we don't bother updating it here.
2611 */
2612 if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES)
2613 dev->io_sqes = 7;
2614 else
2615 dev->io_sqes = NVME_NVM_IOSQES;
1f390c1f
SG		 2616
2617 /*
2618 * Temporary fix for the Apple controller found in the MacBook8,1 and
2619 * some MacBook7,1 to avoid controller resets and data loss.
2620 */
2621 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
2622 dev->q_depth = 2;
9bdcfb10
CH		 2623 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
2624 "set queue depth=%u to work around controller resets\n",
1f390c1f 2625 dev->q_depth);
d554b5e1
MP		 2626 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2627 (pdev->device == 0xa821 || pdev->device == 0xa822) &&
20d0dfe6 2628 NVME_CAP_MQES(dev->ctrl.cap) == 0) {
d554b5e1
MP		 2629 dev->q_depth = 64;
2630 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2631 "set queue depth=%u\n", dev->q_depth);
1f390c1f
SG		 2632 }
2633
d38e9f04
BH		 2634 /*
2635 * Controllers with the shared tags quirk need the IO queue to be
2636 * big enough so that we get 32 tags for the admin queue
2637 */
2638 if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) &&
2639 (dev->q_depth < (NVME_AQ_DEPTH + 2))) {
2640 dev->q_depth = NVME_AQ_DEPTH + 2;
2641 dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n",
2642 dev->q_depth);
2643 }
2644
2645
f65efd6d 2646 nvme_map_cmb(dev);
202021c1 2647
a0a3408e
KB		 2648 pci_enable_pcie_error_reporting(pdev);
2649 pci_save_state(pdev);
0877cb0d
KB		 2650 return 0;
2651
2652 disable:
0877cb0d
KB		 2653 pci_disable_device(pdev);
2654 return result;
2655}
2656
2657static void nvme_dev_unmap(struct nvme_dev *dev)
b00a726a
KB		 2658{
2659 if (dev->bar)
2660 iounmap(dev->bar);
a1f447b3 2661 pci_release_mem_regions(to_pci_dev(dev->dev));
b00a726a
KB		 2662}
2663
2664static void nvme_pci_disable(struct nvme_dev *dev)
0877cb0d 2665{
e75ec752
CH		 2666 struct pci_dev *pdev = to_pci_dev(dev->dev);
2667
dca51e78 2668 pci_free_irq_vectors(pdev);
0877cb0d 2669
a0a3408e
KB		 2670 if (pci_is_enabled(pdev)) {
2671 pci_disable_pcie_error_reporting(pdev);
e75ec752 2672 pci_disable_device(pdev);
4d115420 2673 }
4d115420
KB		 2674}
2675
a5cdb68c 2676static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
b60503ba 2677{
e43269e6 2678 bool dead = true, freeze = false;
302ad8cc 2679 struct pci_dev *pdev = to_pci_dev(dev->dev);
22404274 2680
77bf25ea 2681 mutex_lock(&dev->shutdown_lock);
081f5e75
KB		 2682 if (pci_is_enabled(pdev)) {
2683 u32 csts;
2684
2685 if (pci_device_is_present(pdev))
2686 csts = readl(dev->bar + NVME_REG_CSTS);
2687 else
2688 csts = ~0;
302ad8cc 2689
ebef7368 2690 if (dev->ctrl.state == NVME_CTRL_LIVE ||
e43269e6
KB		 2691 dev->ctrl.state == NVME_CTRL_RESETTING) {
2692 freeze = true;
302ad8cc 2693 nvme_start_freeze(&dev->ctrl);
e43269e6 2694 }
302ad8cc
KB		 2695 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
2696 pdev->error_state != pci_channel_io_normal);
c9d3bf88 2697 }
c21377f8 2698
302ad8cc
KB		 2699 /*
2700 * Give the controller a chance to complete all entered requests if
2701 * doing a safe shutdown.
2702 */
e43269e6
KB		 2703 if (!dead && shutdown && freeze)
2704 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
9a915a5b
JW		 2705
2706 nvme_stop_queues(&dev->ctrl);
87ad72a5 2707
64ee0ac0 2708 if (!dead && dev->ctrl.queue_count > 0) {
8fae268b 2709 nvme_disable_io_queues(dev);
a5cdb68c 2710 nvme_disable_admin_queue(dev, shutdown);
4d115420 2711 }
8fae268b
KB		 2712 nvme_suspend_io_queues(dev);
2713 nvme_suspend_queue(&dev->queues[0]);
b00a726a 2714 nvme_pci_disable(dev);
fa46c6fb 2715 nvme_reap_pending_cqes(dev);
07836e65 2716
1fcfca78
GL		 2717 nvme_cancel_tagset(&dev->ctrl);
2718 nvme_cancel_admin_tagset(&dev->ctrl);
302ad8cc
KB		 2719
2720 /*
2721 * The driver will not be starting up queues again if shutting down so
2722 * must flush all entered requests to their failed completion to avoid
2723 * deadlocking blk-mq hot-cpu notifier.
2724 */
c8e9e9b7 2725 if (shutdown) {
302ad8cc 2726 nvme_start_queues(&dev->ctrl);
c8e9e9b7 2727 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q))
6ca1d902 2728 nvme_start_admin_queue(&dev->ctrl);
c8e9e9b7 2729 }
77bf25ea 2730 mutex_unlock(&dev->shutdown_lock);
b60503ba
MW		 2731}
2732
c1ac9a4b
KB		 2733static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown)
2734{
2735 if (!nvme_wait_reset(&dev->ctrl))
2736 return -EBUSY;
2737 nvme_dev_disable(dev, shutdown);
2738 return 0;
2739}
2740
091b6092
MW		 2741static int nvme_setup_prp_pools(struct nvme_dev *dev)
2742{
e75ec752 2743 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
c61b82c7
CH		 2744 NVME_CTRL_PAGE_SIZE,
2745 NVME_CTRL_PAGE_SIZE, 0);
091b6092
MW		 2746 if (!dev->prp_page_pool)
2747 return -ENOMEM;
2748
99802a7a 2749 /* Optimisation for I/Os between 4k and 128k */
e75ec752 2750 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
99802a7a
MW		 2751 256, 256, 0);
2752 if (!dev->prp_small_pool) {
2753 dma_pool_destroy(dev->prp_page_pool);
2754 return -ENOMEM;
2755 }
091b6092
MW		 2756 return 0;
2757}
2758
2759static void nvme_release_prp_pools(struct nvme_dev *dev)
2760{
2761 dma_pool_destroy(dev->prp_page_pool);
99802a7a 2762 dma_pool_destroy(dev->prp_small_pool);
091b6092
MW		 2763}
2764
770597ec
KB		 2765static void nvme_free_tagset(struct nvme_dev *dev)
2766{
2767 if (dev->tagset.tags)
2768 blk_mq_free_tag_set(&dev->tagset);
2769 dev->ctrl.tagset = NULL;
2770}
2771
1673f1f0 2772static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
5e82e952 2773{
1673f1f0 2774 struct nvme_dev *dev = to_nvme_dev(ctrl);
9ac27090 2775
f9f38e33 2776 nvme_dbbuf_dma_free(dev);
770597ec 2777 nvme_free_tagset(dev);
943e942e 2778 mempool_destroy(dev->iod_mempool);
253fd4ac
IR		 2779 put_device(dev->dev);
2780 kfree(dev->queues);
5e82e952
KB		 2781 kfree(dev);
2782}
2783
7c1ce408 2784static void nvme_remove_dead_ctrl(struct nvme_dev *dev)
f58944e2 2785{
c1ac9a4b
KB		 2786 /*
2787 * Set state to deleting now to avoid blocking nvme_wait_reset(), which
2788 * may be holding this pci_dev's device lock.
2789 */
2790 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
d22524a4 2791 nvme_get_ctrl(&dev->ctrl);
69d9a99c 2792 nvme_dev_disable(dev, false);
cd50f9b2 2793 nvme_mark_namespaces_dead(&dev->ctrl);
03e0f3a6 2794 if (!queue_work(nvme_wq, &dev->remove_work))
f58944e2
KB		 2795 nvme_put_ctrl(&dev->ctrl);
2796}
2797
fd634f41 2798static void nvme_reset_work(struct work_struct *work)
5e82e952 2799{
d86c4d8e
CH		 2800 struct nvme_dev *dev =
2801 container_of(work, struct nvme_dev, ctrl.reset_work);
a98e58e5 2802 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
e71afda4 2803 int result;
5e82e952 2804
7764656b
ZC		 2805 if (dev->ctrl.state != NVME_CTRL_RESETTING) {
2806 dev_warn(dev->ctrl.device, "ctrl state %d is not RESETTING\n",
2807 dev->ctrl.state);
e71afda4 2808 result = -ENODEV;
fd634f41 2809 goto out;
e71afda4 2810 }
5e82e952 2811
fd634f41
CH		 2812 /*
2813 * If we're called to reset a live controller first shut it down before
2814 * moving on.
2815 */
b00a726a 2816 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
a5cdb68c 2817 nvme_dev_disable(dev, false);
d6135c3a 2818 nvme_sync_queues(&dev->ctrl);
5e82e952 2819
5c959d73 2820 mutex_lock(&dev->shutdown_lock);
b00a726a 2821 result = nvme_pci_enable(dev);
f0b50732 2822 if (result)
4726bcf3 2823 goto out_unlock;
f0b50732 2824
01ad0990 2825 result = nvme_pci_configure_admin_queue(dev);
f0b50732 2826 if (result)
4726bcf3 2827 goto out_unlock;
f0b50732 2828
f91b727c
CH		 2829 if (!dev->ctrl.admin_q) {
2830 result = nvme_pci_alloc_admin_tag_set(dev);
2831 if (result)
2832 goto out_unlock;
2833 } else {
2834 nvme_start_admin_queue(&dev->ctrl);
2835 }
b9afca3e 2836
61ce339f
RB		 2837 dma_set_min_align_mask(dev->dev, NVME_CTRL_PAGE_SIZE - 1);
2838
943e942e
JA		 2839 /*
2840 * Limit the max command size to prevent iod->sg allocations going
2841 * over a single page.
2842 */
7637de31
CH		 2843 dev->ctrl.max_hw_sectors = min_t(u32,
2844 NVME_MAX_KB_SZ << 1, dma_max_mapping_size(dev->dev) >> 9);
943e942e 2845 dev->ctrl.max_segments = NVME_MAX_SEGS;
a48bc520
CH		 2846
2847 /*
2848 * Don't limit the IOMMU merged segment size.
2849 */
2850 dma_set_max_seg_size(dev->dev, 0xffffffff);
2851
5c959d73
KB		 2852 mutex_unlock(&dev->shutdown_lock);
2853
2854 /*
2855 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
2856 * initializing procedure here.
2857 */
2858 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
2859 dev_warn(dev->ctrl.device,
2860 "failed to mark controller CONNECTING\n");
cee6c269 2861 result = -EBUSY;
5c959d73
KB		 2862 goto out;
2863 }
943e942e 2864
95093350
MG		 2865 /*
2866 * We do not support an SGL for metadata (yet), so we are limited to a
2867 * single integrity segment for the separate metadata pointer.
2868 */
2869 dev->ctrl.max_integrity_segments = 1;
2870
94cc781f 2871 result = nvme_init_ctrl_finish(&dev->ctrl, was_suspend);
ce4541f4 2872 if (result)
f58944e2 2873 goto out;
ce4541f4 2874
f9f38e33
HK		 2875 if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) {
2876 result = nvme_dbbuf_dma_alloc(dev);
2877 if (result)
2878 dev_warn(dev->dev,
2879 "unable to allocate dma for dbbuf\n");
2880 }
2881
9620cfba
CH		 2882 if (dev->ctrl.hmpre) {
2883 result = nvme_setup_host_mem(dev);
2884 if (result < 0)
2885 goto out;
2886 }
87ad72a5 2887
f0b50732 2888 result = nvme_setup_io_queues(dev);
badc34d4 2889 if (result)
f58944e2 2890 goto out;
f0b50732 2891
0ffc7e98
CH		 2892 if (dev->ctrl.tagset) {
2893 /*
2894 * This is a controller reset and we already have a tagset.
2895 * Freeze and update the number of I/O queues as thos might have
2896 * changed. If there are no I/O queues left after this reset,
2897 * keep the controller around but remove all namespaces.
2898 */
2899 if (dev->online_queues > 1) {
2900 nvme_start_queues(&dev->ctrl);
2901 nvme_wait_freeze(&dev->ctrl);
2902 nvme_pci_update_nr_queues(dev);
2903 nvme_dbbuf_set(dev);
2904 nvme_unfreeze(&dev->ctrl);
2905 } else {
2906 dev_warn(dev->ctrl.device, "IO queues lost\n");
cd50f9b2
CH		 2907 nvme_mark_namespaces_dead(&dev->ctrl);
2908 nvme_start_queues(&dev->ctrl);
0ffc7e98
CH		 2909 nvme_remove_namespaces(&dev->ctrl);
2910 nvme_free_tagset(dev);
2911 }
3cf519b5 2912 } else {
0ffc7e98
CH		 2913 /*
2914 * First probe. Still allow the controller to show up even if
2915 * there are no namespaces.
2916 */
2917 if (dev->online_queues > 1) {
2455a4b7 2918 nvme_pci_alloc_tag_set(dev);
0ffc7e98
CH		 2919 nvme_dbbuf_set(dev);
2920 } else {
2921 dev_warn(dev->ctrl.device, "IO queues not created\n");
2922 }
3cf519b5
CH		 2923 }
2924
2b1b7e78
JW		 2925 /*
2926 * If only admin queue live, keep it to do further investigation or
2927 * recovery.
2928 */
5d02a5c1 2929 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
2b1b7e78 2930 dev_warn(dev->ctrl.device,
5d02a5c1 2931 "failed to mark controller live state\n");
e71afda4 2932 result = -ENODEV;
bb8d261e
CH		 2933 goto out;
2934 }
92911a55 2935
d09f2b45 2936 nvme_start_ctrl(&dev->ctrl);
3cf519b5 2937 return;
f0b50732 2938
4726bcf3
KB		 2939 out_unlock:
2940 mutex_unlock(&dev->shutdown_lock);
3cf519b5 2941 out:
7c1ce408
CK		 2942 if (result)
2943 dev_warn(dev->ctrl.device,
2944 "Removing after probe failure status: %d\n", result);
2945 nvme_remove_dead_ctrl(dev);
f0b50732
KB		 2946}
2947
5c8809e6 2948static void nvme_remove_dead_ctrl_work(struct work_struct *work)
9a6b9458 2949{
5c8809e6 2950 struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
e75ec752 2951 struct pci_dev *pdev = to_pci_dev(dev->dev);
9a6b9458
KB		 2952
2953 if (pci_get_drvdata(pdev))
921920ab 2954 device_release_driver(&pdev->dev);
1673f1f0 2955 nvme_put_ctrl(&dev->ctrl);
9a6b9458
KB		 2956}
2957
1c63dc66 2958static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
9ca97374 2959{
1c63dc66 2960 *val = readl(to_nvme_dev(ctrl)->bar + off);
90667892 2961 return 0;
9ca97374
TH		 2962}
2963
5fd4ce1b 2964static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
4cc06521 2965{
5fd4ce1b
CH		 2966 writel(val, to_nvme_dev(ctrl)->bar + off);
2967 return 0;
2968}
4cc06521 2969
7fd8930f
CH		 2970static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2971{
3a8ecc93 2972 *val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off);
7fd8930f 2973 return 0;
4cc06521
KB		 2974}
2975
97c12223
KB		 2976static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
2977{
2978 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2979
2db24e4a 2980 return snprintf(buf, size, "%s\n", dev_name(&pdev->dev));
97c12223
KB		 2981}
2982
2f0dad17
KB		 2983static void nvme_pci_print_device_info(struct nvme_ctrl *ctrl)
2984{
2985 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2986 struct nvme_subsystem *subsys = ctrl->subsys;
2987
2988 dev_err(ctrl->device,
2989 "VID:DID %04x:%04x model:%.*s firmware:%.*s\n",
2990 pdev->vendor, pdev->device,
2991 nvme_strlen(subsys->model, sizeof(subsys->model)),
2992 subsys->model, nvme_strlen(subsys->firmware_rev,
2993 sizeof(subsys->firmware_rev)),
2994 subsys->firmware_rev);
2995}
2996
2f859441
LG		 2997static bool nvme_pci_supports_pci_p2pdma(struct nvme_ctrl *ctrl)
2998{
2999 struct nvme_dev *dev = to_nvme_dev(ctrl);
3000
3001 return dma_pci_p2pdma_supported(dev->dev);
3002}
3003
1c63dc66 3004static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
1a353d85 3005 .name = "pcie",
e439bb12 3006 .module = THIS_MODULE,
2f859441 3007 .flags = NVME_F_METADATA_SUPPORTED,
86adbf0c 3008 .dev_attr_groups = nvme_pci_dev_attr_groups,
1c63dc66 3009 .reg_read32 = nvme_pci_reg_read32,
5fd4ce1b 3010 .reg_write32 = nvme_pci_reg_write32,
7fd8930f 3011 .reg_read64 = nvme_pci_reg_read64,
1673f1f0 3012 .free_ctrl = nvme_pci_free_ctrl,
f866fc42 3013 .submit_async_event = nvme_pci_submit_async_event,
97c12223 3014 .get_address = nvme_pci_get_address,
2f0dad17 3015 .print_device_info = nvme_pci_print_device_info,
2f859441 3016 .supports_pci_p2pdma = nvme_pci_supports_pci_p2pdma,
1c63dc66 3017};
4cc06521 3018
b00a726a
KB		 3019static int nvme_dev_map(struct nvme_dev *dev)
3020{
b00a726a
KB		 3021 struct pci_dev *pdev = to_pci_dev(dev->dev);
3022
a1f447b3 3023 if (pci_request_mem_regions(pdev, "nvme"))
b00a726a
KB		 3024 return -ENODEV;
3025
97f6ef64 3026 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
b00a726a
KB		 3027 goto release;
3028
9fa196e7 3029 return 0;
b00a726a 3030 release:
9fa196e7
MG		 3031 pci_release_mem_regions(pdev);
3032 return -ENODEV;
b00a726a
KB		 3033}
3034
8427bbc2 3035static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
ff5350a8
AL		 3036{
3037 if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
3038 /*
3039 * Several Samsung devices seem to drop off the PCIe bus
3040 * randomly when APST is on and uses the deepest sleep state.
3041 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
3042 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
3043 * 950 PRO 256GB", but it seems to be restricted to two Dell
3044 * laptops.
3045 */
3046 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
3047 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
3048 dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
3049 return NVME_QUIRK_NO_DEEPEST_PS;
8427bbc2
KHF		 3050 } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
3051 /*
3052 * Samsung SSD 960 EVO drops off the PCIe bus after system
467c77d4
JJ		 3053 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
3054 * within few minutes after bootup on a Coffee Lake board -
3055 * ASUS PRIME Z370-A
8427bbc2
KHF		 3056 */
3057 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
467c77d4
JJ		 3058 (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") ||
3059 dmi_match(DMI_BOARD_NAME, "PRIME Z370-A")))
8427bbc2 3060 return NVME_QUIRK_NO_APST;
1fae37ac
S		 3061 } else if ((pdev->vendor == 0x144d && (pdev->device == 0xa801 ||
3062 pdev->device == 0xa808 || pdev->device == 0xa809)) ||
3063 (pdev->vendor == 0x1e0f && pdev->device == 0x0001)) {
3064 /*
3065 * Forcing to use host managed nvme power settings for
3066 * lowest idle power with quick resume latency on
3067 * Samsung and Toshiba SSDs based on suspend behavior
3068 * on Coffee Lake board for LENOVO C640
3069 */
3070 if ((dmi_match(DMI_BOARD_VENDOR, "LENOVO")) &&
3071 dmi_match(DMI_BOARD_NAME, "LNVNB161216"))
3072 return NVME_QUIRK_SIMPLE_SUSPEND;
ff5350a8
AL		 3073 }
3074
3075 return 0;
3076}
3077
18119775
KB		 3078static void nvme_async_probe(void *data, async_cookie_t cookie)
3079{
3080 struct nvme_dev *dev = data;
80f513b5 3081
bd46a906 3082 flush_work(&dev->ctrl.reset_work);
18119775 3083 flush_work(&dev->ctrl.scan_work);
80f513b5 3084 nvme_put_ctrl(&dev->ctrl);
18119775
KB		 3085}
3086
8d85fce7 3087static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
b60503ba 3088{
a4aea562 3089 int node, result = -ENOMEM;
b60503ba 3090 struct nvme_dev *dev;
ff5350a8 3091 unsigned long quirks = id->driver_data;
943e942e 3092 size_t alloc_size;
b60503ba 3093
a4aea562
MB		 3094 node = dev_to_node(&pdev->dev);
3095 if (node == NUMA_NO_NODE)
2fa84351 3096 set_dev_node(&pdev->dev, first_memory_node);
a4aea562
MB		 3097
3098 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
b60503ba
MW		 3099 if (!dev)
3100 return -ENOMEM;
147b27e4 3101
2a5bcfdd
WZ		 3102 dev->nr_write_queues = write_queues;
3103 dev->nr_poll_queues = poll_queues;
3104 dev->nr_allocated_queues = nvme_max_io_queues(dev) + 1;
3105 dev->queues = kcalloc_node(dev->nr_allocated_queues,
3106 sizeof(struct nvme_queue), GFP_KERNEL, node);
b60503ba
MW		 3107 if (!dev->queues)
3108 goto free;
3109
e75ec752 3110 dev->dev = get_device(&pdev->dev);
9a6b9458 3111 pci_set_drvdata(pdev, dev);
1c63dc66 3112
b00a726a
KB		 3113 result = nvme_dev_map(dev);
3114 if (result)
b00c9b7a 3115 goto put_pci;
b00a726a 3116
d86c4d8e 3117 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
5c8809e6 3118 INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
77bf25ea 3119 mutex_init(&dev->shutdown_lock);
b60503ba 3120
091b6092
MW		 3121 result = nvme_setup_prp_pools(dev);
3122 if (result)
b00c9b7a 3123 goto unmap;
4cc06521 3124
8427bbc2 3125 quirks |= check_vendor_combination_bug(pdev);
ff5350a8 3126
2744d7a0 3127 if (!noacpi && acpi_storage_d3(&pdev->dev)) {
df4f9bc4
DB		 3128 /*
3129 * Some systems use a bios work around to ask for D3 on
3130 * platforms that support kernel managed suspend.
3131 */
3132 dev_info(&pdev->dev,
3133 "platform quirk: setting simple suspend\n");
3134 quirks |= NVME_QUIRK_SIMPLE_SUSPEND;
3135 }
3136
943e942e
JA		 3137 /*
3138 * Double check that our mempool alloc size will cover the biggest
3139 * command we support.
3140 */
b13c6393 3141 alloc_size = nvme_pci_iod_alloc_size();
943e942e
JA		 3142 WARN_ON_ONCE(alloc_size > PAGE_SIZE);
3143
3144 dev->iod_mempool = mempool_create_node(1, mempool_kmalloc,
3145 mempool_kfree,
3146 (void *) alloc_size,
3147 GFP_KERNEL, node);
3148 if (!dev->iod_mempool) {
3149 result = -ENOMEM;
3150 goto release_pools;
3151 }
3152
b6e44b4c
KB		 3153 result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
3154 quirks);
3155 if (result)
3156 goto release_mempool;
3157
1b3c47c1
SG		 3158 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
3159
bd46a906 3160 nvme_reset_ctrl(&dev->ctrl);
18119775 3161 async_schedule(nvme_async_probe, dev);
4caff8fc 3162
b60503ba
MW		 3163 return 0;
3164
b6e44b4c
KB		 3165 release_mempool:
3166 mempool_destroy(dev->iod_mempool);
0877cb0d 3167 release_pools:
091b6092 3168 nvme_release_prp_pools(dev);
b00c9b7a
CJ		 3169 unmap:
3170 nvme_dev_unmap(dev);
a96d4f5c 3171 put_pci:
e75ec752 3172 put_device(dev->dev);
b60503ba
MW		 3173 free:
3174 kfree(dev->queues);
b60503ba
MW		 3175 kfree(dev);
3176 return result;
3177}
3178
775755ed 3179static void nvme_reset_prepare(struct pci_dev *pdev)
f0d54a54 3180{
a6739479 3181 struct nvme_dev *dev = pci_get_drvdata(pdev);
c1ac9a4b
KB		 3182
3183 /*
3184 * We don't need to check the return value from waiting for the reset
3185 * state as pci_dev device lock is held, making it impossible to race
3186 * with ->remove().
3187 */
3188 nvme_disable_prepare_reset(dev, false);
3189 nvme_sync_queues(&dev->ctrl);
775755ed 3190}
f0d54a54 3191
775755ed
CH		 3192static void nvme_reset_done(struct pci_dev *pdev)
3193{
f263fbb8 3194 struct nvme_dev *dev = pci_get_drvdata(pdev);
c1ac9a4b
KB		 3195
3196 if (!nvme_try_sched_reset(&dev->ctrl))
3197 flush_work(&dev->ctrl.reset_work);
f0d54a54
KB		 3198}
3199
09ece142
KB		 3200static void nvme_shutdown(struct pci_dev *pdev)
3201{
3202 struct nvme_dev *dev = pci_get_drvdata(pdev);
4e523547 3203
c1ac9a4b 3204 nvme_disable_prepare_reset(dev, true);
09ece142
KB		 3205}
3206
f58944e2
KB		 3207/*
3208 * The driver's remove may be called on a device in a partially initialized
3209 * state. This function must not have any dependencies on the device state in
3210 * order to proceed.
3211 */
8d85fce7 3212static void nvme_remove(struct pci_dev *pdev)
b60503ba
MW		 3213{
3214 struct nvme_dev *dev = pci_get_drvdata(pdev);
9a6b9458 3215
bb8d261e 3216 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
9a6b9458 3217 pci_set_drvdata(pdev, NULL);
0ff9d4e1 3218
6db28eda 3219 if (!pci_device_is_present(pdev)) {
0ff9d4e1 3220 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
1d39e692 3221 nvme_dev_disable(dev, true);
6db28eda 3222 }
0ff9d4e1 3223
d86c4d8e 3224 flush_work(&dev->ctrl.reset_work);
d09f2b45
SG		 3225 nvme_stop_ctrl(&dev->ctrl);
3226 nvme_remove_namespaces(&dev->ctrl);
a5cdb68c 3227 nvme_dev_disable(dev, true);
87ad72a5 3228 nvme_free_host_mem(dev);
a4aea562 3229 nvme_dev_remove_admin(dev);
a1a5ef99 3230 nvme_free_queues(dev, 0);
9a6b9458 3231 nvme_release_prp_pools(dev);
b00a726a 3232 nvme_dev_unmap(dev);
726612b6 3233 nvme_uninit_ctrl(&dev->ctrl);
b60503ba
MW		 3234}
3235
671a6018 3236#ifdef CONFIG_PM_SLEEP
d916b1be
KB		 3237static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps)
3238{
3239 return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps);
3240}
3241
3242static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps)
3243{
3244 return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL);
3245}
3246
3247static int nvme_resume(struct device *dev)
3248{
3249 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
3250 struct nvme_ctrl *ctrl = &ndev->ctrl;
3251
4eaefe8c 3252 if (ndev->last_ps == U32_MAX ||
d916b1be 3253 nvme_set_power_state(ctrl, ndev->last_ps) != 0)
e5ad96f3
KB		 3254 goto reset;
3255 if (ctrl->hmpre && nvme_setup_host_mem(ndev))
3256 goto reset;
3257
d916b1be 3258 return 0;
e5ad96f3
KB		 3259reset:
3260 return nvme_try_sched_reset(ctrl);
d916b1be
KB		 3261}
3262
cd638946
KB		 3263static int nvme_suspend(struct device *dev)
3264{
3265 struct pci_dev *pdev = to_pci_dev(dev);
3266 struct nvme_dev *ndev = pci_get_drvdata(pdev);
d916b1be
KB		 3267 struct nvme_ctrl *ctrl = &ndev->ctrl;
3268 int ret = -EBUSY;
3269
4eaefe8c
RW		 3270 ndev->last_ps = U32_MAX;
3271
d916b1be
KB		 3272 /*
3273 * The platform does not remove power for a kernel managed suspend so
3274 * use host managed nvme power settings for lowest idle power if
3275 * possible. This should have quicker resume latency than a full device
3276 * shutdown. But if the firmware is involved after the suspend or the
3277 * device does not support any non-default power states, shut down the
3278 * device fully.
4eaefe8c
RW		 3279 *
3280 * If ASPM is not enabled for the device, shut down the device and allow
3281 * the PCI bus layer to put it into D3 in order to take the PCIe link
3282 * down, so as to allow the platform to achieve its minimum low-power
3283 * state (which may not be possible if the link is up).
d916b1be 3284 */
4eaefe8c 3285 if (pm_suspend_via_firmware() || !ctrl->npss ||
cb32de1b 3286 !pcie_aspm_enabled(pdev) ||
c1ac9a4b
KB		 3287 (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND))
3288 return nvme_disable_prepare_reset(ndev, true);
d916b1be
KB		 3289
3290 nvme_start_freeze(ctrl);
3291 nvme_wait_freeze(ctrl);
3292 nvme_sync_queues(ctrl);
3293
5d02a5c1 3294 if (ctrl->state != NVME_CTRL_LIVE)
d916b1be
KB		 3295 goto unfreeze;
3296
e5ad96f3
KB		 3297 /*
3298 * Host memory access may not be successful in a system suspend state,
3299 * but the specification allows the controller to access memory in a
3300 * non-operational power state.
3301 */
3302 if (ndev->hmb) {
3303 ret = nvme_set_host_mem(ndev, 0);
3304 if (ret < 0)
3305 goto unfreeze;
3306 }
3307
d916b1be
KB		 3308 ret = nvme_get_power_state(ctrl, &ndev->last_ps);
3309 if (ret < 0)
3310 goto unfreeze;
3311
7cbb5c6f
ML		 3312 /*
3313 * A saved state prevents pci pm from generically controlling the
3314 * device's power. If we're using protocol specific settings, we don't
3315 * want pci interfering.
3316 */
3317 pci_save_state(pdev);
3318
d916b1be
KB		 3319 ret = nvme_set_power_state(ctrl, ctrl->npss);
3320 if (ret < 0)
3321 goto unfreeze;
3322
3323 if (ret) {
7cbb5c6f
ML		 3324 /* discard the saved state */
3325 pci_load_saved_state(pdev, NULL);
3326
d916b1be
KB		 3327 /*
3328 * Clearing npss forces a controller reset on resume. The
05d3046f 3329 * correct value will be rediscovered then.
d916b1be 3330 */
c1ac9a4b 3331 ret = nvme_disable_prepare_reset(ndev, true);
d916b1be 3332 ctrl->npss = 0;
d916b1be 3333 }
d916b1be
KB		 3334unfreeze:
3335 nvme_unfreeze(ctrl);
3336 return ret;
3337}
3338
3339static int nvme_simple_suspend(struct device *dev)
3340{
3341 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
4e523547 3342
c1ac9a4b 3343 return nvme_disable_prepare_reset(ndev, true);
cd638946
KB		 3344}
3345
d916b1be 3346static int nvme_simple_resume(struct device *dev)
cd638946
KB		 3347{
3348 struct pci_dev *pdev = to_pci_dev(dev);
3349 struct nvme_dev *ndev = pci_get_drvdata(pdev);
cd638946 3350
c1ac9a4b 3351 return nvme_try_sched_reset(&ndev->ctrl);
cd638946
KB		 3352}
3353
21774222 3354static const struct dev_pm_ops nvme_dev_pm_ops = {
d916b1be
KB		 3355 .suspend = nvme_suspend,
3356 .resume = nvme_resume,
3357 .freeze = nvme_simple_suspend,
3358 .thaw = nvme_simple_resume,
3359 .poweroff = nvme_simple_suspend,
3360 .restore = nvme_simple_resume,
3361};
3362#endif /* CONFIG_PM_SLEEP */
b60503ba 3363
a0a3408e
KB		 3364static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
3365 pci_channel_state_t state)
3366{
3367 struct nvme_dev *dev = pci_get_drvdata(pdev);
3368
3369 /*
3370 * A frozen channel requires a reset. When detected, this method will
3371 * shutdown the controller to quiesce. The controller will be restarted
3372 * after the slot reset through driver's slot_reset callback.
3373 */
a0a3408e
KB		 3374 switch (state) {
3375 case pci_channel_io_normal:
3376 return PCI_ERS_RESULT_CAN_RECOVER;
3377 case pci_channel_io_frozen:
d011fb31
KB		 3378 dev_warn(dev->ctrl.device,
3379 "frozen state error detected, reset controller\n");
a5cdb68c 3380 nvme_dev_disable(dev, false);
a0a3408e
KB		 3381 return PCI_ERS_RESULT_NEED_RESET;
3382 case pci_channel_io_perm_failure:
d011fb31
KB		 3383 dev_warn(dev->ctrl.device,
3384 "failure state error detected, request disconnect\n");
a0a3408e
KB		 3385 return PCI_ERS_RESULT_DISCONNECT;
3386 }
3387 return PCI_ERS_RESULT_NEED_RESET;
3388}
3389
3390static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
3391{
3392 struct nvme_dev *dev = pci_get_drvdata(pdev);
3393
1b3c47c1 3394 dev_info(dev->ctrl.device, "restart after slot reset\n");
a0a3408e 3395 pci_restore_state(pdev);
d86c4d8e 3396 nvme_reset_ctrl(&dev->ctrl);
a0a3408e
KB		 3397 return PCI_ERS_RESULT_RECOVERED;
3398}
3399
3400static void nvme_error_resume(struct pci_dev *pdev)
3401{
72cd4cc2
KB		 3402 struct nvme_dev *dev = pci_get_drvdata(pdev);
3403
3404 flush_work(&dev->ctrl.reset_work);
a0a3408e
KB		 3405}
3406
1d352035 3407static const struct pci_error_handlers nvme_err_handler = {
b60503ba 3408 .error_detected = nvme_error_detected,
b60503ba
MW		 3409 .slot_reset = nvme_slot_reset,
3410 .resume = nvme_error_resume,
775755ed
CH		 3411 .reset_prepare = nvme_reset_prepare,
3412 .reset_done = nvme_reset_done,
b60503ba
MW		 3413};
3414
6eb0d698 3415static const struct pci_device_id nvme_id_table[] = {
972b13e2 3416 { PCI_VDEVICE(INTEL, 0x0953), /* Intel 750/P3500/P3600/P3700 */
08095e70 3417 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 3418 NVME_QUIRK_DEALLOCATE_ZEROES, },
972b13e2 3419 { PCI_VDEVICE(INTEL, 0x0a53), /* Intel P3520 */
99466e70 3420 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 3421 NVME_QUIRK_DEALLOCATE_ZEROES, },
972b13e2 3422 { PCI_VDEVICE(INTEL, 0x0a54), /* Intel P4500/P4600 */
99466e70 3423 .driver_data = NVME_QUIRK_STRIPE_SIZE |
25e58af4
WZ		 3424 NVME_QUIRK_DEALLOCATE_ZEROES |
3425 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
972b13e2 3426 { PCI_VDEVICE(INTEL, 0x0a55), /* Dell Express Flash P4600 */
f99cb7af
DWF		 3427 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3428 NVME_QUIRK_DEALLOCATE_ZEROES, },
50af47d0 3429 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */
9abd68ef 3430 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
6c6aa2f2 3431 NVME_QUIRK_MEDIUM_PRIO_SQ |
ce4cc313
DM		 3432 NVME_QUIRK_NO_TEMP_THRESH_CHANGE |
3433 NVME_QUIRK_DISABLE_WRITE_ZEROES, },
6299358d
JD		 3434 { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */
3435 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
540c801c 3436 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */
7b210e4e 3437 .driver_data = NVME_QUIRK_IDENTIFY_CNS |
66dd346b
CH		 3438 NVME_QUIRK_DISABLE_WRITE_ZEROES |
3439 NVME_QUIRK_BOGUS_NID, },
3440 { PCI_VDEVICE(REDHAT, 0x0010), /* Qemu emulated controller */
3441 .driver_data = NVME_QUIRK_BOGUS_NID, },
5bedd3af 3442 { PCI_DEVICE(0x126f, 0x2263), /* Silicon Motion unidentified */
c98a8793
KB		 3443 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST |
3444 NVME_QUIRK_BOGUS_NID, },
0302ae60 3445 { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */
5e112d3f
JE		 3446 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
3447 NVME_QUIRK_NO_NS_DESC_LIST, },
54adc010
GP		 3448 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
3449 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
8c97eecc
JL		 3450 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */
3451 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
015282c9
WW		 3452 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
3453 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
d554b5e1
MP		 3454 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */
3455 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3456 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */
7ee5c78c 3457 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
abbb5f59 3458 NVME_QUIRK_DISABLE_WRITE_ZEROES|
7ee5c78c 3459 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
2cf7a77e
KB		 3460 { PCI_DEVICE(0x1987, 0x5012), /* Phison E12 */
3461 .driver_data = NVME_QUIRK_BOGUS_NID, },
c9e95c39 3462 { PCI_DEVICE(0x1987, 0x5016), /* Phison E16 */
73029c9b
KB		 3463 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN |
3464 NVME_QUIRK_BOGUS_NID, },
d14c2731
TH		 3465 { PCI_DEVICE(0x1987, 0x5019), /* phison E19 */
3466 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3467 { PCI_DEVICE(0x1987, 0x5021), /* Phison E21 */
3468 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
6e6a6828
PT		 3469 { PCI_DEVICE(0x1b4b, 0x1092), /* Lexar 256 GB SSD */
3470 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST |
3471 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
e1c70d79
LVS		 3472 { PCI_DEVICE(0x1cc1, 0x33f8), /* ADATA IM2P33F8ABR1 1 TB */
3473 .driver_data = NVME_QUIRK_BOGUS_NID, },
08b903b5 3474 { PCI_DEVICE(0x10ec, 0x5762), /* ADATA SX6000LNP */
1629de0e
PG		 3475 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN |
3476 NVME_QUIRK_BOGUS_NID, },
f03e42c6
GC		 3477 { PCI_DEVICE(0x1cc1, 0x8201), /* ADATA SX8200PNP 512GB */
3478 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3479 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
41f38043
LS		 3480 { PCI_DEVICE(0x1344, 0x5407), /* Micron Technology Inc NVMe SSD */
3481 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN },
5611ec2b
KHF		 3482 { PCI_DEVICE(0x1c5c, 0x1504), /* SK Hynix PC400 */
3483 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
c4f01a77
KB		 3484 { PCI_DEVICE(0x1c5c, 0x174a), /* SK Hynix P31 SSD */
3485 .driver_data = NVME_QUIRK_BOGUS_NID, },
02ca079c
KHF		 3486 { PCI_DEVICE(0x15b7, 0x2001), /* Sandisk Skyhawk */
3487 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
89919929
CK		 3488 { PCI_DEVICE(0x1d97, 0x2263), /* SPCC */
3489 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
43047e08 3490 { PCI_DEVICE(0x144d, 0xa80b), /* Samsung PM9B1 256G and 512G */
3491 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3492 { PCI_DEVICE(0x144d, 0xa809), /* Samsung MZALQ256HBJD 256G */
3493 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3494 { PCI_DEVICE(0x1cc4, 0x6303), /* UMIS RPJTJ512MGE1QDY 512G */
3495 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3496 { PCI_DEVICE(0x1cc4, 0x6302), /* UMIS RPJTJ256MGE1QDY 256G */
3497 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
dc22c1c0
ZB		 3498 { PCI_DEVICE(0x2646, 0x2262), /* KINGSTON SKC2000 NVMe SSD */
3499 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
538e4a8c
TL		 3500 { PCI_DEVICE(0x2646, 0x2263), /* KINGSTON A2000 NVMe SSD */
3501 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
ac9b57d4
XL		 3502 { PCI_DEVICE(0x2646, 0x5018), /* KINGSTON OM8SFP4xxxxP OS21012 NVMe SSD */
3503 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3504 { PCI_DEVICE(0x2646, 0x5016), /* KINGSTON OM3PGP4xxxxP OS21011 NVMe SSD */
3505 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3506 { PCI_DEVICE(0x2646, 0x501A), /* KINGSTON OM8PGP4xxxxP OS21005 NVMe SSD */
3507 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3508 { PCI_DEVICE(0x2646, 0x501B), /* KINGSTON OM8PGP4xxxxQ OS21005 NVMe SSD */
3509 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3510 { PCI_DEVICE(0x2646, 0x501E), /* KINGSTON OM3PGP4xxxxQ OS21011 NVMe SSD */
3511 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
70ce3455
CH		 3512 { PCI_DEVICE(0x1e4B, 0x1001), /* MAXIO MAP1001 */
3513 .driver_data = NVME_QUIRK_BOGUS_NID, },
a98a945b
CH		 3514 { PCI_DEVICE(0x1e4B, 0x1002), /* MAXIO MAP1002 */
3515 .driver_data = NVME_QUIRK_BOGUS_NID, },
3516 { PCI_DEVICE(0x1e4B, 0x1202), /* MAXIO MAP1202 */
3517 .driver_data = NVME_QUIRK_BOGUS_NID, },
3765fad5
SR		 3518 { PCI_DEVICE(0x1cc1, 0x5350), /* ADATA XPG GAMMIX S50 */
3519 .driver_data = NVME_QUIRK_BOGUS_NID, },
f37527a0
DK		 3520 { PCI_DEVICE(0x1dbe, 0x5236), /* ADATA XPG GAMMIX S70 */
3521 .driver_data = NVME_QUIRK_BOGUS_NID, },
d5d3c100
XR		 3522 { PCI_DEVICE(0x1e49, 0x0021), /* ZHITAI TiPro5000 NVMe SSD */
3523 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
6b961bce
NW		 3524 { PCI_DEVICE(0x1e49, 0x0041), /* ZHITAI TiPro7000 NVMe SSD */
3525 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
d6c52fa3
TG		 3526 { PCI_DEVICE(0xc0a9, 0x540a), /* Crucial P2 */
3527 .driver_data = NVME_QUIRK_BOGUS_NID, },
200dccd0
SA		 3528 { PCI_DEVICE(0x1d97, 0x2263), /* Lexar NM610 */
3529 .driver_data = NVME_QUIRK_BOGUS_NID, },
80b26240
A		 3530 { PCI_DEVICE(0x1d97, 0x2269), /* Lexar NM760 */
3531 .driver_data = NVME_QUIRK_BOGUS_NID, },
4bdf2603
FS		 3532 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0061),
3533 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3534 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0065),
3535 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3536 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x8061),
3537 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3538 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd00),
3539 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3540 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd01),
3541 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3542 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd02),
3543 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
98f7b86a
AS		 3544 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001),
3545 .driver_data = NVME_QUIRK_SINGLE_VECTOR },
124298bd 3546 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
66341331
BH		 3547 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005),
3548 .driver_data = NVME_QUIRK_SINGLE_VECTOR |
d38e9f04 3549 NVME_QUIRK_128_BYTES_SQES |
a2941f6a
KB		 3550 NVME_QUIRK_SHARED_TAGS |
3551 NVME_QUIRK_SKIP_CID_GEN },
0b85f59d 3552 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
b60503ba
MW		 3553 { 0, }
3554};
3555MODULE_DEVICE_TABLE(pci, nvme_id_table);
3556
3557static struct pci_driver nvme_driver = {
3558 .name = "nvme",
3559 .id_table = nvme_id_table,
3560 .probe = nvme_probe,
8d85fce7 3561 .remove = nvme_remove,
09ece142 3562 .shutdown = nvme_shutdown,
d916b1be 3563#ifdef CONFIG_PM_SLEEP
cd638946
KB		 3564 .driver = {
3565 .pm = &nvme_dev_pm_ops,
3566 },
d916b1be 3567#endif
74d986ab 3568 .sriov_configure = pci_sriov_configure_simple,
b60503ba
MW		 3569 .err_handler = &nvme_err_handler,
3570};
3571
3572static int __init nvme_init(void)
3573{
81101540
CH		 3574 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
3575 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
3576 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
612b7286 3577 BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2);
c372cdd1
KB		 3578 BUILD_BUG_ON(DIV_ROUND_UP(nvme_pci_npages_prp(), NVME_CTRL_PAGE_SIZE) >
3579 S8_MAX);
17c33167 3580
9a6327d2 3581 return pci_register_driver(&nvme_driver);
b60503ba
MW		 3582}
3583
3584static void __exit nvme_exit(void)
3585{
3586 pci_unregister_driver(&nvme_driver);
03e0f3a6 3587 flush_workqueue(nvme_wq);
b60503ba
MW		 3588}
3589
3590MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3591MODULE_LICENSE("GPL");
c78b4713 3592MODULE_VERSION("1.0");
b60503ba
MW		 3593module_init(nvme_init);
3594module_exit(nvme_exit);
Linux 6.x block layer and io_uring tree(s)