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nvme-tcp: use __dev_get_by_name instead dev_get_by_name for OPT_HOST_IFACE
[linux-2.6-block.git] / drivers / nvme / host / pci.c
CommitLineData
5f37396d 1// SPDX-License-Identifier: GPL-2.0
b60503ba
MW		 2/*
3 * NVM Express device driver
6eb0d698 4 * Copyright (c) 2011-2014, Intel Corporation.
b60503ba
MW		 5 */
6
df4f9bc4 7#include <linux/acpi.h>
a0a3408e 8#include <linux/aer.h>
18119775 9#include <linux/async.h>
b60503ba 10#include <linux/blkdev.h>
a4aea562 11#include <linux/blk-mq.h>
dca51e78 12#include <linux/blk-mq-pci.h>
ff5350a8 13#include <linux/dmi.h>
b60503ba
MW		 14#include <linux/init.h>
15#include <linux/interrupt.h>
16#include <linux/io.h>
b60503ba
MW		 17#include <linux/mm.h>
18#include <linux/module.h>
77bf25ea 19#include <linux/mutex.h>
d0877473 20#include <linux/once.h>
b60503ba 21#include <linux/pci.h>
d916b1be 22#include <linux/suspend.h>
e1e5e564 23#include <linux/t10-pi.h>
b60503ba 24#include <linux/types.h>
2f8e2c87 25#include <linux/io-64-nonatomic-lo-hi.h>
20d3bb92 26#include <linux/io-64-nonatomic-hi-lo.h>
a98e58e5 27#include <linux/sed-opal.h>
0f238ff5 28#include <linux/pci-p2pdma.h>
797a796a 29
604c01d5 30#include "trace.h"
f11bb3e2
CH		 31#include "nvme.h"
32
c1e0cc7e 33#define SQ_SIZE(q) ((q)->q_depth << (q)->sqes)
8a1d09a6 34#define CQ_SIZE(q) ((q)->q_depth * sizeof(struct nvme_completion))
c965809c 35
a7a7cbe3 36#define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc))
9d43cf64 37
943e942e
JA		 38/*
39 * These can be higher, but we need to ensure that any command doesn't
40 * require an sg allocation that needs more than a page of data.
41 */
42#define NVME_MAX_KB_SZ 4096
43#define NVME_MAX_SEGS 127
44
58ffacb5
MW		 45static int use_threaded_interrupts;
46module_param(use_threaded_interrupts, int, 0);
47
8ffaadf7 48static bool use_cmb_sqes = true;
69f4eb9f 49module_param(use_cmb_sqes, bool, 0444);
8ffaadf7
JD		 50MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
51
87ad72a5
CH		 52static unsigned int max_host_mem_size_mb = 128;
53module_param(max_host_mem_size_mb, uint, 0444);
54MODULE_PARM_DESC(max_host_mem_size_mb,
55 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
1fa6aead 56
a7a7cbe3
CK		 57static unsigned int sgl_threshold = SZ_32K;
58module_param(sgl_threshold, uint, 0644);
59MODULE_PARM_DESC(sgl_threshold,
60 "Use SGLs when average request segment size is larger or equal to "
61 "this size. Use 0 to disable SGLs.");
62
b27c1e68 63static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
64static const struct kernel_param_ops io_queue_depth_ops = {
65 .set = io_queue_depth_set,
61f3b896 66 .get = param_get_uint,
b27c1e68 67};
68
61f3b896 69static unsigned int io_queue_depth = 1024;
b27c1e68 70module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
71MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2");
72
9c9e76d5
WZ		 73static int io_queue_count_set(const char *val, const struct kernel_param *kp)
74{
75 unsigned int n;
76 int ret;
77
78 ret = kstrtouint(val, 10, &n);
79 if (ret != 0 || n > num_possible_cpus())
80 return -EINVAL;
81 return param_set_uint(val, kp);
82}
83
84static const struct kernel_param_ops io_queue_count_ops = {
85 .set = io_queue_count_set,
86 .get = param_get_uint,
87};
88
3f68baf7 89static unsigned int write_queues;
9c9e76d5 90module_param_cb(write_queues, &io_queue_count_ops, &write_queues, 0644);
3b6592f7
JA		 91MODULE_PARM_DESC(write_queues,
92 "Number of queues to use for writes. If not set, reads and writes "
93 "will share a queue set.");
94
3f68baf7 95static unsigned int poll_queues;
9c9e76d5 96module_param_cb(poll_queues, &io_queue_count_ops, &poll_queues, 0644);
4b04cc6a
JA		 97MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO.");
98
df4f9bc4
DB		 99static bool noacpi;
100module_param(noacpi, bool, 0444);
101MODULE_PARM_DESC(noacpi, "disable acpi bios quirks");
102
1c63dc66
CH		 103struct nvme_dev;
104struct nvme_queue;
b3fffdef 105
a5cdb68c 106static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
8fae268b 107static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode);
d4b4ff8e 108
1c63dc66
CH		 109/*
110 * Represents an NVM Express device. Each nvme_dev is a PCI function.
111 */
112struct nvme_dev {
147b27e4 113 struct nvme_queue *queues;
1c63dc66
CH		 114 struct blk_mq_tag_set tagset;
115 struct blk_mq_tag_set admin_tagset;
116 u32 __iomem *dbs;
117 struct device *dev;
118 struct dma_pool *prp_page_pool;
119 struct dma_pool *prp_small_pool;
1c63dc66
CH		 120 unsigned online_queues;
121 unsigned max_qid;
e20ba6e1 122 unsigned io_queues[HCTX_MAX_TYPES];
22b55601 123 unsigned int num_vecs;
7442ddce 124 u32 q_depth;
c1e0cc7e 125 int io_sqes;
1c63dc66 126 u32 db_stride;
1c63dc66 127 void __iomem *bar;
97f6ef64 128 unsigned long bar_mapped_size;
5c8809e6 129 struct work_struct remove_work;
77bf25ea 130 struct mutex shutdown_lock;
1c63dc66 131 bool subsystem;
1c63dc66 132 u64 cmb_size;
0f238ff5 133 bool cmb_use_sqes;
1c63dc66 134 u32 cmbsz;
202021c1 135 u32 cmbloc;
1c63dc66 136 struct nvme_ctrl ctrl;
d916b1be 137 u32 last_ps;
87ad72a5 138
943e942e
JA		 139 mempool_t *iod_mempool;
140
87ad72a5 141 /* shadow doorbell buffer support: */
f9f38e33
HK		 142 u32 *dbbuf_dbs;
143 dma_addr_t dbbuf_dbs_dma_addr;
144 u32 *dbbuf_eis;
145 dma_addr_t dbbuf_eis_dma_addr;
87ad72a5
CH		 146
147 /* host memory buffer support: */
148 u64 host_mem_size;
149 u32 nr_host_mem_descs;
4033f35d 150 dma_addr_t host_mem_descs_dma;
87ad72a5
CH		 151 struct nvme_host_mem_buf_desc *host_mem_descs;
152 void **host_mem_desc_bufs;
2a5bcfdd
WZ		 153 unsigned int nr_allocated_queues;
154 unsigned int nr_write_queues;
155 unsigned int nr_poll_queues;
4d115420 156};
1fa6aead 157
b27c1e68 158static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
159{
61f3b896 160 int ret;
7442ddce 161 u32 n;
b27c1e68 162
7442ddce 163 ret = kstrtou32(val, 10, &n);
b27c1e68 164 if (ret != 0 || n < 2)
165 return -EINVAL;
166
7442ddce 167 return param_set_uint(val, kp);
b27c1e68 168}
169
f9f38e33
HK		 170static inline unsigned int sq_idx(unsigned int qid, u32 stride)
171{
172 return qid * 2 * stride;
173}
174
175static inline unsigned int cq_idx(unsigned int qid, u32 stride)
176{
177 return (qid * 2 + 1) * stride;
178}
179
1c63dc66
CH		 180static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
181{
182 return container_of(ctrl, struct nvme_dev, ctrl);
183}
184
b60503ba
MW		 185/*
186 * An NVM Express queue. Each device has at least two (one for admin
187 * commands and one for I/O commands).
188 */
189struct nvme_queue {
091b6092 190 struct nvme_dev *dev;
1ab0cd69 191 spinlock_t sq_lock;
c1e0cc7e 192 void *sq_cmds;
3a7afd8e
CH		 193 /* only used for poll queues: */
194 spinlock_t cq_poll_lock ____cacheline_aligned_in_smp;
74943d45 195 struct nvme_completion *cqes;
b60503ba
MW		 196 dma_addr_t sq_dma_addr;
197 dma_addr_t cq_dma_addr;
b60503ba 198 u32 __iomem *q_db;
7442ddce 199 u32 q_depth;
7c349dde 200 u16 cq_vector;
b60503ba 201 u16 sq_tail;
38210800 202 u16 last_sq_tail;
b60503ba 203 u16 cq_head;
c30341dc 204 u16 qid;
e9539f47 205 u8 cq_phase;
c1e0cc7e 206 u8 sqes;
4e224106
CH		 207 unsigned long flags;
208#define NVMEQ_ENABLED 0
63223078 209#define NVMEQ_SQ_CMB 1
d1ed6aa1 210#define NVMEQ_DELETE_ERROR 2
7c349dde 211#define NVMEQ_POLLED 3
f9f38e33
HK		 212 u32 *dbbuf_sq_db;
213 u32 *dbbuf_cq_db;
214 u32 *dbbuf_sq_ei;
215 u32 *dbbuf_cq_ei;
d1ed6aa1 216 struct completion delete_done;
b60503ba
MW		 217};
218
71bd150c 219/*
9b048119
CH		 220 * The nvme_iod describes the data in an I/O.
221 *
222 * The sg pointer contains the list of PRP/SGL chunk allocations in addition
223 * to the actual struct scatterlist.
71bd150c
CH		 224 */
225struct nvme_iod {
d49187e9 226 struct nvme_request req;
af7fae85 227 struct nvme_command cmd;
f4800d6d 228 struct nvme_queue *nvmeq;
a7a7cbe3 229 bool use_sgl;
f4800d6d 230 int aborted;
71bd150c 231 int npages; /* In the PRP list. 0 means small pool in use */
71bd150c 232 int nents; /* Used in scatterlist */
71bd150c 233 dma_addr_t first_dma;
dff824b2 234 unsigned int dma_len; /* length of single DMA segment mapping */
783b94bd 235 dma_addr_t meta_dma;
f4800d6d 236 struct scatterlist *sg;
b60503ba
MW		 237};
238
2a5bcfdd 239static inline unsigned int nvme_dbbuf_size(struct nvme_dev *dev)
3b6592f7 240{
2a5bcfdd 241 return dev->nr_allocated_queues * 8 * dev->db_stride;
f9f38e33
HK		 242}
243
244static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
245{
2a5bcfdd 246 unsigned int mem_size = nvme_dbbuf_size(dev);
f9f38e33
HK		 247
248 if (dev->dbbuf_dbs)
249 return 0;
250
251 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
252 &dev->dbbuf_dbs_dma_addr,
253 GFP_KERNEL);
254 if (!dev->dbbuf_dbs)
255 return -ENOMEM;
256 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
257 &dev->dbbuf_eis_dma_addr,
258 GFP_KERNEL);
259 if (!dev->dbbuf_eis) {
260 dma_free_coherent(dev->dev, mem_size,
261 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
262 dev->dbbuf_dbs = NULL;
263 return -ENOMEM;
264 }
265
266 return 0;
267}
268
269static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
270{
2a5bcfdd 271 unsigned int mem_size = nvme_dbbuf_size(dev);
f9f38e33
HK		 272
273 if (dev->dbbuf_dbs) {
274 dma_free_coherent(dev->dev, mem_size,
275 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
276 dev->dbbuf_dbs = NULL;
277 }
278 if (dev->dbbuf_eis) {
279 dma_free_coherent(dev->dev, mem_size,
280 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
281 dev->dbbuf_eis = NULL;
282 }
283}
284
285static void nvme_dbbuf_init(struct nvme_dev *dev,
286 struct nvme_queue *nvmeq, int qid)
287{
288 if (!dev->dbbuf_dbs || !qid)
289 return;
290
291 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
292 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
293 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
294 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
295}
296
0f0d2c87
MI		 297static void nvme_dbbuf_free(struct nvme_queue *nvmeq)
298{
299 if (!nvmeq->qid)
300 return;
301
302 nvmeq->dbbuf_sq_db = NULL;
303 nvmeq->dbbuf_cq_db = NULL;
304 nvmeq->dbbuf_sq_ei = NULL;
305 nvmeq->dbbuf_cq_ei = NULL;
306}
307
f9f38e33
HK		 308static void nvme_dbbuf_set(struct nvme_dev *dev)
309{
f66e2804 310 struct nvme_command c = { };
0f0d2c87 311 unsigned int i;
f9f38e33
HK		 312
313 if (!dev->dbbuf_dbs)
314 return;
315
f9f38e33
HK		 316 c.dbbuf.opcode = nvme_admin_dbbuf;
317 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
318 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
319
320 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
9bdcfb10 321 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
f9f38e33
HK		 322 /* Free memory and continue on */
323 nvme_dbbuf_dma_free(dev);
0f0d2c87
MI		 324
325 for (i = 1; i <= dev->online_queues; i++)
326 nvme_dbbuf_free(&dev->queues[i]);
f9f38e33
HK		 327 }
328}
329
330static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
331{
332 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
333}
334
335/* Update dbbuf and return true if an MMIO is required */
336static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
337 volatile u32 *dbbuf_ei)
338{
339 if (dbbuf_db) {
340 u16 old_value;
341
342 /*
343 * Ensure that the queue is written before updating
344 * the doorbell in memory
345 */
346 wmb();
347
348 old_value = *dbbuf_db;
349 *dbbuf_db = value;
350
f1ed3df2
MW		 351 /*
352 * Ensure that the doorbell is updated before reading the event
353 * index from memory. The controller needs to provide similar
354 * ordering to ensure the envent index is updated before reading
355 * the doorbell.
356 */
357 mb();
358
f9f38e33
HK		 359 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value))
360 return false;
361 }
362
363 return true;
b60503ba
MW		 364}
365
ac3dd5bd
JA		 366/*
367 * Will slightly overestimate the number of pages needed. This is OK
368 * as it only leads to a small amount of wasted memory for the lifetime of
369 * the I/O.
370 */
b13c6393 371static int nvme_pci_npages_prp(void)
ac3dd5bd 372{
b13c6393 373 unsigned nprps = DIV_ROUND_UP(NVME_MAX_KB_SZ + NVME_CTRL_PAGE_SIZE,
6c3c05b0 374 NVME_CTRL_PAGE_SIZE);
ac3dd5bd
JA		 375 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
376}
377
a7a7cbe3
CK		 378/*
379 * Calculates the number of pages needed for the SGL segments. For example a 4k
380 * page can accommodate 256 SGL descriptors.
381 */
b13c6393 382static int nvme_pci_npages_sgl(void)
ac3dd5bd 383{
b13c6393
CK		 384 return DIV_ROUND_UP(NVME_MAX_SEGS * sizeof(struct nvme_sgl_desc),
385 PAGE_SIZE);
f4800d6d 386}
ac3dd5bd 387
b13c6393 388static size_t nvme_pci_iod_alloc_size(void)
f4800d6d 389{
b13c6393 390 size_t npages = max(nvme_pci_npages_prp(), nvme_pci_npages_sgl());
a7a7cbe3 391
b13c6393
CK		 392 return sizeof(__le64 *) * npages +
393 sizeof(struct scatterlist) * NVME_MAX_SEGS;
f4800d6d 394}
ac3dd5bd 395
a4aea562
MB		 396static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
397 unsigned int hctx_idx)
e85248e5 398{
a4aea562 399 struct nvme_dev *dev = data;
147b27e4 400 struct nvme_queue *nvmeq = &dev->queues[0];
a4aea562 401
42483228
KB		 402 WARN_ON(hctx_idx != 0);
403 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
42483228 404
a4aea562
MB		 405 hctx->driver_data = nvmeq;
406 return 0;
e85248e5
MW		 407}
408
a4aea562
MB		 409static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
410 unsigned int hctx_idx)
b60503ba 411{
a4aea562 412 struct nvme_dev *dev = data;
147b27e4 413 struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
a4aea562 414
42483228 415 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
a4aea562
MB		 416 hctx->driver_data = nvmeq;
417 return 0;
b60503ba
MW		 418}
419
d6296d39
CH		 420static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req,
421 unsigned int hctx_idx, unsigned int numa_node)
b60503ba 422{
d6296d39 423 struct nvme_dev *dev = set->driver_data;
f4800d6d 424 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
0350815a 425 int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0;
147b27e4 426 struct nvme_queue *nvmeq = &dev->queues[queue_idx];
a4aea562
MB		 427
428 BUG_ON(!nvmeq);
f4800d6d 429 iod->nvmeq = nvmeq;
59e29ce6
SG		 430
431 nvme_req(req)->ctrl = &dev->ctrl;
f4b9e6c9 432 nvme_req(req)->cmd = &iod->cmd;
a4aea562
MB		 433 return 0;
434}
435
3b6592f7
JA		 436static int queue_irq_offset(struct nvme_dev *dev)
437{
438 /* if we have more than 1 vec, admin queue offsets us by 1 */
439 if (dev->num_vecs > 1)
440 return 1;
441
442 return 0;
443}
444
dca51e78
CH		 445static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
446{
447 struct nvme_dev *dev = set->driver_data;
3b6592f7
JA		 448 int i, qoff, offset;
449
450 offset = queue_irq_offset(dev);
451 for (i = 0, qoff = 0; i < set->nr_maps; i++) {
452 struct blk_mq_queue_map *map = &set->map[i];
453
454 map->nr_queues = dev->io_queues[i];
455 if (!map->nr_queues) {
e20ba6e1 456 BUG_ON(i == HCTX_TYPE_DEFAULT);
7e849dd9 457 continue;
3b6592f7
JA		 458 }
459
4b04cc6a
JA		 460 /*
461 * The poll queue(s) doesn't have an IRQ (and hence IRQ
462 * affinity), so use the regular blk-mq cpu mapping
463 */
3b6592f7 464 map->queue_offset = qoff;
cb9e0e50 465 if (i != HCTX_TYPE_POLL && offset)
4b04cc6a
JA		 466 blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset);
467 else
468 blk_mq_map_queues(map);
3b6592f7
JA		 469 qoff += map->nr_queues;
470 offset += map->nr_queues;
471 }
472
473 return 0;
dca51e78
CH		 474}
475
38210800
KB		 476/*
477 * Write sq tail if we are asked to, or if the next command would wrap.
478 */
479static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq)
04f3eafd 480{
38210800
KB		 481 if (!write_sq) {
482 u16 next_tail = nvmeq->sq_tail + 1;
483
484 if (next_tail == nvmeq->q_depth)
485 next_tail = 0;
486 if (next_tail != nvmeq->last_sq_tail)
487 return;
488 }
489
04f3eafd
JA		 490 if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail,
491 nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei))
492 writel(nvmeq->sq_tail, nvmeq->q_db);
38210800 493 nvmeq->last_sq_tail = nvmeq->sq_tail;
04f3eafd
JA		 494}
495
b60503ba 496/**
90ea5ca4 497 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
b60503ba
MW		 498 * @nvmeq: The queue to use
499 * @cmd: The command to send
04f3eafd 500 * @write_sq: whether to write to the SQ doorbell
b60503ba 501 */
04f3eafd
JA		 502static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd,
503 bool write_sq)
b60503ba 504{
90ea5ca4 505 spin_lock(&nvmeq->sq_lock);
c1e0cc7e
BH		 506 memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes),
507 cmd, sizeof(*cmd));
90ea5ca4
CH		 508 if (++nvmeq->sq_tail == nvmeq->q_depth)
509 nvmeq->sq_tail = 0;
38210800 510 nvme_write_sq_db(nvmeq, write_sq);
04f3eafd
JA		 511 spin_unlock(&nvmeq->sq_lock);
512}
513
514static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx)
515{
516 struct nvme_queue *nvmeq = hctx->driver_data;
517
518 spin_lock(&nvmeq->sq_lock);
38210800
KB		 519 if (nvmeq->sq_tail != nvmeq->last_sq_tail)
520 nvme_write_sq_db(nvmeq, true);
90ea5ca4 521 spin_unlock(&nvmeq->sq_lock);
b60503ba
MW		 522}
523
a7a7cbe3 524static void **nvme_pci_iod_list(struct request *req)
b60503ba 525{
f4800d6d 526 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3 527 return (void **)(iod->sg + blk_rq_nr_phys_segments(req));
b60503ba
MW		 528}
529
955b1b5a
MI		 530static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req)
531{
532 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
20469a37 533 int nseg = blk_rq_nr_phys_segments(req);
955b1b5a
MI		 534 unsigned int avg_seg_size;
535
20469a37 536 avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
955b1b5a 537
253a0b76 538 if (!nvme_ctrl_sgl_supported(&dev->ctrl))
955b1b5a
MI		 539 return false;
540 if (!iod->nvmeq->qid)
541 return false;
542 if (!sgl_threshold || avg_seg_size < sgl_threshold)
543 return false;
544 return true;
545}
546
9275c206 547static void nvme_free_prps(struct nvme_dev *dev, struct request *req)
b60503ba 548{
6c3c05b0 549 const int last_prp = NVME_CTRL_PAGE_SIZE / sizeof(__le64) - 1;
9275c206
CH		 550 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
551 dma_addr_t dma_addr = iod->first_dma;
eca18b23 552 int i;
eca18b23 553
9275c206
CH		 554 for (i = 0; i < iod->npages; i++) {
555 __le64 *prp_list = nvme_pci_iod_list(req)[i];
556 dma_addr_t next_dma_addr = le64_to_cpu(prp_list[last_prp]);
557
558 dma_pool_free(dev->prp_page_pool, prp_list, dma_addr);
559 dma_addr = next_dma_addr;
7fe07d14 560 }
9275c206 561}
dff824b2 562
9275c206
CH		 563static void nvme_free_sgls(struct nvme_dev *dev, struct request *req)
564{
565 const int last_sg = SGES_PER_PAGE - 1;
566 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
567 dma_addr_t dma_addr = iod->first_dma;
568 int i;
dff824b2 569
9275c206
CH		 570 for (i = 0; i < iod->npages; i++) {
571 struct nvme_sgl_desc *sg_list = nvme_pci_iod_list(req)[i];
572 dma_addr_t next_dma_addr = le64_to_cpu((sg_list[last_sg]).addr);
dff824b2 573
9275c206
CH		 574 dma_pool_free(dev->prp_page_pool, sg_list, dma_addr);
575 dma_addr = next_dma_addr;
576 }
9275c206 577}
a7a7cbe3 578
9275c206
CH		 579static void nvme_unmap_sg(struct nvme_dev *dev, struct request *req)
580{
581 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3 582
9275c206
CH		 583 if (is_pci_p2pdma_page(sg_page(iod->sg)))
584 pci_p2pdma_unmap_sg(dev->dev, iod->sg, iod->nents,
585 rq_dma_dir(req));
586 else
587 dma_unmap_sg(dev->dev, iod->sg, iod->nents, rq_dma_dir(req));
588}
a7a7cbe3 589
9275c206
CH		 590static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
591{
592 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3 593
9275c206
CH		 594 if (iod->dma_len) {
595 dma_unmap_page(dev->dev, iod->first_dma, iod->dma_len,
596 rq_dma_dir(req));
597 return;
eca18b23 598 }
ac3dd5bd 599
9275c206
CH		 600 WARN_ON_ONCE(!iod->nents);
601
602 nvme_unmap_sg(dev, req);
603 if (iod->npages == 0)
604 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0],
605 iod->first_dma);
606 else if (iod->use_sgl)
607 nvme_free_sgls(dev, req);
608 else
609 nvme_free_prps(dev, req);
d43f1ccf 610 mempool_free(iod->sg, dev->iod_mempool);
b4ff9c8d
KB		 611}
612
d0877473
KB		 613static void nvme_print_sgl(struct scatterlist *sgl, int nents)
614{
615 int i;
616 struct scatterlist *sg;
617
618 for_each_sg(sgl, sg, nents, i) {
619 dma_addr_t phys = sg_phys(sg);
620 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
621 "dma_address:%pad dma_length:%d\n",
622 i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
623 sg_dma_len(sg));
624 }
625}
626
a7a7cbe3
CK		 627static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
628 struct request *req, struct nvme_rw_command *cmnd)
ff22b54f 629{
f4800d6d 630 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
99802a7a 631 struct dma_pool *pool;
b131c61d 632 int length = blk_rq_payload_bytes(req);
eca18b23 633 struct scatterlist *sg = iod->sg;
ff22b54f
MW		 634 int dma_len = sg_dma_len(sg);
635 u64 dma_addr = sg_dma_address(sg);
6c3c05b0 636 int offset = dma_addr & (NVME_CTRL_PAGE_SIZE - 1);
e025344c 637 __le64 *prp_list;
a7a7cbe3 638 void **list = nvme_pci_iod_list(req);
e025344c 639 dma_addr_t prp_dma;
eca18b23 640 int nprps, i;
ff22b54f 641
6c3c05b0 642 length -= (NVME_CTRL_PAGE_SIZE - offset);
5228b328
JS		 643 if (length <= 0) {
644 iod->first_dma = 0;
a7a7cbe3 645 goto done;
5228b328 646 }
ff22b54f 647
6c3c05b0 648 dma_len -= (NVME_CTRL_PAGE_SIZE - offset);
ff22b54f 649 if (dma_len) {
6c3c05b0 650 dma_addr += (NVME_CTRL_PAGE_SIZE - offset);
ff22b54f
MW		 651 } else {
652 sg = sg_next(sg);
653 dma_addr = sg_dma_address(sg);
654 dma_len = sg_dma_len(sg);
655 }
656
6c3c05b0 657 if (length <= NVME_CTRL_PAGE_SIZE) {
edd10d33 658 iod->first_dma = dma_addr;
a7a7cbe3 659 goto done;
e025344c
SMM		 660 }
661
6c3c05b0 662 nprps = DIV_ROUND_UP(length, NVME_CTRL_PAGE_SIZE);
99802a7a
MW		 663 if (nprps <= (256 / 8)) {
664 pool = dev->prp_small_pool;
eca18b23 665 iod->npages = 0;
99802a7a
MW		 666 } else {
667 pool = dev->prp_page_pool;
eca18b23 668 iod->npages = 1;
99802a7a
MW		 669 }
670
69d2b571 671 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
b77954cb 672 if (!prp_list) {
edd10d33 673 iod->first_dma = dma_addr;
eca18b23 674 iod->npages = -1;
86eea289 675 return BLK_STS_RESOURCE;
b77954cb 676 }
eca18b23
MW		 677 list[0] = prp_list;
678 iod->first_dma = prp_dma;
e025344c
SMM		 679 i = 0;
680 for (;;) {
6c3c05b0 681 if (i == NVME_CTRL_PAGE_SIZE >> 3) {
e025344c 682 __le64 *old_prp_list = prp_list;
69d2b571 683 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
eca18b23 684 if (!prp_list)
fa073216 685 goto free_prps;
eca18b23 686 list[iod->npages++] = prp_list;
7523d834
MW		 687 prp_list[0] = old_prp_list[i - 1];
688 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
689 i = 1;
e025344c
SMM		 690 }
691 prp_list[i++] = cpu_to_le64(dma_addr);
6c3c05b0
CK		 692 dma_len -= NVME_CTRL_PAGE_SIZE;
693 dma_addr += NVME_CTRL_PAGE_SIZE;
694 length -= NVME_CTRL_PAGE_SIZE;
e025344c
SMM		 695 if (length <= 0)
696 break;
697 if (dma_len > 0)
698 continue;
86eea289
KB		 699 if (unlikely(dma_len < 0))
700 goto bad_sgl;
e025344c
SMM		 701 sg = sg_next(sg);
702 dma_addr = sg_dma_address(sg);
703 dma_len = sg_dma_len(sg);
ff22b54f 704 }
a7a7cbe3
CK		 705done:
706 cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
707 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
86eea289 708 return BLK_STS_OK;
fa073216
CH		 709free_prps:
710 nvme_free_prps(dev, req);
711 return BLK_STS_RESOURCE;
712bad_sgl:
d0877473
KB		 713 WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents),
714 "Invalid SGL for payload:%d nents:%d\n",
715 blk_rq_payload_bytes(req), iod->nents);
86eea289 716 return BLK_STS_IOERR;
ff22b54f
MW		 717}
718
a7a7cbe3
CK		 719static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
720 struct scatterlist *sg)
721{
722 sge->addr = cpu_to_le64(sg_dma_address(sg));
723 sge->length = cpu_to_le32(sg_dma_len(sg));
724 sge->type = NVME_SGL_FMT_DATA_DESC << 4;
725}
726
727static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
728 dma_addr_t dma_addr, int entries)
729{
730 sge->addr = cpu_to_le64(dma_addr);
731 if (entries < SGES_PER_PAGE) {
732 sge->length = cpu_to_le32(entries * sizeof(*sge));
733 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
734 } else {
735 sge->length = cpu_to_le32(PAGE_SIZE);
736 sge->type = NVME_SGL_FMT_SEG_DESC << 4;
737 }
738}
739
740static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
b0f2853b 741 struct request *req, struct nvme_rw_command *cmd, int entries)
a7a7cbe3
CK		 742{
743 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3
CK		 744 struct dma_pool *pool;
745 struct nvme_sgl_desc *sg_list;
746 struct scatterlist *sg = iod->sg;
a7a7cbe3 747 dma_addr_t sgl_dma;
b0f2853b 748 int i = 0;
a7a7cbe3 749
a7a7cbe3
CK		 750 /* setting the transfer type as SGL */
751 cmd->flags = NVME_CMD_SGL_METABUF;
752
b0f2853b 753 if (entries == 1) {
a7a7cbe3
CK		 754 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
755 return BLK_STS_OK;
756 }
757
758 if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
759 pool = dev->prp_small_pool;
760 iod->npages = 0;
761 } else {
762 pool = dev->prp_page_pool;
763 iod->npages = 1;
764 }
765
766 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
767 if (!sg_list) {
768 iod->npages = -1;
769 return BLK_STS_RESOURCE;
770 }
771
772 nvme_pci_iod_list(req)[0] = sg_list;
773 iod->first_dma = sgl_dma;
774
775 nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
776
777 do {
778 if (i == SGES_PER_PAGE) {
779 struct nvme_sgl_desc *old_sg_desc = sg_list;
780 struct nvme_sgl_desc *link = &old_sg_desc[i - 1];
781
782 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
783 if (!sg_list)
fa073216 784 goto free_sgls;
a7a7cbe3
CK		 785
786 i = 0;
787 nvme_pci_iod_list(req)[iod->npages++] = sg_list;
788 sg_list[i++] = *link;
789 nvme_pci_sgl_set_seg(link, sgl_dma, entries);
790 }
791
792 nvme_pci_sgl_set_data(&sg_list[i++], sg);
a7a7cbe3 793 sg = sg_next(sg);
b0f2853b 794 } while (--entries > 0);
a7a7cbe3 795
a7a7cbe3 796 return BLK_STS_OK;
fa073216
CH		 797free_sgls:
798 nvme_free_sgls(dev, req);
799 return BLK_STS_RESOURCE;
a7a7cbe3
CK		 800}
801
dff824b2
CH		 802static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev,
803 struct request *req, struct nvme_rw_command *cmnd,
804 struct bio_vec *bv)
805{
806 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
6c3c05b0
CK		 807 unsigned int offset = bv->bv_offset & (NVME_CTRL_PAGE_SIZE - 1);
808 unsigned int first_prp_len = NVME_CTRL_PAGE_SIZE - offset;
dff824b2
CH		 809
810 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
811 if (dma_mapping_error(dev->dev, iod->first_dma))
812 return BLK_STS_RESOURCE;
813 iod->dma_len = bv->bv_len;
814
815 cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma);
816 if (bv->bv_len > first_prp_len)
817 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len);
359c1f88 818 return BLK_STS_OK;
dff824b2
CH		 819}
820
29791057
CH		 821static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev,
822 struct request *req, struct nvme_rw_command *cmnd,
823 struct bio_vec *bv)
824{
825 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
826
827 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
828 if (dma_mapping_error(dev->dev, iod->first_dma))
829 return BLK_STS_RESOURCE;
830 iod->dma_len = bv->bv_len;
831
049bf372 832 cmnd->flags = NVME_CMD_SGL_METABUF;
29791057
CH		 833 cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma);
834 cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len);
835 cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4;
359c1f88 836 return BLK_STS_OK;
29791057
CH		 837}
838
fc17b653 839static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
b131c61d 840 struct nvme_command *cmnd)
d29ec824 841{
f4800d6d 842 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
70479b71 843 blk_status_t ret = BLK_STS_RESOURCE;
b0f2853b 844 int nr_mapped;
d29ec824 845
dff824b2
CH		 846 if (blk_rq_nr_phys_segments(req) == 1) {
847 struct bio_vec bv = req_bvec(req);
848
849 if (!is_pci_p2pdma_page(bv.bv_page)) {
6c3c05b0 850 if (bv.bv_offset + bv.bv_len <= NVME_CTRL_PAGE_SIZE * 2)
dff824b2
CH		 851 return nvme_setup_prp_simple(dev, req,
852 &cmnd->rw, &bv);
29791057 853
e51183be 854 if (iod->nvmeq->qid && sgl_threshold &&
253a0b76 855 nvme_ctrl_sgl_supported(&dev->ctrl))
29791057
CH		 856 return nvme_setup_sgl_simple(dev, req,
857 &cmnd->rw, &bv);
dff824b2
CH		 858 }
859 }
860
861 iod->dma_len = 0;
d43f1ccf
CH		 862 iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC);
863 if (!iod->sg)
864 return BLK_STS_RESOURCE;
f9d03f96 865 sg_init_table(iod->sg, blk_rq_nr_phys_segments(req));
70479b71 866 iod->nents = blk_rq_map_sg(req->q, req, iod->sg);
ba1ca37e 867 if (!iod->nents)
fa073216 868 goto out_free_sg;
d29ec824 869
e0596ab2 870 if (is_pci_p2pdma_page(sg_page(iod->sg)))
2b9f4bb2
LG		 871 nr_mapped = pci_p2pdma_map_sg_attrs(dev->dev, iod->sg,
872 iod->nents, rq_dma_dir(req), DMA_ATTR_NO_WARN);
e0596ab2
LG		 873 else
874 nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents,
70479b71 875 rq_dma_dir(req), DMA_ATTR_NO_WARN);
b0f2853b 876 if (!nr_mapped)
fa073216 877 goto out_free_sg;
d29ec824 878
70479b71 879 iod->use_sgl = nvme_pci_use_sgls(dev, req);
955b1b5a 880 if (iod->use_sgl)
b0f2853b 881 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped);
a7a7cbe3
CK		 882 else
883 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
86eea289 884 if (ret != BLK_STS_OK)
fa073216
CH		 885 goto out_unmap_sg;
886 return BLK_STS_OK;
887
888out_unmap_sg:
889 nvme_unmap_sg(dev, req);
890out_free_sg:
891 mempool_free(iod->sg, dev->iod_mempool);
4aedb705
CH		 892 return ret;
893}
3045c0d0 894
4aedb705
CH		 895static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req,
896 struct nvme_command *cmnd)
897{
898 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
00df5cb4 899
4aedb705
CH		 900 iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req),
901 rq_dma_dir(req), 0);
902 if (dma_mapping_error(dev->dev, iod->meta_dma))
903 return BLK_STS_IOERR;
904 cmnd->rw.metadata = cpu_to_le64(iod->meta_dma);
359c1f88 905 return BLK_STS_OK;
00df5cb4
MW		 906}
907
d29ec824
CH		 908/*
909 * NOTE: ns is NULL when called on the admin queue.
910 */
fc17b653 911static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
a4aea562 912 const struct blk_mq_queue_data *bd)
edd10d33 913{
a4aea562
MB		 914 struct nvme_ns *ns = hctx->queue->queuedata;
915 struct nvme_queue *nvmeq = hctx->driver_data;
d29ec824 916 struct nvme_dev *dev = nvmeq->dev;
a4aea562 917 struct request *req = bd->rq;
9b048119 918 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
af7fae85 919 struct nvme_command *cmnd = &iod->cmd;
ebe6d874 920 blk_status_t ret;
e1e5e564 921
9b048119
CH		 922 iod->aborted = 0;
923 iod->npages = -1;
924 iod->nents = 0;
925
d1f06f4a
JA		 926 /*
927 * We should not need to do this, but we're still using this to
928 * ensure we can drain requests on a dying queue.
929 */
4e224106 930 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
d1f06f4a
JA		 931 return BLK_STS_IOERR;
932
d4060d2b
TC		 933 if (!nvme_check_ready(&dev->ctrl, req, true))
934 return nvme_fail_nonready_command(&dev->ctrl, req);
935
f4b9e6c9 936 ret = nvme_setup_cmd(ns, req);
fc17b653 937 if (ret)
f4800d6d 938 return ret;
a4aea562 939
fc17b653 940 if (blk_rq_nr_phys_segments(req)) {
af7fae85 941 ret = nvme_map_data(dev, req, cmnd);
fc17b653 942 if (ret)
9b048119 943 goto out_free_cmd;
fc17b653 944 }
a4aea562 945
4aedb705 946 if (blk_integrity_rq(req)) {
af7fae85 947 ret = nvme_map_metadata(dev, req, cmnd);
4aedb705
CH		 948 if (ret)
949 goto out_unmap_data;
950 }
951
aae239e1 952 blk_mq_start_request(req);
af7fae85 953 nvme_submit_cmd(nvmeq, cmnd, bd->last);
fc17b653 954 return BLK_STS_OK;
4aedb705
CH		 955out_unmap_data:
956 nvme_unmap_data(dev, req);
f9d03f96
CH		 957out_free_cmd:
958 nvme_cleanup_cmd(req);
ba1ca37e 959 return ret;
b60503ba 960}
e1e5e564 961
77f02a7a 962static void nvme_pci_complete_rq(struct request *req)
eee417b0 963{
f4800d6d 964 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
4aedb705 965 struct nvme_dev *dev = iod->nvmeq->dev;
a4aea562 966
4aedb705
CH		 967 if (blk_integrity_rq(req))
968 dma_unmap_page(dev->dev, iod->meta_dma,
969 rq_integrity_vec(req)->bv_len, rq_data_dir(req));
b15c592d 970 if (blk_rq_nr_phys_segments(req))
4aedb705 971 nvme_unmap_data(dev, req);
77f02a7a 972 nvme_complete_rq(req);
b60503ba
MW		 973}
974
d783e0bd 975/* We read the CQE phase first to check if the rest of the entry is valid */
750dde44 976static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq)
d783e0bd 977{
74943d45
KB		 978 struct nvme_completion *hcqe = &nvmeq->cqes[nvmeq->cq_head];
979
980 return (le16_to_cpu(READ_ONCE(hcqe->status)) & 1) == nvmeq->cq_phase;
d783e0bd
MR		 981}
982
eb281c82 983static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
b60503ba 984{
eb281c82 985 u16 head = nvmeq->cq_head;
adf68f21 986
397c699f
KB		 987 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
988 nvmeq->dbbuf_cq_ei))
989 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
eb281c82 990}
aae239e1 991
cfa27356
CH		 992static inline struct blk_mq_tags *nvme_queue_tagset(struct nvme_queue *nvmeq)
993{
994 if (!nvmeq->qid)
995 return nvmeq->dev->admin_tagset.tags[0];
996 return nvmeq->dev->tagset.tags[nvmeq->qid - 1];
997}
998
5cb525c8 999static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx)
83a12fb7 1000{
74943d45 1001 struct nvme_completion *cqe = &nvmeq->cqes[idx];
62df8016 1002 __u16 command_id = READ_ONCE(cqe->command_id);
83a12fb7 1003 struct request *req;
adf68f21 1004
83a12fb7
SG		 1005 /*
1006 * AEN requests are special as they don't time out and can
1007 * survive any kind of queue freeze and often don't respond to
1008 * aborts. We don't even bother to allocate a struct request
1009 * for them but rather special case them here.
1010 */
62df8016 1011 if (unlikely(nvme_is_aen_req(nvmeq->qid, command_id))) {
83a12fb7
SG		 1012 nvme_complete_async_event(&nvmeq->dev->ctrl,
1013 cqe->status, &cqe->result);
a0fa9647 1014 return;
83a12fb7 1015 }
b60503ba 1016
62df8016 1017 req = blk_mq_tag_to_rq(nvme_queue_tagset(nvmeq), command_id);
50b7c243
XT		 1018 if (unlikely(!req)) {
1019 dev_warn(nvmeq->dev->ctrl.device,
1020 "invalid id %d completed on queue %d\n",
62df8016 1021 command_id, le16_to_cpu(cqe->sq_id));
50b7c243
XT		 1022 return;
1023 }
1024
604c01d5 1025 trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail);
2eb81a33 1026 if (!nvme_try_complete_req(req, cqe->status, cqe->result))
ff029451 1027 nvme_pci_complete_rq(req);
83a12fb7 1028}
b60503ba 1029
5cb525c8
JA		 1030static inline void nvme_update_cq_head(struct nvme_queue *nvmeq)
1031{
a0aac973 1032 u32 tmp = nvmeq->cq_head + 1;
a8de6639
AD		 1033
1034 if (tmp == nvmeq->q_depth) {
5cb525c8 1035 nvmeq->cq_head = 0;
e2a366a4 1036 nvmeq->cq_phase ^= 1;
a8de6639
AD		 1037 } else {
1038 nvmeq->cq_head = tmp;
b60503ba 1039 }
a0fa9647
JA		 1040}
1041
324b494c 1042static inline int nvme_process_cq(struct nvme_queue *nvmeq)
a0fa9647 1043{
1052b8ac 1044 int found = 0;
b60503ba 1045
1052b8ac 1046 while (nvme_cqe_pending(nvmeq)) {
bf392a5d 1047 found++;
b69e2ef2
KB		 1048 /*
1049 * load-load control dependency between phase and the rest of
1050 * the cqe requires a full read memory barrier
1051 */
1052 dma_rmb();
324b494c 1053 nvme_handle_cqe(nvmeq, nvmeq->cq_head);
5cb525c8 1054 nvme_update_cq_head(nvmeq);
920d13a8 1055 }
eb281c82 1056
324b494c 1057 if (found)
920d13a8 1058 nvme_ring_cq_doorbell(nvmeq);
5cb525c8 1059 return found;
b60503ba
MW		 1060}
1061
1062static irqreturn_t nvme_irq(int irq, void *data)
58ffacb5 1063{
58ffacb5 1064 struct nvme_queue *nvmeq = data;
5cb525c8 1065
324b494c 1066 if (nvme_process_cq(nvmeq))
05fae499
CK		 1067 return IRQ_HANDLED;
1068 return IRQ_NONE;
58ffacb5
MW		 1069}
1070
1071static irqreturn_t nvme_irq_check(int irq, void *data)
1072{
1073 struct nvme_queue *nvmeq = data;
4e523547 1074
750dde44 1075 if (nvme_cqe_pending(nvmeq))
d783e0bd
MR		 1076 return IRQ_WAKE_THREAD;
1077 return IRQ_NONE;
58ffacb5
MW		 1078}
1079
0b2a8a9f 1080/*
fa059b85 1081 * Poll for completions for any interrupt driven queue
0b2a8a9f
CH		 1082 * Can be called from any context.
1083 */
fa059b85 1084static void nvme_poll_irqdisable(struct nvme_queue *nvmeq)
a0fa9647 1085{
3a7afd8e 1086 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
a0fa9647 1087
fa059b85 1088 WARN_ON_ONCE(test_bit(NVMEQ_POLLED, &nvmeq->flags));
442e19b7 1089
fa059b85
KB		 1090 disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1091 nvme_process_cq(nvmeq);
1092 enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
a0fa9647
JA		 1093}
1094
9743139c 1095static int nvme_poll(struct blk_mq_hw_ctx *hctx)
dabcefab
JA		 1096{
1097 struct nvme_queue *nvmeq = hctx->driver_data;
dabcefab
JA		 1098 bool found;
1099
1100 if (!nvme_cqe_pending(nvmeq))
1101 return 0;
1102
3a7afd8e 1103 spin_lock(&nvmeq->cq_poll_lock);
324b494c 1104 found = nvme_process_cq(nvmeq);
3a7afd8e 1105 spin_unlock(&nvmeq->cq_poll_lock);
dabcefab 1106
dabcefab
JA		 1107 return found;
1108}
1109
ad22c355 1110static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
b60503ba 1111{
f866fc42 1112 struct nvme_dev *dev = to_nvme_dev(ctrl);
147b27e4 1113 struct nvme_queue *nvmeq = &dev->queues[0];
f66e2804 1114 struct nvme_command c = { };
b60503ba 1115
a4aea562 1116 c.common.opcode = nvme_admin_async_event;
ad22c355 1117 c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
04f3eafd 1118 nvme_submit_cmd(nvmeq, &c, true);
f705f837
CH		 1119}
1120
b60503ba 1121static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
f705f837 1122{
f66e2804 1123 struct nvme_command c = { };
b60503ba 1124
b60503ba
MW		 1125 c.delete_queue.opcode = opcode;
1126 c.delete_queue.qid = cpu_to_le16(id);
1127
1c63dc66 1128 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1129}
1130
b60503ba 1131static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
a8e3e0bb 1132 struct nvme_queue *nvmeq, s16 vector)
b60503ba 1133{
f66e2804 1134 struct nvme_command c = { };
4b04cc6a
JA		 1135 int flags = NVME_QUEUE_PHYS_CONTIG;
1136
7c349dde 1137 if (!test_bit(NVMEQ_POLLED, &nvmeq->flags))
4b04cc6a 1138 flags |= NVME_CQ_IRQ_ENABLED;
b60503ba 1139
d29ec824 1140 /*
16772ae6 1141 * Note: we (ab)use the fact that the prp fields survive if no data
d29ec824
CH		 1142 * is attached to the request.
1143 */
b60503ba
MW		 1144 c.create_cq.opcode = nvme_admin_create_cq;
1145 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1146 c.create_cq.cqid = cpu_to_le16(qid);
1147 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1148 c.create_cq.cq_flags = cpu_to_le16(flags);
7c349dde 1149 c.create_cq.irq_vector = cpu_to_le16(vector);
b60503ba 1150
1c63dc66 1151 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1152}
1153
1154static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1155 struct nvme_queue *nvmeq)
1156{
9abd68ef 1157 struct nvme_ctrl *ctrl = &dev->ctrl;
f66e2804 1158 struct nvme_command c = { };
81c1cd98 1159 int flags = NVME_QUEUE_PHYS_CONTIG;
b60503ba 1160
9abd68ef
JA		 1161 /*
1162 * Some drives have a bug that auto-enables WRRU if MEDIUM isn't
1163 * set. Since URGENT priority is zeroes, it makes all queues
1164 * URGENT.
1165 */
1166 if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ)
1167 flags |= NVME_SQ_PRIO_MEDIUM;
1168
d29ec824 1169 /*
16772ae6 1170 * Note: we (ab)use the fact that the prp fields survive if no data
d29ec824
CH		 1171 * is attached to the request.
1172 */
b60503ba
MW		 1173 c.create_sq.opcode = nvme_admin_create_sq;
1174 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1175 c.create_sq.sqid = cpu_to_le16(qid);
1176 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1177 c.create_sq.sq_flags = cpu_to_le16(flags);
1178 c.create_sq.cqid = cpu_to_le16(qid);
1179
1c63dc66 1180 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1181}
1182
1183static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1184{
1185 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1186}
1187
1188static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1189{
1190 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1191}
1192
2a842aca 1193static void abort_endio(struct request *req, blk_status_t error)
bc5fc7e4 1194{
f4800d6d
CH		 1195 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1196 struct nvme_queue *nvmeq = iod->nvmeq;
e44ac588 1197
27fa9bc5
CH		 1198 dev_warn(nvmeq->dev->ctrl.device,
1199 "Abort status: 0x%x", nvme_req(req)->status);
e7a2a87d 1200 atomic_inc(&nvmeq->dev->ctrl.abort_limit);
e7a2a87d 1201 blk_mq_free_request(req);
bc5fc7e4
MW		 1202}
1203
b2a0eb1a
KB		 1204static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1205{
b2a0eb1a
KB		 1206 /* If true, indicates loss of adapter communication, possibly by a
1207 * NVMe Subsystem reset.
1208 */
1209 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1210
ad70062c
JW		 1211 /* If there is a reset/reinit ongoing, we shouldn't reset again. */
1212 switch (dev->ctrl.state) {
1213 case NVME_CTRL_RESETTING:
ad6a0a52 1214 case NVME_CTRL_CONNECTING:
b2a0eb1a 1215 return false;
ad70062c
JW		 1216 default:
1217 break;
1218 }
b2a0eb1a
KB		 1219
1220 /* We shouldn't reset unless the controller is on fatal error state
1221 * _or_ if we lost the communication with it.
1222 */
1223 if (!(csts & NVME_CSTS_CFS) && !nssro)
1224 return false;
1225
b2a0eb1a
KB		 1226 return true;
1227}
1228
1229static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1230{
1231 /* Read a config register to help see what died. */
1232 u16 pci_status;
1233 int result;
1234
1235 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1236 &pci_status);
1237 if (result == PCIBIOS_SUCCESSFUL)
1238 dev_warn(dev->ctrl.device,
1239 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1240 csts, pci_status);
1241 else
1242 dev_warn(dev->ctrl.device,
1243 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1244 csts, result);
1245}
1246
31c7c7d2 1247static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
c30341dc 1248{
f4800d6d
CH		 1249 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1250 struct nvme_queue *nvmeq = iod->nvmeq;
c30341dc 1251 struct nvme_dev *dev = nvmeq->dev;
a4aea562 1252 struct request *abort_req;
f66e2804 1253 struct nvme_command cmd = { };
b2a0eb1a
KB		 1254 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1255
651438bb
WX		 1256 /* If PCI error recovery process is happening, we cannot reset or
1257 * the recovery mechanism will surely fail.
1258 */
1259 mb();
1260 if (pci_channel_offline(to_pci_dev(dev->dev)))
1261 return BLK_EH_RESET_TIMER;
1262
b2a0eb1a
KB		 1263 /*
1264 * Reset immediately if the controller is failed
1265 */
1266 if (nvme_should_reset(dev, csts)) {
1267 nvme_warn_reset(dev, csts);
1268 nvme_dev_disable(dev, false);
d86c4d8e 1269 nvme_reset_ctrl(&dev->ctrl);
db8c48e4 1270 return BLK_EH_DONE;
b2a0eb1a 1271 }
c30341dc 1272
7776db1c
KB		 1273 /*
1274 * Did we miss an interrupt?
1275 */
fa059b85
KB		 1276 if (test_bit(NVMEQ_POLLED, &nvmeq->flags))
1277 nvme_poll(req->mq_hctx);
1278 else
1279 nvme_poll_irqdisable(nvmeq);
1280
bf392a5d 1281 if (blk_mq_request_completed(req)) {
7776db1c
KB		 1282 dev_warn(dev->ctrl.device,
1283 "I/O %d QID %d timeout, completion polled\n",
1284 req->tag, nvmeq->qid);
db8c48e4 1285 return BLK_EH_DONE;
7776db1c
KB		 1286 }
1287
31c7c7d2 1288 /*
fd634f41
CH		 1289 * Shutdown immediately if controller times out while starting. The
1290 * reset work will see the pci device disabled when it gets the forced
1291 * cancellation error. All outstanding requests are completed on
db8c48e4 1292 * shutdown, so we return BLK_EH_DONE.
fd634f41 1293 */
4244140d
KB		 1294 switch (dev->ctrl.state) {
1295 case NVME_CTRL_CONNECTING:
2036f726 1296 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
df561f66 1297 fallthrough;
2036f726 1298 case NVME_CTRL_DELETING:
b9cac43c 1299 dev_warn_ratelimited(dev->ctrl.device,
fd634f41
CH		 1300 "I/O %d QID %d timeout, disable controller\n",
1301 req->tag, nvmeq->qid);
27fa9bc5 1302 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
7ad92f65 1303 nvme_dev_disable(dev, true);
db8c48e4 1304 return BLK_EH_DONE;
39a9dd81
KB		 1305 case NVME_CTRL_RESETTING:
1306 return BLK_EH_RESET_TIMER;
4244140d
KB		 1307 default:
1308 break;
c30341dc
KB		 1309 }
1310
fd634f41 1311 /*
ee0d96d3
BW		 1312 * Shutdown the controller immediately and schedule a reset if the
1313 * command was already aborted once before and still hasn't been
1314 * returned to the driver, or if this is the admin queue.
31c7c7d2 1315 */
f4800d6d 1316 if (!nvmeq->qid || iod->aborted) {
1b3c47c1 1317 dev_warn(dev->ctrl.device,
e1569a16
KB		 1318 "I/O %d QID %d timeout, reset controller\n",
1319 req->tag, nvmeq->qid);
7ad92f65 1320 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
a5cdb68c 1321 nvme_dev_disable(dev, false);
d86c4d8e 1322 nvme_reset_ctrl(&dev->ctrl);
c30341dc 1323
db8c48e4 1324 return BLK_EH_DONE;
c30341dc 1325 }
c30341dc 1326
e7a2a87d 1327 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
6bf25d16 1328 atomic_inc(&dev->ctrl.abort_limit);
31c7c7d2 1329 return BLK_EH_RESET_TIMER;
6bf25d16 1330 }
7bf7d778 1331 iod->aborted = 1;
a4aea562 1332
c30341dc 1333 cmd.abort.opcode = nvme_admin_abort_cmd;
a4aea562 1334 cmd.abort.cid = req->tag;
c30341dc 1335 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
c30341dc 1336
1b3c47c1
SG		 1337 dev_warn(nvmeq->dev->ctrl.device,
1338 "I/O %d QID %d timeout, aborting\n",
1339 req->tag, nvmeq->qid);
e7a2a87d
CH		 1340
1341 abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
39dfe844 1342 BLK_MQ_REQ_NOWAIT);
e7a2a87d
CH		 1343 if (IS_ERR(abort_req)) {
1344 atomic_inc(&dev->ctrl.abort_limit);
1345 return BLK_EH_RESET_TIMER;
1346 }
1347
e7a2a87d 1348 abort_req->end_io_data = NULL;
8eeed0b5 1349 blk_execute_rq_nowait(NULL, abort_req, 0, abort_endio);
c30341dc 1350
31c7c7d2
CH		 1351 /*
1352 * The aborted req will be completed on receiving the abort req.
1353 * We enable the timer again. If hit twice, it'll cause a device reset,
1354 * as the device then is in a faulty state.
1355 */
1356 return BLK_EH_RESET_TIMER;
c30341dc
KB		 1357}
1358
a4aea562
MB		 1359static void nvme_free_queue(struct nvme_queue *nvmeq)
1360{
8a1d09a6 1361 dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq),
9e866774 1362 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
63223078
CH		 1363 if (!nvmeq->sq_cmds)
1364 return;
0f238ff5 1365
63223078 1366 if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) {
88a041f4 1367 pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev),
8a1d09a6 1368 nvmeq->sq_cmds, SQ_SIZE(nvmeq));
63223078 1369 } else {
8a1d09a6 1370 dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq),
63223078 1371 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
0f238ff5 1372 }
9e866774
MW		 1373}
1374
a1a5ef99 1375static void nvme_free_queues(struct nvme_dev *dev, int lowest)
22404274
KB		 1376{
1377 int i;
1378
d858e5f0 1379 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
d858e5f0 1380 dev->ctrl.queue_count--;
147b27e4 1381 nvme_free_queue(&dev->queues[i]);
121c7ad4 1382 }
22404274
KB		 1383}
1384
4d115420
KB		 1385/**
1386 * nvme_suspend_queue - put queue into suspended state
40581d1a 1387 * @nvmeq: queue to suspend
4d115420
KB		 1388 */
1389static int nvme_suspend_queue(struct nvme_queue *nvmeq)
b60503ba 1390{
4e224106 1391 if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags))
2b25d981 1392 return 1;
a09115b2 1393
4e224106 1394 /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */
d1f06f4a 1395 mb();
a09115b2 1396
4e224106 1397 nvmeq->dev->online_queues--;
1c63dc66 1398 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
c81545f9 1399 blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q);
7c349dde
KB		 1400 if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags))
1401 pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq);
4d115420
KB		 1402 return 0;
1403}
b60503ba 1404
8fae268b
KB		 1405static void nvme_suspend_io_queues(struct nvme_dev *dev)
1406{
1407 int i;
1408
1409 for (i = dev->ctrl.queue_count - 1; i > 0; i--)
1410 nvme_suspend_queue(&dev->queues[i]);
1411}
1412
a5cdb68c 1413static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
4d115420 1414{
147b27e4 1415 struct nvme_queue *nvmeq = &dev->queues[0];
4d115420 1416
a5cdb68c
KB		 1417 if (shutdown)
1418 nvme_shutdown_ctrl(&dev->ctrl);
1419 else
b5b05048 1420 nvme_disable_ctrl(&dev->ctrl);
07836e65 1421
bf392a5d 1422 nvme_poll_irqdisable(nvmeq);
b60503ba
MW		 1423}
1424
fa46c6fb
KB		 1425/*
1426 * Called only on a device that has been disabled and after all other threads
9210c075
DZ		 1427 * that can check this device's completion queues have synced, except
1428 * nvme_poll(). This is the last chance for the driver to see a natural
1429 * completion before nvme_cancel_request() terminates all incomplete requests.
fa46c6fb
KB		 1430 */
1431static void nvme_reap_pending_cqes(struct nvme_dev *dev)
1432{
fa46c6fb
KB		 1433 int i;
1434
9210c075
DZ		 1435 for (i = dev->ctrl.queue_count - 1; i > 0; i--) {
1436 spin_lock(&dev->queues[i].cq_poll_lock);
324b494c 1437 nvme_process_cq(&dev->queues[i]);
9210c075
DZ		 1438 spin_unlock(&dev->queues[i].cq_poll_lock);
1439 }
fa46c6fb
KB		 1440}
1441
8ffaadf7
JD		 1442static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1443 int entry_size)
1444{
1445 int q_depth = dev->q_depth;
5fd4ce1b 1446 unsigned q_size_aligned = roundup(q_depth * entry_size,
6c3c05b0 1447 NVME_CTRL_PAGE_SIZE);
8ffaadf7
JD		 1448
1449 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
c45f5c99 1450 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
4e523547 1451
6c3c05b0 1452 mem_per_q = round_down(mem_per_q, NVME_CTRL_PAGE_SIZE);
c45f5c99 1453 q_depth = div_u64(mem_per_q, entry_size);
8ffaadf7
JD		 1454
1455 /*
1456 * Ensure the reduced q_depth is above some threshold where it
1457 * would be better to map queues in system memory with the
1458 * original depth
1459 */
1460 if (q_depth < 64)
1461 return -ENOMEM;
1462 }
1463
1464 return q_depth;
1465}
1466
1467static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
8a1d09a6 1468 int qid)
8ffaadf7 1469{
0f238ff5
LG		 1470 struct pci_dev *pdev = to_pci_dev(dev->dev);
1471
1472 if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
8a1d09a6 1473 nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq));
bfac8e9f
AM		 1474 if (nvmeq->sq_cmds) {
1475 nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev,
1476 nvmeq->sq_cmds);
1477 if (nvmeq->sq_dma_addr) {
1478 set_bit(NVMEQ_SQ_CMB, &nvmeq->flags);
1479 return 0;
1480 }
1481
8a1d09a6 1482 pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq));
63223078 1483 }
0f238ff5 1484 }
8ffaadf7 1485
8a1d09a6 1486 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq),
63223078 1487 &nvmeq->sq_dma_addr, GFP_KERNEL);
815c6704
KB		 1488 if (!nvmeq->sq_cmds)
1489 return -ENOMEM;
8ffaadf7
JD		 1490 return 0;
1491}
1492
a6ff7262 1493static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
b60503ba 1494{
147b27e4 1495 struct nvme_queue *nvmeq = &dev->queues[qid];
b60503ba 1496
62314e40
KB		 1497 if (dev->ctrl.queue_count > qid)
1498 return 0;
b60503ba 1499
c1e0cc7e 1500 nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES;
8a1d09a6
BH		 1501 nvmeq->q_depth = depth;
1502 nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq),
750afb08 1503 &nvmeq->cq_dma_addr, GFP_KERNEL);
b60503ba
MW		 1504 if (!nvmeq->cqes)
1505 goto free_nvmeq;
b60503ba 1506
8a1d09a6 1507 if (nvme_alloc_sq_cmds(dev, nvmeq, qid))
b60503ba
MW		 1508 goto free_cqdma;
1509
091b6092 1510 nvmeq->dev = dev;
1ab0cd69 1511 spin_lock_init(&nvmeq->sq_lock);
3a7afd8e 1512 spin_lock_init(&nvmeq->cq_poll_lock);
b60503ba 1513 nvmeq->cq_head = 0;
82123460 1514 nvmeq->cq_phase = 1;
b80d5ccc 1515 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
c30341dc 1516 nvmeq->qid = qid;
d858e5f0 1517 dev->ctrl.queue_count++;
36a7e993 1518
147b27e4 1519 return 0;
b60503ba
MW		 1520
1521 free_cqdma:
8a1d09a6
BH		 1522 dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes,
1523 nvmeq->cq_dma_addr);
b60503ba 1524 free_nvmeq:
147b27e4 1525 return -ENOMEM;
b60503ba
MW		 1526}
1527
dca51e78 1528static int queue_request_irq(struct nvme_queue *nvmeq)
3001082c 1529{
0ff199cb
CH		 1530 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1531 int nr = nvmeq->dev->ctrl.instance;
1532
1533 if (use_threaded_interrupts) {
1534 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1535 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1536 } else {
1537 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1538 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1539 }
3001082c
MW		 1540}
1541
22404274 1542static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
b60503ba 1543{
22404274 1544 struct nvme_dev *dev = nvmeq->dev;
b60503ba 1545
22404274 1546 nvmeq->sq_tail = 0;
38210800 1547 nvmeq->last_sq_tail = 0;
22404274
KB		 1548 nvmeq->cq_head = 0;
1549 nvmeq->cq_phase = 1;
b80d5ccc 1550 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
8a1d09a6 1551 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq));
f9f38e33 1552 nvme_dbbuf_init(dev, nvmeq, qid);
42f61420 1553 dev->online_queues++;
3a7afd8e 1554 wmb(); /* ensure the first interrupt sees the initialization */
22404274
KB		 1555}
1556
4b04cc6a 1557static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled)
22404274
KB		 1558{
1559 struct nvme_dev *dev = nvmeq->dev;
1560 int result;
7c349dde 1561 u16 vector = 0;
3f85d50b 1562
d1ed6aa1
CH		 1563 clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
1564
22b55601
KB		 1565 /*
1566 * A queue's vector matches the queue identifier unless the controller
1567 * has only one vector available.
1568 */
4b04cc6a
JA		 1569 if (!polled)
1570 vector = dev->num_vecs == 1 ? 0 : qid;
1571 else
7c349dde 1572 set_bit(NVMEQ_POLLED, &nvmeq->flags);
4b04cc6a 1573
a8e3e0bb 1574 result = adapter_alloc_cq(dev, qid, nvmeq, vector);
ded45505
KB		 1575 if (result)
1576 return result;
b60503ba
MW		 1577
1578 result = adapter_alloc_sq(dev, qid, nvmeq);
1579 if (result < 0)
ded45505 1580 return result;
c80b36cd 1581 if (result)
b60503ba
MW		 1582 goto release_cq;
1583
a8e3e0bb 1584 nvmeq->cq_vector = vector;
161b8be2 1585 nvme_init_queue(nvmeq, qid);
4b04cc6a 1586
7c349dde 1587 if (!polled) {
4b04cc6a
JA		 1588 result = queue_request_irq(nvmeq);
1589 if (result < 0)
1590 goto release_sq;
1591 }
b60503ba 1592
4e224106 1593 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
22404274 1594 return result;
b60503ba 1595
a8e3e0bb 1596release_sq:
f25a2dfc 1597 dev->online_queues--;
b60503ba 1598 adapter_delete_sq(dev, qid);
a8e3e0bb 1599release_cq:
b60503ba 1600 adapter_delete_cq(dev, qid);
22404274 1601 return result;
b60503ba
MW		 1602}
1603
f363b089 1604static const struct blk_mq_ops nvme_mq_admin_ops = {
d29ec824 1605 .queue_rq = nvme_queue_rq,
77f02a7a 1606 .complete = nvme_pci_complete_rq,
a4aea562 1607 .init_hctx = nvme_admin_init_hctx,
0350815a 1608 .init_request = nvme_init_request,
a4aea562
MB		 1609 .timeout = nvme_timeout,
1610};
1611
f363b089 1612static const struct blk_mq_ops nvme_mq_ops = {
376f7ef8
CH		 1613 .queue_rq = nvme_queue_rq,
1614 .complete = nvme_pci_complete_rq,
1615 .commit_rqs = nvme_commit_rqs,
1616 .init_hctx = nvme_init_hctx,
1617 .init_request = nvme_init_request,
1618 .map_queues = nvme_pci_map_queues,
1619 .timeout = nvme_timeout,
1620 .poll = nvme_poll,
dabcefab
JA		 1621};
1622
ea191d2f
KB		 1623static void nvme_dev_remove_admin(struct nvme_dev *dev)
1624{
1c63dc66 1625 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
69d9a99c
KB		 1626 /*
1627 * If the controller was reset during removal, it's possible
1628 * user requests may be waiting on a stopped queue. Start the
1629 * queue to flush these to completion.
1630 */
c81545f9 1631 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1c63dc66 1632 blk_cleanup_queue(dev->ctrl.admin_q);
ea191d2f
KB		 1633 blk_mq_free_tag_set(&dev->admin_tagset);
1634 }
1635}
1636
a4aea562
MB		 1637static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1638{
1c63dc66 1639 if (!dev->ctrl.admin_q) {
a4aea562
MB		 1640 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1641 dev->admin_tagset.nr_hw_queues = 1;
e3e9d50c 1642
38dabe21 1643 dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH;
dc96f938 1644 dev->admin_tagset.timeout = NVME_ADMIN_TIMEOUT;
d4ec47f1 1645 dev->admin_tagset.numa_node = dev->ctrl.numa_node;
d43f1ccf 1646 dev->admin_tagset.cmd_size = sizeof(struct nvme_iod);
d3484991 1647 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED;
a4aea562
MB		 1648 dev->admin_tagset.driver_data = dev;
1649
1650 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1651 return -ENOMEM;
34b6c231 1652 dev->ctrl.admin_tagset = &dev->admin_tagset;
a4aea562 1653
1c63dc66
CH		 1654 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1655 if (IS_ERR(dev->ctrl.admin_q)) {
a4aea562
MB		 1656 blk_mq_free_tag_set(&dev->admin_tagset);
1657 return -ENOMEM;
1658 }
1c63dc66 1659 if (!blk_get_queue(dev->ctrl.admin_q)) {
ea191d2f 1660 nvme_dev_remove_admin(dev);
1c63dc66 1661 dev->ctrl.admin_q = NULL;
ea191d2f
KB		 1662 return -ENODEV;
1663 }
0fb59cbc 1664 } else
c81545f9 1665 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
a4aea562
MB		 1666
1667 return 0;
1668}
1669
97f6ef64
XY		 1670static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1671{
1672 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1673}
1674
1675static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1676{
1677 struct pci_dev *pdev = to_pci_dev(dev->dev);
1678
1679 if (size <= dev->bar_mapped_size)
1680 return 0;
1681 if (size > pci_resource_len(pdev, 0))
1682 return -ENOMEM;
1683 if (dev->bar)
1684 iounmap(dev->bar);
1685 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1686 if (!dev->bar) {
1687 dev->bar_mapped_size = 0;
1688 return -ENOMEM;
1689 }
1690 dev->bar_mapped_size = size;
1691 dev->dbs = dev->bar + NVME_REG_DBS;
1692
1693 return 0;
1694}
1695
01ad0990 1696static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
b60503ba 1697{
ba47e386 1698 int result;
b60503ba
MW		 1699 u32 aqa;
1700 struct nvme_queue *nvmeq;
1701
97f6ef64
XY		 1702 result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1703 if (result < 0)
1704 return result;
1705
8ef2074d 1706 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
20d0dfe6 1707 NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
dfbac8c7 1708
7a67cbea
CH		 1709 if (dev->subsystem &&
1710 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1711 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
dfbac8c7 1712
b5b05048 1713 result = nvme_disable_ctrl(&dev->ctrl);
ba47e386
MW		 1714 if (result < 0)
1715 return result;
b60503ba 1716
a6ff7262 1717 result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
147b27e4
SG		 1718 if (result)
1719 return result;
b60503ba 1720
635333e4
MG		 1721 dev->ctrl.numa_node = dev_to_node(dev->dev);
1722
147b27e4 1723 nvmeq = &dev->queues[0];
b60503ba
MW		 1724 aqa = nvmeq->q_depth - 1;
1725 aqa |= aqa << 16;
1726
7a67cbea
CH		 1727 writel(aqa, dev->bar + NVME_REG_AQA);
1728 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1729 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
b60503ba 1730
c0f2f45b 1731 result = nvme_enable_ctrl(&dev->ctrl);
025c557a 1732 if (result)
d4875622 1733 return result;
a4aea562 1734
2b25d981 1735 nvmeq->cq_vector = 0;
161b8be2 1736 nvme_init_queue(nvmeq, 0);
dca51e78 1737 result = queue_request_irq(nvmeq);
758dd7fd 1738 if (result) {
7c349dde 1739 dev->online_queues--;
d4875622 1740 return result;
758dd7fd 1741 }
025c557a 1742
4e224106 1743 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
b60503ba
MW		 1744 return result;
1745}
1746
749941f2 1747static int nvme_create_io_queues(struct nvme_dev *dev)
42f61420 1748{
4b04cc6a 1749 unsigned i, max, rw_queues;
749941f2 1750 int ret = 0;
42f61420 1751
d858e5f0 1752 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
a6ff7262 1753 if (nvme_alloc_queue(dev, i, dev->q_depth)) {
749941f2 1754 ret = -ENOMEM;
42f61420 1755 break;
749941f2
CH		 1756 }
1757 }
42f61420 1758
d858e5f0 1759 max = min(dev->max_qid, dev->ctrl.queue_count - 1);
e20ba6e1
CH		 1760 if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) {
1761 rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] +
1762 dev->io_queues[HCTX_TYPE_READ];
4b04cc6a
JA		 1763 } else {
1764 rw_queues = max;
1765 }
1766
949928c1 1767 for (i = dev->online_queues; i <= max; i++) {
4b04cc6a
JA		 1768 bool polled = i > rw_queues;
1769
1770 ret = nvme_create_queue(&dev->queues[i], i, polled);
d4875622 1771 if (ret)
42f61420 1772 break;
27e8166c 1773 }
749941f2
CH		 1774
1775 /*
1776 * Ignore failing Create SQ/CQ commands, we can continue with less
8adb8c14
MI		 1777 * than the desired amount of queues, and even a controller without
1778 * I/O queues can still be used to issue admin commands. This might
749941f2
CH		 1779 * be useful to upgrade a buggy firmware for example.
1780 */
1781 return ret >= 0 ? 0 : ret;
b60503ba
MW		 1782}
1783
202021c1
SB		 1784static ssize_t nvme_cmb_show(struct device *dev,
1785 struct device_attribute *attr,
1786 char *buf)
1787{
1788 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
1789
c965809c 1790 return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n",
202021c1
SB		 1791 ndev->cmbloc, ndev->cmbsz);
1792}
1793static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL);
1794
88de4598 1795static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
8ffaadf7 1796{
88de4598
CH		 1797 u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
1798
1799 return 1ULL << (12 + 4 * szu);
1800}
1801
1802static u32 nvme_cmb_size(struct nvme_dev *dev)
1803{
1804 return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
1805}
1806
f65efd6d 1807static void nvme_map_cmb(struct nvme_dev *dev)
8ffaadf7 1808{
88de4598 1809 u64 size, offset;
8ffaadf7
JD		 1810 resource_size_t bar_size;
1811 struct pci_dev *pdev = to_pci_dev(dev->dev);
8969f1f8 1812 int bar;
8ffaadf7 1813
9fe5c59f
KB		 1814 if (dev->cmb_size)
1815 return;
1816
20d3bb92
KJ		 1817 if (NVME_CAP_CMBS(dev->ctrl.cap))
1818 writel(NVME_CMBMSC_CRE, dev->bar + NVME_REG_CMBMSC);
1819
7a67cbea 1820 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
f65efd6d
CH		 1821 if (!dev->cmbsz)
1822 return;
202021c1 1823 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
8ffaadf7 1824
88de4598
CH		 1825 size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
1826 offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
8969f1f8
CH		 1827 bar = NVME_CMB_BIR(dev->cmbloc);
1828 bar_size = pci_resource_len(pdev, bar);
8ffaadf7
JD		 1829
1830 if (offset > bar_size)
f65efd6d 1831 return;
8ffaadf7 1832
20d3bb92
KJ		 1833 /*
1834 * Tell the controller about the host side address mapping the CMB,
1835 * and enable CMB decoding for the NVMe 1.4+ scheme:
1836 */
1837 if (NVME_CAP_CMBS(dev->ctrl.cap)) {
1838 hi_lo_writeq(NVME_CMBMSC_CRE | NVME_CMBMSC_CMSE |
1839 (pci_bus_address(pdev, bar) + offset),
1840 dev->bar + NVME_REG_CMBMSC);
1841 }
1842
8ffaadf7
JD		 1843 /*
1844 * Controllers may support a CMB size larger than their BAR,
1845 * for example, due to being behind a bridge. Reduce the CMB to
1846 * the reported size of the BAR
1847 */
1848 if (size > bar_size - offset)
1849 size = bar_size - offset;
1850
0f238ff5
LG		 1851 if (pci_p2pdma_add_resource(pdev, bar, size, offset)) {
1852 dev_warn(dev->ctrl.device,
1853 "failed to register the CMB\n");
f65efd6d 1854 return;
0f238ff5
LG		 1855 }
1856
8ffaadf7 1857 dev->cmb_size = size;
0f238ff5
LG		 1858 dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS);
1859
1860 if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) ==
1861 (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS))
1862 pci_p2pmem_publish(pdev, true);
f65efd6d
CH		 1863
1864 if (sysfs_add_file_to_group(&dev->ctrl.device->kobj,
1865 &dev_attr_cmb.attr, NULL))
1866 dev_warn(dev->ctrl.device,
1867 "failed to add sysfs attribute for CMB\n");
8ffaadf7
JD		 1868}
1869
1870static inline void nvme_release_cmb(struct nvme_dev *dev)
1871{
0f238ff5 1872 if (dev->cmb_size) {
1c78f773
MG		 1873 sysfs_remove_file_from_group(&dev->ctrl.device->kobj,
1874 &dev_attr_cmb.attr, NULL);
0f238ff5 1875 dev->cmb_size = 0;
8ffaadf7
JD		 1876 }
1877}
1878
87ad72a5
CH		 1879static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1880{
6c3c05b0 1881 u32 host_mem_size = dev->host_mem_size >> NVME_CTRL_PAGE_SHIFT;
4033f35d 1882 u64 dma_addr = dev->host_mem_descs_dma;
f66e2804 1883 struct nvme_command c = { };
87ad72a5
CH		 1884 int ret;
1885
87ad72a5
CH		 1886 c.features.opcode = nvme_admin_set_features;
1887 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1888 c.features.dword11 = cpu_to_le32(bits);
6c3c05b0 1889 c.features.dword12 = cpu_to_le32(host_mem_size);
87ad72a5
CH		 1890 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr));
1891 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr));
1892 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs);
1893
1894 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1895 if (ret) {
1896 dev_warn(dev->ctrl.device,
1897 "failed to set host mem (err %d, flags %#x).\n",
1898 ret, bits);
1899 }
87ad72a5
CH		 1900 return ret;
1901}
1902
1903static void nvme_free_host_mem(struct nvme_dev *dev)
1904{
1905 int i;
1906
1907 for (i = 0; i < dev->nr_host_mem_descs; i++) {
1908 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
6c3c05b0 1909 size_t size = le32_to_cpu(desc->size) * NVME_CTRL_PAGE_SIZE;
87ad72a5 1910
cc667f6d
LD		 1911 dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i],
1912 le64_to_cpu(desc->addr),
1913 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
87ad72a5
CH		 1914 }
1915
1916 kfree(dev->host_mem_desc_bufs);
1917 dev->host_mem_desc_bufs = NULL;
4033f35d
CH		 1918 dma_free_coherent(dev->dev,
1919 dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
1920 dev->host_mem_descs, dev->host_mem_descs_dma);
87ad72a5 1921 dev->host_mem_descs = NULL;
7e5dd57e 1922 dev->nr_host_mem_descs = 0;
87ad72a5
CH		 1923}
1924
92dc6895
CH		 1925static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
1926 u32 chunk_size)
9d713c2b 1927{
87ad72a5 1928 struct nvme_host_mem_buf_desc *descs;
92dc6895 1929 u32 max_entries, len;
4033f35d 1930 dma_addr_t descs_dma;
2ee0e4ed 1931 int i = 0;
87ad72a5 1932 void **bufs;
6fbcde66 1933 u64 size, tmp;
87ad72a5 1934
87ad72a5
CH		 1935 tmp = (preferred + chunk_size - 1);
1936 do_div(tmp, chunk_size);
1937 max_entries = tmp;
044a9df1
CH		 1938
1939 if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
1940 max_entries = dev->ctrl.hmmaxd;
1941
750afb08
LC		 1942 descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs),
1943 &descs_dma, GFP_KERNEL);
87ad72a5
CH		 1944 if (!descs)
1945 goto out;
1946
1947 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
1948 if (!bufs)
1949 goto out_free_descs;
1950
244a8fe4 1951 for (size = 0; size < preferred && i < max_entries; size += len) {
87ad72a5
CH		 1952 dma_addr_t dma_addr;
1953
50cdb7c6 1954 len = min_t(u64, chunk_size, preferred - size);
87ad72a5
CH		 1955 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
1956 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1957 if (!bufs[i])
1958 break;
1959
1960 descs[i].addr = cpu_to_le64(dma_addr);
6c3c05b0 1961 descs[i].size = cpu_to_le32(len / NVME_CTRL_PAGE_SIZE);
87ad72a5
CH		 1962 i++;
1963 }
1964
92dc6895 1965 if (!size)
87ad72a5 1966 goto out_free_bufs;
87ad72a5 1967
87ad72a5
CH		 1968 dev->nr_host_mem_descs = i;
1969 dev->host_mem_size = size;
1970 dev->host_mem_descs = descs;
4033f35d 1971 dev->host_mem_descs_dma = descs_dma;
87ad72a5
CH		 1972 dev->host_mem_desc_bufs = bufs;
1973 return 0;
1974
1975out_free_bufs:
1976 while (--i >= 0) {
6c3c05b0 1977 size_t size = le32_to_cpu(descs[i].size) * NVME_CTRL_PAGE_SIZE;
87ad72a5 1978
cc667f6d
LD		 1979 dma_free_attrs(dev->dev, size, bufs[i],
1980 le64_to_cpu(descs[i].addr),
1981 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
87ad72a5
CH		 1982 }
1983
1984 kfree(bufs);
1985out_free_descs:
4033f35d
CH		 1986 dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
1987 descs_dma);
87ad72a5 1988out:
87ad72a5
CH		 1989 dev->host_mem_descs = NULL;
1990 return -ENOMEM;
1991}
1992
92dc6895
CH		 1993static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
1994{
9dc54a0d
CK		 1995 u64 min_chunk = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
1996 u64 hmminds = max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
1997 u64 chunk_size;
92dc6895
CH		 1998
1999 /* start big and work our way down */
9dc54a0d 2000 for (chunk_size = min_chunk; chunk_size >= hmminds; chunk_size /= 2) {
92dc6895
CH		 2001 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
2002 if (!min || dev->host_mem_size >= min)
2003 return 0;
2004 nvme_free_host_mem(dev);
2005 }
2006 }
2007
2008 return -ENOMEM;
2009}
2010
9620cfba 2011static int nvme_setup_host_mem(struct nvme_dev *dev)
87ad72a5
CH		 2012{
2013 u64 max = (u64)max_host_mem_size_mb * SZ_1M;
2014 u64 preferred = (u64)dev->ctrl.hmpre * 4096;
2015 u64 min = (u64)dev->ctrl.hmmin * 4096;
2016 u32 enable_bits = NVME_HOST_MEM_ENABLE;
6fbcde66 2017 int ret;
87ad72a5
CH		 2018
2019 preferred = min(preferred, max);
2020 if (min > max) {
2021 dev_warn(dev->ctrl.device,
2022 "min host memory (%lld MiB) above limit (%d MiB).\n",
2023 min >> ilog2(SZ_1M), max_host_mem_size_mb);
2024 nvme_free_host_mem(dev);
9620cfba 2025 return 0;
87ad72a5
CH		 2026 }
2027
2028 /*
2029 * If we already have a buffer allocated check if we can reuse it.
2030 */
2031 if (dev->host_mem_descs) {
2032 if (dev->host_mem_size >= min)
2033 enable_bits |= NVME_HOST_MEM_RETURN;
2034 else
2035 nvme_free_host_mem(dev);
2036 }
2037
2038 if (!dev->host_mem_descs) {
92dc6895
CH		 2039 if (nvme_alloc_host_mem(dev, min, preferred)) {
2040 dev_warn(dev->ctrl.device,
2041 "failed to allocate host memory buffer.\n");
9620cfba 2042 return 0; /* controller must work without HMB */
92dc6895
CH		 2043 }
2044
2045 dev_info(dev->ctrl.device,
2046 "allocated %lld MiB host memory buffer.\n",
2047 dev->host_mem_size >> ilog2(SZ_1M));
87ad72a5
CH		 2048 }
2049
9620cfba
CH		 2050 ret = nvme_set_host_mem(dev, enable_bits);
2051 if (ret)
87ad72a5 2052 nvme_free_host_mem(dev);
9620cfba 2053 return ret;
9d713c2b
KB		 2054}
2055
612b7286
ML		 2056/*
2057 * nirqs is the number of interrupts available for write and read
2058 * queues. The core already reserved an interrupt for the admin queue.
2059 */
2060static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs)
3b6592f7 2061{
612b7286 2062 struct nvme_dev *dev = affd->priv;
2a5bcfdd 2063 unsigned int nr_read_queues, nr_write_queues = dev->nr_write_queues;
3b6592f7
JA		 2064
2065 /*
ee0d96d3 2066 * If there is no interrupt available for queues, ensure that
612b7286
ML		 2067 * the default queue is set to 1. The affinity set size is
2068 * also set to one, but the irq core ignores it for this case.
2069 *
2070 * If only one interrupt is available or 'write_queue' == 0, combine
2071 * write and read queues.
2072 *
2073 * If 'write_queues' > 0, ensure it leaves room for at least one read
2074 * queue.
3b6592f7 2075 */
612b7286
ML		 2076 if (!nrirqs) {
2077 nrirqs = 1;
2078 nr_read_queues = 0;
2a5bcfdd 2079 } else if (nrirqs == 1 || !nr_write_queues) {
612b7286 2080 nr_read_queues = 0;
2a5bcfdd 2081 } else if (nr_write_queues >= nrirqs) {
612b7286 2082 nr_read_queues = 1;
3b6592f7 2083 } else {
2a5bcfdd 2084 nr_read_queues = nrirqs - nr_write_queues;
3b6592f7 2085 }
612b7286
ML		 2086
2087 dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2088 affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2089 dev->io_queues[HCTX_TYPE_READ] = nr_read_queues;
2090 affd->set_size[HCTX_TYPE_READ] = nr_read_queues;
2091 affd->nr_sets = nr_read_queues ? 2 : 1;
3b6592f7
JA		 2092}
2093
6451fe73 2094static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues)
3b6592f7
JA		 2095{
2096 struct pci_dev *pdev = to_pci_dev(dev->dev);
3b6592f7 2097 struct irq_affinity affd = {
9cfef55b 2098 .pre_vectors = 1,
612b7286
ML		 2099 .calc_sets = nvme_calc_irq_sets,
2100 .priv = dev,
3b6592f7 2101 };
21cc2f3f 2102 unsigned int irq_queues, poll_queues;
6451fe73
JA		 2103
2104 /*
21cc2f3f
JX		 2105 * Poll queues don't need interrupts, but we need at least one I/O queue
2106 * left over for non-polled I/O.
6451fe73 2107 */
21cc2f3f
JX		 2108 poll_queues = min(dev->nr_poll_queues, nr_io_queues - 1);
2109 dev->io_queues[HCTX_TYPE_POLL] = poll_queues;
3b6592f7 2110
21cc2f3f
JX		 2111 /*
2112 * Initialize for the single interrupt case, will be updated in
2113 * nvme_calc_irq_sets().
2114 */
612b7286
ML		 2115 dev->io_queues[HCTX_TYPE_DEFAULT] = 1;
2116 dev->io_queues[HCTX_TYPE_READ] = 0;
3b6592f7 2117
66341331 2118 /*
21cc2f3f
JX		 2119 * We need interrupts for the admin queue and each non-polled I/O queue,
2120 * but some Apple controllers require all queues to use the first
2121 * vector.
66341331 2122 */
21cc2f3f
JX		 2123 irq_queues = 1;
2124 if (!(dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR))
2125 irq_queues += (nr_io_queues - poll_queues);
612b7286
ML		 2126 return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues,
2127 PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd);
3b6592f7
JA		 2128}
2129
8fae268b
KB		 2130static void nvme_disable_io_queues(struct nvme_dev *dev)
2131{
2132 if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq))
2133 __nvme_disable_io_queues(dev, nvme_admin_delete_cq);
2134}
2135
2a5bcfdd
WZ		 2136static unsigned int nvme_max_io_queues(struct nvme_dev *dev)
2137{
e3aef095
NS		 2138 /*
2139 * If tags are shared with admin queue (Apple bug), then
2140 * make sure we only use one IO queue.
2141 */
2142 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2143 return 1;
2a5bcfdd
WZ		 2144 return num_possible_cpus() + dev->nr_write_queues + dev->nr_poll_queues;
2145}
2146
8d85fce7 2147static int nvme_setup_io_queues(struct nvme_dev *dev)
b60503ba 2148{
147b27e4 2149 struct nvme_queue *adminq = &dev->queues[0];
e75ec752 2150 struct pci_dev *pdev = to_pci_dev(dev->dev);
2a5bcfdd 2151 unsigned int nr_io_queues;
97f6ef64 2152 unsigned long size;
2a5bcfdd 2153 int result;
b60503ba 2154
2a5bcfdd
WZ		 2155 /*
2156 * Sample the module parameters once at reset time so that we have
2157 * stable values to work with.
2158 */
2159 dev->nr_write_queues = write_queues;
2160 dev->nr_poll_queues = poll_queues;
d38e9f04 2161
e3aef095 2162 nr_io_queues = dev->nr_allocated_queues - 1;
9a0be7ab
CH		 2163 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
2164 if (result < 0)
1b23484b 2165 return result;
9a0be7ab 2166
f5fa90dc 2167 if (nr_io_queues == 0)
a5229050 2168 return 0;
53dc180e 2169
4e224106 2170 clear_bit(NVMEQ_ENABLED, &adminq->flags);
b60503ba 2171
0f238ff5 2172 if (dev->cmb_use_sqes) {
8ffaadf7
JD		 2173 result = nvme_cmb_qdepth(dev, nr_io_queues,
2174 sizeof(struct nvme_command));
2175 if (result > 0)
2176 dev->q_depth = result;
2177 else
0f238ff5 2178 dev->cmb_use_sqes = false;
8ffaadf7
JD		 2179 }
2180
97f6ef64
XY		 2181 do {
2182 size = db_bar_size(dev, nr_io_queues);
2183 result = nvme_remap_bar(dev, size);
2184 if (!result)
2185 break;
2186 if (!--nr_io_queues)
2187 return -ENOMEM;
2188 } while (1);
2189 adminq->q_db = dev->dbs;
f1938f6e 2190
8fae268b 2191 retry:
9d713c2b 2192 /* Deregister the admin queue's interrupt */
0ff199cb 2193 pci_free_irq(pdev, 0, adminq);
9d713c2b 2194
e32efbfc
JA		 2195 /*
2196 * If we enable msix early due to not intx, disable it again before
2197 * setting up the full range we need.
2198 */
dca51e78 2199 pci_free_irq_vectors(pdev);
3b6592f7
JA		 2200
2201 result = nvme_setup_irqs(dev, nr_io_queues);
22b55601 2202 if (result <= 0)
dca51e78 2203 return -EIO;
3b6592f7 2204
22b55601 2205 dev->num_vecs = result;
4b04cc6a 2206 result = max(result - 1, 1);
e20ba6e1 2207 dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL];
fa08a396 2208
063a8096
MW		 2209 /*
2210 * Should investigate if there's a performance win from allocating
2211 * more queues than interrupt vectors; it might allow the submission
2212 * path to scale better, even if the receive path is limited by the
2213 * number of interrupts.
2214 */
dca51e78 2215 result = queue_request_irq(adminq);
7c349dde 2216 if (result)
d4875622 2217 return result;
4e224106 2218 set_bit(NVMEQ_ENABLED, &adminq->flags);
8fae268b
KB		 2219
2220 result = nvme_create_io_queues(dev);
2221 if (result || dev->online_queues < 2)
2222 return result;
2223
2224 if (dev->online_queues - 1 < dev->max_qid) {
2225 nr_io_queues = dev->online_queues - 1;
2226 nvme_disable_io_queues(dev);
2227 nvme_suspend_io_queues(dev);
2228 goto retry;
2229 }
2230 dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n",
2231 dev->io_queues[HCTX_TYPE_DEFAULT],
2232 dev->io_queues[HCTX_TYPE_READ],
2233 dev->io_queues[HCTX_TYPE_POLL]);
2234 return 0;
b60503ba
MW		 2235}
2236
2a842aca 2237static void nvme_del_queue_end(struct request *req, blk_status_t error)
a5768aa8 2238{
db3cbfff 2239 struct nvme_queue *nvmeq = req->end_io_data;
b5875222 2240
db3cbfff 2241 blk_mq_free_request(req);
d1ed6aa1 2242 complete(&nvmeq->delete_done);
a5768aa8
KB		 2243}
2244
2a842aca 2245static void nvme_del_cq_end(struct request *req, blk_status_t error)
a5768aa8 2246{
db3cbfff 2247 struct nvme_queue *nvmeq = req->end_io_data;
a5768aa8 2248
d1ed6aa1
CH		 2249 if (error)
2250 set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
db3cbfff
KB		 2251
2252 nvme_del_queue_end(req, error);
a5768aa8
KB		 2253}
2254
db3cbfff 2255static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
bda4e0fb 2256{
db3cbfff
KB		 2257 struct request_queue *q = nvmeq->dev->ctrl.admin_q;
2258 struct request *req;
f66e2804 2259 struct nvme_command cmd = { };
bda4e0fb 2260
db3cbfff
KB		 2261 cmd.delete_queue.opcode = opcode;
2262 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
bda4e0fb 2263
39dfe844 2264 req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT);
db3cbfff
KB		 2265 if (IS_ERR(req))
2266 return PTR_ERR(req);
bda4e0fb 2267
db3cbfff
KB		 2268 req->end_io_data = nvmeq;
2269
d1ed6aa1 2270 init_completion(&nvmeq->delete_done);
8eeed0b5 2271 blk_execute_rq_nowait(NULL, req, false,
db3cbfff
KB		 2272 opcode == nvme_admin_delete_cq ?
2273 nvme_del_cq_end : nvme_del_queue_end);
2274 return 0;
bda4e0fb
KB		 2275}
2276
8fae268b 2277static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode)
a5768aa8 2278{
5271edd4 2279 int nr_queues = dev->online_queues - 1, sent = 0;
db3cbfff 2280 unsigned long timeout;
a5768aa8 2281
db3cbfff 2282 retry:
dc96f938 2283 timeout = NVME_ADMIN_TIMEOUT;
5271edd4
CH		 2284 while (nr_queues > 0) {
2285 if (nvme_delete_queue(&dev->queues[nr_queues], opcode))
2286 break;
2287 nr_queues--;
2288 sent++;
db3cbfff 2289 }
d1ed6aa1
CH		 2290 while (sent) {
2291 struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent];
2292
2293 timeout = wait_for_completion_io_timeout(&nvmeq->delete_done,
5271edd4
CH		 2294 timeout);
2295 if (timeout == 0)
2296 return false;
d1ed6aa1 2297
d1ed6aa1 2298 sent--;
5271edd4
CH		 2299 if (nr_queues)
2300 goto retry;
2301 }
2302 return true;
a5768aa8
KB		 2303}
2304
5d02a5c1 2305static void nvme_dev_add(struct nvme_dev *dev)
b60503ba 2306{
2b1b7e78
JW		 2307 int ret;
2308
5bae7f73 2309 if (!dev->ctrl.tagset) {
376f7ef8 2310 dev->tagset.ops = &nvme_mq_ops;
ffe7704d 2311 dev->tagset.nr_hw_queues = dev->online_queues - 1;
8fe34be1 2312 dev->tagset.nr_maps = 2; /* default + read */
ed92ad37
CH		 2313 if (dev->io_queues[HCTX_TYPE_POLL])
2314 dev->tagset.nr_maps++;
ffe7704d 2315 dev->tagset.timeout = NVME_IO_TIMEOUT;
d4ec47f1 2316 dev->tagset.numa_node = dev->ctrl.numa_node;
61f3b896
CK		 2317 dev->tagset.queue_depth = min_t(unsigned int, dev->q_depth,
2318 BLK_MQ_MAX_DEPTH) - 1;
d43f1ccf 2319 dev->tagset.cmd_size = sizeof(struct nvme_iod);
ffe7704d
KB		 2320 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2321 dev->tagset.driver_data = dev;
b60503ba 2322
d38e9f04
BH		 2323 /*
2324 * Some Apple controllers requires tags to be unique
2325 * across admin and IO queue, so reserve the first 32
2326 * tags of the IO queue.
2327 */
2328 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2329 dev->tagset.reserved_tags = NVME_AQ_DEPTH;
2330
2b1b7e78
JW		 2331 ret = blk_mq_alloc_tag_set(&dev->tagset);
2332 if (ret) {
2333 dev_warn(dev->ctrl.device,
2334 "IO queues tagset allocation failed %d\n", ret);
5d02a5c1 2335 return;
2b1b7e78 2336 }
5bae7f73 2337 dev->ctrl.tagset = &dev->tagset;
949928c1
KB		 2338 } else {
2339 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2340
2341 /* Free previously allocated queues that are no longer usable */
2342 nvme_free_queues(dev, dev->online_queues);
ffe7704d 2343 }
949928c1 2344
e8fd41bb 2345 nvme_dbbuf_set(dev);
b60503ba
MW		 2346}
2347
b00a726a 2348static int nvme_pci_enable(struct nvme_dev *dev)
0877cb0d 2349{
b00a726a 2350 int result = -ENOMEM;
e75ec752 2351 struct pci_dev *pdev = to_pci_dev(dev->dev);
4bdf2603 2352 int dma_address_bits = 64;
0877cb0d
KB		 2353
2354 if (pci_enable_device_mem(pdev))
2355 return result;
2356
0877cb0d 2357 pci_set_master(pdev);
0877cb0d 2358
4bdf2603
FS		 2359 if (dev->ctrl.quirks & NVME_QUIRK_DMA_ADDRESS_BITS_48)
2360 dma_address_bits = 48;
2361 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(dma_address_bits)))
052d0efa 2362 goto disable;
0877cb0d 2363
7a67cbea 2364 if (readl(dev->bar + NVME_REG_CSTS) == -1) {
0e53d180 2365 result = -ENODEV;
b00a726a 2366 goto disable;
0e53d180 2367 }
e32efbfc
JA		 2368
2369 /*
a5229050
KB		 2370 * Some devices and/or platforms don't advertise or work with INTx
2371 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2372 * adjust this later.
e32efbfc 2373 */
dca51e78
CH		 2374 result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
2375 if (result < 0)
2376 return result;
e32efbfc 2377
20d0dfe6 2378 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
7a67cbea 2379
7442ddce 2380 dev->q_depth = min_t(u32, NVME_CAP_MQES(dev->ctrl.cap) + 1,
b27c1e68 2381 io_queue_depth);
aa22c8e6 2382 dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */
20d0dfe6 2383 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
7a67cbea 2384 dev->dbs = dev->bar + 4096;
1f390c1f 2385
66341331
BH		 2386 /*
2387 * Some Apple controllers require a non-standard SQE size.
2388 * Interestingly they also seem to ignore the CC:IOSQES register
2389 * so we don't bother updating it here.
2390 */
2391 if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES)
2392 dev->io_sqes = 7;
2393 else
2394 dev->io_sqes = NVME_NVM_IOSQES;
1f390c1f
SG		 2395
2396 /*
2397 * Temporary fix for the Apple controller found in the MacBook8,1 and
2398 * some MacBook7,1 to avoid controller resets and data loss.
2399 */
2400 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
2401 dev->q_depth = 2;
9bdcfb10
CH		 2402 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
2403 "set queue depth=%u to work around controller resets\n",
1f390c1f 2404 dev->q_depth);
d554b5e1
MP		 2405 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2406 (pdev->device == 0xa821 || pdev->device == 0xa822) &&
20d0dfe6 2407 NVME_CAP_MQES(dev->ctrl.cap) == 0) {
d554b5e1
MP		 2408 dev->q_depth = 64;
2409 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2410 "set queue depth=%u\n", dev->q_depth);
1f390c1f
SG		 2411 }
2412
d38e9f04
BH		 2413 /*
2414 * Controllers with the shared tags quirk need the IO queue to be
2415 * big enough so that we get 32 tags for the admin queue
2416 */
2417 if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) &&
2418 (dev->q_depth < (NVME_AQ_DEPTH + 2))) {
2419 dev->q_depth = NVME_AQ_DEPTH + 2;
2420 dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n",
2421 dev->q_depth);
2422 }
2423
2424
f65efd6d 2425 nvme_map_cmb(dev);
202021c1 2426
a0a3408e
KB		 2427 pci_enable_pcie_error_reporting(pdev);
2428 pci_save_state(pdev);
0877cb0d
KB		 2429 return 0;
2430
2431 disable:
0877cb0d
KB		 2432 pci_disable_device(pdev);
2433 return result;
2434}
2435
2436static void nvme_dev_unmap(struct nvme_dev *dev)
b00a726a
KB		 2437{
2438 if (dev->bar)
2439 iounmap(dev->bar);
a1f447b3 2440 pci_release_mem_regions(to_pci_dev(dev->dev));
b00a726a
KB		 2441}
2442
2443static void nvme_pci_disable(struct nvme_dev *dev)
0877cb0d 2444{
e75ec752
CH		 2445 struct pci_dev *pdev = to_pci_dev(dev->dev);
2446
dca51e78 2447 pci_free_irq_vectors(pdev);
0877cb0d 2448
a0a3408e
KB		 2449 if (pci_is_enabled(pdev)) {
2450 pci_disable_pcie_error_reporting(pdev);
e75ec752 2451 pci_disable_device(pdev);
4d115420 2452 }
4d115420
KB		 2453}
2454
a5cdb68c 2455static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
b60503ba 2456{
e43269e6 2457 bool dead = true, freeze = false;
302ad8cc 2458 struct pci_dev *pdev = to_pci_dev(dev->dev);
22404274 2459
77bf25ea 2460 mutex_lock(&dev->shutdown_lock);
302ad8cc
KB		 2461 if (pci_is_enabled(pdev)) {
2462 u32 csts = readl(dev->bar + NVME_REG_CSTS);
2463
ebef7368 2464 if (dev->ctrl.state == NVME_CTRL_LIVE ||
e43269e6
KB		 2465 dev->ctrl.state == NVME_CTRL_RESETTING) {
2466 freeze = true;
302ad8cc 2467 nvme_start_freeze(&dev->ctrl);
e43269e6 2468 }
302ad8cc
KB		 2469 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
2470 pdev->error_state != pci_channel_io_normal);
c9d3bf88 2471 }
c21377f8 2472
302ad8cc
KB		 2473 /*
2474 * Give the controller a chance to complete all entered requests if
2475 * doing a safe shutdown.
2476 */
e43269e6
KB		 2477 if (!dead && shutdown && freeze)
2478 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
9a915a5b
JW		 2479
2480 nvme_stop_queues(&dev->ctrl);
87ad72a5 2481
64ee0ac0 2482 if (!dead && dev->ctrl.queue_count > 0) {
8fae268b 2483 nvme_disable_io_queues(dev);
a5cdb68c 2484 nvme_disable_admin_queue(dev, shutdown);
4d115420 2485 }
8fae268b
KB		 2486 nvme_suspend_io_queues(dev);
2487 nvme_suspend_queue(&dev->queues[0]);
b00a726a 2488 nvme_pci_disable(dev);
fa46c6fb 2489 nvme_reap_pending_cqes(dev);
07836e65 2490
e1958e65
ML		 2491 blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
2492 blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
622b8b68
ML		 2493 blk_mq_tagset_wait_completed_request(&dev->tagset);
2494 blk_mq_tagset_wait_completed_request(&dev->admin_tagset);
302ad8cc
KB		 2495
2496 /*
2497 * The driver will not be starting up queues again if shutting down so
2498 * must flush all entered requests to their failed completion to avoid
2499 * deadlocking blk-mq hot-cpu notifier.
2500 */
c8e9e9b7 2501 if (shutdown) {
302ad8cc 2502 nvme_start_queues(&dev->ctrl);
c8e9e9b7
KB		 2503 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q))
2504 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
2505 }
77bf25ea 2506 mutex_unlock(&dev->shutdown_lock);
b60503ba
MW		 2507}
2508
c1ac9a4b
KB		 2509static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown)
2510{
2511 if (!nvme_wait_reset(&dev->ctrl))
2512 return -EBUSY;
2513 nvme_dev_disable(dev, shutdown);
2514 return 0;
2515}
2516
091b6092
MW		 2517static int nvme_setup_prp_pools(struct nvme_dev *dev)
2518{
e75ec752 2519 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
c61b82c7
CH		 2520 NVME_CTRL_PAGE_SIZE,
2521 NVME_CTRL_PAGE_SIZE, 0);
091b6092
MW		 2522 if (!dev->prp_page_pool)
2523 return -ENOMEM;
2524
99802a7a 2525 /* Optimisation for I/Os between 4k and 128k */
e75ec752 2526 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
99802a7a
MW		 2527 256, 256, 0);
2528 if (!dev->prp_small_pool) {
2529 dma_pool_destroy(dev->prp_page_pool);
2530 return -ENOMEM;
2531 }
091b6092
MW		 2532 return 0;
2533}
2534
2535static void nvme_release_prp_pools(struct nvme_dev *dev)
2536{
2537 dma_pool_destroy(dev->prp_page_pool);
99802a7a 2538 dma_pool_destroy(dev->prp_small_pool);
091b6092
MW		 2539}
2540
770597ec
KB		 2541static void nvme_free_tagset(struct nvme_dev *dev)
2542{
2543 if (dev->tagset.tags)
2544 blk_mq_free_tag_set(&dev->tagset);
2545 dev->ctrl.tagset = NULL;
2546}
2547
1673f1f0 2548static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
5e82e952 2549{
1673f1f0 2550 struct nvme_dev *dev = to_nvme_dev(ctrl);
9ac27090 2551
f9f38e33 2552 nvme_dbbuf_dma_free(dev);
770597ec 2553 nvme_free_tagset(dev);
1c63dc66
CH		 2554 if (dev->ctrl.admin_q)
2555 blk_put_queue(dev->ctrl.admin_q);
e286bcfc 2556 free_opal_dev(dev->ctrl.opal_dev);
943e942e 2557 mempool_destroy(dev->iod_mempool);
253fd4ac
IR		 2558 put_device(dev->dev);
2559 kfree(dev->queues);
5e82e952
KB		 2560 kfree(dev);
2561}
2562
7c1ce408 2563static void nvme_remove_dead_ctrl(struct nvme_dev *dev)
f58944e2 2564{
c1ac9a4b
KB		 2565 /*
2566 * Set state to deleting now to avoid blocking nvme_wait_reset(), which
2567 * may be holding this pci_dev's device lock.
2568 */
2569 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
d22524a4 2570 nvme_get_ctrl(&dev->ctrl);
69d9a99c 2571 nvme_dev_disable(dev, false);
9f9cafc1 2572 nvme_kill_queues(&dev->ctrl);
03e0f3a6 2573 if (!queue_work(nvme_wq, &dev->remove_work))
f58944e2
KB		 2574 nvme_put_ctrl(&dev->ctrl);
2575}
2576
fd634f41 2577static void nvme_reset_work(struct work_struct *work)
5e82e952 2578{
d86c4d8e
CH		 2579 struct nvme_dev *dev =
2580 container_of(work, struct nvme_dev, ctrl.reset_work);
a98e58e5 2581 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
e71afda4 2582 int result;
5e82e952 2583
e71afda4
CK		 2584 if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING)) {
2585 result = -ENODEV;
fd634f41 2586 goto out;
e71afda4 2587 }
5e82e952 2588
fd634f41
CH		 2589 /*
2590 * If we're called to reset a live controller first shut it down before
2591 * moving on.
2592 */
b00a726a 2593 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
a5cdb68c 2594 nvme_dev_disable(dev, false);
d6135c3a 2595 nvme_sync_queues(&dev->ctrl);
5e82e952 2596
5c959d73 2597 mutex_lock(&dev->shutdown_lock);
b00a726a 2598 result = nvme_pci_enable(dev);
f0b50732 2599 if (result)
4726bcf3 2600 goto out_unlock;
f0b50732 2601
01ad0990 2602 result = nvme_pci_configure_admin_queue(dev);
f0b50732 2603 if (result)
4726bcf3 2604 goto out_unlock;
f0b50732 2605
0fb59cbc
KB		 2606 result = nvme_alloc_admin_tags(dev);
2607 if (result)
4726bcf3 2608 goto out_unlock;
b9afca3e 2609
943e942e
JA		 2610 /*
2611 * Limit the max command size to prevent iod->sg allocations going
2612 * over a single page.
2613 */
7637de31
CH		 2614 dev->ctrl.max_hw_sectors = min_t(u32,
2615 NVME_MAX_KB_SZ << 1, dma_max_mapping_size(dev->dev) >> 9);
943e942e 2616 dev->ctrl.max_segments = NVME_MAX_SEGS;
a48bc520
CH		 2617
2618 /*
2619 * Don't limit the IOMMU merged segment size.
2620 */
2621 dma_set_max_seg_size(dev->dev, 0xffffffff);
3d2d861e 2622 dma_set_min_align_mask(dev->dev, NVME_CTRL_PAGE_SIZE - 1);
a48bc520 2623
5c959d73
KB		 2624 mutex_unlock(&dev->shutdown_lock);
2625
2626 /*
2627 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
2628 * initializing procedure here.
2629 */
2630 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
2631 dev_warn(dev->ctrl.device,
2632 "failed to mark controller CONNECTING\n");
cee6c269 2633 result = -EBUSY;
5c959d73
KB		 2634 goto out;
2635 }
943e942e 2636
95093350
MG		 2637 /*
2638 * We do not support an SGL for metadata (yet), so we are limited to a
2639 * single integrity segment for the separate metadata pointer.
2640 */
2641 dev->ctrl.max_integrity_segments = 1;
2642
f21c4769 2643 result = nvme_init_ctrl_finish(&dev->ctrl);
ce4541f4 2644 if (result)
f58944e2 2645 goto out;
ce4541f4 2646
e286bcfc
SB		 2647 if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
2648 if (!dev->ctrl.opal_dev)
2649 dev->ctrl.opal_dev =
2650 init_opal_dev(&dev->ctrl, &nvme_sec_submit);
2651 else if (was_suspend)
2652 opal_unlock_from_suspend(dev->ctrl.opal_dev);
2653 } else {
2654 free_opal_dev(dev->ctrl.opal_dev);
2655 dev->ctrl.opal_dev = NULL;
4f1244c8 2656 }
a98e58e5 2657
f9f38e33
HK		 2658 if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) {
2659 result = nvme_dbbuf_dma_alloc(dev);
2660 if (result)
2661 dev_warn(dev->dev,
2662 "unable to allocate dma for dbbuf\n");
2663 }
2664
9620cfba
CH		 2665 if (dev->ctrl.hmpre) {
2666 result = nvme_setup_host_mem(dev);
2667 if (result < 0)
2668 goto out;
2669 }
87ad72a5 2670
f0b50732 2671 result = nvme_setup_io_queues(dev);
badc34d4 2672 if (result)
f58944e2 2673 goto out;
f0b50732 2674
2659e57b
CH		 2675 /*
2676 * Keep the controller around but remove all namespaces if we don't have
2677 * any working I/O queue.
2678 */
3cf519b5 2679 if (dev->online_queues < 2) {
1b3c47c1 2680 dev_warn(dev->ctrl.device, "IO queues not created\n");
3b24774e 2681 nvme_kill_queues(&dev->ctrl);
5bae7f73 2682 nvme_remove_namespaces(&dev->ctrl);
770597ec 2683 nvme_free_tagset(dev);
3cf519b5 2684 } else {
25646264 2685 nvme_start_queues(&dev->ctrl);
302ad8cc 2686 nvme_wait_freeze(&dev->ctrl);
5d02a5c1 2687 nvme_dev_add(dev);
302ad8cc 2688 nvme_unfreeze(&dev->ctrl);
3cf519b5
CH		 2689 }
2690
2b1b7e78
JW		 2691 /*
2692 * If only admin queue live, keep it to do further investigation or
2693 * recovery.
2694 */
5d02a5c1 2695 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
2b1b7e78 2696 dev_warn(dev->ctrl.device,
5d02a5c1 2697 "failed to mark controller live state\n");
e71afda4 2698 result = -ENODEV;
bb8d261e
CH		 2699 goto out;
2700 }
92911a55 2701
d09f2b45 2702 nvme_start_ctrl(&dev->ctrl);
3cf519b5 2703 return;
f0b50732 2704
4726bcf3
KB		 2705 out_unlock:
2706 mutex_unlock(&dev->shutdown_lock);
3cf519b5 2707 out:
7c1ce408
CK		 2708 if (result)
2709 dev_warn(dev->ctrl.device,
2710 "Removing after probe failure status: %d\n", result);
2711 nvme_remove_dead_ctrl(dev);
f0b50732
KB		 2712}
2713
5c8809e6 2714static void nvme_remove_dead_ctrl_work(struct work_struct *work)
9a6b9458 2715{
5c8809e6 2716 struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
e75ec752 2717 struct pci_dev *pdev = to_pci_dev(dev->dev);
9a6b9458
KB		 2718
2719 if (pci_get_drvdata(pdev))
921920ab 2720 device_release_driver(&pdev->dev);
1673f1f0 2721 nvme_put_ctrl(&dev->ctrl);
9a6b9458
KB		 2722}
2723
1c63dc66 2724static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
9ca97374 2725{
1c63dc66 2726 *val = readl(to_nvme_dev(ctrl)->bar + off);
90667892 2727 return 0;
9ca97374
TH		 2728}
2729
5fd4ce1b 2730static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
4cc06521 2731{
5fd4ce1b
CH		 2732 writel(val, to_nvme_dev(ctrl)->bar + off);
2733 return 0;
2734}
4cc06521 2735
7fd8930f
CH		 2736static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2737{
3a8ecc93 2738 *val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off);
7fd8930f 2739 return 0;
4cc06521
KB		 2740}
2741
97c12223
KB		 2742static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
2743{
2744 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2745
2db24e4a 2746 return snprintf(buf, size, "%s\n", dev_name(&pdev->dev));
97c12223
KB		 2747}
2748
1c63dc66 2749static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
1a353d85 2750 .name = "pcie",
e439bb12 2751 .module = THIS_MODULE,
e0596ab2
LG		 2752 .flags = NVME_F_METADATA_SUPPORTED |
2753 NVME_F_PCI_P2PDMA,
1c63dc66 2754 .reg_read32 = nvme_pci_reg_read32,
5fd4ce1b 2755 .reg_write32 = nvme_pci_reg_write32,
7fd8930f 2756 .reg_read64 = nvme_pci_reg_read64,
1673f1f0 2757 .free_ctrl = nvme_pci_free_ctrl,
f866fc42 2758 .submit_async_event = nvme_pci_submit_async_event,
97c12223 2759 .get_address = nvme_pci_get_address,
1c63dc66 2760};
4cc06521 2761
b00a726a
KB		 2762static int nvme_dev_map(struct nvme_dev *dev)
2763{
b00a726a
KB		 2764 struct pci_dev *pdev = to_pci_dev(dev->dev);
2765
a1f447b3 2766 if (pci_request_mem_regions(pdev, "nvme"))
b00a726a
KB		 2767 return -ENODEV;
2768
97f6ef64 2769 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
b00a726a
KB		 2770 goto release;
2771
9fa196e7 2772 return 0;
b00a726a 2773 release:
9fa196e7
MG		 2774 pci_release_mem_regions(pdev);
2775 return -ENODEV;
b00a726a
KB		 2776}
2777
8427bbc2 2778static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
ff5350a8
AL		 2779{
2780 if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
2781 /*
2782 * Several Samsung devices seem to drop off the PCIe bus
2783 * randomly when APST is on and uses the deepest sleep state.
2784 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2785 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2786 * 950 PRO 256GB", but it seems to be restricted to two Dell
2787 * laptops.
2788 */
2789 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
2790 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
2791 dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
2792 return NVME_QUIRK_NO_DEEPEST_PS;
8427bbc2
KHF		 2793 } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
2794 /*
2795 * Samsung SSD 960 EVO drops off the PCIe bus after system
467c77d4
JJ		 2796 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
2797 * within few minutes after bootup on a Coffee Lake board -
2798 * ASUS PRIME Z370-A
8427bbc2
KHF		 2799 */
2800 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
467c77d4
JJ		 2801 (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") ||
2802 dmi_match(DMI_BOARD_NAME, "PRIME Z370-A")))
8427bbc2 2803 return NVME_QUIRK_NO_APST;
1fae37ac
S		 2804 } else if ((pdev->vendor == 0x144d && (pdev->device == 0xa801 ||
2805 pdev->device == 0xa808 || pdev->device == 0xa809)) ||
2806 (pdev->vendor == 0x1e0f && pdev->device == 0x0001)) {
2807 /*
2808 * Forcing to use host managed nvme power settings for
2809 * lowest idle power with quick resume latency on
2810 * Samsung and Toshiba SSDs based on suspend behavior
2811 * on Coffee Lake board for LENOVO C640
2812 */
2813 if ((dmi_match(DMI_BOARD_VENDOR, "LENOVO")) &&
2814 dmi_match(DMI_BOARD_NAME, "LNVNB161216"))
2815 return NVME_QUIRK_SIMPLE_SUSPEND;
ff5350a8
AL		 2816 }
2817
2818 return 0;
2819}
2820
18119775
KB		 2821static void nvme_async_probe(void *data, async_cookie_t cookie)
2822{
2823 struct nvme_dev *dev = data;
80f513b5 2824
bd46a906 2825 flush_work(&dev->ctrl.reset_work);
18119775 2826 flush_work(&dev->ctrl.scan_work);
80f513b5 2827 nvme_put_ctrl(&dev->ctrl);
18119775
KB		 2828}
2829
8d85fce7 2830static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
b60503ba 2831{
a4aea562 2832 int node, result = -ENOMEM;
b60503ba 2833 struct nvme_dev *dev;
ff5350a8 2834 unsigned long quirks = id->driver_data;
943e942e 2835 size_t alloc_size;
b60503ba 2836
a4aea562
MB		 2837 node = dev_to_node(&pdev->dev);
2838 if (node == NUMA_NO_NODE)
2fa84351 2839 set_dev_node(&pdev->dev, first_memory_node);
a4aea562
MB		 2840
2841 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
b60503ba
MW		 2842 if (!dev)
2843 return -ENOMEM;
147b27e4 2844
2a5bcfdd
WZ		 2845 dev->nr_write_queues = write_queues;
2846 dev->nr_poll_queues = poll_queues;
2847 dev->nr_allocated_queues = nvme_max_io_queues(dev) + 1;
2848 dev->queues = kcalloc_node(dev->nr_allocated_queues,
2849 sizeof(struct nvme_queue), GFP_KERNEL, node);
b60503ba
MW		 2850 if (!dev->queues)
2851 goto free;
2852
e75ec752 2853 dev->dev = get_device(&pdev->dev);
9a6b9458 2854 pci_set_drvdata(pdev, dev);
1c63dc66 2855
b00a726a
KB		 2856 result = nvme_dev_map(dev);
2857 if (result)
b00c9b7a 2858 goto put_pci;
b00a726a 2859
d86c4d8e 2860 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
5c8809e6 2861 INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
77bf25ea 2862 mutex_init(&dev->shutdown_lock);
b60503ba 2863
091b6092
MW		 2864 result = nvme_setup_prp_pools(dev);
2865 if (result)
b00c9b7a 2866 goto unmap;
4cc06521 2867
8427bbc2 2868 quirks |= check_vendor_combination_bug(pdev);
ff5350a8 2869
2744d7a0 2870 if (!noacpi && acpi_storage_d3(&pdev->dev)) {
df4f9bc4
DB		 2871 /*
2872 * Some systems use a bios work around to ask for D3 on
2873 * platforms that support kernel managed suspend.
2874 */
2875 dev_info(&pdev->dev,
2876 "platform quirk: setting simple suspend\n");
2877 quirks |= NVME_QUIRK_SIMPLE_SUSPEND;
2878 }
2879
943e942e
JA		 2880 /*
2881 * Double check that our mempool alloc size will cover the biggest
2882 * command we support.
2883 */
b13c6393 2884 alloc_size = nvme_pci_iod_alloc_size();
943e942e
JA		 2885 WARN_ON_ONCE(alloc_size > PAGE_SIZE);
2886
2887 dev->iod_mempool = mempool_create_node(1, mempool_kmalloc,
2888 mempool_kfree,
2889 (void *) alloc_size,
2890 GFP_KERNEL, node);
2891 if (!dev->iod_mempool) {
2892 result = -ENOMEM;
2893 goto release_pools;
2894 }
2895
b6e44b4c
KB		 2896 result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
2897 quirks);
2898 if (result)
2899 goto release_mempool;
2900
1b3c47c1
SG		 2901 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
2902
bd46a906 2903 nvme_reset_ctrl(&dev->ctrl);
18119775 2904 async_schedule(nvme_async_probe, dev);
4caff8fc 2905
b60503ba
MW		 2906 return 0;
2907
b6e44b4c
KB		 2908 release_mempool:
2909 mempool_destroy(dev->iod_mempool);
0877cb0d 2910 release_pools:
091b6092 2911 nvme_release_prp_pools(dev);
b00c9b7a
CJ		 2912 unmap:
2913 nvme_dev_unmap(dev);
a96d4f5c 2914 put_pci:
e75ec752 2915 put_device(dev->dev);
b60503ba
MW		 2916 free:
2917 kfree(dev->queues);
b60503ba
MW		 2918 kfree(dev);
2919 return result;
2920}
2921
775755ed 2922static void nvme_reset_prepare(struct pci_dev *pdev)
f0d54a54 2923{
a6739479 2924 struct nvme_dev *dev = pci_get_drvdata(pdev);
c1ac9a4b
KB		 2925
2926 /*
2927 * We don't need to check the return value from waiting for the reset
2928 * state as pci_dev device lock is held, making it impossible to race
2929 * with ->remove().
2930 */
2931 nvme_disable_prepare_reset(dev, false);
2932 nvme_sync_queues(&dev->ctrl);
775755ed 2933}
f0d54a54 2934
775755ed
CH		 2935static void nvme_reset_done(struct pci_dev *pdev)
2936{
f263fbb8 2937 struct nvme_dev *dev = pci_get_drvdata(pdev);
c1ac9a4b
KB		 2938
2939 if (!nvme_try_sched_reset(&dev->ctrl))
2940 flush_work(&dev->ctrl.reset_work);
f0d54a54
KB		 2941}
2942
09ece142
KB		 2943static void nvme_shutdown(struct pci_dev *pdev)
2944{
2945 struct nvme_dev *dev = pci_get_drvdata(pdev);
4e523547 2946
c1ac9a4b 2947 nvme_disable_prepare_reset(dev, true);
09ece142
KB		 2948}
2949
f58944e2
KB		 2950/*
2951 * The driver's remove may be called on a device in a partially initialized
2952 * state. This function must not have any dependencies on the device state in
2953 * order to proceed.
2954 */
8d85fce7 2955static void nvme_remove(struct pci_dev *pdev)
b60503ba
MW		 2956{
2957 struct nvme_dev *dev = pci_get_drvdata(pdev);
9a6b9458 2958
bb8d261e 2959 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
9a6b9458 2960 pci_set_drvdata(pdev, NULL);
0ff9d4e1 2961
6db28eda 2962 if (!pci_device_is_present(pdev)) {
0ff9d4e1 2963 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
1d39e692 2964 nvme_dev_disable(dev, true);
cb4bfda6 2965 nvme_dev_remove_admin(dev);
6db28eda 2966 }
0ff9d4e1 2967
d86c4d8e 2968 flush_work(&dev->ctrl.reset_work);
d09f2b45
SG		 2969 nvme_stop_ctrl(&dev->ctrl);
2970 nvme_remove_namespaces(&dev->ctrl);
a5cdb68c 2971 nvme_dev_disable(dev, true);
9fe5c59f 2972 nvme_release_cmb(dev);
87ad72a5 2973 nvme_free_host_mem(dev);
a4aea562 2974 nvme_dev_remove_admin(dev);
a1a5ef99 2975 nvme_free_queues(dev, 0);
9a6b9458 2976 nvme_release_prp_pools(dev);
b00a726a 2977 nvme_dev_unmap(dev);
726612b6 2978 nvme_uninit_ctrl(&dev->ctrl);
b60503ba
MW		 2979}
2980
671a6018 2981#ifdef CONFIG_PM_SLEEP
d916b1be
KB		 2982static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps)
2983{
2984 return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps);
2985}
2986
2987static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps)
2988{
2989 return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL);
2990}
2991
2992static int nvme_resume(struct device *dev)
2993{
2994 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
2995 struct nvme_ctrl *ctrl = &ndev->ctrl;
2996
4eaefe8c 2997 if (ndev->last_ps == U32_MAX ||
d916b1be 2998 nvme_set_power_state(ctrl, ndev->last_ps) != 0)
c1ac9a4b 2999 return nvme_try_sched_reset(&ndev->ctrl);
d916b1be
KB		 3000 return 0;
3001}
3002
cd638946
KB		 3003static int nvme_suspend(struct device *dev)
3004{
3005 struct pci_dev *pdev = to_pci_dev(dev);
3006 struct nvme_dev *ndev = pci_get_drvdata(pdev);
d916b1be
KB		 3007 struct nvme_ctrl *ctrl = &ndev->ctrl;
3008 int ret = -EBUSY;
3009
4eaefe8c
RW		 3010 ndev->last_ps = U32_MAX;
3011
d916b1be
KB		 3012 /*
3013 * The platform does not remove power for a kernel managed suspend so
3014 * use host managed nvme power settings for lowest idle power if
3015 * possible. This should have quicker resume latency than a full device
3016 * shutdown. But if the firmware is involved after the suspend or the
3017 * device does not support any non-default power states, shut down the
3018 * device fully.
4eaefe8c
RW		 3019 *
3020 * If ASPM is not enabled for the device, shut down the device and allow
3021 * the PCI bus layer to put it into D3 in order to take the PCIe link
3022 * down, so as to allow the platform to achieve its minimum low-power
3023 * state (which may not be possible if the link is up).
b97120b1
CH		 3024 *
3025 * If a host memory buffer is enabled, shut down the device as the NVMe
3026 * specification allows the device to access the host memory buffer in
3027 * host DRAM from all power states, but hosts will fail access to DRAM
3028 * during S3.
d916b1be 3029 */
4eaefe8c 3030 if (pm_suspend_via_firmware() || !ctrl->npss ||
cb32de1b 3031 !pcie_aspm_enabled(pdev) ||
b97120b1 3032 ndev->nr_host_mem_descs ||
c1ac9a4b
KB		 3033 (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND))
3034 return nvme_disable_prepare_reset(ndev, true);
d916b1be
KB		 3035
3036 nvme_start_freeze(ctrl);
3037 nvme_wait_freeze(ctrl);
3038 nvme_sync_queues(ctrl);
3039
5d02a5c1 3040 if (ctrl->state != NVME_CTRL_LIVE)
d916b1be
KB		 3041 goto unfreeze;
3042
d916b1be
KB		 3043 ret = nvme_get_power_state(ctrl, &ndev->last_ps);
3044 if (ret < 0)
3045 goto unfreeze;
3046
7cbb5c6f
ML		 3047 /*
3048 * A saved state prevents pci pm from generically controlling the
3049 * device's power. If we're using protocol specific settings, we don't
3050 * want pci interfering.
3051 */
3052 pci_save_state(pdev);
3053
d916b1be
KB		 3054 ret = nvme_set_power_state(ctrl, ctrl->npss);
3055 if (ret < 0)
3056 goto unfreeze;
3057
3058 if (ret) {
7cbb5c6f
ML		 3059 /* discard the saved state */
3060 pci_load_saved_state(pdev, NULL);
3061
d916b1be
KB		 3062 /*
3063 * Clearing npss forces a controller reset on resume. The
05d3046f 3064 * correct value will be rediscovered then.
d916b1be 3065 */
c1ac9a4b 3066 ret = nvme_disable_prepare_reset(ndev, true);
d916b1be 3067 ctrl->npss = 0;
d916b1be 3068 }
d916b1be
KB		 3069unfreeze:
3070 nvme_unfreeze(ctrl);
3071 return ret;
3072}
3073
3074static int nvme_simple_suspend(struct device *dev)
3075{
3076 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
4e523547 3077
c1ac9a4b 3078 return nvme_disable_prepare_reset(ndev, true);
cd638946
KB		 3079}
3080
d916b1be 3081static int nvme_simple_resume(struct device *dev)
cd638946
KB		 3082{
3083 struct pci_dev *pdev = to_pci_dev(dev);
3084 struct nvme_dev *ndev = pci_get_drvdata(pdev);
cd638946 3085
c1ac9a4b 3086 return nvme_try_sched_reset(&ndev->ctrl);
cd638946
KB		 3087}
3088
21774222 3089static const struct dev_pm_ops nvme_dev_pm_ops = {
d916b1be
KB		 3090 .suspend = nvme_suspend,
3091 .resume = nvme_resume,
3092 .freeze = nvme_simple_suspend,
3093 .thaw = nvme_simple_resume,
3094 .poweroff = nvme_simple_suspend,
3095 .restore = nvme_simple_resume,
3096};
3097#endif /* CONFIG_PM_SLEEP */
b60503ba 3098
a0a3408e
KB		 3099static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
3100 pci_channel_state_t state)
3101{
3102 struct nvme_dev *dev = pci_get_drvdata(pdev);
3103
3104 /*
3105 * A frozen channel requires a reset. When detected, this method will
3106 * shutdown the controller to quiesce. The controller will be restarted
3107 * after the slot reset through driver's slot_reset callback.
3108 */
a0a3408e
KB		 3109 switch (state) {
3110 case pci_channel_io_normal:
3111 return PCI_ERS_RESULT_CAN_RECOVER;
3112 case pci_channel_io_frozen:
d011fb31
KB		 3113 dev_warn(dev->ctrl.device,
3114 "frozen state error detected, reset controller\n");
a5cdb68c 3115 nvme_dev_disable(dev, false);
a0a3408e
KB		 3116 return PCI_ERS_RESULT_NEED_RESET;
3117 case pci_channel_io_perm_failure:
d011fb31
KB		 3118 dev_warn(dev->ctrl.device,
3119 "failure state error detected, request disconnect\n");
a0a3408e
KB		 3120 return PCI_ERS_RESULT_DISCONNECT;
3121 }
3122 return PCI_ERS_RESULT_NEED_RESET;
3123}
3124
3125static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
3126{
3127 struct nvme_dev *dev = pci_get_drvdata(pdev);
3128
1b3c47c1 3129 dev_info(dev->ctrl.device, "restart after slot reset\n");
a0a3408e 3130 pci_restore_state(pdev);
d86c4d8e 3131 nvme_reset_ctrl(&dev->ctrl);
a0a3408e
KB		 3132 return PCI_ERS_RESULT_RECOVERED;
3133}
3134
3135static void nvme_error_resume(struct pci_dev *pdev)
3136{
72cd4cc2
KB		 3137 struct nvme_dev *dev = pci_get_drvdata(pdev);
3138
3139 flush_work(&dev->ctrl.reset_work);
a0a3408e
KB		 3140}
3141
1d352035 3142static const struct pci_error_handlers nvme_err_handler = {
b60503ba 3143 .error_detected = nvme_error_detected,
b60503ba
MW		 3144 .slot_reset = nvme_slot_reset,
3145 .resume = nvme_error_resume,
775755ed
CH		 3146 .reset_prepare = nvme_reset_prepare,
3147 .reset_done = nvme_reset_done,
b60503ba
MW		 3148};
3149
6eb0d698 3150static const struct pci_device_id nvme_id_table[] = {
972b13e2 3151 { PCI_VDEVICE(INTEL, 0x0953), /* Intel 750/P3500/P3600/P3700 */
08095e70 3152 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 3153 NVME_QUIRK_DEALLOCATE_ZEROES, },
972b13e2 3154 { PCI_VDEVICE(INTEL, 0x0a53), /* Intel P3520 */
99466e70 3155 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 3156 NVME_QUIRK_DEALLOCATE_ZEROES, },
972b13e2 3157 { PCI_VDEVICE(INTEL, 0x0a54), /* Intel P4500/P4600 */
99466e70 3158 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 3159 NVME_QUIRK_DEALLOCATE_ZEROES, },
972b13e2 3160 { PCI_VDEVICE(INTEL, 0x0a55), /* Dell Express Flash P4600 */
f99cb7af
DWF		 3161 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3162 NVME_QUIRK_DEALLOCATE_ZEROES, },
50af47d0 3163 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */
9abd68ef 3164 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
6c6aa2f2 3165 NVME_QUIRK_MEDIUM_PRIO_SQ |
ce4cc313
DM		 3166 NVME_QUIRK_NO_TEMP_THRESH_CHANGE |
3167 NVME_QUIRK_DISABLE_WRITE_ZEROES, },
6299358d
JD		 3168 { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */
3169 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
540c801c 3170 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */
7b210e4e
CH		 3171 .driver_data = NVME_QUIRK_IDENTIFY_CNS |
3172 NVME_QUIRK_DISABLE_WRITE_ZEROES, },
5bedd3af
CH		 3173 { PCI_DEVICE(0x126f, 0x2263), /* Silicon Motion unidentified */
3174 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST, },
0302ae60 3175 { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */
5e112d3f
JE		 3176 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
3177 NVME_QUIRK_NO_NS_DESC_LIST, },
54adc010
GP		 3178 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
3179 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
8c97eecc
JL		 3180 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */
3181 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
015282c9
WW		 3182 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
3183 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
d554b5e1
MP		 3184 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */
3185 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3186 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */
7ee5c78c 3187 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
abbb5f59 3188 NVME_QUIRK_DISABLE_WRITE_ZEROES|
7ee5c78c 3189 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
c9e95c39
CS		 3190 { PCI_DEVICE(0x1987, 0x5016), /* Phison E16 */
3191 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
6e6a6828
PT		 3192 { PCI_DEVICE(0x1b4b, 0x1092), /* Lexar 256 GB SSD */
3193 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST |
3194 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
608cc4b1
CH		 3195 { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */
3196 .driver_data = NVME_QUIRK_LIGHTNVM, },
3197 { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */
3198 .driver_data = NVME_QUIRK_LIGHTNVM, },
ea48e877
WX		 3199 { PCI_DEVICE(0x1d1d, 0x2601), /* CNEX Granby */
3200 .driver_data = NVME_QUIRK_LIGHTNVM, },
08b903b5
MN		 3201 { PCI_DEVICE(0x10ec, 0x5762), /* ADATA SX6000LNP */
3202 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
f03e42c6
GC		 3203 { PCI_DEVICE(0x1cc1, 0x8201), /* ADATA SX8200PNP 512GB */
3204 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3205 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
5611ec2b
KHF		 3206 { PCI_DEVICE(0x1c5c, 0x1504), /* SK Hynix PC400 */
3207 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
02ca079c
KHF		 3208 { PCI_DEVICE(0x15b7, 0x2001), /* Sandisk Skyhawk */
3209 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
89919929
CK		 3210 { PCI_DEVICE(0x1d97, 0x2263), /* SPCC */
3211 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
dc22c1c0
ZB		 3212 { PCI_DEVICE(0x2646, 0x2262), /* KINGSTON SKC2000 NVMe SSD */
3213 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
538e4a8c
TL		 3214 { PCI_DEVICE(0x2646, 0x2263), /* KINGSTON A2000 NVMe SSD */
3215 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
4bdf2603
FS		 3216 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0061),
3217 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3218 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0065),
3219 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3220 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x8061),
3221 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3222 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd00),
3223 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3224 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd01),
3225 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3226 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd02),
3227 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
98f7b86a
AS		 3228 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001),
3229 .driver_data = NVME_QUIRK_SINGLE_VECTOR },
124298bd 3230 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
66341331
BH		 3231 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005),
3232 .driver_data = NVME_QUIRK_SINGLE_VECTOR |
d38e9f04
BH		 3233 NVME_QUIRK_128_BYTES_SQES |
3234 NVME_QUIRK_SHARED_TAGS },
0b85f59d
AS		 3235
3236 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
b60503ba
MW		 3237 { 0, }
3238};
3239MODULE_DEVICE_TABLE(pci, nvme_id_table);
3240
3241static struct pci_driver nvme_driver = {
3242 .name = "nvme",
3243 .id_table = nvme_id_table,
3244 .probe = nvme_probe,
8d85fce7 3245 .remove = nvme_remove,
09ece142 3246 .shutdown = nvme_shutdown,
d916b1be 3247#ifdef CONFIG_PM_SLEEP
cd638946
KB		 3248 .driver = {
3249 .pm = &nvme_dev_pm_ops,
3250 },
d916b1be 3251#endif
74d986ab 3252 .sriov_configure = pci_sriov_configure_simple,
b60503ba
MW		 3253 .err_handler = &nvme_err_handler,
3254};
3255
3256static int __init nvme_init(void)
3257{
81101540
CH		 3258 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
3259 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
3260 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
612b7286 3261 BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2);
17c33167 3262
9a6327d2 3263 return pci_register_driver(&nvme_driver);
b60503ba
MW		 3264}
3265
3266static void __exit nvme_exit(void)
3267{
3268 pci_unregister_driver(&nvme_driver);
03e0f3a6 3269 flush_workqueue(nvme_wq);
b60503ba
MW		 3270}
3271
3272MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3273MODULE_LICENSE("GPL");
c78b4713 3274MODULE_VERSION("1.0");
b60503ba
MW		 3275module_init(nvme_init);
3276module_exit(nvme_exit);
Linux 6.x block layer and io_uring tree(s)