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blk-mq: initial support for multiple queue maps
[linux-2.6-block.git] / drivers / nvme / host / pci.c
CommitLineData
b60503ba
MW		 1/*
2 * NVM Express device driver
6eb0d698 3 * Copyright (c) 2011-2014, Intel Corporation.
b60503ba
MW		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
b60503ba
MW		 13 */
14
a0a3408e 15#include <linux/aer.h>
18119775 16#include <linux/async.h>
b60503ba 17#include <linux/blkdev.h>
a4aea562 18#include <linux/blk-mq.h>
dca51e78 19#include <linux/blk-mq-pci.h>
ff5350a8 20#include <linux/dmi.h>
b60503ba
MW		 21#include <linux/init.h>
22#include <linux/interrupt.h>
23#include <linux/io.h>
b60503ba
MW		 24#include <linux/mm.h>
25#include <linux/module.h>
77bf25ea 26#include <linux/mutex.h>
d0877473 27#include <linux/once.h>
b60503ba 28#include <linux/pci.h>
e1e5e564 29#include <linux/t10-pi.h>
b60503ba 30#include <linux/types.h>
2f8e2c87 31#include <linux/io-64-nonatomic-lo-hi.h>
a98e58e5 32#include <linux/sed-opal.h>
0f238ff5 33#include <linux/pci-p2pdma.h>
797a796a 34
f11bb3e2
CH		 35#include "nvme.h"
36
b60503ba
MW		 37#define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
38#define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
c965809c 39
a7a7cbe3 40#define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc))
9d43cf64 41
943e942e
JA		 42/*
43 * These can be higher, but we need to ensure that any command doesn't
44 * require an sg allocation that needs more than a page of data.
45 */
46#define NVME_MAX_KB_SZ 4096
47#define NVME_MAX_SEGS 127
48
58ffacb5
MW		 49static int use_threaded_interrupts;
50module_param(use_threaded_interrupts, int, 0);
51
8ffaadf7 52static bool use_cmb_sqes = true;
69f4eb9f 53module_param(use_cmb_sqes, bool, 0444);
8ffaadf7
JD		 54MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
55
87ad72a5
CH		 56static unsigned int max_host_mem_size_mb = 128;
57module_param(max_host_mem_size_mb, uint, 0444);
58MODULE_PARM_DESC(max_host_mem_size_mb,
59 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
1fa6aead 60
a7a7cbe3
CK		 61static unsigned int sgl_threshold = SZ_32K;
62module_param(sgl_threshold, uint, 0644);
63MODULE_PARM_DESC(sgl_threshold,
64 "Use SGLs when average request segment size is larger or equal to "
65 "this size. Use 0 to disable SGLs.");
66
b27c1e68 67static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
68static const struct kernel_param_ops io_queue_depth_ops = {
69 .set = io_queue_depth_set,
70 .get = param_get_int,
71};
72
73static int io_queue_depth = 1024;
74module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
75MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2");
76
1c63dc66
CH		 77struct nvme_dev;
78struct nvme_queue;
b3fffdef 79
a5cdb68c 80static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
d4b4ff8e 81
1c63dc66
CH		 82/*
83 * Represents an NVM Express device. Each nvme_dev is a PCI function.
84 */
85struct nvme_dev {
147b27e4 86 struct nvme_queue *queues;
1c63dc66
CH		 87 struct blk_mq_tag_set tagset;
88 struct blk_mq_tag_set admin_tagset;
89 u32 __iomem *dbs;
90 struct device *dev;
91 struct dma_pool *prp_page_pool;
92 struct dma_pool *prp_small_pool;
1c63dc66
CH		 93 unsigned online_queues;
94 unsigned max_qid;
22b55601 95 unsigned int num_vecs;
1c63dc66
CH		 96 int q_depth;
97 u32 db_stride;
1c63dc66 98 void __iomem *bar;
97f6ef64 99 unsigned long bar_mapped_size;
5c8809e6 100 struct work_struct remove_work;
77bf25ea 101 struct mutex shutdown_lock;
1c63dc66 102 bool subsystem;
1c63dc66 103 u64 cmb_size;
0f238ff5 104 bool cmb_use_sqes;
1c63dc66 105 u32 cmbsz;
202021c1 106 u32 cmbloc;
1c63dc66 107 struct nvme_ctrl ctrl;
db3cbfff 108 struct completion ioq_wait;
87ad72a5 109
943e942e
JA		 110 mempool_t *iod_mempool;
111
87ad72a5 112 /* shadow doorbell buffer support: */
f9f38e33
HK		 113 u32 *dbbuf_dbs;
114 dma_addr_t dbbuf_dbs_dma_addr;
115 u32 *dbbuf_eis;
116 dma_addr_t dbbuf_eis_dma_addr;
87ad72a5
CH		 117
118 /* host memory buffer support: */
119 u64 host_mem_size;
120 u32 nr_host_mem_descs;
4033f35d 121 dma_addr_t host_mem_descs_dma;
87ad72a5
CH		 122 struct nvme_host_mem_buf_desc *host_mem_descs;
123 void **host_mem_desc_bufs;
4d115420 124};
1fa6aead 125
b27c1e68 126static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
127{
128 int n = 0, ret;
129
130 ret = kstrtoint(val, 10, &n);
131 if (ret != 0 || n < 2)
132 return -EINVAL;
133
134 return param_set_int(val, kp);
135}
136
f9f38e33
HK		 137static inline unsigned int sq_idx(unsigned int qid, u32 stride)
138{
139 return qid * 2 * stride;
140}
141
142static inline unsigned int cq_idx(unsigned int qid, u32 stride)
143{
144 return (qid * 2 + 1) * stride;
145}
146
1c63dc66
CH		 147static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
148{
149 return container_of(ctrl, struct nvme_dev, ctrl);
150}
151
b60503ba
MW		 152/*
153 * An NVM Express queue. Each device has at least two (one for admin
154 * commands and one for I/O commands).
155 */
156struct nvme_queue {
157 struct device *q_dmadev;
091b6092 158 struct nvme_dev *dev;
1ab0cd69 159 spinlock_t sq_lock;
b60503ba 160 struct nvme_command *sq_cmds;
0f238ff5 161 bool sq_cmds_is_io;
1ab0cd69 162 spinlock_t cq_lock ____cacheline_aligned_in_smp;
b60503ba 163 volatile struct nvme_completion *cqes;
42483228 164 struct blk_mq_tags **tags;
b60503ba
MW		 165 dma_addr_t sq_dma_addr;
166 dma_addr_t cq_dma_addr;
b60503ba
MW		 167 u32 __iomem *q_db;
168 u16 q_depth;
6222d172 169 s16 cq_vector;
b60503ba
MW		 170 u16 sq_tail;
171 u16 cq_head;
68fa9dbe 172 u16 last_cq_head;
c30341dc 173 u16 qid;
e9539f47 174 u8 cq_phase;
f9f38e33
HK		 175 u32 *dbbuf_sq_db;
176 u32 *dbbuf_cq_db;
177 u32 *dbbuf_sq_ei;
178 u32 *dbbuf_cq_ei;
b60503ba
MW		 179};
180
71bd150c
CH		 181/*
182 * The nvme_iod describes the data in an I/O, including the list of PRP
183 * entries. You can't see it in this data structure because C doesn't let
f4800d6d 184 * me express that. Use nvme_init_iod to ensure there's enough space
71bd150c
CH		 185 * allocated to store the PRP list.
186 */
187struct nvme_iod {
d49187e9 188 struct nvme_request req;
f4800d6d 189 struct nvme_queue *nvmeq;
a7a7cbe3 190 bool use_sgl;
f4800d6d 191 int aborted;
71bd150c 192 int npages; /* In the PRP list. 0 means small pool in use */
71bd150c
CH		 193 int nents; /* Used in scatterlist */
194 int length; /* Of data, in bytes */
195 dma_addr_t first_dma;
bf684057 196 struct scatterlist meta_sg; /* metadata requires single contiguous buffer */
f4800d6d
CH		 197 struct scatterlist *sg;
198 struct scatterlist inline_sg[0];
b60503ba
MW		 199};
200
201/*
202 * Check we didin't inadvertently grow the command struct
203 */
204static inline void _nvme_check_size(void)
205{
206 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
207 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
208 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
209 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
210 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
f8ebf840 211 BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
c30341dc 212 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
b60503ba 213 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
0add5e8e
JT		 214 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != NVME_IDENTIFY_DATA_SIZE);
215 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != NVME_IDENTIFY_DATA_SIZE);
b60503ba 216 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
6ecec745 217 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
f9f38e33
HK		 218 BUILD_BUG_ON(sizeof(struct nvme_dbbuf) != 64);
219}
220
221static inline unsigned int nvme_dbbuf_size(u32 stride)
222{
223 return ((num_possible_cpus() + 1) * 8 * stride);
224}
225
226static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
227{
228 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
229
230 if (dev->dbbuf_dbs)
231 return 0;
232
233 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
234 &dev->dbbuf_dbs_dma_addr,
235 GFP_KERNEL);
236 if (!dev->dbbuf_dbs)
237 return -ENOMEM;
238 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
239 &dev->dbbuf_eis_dma_addr,
240 GFP_KERNEL);
241 if (!dev->dbbuf_eis) {
242 dma_free_coherent(dev->dev, mem_size,
243 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
244 dev->dbbuf_dbs = NULL;
245 return -ENOMEM;
246 }
247
248 return 0;
249}
250
251static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
252{
253 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
254
255 if (dev->dbbuf_dbs) {
256 dma_free_coherent(dev->dev, mem_size,
257 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
258 dev->dbbuf_dbs = NULL;
259 }
260 if (dev->dbbuf_eis) {
261 dma_free_coherent(dev->dev, mem_size,
262 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
263 dev->dbbuf_eis = NULL;
264 }
265}
266
267static void nvme_dbbuf_init(struct nvme_dev *dev,
268 struct nvme_queue *nvmeq, int qid)
269{
270 if (!dev->dbbuf_dbs || !qid)
271 return;
272
273 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
274 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
275 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
276 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
277}
278
279static void nvme_dbbuf_set(struct nvme_dev *dev)
280{
281 struct nvme_command c;
282
283 if (!dev->dbbuf_dbs)
284 return;
285
286 memset(&c, 0, sizeof(c));
287 c.dbbuf.opcode = nvme_admin_dbbuf;
288 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
289 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
290
291 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
9bdcfb10 292 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
f9f38e33
HK		 293 /* Free memory and continue on */
294 nvme_dbbuf_dma_free(dev);
295 }
296}
297
298static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
299{
300 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
301}
302
303/* Update dbbuf and return true if an MMIO is required */
304static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
305 volatile u32 *dbbuf_ei)
306{
307 if (dbbuf_db) {
308 u16 old_value;
309
310 /*
311 * Ensure that the queue is written before updating
312 * the doorbell in memory
313 */
314 wmb();
315
316 old_value = *dbbuf_db;
317 *dbbuf_db = value;
318
f1ed3df2
MW		 319 /*
320 * Ensure that the doorbell is updated before reading the event
321 * index from memory. The controller needs to provide similar
322 * ordering to ensure the envent index is updated before reading
323 * the doorbell.
324 */
325 mb();
326
f9f38e33
HK		 327 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value))
328 return false;
329 }
330
331 return true;
b60503ba
MW		 332}
333
ac3dd5bd
JA		 334/*
335 * Max size of iod being embedded in the request payload
336 */
337#define NVME_INT_PAGES 2
5fd4ce1b 338#define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size)
ac3dd5bd
JA		 339
340/*
341 * Will slightly overestimate the number of pages needed. This is OK
342 * as it only leads to a small amount of wasted memory for the lifetime of
343 * the I/O.
344 */
345static int nvme_npages(unsigned size, struct nvme_dev *dev)
346{
5fd4ce1b
CH		 347 unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size,
348 dev->ctrl.page_size);
ac3dd5bd
JA		 349 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
350}
351
a7a7cbe3
CK		 352/*
353 * Calculates the number of pages needed for the SGL segments. For example a 4k
354 * page can accommodate 256 SGL descriptors.
355 */
356static int nvme_pci_npages_sgl(unsigned int num_seg)
ac3dd5bd 357{
a7a7cbe3 358 return DIV_ROUND_UP(num_seg * sizeof(struct nvme_sgl_desc), PAGE_SIZE);
f4800d6d 359}
ac3dd5bd 360
a7a7cbe3
CK		 361static unsigned int nvme_pci_iod_alloc_size(struct nvme_dev *dev,
362 unsigned int size, unsigned int nseg, bool use_sgl)
f4800d6d 363{
a7a7cbe3
CK		 364 size_t alloc_size;
365
366 if (use_sgl)
367 alloc_size = sizeof(__le64 *) * nvme_pci_npages_sgl(nseg);
368 else
369 alloc_size = sizeof(__le64 *) * nvme_npages(size, dev);
370
371 return alloc_size + sizeof(struct scatterlist) * nseg;
f4800d6d 372}
ac3dd5bd 373
a7a7cbe3 374static unsigned int nvme_pci_cmd_size(struct nvme_dev *dev, bool use_sgl)
f4800d6d 375{
a7a7cbe3
CK		 376 unsigned int alloc_size = nvme_pci_iod_alloc_size(dev,
377 NVME_INT_BYTES(dev), NVME_INT_PAGES,
378 use_sgl);
379
380 return sizeof(struct nvme_iod) + alloc_size;
ac3dd5bd
JA		 381}
382
a4aea562
MB		 383static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
384 unsigned int hctx_idx)
e85248e5 385{
a4aea562 386 struct nvme_dev *dev = data;
147b27e4 387 struct nvme_queue *nvmeq = &dev->queues[0];
a4aea562 388
42483228
KB		 389 WARN_ON(hctx_idx != 0);
390 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
391 WARN_ON(nvmeq->tags);
392
a4aea562 393 hctx->driver_data = nvmeq;
42483228 394 nvmeq->tags = &dev->admin_tagset.tags[0];
a4aea562 395 return 0;
e85248e5
MW		 396}
397
4af0e21c
KB		 398static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
399{
400 struct nvme_queue *nvmeq = hctx->driver_data;
401
402 nvmeq->tags = NULL;
403}
404
a4aea562
MB		 405static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
406 unsigned int hctx_idx)
b60503ba 407{
a4aea562 408 struct nvme_dev *dev = data;
147b27e4 409 struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
a4aea562 410
42483228
KB		 411 if (!nvmeq->tags)
412 nvmeq->tags = &dev->tagset.tags[hctx_idx];
b60503ba 413
42483228 414 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
a4aea562
MB		 415 hctx->driver_data = nvmeq;
416 return 0;
b60503ba
MW		 417}
418
d6296d39
CH		 419static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req,
420 unsigned int hctx_idx, unsigned int numa_node)
b60503ba 421{
d6296d39 422 struct nvme_dev *dev = set->driver_data;
f4800d6d 423 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
0350815a 424 int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0;
147b27e4 425 struct nvme_queue *nvmeq = &dev->queues[queue_idx];
a4aea562
MB		 426
427 BUG_ON(!nvmeq);
f4800d6d 428 iod->nvmeq = nvmeq;
59e29ce6
SG		 429
430 nvme_req(req)->ctrl = &dev->ctrl;
a4aea562
MB		 431 return 0;
432}
433
dca51e78
CH		 434static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
435{
436 struct nvme_dev *dev = set->driver_data;
437
ed76e329 438 return blk_mq_pci_map_queues(&set->map[0], to_pci_dev(dev->dev),
22b55601 439 dev->num_vecs > 1 ? 1 /* admin queue */ : 0);
dca51e78
CH		 440}
441
b60503ba 442/**
90ea5ca4 443 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
b60503ba
MW		 444 * @nvmeq: The queue to use
445 * @cmd: The command to send
b60503ba 446 */
90ea5ca4 447static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
b60503ba 448{
90ea5ca4 449 spin_lock(&nvmeq->sq_lock);
0f238ff5
LG		 450
451 memcpy(&nvmeq->sq_cmds[nvmeq->sq_tail], cmd, sizeof(*cmd));
8ffaadf7 452
90ea5ca4
CH		 453 if (++nvmeq->sq_tail == nvmeq->q_depth)
454 nvmeq->sq_tail = 0;
455 if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail,
456 nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei))
457 writel(nvmeq->sq_tail, nvmeq->q_db);
458 spin_unlock(&nvmeq->sq_lock);
b60503ba
MW		 459}
460
a7a7cbe3 461static void **nvme_pci_iod_list(struct request *req)
b60503ba 462{
f4800d6d 463 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3 464 return (void **)(iod->sg + blk_rq_nr_phys_segments(req));
b60503ba
MW		 465}
466
955b1b5a
MI		 467static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req)
468{
469 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
20469a37 470 int nseg = blk_rq_nr_phys_segments(req);
955b1b5a
MI		 471 unsigned int avg_seg_size;
472
20469a37
KB		 473 if (nseg == 0)
474 return false;
475
476 avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
955b1b5a
MI		 477
478 if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1))))
479 return false;
480 if (!iod->nvmeq->qid)
481 return false;
482 if (!sgl_threshold || avg_seg_size < sgl_threshold)
483 return false;
484 return true;
485}
486
fc17b653 487static blk_status_t nvme_init_iod(struct request *rq, struct nvme_dev *dev)
ac3dd5bd 488{
f4800d6d 489 struct nvme_iod *iod = blk_mq_rq_to_pdu(rq);
f9d03f96 490 int nseg = blk_rq_nr_phys_segments(rq);
b131c61d 491 unsigned int size = blk_rq_payload_bytes(rq);
ac3dd5bd 492
955b1b5a
MI		 493 iod->use_sgl = nvme_pci_use_sgls(dev, rq);
494
f4800d6d 495 if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) {
943e942e 496 iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC);
f4800d6d 497 if (!iod->sg)
fc17b653 498 return BLK_STS_RESOURCE;
f4800d6d
CH		 499 } else {
500 iod->sg = iod->inline_sg;
ac3dd5bd
JA		 501 }
502
f4800d6d
CH		 503 iod->aborted = 0;
504 iod->npages = -1;
505 iod->nents = 0;
506 iod->length = size;
f80ec966 507
fc17b653 508 return BLK_STS_OK;
ac3dd5bd
JA		 509}
510
f4800d6d 511static void nvme_free_iod(struct nvme_dev *dev, struct request *req)
b60503ba 512{
f4800d6d 513 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3
CK		 514 const int last_prp = dev->ctrl.page_size / sizeof(__le64) - 1;
515 dma_addr_t dma_addr = iod->first_dma, next_dma_addr;
516
eca18b23 517 int i;
eca18b23
MW		 518
519 if (iod->npages == 0)
a7a7cbe3
CK		 520 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0],
521 dma_addr);
522
eca18b23 523 for (i = 0; i < iod->npages; i++) {
a7a7cbe3
CK		 524 void *addr = nvme_pci_iod_list(req)[i];
525
526 if (iod->use_sgl) {
527 struct nvme_sgl_desc *sg_list = addr;
528
529 next_dma_addr =
530 le64_to_cpu((sg_list[SGES_PER_PAGE - 1]).addr);
531 } else {
532 __le64 *prp_list = addr;
533
534 next_dma_addr = le64_to_cpu(prp_list[last_prp]);
535 }
536
537 dma_pool_free(dev->prp_page_pool, addr, dma_addr);
538 dma_addr = next_dma_addr;
eca18b23 539 }
ac3dd5bd 540
f4800d6d 541 if (iod->sg != iod->inline_sg)
943e942e 542 mempool_free(iod->sg, dev->iod_mempool);
b4ff9c8d
KB		 543}
544
d0877473
KB		 545static void nvme_print_sgl(struct scatterlist *sgl, int nents)
546{
547 int i;
548 struct scatterlist *sg;
549
550 for_each_sg(sgl, sg, nents, i) {
551 dma_addr_t phys = sg_phys(sg);
552 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
553 "dma_address:%pad dma_length:%d\n",
554 i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
555 sg_dma_len(sg));
556 }
557}
558
a7a7cbe3
CK		 559static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
560 struct request *req, struct nvme_rw_command *cmnd)
ff22b54f 561{
f4800d6d 562 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
99802a7a 563 struct dma_pool *pool;
b131c61d 564 int length = blk_rq_payload_bytes(req);
eca18b23 565 struct scatterlist *sg = iod->sg;
ff22b54f
MW		 566 int dma_len = sg_dma_len(sg);
567 u64 dma_addr = sg_dma_address(sg);
5fd4ce1b 568 u32 page_size = dev->ctrl.page_size;
f137e0f1 569 int offset = dma_addr & (page_size - 1);
e025344c 570 __le64 *prp_list;
a7a7cbe3 571 void **list = nvme_pci_iod_list(req);
e025344c 572 dma_addr_t prp_dma;
eca18b23 573 int nprps, i;
ff22b54f 574
1d090624 575 length -= (page_size - offset);
5228b328
JS		 576 if (length <= 0) {
577 iod->first_dma = 0;
a7a7cbe3 578 goto done;
5228b328 579 }
ff22b54f 580
1d090624 581 dma_len -= (page_size - offset);
ff22b54f 582 if (dma_len) {
1d090624 583 dma_addr += (page_size - offset);
ff22b54f
MW		 584 } else {
585 sg = sg_next(sg);
586 dma_addr = sg_dma_address(sg);
587 dma_len = sg_dma_len(sg);
588 }
589
1d090624 590 if (length <= page_size) {
edd10d33 591 iod->first_dma = dma_addr;
a7a7cbe3 592 goto done;
e025344c
SMM		 593 }
594
1d090624 595 nprps = DIV_ROUND_UP(length, page_size);
99802a7a
MW		 596 if (nprps <= (256 / 8)) {
597 pool = dev->prp_small_pool;
eca18b23 598 iod->npages = 0;
99802a7a
MW		 599 } else {
600 pool = dev->prp_page_pool;
eca18b23 601 iod->npages = 1;
99802a7a
MW		 602 }
603
69d2b571 604 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
b77954cb 605 if (!prp_list) {
edd10d33 606 iod->first_dma = dma_addr;
eca18b23 607 iod->npages = -1;
86eea289 608 return BLK_STS_RESOURCE;
b77954cb 609 }
eca18b23
MW		 610 list[0] = prp_list;
611 iod->first_dma = prp_dma;
e025344c
SMM		 612 i = 0;
613 for (;;) {
1d090624 614 if (i == page_size >> 3) {
e025344c 615 __le64 *old_prp_list = prp_list;
69d2b571 616 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
eca18b23 617 if (!prp_list)
86eea289 618 return BLK_STS_RESOURCE;
eca18b23 619 list[iod->npages++] = prp_list;
7523d834
MW		 620 prp_list[0] = old_prp_list[i - 1];
621 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
622 i = 1;
e025344c
SMM		 623 }
624 prp_list[i++] = cpu_to_le64(dma_addr);
1d090624
KB		 625 dma_len -= page_size;
626 dma_addr += page_size;
627 length -= page_size;
e025344c
SMM		 628 if (length <= 0)
629 break;
630 if (dma_len > 0)
631 continue;
86eea289
KB		 632 if (unlikely(dma_len < 0))
633 goto bad_sgl;
e025344c
SMM		 634 sg = sg_next(sg);
635 dma_addr = sg_dma_address(sg);
636 dma_len = sg_dma_len(sg);
ff22b54f
MW		 637 }
638
a7a7cbe3
CK		 639done:
640 cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
641 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
642
86eea289
KB		 643 return BLK_STS_OK;
644
645 bad_sgl:
d0877473
KB		 646 WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents),
647 "Invalid SGL for payload:%d nents:%d\n",
648 blk_rq_payload_bytes(req), iod->nents);
86eea289 649 return BLK_STS_IOERR;
ff22b54f
MW		 650}
651
a7a7cbe3
CK		 652static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
653 struct scatterlist *sg)
654{
655 sge->addr = cpu_to_le64(sg_dma_address(sg));
656 sge->length = cpu_to_le32(sg_dma_len(sg));
657 sge->type = NVME_SGL_FMT_DATA_DESC << 4;
658}
659
660static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
661 dma_addr_t dma_addr, int entries)
662{
663 sge->addr = cpu_to_le64(dma_addr);
664 if (entries < SGES_PER_PAGE) {
665 sge->length = cpu_to_le32(entries * sizeof(*sge));
666 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
667 } else {
668 sge->length = cpu_to_le32(PAGE_SIZE);
669 sge->type = NVME_SGL_FMT_SEG_DESC << 4;
670 }
671}
672
673static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
b0f2853b 674 struct request *req, struct nvme_rw_command *cmd, int entries)
a7a7cbe3
CK		 675{
676 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3
CK		 677 struct dma_pool *pool;
678 struct nvme_sgl_desc *sg_list;
679 struct scatterlist *sg = iod->sg;
a7a7cbe3 680 dma_addr_t sgl_dma;
b0f2853b 681 int i = 0;
a7a7cbe3 682
a7a7cbe3
CK		 683 /* setting the transfer type as SGL */
684 cmd->flags = NVME_CMD_SGL_METABUF;
685
b0f2853b 686 if (entries == 1) {
a7a7cbe3
CK		 687 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
688 return BLK_STS_OK;
689 }
690
691 if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
692 pool = dev->prp_small_pool;
693 iod->npages = 0;
694 } else {
695 pool = dev->prp_page_pool;
696 iod->npages = 1;
697 }
698
699 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
700 if (!sg_list) {
701 iod->npages = -1;
702 return BLK_STS_RESOURCE;
703 }
704
705 nvme_pci_iod_list(req)[0] = sg_list;
706 iod->first_dma = sgl_dma;
707
708 nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
709
710 do {
711 if (i == SGES_PER_PAGE) {
712 struct nvme_sgl_desc *old_sg_desc = sg_list;
713 struct nvme_sgl_desc *link = &old_sg_desc[i - 1];
714
715 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
716 if (!sg_list)
717 return BLK_STS_RESOURCE;
718
719 i = 0;
720 nvme_pci_iod_list(req)[iod->npages++] = sg_list;
721 sg_list[i++] = *link;
722 nvme_pci_sgl_set_seg(link, sgl_dma, entries);
723 }
724
725 nvme_pci_sgl_set_data(&sg_list[i++], sg);
a7a7cbe3 726 sg = sg_next(sg);
b0f2853b 727 } while (--entries > 0);
a7a7cbe3 728
a7a7cbe3
CK		 729 return BLK_STS_OK;
730}
731
fc17b653 732static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
b131c61d 733 struct nvme_command *cmnd)
d29ec824 734{
f4800d6d 735 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
ba1ca37e
CH		 736 struct request_queue *q = req->q;
737 enum dma_data_direction dma_dir = rq_data_dir(req) ?
738 DMA_TO_DEVICE : DMA_FROM_DEVICE;
fc17b653 739 blk_status_t ret = BLK_STS_IOERR;
b0f2853b 740 int nr_mapped;
d29ec824 741
f9d03f96 742 sg_init_table(iod->sg, blk_rq_nr_phys_segments(req));
ba1ca37e
CH		 743 iod->nents = blk_rq_map_sg(q, req, iod->sg);
744 if (!iod->nents)
745 goto out;
d29ec824 746
fc17b653 747 ret = BLK_STS_RESOURCE;
e0596ab2
LG		 748
749 if (is_pci_p2pdma_page(sg_page(iod->sg)))
750 nr_mapped = pci_p2pdma_map_sg(dev->dev, iod->sg, iod->nents,
751 dma_dir);
752 else
753 nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents,
754 dma_dir, DMA_ATTR_NO_WARN);
b0f2853b 755 if (!nr_mapped)
ba1ca37e 756 goto out;
d29ec824 757
955b1b5a 758 if (iod->use_sgl)
b0f2853b 759 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped);
a7a7cbe3
CK		 760 else
761 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
762
86eea289 763 if (ret != BLK_STS_OK)
ba1ca37e 764 goto out_unmap;
0e5e4f0e 765
fc17b653 766 ret = BLK_STS_IOERR;
ba1ca37e
CH		 767 if (blk_integrity_rq(req)) {
768 if (blk_rq_count_integrity_sg(q, req->bio) != 1)
769 goto out_unmap;
0e5e4f0e 770
bf684057
CH		 771 sg_init_table(&iod->meta_sg, 1);
772 if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1)
ba1ca37e 773 goto out_unmap;
0e5e4f0e 774
bf684057 775 if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir))
ba1ca37e 776 goto out_unmap;
00df5cb4 777
bf684057 778 cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg));
3045c0d0
CK		 779 }
780
fc17b653 781 return BLK_STS_OK;
00df5cb4 782
ba1ca37e
CH		 783out_unmap:
784 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
785out:
786 return ret;
00df5cb4
MW		 787}
788
f4800d6d 789static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
b60503ba 790{
f4800d6d 791 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
d4f6c3ab
CH		 792 enum dma_data_direction dma_dir = rq_data_dir(req) ?
793 DMA_TO_DEVICE : DMA_FROM_DEVICE;
794
795 if (iod->nents) {
e0596ab2
LG		 796 /* P2PDMA requests do not need to be unmapped */
797 if (!is_pci_p2pdma_page(sg_page(iod->sg)))
798 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
799
f7f1fc36 800 if (blk_integrity_rq(req))
bf684057 801 dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir);
e19b127f 802 }
e1e5e564 803
f9d03f96 804 nvme_cleanup_cmd(req);
f4800d6d 805 nvme_free_iod(dev, req);
d4f6c3ab 806}
b60503ba 807
d29ec824
CH		 808/*
809 * NOTE: ns is NULL when called on the admin queue.
810 */
fc17b653 811static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
a4aea562 812 const struct blk_mq_queue_data *bd)
edd10d33 813{
a4aea562
MB		 814 struct nvme_ns *ns = hctx->queue->queuedata;
815 struct nvme_queue *nvmeq = hctx->driver_data;
d29ec824 816 struct nvme_dev *dev = nvmeq->dev;
a4aea562 817 struct request *req = bd->rq;
ba1ca37e 818 struct nvme_command cmnd;
ebe6d874 819 blk_status_t ret;
e1e5e564 820
d1f06f4a
JA		 821 /*
822 * We should not need to do this, but we're still using this to
823 * ensure we can drain requests on a dying queue.
824 */
825 if (unlikely(nvmeq->cq_vector < 0))
826 return BLK_STS_IOERR;
827
f9d03f96 828 ret = nvme_setup_cmd(ns, req, &cmnd);
fc17b653 829 if (ret)
f4800d6d 830 return ret;
a4aea562 831
b131c61d 832 ret = nvme_init_iod(req, dev);
fc17b653 833 if (ret)
f9d03f96 834 goto out_free_cmd;
a4aea562 835
fc17b653 836 if (blk_rq_nr_phys_segments(req)) {
b131c61d 837 ret = nvme_map_data(dev, req, &cmnd);
fc17b653
CH		 838 if (ret)
839 goto out_cleanup_iod;
840 }
a4aea562 841
aae239e1 842 blk_mq_start_request(req);
90ea5ca4 843 nvme_submit_cmd(nvmeq, &cmnd);
fc17b653 844 return BLK_STS_OK;
f9d03f96 845out_cleanup_iod:
f4800d6d 846 nvme_free_iod(dev, req);
f9d03f96
CH		 847out_free_cmd:
848 nvme_cleanup_cmd(req);
ba1ca37e 849 return ret;
b60503ba 850}
e1e5e564 851
77f02a7a 852static void nvme_pci_complete_rq(struct request *req)
eee417b0 853{
f4800d6d 854 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a4aea562 855
77f02a7a
CH		 856 nvme_unmap_data(iod->nvmeq->dev, req);
857 nvme_complete_rq(req);
b60503ba
MW		 858}
859
d783e0bd 860/* We read the CQE phase first to check if the rest of the entry is valid */
750dde44 861static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq)
d783e0bd 862{
750dde44
CH		 863 return (le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) ==
864 nvmeq->cq_phase;
d783e0bd
MR		 865}
866
eb281c82 867static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
b60503ba 868{
eb281c82 869 u16 head = nvmeq->cq_head;
adf68f21 870
397c699f
KB		 871 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
872 nvmeq->dbbuf_cq_ei))
873 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
eb281c82 874}
aae239e1 875
5cb525c8 876static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx)
83a12fb7 877{
5cb525c8 878 volatile struct nvme_completion *cqe = &nvmeq->cqes[idx];
83a12fb7 879 struct request *req;
adf68f21 880
83a12fb7
SG		 881 if (unlikely(cqe->command_id >= nvmeq->q_depth)) {
882 dev_warn(nvmeq->dev->ctrl.device,
883 "invalid id %d completed on queue %d\n",
884 cqe->command_id, le16_to_cpu(cqe->sq_id));
885 return;
b60503ba
MW		 886 }
887
83a12fb7
SG		 888 /*
889 * AEN requests are special as they don't time out and can
890 * survive any kind of queue freeze and often don't respond to
891 * aborts. We don't even bother to allocate a struct request
892 * for them but rather special case them here.
893 */
894 if (unlikely(nvmeq->qid == 0 &&
38dabe21 895 cqe->command_id >= NVME_AQ_BLK_MQ_DEPTH)) {
83a12fb7
SG		 896 nvme_complete_async_event(&nvmeq->dev->ctrl,
897 cqe->status, &cqe->result);
a0fa9647 898 return;
83a12fb7 899 }
b60503ba 900
83a12fb7
SG		 901 req = blk_mq_tag_to_rq(*nvmeq->tags, cqe->command_id);
902 nvme_end_request(req, cqe->status, cqe->result);
903}
b60503ba 904
5cb525c8 905static void nvme_complete_cqes(struct nvme_queue *nvmeq, u16 start, u16 end)
b60503ba 906{
5cb525c8
JA		 907 while (start != end) {
908 nvme_handle_cqe(nvmeq, start);
909 if (++start == nvmeq->q_depth)
910 start = 0;
911 }
912}
adf68f21 913
5cb525c8
JA		 914static inline void nvme_update_cq_head(struct nvme_queue *nvmeq)
915{
916 if (++nvmeq->cq_head == nvmeq->q_depth) {
917 nvmeq->cq_head = 0;
918 nvmeq->cq_phase = !nvmeq->cq_phase;
b60503ba 919 }
a0fa9647
JA		 920}
921
5cb525c8
JA		 922static inline bool nvme_process_cq(struct nvme_queue *nvmeq, u16 *start,
923 u16 *end, int tag)
a0fa9647 924{
5cb525c8 925 bool found = false;
b60503ba 926
5cb525c8
JA		 927 *start = nvmeq->cq_head;
928 while (!found && nvme_cqe_pending(nvmeq)) {
929 if (nvmeq->cqes[nvmeq->cq_head].command_id == tag)
930 found = true;
931 nvme_update_cq_head(nvmeq);
920d13a8 932 }
5cb525c8 933 *end = nvmeq->cq_head;
eb281c82 934
5cb525c8 935 if (*start != *end)
920d13a8 936 nvme_ring_cq_doorbell(nvmeq);
5cb525c8 937 return found;
b60503ba
MW		 938}
939
940static irqreturn_t nvme_irq(int irq, void *data)
58ffacb5 941{
58ffacb5 942 struct nvme_queue *nvmeq = data;
68fa9dbe 943 irqreturn_t ret = IRQ_NONE;
5cb525c8
JA		 944 u16 start, end;
945
1ab0cd69 946 spin_lock(&nvmeq->cq_lock);
68fa9dbe
JA		 947 if (nvmeq->cq_head != nvmeq->last_cq_head)
948 ret = IRQ_HANDLED;
5cb525c8 949 nvme_process_cq(nvmeq, &start, &end, -1);
68fa9dbe 950 nvmeq->last_cq_head = nvmeq->cq_head;
1ab0cd69 951 spin_unlock(&nvmeq->cq_lock);
5cb525c8 952
68fa9dbe
JA		 953 if (start != end) {
954 nvme_complete_cqes(nvmeq, start, end);
955 return IRQ_HANDLED;
956 }
957
958 return ret;
58ffacb5
MW		 959}
960
961static irqreturn_t nvme_irq_check(int irq, void *data)
962{
963 struct nvme_queue *nvmeq = data;
750dde44 964 if (nvme_cqe_pending(nvmeq))
d783e0bd
MR		 965 return IRQ_WAKE_THREAD;
966 return IRQ_NONE;
58ffacb5
MW		 967}
968
7776db1c 969static int __nvme_poll(struct nvme_queue *nvmeq, unsigned int tag)
a0fa9647 970{
5cb525c8
JA		 971 u16 start, end;
972 bool found;
a0fa9647 973
750dde44 974 if (!nvme_cqe_pending(nvmeq))
442e19b7 975 return 0;
a0fa9647 976
1ab0cd69 977 spin_lock_irq(&nvmeq->cq_lock);
5cb525c8 978 found = nvme_process_cq(nvmeq, &start, &end, tag);
1ab0cd69 979 spin_unlock_irq(&nvmeq->cq_lock);
442e19b7 980
5cb525c8 981 nvme_complete_cqes(nvmeq, start, end);
442e19b7 982 return found;
a0fa9647
JA		 983}
984
7776db1c
KB		 985static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag)
986{
987 struct nvme_queue *nvmeq = hctx->driver_data;
988
989 return __nvme_poll(nvmeq, tag);
990}
991
ad22c355 992static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
b60503ba 993{
f866fc42 994 struct nvme_dev *dev = to_nvme_dev(ctrl);
147b27e4 995 struct nvme_queue *nvmeq = &dev->queues[0];
a4aea562 996 struct nvme_command c;
b60503ba 997
a4aea562
MB		 998 memset(&c, 0, sizeof(c));
999 c.common.opcode = nvme_admin_async_event;
ad22c355 1000 c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
90ea5ca4 1001 nvme_submit_cmd(nvmeq, &c);
f705f837
CH		 1002}
1003
b60503ba 1004static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
f705f837 1005{
b60503ba
MW		 1006 struct nvme_command c;
1007
1008 memset(&c, 0, sizeof(c));
1009 c.delete_queue.opcode = opcode;
1010 c.delete_queue.qid = cpu_to_le16(id);
1011
1c63dc66 1012 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1013}
1014
b60503ba 1015static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
a8e3e0bb 1016 struct nvme_queue *nvmeq, s16 vector)
b60503ba 1017{
b60503ba
MW		 1018 struct nvme_command c;
1019 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
1020
d29ec824 1021 /*
16772ae6 1022 * Note: we (ab)use the fact that the prp fields survive if no data
d29ec824
CH		 1023 * is attached to the request.
1024 */
b60503ba
MW		 1025 memset(&c, 0, sizeof(c));
1026 c.create_cq.opcode = nvme_admin_create_cq;
1027 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1028 c.create_cq.cqid = cpu_to_le16(qid);
1029 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1030 c.create_cq.cq_flags = cpu_to_le16(flags);
a8e3e0bb 1031 c.create_cq.irq_vector = cpu_to_le16(vector);
b60503ba 1032
1c63dc66 1033 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1034}
1035
1036static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1037 struct nvme_queue *nvmeq)
1038{
9abd68ef 1039 struct nvme_ctrl *ctrl = &dev->ctrl;
b60503ba 1040 struct nvme_command c;
81c1cd98 1041 int flags = NVME_QUEUE_PHYS_CONTIG;
b60503ba 1042
9abd68ef
JA		 1043 /*
1044 * Some drives have a bug that auto-enables WRRU if MEDIUM isn't
1045 * set. Since URGENT priority is zeroes, it makes all queues
1046 * URGENT.
1047 */
1048 if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ)
1049 flags |= NVME_SQ_PRIO_MEDIUM;
1050
d29ec824 1051 /*
16772ae6 1052 * Note: we (ab)use the fact that the prp fields survive if no data
d29ec824
CH		 1053 * is attached to the request.
1054 */
b60503ba
MW		 1055 memset(&c, 0, sizeof(c));
1056 c.create_sq.opcode = nvme_admin_create_sq;
1057 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1058 c.create_sq.sqid = cpu_to_le16(qid);
1059 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1060 c.create_sq.sq_flags = cpu_to_le16(flags);
1061 c.create_sq.cqid = cpu_to_le16(qid);
1062
1c63dc66 1063 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1064}
1065
1066static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1067{
1068 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1069}
1070
1071static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1072{
1073 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1074}
1075
2a842aca 1076static void abort_endio(struct request *req, blk_status_t error)
bc5fc7e4 1077{
f4800d6d
CH		 1078 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1079 struct nvme_queue *nvmeq = iod->nvmeq;
e44ac588 1080
27fa9bc5
CH		 1081 dev_warn(nvmeq->dev->ctrl.device,
1082 "Abort status: 0x%x", nvme_req(req)->status);
e7a2a87d 1083 atomic_inc(&nvmeq->dev->ctrl.abort_limit);
e7a2a87d 1084 blk_mq_free_request(req);
bc5fc7e4
MW		 1085}
1086
b2a0eb1a
KB		 1087static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1088{
1089
1090 /* If true, indicates loss of adapter communication, possibly by a
1091 * NVMe Subsystem reset.
1092 */
1093 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1094
ad70062c
JW		 1095 /* If there is a reset/reinit ongoing, we shouldn't reset again. */
1096 switch (dev->ctrl.state) {
1097 case NVME_CTRL_RESETTING:
ad6a0a52 1098 case NVME_CTRL_CONNECTING:
b2a0eb1a 1099 return false;
ad70062c
JW		 1100 default:
1101 break;
1102 }
b2a0eb1a
KB		 1103
1104 /* We shouldn't reset unless the controller is on fatal error state
1105 * _or_ if we lost the communication with it.
1106 */
1107 if (!(csts & NVME_CSTS_CFS) && !nssro)
1108 return false;
1109
b2a0eb1a
KB		 1110 return true;
1111}
1112
1113static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1114{
1115 /* Read a config register to help see what died. */
1116 u16 pci_status;
1117 int result;
1118
1119 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1120 &pci_status);
1121 if (result == PCIBIOS_SUCCESSFUL)
1122 dev_warn(dev->ctrl.device,
1123 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1124 csts, pci_status);
1125 else
1126 dev_warn(dev->ctrl.device,
1127 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1128 csts, result);
1129}
1130
31c7c7d2 1131static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
c30341dc 1132{
f4800d6d
CH		 1133 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1134 struct nvme_queue *nvmeq = iod->nvmeq;
c30341dc 1135 struct nvme_dev *dev = nvmeq->dev;
a4aea562 1136 struct request *abort_req;
a4aea562 1137 struct nvme_command cmd;
b2a0eb1a
KB		 1138 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1139
651438bb
WX		 1140 /* If PCI error recovery process is happening, we cannot reset or
1141 * the recovery mechanism will surely fail.
1142 */
1143 mb();
1144 if (pci_channel_offline(to_pci_dev(dev->dev)))
1145 return BLK_EH_RESET_TIMER;
1146
b2a0eb1a
KB		 1147 /*
1148 * Reset immediately if the controller is failed
1149 */
1150 if (nvme_should_reset(dev, csts)) {
1151 nvme_warn_reset(dev, csts);
1152 nvme_dev_disable(dev, false);
d86c4d8e 1153 nvme_reset_ctrl(&dev->ctrl);
db8c48e4 1154 return BLK_EH_DONE;
b2a0eb1a 1155 }
c30341dc 1156
7776db1c
KB		 1157 /*
1158 * Did we miss an interrupt?
1159 */
1160 if (__nvme_poll(nvmeq, req->tag)) {
1161 dev_warn(dev->ctrl.device,
1162 "I/O %d QID %d timeout, completion polled\n",
1163 req->tag, nvmeq->qid);
db8c48e4 1164 return BLK_EH_DONE;
7776db1c
KB		 1165 }
1166
31c7c7d2 1167 /*
fd634f41
CH		 1168 * Shutdown immediately if controller times out while starting. The
1169 * reset work will see the pci device disabled when it gets the forced
1170 * cancellation error. All outstanding requests are completed on
db8c48e4 1171 * shutdown, so we return BLK_EH_DONE.
fd634f41 1172 */
4244140d
KB		 1173 switch (dev->ctrl.state) {
1174 case NVME_CTRL_CONNECTING:
1175 case NVME_CTRL_RESETTING:
b9cac43c 1176 dev_warn_ratelimited(dev->ctrl.device,
fd634f41
CH		 1177 "I/O %d QID %d timeout, disable controller\n",
1178 req->tag, nvmeq->qid);
a5cdb68c 1179 nvme_dev_disable(dev, false);
27fa9bc5 1180 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
db8c48e4 1181 return BLK_EH_DONE;
4244140d
KB		 1182 default:
1183 break;
c30341dc
KB		 1184 }
1185
fd634f41
CH		 1186 /*
1187 * Shutdown the controller immediately and schedule a reset if the
1188 * command was already aborted once before and still hasn't been
1189 * returned to the driver, or if this is the admin queue.
31c7c7d2 1190 */
f4800d6d 1191 if (!nvmeq->qid || iod->aborted) {
1b3c47c1 1192 dev_warn(dev->ctrl.device,
e1569a16
KB		 1193 "I/O %d QID %d timeout, reset controller\n",
1194 req->tag, nvmeq->qid);
a5cdb68c 1195 nvme_dev_disable(dev, false);
d86c4d8e 1196 nvme_reset_ctrl(&dev->ctrl);
c30341dc 1197
27fa9bc5 1198 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
db8c48e4 1199 return BLK_EH_DONE;
c30341dc 1200 }
c30341dc 1201
e7a2a87d 1202 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
6bf25d16 1203 atomic_inc(&dev->ctrl.abort_limit);
31c7c7d2 1204 return BLK_EH_RESET_TIMER;
6bf25d16 1205 }
7bf7d778 1206 iod->aborted = 1;
a4aea562 1207
c30341dc
KB		 1208 memset(&cmd, 0, sizeof(cmd));
1209 cmd.abort.opcode = nvme_admin_abort_cmd;
a4aea562 1210 cmd.abort.cid = req->tag;
c30341dc 1211 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
c30341dc 1212
1b3c47c1
SG		 1213 dev_warn(nvmeq->dev->ctrl.device,
1214 "I/O %d QID %d timeout, aborting\n",
1215 req->tag, nvmeq->qid);
e7a2a87d
CH		 1216
1217 abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
eb71f435 1218 BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
e7a2a87d
CH		 1219 if (IS_ERR(abort_req)) {
1220 atomic_inc(&dev->ctrl.abort_limit);
1221 return BLK_EH_RESET_TIMER;
1222 }
1223
1224 abort_req->timeout = ADMIN_TIMEOUT;
1225 abort_req->end_io_data = NULL;
1226 blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio);
c30341dc 1227
31c7c7d2
CH		 1228 /*
1229 * The aborted req will be completed on receiving the abort req.
1230 * We enable the timer again. If hit twice, it'll cause a device reset,
1231 * as the device then is in a faulty state.
1232 */
1233 return BLK_EH_RESET_TIMER;
c30341dc
KB		 1234}
1235
a4aea562
MB		 1236static void nvme_free_queue(struct nvme_queue *nvmeq)
1237{
9e866774
MW		 1238 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1239 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
0f238ff5
LG		 1240
1241 if (nvmeq->sq_cmds) {
1242 if (nvmeq->sq_cmds_is_io)
1243 pci_free_p2pmem(to_pci_dev(nvmeq->q_dmadev),
1244 nvmeq->sq_cmds,
1245 SQ_SIZE(nvmeq->q_depth));
1246 else
1247 dma_free_coherent(nvmeq->q_dmadev,
1248 SQ_SIZE(nvmeq->q_depth),
1249 nvmeq->sq_cmds,
1250 nvmeq->sq_dma_addr);
1251 }
9e866774
MW		 1252}
1253
a1a5ef99 1254static void nvme_free_queues(struct nvme_dev *dev, int lowest)
22404274
KB		 1255{
1256 int i;
1257
d858e5f0 1258 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
d858e5f0 1259 dev->ctrl.queue_count--;
147b27e4 1260 nvme_free_queue(&dev->queues[i]);
121c7ad4 1261 }
22404274
KB		 1262}
1263
4d115420
KB		 1264/**
1265 * nvme_suspend_queue - put queue into suspended state
40581d1a 1266 * @nvmeq: queue to suspend
4d115420
KB		 1267 */
1268static int nvme_suspend_queue(struct nvme_queue *nvmeq)
b60503ba 1269{
2b25d981 1270 int vector;
b60503ba 1271
1ab0cd69 1272 spin_lock_irq(&nvmeq->cq_lock);
2b25d981 1273 if (nvmeq->cq_vector == -1) {
1ab0cd69 1274 spin_unlock_irq(&nvmeq->cq_lock);
2b25d981
KB		 1275 return 1;
1276 }
0ff199cb 1277 vector = nvmeq->cq_vector;
42f61420 1278 nvmeq->dev->online_queues--;
2b25d981 1279 nvmeq->cq_vector = -1;
1ab0cd69 1280 spin_unlock_irq(&nvmeq->cq_lock);
a09115b2 1281
d1f06f4a
JA		 1282 /*
1283 * Ensure that nvme_queue_rq() sees it ->cq_vector == -1 without
1284 * having to grab the lock.
1285 */
1286 mb();
a09115b2 1287
1c63dc66 1288 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
c81545f9 1289 blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q);
6df3dbc8 1290
0ff199cb 1291 pci_free_irq(to_pci_dev(nvmeq->dev->dev), vector, nvmeq);
b60503ba 1292
4d115420
KB		 1293 return 0;
1294}
b60503ba 1295
a5cdb68c 1296static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
4d115420 1297{
147b27e4 1298 struct nvme_queue *nvmeq = &dev->queues[0];
5cb525c8 1299 u16 start, end;
4d115420 1300
a5cdb68c
KB		 1301 if (shutdown)
1302 nvme_shutdown_ctrl(&dev->ctrl);
1303 else
20d0dfe6 1304 nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap);
07836e65 1305
1ab0cd69 1306 spin_lock_irq(&nvmeq->cq_lock);
5cb525c8 1307 nvme_process_cq(nvmeq, &start, &end, -1);
1ab0cd69 1308 spin_unlock_irq(&nvmeq->cq_lock);
5cb525c8
JA		 1309
1310 nvme_complete_cqes(nvmeq, start, end);
b60503ba
MW		 1311}
1312
8ffaadf7
JD		 1313static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1314 int entry_size)
1315{
1316 int q_depth = dev->q_depth;
5fd4ce1b
CH		 1317 unsigned q_size_aligned = roundup(q_depth * entry_size,
1318 dev->ctrl.page_size);
8ffaadf7
JD		 1319
1320 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
c45f5c99 1321 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
5fd4ce1b 1322 mem_per_q = round_down(mem_per_q, dev->ctrl.page_size);
c45f5c99 1323 q_depth = div_u64(mem_per_q, entry_size);
8ffaadf7
JD		 1324
1325 /*
1326 * Ensure the reduced q_depth is above some threshold where it
1327 * would be better to map queues in system memory with the
1328 * original depth
1329 */
1330 if (q_depth < 64)
1331 return -ENOMEM;
1332 }
1333
1334 return q_depth;
1335}
1336
1337static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1338 int qid, int depth)
1339{
0f238ff5
LG		 1340 struct pci_dev *pdev = to_pci_dev(dev->dev);
1341
1342 if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
1343 nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(depth));
1344 nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev,
1345 nvmeq->sq_cmds);
1346 nvmeq->sq_cmds_is_io = true;
1347 }
1348
1349 if (!nvmeq->sq_cmds) {
1350 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
1351 &nvmeq->sq_dma_addr, GFP_KERNEL);
1352 nvmeq->sq_cmds_is_io = false;
1353 }
8ffaadf7 1354
815c6704
KB		 1355 if (!nvmeq->sq_cmds)
1356 return -ENOMEM;
8ffaadf7
JD		 1357 return 0;
1358}
1359
a6ff7262 1360static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
b60503ba 1361{
147b27e4 1362 struct nvme_queue *nvmeq = &dev->queues[qid];
b60503ba 1363
62314e40
KB		 1364 if (dev->ctrl.queue_count > qid)
1365 return 0;
b60503ba 1366
e75ec752 1367 nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth),
4d51abf9 1368 &nvmeq->cq_dma_addr, GFP_KERNEL);
b60503ba
MW		 1369 if (!nvmeq->cqes)
1370 goto free_nvmeq;
b60503ba 1371
8ffaadf7 1372 if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth))
b60503ba
MW		 1373 goto free_cqdma;
1374
e75ec752 1375 nvmeq->q_dmadev = dev->dev;
091b6092 1376 nvmeq->dev = dev;
1ab0cd69
JA		 1377 spin_lock_init(&nvmeq->sq_lock);
1378 spin_lock_init(&nvmeq->cq_lock);
b60503ba 1379 nvmeq->cq_head = 0;
82123460 1380 nvmeq->cq_phase = 1;
b80d5ccc 1381 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
b60503ba 1382 nvmeq->q_depth = depth;
c30341dc 1383 nvmeq->qid = qid;
758dd7fd 1384 nvmeq->cq_vector = -1;
d858e5f0 1385 dev->ctrl.queue_count++;
36a7e993 1386
147b27e4 1387 return 0;
b60503ba
MW		 1388
1389 free_cqdma:
e75ec752 1390 dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes,
b60503ba
MW		 1391 nvmeq->cq_dma_addr);
1392 free_nvmeq:
147b27e4 1393 return -ENOMEM;
b60503ba
MW		 1394}
1395
dca51e78 1396static int queue_request_irq(struct nvme_queue *nvmeq)
3001082c 1397{
0ff199cb
CH		 1398 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1399 int nr = nvmeq->dev->ctrl.instance;
1400
1401 if (use_threaded_interrupts) {
1402 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1403 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1404 } else {
1405 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1406 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1407 }
3001082c
MW		 1408}
1409
22404274 1410static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
b60503ba 1411{
22404274 1412 struct nvme_dev *dev = nvmeq->dev;
b60503ba 1413
1ab0cd69 1414 spin_lock_irq(&nvmeq->cq_lock);
22404274
KB		 1415 nvmeq->sq_tail = 0;
1416 nvmeq->cq_head = 0;
1417 nvmeq->cq_phase = 1;
b80d5ccc 1418 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
22404274 1419 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
f9f38e33 1420 nvme_dbbuf_init(dev, nvmeq, qid);
42f61420 1421 dev->online_queues++;
1ab0cd69 1422 spin_unlock_irq(&nvmeq->cq_lock);
22404274
KB		 1423}
1424
1425static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1426{
1427 struct nvme_dev *dev = nvmeq->dev;
1428 int result;
a8e3e0bb 1429 s16 vector;
3f85d50b 1430
22b55601
KB		 1431 /*
1432 * A queue's vector matches the queue identifier unless the controller
1433 * has only one vector available.
1434 */
a8e3e0bb
JW		 1435 vector = dev->num_vecs == 1 ? 0 : qid;
1436 result = adapter_alloc_cq(dev, qid, nvmeq, vector);
ded45505
KB		 1437 if (result)
1438 return result;
b60503ba
MW		 1439
1440 result = adapter_alloc_sq(dev, qid, nvmeq);
1441 if (result < 0)
ded45505
KB		 1442 return result;
1443 else if (result)
b60503ba
MW		 1444 goto release_cq;
1445
a8e3e0bb
JW		 1446 /*
1447 * Set cq_vector after alloc cq/sq, otherwise nvme_suspend_queue will
1448 * invoke free_irq for it and cause a 'Trying to free already-free IRQ
1449 * xxx' warning if the create CQ/SQ command times out.
1450 */
1451 nvmeq->cq_vector = vector;
161b8be2 1452 nvme_init_queue(nvmeq, qid);
dca51e78 1453 result = queue_request_irq(nvmeq);
b60503ba
MW		 1454 if (result < 0)
1455 goto release_sq;
1456
22404274 1457 return result;
b60503ba 1458
a8e3e0bb
JW		 1459release_sq:
1460 nvmeq->cq_vector = -1;
f25a2dfc 1461 dev->online_queues--;
b60503ba 1462 adapter_delete_sq(dev, qid);
a8e3e0bb 1463release_cq:
b60503ba 1464 adapter_delete_cq(dev, qid);
22404274 1465 return result;
b60503ba
MW		 1466}
1467
f363b089 1468static const struct blk_mq_ops nvme_mq_admin_ops = {
d29ec824 1469 .queue_rq = nvme_queue_rq,
77f02a7a 1470 .complete = nvme_pci_complete_rq,
a4aea562 1471 .init_hctx = nvme_admin_init_hctx,
4af0e21c 1472 .exit_hctx = nvme_admin_exit_hctx,
0350815a 1473 .init_request = nvme_init_request,
a4aea562
MB		 1474 .timeout = nvme_timeout,
1475};
1476
f363b089 1477static const struct blk_mq_ops nvme_mq_ops = {
a4aea562 1478 .queue_rq = nvme_queue_rq,
77f02a7a 1479 .complete = nvme_pci_complete_rq,
a4aea562
MB		 1480 .init_hctx = nvme_init_hctx,
1481 .init_request = nvme_init_request,
dca51e78 1482 .map_queues = nvme_pci_map_queues,
a4aea562 1483 .timeout = nvme_timeout,
a0fa9647 1484 .poll = nvme_poll,
a4aea562
MB		 1485};
1486
ea191d2f
KB		 1487static void nvme_dev_remove_admin(struct nvme_dev *dev)
1488{
1c63dc66 1489 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
69d9a99c
KB		 1490 /*
1491 * If the controller was reset during removal, it's possible
1492 * user requests may be waiting on a stopped queue. Start the
1493 * queue to flush these to completion.
1494 */
c81545f9 1495 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1c63dc66 1496 blk_cleanup_queue(dev->ctrl.admin_q);
ea191d2f
KB		 1497 blk_mq_free_tag_set(&dev->admin_tagset);
1498 }
1499}
1500
a4aea562
MB		 1501static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1502{
1c63dc66 1503 if (!dev->ctrl.admin_q) {
a4aea562
MB		 1504 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1505 dev->admin_tagset.nr_hw_queues = 1;
e3e9d50c 1506
38dabe21 1507 dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH;
a4aea562 1508 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
e75ec752 1509 dev->admin_tagset.numa_node = dev_to_node(dev->dev);
a7a7cbe3 1510 dev->admin_tagset.cmd_size = nvme_pci_cmd_size(dev, false);
d3484991 1511 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED;
a4aea562
MB		 1512 dev->admin_tagset.driver_data = dev;
1513
1514 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1515 return -ENOMEM;
34b6c231 1516 dev->ctrl.admin_tagset = &dev->admin_tagset;
a4aea562 1517
1c63dc66
CH		 1518 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1519 if (IS_ERR(dev->ctrl.admin_q)) {
a4aea562
MB		 1520 blk_mq_free_tag_set(&dev->admin_tagset);
1521 return -ENOMEM;
1522 }
1c63dc66 1523 if (!blk_get_queue(dev->ctrl.admin_q)) {
ea191d2f 1524 nvme_dev_remove_admin(dev);
1c63dc66 1525 dev->ctrl.admin_q = NULL;
ea191d2f
KB		 1526 return -ENODEV;
1527 }
0fb59cbc 1528 } else
c81545f9 1529 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
a4aea562
MB		 1530
1531 return 0;
1532}
1533
97f6ef64
XY		 1534static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1535{
1536 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1537}
1538
1539static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1540{
1541 struct pci_dev *pdev = to_pci_dev(dev->dev);
1542
1543 if (size <= dev->bar_mapped_size)
1544 return 0;
1545 if (size > pci_resource_len(pdev, 0))
1546 return -ENOMEM;
1547 if (dev->bar)
1548 iounmap(dev->bar);
1549 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1550 if (!dev->bar) {
1551 dev->bar_mapped_size = 0;
1552 return -ENOMEM;
1553 }
1554 dev->bar_mapped_size = size;
1555 dev->dbs = dev->bar + NVME_REG_DBS;
1556
1557 return 0;
1558}
1559
01ad0990 1560static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
b60503ba 1561{
ba47e386 1562 int result;
b60503ba
MW		 1563 u32 aqa;
1564 struct nvme_queue *nvmeq;
1565
97f6ef64
XY		 1566 result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1567 if (result < 0)
1568 return result;
1569
8ef2074d 1570 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
20d0dfe6 1571 NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
dfbac8c7 1572
7a67cbea
CH		 1573 if (dev->subsystem &&
1574 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1575 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
dfbac8c7 1576
20d0dfe6 1577 result = nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap);
ba47e386
MW		 1578 if (result < 0)
1579 return result;
b60503ba 1580
a6ff7262 1581 result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
147b27e4
SG		 1582 if (result)
1583 return result;
b60503ba 1584
147b27e4 1585 nvmeq = &dev->queues[0];
b60503ba
MW		 1586 aqa = nvmeq->q_depth - 1;
1587 aqa |= aqa << 16;
1588
7a67cbea
CH		 1589 writel(aqa, dev->bar + NVME_REG_AQA);
1590 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1591 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
b60503ba 1592
20d0dfe6 1593 result = nvme_enable_ctrl(&dev->ctrl, dev->ctrl.cap);
025c557a 1594 if (result)
d4875622 1595 return result;
a4aea562 1596
2b25d981 1597 nvmeq->cq_vector = 0;
161b8be2 1598 nvme_init_queue(nvmeq, 0);
dca51e78 1599 result = queue_request_irq(nvmeq);
758dd7fd
JD		 1600 if (result) {
1601 nvmeq->cq_vector = -1;
d4875622 1602 return result;
758dd7fd 1603 }
025c557a 1604
b60503ba
MW		 1605 return result;
1606}
1607
749941f2 1608static int nvme_create_io_queues(struct nvme_dev *dev)
42f61420 1609{
949928c1 1610 unsigned i, max;
749941f2 1611 int ret = 0;
42f61420 1612
d858e5f0 1613 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
a6ff7262 1614 if (nvme_alloc_queue(dev, i, dev->q_depth)) {
749941f2 1615 ret = -ENOMEM;
42f61420 1616 break;
749941f2
CH		 1617 }
1618 }
42f61420 1619
d858e5f0 1620 max = min(dev->max_qid, dev->ctrl.queue_count - 1);
949928c1 1621 for (i = dev->online_queues; i <= max; i++) {
147b27e4 1622 ret = nvme_create_queue(&dev->queues[i], i);
d4875622 1623 if (ret)
42f61420 1624 break;
27e8166c 1625 }
749941f2
CH		 1626
1627 /*
1628 * Ignore failing Create SQ/CQ commands, we can continue with less
8adb8c14
MI		 1629 * than the desired amount of queues, and even a controller without
1630 * I/O queues can still be used to issue admin commands. This might
749941f2
CH		 1631 * be useful to upgrade a buggy firmware for example.
1632 */
1633 return ret >= 0 ? 0 : ret;
b60503ba
MW		 1634}
1635
202021c1
SB		 1636static ssize_t nvme_cmb_show(struct device *dev,
1637 struct device_attribute *attr,
1638 char *buf)
1639{
1640 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
1641
c965809c 1642 return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n",
202021c1
SB		 1643 ndev->cmbloc, ndev->cmbsz);
1644}
1645static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL);
1646
88de4598 1647static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
8ffaadf7 1648{
88de4598
CH		 1649 u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
1650
1651 return 1ULL << (12 + 4 * szu);
1652}
1653
1654static u32 nvme_cmb_size(struct nvme_dev *dev)
1655{
1656 return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
1657}
1658
f65efd6d 1659static void nvme_map_cmb(struct nvme_dev *dev)
8ffaadf7 1660{
88de4598 1661 u64 size, offset;
8ffaadf7
JD		 1662 resource_size_t bar_size;
1663 struct pci_dev *pdev = to_pci_dev(dev->dev);
8969f1f8 1664 int bar;
8ffaadf7 1665
9fe5c59f
KB		 1666 if (dev->cmb_size)
1667 return;
1668
7a67cbea 1669 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
f65efd6d
CH		 1670 if (!dev->cmbsz)
1671 return;
202021c1 1672 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
8ffaadf7 1673
88de4598
CH		 1674 size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
1675 offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
8969f1f8
CH		 1676 bar = NVME_CMB_BIR(dev->cmbloc);
1677 bar_size = pci_resource_len(pdev, bar);
8ffaadf7
JD		 1678
1679 if (offset > bar_size)
f65efd6d 1680 return;
8ffaadf7
JD		 1681
1682 /*
1683 * Controllers may support a CMB size larger than their BAR,
1684 * for example, due to being behind a bridge. Reduce the CMB to
1685 * the reported size of the BAR
1686 */
1687 if (size > bar_size - offset)
1688 size = bar_size - offset;
1689
0f238ff5
LG		 1690 if (pci_p2pdma_add_resource(pdev, bar, size, offset)) {
1691 dev_warn(dev->ctrl.device,
1692 "failed to register the CMB\n");
f65efd6d 1693 return;
0f238ff5
LG		 1694 }
1695
8ffaadf7 1696 dev->cmb_size = size;
0f238ff5
LG		 1697 dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS);
1698
1699 if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) ==
1700 (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS))
1701 pci_p2pmem_publish(pdev, true);
f65efd6d
CH		 1702
1703 if (sysfs_add_file_to_group(&dev->ctrl.device->kobj,
1704 &dev_attr_cmb.attr, NULL))
1705 dev_warn(dev->ctrl.device,
1706 "failed to add sysfs attribute for CMB\n");
8ffaadf7
JD		 1707}
1708
1709static inline void nvme_release_cmb(struct nvme_dev *dev)
1710{
0f238ff5 1711 if (dev->cmb_size) {
1c78f773
MG		 1712 sysfs_remove_file_from_group(&dev->ctrl.device->kobj,
1713 &dev_attr_cmb.attr, NULL);
0f238ff5 1714 dev->cmb_size = 0;
8ffaadf7
JD		 1715 }
1716}
1717
87ad72a5
CH		 1718static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1719{
4033f35d 1720 u64 dma_addr = dev->host_mem_descs_dma;
87ad72a5 1721 struct nvme_command c;
87ad72a5
CH		 1722 int ret;
1723
87ad72a5
CH		 1724 memset(&c, 0, sizeof(c));
1725 c.features.opcode = nvme_admin_set_features;
1726 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1727 c.features.dword11 = cpu_to_le32(bits);
1728 c.features.dword12 = cpu_to_le32(dev->host_mem_size >>
1729 ilog2(dev->ctrl.page_size));
1730 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr));
1731 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr));
1732 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs);
1733
1734 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1735 if (ret) {
1736 dev_warn(dev->ctrl.device,
1737 "failed to set host mem (err %d, flags %#x).\n",
1738 ret, bits);
1739 }
87ad72a5
CH		 1740 return ret;
1741}
1742
1743static void nvme_free_host_mem(struct nvme_dev *dev)
1744{
1745 int i;
1746
1747 for (i = 0; i < dev->nr_host_mem_descs; i++) {
1748 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
1749 size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size;
1750
1751 dma_free_coherent(dev->dev, size, dev->host_mem_desc_bufs[i],
1752 le64_to_cpu(desc->addr));
1753 }
1754
1755 kfree(dev->host_mem_desc_bufs);
1756 dev->host_mem_desc_bufs = NULL;
4033f35d
CH		 1757 dma_free_coherent(dev->dev,
1758 dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
1759 dev->host_mem_descs, dev->host_mem_descs_dma);
87ad72a5 1760 dev->host_mem_descs = NULL;
7e5dd57e 1761 dev->nr_host_mem_descs = 0;
87ad72a5
CH		 1762}
1763
92dc6895
CH		 1764static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
1765 u32 chunk_size)
9d713c2b 1766{
87ad72a5 1767 struct nvme_host_mem_buf_desc *descs;
92dc6895 1768 u32 max_entries, len;
4033f35d 1769 dma_addr_t descs_dma;
2ee0e4ed 1770 int i = 0;
87ad72a5 1771 void **bufs;
6fbcde66 1772 u64 size, tmp;
87ad72a5 1773
87ad72a5
CH		 1774 tmp = (preferred + chunk_size - 1);
1775 do_div(tmp, chunk_size);
1776 max_entries = tmp;
044a9df1
CH		 1777
1778 if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
1779 max_entries = dev->ctrl.hmmaxd;
1780
4033f35d
CH		 1781 descs = dma_zalloc_coherent(dev->dev, max_entries * sizeof(*descs),
1782 &descs_dma, GFP_KERNEL);
87ad72a5
CH		 1783 if (!descs)
1784 goto out;
1785
1786 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
1787 if (!bufs)
1788 goto out_free_descs;
1789
244a8fe4 1790 for (size = 0; size < preferred && i < max_entries; size += len) {
87ad72a5
CH		 1791 dma_addr_t dma_addr;
1792
50cdb7c6 1793 len = min_t(u64, chunk_size, preferred - size);
87ad72a5
CH		 1794 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
1795 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1796 if (!bufs[i])
1797 break;
1798
1799 descs[i].addr = cpu_to_le64(dma_addr);
1800 descs[i].size = cpu_to_le32(len / dev->ctrl.page_size);
1801 i++;
1802 }
1803
92dc6895 1804 if (!size)
87ad72a5 1805 goto out_free_bufs;
87ad72a5 1806
87ad72a5
CH		 1807 dev->nr_host_mem_descs = i;
1808 dev->host_mem_size = size;
1809 dev->host_mem_descs = descs;
4033f35d 1810 dev->host_mem_descs_dma = descs_dma;
87ad72a5
CH		 1811 dev->host_mem_desc_bufs = bufs;
1812 return 0;
1813
1814out_free_bufs:
1815 while (--i >= 0) {
1816 size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size;
1817
1818 dma_free_coherent(dev->dev, size, bufs[i],
1819 le64_to_cpu(descs[i].addr));
1820 }
1821
1822 kfree(bufs);
1823out_free_descs:
4033f35d
CH		 1824 dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
1825 descs_dma);
87ad72a5 1826out:
87ad72a5
CH		 1827 dev->host_mem_descs = NULL;
1828 return -ENOMEM;
1829}
1830
92dc6895
CH		 1831static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
1832{
1833 u32 chunk_size;
1834
1835 /* start big and work our way down */
30f92d62 1836 for (chunk_size = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
044a9df1 1837 chunk_size >= max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
92dc6895
CH		 1838 chunk_size /= 2) {
1839 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
1840 if (!min || dev->host_mem_size >= min)
1841 return 0;
1842 nvme_free_host_mem(dev);
1843 }
1844 }
1845
1846 return -ENOMEM;
1847}
1848
9620cfba 1849static int nvme_setup_host_mem(struct nvme_dev *dev)
87ad72a5
CH		 1850{
1851 u64 max = (u64)max_host_mem_size_mb * SZ_1M;
1852 u64 preferred = (u64)dev->ctrl.hmpre * 4096;
1853 u64 min = (u64)dev->ctrl.hmmin * 4096;
1854 u32 enable_bits = NVME_HOST_MEM_ENABLE;
6fbcde66 1855 int ret;
87ad72a5
CH		 1856
1857 preferred = min(preferred, max);
1858 if (min > max) {
1859 dev_warn(dev->ctrl.device,
1860 "min host memory (%lld MiB) above limit (%d MiB).\n",
1861 min >> ilog2(SZ_1M), max_host_mem_size_mb);
1862 nvme_free_host_mem(dev);
9620cfba 1863 return 0;
87ad72a5
CH		 1864 }
1865
1866 /*
1867 * If we already have a buffer allocated check if we can reuse it.
1868 */
1869 if (dev->host_mem_descs) {
1870 if (dev->host_mem_size >= min)
1871 enable_bits |= NVME_HOST_MEM_RETURN;
1872 else
1873 nvme_free_host_mem(dev);
1874 }
1875
1876 if (!dev->host_mem_descs) {
92dc6895
CH		 1877 if (nvme_alloc_host_mem(dev, min, preferred)) {
1878 dev_warn(dev->ctrl.device,
1879 "failed to allocate host memory buffer.\n");
9620cfba 1880 return 0; /* controller must work without HMB */
92dc6895
CH		 1881 }
1882
1883 dev_info(dev->ctrl.device,
1884 "allocated %lld MiB host memory buffer.\n",
1885 dev->host_mem_size >> ilog2(SZ_1M));
87ad72a5
CH		 1886 }
1887
9620cfba
CH		 1888 ret = nvme_set_host_mem(dev, enable_bits);
1889 if (ret)
87ad72a5 1890 nvme_free_host_mem(dev);
9620cfba 1891 return ret;
9d713c2b
KB		 1892}
1893
8d85fce7 1894static int nvme_setup_io_queues(struct nvme_dev *dev)
b60503ba 1895{
147b27e4 1896 struct nvme_queue *adminq = &dev->queues[0];
e75ec752 1897 struct pci_dev *pdev = to_pci_dev(dev->dev);
97f6ef64
XY		 1898 int result, nr_io_queues;
1899 unsigned long size;
b60503ba 1900
22b55601
KB		 1901 struct irq_affinity affd = {
1902 .pre_vectors = 1
1903 };
1904
16ccfff2 1905 nr_io_queues = num_possible_cpus();
9a0be7ab
CH		 1906 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
1907 if (result < 0)
1b23484b 1908 return result;
9a0be7ab 1909
f5fa90dc 1910 if (nr_io_queues == 0)
a5229050 1911 return 0;
b60503ba 1912
0f238ff5 1913 if (dev->cmb_use_sqes) {
8ffaadf7
JD		 1914 result = nvme_cmb_qdepth(dev, nr_io_queues,
1915 sizeof(struct nvme_command));
1916 if (result > 0)
1917 dev->q_depth = result;
1918 else
0f238ff5 1919 dev->cmb_use_sqes = false;
8ffaadf7
JD		 1920 }
1921
97f6ef64
XY		 1922 do {
1923 size = db_bar_size(dev, nr_io_queues);
1924 result = nvme_remap_bar(dev, size);
1925 if (!result)
1926 break;
1927 if (!--nr_io_queues)
1928 return -ENOMEM;
1929 } while (1);
1930 adminq->q_db = dev->dbs;
f1938f6e 1931
9d713c2b 1932 /* Deregister the admin queue's interrupt */
0ff199cb 1933 pci_free_irq(pdev, 0, adminq);
9d713c2b 1934
e32efbfc
JA		 1935 /*
1936 * If we enable msix early due to not intx, disable it again before
1937 * setting up the full range we need.
1938 */
dca51e78 1939 pci_free_irq_vectors(pdev);
22b55601
KB		 1940 result = pci_alloc_irq_vectors_affinity(pdev, 1, nr_io_queues + 1,
1941 PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd);
1942 if (result <= 0)
dca51e78 1943 return -EIO;
22b55601
KB		 1944 dev->num_vecs = result;
1945 dev->max_qid = max(result - 1, 1);
fa08a396 1946
063a8096
MW		 1947 /*
1948 * Should investigate if there's a performance win from allocating
1949 * more queues than interrupt vectors; it might allow the submission
1950 * path to scale better, even if the receive path is limited by the
1951 * number of interrupts.
1952 */
063a8096 1953
dca51e78 1954 result = queue_request_irq(adminq);
758dd7fd
JD		 1955 if (result) {
1956 adminq->cq_vector = -1;
d4875622 1957 return result;
758dd7fd 1958 }
749941f2 1959 return nvme_create_io_queues(dev);
b60503ba
MW		 1960}
1961
2a842aca 1962static void nvme_del_queue_end(struct request *req, blk_status_t error)
a5768aa8 1963{
db3cbfff 1964 struct nvme_queue *nvmeq = req->end_io_data;
b5875222 1965
db3cbfff
KB		 1966 blk_mq_free_request(req);
1967 complete(&nvmeq->dev->ioq_wait);
a5768aa8
KB		 1968}
1969
2a842aca 1970static void nvme_del_cq_end(struct request *req, blk_status_t error)
a5768aa8 1971{
db3cbfff 1972 struct nvme_queue *nvmeq = req->end_io_data;
5cb525c8 1973 u16 start, end;
a5768aa8 1974
db3cbfff
KB		 1975 if (!error) {
1976 unsigned long flags;
1977
0bc88192 1978 spin_lock_irqsave(&nvmeq->cq_lock, flags);
5cb525c8 1979 nvme_process_cq(nvmeq, &start, &end, -1);
1ab0cd69 1980 spin_unlock_irqrestore(&nvmeq->cq_lock, flags);
5cb525c8
JA		 1981
1982 nvme_complete_cqes(nvmeq, start, end);
a5768aa8 1983 }
db3cbfff
KB		 1984
1985 nvme_del_queue_end(req, error);
a5768aa8
KB		 1986}
1987
db3cbfff 1988static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
bda4e0fb 1989{
db3cbfff
KB		 1990 struct request_queue *q = nvmeq->dev->ctrl.admin_q;
1991 struct request *req;
1992 struct nvme_command cmd;
bda4e0fb 1993
db3cbfff
KB		 1994 memset(&cmd, 0, sizeof(cmd));
1995 cmd.delete_queue.opcode = opcode;
1996 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
bda4e0fb 1997
eb71f435 1998 req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
db3cbfff
KB		 1999 if (IS_ERR(req))
2000 return PTR_ERR(req);
bda4e0fb 2001
db3cbfff
KB		 2002 req->timeout = ADMIN_TIMEOUT;
2003 req->end_io_data = nvmeq;
2004
2005 blk_execute_rq_nowait(q, NULL, req, false,
2006 opcode == nvme_admin_delete_cq ?
2007 nvme_del_cq_end : nvme_del_queue_end);
2008 return 0;
bda4e0fb
KB		 2009}
2010
ee9aebb2 2011static void nvme_disable_io_queues(struct nvme_dev *dev)
a5768aa8 2012{
ee9aebb2 2013 int pass, queues = dev->online_queues - 1;
db3cbfff
KB		 2014 unsigned long timeout;
2015 u8 opcode = nvme_admin_delete_sq;
a5768aa8 2016
db3cbfff 2017 for (pass = 0; pass < 2; pass++) {
014a0d60 2018 int sent = 0, i = queues;
db3cbfff
KB		 2019
2020 reinit_completion(&dev->ioq_wait);
2021 retry:
2022 timeout = ADMIN_TIMEOUT;
c21377f8 2023 for (; i > 0; i--, sent++)
147b27e4 2024 if (nvme_delete_queue(&dev->queues[i], opcode))
db3cbfff 2025 break;
c21377f8 2026
db3cbfff
KB		 2027 while (sent--) {
2028 timeout = wait_for_completion_io_timeout(&dev->ioq_wait, timeout);
2029 if (timeout == 0)
2030 return;
2031 if (i)
2032 goto retry;
2033 }
2034 opcode = nvme_admin_delete_cq;
2035 }
a5768aa8
KB		 2036}
2037
422ef0c7 2038/*
2b1b7e78 2039 * return error value only when tagset allocation failed
422ef0c7 2040 */
8d85fce7 2041static int nvme_dev_add(struct nvme_dev *dev)
b60503ba 2042{
2b1b7e78
JW		 2043 int ret;
2044
5bae7f73 2045 if (!dev->ctrl.tagset) {
ffe7704d
KB		 2046 dev->tagset.ops = &nvme_mq_ops;
2047 dev->tagset.nr_hw_queues = dev->online_queues - 1;
2048 dev->tagset.timeout = NVME_IO_TIMEOUT;
2049 dev->tagset.numa_node = dev_to_node(dev->dev);
2050 dev->tagset.queue_depth =
a4aea562 2051 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
a7a7cbe3
CK		 2052 dev->tagset.cmd_size = nvme_pci_cmd_size(dev, false);
2053 if ((dev->ctrl.sgls & ((1 << 0) | (1 << 1))) && sgl_threshold) {
2054 dev->tagset.cmd_size = max(dev->tagset.cmd_size,
2055 nvme_pci_cmd_size(dev, true));
2056 }
ffe7704d
KB		 2057 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2058 dev->tagset.driver_data = dev;
b60503ba 2059
2b1b7e78
JW		 2060 ret = blk_mq_alloc_tag_set(&dev->tagset);
2061 if (ret) {
2062 dev_warn(dev->ctrl.device,
2063 "IO queues tagset allocation failed %d\n", ret);
2064 return ret;
2065 }
5bae7f73 2066 dev->ctrl.tagset = &dev->tagset;
f9f38e33
HK		 2067
2068 nvme_dbbuf_set(dev);
949928c1
KB		 2069 } else {
2070 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2071
2072 /* Free previously allocated queues that are no longer usable */
2073 nvme_free_queues(dev, dev->online_queues);
ffe7704d 2074 }
949928c1 2075
e1e5e564 2076 return 0;
b60503ba
MW		 2077}
2078
b00a726a 2079static int nvme_pci_enable(struct nvme_dev *dev)
0877cb0d 2080{
b00a726a 2081 int result = -ENOMEM;
e75ec752 2082 struct pci_dev *pdev = to_pci_dev(dev->dev);
0877cb0d
KB		 2083
2084 if (pci_enable_device_mem(pdev))
2085 return result;
2086
0877cb0d 2087 pci_set_master(pdev);
0877cb0d 2088
e75ec752
CH		 2089 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) &&
2090 dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32)))
052d0efa 2091 goto disable;
0877cb0d 2092
7a67cbea 2093 if (readl(dev->bar + NVME_REG_CSTS) == -1) {
0e53d180 2094 result = -ENODEV;
b00a726a 2095 goto disable;
0e53d180 2096 }
e32efbfc
JA		 2097
2098 /*
a5229050
KB		 2099 * Some devices and/or platforms don't advertise or work with INTx
2100 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2101 * adjust this later.
e32efbfc 2102 */
dca51e78
CH		 2103 result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
2104 if (result < 0)
2105 return result;
e32efbfc 2106
20d0dfe6 2107 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
7a67cbea 2108
20d0dfe6 2109 dev->q_depth = min_t(int, NVME_CAP_MQES(dev->ctrl.cap) + 1,
b27c1e68 2110 io_queue_depth);
20d0dfe6 2111 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
7a67cbea 2112 dev->dbs = dev->bar + 4096;
1f390c1f
SG		 2113
2114 /*
2115 * Temporary fix for the Apple controller found in the MacBook8,1 and
2116 * some MacBook7,1 to avoid controller resets and data loss.
2117 */
2118 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
2119 dev->q_depth = 2;
9bdcfb10
CH		 2120 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
2121 "set queue depth=%u to work around controller resets\n",
1f390c1f 2122 dev->q_depth);
d554b5e1
MP		 2123 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2124 (pdev->device == 0xa821 || pdev->device == 0xa822) &&
20d0dfe6 2125 NVME_CAP_MQES(dev->ctrl.cap) == 0) {
d554b5e1
MP		 2126 dev->q_depth = 64;
2127 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2128 "set queue depth=%u\n", dev->q_depth);
1f390c1f
SG		 2129 }
2130
f65efd6d 2131 nvme_map_cmb(dev);
202021c1 2132
a0a3408e
KB		 2133 pci_enable_pcie_error_reporting(pdev);
2134 pci_save_state(pdev);
0877cb0d
KB		 2135 return 0;
2136
2137 disable:
0877cb0d
KB		 2138 pci_disable_device(pdev);
2139 return result;
2140}
2141
2142static void nvme_dev_unmap(struct nvme_dev *dev)
b00a726a
KB		 2143{
2144 if (dev->bar)
2145 iounmap(dev->bar);
a1f447b3 2146 pci_release_mem_regions(to_pci_dev(dev->dev));
b00a726a
KB		 2147}
2148
2149static void nvme_pci_disable(struct nvme_dev *dev)
0877cb0d 2150{
e75ec752
CH		 2151 struct pci_dev *pdev = to_pci_dev(dev->dev);
2152
dca51e78 2153 pci_free_irq_vectors(pdev);
0877cb0d 2154
a0a3408e
KB		 2155 if (pci_is_enabled(pdev)) {
2156 pci_disable_pcie_error_reporting(pdev);
e75ec752 2157 pci_disable_device(pdev);
4d115420 2158 }
4d115420
KB		 2159}
2160
a5cdb68c 2161static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
b60503ba 2162{
ee9aebb2 2163 int i;
302ad8cc
KB		 2164 bool dead = true;
2165 struct pci_dev *pdev = to_pci_dev(dev->dev);
22404274 2166
77bf25ea 2167 mutex_lock(&dev->shutdown_lock);
302ad8cc
KB		 2168 if (pci_is_enabled(pdev)) {
2169 u32 csts = readl(dev->bar + NVME_REG_CSTS);
2170
ebef7368
KB		 2171 if (dev->ctrl.state == NVME_CTRL_LIVE ||
2172 dev->ctrl.state == NVME_CTRL_RESETTING)
302ad8cc
KB		 2173 nvme_start_freeze(&dev->ctrl);
2174 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
2175 pdev->error_state != pci_channel_io_normal);
c9d3bf88 2176 }
c21377f8 2177
302ad8cc
KB		 2178 /*
2179 * Give the controller a chance to complete all entered requests if
2180 * doing a safe shutdown.
2181 */
87ad72a5
CH		 2182 if (!dead) {
2183 if (shutdown)
2184 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
9a915a5b
JW		 2185 }
2186
2187 nvme_stop_queues(&dev->ctrl);
87ad72a5 2188
64ee0ac0 2189 if (!dead && dev->ctrl.queue_count > 0) {
ee9aebb2 2190 nvme_disable_io_queues(dev);
a5cdb68c 2191 nvme_disable_admin_queue(dev, shutdown);
4d115420 2192 }
ee9aebb2
KB		 2193 for (i = dev->ctrl.queue_count - 1; i >= 0; i--)
2194 nvme_suspend_queue(&dev->queues[i]);
2195
b00a726a 2196 nvme_pci_disable(dev);
07836e65 2197
e1958e65
ML		 2198 blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
2199 blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
302ad8cc
KB		 2200
2201 /*
2202 * The driver will not be starting up queues again if shutting down so
2203 * must flush all entered requests to their failed completion to avoid
2204 * deadlocking blk-mq hot-cpu notifier.
2205 */
2206 if (shutdown)
2207 nvme_start_queues(&dev->ctrl);
77bf25ea 2208 mutex_unlock(&dev->shutdown_lock);
b60503ba
MW		 2209}
2210
091b6092
MW		 2211static int nvme_setup_prp_pools(struct nvme_dev *dev)
2212{
e75ec752 2213 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
091b6092
MW		 2214 PAGE_SIZE, PAGE_SIZE, 0);
2215 if (!dev->prp_page_pool)
2216 return -ENOMEM;
2217
99802a7a 2218 /* Optimisation for I/Os between 4k and 128k */
e75ec752 2219 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
99802a7a
MW		 2220 256, 256, 0);
2221 if (!dev->prp_small_pool) {
2222 dma_pool_destroy(dev->prp_page_pool);
2223 return -ENOMEM;
2224 }
091b6092
MW		 2225 return 0;
2226}
2227
2228static void nvme_release_prp_pools(struct nvme_dev *dev)
2229{
2230 dma_pool_destroy(dev->prp_page_pool);
99802a7a 2231 dma_pool_destroy(dev->prp_small_pool);
091b6092
MW		 2232}
2233
1673f1f0 2234static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
5e82e952 2235{
1673f1f0 2236 struct nvme_dev *dev = to_nvme_dev(ctrl);
9ac27090 2237
f9f38e33 2238 nvme_dbbuf_dma_free(dev);
e75ec752 2239 put_device(dev->dev);
4af0e21c
KB		 2240 if (dev->tagset.tags)
2241 blk_mq_free_tag_set(&dev->tagset);
1c63dc66
CH		 2242 if (dev->ctrl.admin_q)
2243 blk_put_queue(dev->ctrl.admin_q);
5e82e952 2244 kfree(dev->queues);
e286bcfc 2245 free_opal_dev(dev->ctrl.opal_dev);
943e942e 2246 mempool_destroy(dev->iod_mempool);
5e82e952
KB		 2247 kfree(dev);
2248}
2249
f58944e2
KB		 2250static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status)
2251{
237045fc 2252 dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status);
f58944e2 2253
d22524a4 2254 nvme_get_ctrl(&dev->ctrl);
69d9a99c 2255 nvme_dev_disable(dev, false);
9f9cafc1 2256 nvme_kill_queues(&dev->ctrl);
03e0f3a6 2257 if (!queue_work(nvme_wq, &dev->remove_work))
f58944e2
KB		 2258 nvme_put_ctrl(&dev->ctrl);
2259}
2260
fd634f41 2261static void nvme_reset_work(struct work_struct *work)
5e82e952 2262{
d86c4d8e
CH		 2263 struct nvme_dev *dev =
2264 container_of(work, struct nvme_dev, ctrl.reset_work);
a98e58e5 2265 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
f58944e2 2266 int result = -ENODEV;
2b1b7e78 2267 enum nvme_ctrl_state new_state = NVME_CTRL_LIVE;
5e82e952 2268
82b057ca 2269 if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING))
fd634f41 2270 goto out;
5e82e952 2271
fd634f41
CH		 2272 /*
2273 * If we're called to reset a live controller first shut it down before
2274 * moving on.
2275 */
b00a726a 2276 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
a5cdb68c 2277 nvme_dev_disable(dev, false);
5e82e952 2278
ad70062c 2279 /*
ad6a0a52 2280 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
ad70062c
JW		 2281 * initializing procedure here.
2282 */
ad6a0a52 2283 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
ad70062c 2284 dev_warn(dev->ctrl.device,
ad6a0a52 2285 "failed to mark controller CONNECTING\n");
ad70062c
JW		 2286 goto out;
2287 }
2288
b00a726a 2289 result = nvme_pci_enable(dev);
f0b50732 2290 if (result)
3cf519b5 2291 goto out;
f0b50732 2292
01ad0990 2293 result = nvme_pci_configure_admin_queue(dev);
f0b50732 2294 if (result)
f58944e2 2295 goto out;
f0b50732 2296
0fb59cbc
KB		 2297 result = nvme_alloc_admin_tags(dev);
2298 if (result)
f58944e2 2299 goto out;
b9afca3e 2300
943e942e
JA		 2301 /*
2302 * Limit the max command size to prevent iod->sg allocations going
2303 * over a single page.
2304 */
2305 dev->ctrl.max_hw_sectors = NVME_MAX_KB_SZ << 1;
2306 dev->ctrl.max_segments = NVME_MAX_SEGS;
2307
ce4541f4
CH		 2308 result = nvme_init_identify(&dev->ctrl);
2309 if (result)
f58944e2 2310 goto out;
ce4541f4 2311
e286bcfc
SB		 2312 if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
2313 if (!dev->ctrl.opal_dev)
2314 dev->ctrl.opal_dev =
2315 init_opal_dev(&dev->ctrl, &nvme_sec_submit);
2316 else if (was_suspend)
2317 opal_unlock_from_suspend(dev->ctrl.opal_dev);
2318 } else {
2319 free_opal_dev(dev->ctrl.opal_dev);
2320 dev->ctrl.opal_dev = NULL;
4f1244c8 2321 }
a98e58e5 2322
f9f38e33
HK		 2323 if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) {
2324 result = nvme_dbbuf_dma_alloc(dev);
2325 if (result)
2326 dev_warn(dev->dev,
2327 "unable to allocate dma for dbbuf\n");
2328 }
2329
9620cfba
CH		 2330 if (dev->ctrl.hmpre) {
2331 result = nvme_setup_host_mem(dev);
2332 if (result < 0)
2333 goto out;
2334 }
87ad72a5 2335
f0b50732 2336 result = nvme_setup_io_queues(dev);
badc34d4 2337 if (result)
f58944e2 2338 goto out;
f0b50732 2339
2659e57b
CH		 2340 /*
2341 * Keep the controller around but remove all namespaces if we don't have
2342 * any working I/O queue.
2343 */
3cf519b5 2344 if (dev->online_queues < 2) {
1b3c47c1 2345 dev_warn(dev->ctrl.device, "IO queues not created\n");
3b24774e 2346 nvme_kill_queues(&dev->ctrl);
5bae7f73 2347 nvme_remove_namespaces(&dev->ctrl);
2b1b7e78 2348 new_state = NVME_CTRL_ADMIN_ONLY;
3cf519b5 2349 } else {
25646264 2350 nvme_start_queues(&dev->ctrl);
302ad8cc 2351 nvme_wait_freeze(&dev->ctrl);
2b1b7e78
JW		 2352 /* hit this only when allocate tagset fails */
2353 if (nvme_dev_add(dev))
2354 new_state = NVME_CTRL_ADMIN_ONLY;
302ad8cc 2355 nvme_unfreeze(&dev->ctrl);
3cf519b5
CH		 2356 }
2357
2b1b7e78
JW		 2358 /*
2359 * If only admin queue live, keep it to do further investigation or
2360 * recovery.
2361 */
2362 if (!nvme_change_ctrl_state(&dev->ctrl, new_state)) {
2363 dev_warn(dev->ctrl.device,
2364 "failed to mark controller state %d\n", new_state);
bb8d261e
CH		 2365 goto out;
2366 }
92911a55 2367
d09f2b45 2368 nvme_start_ctrl(&dev->ctrl);
3cf519b5 2369 return;
f0b50732 2370
3cf519b5 2371 out:
f58944e2 2372 nvme_remove_dead_ctrl(dev, result);
f0b50732
KB		 2373}
2374
5c8809e6 2375static void nvme_remove_dead_ctrl_work(struct work_struct *work)
9a6b9458 2376{
5c8809e6 2377 struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
e75ec752 2378 struct pci_dev *pdev = to_pci_dev(dev->dev);
9a6b9458
KB		 2379
2380 if (pci_get_drvdata(pdev))
921920ab 2381 device_release_driver(&pdev->dev);
1673f1f0 2382 nvme_put_ctrl(&dev->ctrl);
9a6b9458
KB		 2383}
2384
1c63dc66 2385static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
9ca97374 2386{
1c63dc66 2387 *val = readl(to_nvme_dev(ctrl)->bar + off);
90667892 2388 return 0;
9ca97374
TH		 2389}
2390
5fd4ce1b 2391static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
4cc06521 2392{
5fd4ce1b
CH		 2393 writel(val, to_nvme_dev(ctrl)->bar + off);
2394 return 0;
2395}
4cc06521 2396
7fd8930f
CH		 2397static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2398{
2399 *val = readq(to_nvme_dev(ctrl)->bar + off);
2400 return 0;
4cc06521
KB		 2401}
2402
97c12223
KB		 2403static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
2404{
2405 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2406
2407 return snprintf(buf, size, "%s", dev_name(&pdev->dev));
2408}
2409
1c63dc66 2410static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
1a353d85 2411 .name = "pcie",
e439bb12 2412 .module = THIS_MODULE,
e0596ab2
LG		 2413 .flags = NVME_F_METADATA_SUPPORTED |
2414 NVME_F_PCI_P2PDMA,
1c63dc66 2415 .reg_read32 = nvme_pci_reg_read32,
5fd4ce1b 2416 .reg_write32 = nvme_pci_reg_write32,
7fd8930f 2417 .reg_read64 = nvme_pci_reg_read64,
1673f1f0 2418 .free_ctrl = nvme_pci_free_ctrl,
f866fc42 2419 .submit_async_event = nvme_pci_submit_async_event,
97c12223 2420 .get_address = nvme_pci_get_address,
1c63dc66 2421};
4cc06521 2422
b00a726a
KB		 2423static int nvme_dev_map(struct nvme_dev *dev)
2424{
b00a726a
KB		 2425 struct pci_dev *pdev = to_pci_dev(dev->dev);
2426
a1f447b3 2427 if (pci_request_mem_regions(pdev, "nvme"))
b00a726a
KB		 2428 return -ENODEV;
2429
97f6ef64 2430 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
b00a726a
KB		 2431 goto release;
2432
9fa196e7 2433 return 0;
b00a726a 2434 release:
9fa196e7
MG		 2435 pci_release_mem_regions(pdev);
2436 return -ENODEV;
b00a726a
KB		 2437}
2438
8427bbc2 2439static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
ff5350a8
AL		 2440{
2441 if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
2442 /*
2443 * Several Samsung devices seem to drop off the PCIe bus
2444 * randomly when APST is on and uses the deepest sleep state.
2445 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2446 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2447 * 950 PRO 256GB", but it seems to be restricted to two Dell
2448 * laptops.
2449 */
2450 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
2451 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
2452 dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
2453 return NVME_QUIRK_NO_DEEPEST_PS;
8427bbc2
KHF		 2454 } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
2455 /*
2456 * Samsung SSD 960 EVO drops off the PCIe bus after system
467c77d4
JJ		 2457 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
2458 * within few minutes after bootup on a Coffee Lake board -
2459 * ASUS PRIME Z370-A
8427bbc2
KHF		 2460 */
2461 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
467c77d4
JJ		 2462 (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") ||
2463 dmi_match(DMI_BOARD_NAME, "PRIME Z370-A")))
8427bbc2 2464 return NVME_QUIRK_NO_APST;
ff5350a8
AL		 2465 }
2466
2467 return 0;
2468}
2469
18119775
KB		 2470static void nvme_async_probe(void *data, async_cookie_t cookie)
2471{
2472 struct nvme_dev *dev = data;
80f513b5 2473
18119775
KB		 2474 nvme_reset_ctrl_sync(&dev->ctrl);
2475 flush_work(&dev->ctrl.scan_work);
80f513b5 2476 nvme_put_ctrl(&dev->ctrl);
18119775
KB		 2477}
2478
8d85fce7 2479static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
b60503ba 2480{
a4aea562 2481 int node, result = -ENOMEM;
b60503ba 2482 struct nvme_dev *dev;
ff5350a8 2483 unsigned long quirks = id->driver_data;
943e942e 2484 size_t alloc_size;
b60503ba 2485
a4aea562
MB		 2486 node = dev_to_node(&pdev->dev);
2487 if (node == NUMA_NO_NODE)
2fa84351 2488 set_dev_node(&pdev->dev, first_memory_node);
a4aea562
MB		 2489
2490 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
b60503ba
MW		 2491 if (!dev)
2492 return -ENOMEM;
147b27e4
SG		 2493
2494 dev->queues = kcalloc_node(num_possible_cpus() + 1,
2495 sizeof(struct nvme_queue), GFP_KERNEL, node);
b60503ba
MW		 2496 if (!dev->queues)
2497 goto free;
2498
e75ec752 2499 dev->dev = get_device(&pdev->dev);
9a6b9458 2500 pci_set_drvdata(pdev, dev);
1c63dc66 2501
b00a726a
KB		 2502 result = nvme_dev_map(dev);
2503 if (result)
b00c9b7a 2504 goto put_pci;
b00a726a 2505
d86c4d8e 2506 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
5c8809e6 2507 INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
77bf25ea 2508 mutex_init(&dev->shutdown_lock);
db3cbfff 2509 init_completion(&dev->ioq_wait);
b60503ba 2510
091b6092
MW		 2511 result = nvme_setup_prp_pools(dev);
2512 if (result)
b00c9b7a 2513 goto unmap;
4cc06521 2514
8427bbc2 2515 quirks |= check_vendor_combination_bug(pdev);
ff5350a8 2516
943e942e
JA		 2517 /*
2518 * Double check that our mempool alloc size will cover the biggest
2519 * command we support.
2520 */
2521 alloc_size = nvme_pci_iod_alloc_size(dev, NVME_MAX_KB_SZ,
2522 NVME_MAX_SEGS, true);
2523 WARN_ON_ONCE(alloc_size > PAGE_SIZE);
2524
2525 dev->iod_mempool = mempool_create_node(1, mempool_kmalloc,
2526 mempool_kfree,
2527 (void *) alloc_size,
2528 GFP_KERNEL, node);
2529 if (!dev->iod_mempool) {
2530 result = -ENOMEM;
2531 goto release_pools;
2532 }
2533
b6e44b4c
KB		 2534 result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
2535 quirks);
2536 if (result)
2537 goto release_mempool;
2538
1b3c47c1
SG		 2539 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
2540
80f513b5 2541 nvme_get_ctrl(&dev->ctrl);
18119775 2542 async_schedule(nvme_async_probe, dev);
4caff8fc 2543
b60503ba
MW		 2544 return 0;
2545
b6e44b4c
KB		 2546 release_mempool:
2547 mempool_destroy(dev->iod_mempool);
0877cb0d 2548 release_pools:
091b6092 2549 nvme_release_prp_pools(dev);
b00c9b7a
CJ		 2550 unmap:
2551 nvme_dev_unmap(dev);
a96d4f5c 2552 put_pci:
e75ec752 2553 put_device(dev->dev);
b60503ba
MW		 2554 free:
2555 kfree(dev->queues);
b60503ba
MW		 2556 kfree(dev);
2557 return result;
2558}
2559
775755ed 2560static void nvme_reset_prepare(struct pci_dev *pdev)
f0d54a54 2561{
a6739479 2562 struct nvme_dev *dev = pci_get_drvdata(pdev);
f263fbb8 2563 nvme_dev_disable(dev, false);
775755ed 2564}
f0d54a54 2565
775755ed
CH		 2566static void nvme_reset_done(struct pci_dev *pdev)
2567{
f263fbb8 2568 struct nvme_dev *dev = pci_get_drvdata(pdev);
79c48ccf 2569 nvme_reset_ctrl_sync(&dev->ctrl);
f0d54a54
KB		 2570}
2571
09ece142
KB		 2572static void nvme_shutdown(struct pci_dev *pdev)
2573{
2574 struct nvme_dev *dev = pci_get_drvdata(pdev);
a5cdb68c 2575 nvme_dev_disable(dev, true);
09ece142
KB		 2576}
2577
f58944e2
KB		 2578/*
2579 * The driver's remove may be called on a device in a partially initialized
2580 * state. This function must not have any dependencies on the device state in
2581 * order to proceed.
2582 */
8d85fce7 2583static void nvme_remove(struct pci_dev *pdev)
b60503ba
MW		 2584{
2585 struct nvme_dev *dev = pci_get_drvdata(pdev);
9a6b9458 2586
bb8d261e 2587 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
9a6b9458 2588 pci_set_drvdata(pdev, NULL);
0ff9d4e1 2589
6db28eda 2590 if (!pci_device_is_present(pdev)) {
0ff9d4e1 2591 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
1d39e692 2592 nvme_dev_disable(dev, true);
cb4bfda6 2593 nvme_dev_remove_admin(dev);
6db28eda 2594 }
0ff9d4e1 2595
d86c4d8e 2596 flush_work(&dev->ctrl.reset_work);
d09f2b45
SG		 2597 nvme_stop_ctrl(&dev->ctrl);
2598 nvme_remove_namespaces(&dev->ctrl);
a5cdb68c 2599 nvme_dev_disable(dev, true);
9fe5c59f 2600 nvme_release_cmb(dev);
87ad72a5 2601 nvme_free_host_mem(dev);
a4aea562 2602 nvme_dev_remove_admin(dev);
a1a5ef99 2603 nvme_free_queues(dev, 0);
d09f2b45 2604 nvme_uninit_ctrl(&dev->ctrl);
9a6b9458 2605 nvme_release_prp_pools(dev);
b00a726a 2606 nvme_dev_unmap(dev);
1673f1f0 2607 nvme_put_ctrl(&dev->ctrl);
b60503ba
MW		 2608}
2609
671a6018 2610#ifdef CONFIG_PM_SLEEP
cd638946
KB		 2611static int nvme_suspend(struct device *dev)
2612{
2613 struct pci_dev *pdev = to_pci_dev(dev);
2614 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2615
a5cdb68c 2616 nvme_dev_disable(ndev, true);
cd638946
KB		 2617 return 0;
2618}
2619
2620static int nvme_resume(struct device *dev)
2621{
2622 struct pci_dev *pdev = to_pci_dev(dev);
2623 struct nvme_dev *ndev = pci_get_drvdata(pdev);
cd638946 2624
d86c4d8e 2625 nvme_reset_ctrl(&ndev->ctrl);
9a6b9458 2626 return 0;
cd638946 2627}
671a6018 2628#endif
cd638946
KB		 2629
2630static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
b60503ba 2631
a0a3408e
KB		 2632static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
2633 pci_channel_state_t state)
2634{
2635 struct nvme_dev *dev = pci_get_drvdata(pdev);
2636
2637 /*
2638 * A frozen channel requires a reset. When detected, this method will
2639 * shutdown the controller to quiesce. The controller will be restarted
2640 * after the slot reset through driver's slot_reset callback.
2641 */
a0a3408e
KB		 2642 switch (state) {
2643 case pci_channel_io_normal:
2644 return PCI_ERS_RESULT_CAN_RECOVER;
2645 case pci_channel_io_frozen:
d011fb31
KB		 2646 dev_warn(dev->ctrl.device,
2647 "frozen state error detected, reset controller\n");
a5cdb68c 2648 nvme_dev_disable(dev, false);
a0a3408e
KB		 2649 return PCI_ERS_RESULT_NEED_RESET;
2650 case pci_channel_io_perm_failure:
d011fb31
KB		 2651 dev_warn(dev->ctrl.device,
2652 "failure state error detected, request disconnect\n");
a0a3408e
KB		 2653 return PCI_ERS_RESULT_DISCONNECT;
2654 }
2655 return PCI_ERS_RESULT_NEED_RESET;
2656}
2657
2658static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
2659{
2660 struct nvme_dev *dev = pci_get_drvdata(pdev);
2661
1b3c47c1 2662 dev_info(dev->ctrl.device, "restart after slot reset\n");
a0a3408e 2663 pci_restore_state(pdev);
d86c4d8e 2664 nvme_reset_ctrl(&dev->ctrl);
a0a3408e
KB		 2665 return PCI_ERS_RESULT_RECOVERED;
2666}
2667
2668static void nvme_error_resume(struct pci_dev *pdev)
2669{
72cd4cc2
KB		 2670 struct nvme_dev *dev = pci_get_drvdata(pdev);
2671
2672 flush_work(&dev->ctrl.reset_work);
a0a3408e
KB		 2673}
2674
1d352035 2675static const struct pci_error_handlers nvme_err_handler = {
b60503ba 2676 .error_detected = nvme_error_detected,
b60503ba
MW		 2677 .slot_reset = nvme_slot_reset,
2678 .resume = nvme_error_resume,
775755ed
CH		 2679 .reset_prepare = nvme_reset_prepare,
2680 .reset_done = nvme_reset_done,
b60503ba
MW		 2681};
2682
6eb0d698 2683static const struct pci_device_id nvme_id_table[] = {
106198ed 2684 { PCI_VDEVICE(INTEL, 0x0953),
08095e70 2685 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 2686 NVME_QUIRK_DEALLOCATE_ZEROES, },
99466e70
KB		 2687 { PCI_VDEVICE(INTEL, 0x0a53),
2688 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 2689 NVME_QUIRK_DEALLOCATE_ZEROES, },
99466e70
KB		 2690 { PCI_VDEVICE(INTEL, 0x0a54),
2691 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 2692 NVME_QUIRK_DEALLOCATE_ZEROES, },
f99cb7af
DWF		 2693 { PCI_VDEVICE(INTEL, 0x0a55),
2694 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2695 NVME_QUIRK_DEALLOCATE_ZEROES, },
50af47d0 2696 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */
9abd68ef
JA		 2697 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
2698 NVME_QUIRK_MEDIUM_PRIO_SQ },
540c801c
KB		 2699 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */
2700 .driver_data = NVME_QUIRK_IDENTIFY_CNS, },
0302ae60
MP		 2701 { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */
2702 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
54adc010
GP		 2703 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
2704 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
8c97eecc
JL		 2705 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */
2706 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
015282c9
WW		 2707 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
2708 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
d554b5e1
MP		 2709 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */
2710 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2711 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */
2712 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
608cc4b1
CH		 2713 { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */
2714 .driver_data = NVME_QUIRK_LIGHTNVM, },
2715 { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */
2716 .driver_data = NVME_QUIRK_LIGHTNVM, },
ea48e877
WX		 2717 { PCI_DEVICE(0x1d1d, 0x2601), /* CNEX Granby */
2718 .driver_data = NVME_QUIRK_LIGHTNVM, },
b60503ba 2719 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
c74dc780 2720 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) },
124298bd 2721 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
b60503ba
MW		 2722 { 0, }
2723};
2724MODULE_DEVICE_TABLE(pci, nvme_id_table);
2725
2726static struct pci_driver nvme_driver = {
2727 .name = "nvme",
2728 .id_table = nvme_id_table,
2729 .probe = nvme_probe,
8d85fce7 2730 .remove = nvme_remove,
09ece142 2731 .shutdown = nvme_shutdown,
cd638946
KB		 2732 .driver = {
2733 .pm = &nvme_dev_pm_ops,
2734 },
74d986ab 2735 .sriov_configure = pci_sriov_configure_simple,
b60503ba
MW		 2736 .err_handler = &nvme_err_handler,
2737};
2738
2739static int __init nvme_init(void)
2740{
9a6327d2 2741 return pci_register_driver(&nvme_driver);
b60503ba
MW		 2742}
2743
2744static void __exit nvme_exit(void)
2745{
2746 pci_unregister_driver(&nvme_driver);
03e0f3a6 2747 flush_workqueue(nvme_wq);
21bd78bc 2748 _nvme_check_size();
b60503ba
MW		 2749}
2750
2751MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2752MODULE_LICENSE("GPL");
c78b4713 2753MODULE_VERSION("1.0");
b60503ba
MW		 2754module_init(nvme_init);
2755module_exit(nvme_exit);
Linux 6.x block layer and io_uring tree(s)