projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
nvme-pci: place descriptor addresses in iod
[linux-2.6-block.git] / drivers / nvme / host / pci.c
CommitLineData
5f37396d 1// SPDX-License-Identifier: GPL-2.0
b60503ba
MW		 2/*
3 * NVM Express device driver
6eb0d698 4 * Copyright (c) 2011-2014, Intel Corporation.
b60503ba
MW		 5 */
6
df4f9bc4 7#include <linux/acpi.h>
a0a3408e 8#include <linux/aer.h>
18119775 9#include <linux/async.h>
b60503ba 10#include <linux/blkdev.h>
a4aea562 11#include <linux/blk-mq.h>
dca51e78 12#include <linux/blk-mq-pci.h>
fe45e630 13#include <linux/blk-integrity.h>
ff5350a8 14#include <linux/dmi.h>
b60503ba
MW		 15#include <linux/init.h>
16#include <linux/interrupt.h>
17#include <linux/io.h>
99722c8a 18#include <linux/kstrtox.h>
dc90f084 19#include <linux/memremap.h>
b60503ba
MW		 20#include <linux/mm.h>
21#include <linux/module.h>
77bf25ea 22#include <linux/mutex.h>
d0877473 23#include <linux/once.h>
b60503ba 24#include <linux/pci.h>
d916b1be 25#include <linux/suspend.h>
e1e5e564 26#include <linux/t10-pi.h>
b60503ba 27#include <linux/types.h>
2f8e2c87 28#include <linux/io-64-nonatomic-lo-hi.h>
20d3bb92 29#include <linux/io-64-nonatomic-hi-lo.h>
a98e58e5 30#include <linux/sed-opal.h>
0f238ff5 31#include <linux/pci-p2pdma.h>
797a796a 32
604c01d5 33#include "trace.h"
f11bb3e2
CH		 34#include "nvme.h"
35
c1e0cc7e 36#define SQ_SIZE(q) ((q)->q_depth << (q)->sqes)
8a1d09a6 37#define CQ_SIZE(q) ((q)->q_depth * sizeof(struct nvme_completion))
c965809c 38
84173423 39#define SGES_PER_PAGE (NVME_CTRL_PAGE_SIZE / sizeof(struct nvme_sgl_desc))
9d43cf64 40
943e942e
JA		 41/*
42 * These can be higher, but we need to ensure that any command doesn't
43 * require an sg allocation that needs more than a page of data.
44 */
7846c1b5
KB		 45#define NVME_MAX_KB_SZ 8192
46#define NVME_MAX_SEGS 128
47#define NVME_MAX_NR_ALLOCATIONS 5
943e942e 48
58ffacb5 49static int use_threaded_interrupts;
2e21e445 50module_param(use_threaded_interrupts, int, 0444);
58ffacb5 51
8ffaadf7 52static bool use_cmb_sqes = true;
69f4eb9f 53module_param(use_cmb_sqes, bool, 0444);
8ffaadf7
JD		 54MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
55
87ad72a5
CH		 56static unsigned int max_host_mem_size_mb = 128;
57module_param(max_host_mem_size_mb, uint, 0444);
58MODULE_PARM_DESC(max_host_mem_size_mb,
59 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
1fa6aead 60
a7a7cbe3
CK		 61static unsigned int sgl_threshold = SZ_32K;
62module_param(sgl_threshold, uint, 0644);
63MODULE_PARM_DESC(sgl_threshold,
64 "Use SGLs when average request segment size is larger or equal to "
65 "this size. Use 0 to disable SGLs.");
66
27453b45
SG		 67#define NVME_PCI_MIN_QUEUE_SIZE 2
68#define NVME_PCI_MAX_QUEUE_SIZE 4095
b27c1e68 69static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
70static const struct kernel_param_ops io_queue_depth_ops = {
71 .set = io_queue_depth_set,
61f3b896 72 .get = param_get_uint,
b27c1e68 73};
74
61f3b896 75static unsigned int io_queue_depth = 1024;
b27c1e68 76module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
27453b45 77MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2 and < 4096");
b27c1e68 78
9c9e76d5
WZ		 79static int io_queue_count_set(const char *val, const struct kernel_param *kp)
80{
81 unsigned int n;
82 int ret;
83
84 ret = kstrtouint(val, 10, &n);
85 if (ret != 0 || n > num_possible_cpus())
86 return -EINVAL;
87 return param_set_uint(val, kp);
88}
89
90static const struct kernel_param_ops io_queue_count_ops = {
91 .set = io_queue_count_set,
92 .get = param_get_uint,
93};
94
3f68baf7 95static unsigned int write_queues;
9c9e76d5 96module_param_cb(write_queues, &io_queue_count_ops, &write_queues, 0644);
3b6592f7
JA		 97MODULE_PARM_DESC(write_queues,
98 "Number of queues to use for writes. If not set, reads and writes "
99 "will share a queue set.");
100
3f68baf7 101static unsigned int poll_queues;
9c9e76d5 102module_param_cb(poll_queues, &io_queue_count_ops, &poll_queues, 0644);
4b04cc6a
JA		 103MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO.");
104
df4f9bc4
DB		 105static bool noacpi;
106module_param(noacpi, bool, 0444);
107MODULE_PARM_DESC(noacpi, "disable acpi bios quirks");
108
1c63dc66
CH		 109struct nvme_dev;
110struct nvme_queue;
b3fffdef 111
a5cdb68c 112static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
7d879c90 113static void nvme_delete_io_queues(struct nvme_dev *dev);
d4b4ff8e 114
1c63dc66
CH		 115/*
116 * Represents an NVM Express device. Each nvme_dev is a PCI function.
117 */
118struct nvme_dev {
147b27e4 119 struct nvme_queue *queues;
1c63dc66
CH		 120 struct blk_mq_tag_set tagset;
121 struct blk_mq_tag_set admin_tagset;
122 u32 __iomem *dbs;
123 struct device *dev;
124 struct dma_pool *prp_page_pool;
125 struct dma_pool *prp_small_pool;
1c63dc66
CH		 126 unsigned online_queues;
127 unsigned max_qid;
e20ba6e1 128 unsigned io_queues[HCTX_MAX_TYPES];
22b55601 129 unsigned int num_vecs;
7442ddce 130 u32 q_depth;
c1e0cc7e 131 int io_sqes;
1c63dc66 132 u32 db_stride;
1c63dc66 133 void __iomem *bar;
97f6ef64 134 unsigned long bar_mapped_size;
77bf25ea 135 struct mutex shutdown_lock;
1c63dc66 136 bool subsystem;
1c63dc66 137 u64 cmb_size;
0f238ff5 138 bool cmb_use_sqes;
1c63dc66 139 u32 cmbsz;
202021c1 140 u32 cmbloc;
1c63dc66 141 struct nvme_ctrl ctrl;
d916b1be 142 u32 last_ps;
a5df5e79 143 bool hmb;
87ad72a5 144
943e942e
JA		 145 mempool_t *iod_mempool;
146
87ad72a5 147 /* shadow doorbell buffer support: */
b5f96cb7 148 __le32 *dbbuf_dbs;
f9f38e33 149 dma_addr_t dbbuf_dbs_dma_addr;
b5f96cb7 150 __le32 *dbbuf_eis;
f9f38e33 151 dma_addr_t dbbuf_eis_dma_addr;
87ad72a5
CH		 152
153 /* host memory buffer support: */
154 u64 host_mem_size;
155 u32 nr_host_mem_descs;
4033f35d 156 dma_addr_t host_mem_descs_dma;
87ad72a5
CH		 157 struct nvme_host_mem_buf_desc *host_mem_descs;
158 void **host_mem_desc_bufs;
2a5bcfdd
WZ		 159 unsigned int nr_allocated_queues;
160 unsigned int nr_write_queues;
161 unsigned int nr_poll_queues;
4d115420 162};
1fa6aead 163
b27c1e68 164static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
165{
27453b45
SG		 166 return param_set_uint_minmax(val, kp, NVME_PCI_MIN_QUEUE_SIZE,
167 NVME_PCI_MAX_QUEUE_SIZE);
b27c1e68 168}
169
f9f38e33
HK		 170static inline unsigned int sq_idx(unsigned int qid, u32 stride)
171{
172 return qid * 2 * stride;
173}
174
175static inline unsigned int cq_idx(unsigned int qid, u32 stride)
176{
177 return (qid * 2 + 1) * stride;
178}
179
1c63dc66
CH		 180static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
181{
182 return container_of(ctrl, struct nvme_dev, ctrl);
183}
184
b60503ba
MW		 185/*
186 * An NVM Express queue. Each device has at least two (one for admin
187 * commands and one for I/O commands).
188 */
189struct nvme_queue {
091b6092 190 struct nvme_dev *dev;
1ab0cd69 191 spinlock_t sq_lock;
c1e0cc7e 192 void *sq_cmds;
3a7afd8e
CH		 193 /* only used for poll queues: */
194 spinlock_t cq_poll_lock ____cacheline_aligned_in_smp;
74943d45 195 struct nvme_completion *cqes;
b60503ba
MW		 196 dma_addr_t sq_dma_addr;
197 dma_addr_t cq_dma_addr;
b60503ba 198 u32 __iomem *q_db;
7442ddce 199 u32 q_depth;
7c349dde 200 u16 cq_vector;
b60503ba 201 u16 sq_tail;
38210800 202 u16 last_sq_tail;
b60503ba 203 u16 cq_head;
c30341dc 204 u16 qid;
e9539f47 205 u8 cq_phase;
c1e0cc7e 206 u8 sqes;
4e224106
CH		 207 unsigned long flags;
208#define NVMEQ_ENABLED 0
63223078 209#define NVMEQ_SQ_CMB 1
d1ed6aa1 210#define NVMEQ_DELETE_ERROR 2
7c349dde 211#define NVMEQ_POLLED 3
b5f96cb7
KJ		 212 __le32 *dbbuf_sq_db;
213 __le32 *dbbuf_cq_db;
214 __le32 *dbbuf_sq_ei;
215 __le32 *dbbuf_cq_ei;
d1ed6aa1 216 struct completion delete_done;
b60503ba
MW		 217};
218
7846c1b5
KB		 219union nvme_descriptor {
220 struct nvme_sgl_desc *sg_list;
221 __le64 *prp_list;
222};
223
71bd150c 224/*
9b048119
CH		 225 * The nvme_iod describes the data in an I/O.
226 *
227 * The sg pointer contains the list of PRP/SGL chunk allocations in addition
228 * to the actual struct scatterlist.
71bd150c
CH		 229 */
230struct nvme_iod {
d49187e9 231 struct nvme_request req;
af7fae85 232 struct nvme_command cmd;
a7a7cbe3 233 bool use_sgl;
52da4f3f 234 bool aborted;
c372cdd1
KB		 235 s8 nr_allocations; /* PRP list pool allocations. 0 means small
236 pool in use */
dff824b2 237 unsigned int dma_len; /* length of single DMA segment mapping */
c4c22c52 238 dma_addr_t first_dma;
783b94bd 239 dma_addr_t meta_dma;
91fb2b60 240 struct sg_table sgt;
7846c1b5 241 union nvme_descriptor list[NVME_MAX_NR_ALLOCATIONS];
b60503ba
MW		 242};
243
2a5bcfdd 244static inline unsigned int nvme_dbbuf_size(struct nvme_dev *dev)
3b6592f7 245{
2a5bcfdd 246 return dev->nr_allocated_queues * 8 * dev->db_stride;
f9f38e33
HK		 247}
248
65a54646 249static void nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
f9f38e33 250{
2a5bcfdd 251 unsigned int mem_size = nvme_dbbuf_size(dev);
f9f38e33 252
65a54646
CH		 253 if (!(dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP))
254 return;
255
58847f12
KB		 256 if (dev->dbbuf_dbs) {
257 /*
258 * Clear the dbbuf memory so the driver doesn't observe stale
259 * values from the previous instantiation.
260 */
261 memset(dev->dbbuf_dbs, 0, mem_size);
262 memset(dev->dbbuf_eis, 0, mem_size);
65a54646 263 return;
58847f12 264 }
f9f38e33
HK		 265
266 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
267 &dev->dbbuf_dbs_dma_addr,
268 GFP_KERNEL);
269 if (!dev->dbbuf_dbs)
65a54646 270 goto fail;
f9f38e33
HK		 271 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
272 &dev->dbbuf_eis_dma_addr,
273 GFP_KERNEL);
65a54646
CH		 274 if (!dev->dbbuf_eis)
275 goto fail_free_dbbuf_dbs;
276 return;
f9f38e33 277
65a54646
CH		 278fail_free_dbbuf_dbs:
279 dma_free_coherent(dev->dev, mem_size, dev->dbbuf_dbs,
280 dev->dbbuf_dbs_dma_addr);
281 dev->dbbuf_dbs = NULL;
282fail:
283 dev_warn(dev->dev, "unable to allocate dma for dbbuf\n");
f9f38e33
HK		 284}
285
286static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
287{
2a5bcfdd 288 unsigned int mem_size = nvme_dbbuf_size(dev);
f9f38e33
HK		 289
290 if (dev->dbbuf_dbs) {
291 dma_free_coherent(dev->dev, mem_size,
292 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
293 dev->dbbuf_dbs = NULL;
294 }
295 if (dev->dbbuf_eis) {
296 dma_free_coherent(dev->dev, mem_size,
297 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
298 dev->dbbuf_eis = NULL;
299 }
300}
301
302static void nvme_dbbuf_init(struct nvme_dev *dev,
303 struct nvme_queue *nvmeq, int qid)
304{
305 if (!dev->dbbuf_dbs || !qid)
306 return;
307
308 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
309 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
310 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
311 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
312}
313
0f0d2c87
MI		 314static void nvme_dbbuf_free(struct nvme_queue *nvmeq)
315{
316 if (!nvmeq->qid)
317 return;
318
319 nvmeq->dbbuf_sq_db = NULL;
320 nvmeq->dbbuf_cq_db = NULL;
321 nvmeq->dbbuf_sq_ei = NULL;
322 nvmeq->dbbuf_cq_ei = NULL;
323}
324
f9f38e33
HK		 325static void nvme_dbbuf_set(struct nvme_dev *dev)
326{
f66e2804 327 struct nvme_command c = { };
0f0d2c87 328 unsigned int i;
f9f38e33
HK		 329
330 if (!dev->dbbuf_dbs)
331 return;
332
f9f38e33
HK		 333 c.dbbuf.opcode = nvme_admin_dbbuf;
334 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
335 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
336
337 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
9bdcfb10 338 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
f9f38e33
HK		 339 /* Free memory and continue on */
340 nvme_dbbuf_dma_free(dev);
0f0d2c87
MI		 341
342 for (i = 1; i <= dev->online_queues; i++)
343 nvme_dbbuf_free(&dev->queues[i]);
f9f38e33
HK		 344 }
345}
346
347static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
348{
349 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
350}
351
352/* Update dbbuf and return true if an MMIO is required */
b5f96cb7
KJ		 353static bool nvme_dbbuf_update_and_check_event(u16 value, __le32 *dbbuf_db,
354 volatile __le32 *dbbuf_ei)
f9f38e33
HK		 355{
356 if (dbbuf_db) {
b5f96cb7 357 u16 old_value, event_idx;
f9f38e33
HK		 358
359 /*
360 * Ensure that the queue is written before updating
361 * the doorbell in memory
362 */
363 wmb();
364
b5f96cb7
KJ		 365 old_value = le32_to_cpu(*dbbuf_db);
366 *dbbuf_db = cpu_to_le32(value);
f9f38e33 367
f1ed3df2
MW		 368 /*
369 * Ensure that the doorbell is updated before reading the event
370 * index from memory. The controller needs to provide similar
371 * ordering to ensure the envent index is updated before reading
372 * the doorbell.
373 */
374 mb();
375
b5f96cb7
KJ		 376 event_idx = le32_to_cpu(*dbbuf_ei);
377 if (!nvme_dbbuf_need_event(event_idx, value, old_value))
f9f38e33
HK		 378 return false;
379 }
380
381 return true;
b60503ba
MW		 382}
383
ac3dd5bd
JA		 384/*
385 * Will slightly overestimate the number of pages needed. This is OK
386 * as it only leads to a small amount of wasted memory for the lifetime of
387 * the I/O.
388 */
b13c6393 389static int nvme_pci_npages_prp(void)
ac3dd5bd 390{
c89a529e
KB		 391 unsigned max_bytes = (NVME_MAX_KB_SZ * 1024) + NVME_CTRL_PAGE_SIZE;
392 unsigned nprps = DIV_ROUND_UP(max_bytes, NVME_CTRL_PAGE_SIZE);
84173423 393 return DIV_ROUND_UP(8 * nprps, NVME_CTRL_PAGE_SIZE - 8);
ac3dd5bd
JA		 394}
395
a4aea562
MB		 396static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
397 unsigned int hctx_idx)
e85248e5 398{
0da7feaa 399 struct nvme_dev *dev = to_nvme_dev(data);
147b27e4 400 struct nvme_queue *nvmeq = &dev->queues[0];
a4aea562 401
42483228
KB		 402 WARN_ON(hctx_idx != 0);
403 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
42483228 404
a4aea562
MB		 405 hctx->driver_data = nvmeq;
406 return 0;
e85248e5
MW		 407}
408
a4aea562
MB		 409static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
410 unsigned int hctx_idx)
b60503ba 411{
0da7feaa 412 struct nvme_dev *dev = to_nvme_dev(data);
147b27e4 413 struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
a4aea562 414
42483228 415 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
a4aea562
MB		 416 hctx->driver_data = nvmeq;
417 return 0;
b60503ba
MW		 418}
419
e559398f
CH		 420static int nvme_pci_init_request(struct blk_mq_tag_set *set,
421 struct request *req, unsigned int hctx_idx,
422 unsigned int numa_node)
b60503ba 423{
0da7feaa 424 struct nvme_dev *dev = to_nvme_dev(set->driver_data);
f4800d6d 425 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
59e29ce6
SG		 426
427 nvme_req(req)->ctrl = &dev->ctrl;
f4b9e6c9 428 nvme_req(req)->cmd = &iod->cmd;
a4aea562
MB		 429 return 0;
430}
431
3b6592f7
JA		 432static int queue_irq_offset(struct nvme_dev *dev)
433{
434 /* if we have more than 1 vec, admin queue offsets us by 1 */
435 if (dev->num_vecs > 1)
436 return 1;
437
438 return 0;
439}
440
a4e1d0b7 441static void nvme_pci_map_queues(struct blk_mq_tag_set *set)
dca51e78 442{
0da7feaa 443 struct nvme_dev *dev = to_nvme_dev(set->driver_data);
3b6592f7
JA		 444 int i, qoff, offset;
445
446 offset = queue_irq_offset(dev);
447 for (i = 0, qoff = 0; i < set->nr_maps; i++) {
448 struct blk_mq_queue_map *map = &set->map[i];
449
450 map->nr_queues = dev->io_queues[i];
451 if (!map->nr_queues) {
e20ba6e1 452 BUG_ON(i == HCTX_TYPE_DEFAULT);
7e849dd9 453 continue;
3b6592f7
JA		 454 }
455
4b04cc6a
JA		 456 /*
457 * The poll queue(s) doesn't have an IRQ (and hence IRQ
458 * affinity), so use the regular blk-mq cpu mapping
459 */
3b6592f7 460 map->queue_offset = qoff;
cb9e0e50 461 if (i != HCTX_TYPE_POLL && offset)
4b04cc6a
JA		 462 blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset);
463 else
464 blk_mq_map_queues(map);
3b6592f7
JA		 465 qoff += map->nr_queues;
466 offset += map->nr_queues;
467 }
dca51e78
CH		 468}
469
38210800
KB		 470/*
471 * Write sq tail if we are asked to, or if the next command would wrap.
472 */
473static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq)
04f3eafd 474{
38210800
KB		 475 if (!write_sq) {
476 u16 next_tail = nvmeq->sq_tail + 1;
477
478 if (next_tail == nvmeq->q_depth)
479 next_tail = 0;
480 if (next_tail != nvmeq->last_sq_tail)
481 return;
482 }
483
04f3eafd
JA		 484 if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail,
485 nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei))
486 writel(nvmeq->sq_tail, nvmeq->q_db);
38210800 487 nvmeq->last_sq_tail = nvmeq->sq_tail;
04f3eafd
JA		 488}
489
3233b94c
JA		 490static inline void nvme_sq_copy_cmd(struct nvme_queue *nvmeq,
491 struct nvme_command *cmd)
b60503ba 492{
c1e0cc7e 493 memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes),
3233b94c 494 absolute_pointer(cmd), sizeof(*cmd));
90ea5ca4
CH		 495 if (++nvmeq->sq_tail == nvmeq->q_depth)
496 nvmeq->sq_tail = 0;
04f3eafd
JA		 497}
498
499static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx)
500{
501 struct nvme_queue *nvmeq = hctx->driver_data;
502
503 spin_lock(&nvmeq->sq_lock);
38210800
KB		 504 if (nvmeq->sq_tail != nvmeq->last_sq_tail)
505 nvme_write_sq_db(nvmeq, true);
90ea5ca4 506 spin_unlock(&nvmeq->sq_lock);
b60503ba
MW		 507}
508
ae582935
KB		 509static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req,
510 int nseg)
955b1b5a 511{
a53232cb 512 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
955b1b5a
MI		 513 unsigned int avg_seg_size;
514
20469a37 515 avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
955b1b5a 516
253a0b76 517 if (!nvme_ctrl_sgl_supported(&dev->ctrl))
955b1b5a 518 return false;
a53232cb 519 if (!nvmeq->qid)
955b1b5a
MI		 520 return false;
521 if (!sgl_threshold || avg_seg_size < sgl_threshold)
522 return false;
523 return true;
524}
525
9275c206 526static void nvme_free_prps(struct nvme_dev *dev, struct request *req)
b60503ba 527{
6c3c05b0 528 const int last_prp = NVME_CTRL_PAGE_SIZE / sizeof(__le64) - 1;
9275c206
CH		 529 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
530 dma_addr_t dma_addr = iod->first_dma;
eca18b23 531 int i;
eca18b23 532
c372cdd1 533 for (i = 0; i < iod->nr_allocations; i++) {
7846c1b5 534 __le64 *prp_list = iod->list[i].prp_list;
9275c206
CH		 535 dma_addr_t next_dma_addr = le64_to_cpu(prp_list[last_prp]);
536
537 dma_pool_free(dev->prp_page_pool, prp_list, dma_addr);
538 dma_addr = next_dma_addr;
7fe07d14 539 }
9275c206 540}
dff824b2 541
9275c206
CH		 542static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
543{
544 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3 545
9275c206
CH		 546 if (iod->dma_len) {
547 dma_unmap_page(dev->dev, iod->first_dma, iod->dma_len,
548 rq_dma_dir(req));
549 return;
eca18b23 550 }
ac3dd5bd 551
91fb2b60
LG		 552 WARN_ON_ONCE(!iod->sgt.nents);
553
554 dma_unmap_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req), 0);
9275c206 555
c372cdd1 556 if (iod->nr_allocations == 0)
7846c1b5 557 dma_pool_free(dev->prp_small_pool, iod->list[0].sg_list,
9275c206
CH		 558 iod->first_dma);
559 else if (iod->use_sgl)
7846c1b5 560 dma_pool_free(dev->prp_page_pool, iod->list[0].sg_list,
01df742d 561 iod->first_dma);
9275c206
CH		 562 else
563 nvme_free_prps(dev, req);
91fb2b60 564 mempool_free(iod->sgt.sgl, dev->iod_mempool);
b4ff9c8d
KB		 565}
566
d0877473
KB		 567static void nvme_print_sgl(struct scatterlist *sgl, int nents)
568{
569 int i;
570 struct scatterlist *sg;
571
572 for_each_sg(sgl, sg, nents, i) {
573 dma_addr_t phys = sg_phys(sg);
574 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
575 "dma_address:%pad dma_length:%d\n",
576 i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
577 sg_dma_len(sg));
578 }
579}
580
a7a7cbe3
CK		 581static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
582 struct request *req, struct nvme_rw_command *cmnd)
ff22b54f 583{
f4800d6d 584 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
99802a7a 585 struct dma_pool *pool;
b131c61d 586 int length = blk_rq_payload_bytes(req);
91fb2b60 587 struct scatterlist *sg = iod->sgt.sgl;
ff22b54f
MW		 588 int dma_len = sg_dma_len(sg);
589 u64 dma_addr = sg_dma_address(sg);
6c3c05b0 590 int offset = dma_addr & (NVME_CTRL_PAGE_SIZE - 1);
e025344c
SMM		 591 __le64 *prp_list;
592 dma_addr_t prp_dma;
eca18b23 593 int nprps, i;
ff22b54f 594
6c3c05b0 595 length -= (NVME_CTRL_PAGE_SIZE - offset);
5228b328
JS		 596 if (length <= 0) {
597 iod->first_dma = 0;
a7a7cbe3 598 goto done;
5228b328 599 }
ff22b54f 600
6c3c05b0 601 dma_len -= (NVME_CTRL_PAGE_SIZE - offset);
ff22b54f 602 if (dma_len) {
6c3c05b0 603 dma_addr += (NVME_CTRL_PAGE_SIZE - offset);
ff22b54f
MW		 604 } else {
605 sg = sg_next(sg);
606 dma_addr = sg_dma_address(sg);
607 dma_len = sg_dma_len(sg);
608 }
609
6c3c05b0 610 if (length <= NVME_CTRL_PAGE_SIZE) {
edd10d33 611 iod->first_dma = dma_addr;
a7a7cbe3 612 goto done;
e025344c
SMM		 613 }
614
6c3c05b0 615 nprps = DIV_ROUND_UP(length, NVME_CTRL_PAGE_SIZE);
99802a7a
MW		 616 if (nprps <= (256 / 8)) {
617 pool = dev->prp_small_pool;
c372cdd1 618 iod->nr_allocations = 0;
99802a7a
MW		 619 } else {
620 pool = dev->prp_page_pool;
c372cdd1 621 iod->nr_allocations = 1;
99802a7a
MW		 622 }
623
69d2b571 624 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
b77954cb 625 if (!prp_list) {
c372cdd1 626 iod->nr_allocations = -1;
86eea289 627 return BLK_STS_RESOURCE;
b77954cb 628 }
7846c1b5 629 iod->list[0].prp_list = prp_list;
eca18b23 630 iod->first_dma = prp_dma;
e025344c
SMM		 631 i = 0;
632 for (;;) {
6c3c05b0 633 if (i == NVME_CTRL_PAGE_SIZE >> 3) {
e025344c 634 __le64 *old_prp_list = prp_list;
69d2b571 635 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
eca18b23 636 if (!prp_list)
fa073216 637 goto free_prps;
7846c1b5 638 iod->list[iod->nr_allocations++].prp_list = prp_list;
7523d834
MW		 639 prp_list[0] = old_prp_list[i - 1];
640 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
641 i = 1;
e025344c
SMM		 642 }
643 prp_list[i++] = cpu_to_le64(dma_addr);
6c3c05b0
CK		 644 dma_len -= NVME_CTRL_PAGE_SIZE;
645 dma_addr += NVME_CTRL_PAGE_SIZE;
646 length -= NVME_CTRL_PAGE_SIZE;
e025344c
SMM		 647 if (length <= 0)
648 break;
649 if (dma_len > 0)
650 continue;
86eea289
KB		 651 if (unlikely(dma_len < 0))
652 goto bad_sgl;
e025344c
SMM		 653 sg = sg_next(sg);
654 dma_addr = sg_dma_address(sg);
655 dma_len = sg_dma_len(sg);
ff22b54f 656 }
a7a7cbe3 657done:
91fb2b60 658 cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sgt.sgl));
a7a7cbe3 659 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
86eea289 660 return BLK_STS_OK;
fa073216
CH		 661free_prps:
662 nvme_free_prps(dev, req);
663 return BLK_STS_RESOURCE;
664bad_sgl:
91fb2b60 665 WARN(DO_ONCE(nvme_print_sgl, iod->sgt.sgl, iod->sgt.nents),
d0877473 666 "Invalid SGL for payload:%d nents:%d\n",
91fb2b60 667 blk_rq_payload_bytes(req), iod->sgt.nents);
86eea289 668 return BLK_STS_IOERR;
ff22b54f
MW		 669}
670
a7a7cbe3
CK		 671static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
672 struct scatterlist *sg)
673{
674 sge->addr = cpu_to_le64(sg_dma_address(sg));
675 sge->length = cpu_to_le32(sg_dma_len(sg));
676 sge->type = NVME_SGL_FMT_DATA_DESC << 4;
677}
678
679static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
680 dma_addr_t dma_addr, int entries)
681{
682 sge->addr = cpu_to_le64(dma_addr);
01df742d
KB		 683 sge->length = cpu_to_le32(entries * sizeof(*sge));
684 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
a7a7cbe3
CK		 685}
686
687static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
91fb2b60 688 struct request *req, struct nvme_rw_command *cmd)
a7a7cbe3
CK		 689{
690 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3
CK		 691 struct dma_pool *pool;
692 struct nvme_sgl_desc *sg_list;
91fb2b60
LG		 693 struct scatterlist *sg = iod->sgt.sgl;
694 unsigned int entries = iod->sgt.nents;
a7a7cbe3 695 dma_addr_t sgl_dma;
b0f2853b 696 int i = 0;
a7a7cbe3 697
a7a7cbe3
CK		 698 /* setting the transfer type as SGL */
699 cmd->flags = NVME_CMD_SGL_METABUF;
700
b0f2853b 701 if (entries == 1) {
a7a7cbe3
CK		 702 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
703 return BLK_STS_OK;
704 }
705
706 if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
707 pool = dev->prp_small_pool;
c372cdd1 708 iod->nr_allocations = 0;
a7a7cbe3
CK		 709 } else {
710 pool = dev->prp_page_pool;
c372cdd1 711 iod->nr_allocations = 1;
a7a7cbe3
CK		 712 }
713
714 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
715 if (!sg_list) {
c372cdd1 716 iod->nr_allocations = -1;
a7a7cbe3
CK		 717 return BLK_STS_RESOURCE;
718 }
719
7846c1b5 720 iod->list[0].sg_list = sg_list;
a7a7cbe3
CK		 721 iod->first_dma = sgl_dma;
722
723 nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
a7a7cbe3 724 do {
a7a7cbe3 725 nvme_pci_sgl_set_data(&sg_list[i++], sg);
a7a7cbe3 726 sg = sg_next(sg);
b0f2853b 727 } while (--entries > 0);
a7a7cbe3 728
a7a7cbe3
CK		 729 return BLK_STS_OK;
730}
731
dff824b2
CH		 732static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev,
733 struct request *req, struct nvme_rw_command *cmnd,
734 struct bio_vec *bv)
735{
736 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
6c3c05b0
CK		 737 unsigned int offset = bv->bv_offset & (NVME_CTRL_PAGE_SIZE - 1);
738 unsigned int first_prp_len = NVME_CTRL_PAGE_SIZE - offset;
dff824b2
CH		 739
740 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
741 if (dma_mapping_error(dev->dev, iod->first_dma))
742 return BLK_STS_RESOURCE;
743 iod->dma_len = bv->bv_len;
744
745 cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma);
746 if (bv->bv_len > first_prp_len)
747 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len);
a56ea614
LR		 748 else
749 cmnd->dptr.prp2 = 0;
359c1f88 750 return BLK_STS_OK;
dff824b2
CH		 751}
752
29791057
CH		 753static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev,
754 struct request *req, struct nvme_rw_command *cmnd,
755 struct bio_vec *bv)
756{
757 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
758
759 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
760 if (dma_mapping_error(dev->dev, iod->first_dma))
761 return BLK_STS_RESOURCE;
762 iod->dma_len = bv->bv_len;
763
049bf372 764 cmnd->flags = NVME_CMD_SGL_METABUF;
29791057
CH		 765 cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma);
766 cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len);
767 cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4;
359c1f88 768 return BLK_STS_OK;
29791057
CH		 769}
770
fc17b653 771static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
b131c61d 772 struct nvme_command *cmnd)
d29ec824 773{
f4800d6d 774 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
70479b71 775 blk_status_t ret = BLK_STS_RESOURCE;
91fb2b60 776 int rc;
d29ec824 777
dff824b2 778 if (blk_rq_nr_phys_segments(req) == 1) {
a53232cb 779 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
dff824b2
CH		 780 struct bio_vec bv = req_bvec(req);
781
782 if (!is_pci_p2pdma_page(bv.bv_page)) {
6c3c05b0 783 if (bv.bv_offset + bv.bv_len <= NVME_CTRL_PAGE_SIZE * 2)
dff824b2
CH		 784 return nvme_setup_prp_simple(dev, req,
785 &cmnd->rw, &bv);
29791057 786
a53232cb 787 if (nvmeq->qid && sgl_threshold &&
253a0b76 788 nvme_ctrl_sgl_supported(&dev->ctrl))
29791057
CH		 789 return nvme_setup_sgl_simple(dev, req,
790 &cmnd->rw, &bv);
dff824b2
CH		 791 }
792 }
793
794 iod->dma_len = 0;
91fb2b60
LG		 795 iod->sgt.sgl = mempool_alloc(dev->iod_mempool, GFP_ATOMIC);
796 if (!iod->sgt.sgl)
d43f1ccf 797 return BLK_STS_RESOURCE;
91fb2b60
LG		 798 sg_init_table(iod->sgt.sgl, blk_rq_nr_phys_segments(req));
799 iod->sgt.orig_nents = blk_rq_map_sg(req->q, req, iod->sgt.sgl);
800 if (!iod->sgt.orig_nents)
fa073216 801 goto out_free_sg;
d29ec824 802
91fb2b60
LG		 803 rc = dma_map_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req),
804 DMA_ATTR_NO_WARN);
805 if (rc) {
806 if (rc == -EREMOTEIO)
807 ret = BLK_STS_TARGET;
fa073216 808 goto out_free_sg;
91fb2b60 809 }
d29ec824 810
ae582935 811 iod->use_sgl = nvme_pci_use_sgls(dev, req, iod->sgt.nents);
955b1b5a 812 if (iod->use_sgl)
91fb2b60 813 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw);
a7a7cbe3
CK		 814 else
815 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
86eea289 816 if (ret != BLK_STS_OK)
fa073216
CH		 817 goto out_unmap_sg;
818 return BLK_STS_OK;
819
820out_unmap_sg:
91fb2b60 821 dma_unmap_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req), 0);
fa073216 822out_free_sg:
91fb2b60 823 mempool_free(iod->sgt.sgl, dev->iod_mempool);
4aedb705
CH		 824 return ret;
825}
3045c0d0 826
4aedb705
CH		 827static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req,
828 struct nvme_command *cmnd)
829{
830 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
00df5cb4 831
4aedb705
CH		 832 iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req),
833 rq_dma_dir(req), 0);
834 if (dma_mapping_error(dev->dev, iod->meta_dma))
835 return BLK_STS_IOERR;
836 cmnd->rw.metadata = cpu_to_le64(iod->meta_dma);
359c1f88 837 return BLK_STS_OK;
00df5cb4
MW		 838}
839
62451a2b 840static blk_status_t nvme_prep_rq(struct nvme_dev *dev, struct request *req)
edd10d33 841{
9b048119 842 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
ebe6d874 843 blk_status_t ret;
e1e5e564 844
52da4f3f 845 iod->aborted = false;
c372cdd1 846 iod->nr_allocations = -1;
91fb2b60 847 iod->sgt.nents = 0;
9b048119 848
62451a2b 849 ret = nvme_setup_cmd(req->q->queuedata, req);
fc17b653 850 if (ret)
f4800d6d 851 return ret;
a4aea562 852
fc17b653 853 if (blk_rq_nr_phys_segments(req)) {
62451a2b 854 ret = nvme_map_data(dev, req, &iod->cmd);
fc17b653 855 if (ret)
9b048119 856 goto out_free_cmd;
fc17b653 857 }
a4aea562 858
4aedb705 859 if (blk_integrity_rq(req)) {
62451a2b 860 ret = nvme_map_metadata(dev, req, &iod->cmd);
4aedb705
CH		 861 if (ret)
862 goto out_unmap_data;
863 }
864
6887fc64 865 nvme_start_request(req);
fc17b653 866 return BLK_STS_OK;
4aedb705
CH		 867out_unmap_data:
868 nvme_unmap_data(dev, req);
f9d03f96
CH		 869out_free_cmd:
870 nvme_cleanup_cmd(req);
ba1ca37e 871 return ret;
b60503ba 872}
e1e5e564 873
62451a2b
JA		 874/*
875 * NOTE: ns is NULL when called on the admin queue.
876 */
877static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
878 const struct blk_mq_queue_data *bd)
879{
880 struct nvme_queue *nvmeq = hctx->driver_data;
881 struct nvme_dev *dev = nvmeq->dev;
882 struct request *req = bd->rq;
883 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
884 blk_status_t ret;
885
886 /*
887 * We should not need to do this, but we're still using this to
888 * ensure we can drain requests on a dying queue.
889 */
890 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
891 return BLK_STS_IOERR;
892
893 if (unlikely(!nvme_check_ready(&dev->ctrl, req, true)))
894 return nvme_fail_nonready_command(&dev->ctrl, req);
895
896 ret = nvme_prep_rq(dev, req);
897 if (unlikely(ret))
898 return ret;
899 spin_lock(&nvmeq->sq_lock);
900 nvme_sq_copy_cmd(nvmeq, &iod->cmd);
901 nvme_write_sq_db(nvmeq, bd->last);
902 spin_unlock(&nvmeq->sq_lock);
903 return BLK_STS_OK;
904}
905
d62cbcf6
JA		 906static void nvme_submit_cmds(struct nvme_queue *nvmeq, struct request **rqlist)
907{
908 spin_lock(&nvmeq->sq_lock);
909 while (!rq_list_empty(*rqlist)) {
910 struct request *req = rq_list_pop(rqlist);
911 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
912
913 nvme_sq_copy_cmd(nvmeq, &iod->cmd);
914 }
915 nvme_write_sq_db(nvmeq, true);
916 spin_unlock(&nvmeq->sq_lock);
917}
918
919static bool nvme_prep_rq_batch(struct nvme_queue *nvmeq, struct request *req)
920{
921 /*
922 * We should not need to do this, but we're still using this to
923 * ensure we can drain requests on a dying queue.
924 */
925 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
926 return false;
927 if (unlikely(!nvme_check_ready(&nvmeq->dev->ctrl, req, true)))
928 return false;
929
930 req->mq_hctx->tags->rqs[req->tag] = req;
931 return nvme_prep_rq(nvmeq->dev, req) == BLK_STS_OK;
932}
933
934static void nvme_queue_rqs(struct request **rqlist)
935{
6bfec799 936 struct request *req, *next, *prev = NULL;
d62cbcf6
JA		 937 struct request *requeue_list = NULL;
938
6bfec799 939 rq_list_for_each_safe(rqlist, req, next) {
d62cbcf6
JA		 940 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
941
942 if (!nvme_prep_rq_batch(nvmeq, req)) {
943 /* detach 'req' and add to remainder list */
6bfec799
KB		 944 rq_list_move(rqlist, &requeue_list, req, prev);
945
946 req = prev;
947 if (!req)
948 continue;
d62cbcf6
JA		 949 }
950
6bfec799 951 if (!next || req->mq_hctx != next->mq_hctx) {
d62cbcf6 952 /* detach rest of list, and submit */
6bfec799 953 req->rq_next = NULL;
d62cbcf6 954 nvme_submit_cmds(nvmeq, rqlist);
6bfec799
KB		 955 *rqlist = next;
956 prev = NULL;
957 } else
958 prev = req;
959 }
d62cbcf6
JA		 960
961 *rqlist = requeue_list;
962}
963
c234a653 964static __always_inline void nvme_pci_unmap_rq(struct request *req)
eee417b0 965{
a53232cb
KB		 966 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
967 struct nvme_dev *dev = nvmeq->dev;
968
969 if (blk_integrity_rq(req)) {
970 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a4aea562 971
4aedb705
CH		 972 dma_unmap_page(dev->dev, iod->meta_dma,
973 rq_integrity_vec(req)->bv_len, rq_data_dir(req));
a53232cb
KB		 974 }
975
b15c592d 976 if (blk_rq_nr_phys_segments(req))
4aedb705 977 nvme_unmap_data(dev, req);
c234a653
JA		 978}
979
980static void nvme_pci_complete_rq(struct request *req)
981{
982 nvme_pci_unmap_rq(req);
77f02a7a 983 nvme_complete_rq(req);
b60503ba
MW		 984}
985
c234a653
JA		 986static void nvme_pci_complete_batch(struct io_comp_batch *iob)
987{
988 nvme_complete_batch(iob, nvme_pci_unmap_rq);
989}
990
d783e0bd 991/* We read the CQE phase first to check if the rest of the entry is valid */
750dde44 992static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq)
d783e0bd 993{
74943d45
KB		 994 struct nvme_completion *hcqe = &nvmeq->cqes[nvmeq->cq_head];
995
996 return (le16_to_cpu(READ_ONCE(hcqe->status)) & 1) == nvmeq->cq_phase;
d783e0bd
MR		 997}
998
eb281c82 999static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
b60503ba 1000{
eb281c82 1001 u16 head = nvmeq->cq_head;
adf68f21 1002
397c699f
KB		 1003 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
1004 nvmeq->dbbuf_cq_ei))
1005 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
eb281c82 1006}
aae239e1 1007
cfa27356
CH		 1008static inline struct blk_mq_tags *nvme_queue_tagset(struct nvme_queue *nvmeq)
1009{
1010 if (!nvmeq->qid)
1011 return nvmeq->dev->admin_tagset.tags[0];
1012 return nvmeq->dev->tagset.tags[nvmeq->qid - 1];
1013}
1014
c234a653
JA		 1015static inline void nvme_handle_cqe(struct nvme_queue *nvmeq,
1016 struct io_comp_batch *iob, u16 idx)
83a12fb7 1017{
74943d45 1018 struct nvme_completion *cqe = &nvmeq->cqes[idx];
62df8016 1019 __u16 command_id = READ_ONCE(cqe->command_id);
83a12fb7 1020 struct request *req;
adf68f21 1021
83a12fb7
SG		 1022 /*
1023 * AEN requests are special as they don't time out and can
1024 * survive any kind of queue freeze and often don't respond to
1025 * aborts. We don't even bother to allocate a struct request
1026 * for them but rather special case them here.
1027 */
62df8016 1028 if (unlikely(nvme_is_aen_req(nvmeq->qid, command_id))) {
83a12fb7
SG		 1029 nvme_complete_async_event(&nvmeq->dev->ctrl,
1030 cqe->status, &cqe->result);
a0fa9647 1031 return;
83a12fb7 1032 }
b60503ba 1033
e7006de6 1034 req = nvme_find_rq(nvme_queue_tagset(nvmeq), command_id);
50b7c243
XT		 1035 if (unlikely(!req)) {
1036 dev_warn(nvmeq->dev->ctrl.device,
1037 "invalid id %d completed on queue %d\n",
62df8016 1038 command_id, le16_to_cpu(cqe->sq_id));
50b7c243
XT		 1039 return;
1040 }
1041
604c01d5 1042 trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail);
c234a653
JA		 1043 if (!nvme_try_complete_req(req, cqe->status, cqe->result) &&
1044 !blk_mq_add_to_batch(req, iob, nvme_req(req)->status,
1045 nvme_pci_complete_batch))
ff029451 1046 nvme_pci_complete_rq(req);
83a12fb7 1047}
b60503ba 1048
5cb525c8
JA		 1049static inline void nvme_update_cq_head(struct nvme_queue *nvmeq)
1050{
a0aac973 1051 u32 tmp = nvmeq->cq_head + 1;
a8de6639
AD		 1052
1053 if (tmp == nvmeq->q_depth) {
5cb525c8 1054 nvmeq->cq_head = 0;
e2a366a4 1055 nvmeq->cq_phase ^= 1;
a8de6639
AD		 1056 } else {
1057 nvmeq->cq_head = tmp;
b60503ba 1058 }
a0fa9647
JA		 1059}
1060
c234a653
JA		 1061static inline int nvme_poll_cq(struct nvme_queue *nvmeq,
1062 struct io_comp_batch *iob)
a0fa9647 1063{
1052b8ac 1064 int found = 0;
b60503ba 1065
1052b8ac 1066 while (nvme_cqe_pending(nvmeq)) {
bf392a5d 1067 found++;
b69e2ef2
KB		 1068 /*
1069 * load-load control dependency between phase and the rest of
1070 * the cqe requires a full read memory barrier
1071 */
1072 dma_rmb();
c234a653 1073 nvme_handle_cqe(nvmeq, iob, nvmeq->cq_head);
5cb525c8 1074 nvme_update_cq_head(nvmeq);
920d13a8 1075 }
eb281c82 1076
324b494c 1077 if (found)
920d13a8 1078 nvme_ring_cq_doorbell(nvmeq);
5cb525c8 1079 return found;
b60503ba
MW		 1080}
1081
1082static irqreturn_t nvme_irq(int irq, void *data)
58ffacb5 1083{
58ffacb5 1084 struct nvme_queue *nvmeq = data;
4f502245 1085 DEFINE_IO_COMP_BATCH(iob);
5cb525c8 1086
4f502245
JA		 1087 if (nvme_poll_cq(nvmeq, &iob)) {
1088 if (!rq_list_empty(iob.req_list))
1089 nvme_pci_complete_batch(&iob);
05fae499 1090 return IRQ_HANDLED;
4f502245 1091 }
05fae499 1092 return IRQ_NONE;
58ffacb5
MW		 1093}
1094
1095static irqreturn_t nvme_irq_check(int irq, void *data)
1096{
1097 struct nvme_queue *nvmeq = data;
4e523547 1098
750dde44 1099 if (nvme_cqe_pending(nvmeq))
d783e0bd
MR		 1100 return IRQ_WAKE_THREAD;
1101 return IRQ_NONE;
58ffacb5
MW		 1102}
1103
0b2a8a9f 1104/*
fa059b85 1105 * Poll for completions for any interrupt driven queue
0b2a8a9f
CH		 1106 * Can be called from any context.
1107 */
fa059b85 1108static void nvme_poll_irqdisable(struct nvme_queue *nvmeq)
a0fa9647 1109{
3a7afd8e 1110 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
a0fa9647 1111
fa059b85 1112 WARN_ON_ONCE(test_bit(NVMEQ_POLLED, &nvmeq->flags));
442e19b7 1113
fa059b85 1114 disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
c234a653 1115 nvme_poll_cq(nvmeq, NULL);
fa059b85 1116 enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
a0fa9647
JA		 1117}
1118
5a72e899 1119static int nvme_poll(struct blk_mq_hw_ctx *hctx, struct io_comp_batch *iob)
dabcefab
JA		 1120{
1121 struct nvme_queue *nvmeq = hctx->driver_data;
dabcefab
JA		 1122 bool found;
1123
1124 if (!nvme_cqe_pending(nvmeq))
1125 return 0;
1126
3a7afd8e 1127 spin_lock(&nvmeq->cq_poll_lock);
c234a653 1128 found = nvme_poll_cq(nvmeq, iob);
3a7afd8e 1129 spin_unlock(&nvmeq->cq_poll_lock);
dabcefab 1130
dabcefab
JA		 1131 return found;
1132}
1133
ad22c355 1134static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
b60503ba 1135{
f866fc42 1136 struct nvme_dev *dev = to_nvme_dev(ctrl);
147b27e4 1137 struct nvme_queue *nvmeq = &dev->queues[0];
f66e2804 1138 struct nvme_command c = { };
b60503ba 1139
a4aea562 1140 c.common.opcode = nvme_admin_async_event;
ad22c355 1141 c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
3233b94c
JA		 1142
1143 spin_lock(&nvmeq->sq_lock);
1144 nvme_sq_copy_cmd(nvmeq, &c);
1145 nvme_write_sq_db(nvmeq, true);
1146 spin_unlock(&nvmeq->sq_lock);
f705f837
CH		 1147}
1148
b60503ba 1149static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
f705f837 1150{
f66e2804 1151 struct nvme_command c = { };
b60503ba 1152
b60503ba
MW		 1153 c.delete_queue.opcode = opcode;
1154 c.delete_queue.qid = cpu_to_le16(id);
1155
1c63dc66 1156 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1157}
1158
b60503ba 1159static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
a8e3e0bb 1160 struct nvme_queue *nvmeq, s16 vector)
b60503ba 1161{
f66e2804 1162 struct nvme_command c = { };
4b04cc6a
JA		 1163 int flags = NVME_QUEUE_PHYS_CONTIG;
1164
7c349dde 1165 if (!test_bit(NVMEQ_POLLED, &nvmeq->flags))
4b04cc6a 1166 flags |= NVME_CQ_IRQ_ENABLED;
b60503ba 1167
d29ec824 1168 /*
16772ae6 1169 * Note: we (ab)use the fact that the prp fields survive if no data
d29ec824
CH		 1170 * is attached to the request.
1171 */
b60503ba
MW		 1172 c.create_cq.opcode = nvme_admin_create_cq;
1173 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1174 c.create_cq.cqid = cpu_to_le16(qid);
1175 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1176 c.create_cq.cq_flags = cpu_to_le16(flags);
7c349dde 1177 c.create_cq.irq_vector = cpu_to_le16(vector);
b60503ba 1178
1c63dc66 1179 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1180}
1181
1182static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1183 struct nvme_queue *nvmeq)
1184{
9abd68ef 1185 struct nvme_ctrl *ctrl = &dev->ctrl;
f66e2804 1186 struct nvme_command c = { };
81c1cd98 1187 int flags = NVME_QUEUE_PHYS_CONTIG;
b60503ba 1188
9abd68ef
JA		 1189 /*
1190 * Some drives have a bug that auto-enables WRRU if MEDIUM isn't
1191 * set. Since URGENT priority is zeroes, it makes all queues
1192 * URGENT.
1193 */
1194 if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ)
1195 flags |= NVME_SQ_PRIO_MEDIUM;
1196
d29ec824 1197 /*
16772ae6 1198 * Note: we (ab)use the fact that the prp fields survive if no data
d29ec824
CH		 1199 * is attached to the request.
1200 */
b60503ba
MW		 1201 c.create_sq.opcode = nvme_admin_create_sq;
1202 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1203 c.create_sq.sqid = cpu_to_le16(qid);
1204 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1205 c.create_sq.sq_flags = cpu_to_le16(flags);
1206 c.create_sq.cqid = cpu_to_le16(qid);
1207
1c63dc66 1208 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1209}
1210
1211static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1212{
1213 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1214}
1215
1216static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1217{
1218 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1219}
1220
de671d61 1221static enum rq_end_io_ret abort_endio(struct request *req, blk_status_t error)
bc5fc7e4 1222{
a53232cb 1223 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
e44ac588 1224
27fa9bc5
CH		 1225 dev_warn(nvmeq->dev->ctrl.device,
1226 "Abort status: 0x%x", nvme_req(req)->status);
e7a2a87d 1227 atomic_inc(&nvmeq->dev->ctrl.abort_limit);
e7a2a87d 1228 blk_mq_free_request(req);
de671d61 1229 return RQ_END_IO_NONE;
bc5fc7e4
MW		 1230}
1231
b2a0eb1a
KB		 1232static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1233{
b2a0eb1a
KB		 1234 /* If true, indicates loss of adapter communication, possibly by a
1235 * NVMe Subsystem reset.
1236 */
1237 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1238
ad70062c
JW		 1239 /* If there is a reset/reinit ongoing, we shouldn't reset again. */
1240 switch (dev->ctrl.state) {
1241 case NVME_CTRL_RESETTING:
ad6a0a52 1242 case NVME_CTRL_CONNECTING:
b2a0eb1a 1243 return false;
ad70062c
JW		 1244 default:
1245 break;
1246 }
b2a0eb1a
KB		 1247
1248 /* We shouldn't reset unless the controller is on fatal error state
1249 * _or_ if we lost the communication with it.
1250 */
1251 if (!(csts & NVME_CSTS_CFS) && !nssro)
1252 return false;
1253
b2a0eb1a
KB		 1254 return true;
1255}
1256
1257static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1258{
1259 /* Read a config register to help see what died. */
1260 u16 pci_status;
1261 int result;
1262
1263 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1264 &pci_status);
1265 if (result == PCIBIOS_SUCCESSFUL)
1266 dev_warn(dev->ctrl.device,
1267 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1268 csts, pci_status);
1269 else
1270 dev_warn(dev->ctrl.device,
1271 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1272 csts, result);
4641a8e6
KB		 1273
1274 if (csts != ~0)
1275 return;
1276
1277 dev_warn(dev->ctrl.device,
1278 "Does your device have a faulty power saving mode enabled?\n");
1279 dev_warn(dev->ctrl.device,
1280 "Try \"nvme_core.default_ps_max_latency_us=0 pcie_aspm=off\" and report a bug\n");
b2a0eb1a
KB		 1281}
1282
9bdb4833 1283static enum blk_eh_timer_return nvme_timeout(struct request *req)
c30341dc 1284{
f4800d6d 1285 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a53232cb 1286 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
c30341dc 1287 struct nvme_dev *dev = nvmeq->dev;
a4aea562 1288 struct request *abort_req;
f66e2804 1289 struct nvme_command cmd = { };
b2a0eb1a
KB		 1290 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1291
651438bb
WX		 1292 /* If PCI error recovery process is happening, we cannot reset or
1293 * the recovery mechanism will surely fail.
1294 */
1295 mb();
1296 if (pci_channel_offline(to_pci_dev(dev->dev)))
1297 return BLK_EH_RESET_TIMER;
1298
b2a0eb1a
KB		 1299 /*
1300 * Reset immediately if the controller is failed
1301 */
1302 if (nvme_should_reset(dev, csts)) {
1303 nvme_warn_reset(dev, csts);
1304 nvme_dev_disable(dev, false);
d86c4d8e 1305 nvme_reset_ctrl(&dev->ctrl);
db8c48e4 1306 return BLK_EH_DONE;
b2a0eb1a 1307 }
c30341dc 1308
7776db1c
KB		 1309 /*
1310 * Did we miss an interrupt?
1311 */
fa059b85 1312 if (test_bit(NVMEQ_POLLED, &nvmeq->flags))
5a72e899 1313 nvme_poll(req->mq_hctx, NULL);
fa059b85
KB		 1314 else
1315 nvme_poll_irqdisable(nvmeq);
1316
1c584208 1317 if (blk_mq_rq_state(req) != MQ_RQ_IN_FLIGHT) {
7776db1c
KB		 1318 dev_warn(dev->ctrl.device,
1319 "I/O %d QID %d timeout, completion polled\n",
1320 req->tag, nvmeq->qid);
db8c48e4 1321 return BLK_EH_DONE;
7776db1c
KB		 1322 }
1323
31c7c7d2 1324 /*
fd634f41
CH		 1325 * Shutdown immediately if controller times out while starting. The
1326 * reset work will see the pci device disabled when it gets the forced
1327 * cancellation error. All outstanding requests are completed on
db8c48e4 1328 * shutdown, so we return BLK_EH_DONE.
fd634f41 1329 */
4244140d
KB		 1330 switch (dev->ctrl.state) {
1331 case NVME_CTRL_CONNECTING:
2036f726 1332 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
df561f66 1333 fallthrough;
2036f726 1334 case NVME_CTRL_DELETING:
b9cac43c 1335 dev_warn_ratelimited(dev->ctrl.device,
fd634f41
CH		 1336 "I/O %d QID %d timeout, disable controller\n",
1337 req->tag, nvmeq->qid);
27fa9bc5 1338 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
7ad92f65 1339 nvme_dev_disable(dev, true);
db8c48e4 1340 return BLK_EH_DONE;
39a9dd81
KB		 1341 case NVME_CTRL_RESETTING:
1342 return BLK_EH_RESET_TIMER;
4244140d
KB		 1343 default:
1344 break;
c30341dc
KB		 1345 }
1346
fd634f41 1347 /*
ee0d96d3
BW		 1348 * Shutdown the controller immediately and schedule a reset if the
1349 * command was already aborted once before and still hasn't been
1350 * returned to the driver, or if this is the admin queue.
31c7c7d2 1351 */
f4800d6d 1352 if (!nvmeq->qid || iod->aborted) {
1b3c47c1 1353 dev_warn(dev->ctrl.device,
e1569a16
KB		 1354 "I/O %d QID %d timeout, reset controller\n",
1355 req->tag, nvmeq->qid);
7ad92f65 1356 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
a5cdb68c 1357 nvme_dev_disable(dev, false);
d86c4d8e 1358 nvme_reset_ctrl(&dev->ctrl);
c30341dc 1359
db8c48e4 1360 return BLK_EH_DONE;
c30341dc 1361 }
c30341dc 1362
e7a2a87d 1363 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
6bf25d16 1364 atomic_inc(&dev->ctrl.abort_limit);
31c7c7d2 1365 return BLK_EH_RESET_TIMER;
6bf25d16 1366 }
52da4f3f 1367 iod->aborted = true;
a4aea562 1368
c30341dc 1369 cmd.abort.opcode = nvme_admin_abort_cmd;
85f74acf 1370 cmd.abort.cid = nvme_cid(req);
c30341dc 1371 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
c30341dc 1372
1b3c47c1 1373 dev_warn(nvmeq->dev->ctrl.device,
86141440
CH		 1374 "I/O %d (%s) QID %d timeout, aborting\n",
1375 req->tag,
1376 nvme_get_opcode_str(nvme_req(req)->cmd->common.opcode),
1377 nvmeq->qid);
e7a2a87d 1378
e559398f
CH		 1379 abort_req = blk_mq_alloc_request(dev->ctrl.admin_q, nvme_req_op(&cmd),
1380 BLK_MQ_REQ_NOWAIT);
e7a2a87d
CH		 1381 if (IS_ERR(abort_req)) {
1382 atomic_inc(&dev->ctrl.abort_limit);
1383 return BLK_EH_RESET_TIMER;
1384 }
e559398f 1385 nvme_init_request(abort_req, &cmd);
e7a2a87d 1386
e2e53086 1387 abort_req->end_io = abort_endio;
e7a2a87d 1388 abort_req->end_io_data = NULL;
e2e53086 1389 blk_execute_rq_nowait(abort_req, false);
c30341dc 1390
31c7c7d2
CH		 1391 /*
1392 * The aborted req will be completed on receiving the abort req.
1393 * We enable the timer again. If hit twice, it'll cause a device reset,
1394 * as the device then is in a faulty state.
1395 */
1396 return BLK_EH_RESET_TIMER;
c30341dc
KB		 1397}
1398
a4aea562
MB		 1399static void nvme_free_queue(struct nvme_queue *nvmeq)
1400{
8a1d09a6 1401 dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq),
9e866774 1402 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
63223078
CH		 1403 if (!nvmeq->sq_cmds)
1404 return;
0f238ff5 1405
63223078 1406 if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) {
88a041f4 1407 pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev),
8a1d09a6 1408 nvmeq->sq_cmds, SQ_SIZE(nvmeq));
63223078 1409 } else {
8a1d09a6 1410 dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq),
63223078 1411 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
0f238ff5 1412 }
9e866774
MW		 1413}
1414
a1a5ef99 1415static void nvme_free_queues(struct nvme_dev *dev, int lowest)
22404274
KB		 1416{
1417 int i;
1418
d858e5f0 1419 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
d858e5f0 1420 dev->ctrl.queue_count--;
147b27e4 1421 nvme_free_queue(&dev->queues[i]);
121c7ad4 1422 }
22404274
KB		 1423}
1424
10981f23 1425static void nvme_suspend_queue(struct nvme_dev *dev, unsigned int qid)
b60503ba 1426{
10981f23
CH		 1427 struct nvme_queue *nvmeq = &dev->queues[qid];
1428
4e224106 1429 if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags))
10981f23 1430 return;
a09115b2 1431
4e224106 1432 /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */
d1f06f4a 1433 mb();
a09115b2 1434
4e224106 1435 nvmeq->dev->online_queues--;
1c63dc66 1436 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
9f27bd70 1437 nvme_quiesce_admin_queue(&nvmeq->dev->ctrl);
7c349dde 1438 if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags))
10981f23 1439 pci_free_irq(to_pci_dev(dev->dev), nvmeq->cq_vector, nvmeq);
4d115420 1440}
b60503ba 1441
8fae268b
KB		 1442static void nvme_suspend_io_queues(struct nvme_dev *dev)
1443{
1444 int i;
1445
1446 for (i = dev->ctrl.queue_count - 1; i > 0; i--)
10981f23 1447 nvme_suspend_queue(dev, i);
b60503ba
MW		 1448}
1449
fa46c6fb
KB		 1450/*
1451 * Called only on a device that has been disabled and after all other threads
9210c075
DZ		 1452 * that can check this device's completion queues have synced, except
1453 * nvme_poll(). This is the last chance for the driver to see a natural
1454 * completion before nvme_cancel_request() terminates all incomplete requests.
fa46c6fb
KB		 1455 */
1456static void nvme_reap_pending_cqes(struct nvme_dev *dev)
1457{
fa46c6fb
KB		 1458 int i;
1459
9210c075
DZ		 1460 for (i = dev->ctrl.queue_count - 1; i > 0; i--) {
1461 spin_lock(&dev->queues[i].cq_poll_lock);
c234a653 1462 nvme_poll_cq(&dev->queues[i], NULL);
9210c075
DZ		 1463 spin_unlock(&dev->queues[i].cq_poll_lock);
1464 }
fa46c6fb
KB		 1465}
1466
8ffaadf7
JD		 1467static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1468 int entry_size)
1469{
1470 int q_depth = dev->q_depth;
5fd4ce1b 1471 unsigned q_size_aligned = roundup(q_depth * entry_size,
6c3c05b0 1472 NVME_CTRL_PAGE_SIZE);
8ffaadf7
JD		 1473
1474 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
c45f5c99 1475 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
4e523547 1476
6c3c05b0 1477 mem_per_q = round_down(mem_per_q, NVME_CTRL_PAGE_SIZE);
c45f5c99 1478 q_depth = div_u64(mem_per_q, entry_size);
8ffaadf7
JD		 1479
1480 /*
1481 * Ensure the reduced q_depth is above some threshold where it
1482 * would be better to map queues in system memory with the
1483 * original depth
1484 */
1485 if (q_depth < 64)
1486 return -ENOMEM;
1487 }
1488
1489 return q_depth;
1490}
1491
1492static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
8a1d09a6 1493 int qid)
8ffaadf7 1494{
0f238ff5
LG		 1495 struct pci_dev *pdev = to_pci_dev(dev->dev);
1496
1497 if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
8a1d09a6 1498 nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq));
bfac8e9f
AM		 1499 if (nvmeq->sq_cmds) {
1500 nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev,
1501 nvmeq->sq_cmds);
1502 if (nvmeq->sq_dma_addr) {
1503 set_bit(NVMEQ_SQ_CMB, &nvmeq->flags);
1504 return 0;
1505 }
1506
8a1d09a6 1507 pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq));
63223078 1508 }
0f238ff5 1509 }
8ffaadf7 1510
8a1d09a6 1511 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq),
63223078 1512 &nvmeq->sq_dma_addr, GFP_KERNEL);
815c6704
KB		 1513 if (!nvmeq->sq_cmds)
1514 return -ENOMEM;
8ffaadf7
JD		 1515 return 0;
1516}
1517
a6ff7262 1518static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
b60503ba 1519{
147b27e4 1520 struct nvme_queue *nvmeq = &dev->queues[qid];
b60503ba 1521
62314e40
KB		 1522 if (dev->ctrl.queue_count > qid)
1523 return 0;
b60503ba 1524
c1e0cc7e 1525 nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES;
8a1d09a6
BH		 1526 nvmeq->q_depth = depth;
1527 nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq),
750afb08 1528 &nvmeq->cq_dma_addr, GFP_KERNEL);
b60503ba
MW		 1529 if (!nvmeq->cqes)
1530 goto free_nvmeq;
b60503ba 1531
8a1d09a6 1532 if (nvme_alloc_sq_cmds(dev, nvmeq, qid))
b60503ba
MW		 1533 goto free_cqdma;
1534
091b6092 1535 nvmeq->dev = dev;
1ab0cd69 1536 spin_lock_init(&nvmeq->sq_lock);
3a7afd8e 1537 spin_lock_init(&nvmeq->cq_poll_lock);
b60503ba 1538 nvmeq->cq_head = 0;
82123460 1539 nvmeq->cq_phase = 1;
b80d5ccc 1540 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
c30341dc 1541 nvmeq->qid = qid;
d858e5f0 1542 dev->ctrl.queue_count++;
36a7e993 1543
147b27e4 1544 return 0;
b60503ba
MW		 1545
1546 free_cqdma:
8a1d09a6
BH		 1547 dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes,
1548 nvmeq->cq_dma_addr);
b60503ba 1549 free_nvmeq:
147b27e4 1550 return -ENOMEM;
b60503ba
MW		 1551}
1552
dca51e78 1553static int queue_request_irq(struct nvme_queue *nvmeq)
3001082c 1554{
0ff199cb
CH		 1555 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1556 int nr = nvmeq->dev->ctrl.instance;
1557
1558 if (use_threaded_interrupts) {
1559 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1560 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1561 } else {
1562 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1563 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1564 }
3001082c
MW		 1565}
1566
22404274 1567static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
b60503ba 1568{
22404274 1569 struct nvme_dev *dev = nvmeq->dev;
b60503ba 1570
22404274 1571 nvmeq->sq_tail = 0;
38210800 1572 nvmeq->last_sq_tail = 0;
22404274
KB		 1573 nvmeq->cq_head = 0;
1574 nvmeq->cq_phase = 1;
b80d5ccc 1575 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
8a1d09a6 1576 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq));
f9f38e33 1577 nvme_dbbuf_init(dev, nvmeq, qid);
42f61420 1578 dev->online_queues++;
3a7afd8e 1579 wmb(); /* ensure the first interrupt sees the initialization */
22404274
KB		 1580}
1581
e4b9852a
CC		 1582/*
1583 * Try getting shutdown_lock while setting up IO queues.
1584 */
1585static int nvme_setup_io_queues_trylock(struct nvme_dev *dev)
1586{
1587 /*
1588 * Give up if the lock is being held by nvme_dev_disable.
1589 */
1590 if (!mutex_trylock(&dev->shutdown_lock))
1591 return -ENODEV;
1592
1593 /*
1594 * Controller is in wrong state, fail early.
1595 */
1596 if (dev->ctrl.state != NVME_CTRL_CONNECTING) {
1597 mutex_unlock(&dev->shutdown_lock);
1598 return -ENODEV;
1599 }
1600
1601 return 0;
1602}
1603
4b04cc6a 1604static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled)
22404274
KB		 1605{
1606 struct nvme_dev *dev = nvmeq->dev;
1607 int result;
7c349dde 1608 u16 vector = 0;
3f85d50b 1609
d1ed6aa1
CH		 1610 clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
1611
22b55601
KB		 1612 /*
1613 * A queue's vector matches the queue identifier unless the controller
1614 * has only one vector available.
1615 */
4b04cc6a
JA		 1616 if (!polled)
1617 vector = dev->num_vecs == 1 ? 0 : qid;
1618 else
7c349dde 1619 set_bit(NVMEQ_POLLED, &nvmeq->flags);
4b04cc6a 1620
a8e3e0bb 1621 result = adapter_alloc_cq(dev, qid, nvmeq, vector);
ded45505
KB		 1622 if (result)
1623 return result;
b60503ba
MW		 1624
1625 result = adapter_alloc_sq(dev, qid, nvmeq);
1626 if (result < 0)
ded45505 1627 return result;
c80b36cd 1628 if (result)
b60503ba
MW		 1629 goto release_cq;
1630
a8e3e0bb 1631 nvmeq->cq_vector = vector;
4b04cc6a 1632
e4b9852a
CC		 1633 result = nvme_setup_io_queues_trylock(dev);
1634 if (result)
1635 return result;
1636 nvme_init_queue(nvmeq, qid);
7c349dde 1637 if (!polled) {
4b04cc6a
JA		 1638 result = queue_request_irq(nvmeq);
1639 if (result < 0)
1640 goto release_sq;
1641 }
b60503ba 1642
4e224106 1643 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
e4b9852a 1644 mutex_unlock(&dev->shutdown_lock);
22404274 1645 return result;
b60503ba 1646
a8e3e0bb 1647release_sq:
f25a2dfc 1648 dev->online_queues--;
e4b9852a 1649 mutex_unlock(&dev->shutdown_lock);
b60503ba 1650 adapter_delete_sq(dev, qid);
a8e3e0bb 1651release_cq:
b60503ba 1652 adapter_delete_cq(dev, qid);
22404274 1653 return result;
b60503ba
MW		 1654}
1655
f363b089 1656static const struct blk_mq_ops nvme_mq_admin_ops = {
d29ec824 1657 .queue_rq = nvme_queue_rq,
77f02a7a 1658 .complete = nvme_pci_complete_rq,
a4aea562 1659 .init_hctx = nvme_admin_init_hctx,
e559398f 1660 .init_request = nvme_pci_init_request,
a4aea562
MB		 1661 .timeout = nvme_timeout,
1662};
1663
f363b089 1664static const struct blk_mq_ops nvme_mq_ops = {
376f7ef8 1665 .queue_rq = nvme_queue_rq,
d62cbcf6 1666 .queue_rqs = nvme_queue_rqs,
376f7ef8
CH		 1667 .complete = nvme_pci_complete_rq,
1668 .commit_rqs = nvme_commit_rqs,
1669 .init_hctx = nvme_init_hctx,
e559398f 1670 .init_request = nvme_pci_init_request,
376f7ef8
CH		 1671 .map_queues = nvme_pci_map_queues,
1672 .timeout = nvme_timeout,
1673 .poll = nvme_poll,
dabcefab
JA		 1674};
1675
ea191d2f
KB		 1676static void nvme_dev_remove_admin(struct nvme_dev *dev)
1677{
1c63dc66 1678 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
69d9a99c
KB		 1679 /*
1680 * If the controller was reset during removal, it's possible
1681 * user requests may be waiting on a stopped queue. Start the
1682 * queue to flush these to completion.
1683 */
9f27bd70 1684 nvme_unquiesce_admin_queue(&dev->ctrl);
0da7feaa 1685 nvme_remove_admin_tag_set(&dev->ctrl);
ea191d2f
KB		 1686 }
1687}
1688
97f6ef64
XY		 1689static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1690{
1691 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1692}
1693
1694static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1695{
1696 struct pci_dev *pdev = to_pci_dev(dev->dev);
1697
1698 if (size <= dev->bar_mapped_size)
1699 return 0;
1700 if (size > pci_resource_len(pdev, 0))
1701 return -ENOMEM;
1702 if (dev->bar)
1703 iounmap(dev->bar);
1704 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1705 if (!dev->bar) {
1706 dev->bar_mapped_size = 0;
1707 return -ENOMEM;
1708 }
1709 dev->bar_mapped_size = size;
1710 dev->dbs = dev->bar + NVME_REG_DBS;
1711
1712 return 0;
1713}
1714
01ad0990 1715static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
b60503ba 1716{
ba47e386 1717 int result;
b60503ba
MW		 1718 u32 aqa;
1719 struct nvme_queue *nvmeq;
1720
97f6ef64
XY		 1721 result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1722 if (result < 0)
1723 return result;
1724
8ef2074d 1725 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
20d0dfe6 1726 NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
dfbac8c7 1727
7a67cbea
CH		 1728 if (dev->subsystem &&
1729 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1730 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
dfbac8c7 1731
285b6e9b
CH		 1732 /*
1733 * If the device has been passed off to us in an enabled state, just
1734 * clear the enabled bit. The spec says we should set the 'shutdown
1735 * notification bits', but doing so may cause the device to complete
1736 * commands to the admin queue ... and we don't know what memory that
1737 * might be pointing at!
1738 */
1739 result = nvme_disable_ctrl(&dev->ctrl, false);
ba47e386
MW		 1740 if (result < 0)
1741 return result;
b60503ba 1742
a6ff7262 1743 result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
147b27e4
SG		 1744 if (result)
1745 return result;
b60503ba 1746
635333e4
MG		 1747 dev->ctrl.numa_node = dev_to_node(dev->dev);
1748
147b27e4 1749 nvmeq = &dev->queues[0];
b60503ba
MW		 1750 aqa = nvmeq->q_depth - 1;
1751 aqa |= aqa << 16;
1752
7a67cbea
CH		 1753 writel(aqa, dev->bar + NVME_REG_AQA);
1754 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1755 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
b60503ba 1756
c0f2f45b 1757 result = nvme_enable_ctrl(&dev->ctrl);
025c557a 1758 if (result)
d4875622 1759 return result;
a4aea562 1760
2b25d981 1761 nvmeq->cq_vector = 0;
161b8be2 1762 nvme_init_queue(nvmeq, 0);
dca51e78 1763 result = queue_request_irq(nvmeq);
758dd7fd 1764 if (result) {
7c349dde 1765 dev->online_queues--;
d4875622 1766 return result;
758dd7fd 1767 }
025c557a 1768
4e224106 1769 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
b60503ba
MW		 1770 return result;
1771}
1772
749941f2 1773static int nvme_create_io_queues(struct nvme_dev *dev)
42f61420 1774{
4b04cc6a 1775 unsigned i, max, rw_queues;
749941f2 1776 int ret = 0;
42f61420 1777
d858e5f0 1778 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
a6ff7262 1779 if (nvme_alloc_queue(dev, i, dev->q_depth)) {
749941f2 1780 ret = -ENOMEM;
42f61420 1781 break;
749941f2
CH		 1782 }
1783 }
42f61420 1784
d858e5f0 1785 max = min(dev->max_qid, dev->ctrl.queue_count - 1);
e20ba6e1
CH		 1786 if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) {
1787 rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] +
1788 dev->io_queues[HCTX_TYPE_READ];
4b04cc6a
JA		 1789 } else {
1790 rw_queues = max;
1791 }
1792
949928c1 1793 for (i = dev->online_queues; i <= max; i++) {
4b04cc6a
JA		 1794 bool polled = i > rw_queues;
1795
1796 ret = nvme_create_queue(&dev->queues[i], i, polled);
d4875622 1797 if (ret)
42f61420 1798 break;
27e8166c 1799 }
749941f2
CH		 1800
1801 /*
1802 * Ignore failing Create SQ/CQ commands, we can continue with less
8adb8c14
MI		 1803 * than the desired amount of queues, and even a controller without
1804 * I/O queues can still be used to issue admin commands. This might
749941f2
CH		 1805 * be useful to upgrade a buggy firmware for example.
1806 */
1807 return ret >= 0 ? 0 : ret;
b60503ba
MW		 1808}
1809
88de4598 1810static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
8ffaadf7 1811{
88de4598
CH		 1812 u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
1813
1814 return 1ULL << (12 + 4 * szu);
1815}
1816
1817static u32 nvme_cmb_size(struct nvme_dev *dev)
1818{
1819 return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
1820}
1821
f65efd6d 1822static void nvme_map_cmb(struct nvme_dev *dev)
8ffaadf7 1823{
88de4598 1824 u64 size, offset;
8ffaadf7
JD		 1825 resource_size_t bar_size;
1826 struct pci_dev *pdev = to_pci_dev(dev->dev);
8969f1f8 1827 int bar;
8ffaadf7 1828
9fe5c59f
KB		 1829 if (dev->cmb_size)
1830 return;
1831
20d3bb92
KJ		 1832 if (NVME_CAP_CMBS(dev->ctrl.cap))
1833 writel(NVME_CMBMSC_CRE, dev->bar + NVME_REG_CMBMSC);
1834
7a67cbea 1835 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
f65efd6d
CH		 1836 if (!dev->cmbsz)
1837 return;
202021c1 1838 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
8ffaadf7 1839
88de4598
CH		 1840 size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
1841 offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
8969f1f8
CH		 1842 bar = NVME_CMB_BIR(dev->cmbloc);
1843 bar_size = pci_resource_len(pdev, bar);
8ffaadf7
JD		 1844
1845 if (offset > bar_size)
f65efd6d 1846 return;
8ffaadf7 1847
20d3bb92
KJ		 1848 /*
1849 * Tell the controller about the host side address mapping the CMB,
1850 * and enable CMB decoding for the NVMe 1.4+ scheme:
1851 */
1852 if (NVME_CAP_CMBS(dev->ctrl.cap)) {
1853 hi_lo_writeq(NVME_CMBMSC_CRE | NVME_CMBMSC_CMSE |
1854 (pci_bus_address(pdev, bar) + offset),
1855 dev->bar + NVME_REG_CMBMSC);
1856 }
1857
8ffaadf7
JD		 1858 /*
1859 * Controllers may support a CMB size larger than their BAR,
1860 * for example, due to being behind a bridge. Reduce the CMB to
1861 * the reported size of the BAR
1862 */
1863 if (size > bar_size - offset)
1864 size = bar_size - offset;
1865
0f238ff5
LG		 1866 if (pci_p2pdma_add_resource(pdev, bar, size, offset)) {
1867 dev_warn(dev->ctrl.device,
1868 "failed to register the CMB\n");
f65efd6d 1869 return;
0f238ff5
LG		 1870 }
1871
8ffaadf7 1872 dev->cmb_size = size;
0f238ff5
LG		 1873 dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS);
1874
1875 if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) ==
1876 (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS))
1877 pci_p2pmem_publish(pdev, true);
8ffaadf7
JD		 1878}
1879
87ad72a5
CH		 1880static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1881{
6c3c05b0 1882 u32 host_mem_size = dev->host_mem_size >> NVME_CTRL_PAGE_SHIFT;
4033f35d 1883 u64 dma_addr = dev->host_mem_descs_dma;
f66e2804 1884 struct nvme_command c = { };
87ad72a5
CH		 1885 int ret;
1886
87ad72a5
CH		 1887 c.features.opcode = nvme_admin_set_features;
1888 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1889 c.features.dword11 = cpu_to_le32(bits);
6c3c05b0 1890 c.features.dword12 = cpu_to_le32(host_mem_size);
87ad72a5
CH		 1891 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr));
1892 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr));
1893 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs);
1894
1895 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1896 if (ret) {
1897 dev_warn(dev->ctrl.device,
1898 "failed to set host mem (err %d, flags %#x).\n",
1899 ret, bits);
a5df5e79
KB		 1900 } else
1901 dev->hmb = bits & NVME_HOST_MEM_ENABLE;
1902
87ad72a5
CH		 1903 return ret;
1904}
1905
1906static void nvme_free_host_mem(struct nvme_dev *dev)
1907{
1908 int i;
1909
1910 for (i = 0; i < dev->nr_host_mem_descs; i++) {
1911 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
6c3c05b0 1912 size_t size = le32_to_cpu(desc->size) * NVME_CTRL_PAGE_SIZE;
87ad72a5 1913
cc667f6d
LD		 1914 dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i],
1915 le64_to_cpu(desc->addr),
1916 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
87ad72a5
CH		 1917 }
1918
1919 kfree(dev->host_mem_desc_bufs);
1920 dev->host_mem_desc_bufs = NULL;
4033f35d
CH		 1921 dma_free_coherent(dev->dev,
1922 dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
1923 dev->host_mem_descs, dev->host_mem_descs_dma);
87ad72a5 1924 dev->host_mem_descs = NULL;
7e5dd57e 1925 dev->nr_host_mem_descs = 0;
87ad72a5
CH		 1926}
1927
92dc6895
CH		 1928static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
1929 u32 chunk_size)
9d713c2b 1930{
87ad72a5 1931 struct nvme_host_mem_buf_desc *descs;
92dc6895 1932 u32 max_entries, len;
4033f35d 1933 dma_addr_t descs_dma;
2ee0e4ed 1934 int i = 0;
87ad72a5 1935 void **bufs;
6fbcde66 1936 u64 size, tmp;
87ad72a5 1937
87ad72a5
CH		 1938 tmp = (preferred + chunk_size - 1);
1939 do_div(tmp, chunk_size);
1940 max_entries = tmp;
044a9df1
CH		 1941
1942 if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
1943 max_entries = dev->ctrl.hmmaxd;
1944
750afb08
LC		 1945 descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs),
1946 &descs_dma, GFP_KERNEL);
87ad72a5
CH		 1947 if (!descs)
1948 goto out;
1949
1950 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
1951 if (!bufs)
1952 goto out_free_descs;
1953
244a8fe4 1954 for (size = 0; size < preferred && i < max_entries; size += len) {
87ad72a5
CH		 1955 dma_addr_t dma_addr;
1956
50cdb7c6 1957 len = min_t(u64, chunk_size, preferred - size);
87ad72a5
CH		 1958 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
1959 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1960 if (!bufs[i])
1961 break;
1962
1963 descs[i].addr = cpu_to_le64(dma_addr);
6c3c05b0 1964 descs[i].size = cpu_to_le32(len / NVME_CTRL_PAGE_SIZE);
87ad72a5
CH		 1965 i++;
1966 }
1967
92dc6895 1968 if (!size)
87ad72a5 1969 goto out_free_bufs;
87ad72a5 1970
87ad72a5
CH		 1971 dev->nr_host_mem_descs = i;
1972 dev->host_mem_size = size;
1973 dev->host_mem_descs = descs;
4033f35d 1974 dev->host_mem_descs_dma = descs_dma;
87ad72a5
CH		 1975 dev->host_mem_desc_bufs = bufs;
1976 return 0;
1977
1978out_free_bufs:
1979 while (--i >= 0) {
6c3c05b0 1980 size_t size = le32_to_cpu(descs[i].size) * NVME_CTRL_PAGE_SIZE;
87ad72a5 1981
cc667f6d
LD		 1982 dma_free_attrs(dev->dev, size, bufs[i],
1983 le64_to_cpu(descs[i].addr),
1984 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
87ad72a5
CH		 1985 }
1986
1987 kfree(bufs);
1988out_free_descs:
4033f35d
CH		 1989 dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
1990 descs_dma);
87ad72a5 1991out:
87ad72a5
CH		 1992 dev->host_mem_descs = NULL;
1993 return -ENOMEM;
1994}
1995
92dc6895
CH		 1996static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
1997{
9dc54a0d
CK		 1998 u64 min_chunk = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
1999 u64 hmminds = max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
2000 u64 chunk_size;
92dc6895
CH		 2001
2002 /* start big and work our way down */
9dc54a0d 2003 for (chunk_size = min_chunk; chunk_size >= hmminds; chunk_size /= 2) {
92dc6895
CH		 2004 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
2005 if (!min || dev->host_mem_size >= min)
2006 return 0;
2007 nvme_free_host_mem(dev);
2008 }
2009 }
2010
2011 return -ENOMEM;
2012}
2013
9620cfba 2014static int nvme_setup_host_mem(struct nvme_dev *dev)
87ad72a5
CH		 2015{
2016 u64 max = (u64)max_host_mem_size_mb * SZ_1M;
2017 u64 preferred = (u64)dev->ctrl.hmpre * 4096;
2018 u64 min = (u64)dev->ctrl.hmmin * 4096;
2019 u32 enable_bits = NVME_HOST_MEM_ENABLE;
6fbcde66 2020 int ret;
87ad72a5 2021
acb71e53
CH		 2022 if (!dev->ctrl.hmpre)
2023 return 0;
2024
87ad72a5
CH		 2025 preferred = min(preferred, max);
2026 if (min > max) {
2027 dev_warn(dev->ctrl.device,
2028 "min host memory (%lld MiB) above limit (%d MiB).\n",
2029 min >> ilog2(SZ_1M), max_host_mem_size_mb);
2030 nvme_free_host_mem(dev);
9620cfba 2031 return 0;
87ad72a5
CH		 2032 }
2033
2034 /*
2035 * If we already have a buffer allocated check if we can reuse it.
2036 */
2037 if (dev->host_mem_descs) {
2038 if (dev->host_mem_size >= min)
2039 enable_bits |= NVME_HOST_MEM_RETURN;
2040 else
2041 nvme_free_host_mem(dev);
2042 }
2043
2044 if (!dev->host_mem_descs) {
92dc6895
CH		 2045 if (nvme_alloc_host_mem(dev, min, preferred)) {
2046 dev_warn(dev->ctrl.device,
2047 "failed to allocate host memory buffer.\n");
9620cfba 2048 return 0; /* controller must work without HMB */
92dc6895
CH		 2049 }
2050
2051 dev_info(dev->ctrl.device,
2052 "allocated %lld MiB host memory buffer.\n",
2053 dev->host_mem_size >> ilog2(SZ_1M));
87ad72a5
CH		 2054 }
2055
9620cfba
CH		 2056 ret = nvme_set_host_mem(dev, enable_bits);
2057 if (ret)
87ad72a5 2058 nvme_free_host_mem(dev);
9620cfba 2059 return ret;
9d713c2b
KB		 2060}
2061
0521905e
KB		 2062static ssize_t cmb_show(struct device *dev, struct device_attribute *attr,
2063 char *buf)
2064{
2065 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2066
2067 return sysfs_emit(buf, "cmbloc : x%08x\ncmbsz : x%08x\n",
2068 ndev->cmbloc, ndev->cmbsz);
2069}
2070static DEVICE_ATTR_RO(cmb);
2071
1751e97a
KB		 2072static ssize_t cmbloc_show(struct device *dev, struct device_attribute *attr,
2073 char *buf)
2074{
2075 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2076
2077 return sysfs_emit(buf, "%u\n", ndev->cmbloc);
2078}
2079static DEVICE_ATTR_RO(cmbloc);
2080
2081static ssize_t cmbsz_show(struct device *dev, struct device_attribute *attr,
2082 char *buf)
2083{
2084 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2085
2086 return sysfs_emit(buf, "%u\n", ndev->cmbsz);
2087}
2088static DEVICE_ATTR_RO(cmbsz);
2089
a5df5e79
KB		 2090static ssize_t hmb_show(struct device *dev, struct device_attribute *attr,
2091 char *buf)
2092{
2093 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2094
2095 return sysfs_emit(buf, "%d\n", ndev->hmb);
2096}
2097
2098static ssize_t hmb_store(struct device *dev, struct device_attribute *attr,
2099 const char *buf, size_t count)
2100{
2101 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2102 bool new;
2103 int ret;
2104
99722c8a 2105 if (kstrtobool(buf, &new) < 0)
a5df5e79
KB		 2106 return -EINVAL;
2107
2108 if (new == ndev->hmb)
2109 return count;
2110
2111 if (new) {
2112 ret = nvme_setup_host_mem(ndev);
2113 } else {
2114 ret = nvme_set_host_mem(ndev, 0);
2115 if (!ret)
2116 nvme_free_host_mem(ndev);
2117 }
2118
2119 if (ret < 0)
2120 return ret;
2121
2122 return count;
2123}
2124static DEVICE_ATTR_RW(hmb);
2125
0521905e
KB		 2126static umode_t nvme_pci_attrs_are_visible(struct kobject *kobj,
2127 struct attribute *a, int n)
2128{
2129 struct nvme_ctrl *ctrl =
2130 dev_get_drvdata(container_of(kobj, struct device, kobj));
2131 struct nvme_dev *dev = to_nvme_dev(ctrl);
2132
1751e97a
KB		 2133 if (a == &dev_attr_cmb.attr ||
2134 a == &dev_attr_cmbloc.attr ||
2135 a == &dev_attr_cmbsz.attr) {
2136 if (!dev->cmbsz)
2137 return 0;
2138 }
a5df5e79
KB		 2139 if (a == &dev_attr_hmb.attr && !ctrl->hmpre)
2140 return 0;
2141
0521905e
KB		 2142 return a->mode;
2143}
2144
2145static struct attribute *nvme_pci_attrs[] = {
2146 &dev_attr_cmb.attr,
1751e97a
KB		 2147 &dev_attr_cmbloc.attr,
2148 &dev_attr_cmbsz.attr,
a5df5e79 2149 &dev_attr_hmb.attr,
0521905e
KB		 2150 NULL,
2151};
2152
86adbf0c 2153static const struct attribute_group nvme_pci_dev_attrs_group = {
0521905e
KB		 2154 .attrs = nvme_pci_attrs,
2155 .is_visible = nvme_pci_attrs_are_visible,
2156};
2157
86adbf0c
CH		 2158static const struct attribute_group *nvme_pci_dev_attr_groups[] = {
2159 &nvme_dev_attrs_group,
2160 &nvme_pci_dev_attrs_group,
2161 NULL,
2162};
2163
612b7286
ML		 2164/*
2165 * nirqs is the number of interrupts available for write and read
2166 * queues. The core already reserved an interrupt for the admin queue.
2167 */
2168static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs)
3b6592f7 2169{
612b7286 2170 struct nvme_dev *dev = affd->priv;
2a5bcfdd 2171 unsigned int nr_read_queues, nr_write_queues = dev->nr_write_queues;
3b6592f7
JA		 2172
2173 /*
ee0d96d3 2174 * If there is no interrupt available for queues, ensure that
612b7286
ML		 2175 * the default queue is set to 1. The affinity set size is
2176 * also set to one, but the irq core ignores it for this case.
2177 *
2178 * If only one interrupt is available or 'write_queue' == 0, combine
2179 * write and read queues.
2180 *
2181 * If 'write_queues' > 0, ensure it leaves room for at least one read
2182 * queue.
3b6592f7 2183 */
612b7286
ML		 2184 if (!nrirqs) {
2185 nrirqs = 1;
2186 nr_read_queues = 0;
2a5bcfdd 2187 } else if (nrirqs == 1 || !nr_write_queues) {
612b7286 2188 nr_read_queues = 0;
2a5bcfdd 2189 } else if (nr_write_queues >= nrirqs) {
612b7286 2190 nr_read_queues = 1;
3b6592f7 2191 } else {
2a5bcfdd 2192 nr_read_queues = nrirqs - nr_write_queues;
3b6592f7 2193 }
612b7286
ML		 2194
2195 dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2196 affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2197 dev->io_queues[HCTX_TYPE_READ] = nr_read_queues;
2198 affd->set_size[HCTX_TYPE_READ] = nr_read_queues;
2199 affd->nr_sets = nr_read_queues ? 2 : 1;
3b6592f7
JA		 2200}
2201
6451fe73 2202static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues)
3b6592f7
JA		 2203{
2204 struct pci_dev *pdev = to_pci_dev(dev->dev);
3b6592f7 2205 struct irq_affinity affd = {
9cfef55b 2206 .pre_vectors = 1,
612b7286
ML		 2207 .calc_sets = nvme_calc_irq_sets,
2208 .priv = dev,
3b6592f7 2209 };
21cc2f3f 2210 unsigned int irq_queues, poll_queues;
6451fe73
JA		 2211
2212 /*
21cc2f3f
JX		 2213 * Poll queues don't need interrupts, but we need at least one I/O queue
2214 * left over for non-polled I/O.
6451fe73 2215 */
21cc2f3f
JX		 2216 poll_queues = min(dev->nr_poll_queues, nr_io_queues - 1);
2217 dev->io_queues[HCTX_TYPE_POLL] = poll_queues;
3b6592f7 2218
21cc2f3f
JX		 2219 /*
2220 * Initialize for the single interrupt case, will be updated in
2221 * nvme_calc_irq_sets().
2222 */
612b7286
ML		 2223 dev->io_queues[HCTX_TYPE_DEFAULT] = 1;
2224 dev->io_queues[HCTX_TYPE_READ] = 0;
3b6592f7 2225
66341331 2226 /*
21cc2f3f
JX		 2227 * We need interrupts for the admin queue and each non-polled I/O queue,
2228 * but some Apple controllers require all queues to use the first
2229 * vector.
66341331 2230 */
21cc2f3f
JX		 2231 irq_queues = 1;
2232 if (!(dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR))
2233 irq_queues += (nr_io_queues - poll_queues);
612b7286
ML		 2234 return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues,
2235 PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd);
3b6592f7
JA		 2236}
2237
2a5bcfdd
WZ		 2238static unsigned int nvme_max_io_queues(struct nvme_dev *dev)
2239{
e3aef095
NS		 2240 /*
2241 * If tags are shared with admin queue (Apple bug), then
2242 * make sure we only use one IO queue.
2243 */
2244 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2245 return 1;
2a5bcfdd
WZ		 2246 return num_possible_cpus() + dev->nr_write_queues + dev->nr_poll_queues;
2247}
2248
8d85fce7 2249static int nvme_setup_io_queues(struct nvme_dev *dev)
b60503ba 2250{
147b27e4 2251 struct nvme_queue *adminq = &dev->queues[0];
e75ec752 2252 struct pci_dev *pdev = to_pci_dev(dev->dev);
2a5bcfdd 2253 unsigned int nr_io_queues;
97f6ef64 2254 unsigned long size;
2a5bcfdd 2255 int result;
b60503ba 2256
2a5bcfdd
WZ		 2257 /*
2258 * Sample the module parameters once at reset time so that we have
2259 * stable values to work with.
2260 */
2261 dev->nr_write_queues = write_queues;
2262 dev->nr_poll_queues = poll_queues;
d38e9f04 2263
e3aef095 2264 nr_io_queues = dev->nr_allocated_queues - 1;
9a0be7ab
CH		 2265 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
2266 if (result < 0)
1b23484b 2267 return result;
9a0be7ab 2268
f5fa90dc 2269 if (nr_io_queues == 0)
a5229050 2270 return 0;
53dc180e 2271
e4b9852a
CC		 2272 /*
2273 * Free IRQ resources as soon as NVMEQ_ENABLED bit transitions
2274 * from set to unset. If there is a window to it is truely freed,
2275 * pci_free_irq_vectors() jumping into this window will crash.
2276 * And take lock to avoid racing with pci_free_irq_vectors() in
2277 * nvme_dev_disable() path.
2278 */
2279 result = nvme_setup_io_queues_trylock(dev);
2280 if (result)
2281 return result;
2282 if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags))
2283 pci_free_irq(pdev, 0, adminq);
b60503ba 2284
0f238ff5 2285 if (dev->cmb_use_sqes) {
8ffaadf7
JD		 2286 result = nvme_cmb_qdepth(dev, nr_io_queues,
2287 sizeof(struct nvme_command));
88d356ca 2288 if (result > 0) {
8ffaadf7 2289 dev->q_depth = result;
88d356ca
CH		 2290 dev->ctrl.sqsize = result - 1;
2291 } else {
0f238ff5 2292 dev->cmb_use_sqes = false;
88d356ca 2293 }
8ffaadf7
JD		 2294 }
2295
97f6ef64
XY		 2296 do {
2297 size = db_bar_size(dev, nr_io_queues);
2298 result = nvme_remap_bar(dev, size);
2299 if (!result)
2300 break;
e4b9852a
CC		 2301 if (!--nr_io_queues) {
2302 result = -ENOMEM;
2303 goto out_unlock;
2304 }
97f6ef64
XY		 2305 } while (1);
2306 adminq->q_db = dev->dbs;
f1938f6e 2307
8fae268b 2308 retry:
9d713c2b 2309 /* Deregister the admin queue's interrupt */
e4b9852a
CC		 2310 if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags))
2311 pci_free_irq(pdev, 0, adminq);
9d713c2b 2312
e32efbfc
JA		 2313 /*
2314 * If we enable msix early due to not intx, disable it again before
2315 * setting up the full range we need.
2316 */
dca51e78 2317 pci_free_irq_vectors(pdev);
3b6592f7
JA		 2318
2319 result = nvme_setup_irqs(dev, nr_io_queues);
e4b9852a
CC		 2320 if (result <= 0) {
2321 result = -EIO;
2322 goto out_unlock;
2323 }
3b6592f7 2324
22b55601 2325 dev->num_vecs = result;
4b04cc6a 2326 result = max(result - 1, 1);
e20ba6e1 2327 dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL];
fa08a396 2328
063a8096
MW		 2329 /*
2330 * Should investigate if there's a performance win from allocating
2331 * more queues than interrupt vectors; it might allow the submission
2332 * path to scale better, even if the receive path is limited by the
2333 * number of interrupts.
2334 */
dca51e78 2335 result = queue_request_irq(adminq);
7c349dde 2336 if (result)
e4b9852a 2337 goto out_unlock;
4e224106 2338 set_bit(NVMEQ_ENABLED, &adminq->flags);
e4b9852a 2339 mutex_unlock(&dev->shutdown_lock);
8fae268b
KB		 2340
2341 result = nvme_create_io_queues(dev);
2342 if (result || dev->online_queues < 2)
2343 return result;
2344
2345 if (dev->online_queues - 1 < dev->max_qid) {
2346 nr_io_queues = dev->online_queues - 1;
7d879c90 2347 nvme_delete_io_queues(dev);
e4b9852a
CC		 2348 result = nvme_setup_io_queues_trylock(dev);
2349 if (result)
2350 return result;
8fae268b
KB		 2351 nvme_suspend_io_queues(dev);
2352 goto retry;
2353 }
2354 dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n",
2355 dev->io_queues[HCTX_TYPE_DEFAULT],
2356 dev->io_queues[HCTX_TYPE_READ],
2357 dev->io_queues[HCTX_TYPE_POLL]);
2358 return 0;
e4b9852a
CC		 2359out_unlock:
2360 mutex_unlock(&dev->shutdown_lock);
2361 return result;
b60503ba
MW		 2362}
2363
de671d61
JA		 2364static enum rq_end_io_ret nvme_del_queue_end(struct request *req,
2365 blk_status_t error)
a5768aa8 2366{
db3cbfff 2367 struct nvme_queue *nvmeq = req->end_io_data;
b5875222 2368
db3cbfff 2369 blk_mq_free_request(req);
d1ed6aa1 2370 complete(&nvmeq->delete_done);
de671d61 2371 return RQ_END_IO_NONE;
a5768aa8
KB		 2372}
2373
de671d61
JA		 2374static enum rq_end_io_ret nvme_del_cq_end(struct request *req,
2375 blk_status_t error)
a5768aa8 2376{
db3cbfff 2377 struct nvme_queue *nvmeq = req->end_io_data;
a5768aa8 2378
d1ed6aa1
CH		 2379 if (error)
2380 set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
db3cbfff 2381
de671d61 2382 return nvme_del_queue_end(req, error);
a5768aa8
KB		 2383}
2384
db3cbfff 2385static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
bda4e0fb 2386{
db3cbfff
KB		 2387 struct request_queue *q = nvmeq->dev->ctrl.admin_q;
2388 struct request *req;
f66e2804 2389 struct nvme_command cmd = { };
bda4e0fb 2390
db3cbfff
KB		 2391 cmd.delete_queue.opcode = opcode;
2392 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
bda4e0fb 2393
e559398f 2394 req = blk_mq_alloc_request(q, nvme_req_op(&cmd), BLK_MQ_REQ_NOWAIT);
db3cbfff
KB		 2395 if (IS_ERR(req))
2396 return PTR_ERR(req);
e559398f 2397 nvme_init_request(req, &cmd);
bda4e0fb 2398
e2e53086
CH		 2399 if (opcode == nvme_admin_delete_cq)
2400 req->end_io = nvme_del_cq_end;
2401 else
2402 req->end_io = nvme_del_queue_end;
db3cbfff
KB		 2403 req->end_io_data = nvmeq;
2404
d1ed6aa1 2405 init_completion(&nvmeq->delete_done);
e2e53086 2406 blk_execute_rq_nowait(req, false);
db3cbfff 2407 return 0;
bda4e0fb
KB		 2408}
2409
7d879c90 2410static bool __nvme_delete_io_queues(struct nvme_dev *dev, u8 opcode)
a5768aa8 2411{
5271edd4 2412 int nr_queues = dev->online_queues - 1, sent = 0;
db3cbfff 2413 unsigned long timeout;
a5768aa8 2414
db3cbfff 2415 retry:
dc96f938 2416 timeout = NVME_ADMIN_TIMEOUT;
5271edd4
CH		 2417 while (nr_queues > 0) {
2418 if (nvme_delete_queue(&dev->queues[nr_queues], opcode))
2419 break;
2420 nr_queues--;
2421 sent++;
db3cbfff 2422 }
d1ed6aa1
CH		 2423 while (sent) {
2424 struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent];
2425
2426 timeout = wait_for_completion_io_timeout(&nvmeq->delete_done,
5271edd4
CH		 2427 timeout);
2428 if (timeout == 0)
2429 return false;
d1ed6aa1 2430
d1ed6aa1 2431 sent--;
5271edd4
CH		 2432 if (nr_queues)
2433 goto retry;
2434 }
2435 return true;
a5768aa8
KB		 2436}
2437
7d879c90 2438static void nvme_delete_io_queues(struct nvme_dev *dev)
b60503ba 2439{
7d879c90
CH		 2440 if (__nvme_delete_io_queues(dev, nvme_admin_delete_sq))
2441 __nvme_delete_io_queues(dev, nvme_admin_delete_cq);
2442}
2b1b7e78 2443
0da7feaa 2444static unsigned int nvme_pci_nr_maps(struct nvme_dev *dev)
b60503ba 2445{
2455a4b7 2446 if (dev->io_queues[HCTX_TYPE_POLL])
0da7feaa
CH		 2447 return 3;
2448 if (dev->io_queues[HCTX_TYPE_READ])
2449 return 2;
2450 return 1;
2455a4b7 2451}
949928c1 2452
2455a4b7
CH		 2453static void nvme_pci_update_nr_queues(struct nvme_dev *dev)
2454{
2455 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2456 /* free previously allocated queues that are no longer usable */
2457 nvme_free_queues(dev, dev->online_queues);
b60503ba
MW		 2458}
2459
b00a726a 2460static int nvme_pci_enable(struct nvme_dev *dev)
0877cb0d 2461{
b00a726a 2462 int result = -ENOMEM;
e75ec752 2463 struct pci_dev *pdev = to_pci_dev(dev->dev);
4bdf2603 2464 int dma_address_bits = 64;
0877cb0d
KB		 2465
2466 if (pci_enable_device_mem(pdev))
2467 return result;
2468
0877cb0d 2469 pci_set_master(pdev);
0877cb0d 2470
4bdf2603
FS		 2471 if (dev->ctrl.quirks & NVME_QUIRK_DMA_ADDRESS_BITS_48)
2472 dma_address_bits = 48;
2473 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(dma_address_bits)))
052d0efa 2474 goto disable;
0877cb0d 2475
7a67cbea 2476 if (readl(dev->bar + NVME_REG_CSTS) == -1) {
0e53d180 2477 result = -ENODEV;
b00a726a 2478 goto disable;
0e53d180 2479 }
e32efbfc
JA		 2480
2481 /*
a5229050
KB		 2482 * Some devices and/or platforms don't advertise or work with INTx
2483 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2484 * adjust this later.
e32efbfc 2485 */
dca51e78
CH		 2486 result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
2487 if (result < 0)
09113abf 2488 goto disable;
e32efbfc 2489
20d0dfe6 2490 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
7a67cbea 2491
7442ddce 2492 dev->q_depth = min_t(u32, NVME_CAP_MQES(dev->ctrl.cap) + 1,
b27c1e68 2493 io_queue_depth);
20d0dfe6 2494 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
7a67cbea 2495 dev->dbs = dev->bar + 4096;
1f390c1f 2496
66341331
BH		 2497 /*
2498 * Some Apple controllers require a non-standard SQE size.
2499 * Interestingly they also seem to ignore the CC:IOSQES register
2500 * so we don't bother updating it here.
2501 */
2502 if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES)
2503 dev->io_sqes = 7;
2504 else
2505 dev->io_sqes = NVME_NVM_IOSQES;
1f390c1f
SG		 2506
2507 /*
2508 * Temporary fix for the Apple controller found in the MacBook8,1 and
2509 * some MacBook7,1 to avoid controller resets and data loss.
2510 */
2511 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
2512 dev->q_depth = 2;
9bdcfb10
CH		 2513 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
2514 "set queue depth=%u to work around controller resets\n",
1f390c1f 2515 dev->q_depth);
d554b5e1
MP		 2516 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2517 (pdev->device == 0xa821 || pdev->device == 0xa822) &&
20d0dfe6 2518 NVME_CAP_MQES(dev->ctrl.cap) == 0) {
d554b5e1
MP		 2519 dev->q_depth = 64;
2520 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2521 "set queue depth=%u\n", dev->q_depth);
1f390c1f
SG		 2522 }
2523
d38e9f04
BH		 2524 /*
2525 * Controllers with the shared tags quirk need the IO queue to be
2526 * big enough so that we get 32 tags for the admin queue
2527 */
2528 if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) &&
2529 (dev->q_depth < (NVME_AQ_DEPTH + 2))) {
2530 dev->q_depth = NVME_AQ_DEPTH + 2;
2531 dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n",
2532 dev->q_depth);
2533 }
88d356ca 2534 dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */
d38e9f04 2535
f65efd6d 2536 nvme_map_cmb(dev);
202021c1 2537
a0a3408e
KB		 2538 pci_enable_pcie_error_reporting(pdev);
2539 pci_save_state(pdev);
a6ee7f19 2540
09113abf
TZ		 2541 result = nvme_pci_configure_admin_queue(dev);
2542 if (result)
2543 goto free_irq;
2544 return result;
0877cb0d 2545
09113abf
TZ		 2546 free_irq:
2547 pci_free_irq_vectors(pdev);
0877cb0d 2548 disable:
0877cb0d
KB		 2549 pci_disable_device(pdev);
2550 return result;
2551}
2552
2553static void nvme_dev_unmap(struct nvme_dev *dev)
b00a726a
KB		 2554{
2555 if (dev->bar)
2556 iounmap(dev->bar);
a1f447b3 2557 pci_release_mem_regions(to_pci_dev(dev->dev));
b00a726a
KB		 2558}
2559
68e81eba 2560static bool nvme_pci_ctrl_is_dead(struct nvme_dev *dev)
0877cb0d 2561{
e75ec752 2562 struct pci_dev *pdev = to_pci_dev(dev->dev);
68e81eba 2563 u32 csts;
e75ec752 2564
68e81eba
CH		 2565 if (!pci_is_enabled(pdev) || !pci_device_is_present(pdev))
2566 return true;
2567 if (pdev->error_state != pci_channel_io_normal)
2568 return true;
0877cb0d 2569
68e81eba
CH		 2570 csts = readl(dev->bar + NVME_REG_CSTS);
2571 return (csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY);
4d115420
KB		 2572}
2573
a5cdb68c 2574static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
b60503ba 2575{
302ad8cc 2576 struct pci_dev *pdev = to_pci_dev(dev->dev);
68e81eba 2577 bool dead;
22404274 2578
77bf25ea 2579 mutex_lock(&dev->shutdown_lock);
68e81eba
CH		 2580 dead = nvme_pci_ctrl_is_dead(dev);
2581 if (dev->ctrl.state == NVME_CTRL_LIVE ||
2582 dev->ctrl.state == NVME_CTRL_RESETTING) {
2583 if (pci_is_enabled(pdev))
302ad8cc 2584 nvme_start_freeze(&dev->ctrl);
68e81eba
CH		 2585 /*
2586 * Give the controller a chance to complete all entered requests
2587 * if doing a safe shutdown.
2588 */
2589 if (!dead && shutdown)
2590 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
c9d3bf88 2591 }
c21377f8 2592
9f27bd70 2593 nvme_quiesce_io_queues(&dev->ctrl);
87ad72a5 2594
64ee0ac0 2595 if (!dead && dev->ctrl.queue_count > 0) {
7d879c90 2596 nvme_delete_io_queues(dev);
47d42d22
CH		 2597 nvme_disable_ctrl(&dev->ctrl, shutdown);
2598 nvme_poll_irqdisable(&dev->queues[0]);
4d115420 2599 }
8fae268b 2600 nvme_suspend_io_queues(dev);
10981f23 2601 nvme_suspend_queue(dev, 0);
c80767f7
CH		 2602 pci_free_irq_vectors(pdev);
2603 if (pci_is_enabled(pdev)) {
2604 pci_disable_pcie_error_reporting(pdev);
2605 pci_disable_device(pdev);
2606 }
fa46c6fb 2607 nvme_reap_pending_cqes(dev);
07836e65 2608
1fcfca78
GL		 2609 nvme_cancel_tagset(&dev->ctrl);
2610 nvme_cancel_admin_tagset(&dev->ctrl);
302ad8cc
KB		 2611
2612 /*
2613 * The driver will not be starting up queues again if shutting down so
2614 * must flush all entered requests to their failed completion to avoid
2615 * deadlocking blk-mq hot-cpu notifier.
2616 */
c8e9e9b7 2617 if (shutdown) {
9f27bd70 2618 nvme_unquiesce_io_queues(&dev->ctrl);
c8e9e9b7 2619 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q))
9f27bd70 2620 nvme_unquiesce_admin_queue(&dev->ctrl);
c8e9e9b7 2621 }
77bf25ea 2622 mutex_unlock(&dev->shutdown_lock);
b60503ba
MW		 2623}
2624
c1ac9a4b
KB		 2625static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown)
2626{
2627 if (!nvme_wait_reset(&dev->ctrl))
2628 return -EBUSY;
2629 nvme_dev_disable(dev, shutdown);
2630 return 0;
2631}
2632
091b6092
MW		 2633static int nvme_setup_prp_pools(struct nvme_dev *dev)
2634{
e75ec752 2635 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
c61b82c7
CH		 2636 NVME_CTRL_PAGE_SIZE,
2637 NVME_CTRL_PAGE_SIZE, 0);
091b6092
MW		 2638 if (!dev->prp_page_pool)
2639 return -ENOMEM;
2640
99802a7a 2641 /* Optimisation for I/Os between 4k and 128k */
e75ec752 2642 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
99802a7a
MW		 2643 256, 256, 0);
2644 if (!dev->prp_small_pool) {
2645 dma_pool_destroy(dev->prp_page_pool);
2646 return -ENOMEM;
2647 }
091b6092
MW		 2648 return 0;
2649}
2650
2651static void nvme_release_prp_pools(struct nvme_dev *dev)
2652{
2653 dma_pool_destroy(dev->prp_page_pool);
99802a7a 2654 dma_pool_destroy(dev->prp_small_pool);
091b6092
MW		 2655}
2656
081a7d95
CH		 2657static int nvme_pci_alloc_iod_mempool(struct nvme_dev *dev)
2658{
7846c1b5 2659 size_t alloc_size = sizeof(struct scatterlist) * NVME_MAX_SEGS;
081a7d95 2660
081a7d95
CH		 2661 dev->iod_mempool = mempool_create_node(1,
2662 mempool_kmalloc, mempool_kfree,
2663 (void *)alloc_size, GFP_KERNEL,
2664 dev_to_node(dev->dev));
2665 if (!dev->iod_mempool)
2666 return -ENOMEM;
2667 return 0;
2668}
2669
770597ec
KB		 2670static void nvme_free_tagset(struct nvme_dev *dev)
2671{
2672 if (dev->tagset.tags)
0da7feaa 2673 nvme_remove_io_tag_set(&dev->ctrl);
770597ec
KB		 2674 dev->ctrl.tagset = NULL;
2675}
2676
2e87570b 2677/* pairs with nvme_pci_alloc_dev */
1673f1f0 2678static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
5e82e952 2679{
1673f1f0 2680 struct nvme_dev *dev = to_nvme_dev(ctrl);
9ac27090 2681
770597ec 2682 nvme_free_tagset(dev);
253fd4ac
IR		 2683 put_device(dev->dev);
2684 kfree(dev->queues);
5e82e952
KB		 2685 kfree(dev);
2686}
2687
fd634f41 2688static void nvme_reset_work(struct work_struct *work)
5e82e952 2689{
d86c4d8e
CH		 2690 struct nvme_dev *dev =
2691 container_of(work, struct nvme_dev, ctrl.reset_work);
a98e58e5 2692 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
e71afda4 2693 int result;
5e82e952 2694
7764656b
ZC		 2695 if (dev->ctrl.state != NVME_CTRL_RESETTING) {
2696 dev_warn(dev->ctrl.device, "ctrl state %d is not RESETTING\n",
2697 dev->ctrl.state);
8cb9f10b 2698 return;
e71afda4 2699 }
5e82e952 2700
fd634f41
CH		 2701 /*
2702 * If we're called to reset a live controller first shut it down before
2703 * moving on.
2704 */
b00a726a 2705 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
a5cdb68c 2706 nvme_dev_disable(dev, false);
d6135c3a 2707 nvme_sync_queues(&dev->ctrl);
5e82e952 2708
5c959d73 2709 mutex_lock(&dev->shutdown_lock);
b00a726a 2710 result = nvme_pci_enable(dev);
f0b50732 2711 if (result)
4726bcf3 2712 goto out_unlock;
9f27bd70 2713 nvme_unquiesce_admin_queue(&dev->ctrl);
5c959d73
KB		 2714 mutex_unlock(&dev->shutdown_lock);
2715
2716 /*
2717 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
2718 * initializing procedure here.
2719 */
2720 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
2721 dev_warn(dev->ctrl.device,
2722 "failed to mark controller CONNECTING\n");
cee6c269 2723 result = -EBUSY;
5c959d73
KB		 2724 goto out;
2725 }
943e942e 2726
94cc781f 2727 result = nvme_init_ctrl_finish(&dev->ctrl, was_suspend);
ce4541f4 2728 if (result)
f58944e2 2729 goto out;
ce4541f4 2730
65a54646 2731 nvme_dbbuf_dma_alloc(dev);
f9f38e33 2732
acb71e53
CH		 2733 result = nvme_setup_host_mem(dev);
2734 if (result < 0)
2735 goto out;
87ad72a5 2736
f0b50732 2737 result = nvme_setup_io_queues(dev);
badc34d4 2738 if (result)
f58944e2 2739 goto out;
f0b50732 2740
2659e57b 2741 /*
eac3ef26
CH		 2742 * Freeze and update the number of I/O queues as thos might have
2743 * changed. If there are no I/O queues left after this reset, keep the
2744 * controller around but remove all namespaces.
2659e57b 2745 */
eac3ef26 2746 if (dev->online_queues > 1) {
9f27bd70 2747 nvme_unquiesce_io_queues(&dev->ctrl);
302ad8cc 2748 nvme_wait_freeze(&dev->ctrl);
eac3ef26 2749 nvme_pci_update_nr_queues(dev);
2455a4b7 2750 nvme_dbbuf_set(dev);
302ad8cc 2751 nvme_unfreeze(&dev->ctrl);
3cf519b5 2752 } else {
eac3ef26
CH		 2753 dev_warn(dev->ctrl.device, "IO queues lost\n");
2754 nvme_mark_namespaces_dead(&dev->ctrl);
9f27bd70 2755 nvme_unquiesce_io_queues(&dev->ctrl);
eac3ef26
CH		 2756 nvme_remove_namespaces(&dev->ctrl);
2757 nvme_free_tagset(dev);
3cf519b5
CH		 2758 }
2759
2b1b7e78
JW		 2760 /*
2761 * If only admin queue live, keep it to do further investigation or
2762 * recovery.
2763 */
5d02a5c1 2764 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
2b1b7e78 2765 dev_warn(dev->ctrl.device,
5d02a5c1 2766 "failed to mark controller live state\n");
e71afda4 2767 result = -ENODEV;
bb8d261e
CH		 2768 goto out;
2769 }
92911a55 2770
d09f2b45 2771 nvme_start_ctrl(&dev->ctrl);
3cf519b5 2772 return;
f0b50732 2773
4726bcf3
KB		 2774 out_unlock:
2775 mutex_unlock(&dev->shutdown_lock);
3cf519b5 2776 out:
c7c16c5b
CH		 2777 /*
2778 * Set state to deleting now to avoid blocking nvme_wait_reset(), which
2779 * may be holding this pci_dev's device lock.
2780 */
2781 dev_warn(dev->ctrl.device, "Disabling device after reset failure: %d\n",
2782 result);
2783 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
2784 nvme_dev_disable(dev, true);
2785 nvme_mark_namespaces_dead(&dev->ctrl);
2786 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
9a6b9458
KB		 2787}
2788
1c63dc66 2789static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
9ca97374 2790{
1c63dc66 2791 *val = readl(to_nvme_dev(ctrl)->bar + off);
90667892 2792 return 0;
9ca97374
TH		 2793}
2794
5fd4ce1b 2795static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
4cc06521 2796{
5fd4ce1b
CH		 2797 writel(val, to_nvme_dev(ctrl)->bar + off);
2798 return 0;
2799}
4cc06521 2800
7fd8930f
CH		 2801static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2802{
3a8ecc93 2803 *val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off);
7fd8930f 2804 return 0;
4cc06521
KB		 2805}
2806
97c12223
KB		 2807static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
2808{
2809 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2810
2db24e4a 2811 return snprintf(buf, size, "%s\n", dev_name(&pdev->dev));
97c12223
KB		 2812}
2813
2f0dad17
KB		 2814static void nvme_pci_print_device_info(struct nvme_ctrl *ctrl)
2815{
2816 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2817 struct nvme_subsystem *subsys = ctrl->subsys;
2818
2819 dev_err(ctrl->device,
2820 "VID:DID %04x:%04x model:%.*s firmware:%.*s\n",
2821 pdev->vendor, pdev->device,
2822 nvme_strlen(subsys->model, sizeof(subsys->model)),
2823 subsys->model, nvme_strlen(subsys->firmware_rev,
2824 sizeof(subsys->firmware_rev)),
2825 subsys->firmware_rev);
2826}
2827
2f859441
LG		 2828static bool nvme_pci_supports_pci_p2pdma(struct nvme_ctrl *ctrl)
2829{
2830 struct nvme_dev *dev = to_nvme_dev(ctrl);
2831
2832 return dma_pci_p2pdma_supported(dev->dev);
2833}
2834
1c63dc66 2835static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
1a353d85 2836 .name = "pcie",
e439bb12 2837 .module = THIS_MODULE,
2f859441 2838 .flags = NVME_F_METADATA_SUPPORTED,
86adbf0c 2839 .dev_attr_groups = nvme_pci_dev_attr_groups,
1c63dc66 2840 .reg_read32 = nvme_pci_reg_read32,
5fd4ce1b 2841 .reg_write32 = nvme_pci_reg_write32,
7fd8930f 2842 .reg_read64 = nvme_pci_reg_read64,
1673f1f0 2843 .free_ctrl = nvme_pci_free_ctrl,
f866fc42 2844 .submit_async_event = nvme_pci_submit_async_event,
97c12223 2845 .get_address = nvme_pci_get_address,
2f0dad17 2846 .print_device_info = nvme_pci_print_device_info,
2f859441 2847 .supports_pci_p2pdma = nvme_pci_supports_pci_p2pdma,
1c63dc66 2848};
4cc06521 2849
b00a726a
KB		 2850static int nvme_dev_map(struct nvme_dev *dev)
2851{
b00a726a
KB		 2852 struct pci_dev *pdev = to_pci_dev(dev->dev);
2853
a1f447b3 2854 if (pci_request_mem_regions(pdev, "nvme"))
b00a726a
KB		 2855 return -ENODEV;
2856
97f6ef64 2857 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
b00a726a
KB		 2858 goto release;
2859
9fa196e7 2860 return 0;
b00a726a 2861 release:
9fa196e7
MG		 2862 pci_release_mem_regions(pdev);
2863 return -ENODEV;
b00a726a
KB		 2864}
2865
8427bbc2 2866static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
ff5350a8
AL		 2867{
2868 if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
2869 /*
2870 * Several Samsung devices seem to drop off the PCIe bus
2871 * randomly when APST is on and uses the deepest sleep state.
2872 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2873 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2874 * 950 PRO 256GB", but it seems to be restricted to two Dell
2875 * laptops.
2876 */
2877 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
2878 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
2879 dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
2880 return NVME_QUIRK_NO_DEEPEST_PS;
8427bbc2
KHF		 2881 } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
2882 /*
2883 * Samsung SSD 960 EVO drops off the PCIe bus after system
467c77d4
JJ		 2884 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
2885 * within few minutes after bootup on a Coffee Lake board -
2886 * ASUS PRIME Z370-A
8427bbc2
KHF		 2887 */
2888 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
467c77d4
JJ		 2889 (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") ||
2890 dmi_match(DMI_BOARD_NAME, "PRIME Z370-A")))
8427bbc2 2891 return NVME_QUIRK_NO_APST;
1fae37ac
S		 2892 } else if ((pdev->vendor == 0x144d && (pdev->device == 0xa801 ||
2893 pdev->device == 0xa808 || pdev->device == 0xa809)) ||
2894 (pdev->vendor == 0x1e0f && pdev->device == 0x0001)) {
2895 /*
2896 * Forcing to use host managed nvme power settings for
2897 * lowest idle power with quick resume latency on
2898 * Samsung and Toshiba SSDs based on suspend behavior
2899 * on Coffee Lake board for LENOVO C640
2900 */
2901 if ((dmi_match(DMI_BOARD_VENDOR, "LENOVO")) &&
2902 dmi_match(DMI_BOARD_NAME, "LNVNB161216"))
2903 return NVME_QUIRK_SIMPLE_SUSPEND;
ff5350a8
AL		 2904 }
2905
2906 return 0;
2907}
2908
2e87570b
CH		 2909static struct nvme_dev *nvme_pci_alloc_dev(struct pci_dev *pdev,
2910 const struct pci_device_id *id)
18119775 2911{
ff5350a8 2912 unsigned long quirks = id->driver_data;
2e87570b
CH		 2913 int node = dev_to_node(&pdev->dev);
2914 struct nvme_dev *dev;
2915 int ret = -ENOMEM;
b60503ba 2916
a4aea562 2917 if (node == NUMA_NO_NODE)
2fa84351 2918 set_dev_node(&pdev->dev, first_memory_node);
a4aea562
MB		 2919
2920 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
b60503ba 2921 if (!dev)
2e87570b
CH		 2922 return NULL;
2923 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
2e87570b 2924 mutex_init(&dev->shutdown_lock);
147b27e4 2925
2a5bcfdd
WZ		 2926 dev->nr_write_queues = write_queues;
2927 dev->nr_poll_queues = poll_queues;
2928 dev->nr_allocated_queues = nvme_max_io_queues(dev) + 1;
2929 dev->queues = kcalloc_node(dev->nr_allocated_queues,
2930 sizeof(struct nvme_queue), GFP_KERNEL, node);
b60503ba 2931 if (!dev->queues)
2e87570b 2932 goto out_free_dev;
b60503ba 2933
e75ec752 2934 dev->dev = get_device(&pdev->dev);
4cc06521 2935
8427bbc2 2936 quirks |= check_vendor_combination_bug(pdev);
2744d7a0 2937 if (!noacpi && acpi_storage_d3(&pdev->dev)) {
df4f9bc4
DB		 2938 /*
2939 * Some systems use a bios work around to ask for D3 on
2940 * platforms that support kernel managed suspend.
2941 */
2942 dev_info(&pdev->dev,
2943 "platform quirk: setting simple suspend\n");
2944 quirks |= NVME_QUIRK_SIMPLE_SUSPEND;
2945 }
2e87570b
CH		 2946 ret = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
2947 quirks);
2948 if (ret)
2949 goto out_put_device;
3f30a79c
CH		 2950
2951 dma_set_min_align_mask(&pdev->dev, NVME_CTRL_PAGE_SIZE - 1);
2952 dma_set_max_seg_size(&pdev->dev, 0xffffffff);
df4f9bc4 2953
943e942e 2954 /*
3f30a79c
CH		 2955 * Limit the max command size to prevent iod->sg allocations going
2956 * over a single page.
943e942e 2957 */
3f30a79c
CH		 2958 dev->ctrl.max_hw_sectors = min_t(u32,
2959 NVME_MAX_KB_SZ << 1, dma_max_mapping_size(&pdev->dev) >> 9);
2960 dev->ctrl.max_segments = NVME_MAX_SEGS;
943e942e 2961
3f30a79c
CH		 2962 /*
2963 * There is no support for SGLs for metadata (yet), so we are limited to
2964 * a single integrity segment for the separate metadata pointer.
2965 */
2966 dev->ctrl.max_integrity_segments = 1;
2e87570b 2967 return dev;
df4f9bc4 2968
2e87570b
CH		 2969out_put_device:
2970 put_device(dev->dev);
2971 kfree(dev->queues);
2972out_free_dev:
2973 kfree(dev);
2974 return ERR_PTR(ret);
2975}
943e942e 2976
2e87570b
CH		 2977static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2978{
2979 struct nvme_dev *dev;
2980 int result = -ENOMEM;
2981
2982 dev = nvme_pci_alloc_dev(pdev, id);
2983 if (!dev)
2984 return -ENOMEM;
2985
2986 result = nvme_dev_map(dev);
b6e44b4c 2987 if (result)
2e87570b
CH		 2988 goto out_uninit_ctrl;
2989
2990 result = nvme_setup_prp_pools(dev);
081a7d95 2991 if (result)
2e87570b 2992 goto out_dev_unmap;
943e942e 2993
2e87570b 2994 result = nvme_pci_alloc_iod_mempool(dev);
b6e44b4c 2995 if (result)
2e87570b 2996 goto out_release_prp_pools;
b6e44b4c 2997
1b3c47c1
SG		 2998 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
2999
eac3ef26
CH		 3000 result = nvme_pci_enable(dev);
3001 if (result)
3002 goto out_release_iod_mempool;
3003
0da7feaa
CH		 3004 result = nvme_alloc_admin_tag_set(&dev->ctrl, &dev->admin_tagset,
3005 &nvme_mq_admin_ops, sizeof(struct nvme_iod));
eac3ef26
CH		 3006 if (result)
3007 goto out_disable;
3008
3009 /*
3010 * Mark the controller as connecting before sending admin commands to
3011 * allow the timeout handler to do the right thing.
3012 */
3013 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
3014 dev_warn(dev->ctrl.device,
3015 "failed to mark controller CONNECTING\n");
3016 result = -EBUSY;
3017 goto out_disable;
3018 }
3019
3020 result = nvme_init_ctrl_finish(&dev->ctrl, false);
3021 if (result)
3022 goto out_disable;
3023
3024 nvme_dbbuf_dma_alloc(dev);
3025
3026 result = nvme_setup_host_mem(dev);
3027 if (result < 0)
3028 goto out_disable;
3029
3030 result = nvme_setup_io_queues(dev);
3031 if (result)
3032 goto out_disable;
4caff8fc 3033
eac3ef26 3034 if (dev->online_queues > 1) {
0da7feaa
CH		 3035 nvme_alloc_io_tag_set(&dev->ctrl, &dev->tagset, &nvme_mq_ops,
3036 nvme_pci_nr_maps(dev), sizeof(struct nvme_iod));
eac3ef26 3037 nvme_dbbuf_set(dev);
eac3ef26
CH		 3038 }
3039
0da7feaa
CH		 3040 if (!dev->ctrl.tagset)
3041 dev_warn(dev->ctrl.device, "IO queues not created\n");
3042
eac3ef26
CH		 3043 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
3044 dev_warn(dev->ctrl.device,
3045 "failed to mark controller live state\n");
3046 result = -ENODEV;
3047 goto out_disable;
3048 }
3049
2e87570b 3050 pci_set_drvdata(pdev, dev);
1b3c47c1 3051
eac3ef26
CH		 3052 nvme_start_ctrl(&dev->ctrl);
3053 nvme_put_ctrl(&dev->ctrl);
5a5754a4 3054 flush_work(&dev->ctrl.scan_work);
b60503ba
MW		 3055 return 0;
3056
eac3ef26
CH		 3057out_disable:
3058 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
3059 nvme_dev_disable(dev, true);
3060 nvme_free_host_mem(dev);
3061 nvme_dev_remove_admin(dev);
3062 nvme_dbbuf_dma_free(dev);
3063 nvme_free_queues(dev, 0);
3064out_release_iod_mempool:
b6e44b4c 3065 mempool_destroy(dev->iod_mempool);
2e87570b 3066out_release_prp_pools:
091b6092 3067 nvme_release_prp_pools(dev);
2e87570b 3068out_dev_unmap:
b00c9b7a 3069 nvme_dev_unmap(dev);
2e87570b
CH		 3070out_uninit_ctrl:
3071 nvme_uninit_ctrl(&dev->ctrl);
b60503ba
MW		 3072 return result;
3073}
3074
775755ed 3075static void nvme_reset_prepare(struct pci_dev *pdev)
f0d54a54 3076{
a6739479 3077 struct nvme_dev *dev = pci_get_drvdata(pdev);
c1ac9a4b
KB		 3078
3079 /*
3080 * We don't need to check the return value from waiting for the reset
3081 * state as pci_dev device lock is held, making it impossible to race
3082 * with ->remove().
3083 */
3084 nvme_disable_prepare_reset(dev, false);
3085 nvme_sync_queues(&dev->ctrl);
775755ed 3086}
f0d54a54 3087
775755ed
CH		 3088static void nvme_reset_done(struct pci_dev *pdev)
3089{
f263fbb8 3090 struct nvme_dev *dev = pci_get_drvdata(pdev);
c1ac9a4b
KB		 3091
3092 if (!nvme_try_sched_reset(&dev->ctrl))
3093 flush_work(&dev->ctrl.reset_work);
f0d54a54
KB		 3094}
3095
09ece142
KB		 3096static void nvme_shutdown(struct pci_dev *pdev)
3097{
3098 struct nvme_dev *dev = pci_get_drvdata(pdev);
4e523547 3099
c1ac9a4b 3100 nvme_disable_prepare_reset(dev, true);
09ece142
KB		 3101}
3102
f58944e2
KB		 3103/*
3104 * The driver's remove may be called on a device in a partially initialized
3105 * state. This function must not have any dependencies on the device state in
3106 * order to proceed.
3107 */
8d85fce7 3108static void nvme_remove(struct pci_dev *pdev)
b60503ba
MW		 3109{
3110 struct nvme_dev *dev = pci_get_drvdata(pdev);
9a6b9458 3111
bb8d261e 3112 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
9a6b9458 3113 pci_set_drvdata(pdev, NULL);
0ff9d4e1 3114
6db28eda 3115 if (!pci_device_is_present(pdev)) {
0ff9d4e1 3116 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
1d39e692 3117 nvme_dev_disable(dev, true);
6db28eda 3118 }
0ff9d4e1 3119
d86c4d8e 3120 flush_work(&dev->ctrl.reset_work);
d09f2b45
SG		 3121 nvme_stop_ctrl(&dev->ctrl);
3122 nvme_remove_namespaces(&dev->ctrl);
a5cdb68c 3123 nvme_dev_disable(dev, true);
87ad72a5 3124 nvme_free_host_mem(dev);
a4aea562 3125 nvme_dev_remove_admin(dev);
c11b7716 3126 nvme_dbbuf_dma_free(dev);
a1a5ef99 3127 nvme_free_queues(dev, 0);
c11b7716 3128 mempool_destroy(dev->iod_mempool);
9a6b9458 3129 nvme_release_prp_pools(dev);
b00a726a 3130 nvme_dev_unmap(dev);
726612b6 3131 nvme_uninit_ctrl(&dev->ctrl);
b60503ba
MW		 3132}
3133
671a6018 3134#ifdef CONFIG_PM_SLEEP
d916b1be
KB		 3135static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps)
3136{
3137 return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps);
3138}
3139
3140static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps)
3141{
3142 return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL);
3143}
3144
3145static int nvme_resume(struct device *dev)
3146{
3147 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
3148 struct nvme_ctrl *ctrl = &ndev->ctrl;
3149
4eaefe8c 3150 if (ndev->last_ps == U32_MAX ||
d916b1be 3151 nvme_set_power_state(ctrl, ndev->last_ps) != 0)
e5ad96f3
KB		 3152 goto reset;
3153 if (ctrl->hmpre && nvme_setup_host_mem(ndev))
3154 goto reset;
3155
d916b1be 3156 return 0;
e5ad96f3
KB		 3157reset:
3158 return nvme_try_sched_reset(ctrl);
d916b1be
KB		 3159}
3160
cd638946
KB		 3161static int nvme_suspend(struct device *dev)
3162{
3163 struct pci_dev *pdev = to_pci_dev(dev);
3164 struct nvme_dev *ndev = pci_get_drvdata(pdev);
d916b1be
KB		 3165 struct nvme_ctrl *ctrl = &ndev->ctrl;
3166 int ret = -EBUSY;
3167
4eaefe8c
RW		 3168 ndev->last_ps = U32_MAX;
3169
d916b1be
KB		 3170 /*
3171 * The platform does not remove power for a kernel managed suspend so
3172 * use host managed nvme power settings for lowest idle power if
3173 * possible. This should have quicker resume latency than a full device
3174 * shutdown. But if the firmware is involved after the suspend or the
3175 * device does not support any non-default power states, shut down the
3176 * device fully.
4eaefe8c
RW		 3177 *
3178 * If ASPM is not enabled for the device, shut down the device and allow
3179 * the PCI bus layer to put it into D3 in order to take the PCIe link
3180 * down, so as to allow the platform to achieve its minimum low-power
3181 * state (which may not be possible if the link is up).
d916b1be 3182 */
4eaefe8c 3183 if (pm_suspend_via_firmware() || !ctrl->npss ||
cb32de1b 3184 !pcie_aspm_enabled(pdev) ||
c1ac9a4b
KB		 3185 (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND))
3186 return nvme_disable_prepare_reset(ndev, true);
d916b1be
KB		 3187
3188 nvme_start_freeze(ctrl);
3189 nvme_wait_freeze(ctrl);
3190 nvme_sync_queues(ctrl);
3191
5d02a5c1 3192 if (ctrl->state != NVME_CTRL_LIVE)
d916b1be
KB		 3193 goto unfreeze;
3194
e5ad96f3
KB		 3195 /*
3196 * Host memory access may not be successful in a system suspend state,
3197 * but the specification allows the controller to access memory in a
3198 * non-operational power state.
3199 */
3200 if (ndev->hmb) {
3201 ret = nvme_set_host_mem(ndev, 0);
3202 if (ret < 0)
3203 goto unfreeze;
3204 }
3205
d916b1be
KB		 3206 ret = nvme_get_power_state(ctrl, &ndev->last_ps);
3207 if (ret < 0)
3208 goto unfreeze;
3209
7cbb5c6f
ML		 3210 /*
3211 * A saved state prevents pci pm from generically controlling the
3212 * device's power. If we're using protocol specific settings, we don't
3213 * want pci interfering.
3214 */
3215 pci_save_state(pdev);
3216
d916b1be
KB		 3217 ret = nvme_set_power_state(ctrl, ctrl->npss);
3218 if (ret < 0)
3219 goto unfreeze;
3220
3221 if (ret) {
7cbb5c6f
ML		 3222 /* discard the saved state */
3223 pci_load_saved_state(pdev, NULL);
3224
d916b1be
KB		 3225 /*
3226 * Clearing npss forces a controller reset on resume. The
05d3046f 3227 * correct value will be rediscovered then.
d916b1be 3228 */
c1ac9a4b 3229 ret = nvme_disable_prepare_reset(ndev, true);
d916b1be 3230 ctrl->npss = 0;
d916b1be 3231 }
d916b1be
KB		 3232unfreeze:
3233 nvme_unfreeze(ctrl);
3234 return ret;
3235}
3236
3237static int nvme_simple_suspend(struct device *dev)
3238{
3239 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
4e523547 3240
c1ac9a4b 3241 return nvme_disable_prepare_reset(ndev, true);
cd638946
KB		 3242}
3243
d916b1be 3244static int nvme_simple_resume(struct device *dev)
cd638946
KB		 3245{
3246 struct pci_dev *pdev = to_pci_dev(dev);
3247 struct nvme_dev *ndev = pci_get_drvdata(pdev);
cd638946 3248
c1ac9a4b 3249 return nvme_try_sched_reset(&ndev->ctrl);
cd638946
KB		 3250}
3251
21774222 3252static const struct dev_pm_ops nvme_dev_pm_ops = {
d916b1be
KB		 3253 .suspend = nvme_suspend,
3254 .resume = nvme_resume,
3255 .freeze = nvme_simple_suspend,
3256 .thaw = nvme_simple_resume,
3257 .poweroff = nvme_simple_suspend,
3258 .restore = nvme_simple_resume,
3259};
3260#endif /* CONFIG_PM_SLEEP */
b60503ba 3261
a0a3408e
KB		 3262static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
3263 pci_channel_state_t state)
3264{
3265 struct nvme_dev *dev = pci_get_drvdata(pdev);
3266
3267 /*
3268 * A frozen channel requires a reset. When detected, this method will
3269 * shutdown the controller to quiesce. The controller will be restarted
3270 * after the slot reset through driver's slot_reset callback.
3271 */
a0a3408e
KB		 3272 switch (state) {
3273 case pci_channel_io_normal:
3274 return PCI_ERS_RESULT_CAN_RECOVER;
3275 case pci_channel_io_frozen:
d011fb31
KB		 3276 dev_warn(dev->ctrl.device,
3277 "frozen state error detected, reset controller\n");
a5cdb68c 3278 nvme_dev_disable(dev, false);
a0a3408e
KB		 3279 return PCI_ERS_RESULT_NEED_RESET;
3280 case pci_channel_io_perm_failure:
d011fb31
KB		 3281 dev_warn(dev->ctrl.device,
3282 "failure state error detected, request disconnect\n");
a0a3408e
KB		 3283 return PCI_ERS_RESULT_DISCONNECT;
3284 }
3285 return PCI_ERS_RESULT_NEED_RESET;
3286}
3287
3288static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
3289{
3290 struct nvme_dev *dev = pci_get_drvdata(pdev);
3291
1b3c47c1 3292 dev_info(dev->ctrl.device, "restart after slot reset\n");
a0a3408e 3293 pci_restore_state(pdev);
d86c4d8e 3294 nvme_reset_ctrl(&dev->ctrl);
a0a3408e
KB		 3295 return PCI_ERS_RESULT_RECOVERED;
3296}
3297
3298static void nvme_error_resume(struct pci_dev *pdev)
3299{
72cd4cc2
KB		 3300 struct nvme_dev *dev = pci_get_drvdata(pdev);
3301
3302 flush_work(&dev->ctrl.reset_work);
a0a3408e
KB		 3303}
3304
1d352035 3305static const struct pci_error_handlers nvme_err_handler = {
b60503ba 3306 .error_detected = nvme_error_detected,
b60503ba
MW		 3307 .slot_reset = nvme_slot_reset,
3308 .resume = nvme_error_resume,
775755ed
CH		 3309 .reset_prepare = nvme_reset_prepare,
3310 .reset_done = nvme_reset_done,
b60503ba
MW		 3311};
3312
6eb0d698 3313static const struct pci_device_id nvme_id_table[] = {
972b13e2 3314 { PCI_VDEVICE(INTEL, 0x0953), /* Intel 750/P3500/P3600/P3700 */
08095e70 3315 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 3316 NVME_QUIRK_DEALLOCATE_ZEROES, },
972b13e2 3317 { PCI_VDEVICE(INTEL, 0x0a53), /* Intel P3520 */
99466e70 3318 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 3319 NVME_QUIRK_DEALLOCATE_ZEROES, },
972b13e2 3320 { PCI_VDEVICE(INTEL, 0x0a54), /* Intel P4500/P4600 */
99466e70 3321 .driver_data = NVME_QUIRK_STRIPE_SIZE |
25e58af4
WZ		 3322 NVME_QUIRK_DEALLOCATE_ZEROES |
3323 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
972b13e2 3324 { PCI_VDEVICE(INTEL, 0x0a55), /* Dell Express Flash P4600 */
f99cb7af
DWF		 3325 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3326 NVME_QUIRK_DEALLOCATE_ZEROES, },
50af47d0 3327 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */
9abd68ef 3328 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
6c6aa2f2 3329 NVME_QUIRK_MEDIUM_PRIO_SQ |
ce4cc313
DM		 3330 NVME_QUIRK_NO_TEMP_THRESH_CHANGE |
3331 NVME_QUIRK_DISABLE_WRITE_ZEROES, },
6299358d
JD		 3332 { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */
3333 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
540c801c 3334 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */
7b210e4e 3335 .driver_data = NVME_QUIRK_IDENTIFY_CNS |
66dd346b
CH		 3336 NVME_QUIRK_DISABLE_WRITE_ZEROES |
3337 NVME_QUIRK_BOGUS_NID, },
3338 { PCI_VDEVICE(REDHAT, 0x0010), /* Qemu emulated controller */
3339 .driver_data = NVME_QUIRK_BOGUS_NID, },
5bedd3af 3340 { PCI_DEVICE(0x126f, 0x2263), /* Silicon Motion unidentified */
c98a8793
KB		 3341 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST |
3342 NVME_QUIRK_BOGUS_NID, },
0302ae60 3343 { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */
5e112d3f
JE		 3344 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
3345 NVME_QUIRK_NO_NS_DESC_LIST, },
54adc010
GP		 3346 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
3347 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
8c97eecc
JL		 3348 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */
3349 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
015282c9
WW		 3350 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
3351 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
d554b5e1
MP		 3352 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */
3353 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3354 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */
7ee5c78c 3355 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
abbb5f59 3356 NVME_QUIRK_DISABLE_WRITE_ZEROES|
7ee5c78c 3357 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
2cf7a77e
KB		 3358 { PCI_DEVICE(0x1987, 0x5012), /* Phison E12 */
3359 .driver_data = NVME_QUIRK_BOGUS_NID, },
c9e95c39 3360 { PCI_DEVICE(0x1987, 0x5016), /* Phison E16 */
73029c9b
KB		 3361 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN |
3362 NVME_QUIRK_BOGUS_NID, },
d14c2731
TH		 3363 { PCI_DEVICE(0x1987, 0x5019), /* phison E19 */
3364 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3365 { PCI_DEVICE(0x1987, 0x5021), /* Phison E21 */
3366 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
6e6a6828
PT		 3367 { PCI_DEVICE(0x1b4b, 0x1092), /* Lexar 256 GB SSD */
3368 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST |
3369 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
e1c70d79
LVS		 3370 { PCI_DEVICE(0x1cc1, 0x33f8), /* ADATA IM2P33F8ABR1 1 TB */
3371 .driver_data = NVME_QUIRK_BOGUS_NID, },
08b903b5 3372 { PCI_DEVICE(0x10ec, 0x5762), /* ADATA SX6000LNP */
1629de0e
PG		 3373 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN |
3374 NVME_QUIRK_BOGUS_NID, },
f03e42c6
GC		 3375 { PCI_DEVICE(0x1cc1, 0x8201), /* ADATA SX8200PNP 512GB */
3376 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3377 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
41f38043
LS		 3378 { PCI_DEVICE(0x1344, 0x5407), /* Micron Technology Inc NVMe SSD */
3379 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN },
d5ceb4d1
BH		 3380 { PCI_DEVICE(0x1344, 0x6001), /* Micron Nitro NVMe */
3381 .driver_data = NVME_QUIRK_BOGUS_NID, },
5611ec2b
KHF		 3382 { PCI_DEVICE(0x1c5c, 0x1504), /* SK Hynix PC400 */
3383 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
c4f01a77
KB		 3384 { PCI_DEVICE(0x1c5c, 0x174a), /* SK Hynix P31 SSD */
3385 .driver_data = NVME_QUIRK_BOGUS_NID, },
02ca079c
KHF		 3386 { PCI_DEVICE(0x15b7, 0x2001), /* Sandisk Skyhawk */
3387 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
89919929
CK		 3388 { PCI_DEVICE(0x1d97, 0x2263), /* SPCC */
3389 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
43047e08 3390 { PCI_DEVICE(0x144d, 0xa80b), /* Samsung PM9B1 256G and 512G */
3391 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3392 { PCI_DEVICE(0x144d, 0xa809), /* Samsung MZALQ256HBJD 256G */
3393 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3394 { PCI_DEVICE(0x1cc4, 0x6303), /* UMIS RPJTJ512MGE1QDY 512G */
3395 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3396 { PCI_DEVICE(0x1cc4, 0x6302), /* UMIS RPJTJ256MGE1QDY 256G */
3397 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
dc22c1c0
ZB		 3398 { PCI_DEVICE(0x2646, 0x2262), /* KINGSTON SKC2000 NVMe SSD */
3399 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
538e4a8c
TL		 3400 { PCI_DEVICE(0x2646, 0x2263), /* KINGSTON A2000 NVMe SSD */
3401 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
ac9b57d4
XL		 3402 { PCI_DEVICE(0x2646, 0x5018), /* KINGSTON OM8SFP4xxxxP OS21012 NVMe SSD */
3403 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3404 { PCI_DEVICE(0x2646, 0x5016), /* KINGSTON OM3PGP4xxxxP OS21011 NVMe SSD */
3405 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3406 { PCI_DEVICE(0x2646, 0x501A), /* KINGSTON OM8PGP4xxxxP OS21005 NVMe SSD */
3407 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3408 { PCI_DEVICE(0x2646, 0x501B), /* KINGSTON OM8PGP4xxxxQ OS21005 NVMe SSD */
3409 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3410 { PCI_DEVICE(0x2646, 0x501E), /* KINGSTON OM3PGP4xxxxQ OS21011 NVMe SSD */
3411 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
8d6e38f6
TDF		 3412 { PCI_DEVICE(0x1f40, 0x5236), /* Netac Technologies Co. NV7000 NVMe SSD */
3413 .driver_data = NVME_QUIRK_BOGUS_NID, },
70ce3455
CH		 3414 { PCI_DEVICE(0x1e4B, 0x1001), /* MAXIO MAP1001 */
3415 .driver_data = NVME_QUIRK_BOGUS_NID, },
a98a945b
CH		 3416 { PCI_DEVICE(0x1e4B, 0x1002), /* MAXIO MAP1002 */
3417 .driver_data = NVME_QUIRK_BOGUS_NID, },
3418 { PCI_DEVICE(0x1e4B, 0x1202), /* MAXIO MAP1202 */
3419 .driver_data = NVME_QUIRK_BOGUS_NID, },
3765fad5
SR		 3420 { PCI_DEVICE(0x1cc1, 0x5350), /* ADATA XPG GAMMIX S50 */
3421 .driver_data = NVME_QUIRK_BOGUS_NID, },
f37527a0
DK		 3422 { PCI_DEVICE(0x1dbe, 0x5236), /* ADATA XPG GAMMIX S70 */
3423 .driver_data = NVME_QUIRK_BOGUS_NID, },
d5d3c100
XR		 3424 { PCI_DEVICE(0x1e49, 0x0021), /* ZHITAI TiPro5000 NVMe SSD */
3425 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
6b961bce
NW		 3426 { PCI_DEVICE(0x1e49, 0x0041), /* ZHITAI TiPro7000 NVMe SSD */
3427 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
d6c52fa3
TG		 3428 { PCI_DEVICE(0xc0a9, 0x540a), /* Crucial P2 */
3429 .driver_data = NVME_QUIRK_BOGUS_NID, },
200dccd0
SA		 3430 { PCI_DEVICE(0x1d97, 0x2263), /* Lexar NM610 */
3431 .driver_data = NVME_QUIRK_BOGUS_NID, },
80b26240
A		 3432 { PCI_DEVICE(0x1d97, 0x2269), /* Lexar NM760 */
3433 .driver_data = NVME_QUIRK_BOGUS_NID, },
4bdf2603
FS		 3434 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0061),
3435 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3436 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0065),
3437 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3438 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x8061),
3439 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3440 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd00),
3441 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3442 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd01),
3443 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3444 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd02),
3445 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
98f7b86a
AS		 3446 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001),
3447 .driver_data = NVME_QUIRK_SINGLE_VECTOR },
124298bd 3448 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
66341331
BH		 3449 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005),
3450 .driver_data = NVME_QUIRK_SINGLE_VECTOR |
d38e9f04 3451 NVME_QUIRK_128_BYTES_SQES |
a2941f6a 3452 NVME_QUIRK_SHARED_TAGS |
453116a4
HM		 3453 NVME_QUIRK_SKIP_CID_GEN |
3454 NVME_QUIRK_IDENTIFY_CNS },
0b85f59d 3455 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
b60503ba
MW		 3456 { 0, }
3457};
3458MODULE_DEVICE_TABLE(pci, nvme_id_table);
3459
3460static struct pci_driver nvme_driver = {
3461 .name = "nvme",
3462 .id_table = nvme_id_table,
3463 .probe = nvme_probe,
8d85fce7 3464 .remove = nvme_remove,
09ece142 3465 .shutdown = nvme_shutdown,
cd638946 3466 .driver = {
eac3ef26
CH		 3467 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
3468#ifdef CONFIG_PM_SLEEP
3469 .pm = &nvme_dev_pm_ops,
d916b1be 3470#endif
eac3ef26 3471 },
74d986ab 3472 .sriov_configure = pci_sriov_configure_simple,
b60503ba
MW		 3473 .err_handler = &nvme_err_handler,
3474};
3475
3476static int __init nvme_init(void)
3477{
81101540
CH		 3478 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
3479 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
3480 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
612b7286 3481 BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2);
01df742d 3482 BUILD_BUG_ON(NVME_MAX_SEGS > SGES_PER_PAGE);
7846c1b5
KB		 3483 BUILD_BUG_ON(sizeof(struct scatterlist) * NVME_MAX_SEGS > PAGE_SIZE);
3484 BUILD_BUG_ON(nvme_pci_npages_prp() > NVME_MAX_NR_ALLOCATIONS);
17c33167 3485
9a6327d2 3486 return pci_register_driver(&nvme_driver);
b60503ba
MW		 3487}
3488
3489static void __exit nvme_exit(void)
3490{
3491 pci_unregister_driver(&nvme_driver);
03e0f3a6 3492 flush_workqueue(nvme_wq);
b60503ba
MW		 3493}
3494
3495MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3496MODULE_LICENSE("GPL");
c78b4713 3497MODULE_VERSION("1.0");
b60503ba
MW		 3498module_init(nvme_init);
3499module_exit(nvme_exit);
Linux 6.x block layer and io_uring tree(s)