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nvme-pci: do not build a scatterlist to map metadata
[linux-2.6-block.git] / drivers / nvme / host / pci.c
CommitLineData
5f37396d 1// SPDX-License-Identifier: GPL-2.0
b60503ba
MW		 2/*
3 * NVM Express device driver
6eb0d698 4 * Copyright (c) 2011-2014, Intel Corporation.
b60503ba
MW		 5 */
6
a0a3408e 7#include <linux/aer.h>
18119775 8#include <linux/async.h>
b60503ba 9#include <linux/blkdev.h>
a4aea562 10#include <linux/blk-mq.h>
dca51e78 11#include <linux/blk-mq-pci.h>
ff5350a8 12#include <linux/dmi.h>
b60503ba
MW		 13#include <linux/init.h>
14#include <linux/interrupt.h>
15#include <linux/io.h>
b60503ba
MW		 16#include <linux/mm.h>
17#include <linux/module.h>
77bf25ea 18#include <linux/mutex.h>
d0877473 19#include <linux/once.h>
b60503ba 20#include <linux/pci.h>
e1e5e564 21#include <linux/t10-pi.h>
b60503ba 22#include <linux/types.h>
2f8e2c87 23#include <linux/io-64-nonatomic-lo-hi.h>
a98e58e5 24#include <linux/sed-opal.h>
0f238ff5 25#include <linux/pci-p2pdma.h>
797a796a 26
604c01d5 27#include "trace.h"
f11bb3e2
CH		 28#include "nvme.h"
29
b60503ba
MW		 30#define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
31#define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
c965809c 32
a7a7cbe3 33#define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc))
9d43cf64 34
943e942e
JA		 35/*
36 * These can be higher, but we need to ensure that any command doesn't
37 * require an sg allocation that needs more than a page of data.
38 */
39#define NVME_MAX_KB_SZ 4096
40#define NVME_MAX_SEGS 127
41
58ffacb5
MW		 42static int use_threaded_interrupts;
43module_param(use_threaded_interrupts, int, 0);
44
8ffaadf7 45static bool use_cmb_sqes = true;
69f4eb9f 46module_param(use_cmb_sqes, bool, 0444);
8ffaadf7
JD		 47MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
48
87ad72a5
CH		 49static unsigned int max_host_mem_size_mb = 128;
50module_param(max_host_mem_size_mb, uint, 0444);
51MODULE_PARM_DESC(max_host_mem_size_mb,
52 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
1fa6aead 53
a7a7cbe3
CK		 54static unsigned int sgl_threshold = SZ_32K;
55module_param(sgl_threshold, uint, 0644);
56MODULE_PARM_DESC(sgl_threshold,
57 "Use SGLs when average request segment size is larger or equal to "
58 "this size. Use 0 to disable SGLs.");
59
b27c1e68 60static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
61static const struct kernel_param_ops io_queue_depth_ops = {
62 .set = io_queue_depth_set,
63 .get = param_get_int,
64};
65
66static int io_queue_depth = 1024;
67module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
68MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2");
69
3b6592f7
JA		 70static int queue_count_set(const char *val, const struct kernel_param *kp);
71static const struct kernel_param_ops queue_count_ops = {
72 .set = queue_count_set,
73 .get = param_get_int,
74};
75
76static int write_queues;
77module_param_cb(write_queues, &queue_count_ops, &write_queues, 0644);
78MODULE_PARM_DESC(write_queues,
79 "Number of queues to use for writes. If not set, reads and writes "
80 "will share a queue set.");
81
a4668d9b 82static int poll_queues = 0;
4b04cc6a
JA		 83module_param_cb(poll_queues, &queue_count_ops, &poll_queues, 0644);
84MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO.");
85
1c63dc66
CH		 86struct nvme_dev;
87struct nvme_queue;
b3fffdef 88
a5cdb68c 89static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
8fae268b 90static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode);
d4b4ff8e 91
1c63dc66
CH		 92/*
93 * Represents an NVM Express device. Each nvme_dev is a PCI function.
94 */
95struct nvme_dev {
147b27e4 96 struct nvme_queue *queues;
1c63dc66
CH		 97 struct blk_mq_tag_set tagset;
98 struct blk_mq_tag_set admin_tagset;
99 u32 __iomem *dbs;
100 struct device *dev;
101 struct dma_pool *prp_page_pool;
102 struct dma_pool *prp_small_pool;
1c63dc66
CH		 103 unsigned online_queues;
104 unsigned max_qid;
e20ba6e1 105 unsigned io_queues[HCTX_MAX_TYPES];
22b55601 106 unsigned int num_vecs;
1c63dc66
CH		 107 int q_depth;
108 u32 db_stride;
1c63dc66 109 void __iomem *bar;
97f6ef64 110 unsigned long bar_mapped_size;
5c8809e6 111 struct work_struct remove_work;
77bf25ea 112 struct mutex shutdown_lock;
1c63dc66 113 bool subsystem;
1c63dc66 114 u64 cmb_size;
0f238ff5 115 bool cmb_use_sqes;
1c63dc66 116 u32 cmbsz;
202021c1 117 u32 cmbloc;
1c63dc66 118 struct nvme_ctrl ctrl;
87ad72a5 119
943e942e
JA		 120 mempool_t *iod_mempool;
121
87ad72a5 122 /* shadow doorbell buffer support: */
f9f38e33
HK		 123 u32 *dbbuf_dbs;
124 dma_addr_t dbbuf_dbs_dma_addr;
125 u32 *dbbuf_eis;
126 dma_addr_t dbbuf_eis_dma_addr;
87ad72a5
CH		 127
128 /* host memory buffer support: */
129 u64 host_mem_size;
130 u32 nr_host_mem_descs;
4033f35d 131 dma_addr_t host_mem_descs_dma;
87ad72a5
CH		 132 struct nvme_host_mem_buf_desc *host_mem_descs;
133 void **host_mem_desc_bufs;
4d115420 134};
1fa6aead 135
b27c1e68 136static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
137{
138 int n = 0, ret;
139
140 ret = kstrtoint(val, 10, &n);
141 if (ret != 0 || n < 2)
142 return -EINVAL;
143
144 return param_set_int(val, kp);
145}
146
3b6592f7
JA		 147static int queue_count_set(const char *val, const struct kernel_param *kp)
148{
149 int n = 0, ret;
150
151 ret = kstrtoint(val, 10, &n);
e895fedf
BVA		 152 if (ret)
153 return ret;
3b6592f7
JA		 154 if (n > num_possible_cpus())
155 n = num_possible_cpus();
156
157 return param_set_int(val, kp);
158}
159
f9f38e33
HK		 160static inline unsigned int sq_idx(unsigned int qid, u32 stride)
161{
162 return qid * 2 * stride;
163}
164
165static inline unsigned int cq_idx(unsigned int qid, u32 stride)
166{
167 return (qid * 2 + 1) * stride;
168}
169
1c63dc66
CH		 170static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
171{
172 return container_of(ctrl, struct nvme_dev, ctrl);
173}
174
b60503ba
MW		 175/*
176 * An NVM Express queue. Each device has at least two (one for admin
177 * commands and one for I/O commands).
178 */
179struct nvme_queue {
091b6092 180 struct nvme_dev *dev;
1ab0cd69 181 spinlock_t sq_lock;
b60503ba 182 struct nvme_command *sq_cmds;
3a7afd8e
CH		 183 /* only used for poll queues: */
184 spinlock_t cq_poll_lock ____cacheline_aligned_in_smp;
b60503ba 185 volatile struct nvme_completion *cqes;
42483228 186 struct blk_mq_tags **tags;
b60503ba
MW		 187 dma_addr_t sq_dma_addr;
188 dma_addr_t cq_dma_addr;
b60503ba
MW		 189 u32 __iomem *q_db;
190 u16 q_depth;
7c349dde 191 u16 cq_vector;
b60503ba 192 u16 sq_tail;
04f3eafd 193 u16 last_sq_tail;
b60503ba 194 u16 cq_head;
68fa9dbe 195 u16 last_cq_head;
c30341dc 196 u16 qid;
e9539f47 197 u8 cq_phase;
4e224106
CH		 198 unsigned long flags;
199#define NVMEQ_ENABLED 0
63223078 200#define NVMEQ_SQ_CMB 1
d1ed6aa1 201#define NVMEQ_DELETE_ERROR 2
7c349dde 202#define NVMEQ_POLLED 3
f9f38e33
HK		 203 u32 *dbbuf_sq_db;
204 u32 *dbbuf_cq_db;
205 u32 *dbbuf_sq_ei;
206 u32 *dbbuf_cq_ei;
d1ed6aa1 207 struct completion delete_done;
b60503ba
MW		 208};
209
71bd150c 210/*
9b048119
CH		 211 * The nvme_iod describes the data in an I/O.
212 *
213 * The sg pointer contains the list of PRP/SGL chunk allocations in addition
214 * to the actual struct scatterlist.
71bd150c
CH		 215 */
216struct nvme_iod {
d49187e9 217 struct nvme_request req;
f4800d6d 218 struct nvme_queue *nvmeq;
a7a7cbe3 219 bool use_sgl;
f4800d6d 220 int aborted;
71bd150c 221 int npages; /* In the PRP list. 0 means small pool in use */
71bd150c 222 int nents; /* Used in scatterlist */
71bd150c 223 dma_addr_t first_dma;
783b94bd 224 dma_addr_t meta_dma;
f4800d6d
CH		 225 struct scatterlist *sg;
226 struct scatterlist inline_sg[0];
b60503ba
MW		 227};
228
229/*
230 * Check we didin't inadvertently grow the command struct
231 */
232static inline void _nvme_check_size(void)
233{
234 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
235 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
236 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
237 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
238 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
f8ebf840 239 BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
c30341dc 240 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
b60503ba 241 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
0add5e8e
JT		 242 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != NVME_IDENTIFY_DATA_SIZE);
243 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != NVME_IDENTIFY_DATA_SIZE);
b60503ba 244 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
6ecec745 245 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
f9f38e33
HK		 246 BUILD_BUG_ON(sizeof(struct nvme_dbbuf) != 64);
247}
248
3b6592f7
JA		 249static unsigned int max_io_queues(void)
250{
4b04cc6a 251 return num_possible_cpus() + write_queues + poll_queues;
3b6592f7
JA		 252}
253
254static unsigned int max_queue_count(void)
255{
256 /* IO queues + admin queue */
257 return 1 + max_io_queues();
258}
259
f9f38e33
HK		 260static inline unsigned int nvme_dbbuf_size(u32 stride)
261{
3b6592f7 262 return (max_queue_count() * 8 * stride);
f9f38e33
HK		 263}
264
265static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
266{
267 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
268
269 if (dev->dbbuf_dbs)
270 return 0;
271
272 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
273 &dev->dbbuf_dbs_dma_addr,
274 GFP_KERNEL);
275 if (!dev->dbbuf_dbs)
276 return -ENOMEM;
277 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
278 &dev->dbbuf_eis_dma_addr,
279 GFP_KERNEL);
280 if (!dev->dbbuf_eis) {
281 dma_free_coherent(dev->dev, mem_size,
282 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
283 dev->dbbuf_dbs = NULL;
284 return -ENOMEM;
285 }
286
287 return 0;
288}
289
290static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
291{
292 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
293
294 if (dev->dbbuf_dbs) {
295 dma_free_coherent(dev->dev, mem_size,
296 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
297 dev->dbbuf_dbs = NULL;
298 }
299 if (dev->dbbuf_eis) {
300 dma_free_coherent(dev->dev, mem_size,
301 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
302 dev->dbbuf_eis = NULL;
303 }
304}
305
306static void nvme_dbbuf_init(struct nvme_dev *dev,
307 struct nvme_queue *nvmeq, int qid)
308{
309 if (!dev->dbbuf_dbs || !qid)
310 return;
311
312 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
313 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
314 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
315 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
316}
317
318static void nvme_dbbuf_set(struct nvme_dev *dev)
319{
320 struct nvme_command c;
321
322 if (!dev->dbbuf_dbs)
323 return;
324
325 memset(&c, 0, sizeof(c));
326 c.dbbuf.opcode = nvme_admin_dbbuf;
327 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
328 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
329
330 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
9bdcfb10 331 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
f9f38e33
HK		 332 /* Free memory and continue on */
333 nvme_dbbuf_dma_free(dev);
334 }
335}
336
337static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
338{
339 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
340}
341
342/* Update dbbuf and return true if an MMIO is required */
343static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
344 volatile u32 *dbbuf_ei)
345{
346 if (dbbuf_db) {
347 u16 old_value;
348
349 /*
350 * Ensure that the queue is written before updating
351 * the doorbell in memory
352 */
353 wmb();
354
355 old_value = *dbbuf_db;
356 *dbbuf_db = value;
357
f1ed3df2
MW		 358 /*
359 * Ensure that the doorbell is updated before reading the event
360 * index from memory. The controller needs to provide similar
361 * ordering to ensure the envent index is updated before reading
362 * the doorbell.
363 */
364 mb();
365
f9f38e33
HK		 366 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value))
367 return false;
368 }
369
370 return true;
b60503ba
MW		 371}
372
ac3dd5bd
JA		 373/*
374 * Max size of iod being embedded in the request payload
375 */
376#define NVME_INT_PAGES 2
5fd4ce1b 377#define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size)
ac3dd5bd
JA		 378
379/*
380 * Will slightly overestimate the number of pages needed. This is OK
381 * as it only leads to a small amount of wasted memory for the lifetime of
382 * the I/O.
383 */
384static int nvme_npages(unsigned size, struct nvme_dev *dev)
385{
5fd4ce1b
CH		 386 unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size,
387 dev->ctrl.page_size);
ac3dd5bd
JA		 388 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
389}
390
a7a7cbe3
CK		 391/*
392 * Calculates the number of pages needed for the SGL segments. For example a 4k
393 * page can accommodate 256 SGL descriptors.
394 */
395static int nvme_pci_npages_sgl(unsigned int num_seg)
ac3dd5bd 396{
a7a7cbe3 397 return DIV_ROUND_UP(num_seg * sizeof(struct nvme_sgl_desc), PAGE_SIZE);
f4800d6d 398}
ac3dd5bd 399
a7a7cbe3
CK		 400static unsigned int nvme_pci_iod_alloc_size(struct nvme_dev *dev,
401 unsigned int size, unsigned int nseg, bool use_sgl)
f4800d6d 402{
a7a7cbe3
CK		 403 size_t alloc_size;
404
405 if (use_sgl)
406 alloc_size = sizeof(__le64 *) * nvme_pci_npages_sgl(nseg);
407 else
408 alloc_size = sizeof(__le64 *) * nvme_npages(size, dev);
409
410 return alloc_size + sizeof(struct scatterlist) * nseg;
f4800d6d 411}
ac3dd5bd 412
a7a7cbe3 413static unsigned int nvme_pci_cmd_size(struct nvme_dev *dev, bool use_sgl)
f4800d6d 414{
a7a7cbe3
CK		 415 unsigned int alloc_size = nvme_pci_iod_alloc_size(dev,
416 NVME_INT_BYTES(dev), NVME_INT_PAGES,
417 use_sgl);
418
419 return sizeof(struct nvme_iod) + alloc_size;
ac3dd5bd
JA		 420}
421
a4aea562
MB		 422static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
423 unsigned int hctx_idx)
e85248e5 424{
a4aea562 425 struct nvme_dev *dev = data;
147b27e4 426 struct nvme_queue *nvmeq = &dev->queues[0];
a4aea562 427
42483228
KB		 428 WARN_ON(hctx_idx != 0);
429 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
430 WARN_ON(nvmeq->tags);
431
a4aea562 432 hctx->driver_data = nvmeq;
42483228 433 nvmeq->tags = &dev->admin_tagset.tags[0];
a4aea562 434 return 0;
e85248e5
MW		 435}
436
4af0e21c
KB		 437static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
438{
439 struct nvme_queue *nvmeq = hctx->driver_data;
440
441 nvmeq->tags = NULL;
442}
443
a4aea562
MB		 444static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
445 unsigned int hctx_idx)
b60503ba 446{
a4aea562 447 struct nvme_dev *dev = data;
147b27e4 448 struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
a4aea562 449
42483228
KB		 450 if (!nvmeq->tags)
451 nvmeq->tags = &dev->tagset.tags[hctx_idx];
b60503ba 452
42483228 453 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
a4aea562
MB		 454 hctx->driver_data = nvmeq;
455 return 0;
b60503ba
MW		 456}
457
d6296d39
CH		 458static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req,
459 unsigned int hctx_idx, unsigned int numa_node)
b60503ba 460{
d6296d39 461 struct nvme_dev *dev = set->driver_data;
f4800d6d 462 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
0350815a 463 int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0;
147b27e4 464 struct nvme_queue *nvmeq = &dev->queues[queue_idx];
a4aea562
MB		 465
466 BUG_ON(!nvmeq);
f4800d6d 467 iod->nvmeq = nvmeq;
59e29ce6
SG		 468
469 nvme_req(req)->ctrl = &dev->ctrl;
a4aea562
MB		 470 return 0;
471}
472
3b6592f7
JA		 473static int queue_irq_offset(struct nvme_dev *dev)
474{
475 /* if we have more than 1 vec, admin queue offsets us by 1 */
476 if (dev->num_vecs > 1)
477 return 1;
478
479 return 0;
480}
481
dca51e78
CH		 482static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
483{
484 struct nvme_dev *dev = set->driver_data;
3b6592f7
JA		 485 int i, qoff, offset;
486
487 offset = queue_irq_offset(dev);
488 for (i = 0, qoff = 0; i < set->nr_maps; i++) {
489 struct blk_mq_queue_map *map = &set->map[i];
490
491 map->nr_queues = dev->io_queues[i];
492 if (!map->nr_queues) {
e20ba6e1 493 BUG_ON(i == HCTX_TYPE_DEFAULT);
7e849dd9 494 continue;
3b6592f7
JA		 495 }
496
4b04cc6a
JA		 497 /*
498 * The poll queue(s) doesn't have an IRQ (and hence IRQ
499 * affinity), so use the regular blk-mq cpu mapping
500 */
3b6592f7 501 map->queue_offset = qoff;
e20ba6e1 502 if (i != HCTX_TYPE_POLL)
4b04cc6a
JA		 503 blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset);
504 else
505 blk_mq_map_queues(map);
3b6592f7
JA		 506 qoff += map->nr_queues;
507 offset += map->nr_queues;
508 }
509
510 return 0;
dca51e78
CH		 511}
512
04f3eafd
JA		 513/*
514 * Write sq tail if we are asked to, or if the next command would wrap.
515 */
516static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq)
517{
518 if (!write_sq) {
519 u16 next_tail = nvmeq->sq_tail + 1;
520
521 if (next_tail == nvmeq->q_depth)
522 next_tail = 0;
523 if (next_tail != nvmeq->last_sq_tail)
524 return;
525 }
526
527 if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail,
528 nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei))
529 writel(nvmeq->sq_tail, nvmeq->q_db);
530 nvmeq->last_sq_tail = nvmeq->sq_tail;
531}
532
b60503ba 533/**
90ea5ca4 534 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
b60503ba
MW		 535 * @nvmeq: The queue to use
536 * @cmd: The command to send
04f3eafd 537 * @write_sq: whether to write to the SQ doorbell
b60503ba 538 */
04f3eafd
JA		 539static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd,
540 bool write_sq)
b60503ba 541{
90ea5ca4 542 spin_lock(&nvmeq->sq_lock);
0f238ff5 543 memcpy(&nvmeq->sq_cmds[nvmeq->sq_tail], cmd, sizeof(*cmd));
90ea5ca4
CH		 544 if (++nvmeq->sq_tail == nvmeq->q_depth)
545 nvmeq->sq_tail = 0;
04f3eafd
JA		 546 nvme_write_sq_db(nvmeq, write_sq);
547 spin_unlock(&nvmeq->sq_lock);
548}
549
550static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx)
551{
552 struct nvme_queue *nvmeq = hctx->driver_data;
553
554 spin_lock(&nvmeq->sq_lock);
555 if (nvmeq->sq_tail != nvmeq->last_sq_tail)
556 nvme_write_sq_db(nvmeq, true);
90ea5ca4 557 spin_unlock(&nvmeq->sq_lock);
b60503ba
MW		 558}
559
a7a7cbe3 560static void **nvme_pci_iod_list(struct request *req)
b60503ba 561{
f4800d6d 562 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3 563 return (void **)(iod->sg + blk_rq_nr_phys_segments(req));
b60503ba
MW		 564}
565
955b1b5a
MI		 566static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req)
567{
568 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
20469a37 569 int nseg = blk_rq_nr_phys_segments(req);
955b1b5a
MI		 570 unsigned int avg_seg_size;
571
20469a37
KB		 572 if (nseg == 0)
573 return false;
574
575 avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
955b1b5a
MI		 576
577 if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1))))
578 return false;
579 if (!iod->nvmeq->qid)
580 return false;
581 if (!sgl_threshold || avg_seg_size < sgl_threshold)
582 return false;
583 return true;
584}
585
7fe07d14 586static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
b60503ba 587{
f4800d6d 588 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
7fe07d14
CH		 589 enum dma_data_direction dma_dir = rq_data_dir(req) ?
590 DMA_TO_DEVICE : DMA_FROM_DEVICE;
a7a7cbe3
CK		 591 const int last_prp = dev->ctrl.page_size / sizeof(__le64) - 1;
592 dma_addr_t dma_addr = iod->first_dma, next_dma_addr;
eca18b23 593 int i;
eca18b23 594
783b94bd
CH		 595 if (blk_integrity_rq(req)) {
596 dma_unmap_page(dev->dev, iod->meta_dma,
597 rq_integrity_vec(req)->bv_len, dma_dir);
598 }
599
7fe07d14
CH		 600 if (iod->nents) {
601 /* P2PDMA requests do not need to be unmapped */
602 if (!is_pci_p2pdma_page(sg_page(iod->sg)))
603 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
604
7fe07d14
CH		 605 }
606
eca18b23 607 if (iod->npages == 0)
a7a7cbe3
CK		 608 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0],
609 dma_addr);
610
eca18b23 611 for (i = 0; i < iod->npages; i++) {
a7a7cbe3
CK		 612 void *addr = nvme_pci_iod_list(req)[i];
613
614 if (iod->use_sgl) {
615 struct nvme_sgl_desc *sg_list = addr;
616
617 next_dma_addr =
618 le64_to_cpu((sg_list[SGES_PER_PAGE - 1]).addr);
619 } else {
620 __le64 *prp_list = addr;
621
622 next_dma_addr = le64_to_cpu(prp_list[last_prp]);
623 }
624
625 dma_pool_free(dev->prp_page_pool, addr, dma_addr);
626 dma_addr = next_dma_addr;
eca18b23 627 }
ac3dd5bd 628
f4800d6d 629 if (iod->sg != iod->inline_sg)
943e942e 630 mempool_free(iod->sg, dev->iod_mempool);
b4ff9c8d
KB		 631}
632
d0877473
KB		 633static void nvme_print_sgl(struct scatterlist *sgl, int nents)
634{
635 int i;
636 struct scatterlist *sg;
637
638 for_each_sg(sgl, sg, nents, i) {
639 dma_addr_t phys = sg_phys(sg);
640 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
641 "dma_address:%pad dma_length:%d\n",
642 i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
643 sg_dma_len(sg));
644 }
645}
646
a7a7cbe3
CK		 647static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
648 struct request *req, struct nvme_rw_command *cmnd)
ff22b54f 649{
f4800d6d 650 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
99802a7a 651 struct dma_pool *pool;
b131c61d 652 int length = blk_rq_payload_bytes(req);
eca18b23 653 struct scatterlist *sg = iod->sg;
ff22b54f
MW		 654 int dma_len = sg_dma_len(sg);
655 u64 dma_addr = sg_dma_address(sg);
5fd4ce1b 656 u32 page_size = dev->ctrl.page_size;
f137e0f1 657 int offset = dma_addr & (page_size - 1);
e025344c 658 __le64 *prp_list;
a7a7cbe3 659 void **list = nvme_pci_iod_list(req);
e025344c 660 dma_addr_t prp_dma;
eca18b23 661 int nprps, i;
ff22b54f 662
1d090624 663 length -= (page_size - offset);
5228b328
JS		 664 if (length <= 0) {
665 iod->first_dma = 0;
a7a7cbe3 666 goto done;
5228b328 667 }
ff22b54f 668
1d090624 669 dma_len -= (page_size - offset);
ff22b54f 670 if (dma_len) {
1d090624 671 dma_addr += (page_size - offset);
ff22b54f
MW		 672 } else {
673 sg = sg_next(sg);
674 dma_addr = sg_dma_address(sg);
675 dma_len = sg_dma_len(sg);
676 }
677
1d090624 678 if (length <= page_size) {
edd10d33 679 iod->first_dma = dma_addr;
a7a7cbe3 680 goto done;
e025344c
SMM		 681 }
682
1d090624 683 nprps = DIV_ROUND_UP(length, page_size);
99802a7a
MW		 684 if (nprps <= (256 / 8)) {
685 pool = dev->prp_small_pool;
eca18b23 686 iod->npages = 0;
99802a7a
MW		 687 } else {
688 pool = dev->prp_page_pool;
eca18b23 689 iod->npages = 1;
99802a7a
MW		 690 }
691
69d2b571 692 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
b77954cb 693 if (!prp_list) {
edd10d33 694 iod->first_dma = dma_addr;
eca18b23 695 iod->npages = -1;
86eea289 696 return BLK_STS_RESOURCE;
b77954cb 697 }
eca18b23
MW		 698 list[0] = prp_list;
699 iod->first_dma = prp_dma;
e025344c
SMM		 700 i = 0;
701 for (;;) {
1d090624 702 if (i == page_size >> 3) {
e025344c 703 __le64 *old_prp_list = prp_list;
69d2b571 704 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
eca18b23 705 if (!prp_list)
86eea289 706 return BLK_STS_RESOURCE;
eca18b23 707 list[iod->npages++] = prp_list;
7523d834
MW		 708 prp_list[0] = old_prp_list[i - 1];
709 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
710 i = 1;
e025344c
SMM		 711 }
712 prp_list[i++] = cpu_to_le64(dma_addr);
1d090624
KB		 713 dma_len -= page_size;
714 dma_addr += page_size;
715 length -= page_size;
e025344c
SMM		 716 if (length <= 0)
717 break;
718 if (dma_len > 0)
719 continue;
86eea289
KB		 720 if (unlikely(dma_len < 0))
721 goto bad_sgl;
e025344c
SMM		 722 sg = sg_next(sg);
723 dma_addr = sg_dma_address(sg);
724 dma_len = sg_dma_len(sg);
ff22b54f
MW		 725 }
726
a7a7cbe3
CK		 727done:
728 cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
729 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
730
86eea289
KB		 731 return BLK_STS_OK;
732
733 bad_sgl:
d0877473
KB		 734 WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents),
735 "Invalid SGL for payload:%d nents:%d\n",
736 blk_rq_payload_bytes(req), iod->nents);
86eea289 737 return BLK_STS_IOERR;
ff22b54f
MW		 738}
739
a7a7cbe3
CK		 740static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
741 struct scatterlist *sg)
742{
743 sge->addr = cpu_to_le64(sg_dma_address(sg));
744 sge->length = cpu_to_le32(sg_dma_len(sg));
745 sge->type = NVME_SGL_FMT_DATA_DESC << 4;
746}
747
748static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
749 dma_addr_t dma_addr, int entries)
750{
751 sge->addr = cpu_to_le64(dma_addr);
752 if (entries < SGES_PER_PAGE) {
753 sge->length = cpu_to_le32(entries * sizeof(*sge));
754 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
755 } else {
756 sge->length = cpu_to_le32(PAGE_SIZE);
757 sge->type = NVME_SGL_FMT_SEG_DESC << 4;
758 }
759}
760
761static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
b0f2853b 762 struct request *req, struct nvme_rw_command *cmd, int entries)
a7a7cbe3
CK		 763{
764 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3
CK		 765 struct dma_pool *pool;
766 struct nvme_sgl_desc *sg_list;
767 struct scatterlist *sg = iod->sg;
a7a7cbe3 768 dma_addr_t sgl_dma;
b0f2853b 769 int i = 0;
a7a7cbe3 770
a7a7cbe3
CK		 771 /* setting the transfer type as SGL */
772 cmd->flags = NVME_CMD_SGL_METABUF;
773
b0f2853b 774 if (entries == 1) {
a7a7cbe3
CK		 775 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
776 return BLK_STS_OK;
777 }
778
779 if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
780 pool = dev->prp_small_pool;
781 iod->npages = 0;
782 } else {
783 pool = dev->prp_page_pool;
784 iod->npages = 1;
785 }
786
787 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
788 if (!sg_list) {
789 iod->npages = -1;
790 return BLK_STS_RESOURCE;
791 }
792
793 nvme_pci_iod_list(req)[0] = sg_list;
794 iod->first_dma = sgl_dma;
795
796 nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
797
798 do {
799 if (i == SGES_PER_PAGE) {
800 struct nvme_sgl_desc *old_sg_desc = sg_list;
801 struct nvme_sgl_desc *link = &old_sg_desc[i - 1];
802
803 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
804 if (!sg_list)
805 return BLK_STS_RESOURCE;
806
807 i = 0;
808 nvme_pci_iod_list(req)[iod->npages++] = sg_list;
809 sg_list[i++] = *link;
810 nvme_pci_sgl_set_seg(link, sgl_dma, entries);
811 }
812
813 nvme_pci_sgl_set_data(&sg_list[i++], sg);
a7a7cbe3 814 sg = sg_next(sg);
b0f2853b 815 } while (--entries > 0);
a7a7cbe3 816
a7a7cbe3
CK		 817 return BLK_STS_OK;
818}
819
fc17b653 820static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
b131c61d 821 struct nvme_command *cmnd)
d29ec824 822{
f4800d6d 823 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
ba1ca37e
CH		 824 struct request_queue *q = req->q;
825 enum dma_data_direction dma_dir = rq_data_dir(req) ?
826 DMA_TO_DEVICE : DMA_FROM_DEVICE;
fc17b653 827 blk_status_t ret = BLK_STS_IOERR;
b0f2853b 828 int nr_mapped;
d29ec824 829
9b048119
CH		 830 if (blk_rq_payload_bytes(req) > NVME_INT_BYTES(dev) ||
831 blk_rq_nr_phys_segments(req) > NVME_INT_PAGES) {
832 iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC);
833 if (!iod->sg)
834 return BLK_STS_RESOURCE;
835 } else {
836 iod->sg = iod->inline_sg;
837 }
838
839 iod->use_sgl = nvme_pci_use_sgls(dev, req);
840
f9d03f96 841 sg_init_table(iod->sg, blk_rq_nr_phys_segments(req));
ba1ca37e
CH		 842 iod->nents = blk_rq_map_sg(q, req, iod->sg);
843 if (!iod->nents)
844 goto out;
d29ec824 845
fc17b653 846 ret = BLK_STS_RESOURCE;
e0596ab2
LG		 847
848 if (is_pci_p2pdma_page(sg_page(iod->sg)))
849 nr_mapped = pci_p2pdma_map_sg(dev->dev, iod->sg, iod->nents,
850 dma_dir);
851 else
852 nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents,
853 dma_dir, DMA_ATTR_NO_WARN);
b0f2853b 854 if (!nr_mapped)
ba1ca37e 855 goto out;
d29ec824 856
955b1b5a 857 if (iod->use_sgl)
b0f2853b 858 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped);
a7a7cbe3
CK		 859 else
860 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
861
86eea289 862 if (ret != BLK_STS_OK)
7fe07d14 863 goto out;
0e5e4f0e 864
fc17b653 865 ret = BLK_STS_IOERR;
ba1ca37e 866 if (blk_integrity_rq(req)) {
783b94bd
CH		 867 iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req),
868 dma_dir, 0);
869 if (dma_mapping_error(dev->dev, iod->meta_dma))
7fe07d14 870 goto out;
783b94bd 871 cmnd->rw.metadata = cpu_to_le64(iod->meta_dma);
3045c0d0
CK		 872 }
873
fc17b653 874 return BLK_STS_OK;
00df5cb4 875
ba1ca37e 876out:
7fe07d14 877 nvme_unmap_data(dev, req);
ba1ca37e 878 return ret;
00df5cb4
MW		 879}
880
d29ec824
CH		 881/*
882 * NOTE: ns is NULL when called on the admin queue.
883 */
fc17b653 884static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
a4aea562 885 const struct blk_mq_queue_data *bd)
edd10d33 886{
a4aea562
MB		 887 struct nvme_ns *ns = hctx->queue->queuedata;
888 struct nvme_queue *nvmeq = hctx->driver_data;
d29ec824 889 struct nvme_dev *dev = nvmeq->dev;
a4aea562 890 struct request *req = bd->rq;
9b048119 891 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
ba1ca37e 892 struct nvme_command cmnd;
ebe6d874 893 blk_status_t ret;
e1e5e564 894
9b048119
CH		 895 iod->aborted = 0;
896 iod->npages = -1;
897 iod->nents = 0;
898
d1f06f4a
JA		 899 /*
900 * We should not need to do this, but we're still using this to
901 * ensure we can drain requests on a dying queue.
902 */
4e224106 903 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
d1f06f4a
JA		 904 return BLK_STS_IOERR;
905
f9d03f96 906 ret = nvme_setup_cmd(ns, req, &cmnd);
fc17b653 907 if (ret)
f4800d6d 908 return ret;
a4aea562 909
fc17b653 910 if (blk_rq_nr_phys_segments(req)) {
b131c61d 911 ret = nvme_map_data(dev, req, &cmnd);
fc17b653 912 if (ret)
9b048119 913 goto out_free_cmd;
fc17b653 914 }
a4aea562 915
aae239e1 916 blk_mq_start_request(req);
04f3eafd 917 nvme_submit_cmd(nvmeq, &cmnd, bd->last);
fc17b653 918 return BLK_STS_OK;
f9d03f96
CH		 919out_free_cmd:
920 nvme_cleanup_cmd(req);
ba1ca37e 921 return ret;
b60503ba 922}
e1e5e564 923
77f02a7a 924static void nvme_pci_complete_rq(struct request *req)
eee417b0 925{
f4800d6d 926 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a4aea562 927
915f04c9 928 nvme_cleanup_cmd(req);
b15c592d
CH		 929 if (blk_rq_nr_phys_segments(req))
930 nvme_unmap_data(iod->nvmeq->dev, req);
77f02a7a 931 nvme_complete_rq(req);
b60503ba
MW		 932}
933
d783e0bd 934/* We read the CQE phase first to check if the rest of the entry is valid */
750dde44 935static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq)
d783e0bd 936{
750dde44
CH		 937 return (le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) ==
938 nvmeq->cq_phase;
d783e0bd
MR		 939}
940
eb281c82 941static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
b60503ba 942{
eb281c82 943 u16 head = nvmeq->cq_head;
adf68f21 944
397c699f
KB		 945 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
946 nvmeq->dbbuf_cq_ei))
947 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
eb281c82 948}
aae239e1 949
5cb525c8 950static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx)
83a12fb7 951{
5cb525c8 952 volatile struct nvme_completion *cqe = &nvmeq->cqes[idx];
83a12fb7 953 struct request *req;
adf68f21 954
83a12fb7
SG		 955 if (unlikely(cqe->command_id >= nvmeq->q_depth)) {
956 dev_warn(nvmeq->dev->ctrl.device,
957 "invalid id %d completed on queue %d\n",
958 cqe->command_id, le16_to_cpu(cqe->sq_id));
959 return;
b60503ba
MW		 960 }
961
83a12fb7
SG		 962 /*
963 * AEN requests are special as they don't time out and can
964 * survive any kind of queue freeze and often don't respond to
965 * aborts. We don't even bother to allocate a struct request
966 * for them but rather special case them here.
967 */
968 if (unlikely(nvmeq->qid == 0 &&
38dabe21 969 cqe->command_id >= NVME_AQ_BLK_MQ_DEPTH)) {
83a12fb7
SG		 970 nvme_complete_async_event(&nvmeq->dev->ctrl,
971 cqe->status, &cqe->result);
a0fa9647 972 return;
83a12fb7 973 }
b60503ba 974
83a12fb7 975 req = blk_mq_tag_to_rq(*nvmeq->tags, cqe->command_id);
604c01d5 976 trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail);
83a12fb7
SG		 977 nvme_end_request(req, cqe->status, cqe->result);
978}
b60503ba 979
5cb525c8 980static void nvme_complete_cqes(struct nvme_queue *nvmeq, u16 start, u16 end)
b60503ba 981{
5cb525c8
JA		 982 while (start != end) {
983 nvme_handle_cqe(nvmeq, start);
984 if (++start == nvmeq->q_depth)
985 start = 0;
986 }
987}
adf68f21 988
5cb525c8
JA		 989static inline void nvme_update_cq_head(struct nvme_queue *nvmeq)
990{
dcca1662 991 if (nvmeq->cq_head == nvmeq->q_depth - 1) {
5cb525c8
JA		 992 nvmeq->cq_head = 0;
993 nvmeq->cq_phase = !nvmeq->cq_phase;
dcca1662
HY		 994 } else {
995 nvmeq->cq_head++;
b60503ba 996 }
a0fa9647
JA		 997}
998
1052b8ac
JA		 999static inline int nvme_process_cq(struct nvme_queue *nvmeq, u16 *start,
1000 u16 *end, unsigned int tag)
a0fa9647 1001{
1052b8ac 1002 int found = 0;
b60503ba 1003
5cb525c8 1004 *start = nvmeq->cq_head;
1052b8ac
JA		 1005 while (nvme_cqe_pending(nvmeq)) {
1006 if (tag == -1U || nvmeq->cqes[nvmeq->cq_head].command_id == tag)
1007 found++;
5cb525c8 1008 nvme_update_cq_head(nvmeq);
920d13a8 1009 }
5cb525c8 1010 *end = nvmeq->cq_head;
eb281c82 1011
5cb525c8 1012 if (*start != *end)
920d13a8 1013 nvme_ring_cq_doorbell(nvmeq);
5cb525c8 1014 return found;
b60503ba
MW		 1015}
1016
1017static irqreturn_t nvme_irq(int irq, void *data)
58ffacb5 1018{
58ffacb5 1019 struct nvme_queue *nvmeq = data;
68fa9dbe 1020 irqreturn_t ret = IRQ_NONE;
5cb525c8
JA		 1021 u16 start, end;
1022
3a7afd8e
CH		 1023 /*
1024 * The rmb/wmb pair ensures we see all updates from a previous run of
1025 * the irq handler, even if that was on another CPU.
1026 */
1027 rmb();
68fa9dbe
JA		 1028 if (nvmeq->cq_head != nvmeq->last_cq_head)
1029 ret = IRQ_HANDLED;
5cb525c8 1030 nvme_process_cq(nvmeq, &start, &end, -1);
68fa9dbe 1031 nvmeq->last_cq_head = nvmeq->cq_head;
3a7afd8e 1032 wmb();
5cb525c8 1033
68fa9dbe
JA		 1034 if (start != end) {
1035 nvme_complete_cqes(nvmeq, start, end);
1036 return IRQ_HANDLED;
1037 }
1038
1039 return ret;
58ffacb5
MW		 1040}
1041
1042static irqreturn_t nvme_irq_check(int irq, void *data)
1043{
1044 struct nvme_queue *nvmeq = data;
750dde44 1045 if (nvme_cqe_pending(nvmeq))
d783e0bd
MR		 1046 return IRQ_WAKE_THREAD;
1047 return IRQ_NONE;
58ffacb5
MW		 1048}
1049
0b2a8a9f
CH		 1050/*
1051 * Poll for completions any queue, including those not dedicated to polling.
1052 * Can be called from any context.
1053 */
1054static int nvme_poll_irqdisable(struct nvme_queue *nvmeq, unsigned int tag)
a0fa9647 1055{
3a7afd8e 1056 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
5cb525c8 1057 u16 start, end;
1052b8ac 1058 int found;
a0fa9647 1059
3a7afd8e
CH		 1060 /*
1061 * For a poll queue we need to protect against the polling thread
1062 * using the CQ lock. For normal interrupt driven threads we have
1063 * to disable the interrupt to avoid racing with it.
1064 */
7c349dde 1065 if (test_bit(NVMEQ_POLLED, &nvmeq->flags)) {
3a7afd8e 1066 spin_lock(&nvmeq->cq_poll_lock);
91a509f8 1067 found = nvme_process_cq(nvmeq, &start, &end, tag);
3a7afd8e 1068 spin_unlock(&nvmeq->cq_poll_lock);
91a509f8
CH		 1069 } else {
1070 disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1071 found = nvme_process_cq(nvmeq, &start, &end, tag);
3a7afd8e 1072 enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
91a509f8 1073 }
442e19b7 1074
5cb525c8 1075 nvme_complete_cqes(nvmeq, start, end);
442e19b7 1076 return found;
a0fa9647
JA		 1077}
1078
9743139c 1079static int nvme_poll(struct blk_mq_hw_ctx *hctx)
dabcefab
JA		 1080{
1081 struct nvme_queue *nvmeq = hctx->driver_data;
1082 u16 start, end;
1083 bool found;
1084
1085 if (!nvme_cqe_pending(nvmeq))
1086 return 0;
1087
3a7afd8e 1088 spin_lock(&nvmeq->cq_poll_lock);
9743139c 1089 found = nvme_process_cq(nvmeq, &start, &end, -1);
3a7afd8e 1090 spin_unlock(&nvmeq->cq_poll_lock);
dabcefab
JA		 1091
1092 nvme_complete_cqes(nvmeq, start, end);
1093 return found;
1094}
1095
ad22c355 1096static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
b60503ba 1097{
f866fc42 1098 struct nvme_dev *dev = to_nvme_dev(ctrl);
147b27e4 1099 struct nvme_queue *nvmeq = &dev->queues[0];
a4aea562 1100 struct nvme_command c;
b60503ba 1101
a4aea562
MB		 1102 memset(&c, 0, sizeof(c));
1103 c.common.opcode = nvme_admin_async_event;
ad22c355 1104 c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
04f3eafd 1105 nvme_submit_cmd(nvmeq, &c, true);
f705f837
CH		 1106}
1107
b60503ba 1108static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
f705f837 1109{
b60503ba
MW		 1110 struct nvme_command c;
1111
1112 memset(&c, 0, sizeof(c));
1113 c.delete_queue.opcode = opcode;
1114 c.delete_queue.qid = cpu_to_le16(id);
1115
1c63dc66 1116 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1117}
1118
b60503ba 1119static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
a8e3e0bb 1120 struct nvme_queue *nvmeq, s16 vector)
b60503ba 1121{
b60503ba 1122 struct nvme_command c;
4b04cc6a
JA		 1123 int flags = NVME_QUEUE_PHYS_CONTIG;
1124
7c349dde 1125 if (!test_bit(NVMEQ_POLLED, &nvmeq->flags))
4b04cc6a 1126 flags |= NVME_CQ_IRQ_ENABLED;
b60503ba 1127
d29ec824 1128 /*
16772ae6 1129 * Note: we (ab)use the fact that the prp fields survive if no data
d29ec824
CH		 1130 * is attached to the request.
1131 */
b60503ba
MW		 1132 memset(&c, 0, sizeof(c));
1133 c.create_cq.opcode = nvme_admin_create_cq;
1134 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1135 c.create_cq.cqid = cpu_to_le16(qid);
1136 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1137 c.create_cq.cq_flags = cpu_to_le16(flags);
7c349dde 1138 c.create_cq.irq_vector = cpu_to_le16(vector);
b60503ba 1139
1c63dc66 1140 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1141}
1142
1143static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1144 struct nvme_queue *nvmeq)
1145{
9abd68ef 1146 struct nvme_ctrl *ctrl = &dev->ctrl;
b60503ba 1147 struct nvme_command c;
81c1cd98 1148 int flags = NVME_QUEUE_PHYS_CONTIG;
b60503ba 1149
9abd68ef
JA		 1150 /*
1151 * Some drives have a bug that auto-enables WRRU if MEDIUM isn't
1152 * set. Since URGENT priority is zeroes, it makes all queues
1153 * URGENT.
1154 */
1155 if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ)
1156 flags |= NVME_SQ_PRIO_MEDIUM;
1157
d29ec824 1158 /*
16772ae6 1159 * Note: we (ab)use the fact that the prp fields survive if no data
d29ec824
CH		 1160 * is attached to the request.
1161 */
b60503ba
MW		 1162 memset(&c, 0, sizeof(c));
1163 c.create_sq.opcode = nvme_admin_create_sq;
1164 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1165 c.create_sq.sqid = cpu_to_le16(qid);
1166 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1167 c.create_sq.sq_flags = cpu_to_le16(flags);
1168 c.create_sq.cqid = cpu_to_le16(qid);
1169
1c63dc66 1170 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1171}
1172
1173static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1174{
1175 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1176}
1177
1178static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1179{
1180 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1181}
1182
2a842aca 1183static void abort_endio(struct request *req, blk_status_t error)
bc5fc7e4 1184{
f4800d6d
CH		 1185 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1186 struct nvme_queue *nvmeq = iod->nvmeq;
e44ac588 1187
27fa9bc5
CH		 1188 dev_warn(nvmeq->dev->ctrl.device,
1189 "Abort status: 0x%x", nvme_req(req)->status);
e7a2a87d 1190 atomic_inc(&nvmeq->dev->ctrl.abort_limit);
e7a2a87d 1191 blk_mq_free_request(req);
bc5fc7e4
MW		 1192}
1193
b2a0eb1a
KB		 1194static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1195{
1196
1197 /* If true, indicates loss of adapter communication, possibly by a
1198 * NVMe Subsystem reset.
1199 */
1200 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1201
ad70062c
JW		 1202 /* If there is a reset/reinit ongoing, we shouldn't reset again. */
1203 switch (dev->ctrl.state) {
1204 case NVME_CTRL_RESETTING:
ad6a0a52 1205 case NVME_CTRL_CONNECTING:
b2a0eb1a 1206 return false;
ad70062c
JW		 1207 default:
1208 break;
1209 }
b2a0eb1a
KB		 1210
1211 /* We shouldn't reset unless the controller is on fatal error state
1212 * _or_ if we lost the communication with it.
1213 */
1214 if (!(csts & NVME_CSTS_CFS) && !nssro)
1215 return false;
1216
b2a0eb1a
KB		 1217 return true;
1218}
1219
1220static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1221{
1222 /* Read a config register to help see what died. */
1223 u16 pci_status;
1224 int result;
1225
1226 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1227 &pci_status);
1228 if (result == PCIBIOS_SUCCESSFUL)
1229 dev_warn(dev->ctrl.device,
1230 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1231 csts, pci_status);
1232 else
1233 dev_warn(dev->ctrl.device,
1234 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1235 csts, result);
1236}
1237
31c7c7d2 1238static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
c30341dc 1239{
f4800d6d
CH		 1240 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1241 struct nvme_queue *nvmeq = iod->nvmeq;
c30341dc 1242 struct nvme_dev *dev = nvmeq->dev;
a4aea562 1243 struct request *abort_req;
a4aea562 1244 struct nvme_command cmd;
b2a0eb1a
KB		 1245 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1246
651438bb
WX		 1247 /* If PCI error recovery process is happening, we cannot reset or
1248 * the recovery mechanism will surely fail.
1249 */
1250 mb();
1251 if (pci_channel_offline(to_pci_dev(dev->dev)))
1252 return BLK_EH_RESET_TIMER;
1253
b2a0eb1a
KB		 1254 /*
1255 * Reset immediately if the controller is failed
1256 */
1257 if (nvme_should_reset(dev, csts)) {
1258 nvme_warn_reset(dev, csts);
1259 nvme_dev_disable(dev, false);
d86c4d8e 1260 nvme_reset_ctrl(&dev->ctrl);
db8c48e4 1261 return BLK_EH_DONE;
b2a0eb1a 1262 }
c30341dc 1263
7776db1c
KB		 1264 /*
1265 * Did we miss an interrupt?
1266 */
0b2a8a9f 1267 if (nvme_poll_irqdisable(nvmeq, req->tag)) {
7776db1c
KB		 1268 dev_warn(dev->ctrl.device,
1269 "I/O %d QID %d timeout, completion polled\n",
1270 req->tag, nvmeq->qid);
db8c48e4 1271 return BLK_EH_DONE;
7776db1c
KB		 1272 }
1273
31c7c7d2 1274 /*
fd634f41
CH		 1275 * Shutdown immediately if controller times out while starting. The
1276 * reset work will see the pci device disabled when it gets the forced
1277 * cancellation error. All outstanding requests are completed on
db8c48e4 1278 * shutdown, so we return BLK_EH_DONE.
fd634f41 1279 */
4244140d
KB		 1280 switch (dev->ctrl.state) {
1281 case NVME_CTRL_CONNECTING:
1282 case NVME_CTRL_RESETTING:
b9cac43c 1283 dev_warn_ratelimited(dev->ctrl.device,
fd634f41
CH		 1284 "I/O %d QID %d timeout, disable controller\n",
1285 req->tag, nvmeq->qid);
a5cdb68c 1286 nvme_dev_disable(dev, false);
27fa9bc5 1287 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
db8c48e4 1288 return BLK_EH_DONE;
4244140d
KB		 1289 default:
1290 break;
c30341dc
KB		 1291 }
1292
fd634f41
CH		 1293 /*
1294 * Shutdown the controller immediately and schedule a reset if the
1295 * command was already aborted once before and still hasn't been
1296 * returned to the driver, or if this is the admin queue.
31c7c7d2 1297 */
f4800d6d 1298 if (!nvmeq->qid || iod->aborted) {
1b3c47c1 1299 dev_warn(dev->ctrl.device,
e1569a16
KB		 1300 "I/O %d QID %d timeout, reset controller\n",
1301 req->tag, nvmeq->qid);
a5cdb68c 1302 nvme_dev_disable(dev, false);
d86c4d8e 1303 nvme_reset_ctrl(&dev->ctrl);
c30341dc 1304
27fa9bc5 1305 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
db8c48e4 1306 return BLK_EH_DONE;
c30341dc 1307 }
c30341dc 1308
e7a2a87d 1309 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
6bf25d16 1310 atomic_inc(&dev->ctrl.abort_limit);
31c7c7d2 1311 return BLK_EH_RESET_TIMER;
6bf25d16 1312 }
7bf7d778 1313 iod->aborted = 1;
a4aea562 1314
c30341dc
KB		 1315 memset(&cmd, 0, sizeof(cmd));
1316 cmd.abort.opcode = nvme_admin_abort_cmd;
a4aea562 1317 cmd.abort.cid = req->tag;
c30341dc 1318 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
c30341dc 1319
1b3c47c1
SG		 1320 dev_warn(nvmeq->dev->ctrl.device,
1321 "I/O %d QID %d timeout, aborting\n",
1322 req->tag, nvmeq->qid);
e7a2a87d
CH		 1323
1324 abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
eb71f435 1325 BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
e7a2a87d
CH		 1326 if (IS_ERR(abort_req)) {
1327 atomic_inc(&dev->ctrl.abort_limit);
1328 return BLK_EH_RESET_TIMER;
1329 }
1330
1331 abort_req->timeout = ADMIN_TIMEOUT;
1332 abort_req->end_io_data = NULL;
1333 blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio);
c30341dc 1334
31c7c7d2
CH		 1335 /*
1336 * The aborted req will be completed on receiving the abort req.
1337 * We enable the timer again. If hit twice, it'll cause a device reset,
1338 * as the device then is in a faulty state.
1339 */
1340 return BLK_EH_RESET_TIMER;
c30341dc
KB		 1341}
1342
a4aea562
MB		 1343static void nvme_free_queue(struct nvme_queue *nvmeq)
1344{
88a041f4 1345 dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq->q_depth),
9e866774 1346 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
63223078
CH		 1347 if (!nvmeq->sq_cmds)
1348 return;
0f238ff5 1349
63223078 1350 if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) {
88a041f4 1351 pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev),
63223078
CH		 1352 nvmeq->sq_cmds, SQ_SIZE(nvmeq->q_depth));
1353 } else {
88a041f4 1354 dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq->q_depth),
63223078 1355 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
0f238ff5 1356 }
9e866774
MW		 1357}
1358
a1a5ef99 1359static void nvme_free_queues(struct nvme_dev *dev, int lowest)
22404274
KB		 1360{
1361 int i;
1362
d858e5f0 1363 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
d858e5f0 1364 dev->ctrl.queue_count--;
147b27e4 1365 nvme_free_queue(&dev->queues[i]);
121c7ad4 1366 }
22404274
KB		 1367}
1368
4d115420
KB		 1369/**
1370 * nvme_suspend_queue - put queue into suspended state
40581d1a 1371 * @nvmeq: queue to suspend
4d115420
KB		 1372 */
1373static int nvme_suspend_queue(struct nvme_queue *nvmeq)
b60503ba 1374{
4e224106 1375 if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags))
2b25d981 1376 return 1;
a09115b2 1377
4e224106 1378 /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */
d1f06f4a 1379 mb();
a09115b2 1380
4e224106 1381 nvmeq->dev->online_queues--;
1c63dc66 1382 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
c81545f9 1383 blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q);
7c349dde
KB		 1384 if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags))
1385 pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq);
4d115420
KB		 1386 return 0;
1387}
b60503ba 1388
8fae268b
KB		 1389static void nvme_suspend_io_queues(struct nvme_dev *dev)
1390{
1391 int i;
1392
1393 for (i = dev->ctrl.queue_count - 1; i > 0; i--)
1394 nvme_suspend_queue(&dev->queues[i]);
1395}
1396
a5cdb68c 1397static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
4d115420 1398{
147b27e4 1399 struct nvme_queue *nvmeq = &dev->queues[0];
4d115420 1400
a5cdb68c
KB		 1401 if (shutdown)
1402 nvme_shutdown_ctrl(&dev->ctrl);
1403 else
20d0dfe6 1404 nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap);
07836e65 1405
0b2a8a9f 1406 nvme_poll_irqdisable(nvmeq, -1);
b60503ba
MW		 1407}
1408
8ffaadf7
JD		 1409static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1410 int entry_size)
1411{
1412 int q_depth = dev->q_depth;
5fd4ce1b
CH		 1413 unsigned q_size_aligned = roundup(q_depth * entry_size,
1414 dev->ctrl.page_size);
8ffaadf7
JD		 1415
1416 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
c45f5c99 1417 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
5fd4ce1b 1418 mem_per_q = round_down(mem_per_q, dev->ctrl.page_size);
c45f5c99 1419 q_depth = div_u64(mem_per_q, entry_size);
8ffaadf7
JD		 1420
1421 /*
1422 * Ensure the reduced q_depth is above some threshold where it
1423 * would be better to map queues in system memory with the
1424 * original depth
1425 */
1426 if (q_depth < 64)
1427 return -ENOMEM;
1428 }
1429
1430 return q_depth;
1431}
1432
1433static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1434 int qid, int depth)
1435{
0f238ff5
LG		 1436 struct pci_dev *pdev = to_pci_dev(dev->dev);
1437
1438 if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
1439 nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(depth));
1440 nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev,
1441 nvmeq->sq_cmds);
63223078
CH		 1442 if (nvmeq->sq_dma_addr) {
1443 set_bit(NVMEQ_SQ_CMB, &nvmeq->flags);
1444 return 0;
1445 }
0f238ff5 1446 }
8ffaadf7 1447
63223078
CH		 1448 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
1449 &nvmeq->sq_dma_addr, GFP_KERNEL);
815c6704
KB		 1450 if (!nvmeq->sq_cmds)
1451 return -ENOMEM;
8ffaadf7
JD		 1452 return 0;
1453}
1454
a6ff7262 1455static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
b60503ba 1456{
147b27e4 1457 struct nvme_queue *nvmeq = &dev->queues[qid];
b60503ba 1458
62314e40
KB		 1459 if (dev->ctrl.queue_count > qid)
1460 return 0;
b60503ba 1461
750afb08
LC		 1462 nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(depth),
1463 &nvmeq->cq_dma_addr, GFP_KERNEL);
b60503ba
MW		 1464 if (!nvmeq->cqes)
1465 goto free_nvmeq;
b60503ba 1466
8ffaadf7 1467 if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth))
b60503ba
MW		 1468 goto free_cqdma;
1469
091b6092 1470 nvmeq->dev = dev;
1ab0cd69 1471 spin_lock_init(&nvmeq->sq_lock);
3a7afd8e 1472 spin_lock_init(&nvmeq->cq_poll_lock);
b60503ba 1473 nvmeq->cq_head = 0;
82123460 1474 nvmeq->cq_phase = 1;
b80d5ccc 1475 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
b60503ba 1476 nvmeq->q_depth = depth;
c30341dc 1477 nvmeq->qid = qid;
d858e5f0 1478 dev->ctrl.queue_count++;
36a7e993 1479
147b27e4 1480 return 0;
b60503ba
MW		 1481
1482 free_cqdma:
e75ec752 1483 dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes,
b60503ba
MW		 1484 nvmeq->cq_dma_addr);
1485 free_nvmeq:
147b27e4 1486 return -ENOMEM;
b60503ba
MW		 1487}
1488
dca51e78 1489static int queue_request_irq(struct nvme_queue *nvmeq)
3001082c 1490{
0ff199cb
CH		 1491 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1492 int nr = nvmeq->dev->ctrl.instance;
1493
1494 if (use_threaded_interrupts) {
1495 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1496 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1497 } else {
1498 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1499 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1500 }
3001082c
MW		 1501}
1502
22404274 1503static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
b60503ba 1504{
22404274 1505 struct nvme_dev *dev = nvmeq->dev;
b60503ba 1506
22404274 1507 nvmeq->sq_tail = 0;
04f3eafd 1508 nvmeq->last_sq_tail = 0;
22404274
KB		 1509 nvmeq->cq_head = 0;
1510 nvmeq->cq_phase = 1;
b80d5ccc 1511 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
22404274 1512 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
f9f38e33 1513 nvme_dbbuf_init(dev, nvmeq, qid);
42f61420 1514 dev->online_queues++;
3a7afd8e 1515 wmb(); /* ensure the first interrupt sees the initialization */
22404274
KB		 1516}
1517
4b04cc6a 1518static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled)
22404274
KB		 1519{
1520 struct nvme_dev *dev = nvmeq->dev;
1521 int result;
7c349dde 1522 u16 vector = 0;
3f85d50b 1523
d1ed6aa1
CH		 1524 clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
1525
22b55601
KB		 1526 /*
1527 * A queue's vector matches the queue identifier unless the controller
1528 * has only one vector available.
1529 */
4b04cc6a
JA		 1530 if (!polled)
1531 vector = dev->num_vecs == 1 ? 0 : qid;
1532 else
7c349dde 1533 set_bit(NVMEQ_POLLED, &nvmeq->flags);
4b04cc6a 1534
a8e3e0bb 1535 result = adapter_alloc_cq(dev, qid, nvmeq, vector);
ded45505
KB		 1536 if (result)
1537 return result;
b60503ba
MW		 1538
1539 result = adapter_alloc_sq(dev, qid, nvmeq);
1540 if (result < 0)
ded45505
KB		 1541 return result;
1542 else if (result)
b60503ba
MW		 1543 goto release_cq;
1544
a8e3e0bb 1545 nvmeq->cq_vector = vector;
161b8be2 1546 nvme_init_queue(nvmeq, qid);
4b04cc6a 1547
7c349dde
KB		 1548 if (!polled) {
1549 nvmeq->cq_vector = vector;
4b04cc6a
JA		 1550 result = queue_request_irq(nvmeq);
1551 if (result < 0)
1552 goto release_sq;
1553 }
b60503ba 1554
4e224106 1555 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
22404274 1556 return result;
b60503ba 1557
a8e3e0bb 1558release_sq:
f25a2dfc 1559 dev->online_queues--;
b60503ba 1560 adapter_delete_sq(dev, qid);
a8e3e0bb 1561release_cq:
b60503ba 1562 adapter_delete_cq(dev, qid);
22404274 1563 return result;
b60503ba
MW		 1564}
1565
f363b089 1566static const struct blk_mq_ops nvme_mq_admin_ops = {
d29ec824 1567 .queue_rq = nvme_queue_rq,
77f02a7a 1568 .complete = nvme_pci_complete_rq,
a4aea562 1569 .init_hctx = nvme_admin_init_hctx,
4af0e21c 1570 .exit_hctx = nvme_admin_exit_hctx,
0350815a 1571 .init_request = nvme_init_request,
a4aea562
MB		 1572 .timeout = nvme_timeout,
1573};
1574
f363b089 1575static const struct blk_mq_ops nvme_mq_ops = {
376f7ef8
CH		 1576 .queue_rq = nvme_queue_rq,
1577 .complete = nvme_pci_complete_rq,
1578 .commit_rqs = nvme_commit_rqs,
1579 .init_hctx = nvme_init_hctx,
1580 .init_request = nvme_init_request,
1581 .map_queues = nvme_pci_map_queues,
1582 .timeout = nvme_timeout,
1583 .poll = nvme_poll,
dabcefab
JA		 1584};
1585
ea191d2f
KB		 1586static void nvme_dev_remove_admin(struct nvme_dev *dev)
1587{
1c63dc66 1588 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
69d9a99c
KB		 1589 /*
1590 * If the controller was reset during removal, it's possible
1591 * user requests may be waiting on a stopped queue. Start the
1592 * queue to flush these to completion.
1593 */
c81545f9 1594 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1c63dc66 1595 blk_cleanup_queue(dev->ctrl.admin_q);
ea191d2f
KB		 1596 blk_mq_free_tag_set(&dev->admin_tagset);
1597 }
1598}
1599
a4aea562
MB		 1600static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1601{
1c63dc66 1602 if (!dev->ctrl.admin_q) {
a4aea562
MB		 1603 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1604 dev->admin_tagset.nr_hw_queues = 1;
e3e9d50c 1605
38dabe21 1606 dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH;
a4aea562 1607 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
e75ec752 1608 dev->admin_tagset.numa_node = dev_to_node(dev->dev);
a7a7cbe3 1609 dev->admin_tagset.cmd_size = nvme_pci_cmd_size(dev, false);
d3484991 1610 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED;
a4aea562
MB		 1611 dev->admin_tagset.driver_data = dev;
1612
1613 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1614 return -ENOMEM;
34b6c231 1615 dev->ctrl.admin_tagset = &dev->admin_tagset;
a4aea562 1616
1c63dc66
CH		 1617 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1618 if (IS_ERR(dev->ctrl.admin_q)) {
a4aea562
MB		 1619 blk_mq_free_tag_set(&dev->admin_tagset);
1620 return -ENOMEM;
1621 }
1c63dc66 1622 if (!blk_get_queue(dev->ctrl.admin_q)) {
ea191d2f 1623 nvme_dev_remove_admin(dev);
1c63dc66 1624 dev->ctrl.admin_q = NULL;
ea191d2f
KB		 1625 return -ENODEV;
1626 }
0fb59cbc 1627 } else
c81545f9 1628 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
a4aea562
MB		 1629
1630 return 0;
1631}
1632
97f6ef64
XY		 1633static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1634{
1635 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1636}
1637
1638static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1639{
1640 struct pci_dev *pdev = to_pci_dev(dev->dev);
1641
1642 if (size <= dev->bar_mapped_size)
1643 return 0;
1644 if (size > pci_resource_len(pdev, 0))
1645 return -ENOMEM;
1646 if (dev->bar)
1647 iounmap(dev->bar);
1648 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1649 if (!dev->bar) {
1650 dev->bar_mapped_size = 0;
1651 return -ENOMEM;
1652 }
1653 dev->bar_mapped_size = size;
1654 dev->dbs = dev->bar + NVME_REG_DBS;
1655
1656 return 0;
1657}
1658
01ad0990 1659static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
b60503ba 1660{
ba47e386 1661 int result;
b60503ba
MW		 1662 u32 aqa;
1663 struct nvme_queue *nvmeq;
1664
97f6ef64
XY		 1665 result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1666 if (result < 0)
1667 return result;
1668
8ef2074d 1669 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
20d0dfe6 1670 NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
dfbac8c7 1671
7a67cbea
CH		 1672 if (dev->subsystem &&
1673 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1674 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
dfbac8c7 1675
20d0dfe6 1676 result = nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap);
ba47e386
MW		 1677 if (result < 0)
1678 return result;
b60503ba 1679
a6ff7262 1680 result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
147b27e4
SG		 1681 if (result)
1682 return result;
b60503ba 1683
147b27e4 1684 nvmeq = &dev->queues[0];
b60503ba
MW		 1685 aqa = nvmeq->q_depth - 1;
1686 aqa |= aqa << 16;
1687
7a67cbea
CH		 1688 writel(aqa, dev->bar + NVME_REG_AQA);
1689 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1690 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
b60503ba 1691
20d0dfe6 1692 result = nvme_enable_ctrl(&dev->ctrl, dev->ctrl.cap);
025c557a 1693 if (result)
d4875622 1694 return result;
a4aea562 1695
2b25d981 1696 nvmeq->cq_vector = 0;
161b8be2 1697 nvme_init_queue(nvmeq, 0);
dca51e78 1698 result = queue_request_irq(nvmeq);
758dd7fd 1699 if (result) {
7c349dde 1700 dev->online_queues--;
d4875622 1701 return result;
758dd7fd 1702 }
025c557a 1703
4e224106 1704 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
b60503ba
MW		 1705 return result;
1706}
1707
749941f2 1708static int nvme_create_io_queues(struct nvme_dev *dev)
42f61420 1709{
4b04cc6a 1710 unsigned i, max, rw_queues;
749941f2 1711 int ret = 0;
42f61420 1712
d858e5f0 1713 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
a6ff7262 1714 if (nvme_alloc_queue(dev, i, dev->q_depth)) {
749941f2 1715 ret = -ENOMEM;
42f61420 1716 break;
749941f2
CH		 1717 }
1718 }
42f61420 1719
d858e5f0 1720 max = min(dev->max_qid, dev->ctrl.queue_count - 1);
e20ba6e1
CH		 1721 if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) {
1722 rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] +
1723 dev->io_queues[HCTX_TYPE_READ];
4b04cc6a
JA		 1724 } else {
1725 rw_queues = max;
1726 }
1727
949928c1 1728 for (i = dev->online_queues; i <= max; i++) {
4b04cc6a
JA		 1729 bool polled = i > rw_queues;
1730
1731 ret = nvme_create_queue(&dev->queues[i], i, polled);
d4875622 1732 if (ret)
42f61420 1733 break;
27e8166c 1734 }
749941f2
CH		 1735
1736 /*
1737 * Ignore failing Create SQ/CQ commands, we can continue with less
8adb8c14
MI		 1738 * than the desired amount of queues, and even a controller without
1739 * I/O queues can still be used to issue admin commands. This might
749941f2
CH		 1740 * be useful to upgrade a buggy firmware for example.
1741 */
1742 return ret >= 0 ? 0 : ret;
b60503ba
MW		 1743}
1744
202021c1
SB		 1745static ssize_t nvme_cmb_show(struct device *dev,
1746 struct device_attribute *attr,
1747 char *buf)
1748{
1749 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
1750
c965809c 1751 return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n",
202021c1
SB		 1752 ndev->cmbloc, ndev->cmbsz);
1753}
1754static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL);
1755
88de4598 1756static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
8ffaadf7 1757{
88de4598
CH		 1758 u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
1759
1760 return 1ULL << (12 + 4 * szu);
1761}
1762
1763static u32 nvme_cmb_size(struct nvme_dev *dev)
1764{
1765 return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
1766}
1767
f65efd6d 1768static void nvme_map_cmb(struct nvme_dev *dev)
8ffaadf7 1769{
88de4598 1770 u64 size, offset;
8ffaadf7
JD		 1771 resource_size_t bar_size;
1772 struct pci_dev *pdev = to_pci_dev(dev->dev);
8969f1f8 1773 int bar;
8ffaadf7 1774
9fe5c59f
KB		 1775 if (dev->cmb_size)
1776 return;
1777
7a67cbea 1778 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
f65efd6d
CH		 1779 if (!dev->cmbsz)
1780 return;
202021c1 1781 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
8ffaadf7 1782
88de4598
CH		 1783 size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
1784 offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
8969f1f8
CH		 1785 bar = NVME_CMB_BIR(dev->cmbloc);
1786 bar_size = pci_resource_len(pdev, bar);
8ffaadf7
JD		 1787
1788 if (offset > bar_size)
f65efd6d 1789 return;
8ffaadf7
JD		 1790
1791 /*
1792 * Controllers may support a CMB size larger than their BAR,
1793 * for example, due to being behind a bridge. Reduce the CMB to
1794 * the reported size of the BAR
1795 */
1796 if (size > bar_size - offset)
1797 size = bar_size - offset;
1798
0f238ff5
LG		 1799 if (pci_p2pdma_add_resource(pdev, bar, size, offset)) {
1800 dev_warn(dev->ctrl.device,
1801 "failed to register the CMB\n");
f65efd6d 1802 return;
0f238ff5
LG		 1803 }
1804
8ffaadf7 1805 dev->cmb_size = size;
0f238ff5
LG		 1806 dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS);
1807
1808 if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) ==
1809 (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS))
1810 pci_p2pmem_publish(pdev, true);
f65efd6d
CH		 1811
1812 if (sysfs_add_file_to_group(&dev->ctrl.device->kobj,
1813 &dev_attr_cmb.attr, NULL))
1814 dev_warn(dev->ctrl.device,
1815 "failed to add sysfs attribute for CMB\n");
8ffaadf7
JD		 1816}
1817
1818static inline void nvme_release_cmb(struct nvme_dev *dev)
1819{
0f238ff5 1820 if (dev->cmb_size) {
1c78f773
MG		 1821 sysfs_remove_file_from_group(&dev->ctrl.device->kobj,
1822 &dev_attr_cmb.attr, NULL);
0f238ff5 1823 dev->cmb_size = 0;
8ffaadf7
JD		 1824 }
1825}
1826
87ad72a5
CH		 1827static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1828{
4033f35d 1829 u64 dma_addr = dev->host_mem_descs_dma;
87ad72a5 1830 struct nvme_command c;
87ad72a5
CH		 1831 int ret;
1832
87ad72a5
CH		 1833 memset(&c, 0, sizeof(c));
1834 c.features.opcode = nvme_admin_set_features;
1835 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1836 c.features.dword11 = cpu_to_le32(bits);
1837 c.features.dword12 = cpu_to_le32(dev->host_mem_size >>
1838 ilog2(dev->ctrl.page_size));
1839 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr));
1840 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr));
1841 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs);
1842
1843 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1844 if (ret) {
1845 dev_warn(dev->ctrl.device,
1846 "failed to set host mem (err %d, flags %#x).\n",
1847 ret, bits);
1848 }
87ad72a5
CH		 1849 return ret;
1850}
1851
1852static void nvme_free_host_mem(struct nvme_dev *dev)
1853{
1854 int i;
1855
1856 for (i = 0; i < dev->nr_host_mem_descs; i++) {
1857 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
1858 size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size;
1859
cc667f6d
LD		 1860 dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i],
1861 le64_to_cpu(desc->addr),
1862 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
87ad72a5
CH		 1863 }
1864
1865 kfree(dev->host_mem_desc_bufs);
1866 dev->host_mem_desc_bufs = NULL;
4033f35d
CH		 1867 dma_free_coherent(dev->dev,
1868 dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
1869 dev->host_mem_descs, dev->host_mem_descs_dma);
87ad72a5 1870 dev->host_mem_descs = NULL;
7e5dd57e 1871 dev->nr_host_mem_descs = 0;
87ad72a5
CH		 1872}
1873
92dc6895
CH		 1874static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
1875 u32 chunk_size)
9d713c2b 1876{
87ad72a5 1877 struct nvme_host_mem_buf_desc *descs;
92dc6895 1878 u32 max_entries, len;
4033f35d 1879 dma_addr_t descs_dma;
2ee0e4ed 1880 int i = 0;
87ad72a5 1881 void **bufs;
6fbcde66 1882 u64 size, tmp;
87ad72a5 1883
87ad72a5
CH		 1884 tmp = (preferred + chunk_size - 1);
1885 do_div(tmp, chunk_size);
1886 max_entries = tmp;
044a9df1
CH		 1887
1888 if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
1889 max_entries = dev->ctrl.hmmaxd;
1890
750afb08
LC		 1891 descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs),
1892 &descs_dma, GFP_KERNEL);
87ad72a5
CH		 1893 if (!descs)
1894 goto out;
1895
1896 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
1897 if (!bufs)
1898 goto out_free_descs;
1899
244a8fe4 1900 for (size = 0; size < preferred && i < max_entries; size += len) {
87ad72a5
CH		 1901 dma_addr_t dma_addr;
1902
50cdb7c6 1903 len = min_t(u64, chunk_size, preferred - size);
87ad72a5
CH		 1904 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
1905 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1906 if (!bufs[i])
1907 break;
1908
1909 descs[i].addr = cpu_to_le64(dma_addr);
1910 descs[i].size = cpu_to_le32(len / dev->ctrl.page_size);
1911 i++;
1912 }
1913
92dc6895 1914 if (!size)
87ad72a5 1915 goto out_free_bufs;
87ad72a5 1916
87ad72a5
CH		 1917 dev->nr_host_mem_descs = i;
1918 dev->host_mem_size = size;
1919 dev->host_mem_descs = descs;
4033f35d 1920 dev->host_mem_descs_dma = descs_dma;
87ad72a5
CH		 1921 dev->host_mem_desc_bufs = bufs;
1922 return 0;
1923
1924out_free_bufs:
1925 while (--i >= 0) {
1926 size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size;
1927
cc667f6d
LD		 1928 dma_free_attrs(dev->dev, size, bufs[i],
1929 le64_to_cpu(descs[i].addr),
1930 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
87ad72a5
CH		 1931 }
1932
1933 kfree(bufs);
1934out_free_descs:
4033f35d
CH		 1935 dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
1936 descs_dma);
87ad72a5 1937out:
87ad72a5
CH		 1938 dev->host_mem_descs = NULL;
1939 return -ENOMEM;
1940}
1941
92dc6895
CH		 1942static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
1943{
1944 u32 chunk_size;
1945
1946 /* start big and work our way down */
30f92d62 1947 for (chunk_size = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
044a9df1 1948 chunk_size >= max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
92dc6895
CH		 1949 chunk_size /= 2) {
1950 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
1951 if (!min || dev->host_mem_size >= min)
1952 return 0;
1953 nvme_free_host_mem(dev);
1954 }
1955 }
1956
1957 return -ENOMEM;
1958}
1959
9620cfba 1960static int nvme_setup_host_mem(struct nvme_dev *dev)
87ad72a5
CH		 1961{
1962 u64 max = (u64)max_host_mem_size_mb * SZ_1M;
1963 u64 preferred = (u64)dev->ctrl.hmpre * 4096;
1964 u64 min = (u64)dev->ctrl.hmmin * 4096;
1965 u32 enable_bits = NVME_HOST_MEM_ENABLE;
6fbcde66 1966 int ret;
87ad72a5
CH		 1967
1968 preferred = min(preferred, max);
1969 if (min > max) {
1970 dev_warn(dev->ctrl.device,
1971 "min host memory (%lld MiB) above limit (%d MiB).\n",
1972 min >> ilog2(SZ_1M), max_host_mem_size_mb);
1973 nvme_free_host_mem(dev);
9620cfba 1974 return 0;
87ad72a5
CH		 1975 }
1976
1977 /*
1978 * If we already have a buffer allocated check if we can reuse it.
1979 */
1980 if (dev->host_mem_descs) {
1981 if (dev->host_mem_size >= min)
1982 enable_bits |= NVME_HOST_MEM_RETURN;
1983 else
1984 nvme_free_host_mem(dev);
1985 }
1986
1987 if (!dev->host_mem_descs) {
92dc6895
CH		 1988 if (nvme_alloc_host_mem(dev, min, preferred)) {
1989 dev_warn(dev->ctrl.device,
1990 "failed to allocate host memory buffer.\n");
9620cfba 1991 return 0; /* controller must work without HMB */
92dc6895
CH		 1992 }
1993
1994 dev_info(dev->ctrl.device,
1995 "allocated %lld MiB host memory buffer.\n",
1996 dev->host_mem_size >> ilog2(SZ_1M));
87ad72a5
CH		 1997 }
1998
9620cfba
CH		 1999 ret = nvme_set_host_mem(dev, enable_bits);
2000 if (ret)
87ad72a5 2001 nvme_free_host_mem(dev);
9620cfba 2002 return ret;
9d713c2b
KB		 2003}
2004
612b7286
ML		 2005/*
2006 * nirqs is the number of interrupts available for write and read
2007 * queues. The core already reserved an interrupt for the admin queue.
2008 */
2009static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs)
3b6592f7 2010{
612b7286
ML		 2011 struct nvme_dev *dev = affd->priv;
2012 unsigned int nr_read_queues;
3b6592f7
JA		 2013
2014 /*
612b7286
ML		 2015 * If there is no interupt available for queues, ensure that
2016 * the default queue is set to 1. The affinity set size is
2017 * also set to one, but the irq core ignores it for this case.
2018 *
2019 * If only one interrupt is available or 'write_queue' == 0, combine
2020 * write and read queues.
2021 *
2022 * If 'write_queues' > 0, ensure it leaves room for at least one read
2023 * queue.
3b6592f7 2024 */
612b7286
ML		 2025 if (!nrirqs) {
2026 nrirqs = 1;
2027 nr_read_queues = 0;
2028 } else if (nrirqs == 1 || !write_queues) {
2029 nr_read_queues = 0;
2030 } else if (write_queues >= nrirqs) {
2031 nr_read_queues = 1;
3b6592f7 2032 } else {
612b7286 2033 nr_read_queues = nrirqs - write_queues;
3b6592f7 2034 }
612b7286
ML		 2035
2036 dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2037 affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2038 dev->io_queues[HCTX_TYPE_READ] = nr_read_queues;
2039 affd->set_size[HCTX_TYPE_READ] = nr_read_queues;
2040 affd->nr_sets = nr_read_queues ? 2 : 1;
3b6592f7
JA		 2041}
2042
6451fe73 2043static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues)
3b6592f7
JA		 2044{
2045 struct pci_dev *pdev = to_pci_dev(dev->dev);
3b6592f7 2046 struct irq_affinity affd = {
9cfef55b 2047 .pre_vectors = 1,
612b7286
ML		 2048 .calc_sets = nvme_calc_irq_sets,
2049 .priv = dev,
3b6592f7 2050 };
6451fe73
JA		 2051 unsigned int irq_queues, this_p_queues;
2052
2053 /*
2054 * Poll queues don't need interrupts, but we need at least one IO
2055 * queue left over for non-polled IO.
2056 */
2057 this_p_queues = poll_queues;
2058 if (this_p_queues >= nr_io_queues) {
2059 this_p_queues = nr_io_queues - 1;
2060 irq_queues = 1;
2061 } else {
c45b1fa2 2062 irq_queues = nr_io_queues - this_p_queues + 1;
6451fe73
JA		 2063 }
2064 dev->io_queues[HCTX_TYPE_POLL] = this_p_queues;
3b6592f7 2065
612b7286
ML		 2066 /* Initialize for the single interrupt case */
2067 dev->io_queues[HCTX_TYPE_DEFAULT] = 1;
2068 dev->io_queues[HCTX_TYPE_READ] = 0;
3b6592f7 2069
612b7286
ML		 2070 return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues,
2071 PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd);
3b6592f7
JA		 2072}
2073
8fae268b
KB		 2074static void nvme_disable_io_queues(struct nvme_dev *dev)
2075{
2076 if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq))
2077 __nvme_disable_io_queues(dev, nvme_admin_delete_cq);
2078}
2079
8d85fce7 2080static int nvme_setup_io_queues(struct nvme_dev *dev)
b60503ba 2081{
147b27e4 2082 struct nvme_queue *adminq = &dev->queues[0];
e75ec752 2083 struct pci_dev *pdev = to_pci_dev(dev->dev);
97f6ef64
XY		 2084 int result, nr_io_queues;
2085 unsigned long size;
b60503ba 2086
3b6592f7 2087 nr_io_queues = max_io_queues();
9a0be7ab
CH		 2088 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
2089 if (result < 0)
1b23484b 2090 return result;
9a0be7ab 2091
f5fa90dc 2092 if (nr_io_queues == 0)
a5229050 2093 return 0;
4e224106
CH		 2094
2095 clear_bit(NVMEQ_ENABLED, &adminq->flags);
b60503ba 2096
0f238ff5 2097 if (dev->cmb_use_sqes) {
8ffaadf7
JD		 2098 result = nvme_cmb_qdepth(dev, nr_io_queues,
2099 sizeof(struct nvme_command));
2100 if (result > 0)
2101 dev->q_depth = result;
2102 else
0f238ff5 2103 dev->cmb_use_sqes = false;
8ffaadf7
JD		 2104 }
2105
97f6ef64
XY		 2106 do {
2107 size = db_bar_size(dev, nr_io_queues);
2108 result = nvme_remap_bar(dev, size);
2109 if (!result)
2110 break;
2111 if (!--nr_io_queues)
2112 return -ENOMEM;
2113 } while (1);
2114 adminq->q_db = dev->dbs;
f1938f6e 2115
8fae268b 2116 retry:
9d713c2b 2117 /* Deregister the admin queue's interrupt */
0ff199cb 2118 pci_free_irq(pdev, 0, adminq);
9d713c2b 2119
e32efbfc
JA		 2120 /*
2121 * If we enable msix early due to not intx, disable it again before
2122 * setting up the full range we need.
2123 */
dca51e78 2124 pci_free_irq_vectors(pdev);
3b6592f7
JA		 2125
2126 result = nvme_setup_irqs(dev, nr_io_queues);
22b55601 2127 if (result <= 0)
dca51e78 2128 return -EIO;
3b6592f7 2129
22b55601 2130 dev->num_vecs = result;
4b04cc6a 2131 result = max(result - 1, 1);
e20ba6e1 2132 dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL];
fa08a396 2133
063a8096
MW		 2134 /*
2135 * Should investigate if there's a performance win from allocating
2136 * more queues than interrupt vectors; it might allow the submission
2137 * path to scale better, even if the receive path is limited by the
2138 * number of interrupts.
2139 */
dca51e78 2140 result = queue_request_irq(adminq);
7c349dde 2141 if (result)
d4875622 2142 return result;
4e224106 2143 set_bit(NVMEQ_ENABLED, &adminq->flags);
8fae268b
KB		 2144
2145 result = nvme_create_io_queues(dev);
2146 if (result || dev->online_queues < 2)
2147 return result;
2148
2149 if (dev->online_queues - 1 < dev->max_qid) {
2150 nr_io_queues = dev->online_queues - 1;
2151 nvme_disable_io_queues(dev);
2152 nvme_suspend_io_queues(dev);
2153 goto retry;
2154 }
2155 dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n",
2156 dev->io_queues[HCTX_TYPE_DEFAULT],
2157 dev->io_queues[HCTX_TYPE_READ],
2158 dev->io_queues[HCTX_TYPE_POLL]);
2159 return 0;
b60503ba
MW		 2160}
2161
2a842aca 2162static void nvme_del_queue_end(struct request *req, blk_status_t error)
a5768aa8 2163{
db3cbfff 2164 struct nvme_queue *nvmeq = req->end_io_data;
b5875222 2165
db3cbfff 2166 blk_mq_free_request(req);
d1ed6aa1 2167 complete(&nvmeq->delete_done);
a5768aa8
KB		 2168}
2169
2a842aca 2170static void nvme_del_cq_end(struct request *req, blk_status_t error)
a5768aa8 2171{
db3cbfff 2172 struct nvme_queue *nvmeq = req->end_io_data;
a5768aa8 2173
d1ed6aa1
CH		 2174 if (error)
2175 set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
db3cbfff
KB		 2176
2177 nvme_del_queue_end(req, error);
a5768aa8
KB		 2178}
2179
db3cbfff 2180static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
bda4e0fb 2181{
db3cbfff
KB		 2182 struct request_queue *q = nvmeq->dev->ctrl.admin_q;
2183 struct request *req;
2184 struct nvme_command cmd;
bda4e0fb 2185
db3cbfff
KB		 2186 memset(&cmd, 0, sizeof(cmd));
2187 cmd.delete_queue.opcode = opcode;
2188 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
bda4e0fb 2189
eb71f435 2190 req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
db3cbfff
KB		 2191 if (IS_ERR(req))
2192 return PTR_ERR(req);
bda4e0fb 2193
db3cbfff
KB		 2194 req->timeout = ADMIN_TIMEOUT;
2195 req->end_io_data = nvmeq;
2196
d1ed6aa1 2197 init_completion(&nvmeq->delete_done);
db3cbfff
KB		 2198 blk_execute_rq_nowait(q, NULL, req, false,
2199 opcode == nvme_admin_delete_cq ?
2200 nvme_del_cq_end : nvme_del_queue_end);
2201 return 0;
bda4e0fb
KB		 2202}
2203
8fae268b 2204static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode)
a5768aa8 2205{
5271edd4 2206 int nr_queues = dev->online_queues - 1, sent = 0;
db3cbfff 2207 unsigned long timeout;
a5768aa8 2208
db3cbfff 2209 retry:
5271edd4
CH		 2210 timeout = ADMIN_TIMEOUT;
2211 while (nr_queues > 0) {
2212 if (nvme_delete_queue(&dev->queues[nr_queues], opcode))
2213 break;
2214 nr_queues--;
2215 sent++;
db3cbfff 2216 }
d1ed6aa1
CH		 2217 while (sent) {
2218 struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent];
2219
2220 timeout = wait_for_completion_io_timeout(&nvmeq->delete_done,
5271edd4
CH		 2221 timeout);
2222 if (timeout == 0)
2223 return false;
d1ed6aa1
CH		 2224
2225 /* handle any remaining CQEs */
2226 if (opcode == nvme_admin_delete_cq &&
2227 !test_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags))
2228 nvme_poll_irqdisable(nvmeq, -1);
2229
2230 sent--;
5271edd4
CH		 2231 if (nr_queues)
2232 goto retry;
2233 }
2234 return true;
a5768aa8
KB		 2235}
2236
422ef0c7 2237/*
2b1b7e78 2238 * return error value only when tagset allocation failed
422ef0c7 2239 */
8d85fce7 2240static int nvme_dev_add(struct nvme_dev *dev)
b60503ba 2241{
2b1b7e78
JW		 2242 int ret;
2243
5bae7f73 2244 if (!dev->ctrl.tagset) {
376f7ef8 2245 dev->tagset.ops = &nvme_mq_ops;
ffe7704d 2246 dev->tagset.nr_hw_queues = dev->online_queues - 1;
ed92ad37
CH		 2247 dev->tagset.nr_maps = 2; /* default + read */
2248 if (dev->io_queues[HCTX_TYPE_POLL])
2249 dev->tagset.nr_maps++;
ffe7704d
KB		 2250 dev->tagset.timeout = NVME_IO_TIMEOUT;
2251 dev->tagset.numa_node = dev_to_node(dev->dev);
2252 dev->tagset.queue_depth =
a4aea562 2253 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
a7a7cbe3
CK		 2254 dev->tagset.cmd_size = nvme_pci_cmd_size(dev, false);
2255 if ((dev->ctrl.sgls & ((1 << 0) | (1 << 1))) && sgl_threshold) {
2256 dev->tagset.cmd_size = max(dev->tagset.cmd_size,
2257 nvme_pci_cmd_size(dev, true));
2258 }
ffe7704d
KB		 2259 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2260 dev->tagset.driver_data = dev;
b60503ba 2261
2b1b7e78
JW		 2262 ret = blk_mq_alloc_tag_set(&dev->tagset);
2263 if (ret) {
2264 dev_warn(dev->ctrl.device,
2265 "IO queues tagset allocation failed %d\n", ret);
2266 return ret;
2267 }
5bae7f73 2268 dev->ctrl.tagset = &dev->tagset;
f9f38e33
HK		 2269
2270 nvme_dbbuf_set(dev);
949928c1
KB		 2271 } else {
2272 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2273
2274 /* Free previously allocated queues that are no longer usable */
2275 nvme_free_queues(dev, dev->online_queues);
ffe7704d 2276 }
949928c1 2277
e1e5e564 2278 return 0;
b60503ba
MW		 2279}
2280
b00a726a 2281static int nvme_pci_enable(struct nvme_dev *dev)
0877cb0d 2282{
b00a726a 2283 int result = -ENOMEM;
e75ec752 2284 struct pci_dev *pdev = to_pci_dev(dev->dev);
0877cb0d
KB		 2285
2286 if (pci_enable_device_mem(pdev))
2287 return result;
2288
0877cb0d 2289 pci_set_master(pdev);
0877cb0d 2290
e75ec752
CH		 2291 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) &&
2292 dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32)))
052d0efa 2293 goto disable;
0877cb0d 2294
7a67cbea 2295 if (readl(dev->bar + NVME_REG_CSTS) == -1) {
0e53d180 2296 result = -ENODEV;
b00a726a 2297 goto disable;
0e53d180 2298 }
e32efbfc
JA		 2299
2300 /*
a5229050
KB		 2301 * Some devices and/or platforms don't advertise or work with INTx
2302 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2303 * adjust this later.
e32efbfc 2304 */
dca51e78
CH		 2305 result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
2306 if (result < 0)
2307 return result;
e32efbfc 2308
20d0dfe6 2309 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
7a67cbea 2310
20d0dfe6 2311 dev->q_depth = min_t(int, NVME_CAP_MQES(dev->ctrl.cap) + 1,
b27c1e68 2312 io_queue_depth);
20d0dfe6 2313 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
7a67cbea 2314 dev->dbs = dev->bar + 4096;
1f390c1f
SG		 2315
2316 /*
2317 * Temporary fix for the Apple controller found in the MacBook8,1 and
2318 * some MacBook7,1 to avoid controller resets and data loss.
2319 */
2320 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
2321 dev->q_depth = 2;
9bdcfb10
CH		 2322 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
2323 "set queue depth=%u to work around controller resets\n",
1f390c1f 2324 dev->q_depth);
d554b5e1
MP		 2325 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2326 (pdev->device == 0xa821 || pdev->device == 0xa822) &&
20d0dfe6 2327 NVME_CAP_MQES(dev->ctrl.cap) == 0) {
d554b5e1
MP		 2328 dev->q_depth = 64;
2329 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2330 "set queue depth=%u\n", dev->q_depth);
1f390c1f
SG		 2331 }
2332
f65efd6d 2333 nvme_map_cmb(dev);
202021c1 2334
a0a3408e
KB		 2335 pci_enable_pcie_error_reporting(pdev);
2336 pci_save_state(pdev);
0877cb0d
KB		 2337 return 0;
2338
2339 disable:
0877cb0d
KB		 2340 pci_disable_device(pdev);
2341 return result;
2342}
2343
2344static void nvme_dev_unmap(struct nvme_dev *dev)
b00a726a
KB		 2345{
2346 if (dev->bar)
2347 iounmap(dev->bar);
a1f447b3 2348 pci_release_mem_regions(to_pci_dev(dev->dev));
b00a726a
KB		 2349}
2350
2351static void nvme_pci_disable(struct nvme_dev *dev)
0877cb0d 2352{
e75ec752
CH		 2353 struct pci_dev *pdev = to_pci_dev(dev->dev);
2354
dca51e78 2355 pci_free_irq_vectors(pdev);
0877cb0d 2356
a0a3408e
KB		 2357 if (pci_is_enabled(pdev)) {
2358 pci_disable_pcie_error_reporting(pdev);
e75ec752 2359 pci_disable_device(pdev);
4d115420 2360 }
4d115420
KB		 2361}
2362
a5cdb68c 2363static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
b60503ba 2364{
302ad8cc
KB		 2365 bool dead = true;
2366 struct pci_dev *pdev = to_pci_dev(dev->dev);
22404274 2367
77bf25ea 2368 mutex_lock(&dev->shutdown_lock);
302ad8cc
KB		 2369 if (pci_is_enabled(pdev)) {
2370 u32 csts = readl(dev->bar + NVME_REG_CSTS);
2371
ebef7368
KB		 2372 if (dev->ctrl.state == NVME_CTRL_LIVE ||
2373 dev->ctrl.state == NVME_CTRL_RESETTING)
302ad8cc
KB		 2374 nvme_start_freeze(&dev->ctrl);
2375 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
2376 pdev->error_state != pci_channel_io_normal);
c9d3bf88 2377 }
c21377f8 2378
302ad8cc
KB		 2379 /*
2380 * Give the controller a chance to complete all entered requests if
2381 * doing a safe shutdown.
2382 */
87ad72a5
CH		 2383 if (!dead) {
2384 if (shutdown)
2385 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
9a915a5b
JW		 2386 }
2387
2388 nvme_stop_queues(&dev->ctrl);
87ad72a5 2389
64ee0ac0 2390 if (!dead && dev->ctrl.queue_count > 0) {
8fae268b 2391 nvme_disable_io_queues(dev);
a5cdb68c 2392 nvme_disable_admin_queue(dev, shutdown);
4d115420 2393 }
8fae268b
KB		 2394 nvme_suspend_io_queues(dev);
2395 nvme_suspend_queue(&dev->queues[0]);
b00a726a 2396 nvme_pci_disable(dev);
07836e65 2397
e1958e65
ML		 2398 blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
2399 blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
302ad8cc
KB		 2400
2401 /*
2402 * The driver will not be starting up queues again if shutting down so
2403 * must flush all entered requests to their failed completion to avoid
2404 * deadlocking blk-mq hot-cpu notifier.
2405 */
2406 if (shutdown)
2407 nvme_start_queues(&dev->ctrl);
77bf25ea 2408 mutex_unlock(&dev->shutdown_lock);
b60503ba
MW		 2409}
2410
091b6092
MW		 2411static int nvme_setup_prp_pools(struct nvme_dev *dev)
2412{
e75ec752 2413 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
091b6092
MW		 2414 PAGE_SIZE, PAGE_SIZE, 0);
2415 if (!dev->prp_page_pool)
2416 return -ENOMEM;
2417
99802a7a 2418 /* Optimisation for I/Os between 4k and 128k */
e75ec752 2419 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
99802a7a
MW		 2420 256, 256, 0);
2421 if (!dev->prp_small_pool) {
2422 dma_pool_destroy(dev->prp_page_pool);
2423 return -ENOMEM;
2424 }
091b6092
MW		 2425 return 0;
2426}
2427
2428static void nvme_release_prp_pools(struct nvme_dev *dev)
2429{
2430 dma_pool_destroy(dev->prp_page_pool);
99802a7a 2431 dma_pool_destroy(dev->prp_small_pool);
091b6092
MW		 2432}
2433
1673f1f0 2434static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
5e82e952 2435{
1673f1f0 2436 struct nvme_dev *dev = to_nvme_dev(ctrl);
9ac27090 2437
f9f38e33 2438 nvme_dbbuf_dma_free(dev);
e75ec752 2439 put_device(dev->dev);
4af0e21c
KB		 2440 if (dev->tagset.tags)
2441 blk_mq_free_tag_set(&dev->tagset);
1c63dc66
CH		 2442 if (dev->ctrl.admin_q)
2443 blk_put_queue(dev->ctrl.admin_q);
5e82e952 2444 kfree(dev->queues);
e286bcfc 2445 free_opal_dev(dev->ctrl.opal_dev);
943e942e 2446 mempool_destroy(dev->iod_mempool);
5e82e952
KB		 2447 kfree(dev);
2448}
2449
f58944e2
KB		 2450static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status)
2451{
237045fc 2452 dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status);
f58944e2 2453
d22524a4 2454 nvme_get_ctrl(&dev->ctrl);
69d9a99c 2455 nvme_dev_disable(dev, false);
9f9cafc1 2456 nvme_kill_queues(&dev->ctrl);
03e0f3a6 2457 if (!queue_work(nvme_wq, &dev->remove_work))
f58944e2
KB		 2458 nvme_put_ctrl(&dev->ctrl);
2459}
2460
fd634f41 2461static void nvme_reset_work(struct work_struct *work)
5e82e952 2462{
d86c4d8e
CH		 2463 struct nvme_dev *dev =
2464 container_of(work, struct nvme_dev, ctrl.reset_work);
a98e58e5 2465 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
f58944e2 2466 int result = -ENODEV;
2b1b7e78 2467 enum nvme_ctrl_state new_state = NVME_CTRL_LIVE;
5e82e952 2468
82b057ca 2469 if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING))
fd634f41 2470 goto out;
5e82e952 2471
fd634f41
CH		 2472 /*
2473 * If we're called to reset a live controller first shut it down before
2474 * moving on.
2475 */
b00a726a 2476 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
a5cdb68c 2477 nvme_dev_disable(dev, false);
5e82e952 2478
5c959d73 2479 mutex_lock(&dev->shutdown_lock);
b00a726a 2480 result = nvme_pci_enable(dev);
f0b50732 2481 if (result)
4726bcf3 2482 goto out_unlock;
f0b50732 2483
01ad0990 2484 result = nvme_pci_configure_admin_queue(dev);
f0b50732 2485 if (result)
4726bcf3 2486 goto out_unlock;
f0b50732 2487
0fb59cbc
KB		 2488 result = nvme_alloc_admin_tags(dev);
2489 if (result)
4726bcf3 2490 goto out_unlock;
b9afca3e 2491
943e942e
JA		 2492 /*
2493 * Limit the max command size to prevent iod->sg allocations going
2494 * over a single page.
2495 */
2496 dev->ctrl.max_hw_sectors = NVME_MAX_KB_SZ << 1;
2497 dev->ctrl.max_segments = NVME_MAX_SEGS;
5c959d73
KB		 2498 mutex_unlock(&dev->shutdown_lock);
2499
2500 /*
2501 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
2502 * initializing procedure here.
2503 */
2504 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
2505 dev_warn(dev->ctrl.device,
2506 "failed to mark controller CONNECTING\n");
2507 goto out;
2508 }
943e942e 2509
ce4541f4
CH		 2510 result = nvme_init_identify(&dev->ctrl);
2511 if (result)
f58944e2 2512 goto out;
ce4541f4 2513
e286bcfc
SB		 2514 if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
2515 if (!dev->ctrl.opal_dev)
2516 dev->ctrl.opal_dev =
2517 init_opal_dev(&dev->ctrl, &nvme_sec_submit);
2518 else if (was_suspend)
2519 opal_unlock_from_suspend(dev->ctrl.opal_dev);
2520 } else {
2521 free_opal_dev(dev->ctrl.opal_dev);
2522 dev->ctrl.opal_dev = NULL;
4f1244c8 2523 }
a98e58e5 2524
f9f38e33
HK		 2525 if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) {
2526 result = nvme_dbbuf_dma_alloc(dev);
2527 if (result)
2528 dev_warn(dev->dev,
2529 "unable to allocate dma for dbbuf\n");
2530 }
2531
9620cfba
CH		 2532 if (dev->ctrl.hmpre) {
2533 result = nvme_setup_host_mem(dev);
2534 if (result < 0)
2535 goto out;
2536 }
87ad72a5 2537
f0b50732 2538 result = nvme_setup_io_queues(dev);
badc34d4 2539 if (result)
f58944e2 2540 goto out;
f0b50732 2541
2659e57b
CH		 2542 /*
2543 * Keep the controller around but remove all namespaces if we don't have
2544 * any working I/O queue.
2545 */
3cf519b5 2546 if (dev->online_queues < 2) {
1b3c47c1 2547 dev_warn(dev->ctrl.device, "IO queues not created\n");
3b24774e 2548 nvme_kill_queues(&dev->ctrl);
5bae7f73 2549 nvme_remove_namespaces(&dev->ctrl);
2b1b7e78 2550 new_state = NVME_CTRL_ADMIN_ONLY;
3cf519b5 2551 } else {
25646264 2552 nvme_start_queues(&dev->ctrl);
302ad8cc 2553 nvme_wait_freeze(&dev->ctrl);
2b1b7e78
JW		 2554 /* hit this only when allocate tagset fails */
2555 if (nvme_dev_add(dev))
2556 new_state = NVME_CTRL_ADMIN_ONLY;
302ad8cc 2557 nvme_unfreeze(&dev->ctrl);
3cf519b5
CH		 2558 }
2559
2b1b7e78
JW		 2560 /*
2561 * If only admin queue live, keep it to do further investigation or
2562 * recovery.
2563 */
2564 if (!nvme_change_ctrl_state(&dev->ctrl, new_state)) {
2565 dev_warn(dev->ctrl.device,
2566 "failed to mark controller state %d\n", new_state);
bb8d261e
CH		 2567 goto out;
2568 }
92911a55 2569
d09f2b45 2570 nvme_start_ctrl(&dev->ctrl);
3cf519b5 2571 return;
f0b50732 2572
4726bcf3
KB		 2573 out_unlock:
2574 mutex_unlock(&dev->shutdown_lock);
3cf519b5 2575 out:
f58944e2 2576 nvme_remove_dead_ctrl(dev, result);
f0b50732
KB		 2577}
2578
5c8809e6 2579static void nvme_remove_dead_ctrl_work(struct work_struct *work)
9a6b9458 2580{
5c8809e6 2581 struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
e75ec752 2582 struct pci_dev *pdev = to_pci_dev(dev->dev);
9a6b9458
KB		 2583
2584 if (pci_get_drvdata(pdev))
921920ab 2585 device_release_driver(&pdev->dev);
1673f1f0 2586 nvme_put_ctrl(&dev->ctrl);
9a6b9458
KB		 2587}
2588
1c63dc66 2589static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
9ca97374 2590{
1c63dc66 2591 *val = readl(to_nvme_dev(ctrl)->bar + off);
90667892 2592 return 0;
9ca97374
TH		 2593}
2594
5fd4ce1b 2595static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
4cc06521 2596{
5fd4ce1b
CH		 2597 writel(val, to_nvme_dev(ctrl)->bar + off);
2598 return 0;
2599}
4cc06521 2600
7fd8930f
CH		 2601static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2602{
2603 *val = readq(to_nvme_dev(ctrl)->bar + off);
2604 return 0;
4cc06521
KB		 2605}
2606
97c12223
KB		 2607static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
2608{
2609 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2610
2611 return snprintf(buf, size, "%s", dev_name(&pdev->dev));
2612}
2613
1c63dc66 2614static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
1a353d85 2615 .name = "pcie",
e439bb12 2616 .module = THIS_MODULE,
e0596ab2
LG		 2617 .flags = NVME_F_METADATA_SUPPORTED |
2618 NVME_F_PCI_P2PDMA,
1c63dc66 2619 .reg_read32 = nvme_pci_reg_read32,
5fd4ce1b 2620 .reg_write32 = nvme_pci_reg_write32,
7fd8930f 2621 .reg_read64 = nvme_pci_reg_read64,
1673f1f0 2622 .free_ctrl = nvme_pci_free_ctrl,
f866fc42 2623 .submit_async_event = nvme_pci_submit_async_event,
97c12223 2624 .get_address = nvme_pci_get_address,
1c63dc66 2625};
4cc06521 2626
b00a726a
KB		 2627static int nvme_dev_map(struct nvme_dev *dev)
2628{
b00a726a
KB		 2629 struct pci_dev *pdev = to_pci_dev(dev->dev);
2630
a1f447b3 2631 if (pci_request_mem_regions(pdev, "nvme"))
b00a726a
KB		 2632 return -ENODEV;
2633
97f6ef64 2634 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
b00a726a
KB		 2635 goto release;
2636
9fa196e7 2637 return 0;
b00a726a 2638 release:
9fa196e7
MG		 2639 pci_release_mem_regions(pdev);
2640 return -ENODEV;
b00a726a
KB		 2641}
2642
8427bbc2 2643static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
ff5350a8
AL		 2644{
2645 if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
2646 /*
2647 * Several Samsung devices seem to drop off the PCIe bus
2648 * randomly when APST is on and uses the deepest sleep state.
2649 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2650 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2651 * 950 PRO 256GB", but it seems to be restricted to two Dell
2652 * laptops.
2653 */
2654 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
2655 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
2656 dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
2657 return NVME_QUIRK_NO_DEEPEST_PS;
8427bbc2
KHF		 2658 } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
2659 /*
2660 * Samsung SSD 960 EVO drops off the PCIe bus after system
467c77d4
JJ		 2661 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
2662 * within few minutes after bootup on a Coffee Lake board -
2663 * ASUS PRIME Z370-A
8427bbc2
KHF		 2664 */
2665 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
467c77d4
JJ		 2666 (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") ||
2667 dmi_match(DMI_BOARD_NAME, "PRIME Z370-A")))
8427bbc2 2668 return NVME_QUIRK_NO_APST;
ff5350a8
AL		 2669 }
2670
2671 return 0;
2672}
2673
18119775
KB		 2674static void nvme_async_probe(void *data, async_cookie_t cookie)
2675{
2676 struct nvme_dev *dev = data;
80f513b5 2677
18119775
KB		 2678 nvme_reset_ctrl_sync(&dev->ctrl);
2679 flush_work(&dev->ctrl.scan_work);
80f513b5 2680 nvme_put_ctrl(&dev->ctrl);
18119775
KB		 2681}
2682
8d85fce7 2683static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
b60503ba 2684{
a4aea562 2685 int node, result = -ENOMEM;
b60503ba 2686 struct nvme_dev *dev;
ff5350a8 2687 unsigned long quirks = id->driver_data;
943e942e 2688 size_t alloc_size;
b60503ba 2689
a4aea562
MB		 2690 node = dev_to_node(&pdev->dev);
2691 if (node == NUMA_NO_NODE)
2fa84351 2692 set_dev_node(&pdev->dev, first_memory_node);
a4aea562
MB		 2693
2694 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
b60503ba
MW		 2695 if (!dev)
2696 return -ENOMEM;
147b27e4 2697
3b6592f7
JA		 2698 dev->queues = kcalloc_node(max_queue_count(), sizeof(struct nvme_queue),
2699 GFP_KERNEL, node);
b60503ba
MW		 2700 if (!dev->queues)
2701 goto free;
2702
e75ec752 2703 dev->dev = get_device(&pdev->dev);
9a6b9458 2704 pci_set_drvdata(pdev, dev);
1c63dc66 2705
b00a726a
KB		 2706 result = nvme_dev_map(dev);
2707 if (result)
b00c9b7a 2708 goto put_pci;
b00a726a 2709
d86c4d8e 2710 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
5c8809e6 2711 INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
77bf25ea 2712 mutex_init(&dev->shutdown_lock);
b60503ba 2713
091b6092
MW		 2714 result = nvme_setup_prp_pools(dev);
2715 if (result)
b00c9b7a 2716 goto unmap;
4cc06521 2717
8427bbc2 2718 quirks |= check_vendor_combination_bug(pdev);
ff5350a8 2719
943e942e
JA		 2720 /*
2721 * Double check that our mempool alloc size will cover the biggest
2722 * command we support.
2723 */
2724 alloc_size = nvme_pci_iod_alloc_size(dev, NVME_MAX_KB_SZ,
2725 NVME_MAX_SEGS, true);
2726 WARN_ON_ONCE(alloc_size > PAGE_SIZE);
2727
2728 dev->iod_mempool = mempool_create_node(1, mempool_kmalloc,
2729 mempool_kfree,
2730 (void *) alloc_size,
2731 GFP_KERNEL, node);
2732 if (!dev->iod_mempool) {
2733 result = -ENOMEM;
2734 goto release_pools;
2735 }
2736
b6e44b4c
KB		 2737 result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
2738 quirks);
2739 if (result)
2740 goto release_mempool;
2741
1b3c47c1
SG		 2742 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
2743
80f513b5 2744 nvme_get_ctrl(&dev->ctrl);
18119775 2745 async_schedule(nvme_async_probe, dev);
4caff8fc 2746
b60503ba
MW		 2747 return 0;
2748
b6e44b4c
KB		 2749 release_mempool:
2750 mempool_destroy(dev->iod_mempool);
0877cb0d 2751 release_pools:
091b6092 2752 nvme_release_prp_pools(dev);
b00c9b7a
CJ		 2753 unmap:
2754 nvme_dev_unmap(dev);
a96d4f5c 2755 put_pci:
e75ec752 2756 put_device(dev->dev);
b60503ba
MW		 2757 free:
2758 kfree(dev->queues);
b60503ba
MW		 2759 kfree(dev);
2760 return result;
2761}
2762
775755ed 2763static void nvme_reset_prepare(struct pci_dev *pdev)
f0d54a54 2764{
a6739479 2765 struct nvme_dev *dev = pci_get_drvdata(pdev);
f263fbb8 2766 nvme_dev_disable(dev, false);
775755ed 2767}
f0d54a54 2768
775755ed
CH		 2769static void nvme_reset_done(struct pci_dev *pdev)
2770{
f263fbb8 2771 struct nvme_dev *dev = pci_get_drvdata(pdev);
79c48ccf 2772 nvme_reset_ctrl_sync(&dev->ctrl);
f0d54a54
KB		 2773}
2774
09ece142
KB		 2775static void nvme_shutdown(struct pci_dev *pdev)
2776{
2777 struct nvme_dev *dev = pci_get_drvdata(pdev);
a5cdb68c 2778 nvme_dev_disable(dev, true);
09ece142
KB		 2779}
2780
f58944e2
KB		 2781/*
2782 * The driver's remove may be called on a device in a partially initialized
2783 * state. This function must not have any dependencies on the device state in
2784 * order to proceed.
2785 */
8d85fce7 2786static void nvme_remove(struct pci_dev *pdev)
b60503ba
MW		 2787{
2788 struct nvme_dev *dev = pci_get_drvdata(pdev);
9a6b9458 2789
bb8d261e 2790 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
9a6b9458 2791 pci_set_drvdata(pdev, NULL);
0ff9d4e1 2792
6db28eda 2793 if (!pci_device_is_present(pdev)) {
0ff9d4e1 2794 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
1d39e692 2795 nvme_dev_disable(dev, true);
cb4bfda6 2796 nvme_dev_remove_admin(dev);
6db28eda 2797 }
0ff9d4e1 2798
d86c4d8e 2799 flush_work(&dev->ctrl.reset_work);
d09f2b45
SG		 2800 nvme_stop_ctrl(&dev->ctrl);
2801 nvme_remove_namespaces(&dev->ctrl);
a5cdb68c 2802 nvme_dev_disable(dev, true);
9fe5c59f 2803 nvme_release_cmb(dev);
87ad72a5 2804 nvme_free_host_mem(dev);
a4aea562 2805 nvme_dev_remove_admin(dev);
a1a5ef99 2806 nvme_free_queues(dev, 0);
d09f2b45 2807 nvme_uninit_ctrl(&dev->ctrl);
9a6b9458 2808 nvme_release_prp_pools(dev);
b00a726a 2809 nvme_dev_unmap(dev);
1673f1f0 2810 nvme_put_ctrl(&dev->ctrl);
b60503ba
MW		 2811}
2812
671a6018 2813#ifdef CONFIG_PM_SLEEP
cd638946
KB		 2814static int nvme_suspend(struct device *dev)
2815{
2816 struct pci_dev *pdev = to_pci_dev(dev);
2817 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2818
a5cdb68c 2819 nvme_dev_disable(ndev, true);
cd638946
KB		 2820 return 0;
2821}
2822
2823static int nvme_resume(struct device *dev)
2824{
2825 struct pci_dev *pdev = to_pci_dev(dev);
2826 struct nvme_dev *ndev = pci_get_drvdata(pdev);
cd638946 2827
d86c4d8e 2828 nvme_reset_ctrl(&ndev->ctrl);
9a6b9458 2829 return 0;
cd638946 2830}
671a6018 2831#endif
cd638946
KB		 2832
2833static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
b60503ba 2834
a0a3408e
KB		 2835static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
2836 pci_channel_state_t state)
2837{
2838 struct nvme_dev *dev = pci_get_drvdata(pdev);
2839
2840 /*
2841 * A frozen channel requires a reset. When detected, this method will
2842 * shutdown the controller to quiesce. The controller will be restarted
2843 * after the slot reset through driver's slot_reset callback.
2844 */
a0a3408e
KB		 2845 switch (state) {
2846 case pci_channel_io_normal:
2847 return PCI_ERS_RESULT_CAN_RECOVER;
2848 case pci_channel_io_frozen:
d011fb31
KB		 2849 dev_warn(dev->ctrl.device,
2850 "frozen state error detected, reset controller\n");
a5cdb68c 2851 nvme_dev_disable(dev, false);
a0a3408e
KB		 2852 return PCI_ERS_RESULT_NEED_RESET;
2853 case pci_channel_io_perm_failure:
d011fb31
KB		 2854 dev_warn(dev->ctrl.device,
2855 "failure state error detected, request disconnect\n");
a0a3408e
KB		 2856 return PCI_ERS_RESULT_DISCONNECT;
2857 }
2858 return PCI_ERS_RESULT_NEED_RESET;
2859}
2860
2861static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
2862{
2863 struct nvme_dev *dev = pci_get_drvdata(pdev);
2864
1b3c47c1 2865 dev_info(dev->ctrl.device, "restart after slot reset\n");
a0a3408e 2866 pci_restore_state(pdev);
d86c4d8e 2867 nvme_reset_ctrl(&dev->ctrl);
a0a3408e
KB		 2868 return PCI_ERS_RESULT_RECOVERED;
2869}
2870
2871static void nvme_error_resume(struct pci_dev *pdev)
2872{
72cd4cc2
KB		 2873 struct nvme_dev *dev = pci_get_drvdata(pdev);
2874
2875 flush_work(&dev->ctrl.reset_work);
a0a3408e
KB		 2876}
2877
1d352035 2878static const struct pci_error_handlers nvme_err_handler = {
b60503ba 2879 .error_detected = nvme_error_detected,
b60503ba
MW		 2880 .slot_reset = nvme_slot_reset,
2881 .resume = nvme_error_resume,
775755ed
CH		 2882 .reset_prepare = nvme_reset_prepare,
2883 .reset_done = nvme_reset_done,
b60503ba
MW		 2884};
2885
6eb0d698 2886static const struct pci_device_id nvme_id_table[] = {
106198ed 2887 { PCI_VDEVICE(INTEL, 0x0953),
08095e70 2888 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 2889 NVME_QUIRK_DEALLOCATE_ZEROES, },
99466e70
KB		 2890 { PCI_VDEVICE(INTEL, 0x0a53),
2891 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 2892 NVME_QUIRK_DEALLOCATE_ZEROES, },
99466e70
KB		 2893 { PCI_VDEVICE(INTEL, 0x0a54),
2894 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 2895 NVME_QUIRK_DEALLOCATE_ZEROES, },
f99cb7af
DWF		 2896 { PCI_VDEVICE(INTEL, 0x0a55),
2897 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2898 NVME_QUIRK_DEALLOCATE_ZEROES, },
50af47d0 2899 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */
9abd68ef
JA		 2900 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
2901 NVME_QUIRK_MEDIUM_PRIO_SQ },
6299358d
JD		 2902 { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */
2903 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
540c801c 2904 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */
7b210e4e
CH		 2905 .driver_data = NVME_QUIRK_IDENTIFY_CNS |
2906 NVME_QUIRK_DISABLE_WRITE_ZEROES, },
0302ae60
MP		 2907 { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */
2908 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
54adc010
GP		 2909 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
2910 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
8c97eecc
JL		 2911 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */
2912 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
015282c9
WW		 2913 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
2914 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
d554b5e1
MP		 2915 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */
2916 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2917 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */
2918 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
608cc4b1
CH		 2919 { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */
2920 .driver_data = NVME_QUIRK_LIGHTNVM, },
2921 { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */
2922 .driver_data = NVME_QUIRK_LIGHTNVM, },
ea48e877
WX		 2923 { PCI_DEVICE(0x1d1d, 0x2601), /* CNEX Granby */
2924 .driver_data = NVME_QUIRK_LIGHTNVM, },
b60503ba 2925 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
c74dc780 2926 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) },
124298bd 2927 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
b60503ba
MW		 2928 { 0, }
2929};
2930MODULE_DEVICE_TABLE(pci, nvme_id_table);
2931
2932static struct pci_driver nvme_driver = {
2933 .name = "nvme",
2934 .id_table = nvme_id_table,
2935 .probe = nvme_probe,
8d85fce7 2936 .remove = nvme_remove,
09ece142 2937 .shutdown = nvme_shutdown,
cd638946
KB		 2938 .driver = {
2939 .pm = &nvme_dev_pm_ops,
2940 },
74d986ab 2941 .sriov_configure = pci_sriov_configure_simple,
b60503ba
MW		 2942 .err_handler = &nvme_err_handler,
2943};
2944
2945static int __init nvme_init(void)
2946{
612b7286 2947 BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2);
9a6327d2 2948 return pci_register_driver(&nvme_driver);
b60503ba
MW		 2949}
2950
2951static void __exit nvme_exit(void)
2952{
2953 pci_unregister_driver(&nvme_driver);
03e0f3a6 2954 flush_workqueue(nvme_wq);
21bd78bc 2955 _nvme_check_size();
b60503ba
MW		 2956}
2957
2958MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2959MODULE_LICENSE("GPL");
c78b4713 2960MODULE_VERSION("1.0");
b60503ba
MW		 2961module_init(nvme_init);
2962module_exit(nvme_exit);
Linux 6.x block layer and io_uring tree(s)