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nvme-pci: Free tagset if no IO queues
[linux-2.6-block.git] / drivers / nvme / host / pci.c
CommitLineData
5f37396d 1// SPDX-License-Identifier: GPL-2.0
b60503ba
MW		 2/*
3 * NVM Express device driver
6eb0d698 4 * Copyright (c) 2011-2014, Intel Corporation.
b60503ba
MW		 5 */
6
a0a3408e 7#include <linux/aer.h>
18119775 8#include <linux/async.h>
b60503ba 9#include <linux/blkdev.h>
a4aea562 10#include <linux/blk-mq.h>
dca51e78 11#include <linux/blk-mq-pci.h>
ff5350a8 12#include <linux/dmi.h>
b60503ba
MW		 13#include <linux/init.h>
14#include <linux/interrupt.h>
15#include <linux/io.h>
b60503ba
MW		 16#include <linux/mm.h>
17#include <linux/module.h>
77bf25ea 18#include <linux/mutex.h>
d0877473 19#include <linux/once.h>
b60503ba 20#include <linux/pci.h>
d916b1be 21#include <linux/suspend.h>
e1e5e564 22#include <linux/t10-pi.h>
b60503ba 23#include <linux/types.h>
2f8e2c87 24#include <linux/io-64-nonatomic-lo-hi.h>
a98e58e5 25#include <linux/sed-opal.h>
0f238ff5 26#include <linux/pci-p2pdma.h>
797a796a 27
604c01d5 28#include "trace.h"
f11bb3e2
CH		 29#include "nvme.h"
30
c1e0cc7e 31#define SQ_SIZE(q) ((q)->q_depth << (q)->sqes)
8a1d09a6 32#define CQ_SIZE(q) ((q)->q_depth * sizeof(struct nvme_completion))
c965809c 33
a7a7cbe3 34#define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc))
9d43cf64 35
943e942e
JA		 36/*
37 * These can be higher, but we need to ensure that any command doesn't
38 * require an sg allocation that needs more than a page of data.
39 */
40#define NVME_MAX_KB_SZ 4096
41#define NVME_MAX_SEGS 127
42
58ffacb5
MW		 43static int use_threaded_interrupts;
44module_param(use_threaded_interrupts, int, 0);
45
8ffaadf7 46static bool use_cmb_sqes = true;
69f4eb9f 47module_param(use_cmb_sqes, bool, 0444);
8ffaadf7
JD		 48MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
49
87ad72a5
CH		 50static unsigned int max_host_mem_size_mb = 128;
51module_param(max_host_mem_size_mb, uint, 0444);
52MODULE_PARM_DESC(max_host_mem_size_mb,
53 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
1fa6aead 54
a7a7cbe3
CK		 55static unsigned int sgl_threshold = SZ_32K;
56module_param(sgl_threshold, uint, 0644);
57MODULE_PARM_DESC(sgl_threshold,
58 "Use SGLs when average request segment size is larger or equal to "
59 "this size. Use 0 to disable SGLs.");
60
b27c1e68 61static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
62static const struct kernel_param_ops io_queue_depth_ops = {
63 .set = io_queue_depth_set,
64 .get = param_get_int,
65};
66
67static int io_queue_depth = 1024;
68module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
69MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2");
70
3b6592f7 71static int write_queues;
483178f3 72module_param(write_queues, int, 0644);
3b6592f7
JA		 73MODULE_PARM_DESC(write_queues,
74 "Number of queues to use for writes. If not set, reads and writes "
75 "will share a queue set.");
76
a232ea0e 77static int poll_queues;
483178f3 78module_param(poll_queues, int, 0644);
4b04cc6a
JA		 79MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO.");
80
1c63dc66
CH		 81struct nvme_dev;
82struct nvme_queue;
b3fffdef 83
a5cdb68c 84static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
8fae268b 85static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode);
d4b4ff8e 86
1c63dc66
CH		 87/*
88 * Represents an NVM Express device. Each nvme_dev is a PCI function.
89 */
90struct nvme_dev {
147b27e4 91 struct nvme_queue *queues;
1c63dc66
CH		 92 struct blk_mq_tag_set tagset;
93 struct blk_mq_tag_set admin_tagset;
94 u32 __iomem *dbs;
95 struct device *dev;
96 struct dma_pool *prp_page_pool;
97 struct dma_pool *prp_small_pool;
1c63dc66
CH		 98 unsigned online_queues;
99 unsigned max_qid;
e20ba6e1 100 unsigned io_queues[HCTX_MAX_TYPES];
22b55601 101 unsigned int num_vecs;
1c63dc66 102 int q_depth;
c1e0cc7e 103 int io_sqes;
1c63dc66 104 u32 db_stride;
1c63dc66 105 void __iomem *bar;
97f6ef64 106 unsigned long bar_mapped_size;
5c8809e6 107 struct work_struct remove_work;
77bf25ea 108 struct mutex shutdown_lock;
1c63dc66 109 bool subsystem;
1c63dc66 110 u64 cmb_size;
0f238ff5 111 bool cmb_use_sqes;
1c63dc66 112 u32 cmbsz;
202021c1 113 u32 cmbloc;
1c63dc66 114 struct nvme_ctrl ctrl;
d916b1be 115 u32 last_ps;
87ad72a5 116
943e942e
JA		 117 mempool_t *iod_mempool;
118
87ad72a5 119 /* shadow doorbell buffer support: */
f9f38e33
HK		 120 u32 *dbbuf_dbs;
121 dma_addr_t dbbuf_dbs_dma_addr;
122 u32 *dbbuf_eis;
123 dma_addr_t dbbuf_eis_dma_addr;
87ad72a5
CH		 124
125 /* host memory buffer support: */
126 u64 host_mem_size;
127 u32 nr_host_mem_descs;
4033f35d 128 dma_addr_t host_mem_descs_dma;
87ad72a5
CH		 129 struct nvme_host_mem_buf_desc *host_mem_descs;
130 void **host_mem_desc_bufs;
4d115420 131};
1fa6aead 132
b27c1e68 133static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
134{
135 int n = 0, ret;
136
137 ret = kstrtoint(val, 10, &n);
138 if (ret != 0 || n < 2)
139 return -EINVAL;
140
141 return param_set_int(val, kp);
142}
143
f9f38e33
HK		 144static inline unsigned int sq_idx(unsigned int qid, u32 stride)
145{
146 return qid * 2 * stride;
147}
148
149static inline unsigned int cq_idx(unsigned int qid, u32 stride)
150{
151 return (qid * 2 + 1) * stride;
152}
153
1c63dc66
CH		 154static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
155{
156 return container_of(ctrl, struct nvme_dev, ctrl);
157}
158
b60503ba
MW		 159/*
160 * An NVM Express queue. Each device has at least two (one for admin
161 * commands and one for I/O commands).
162 */
163struct nvme_queue {
091b6092 164 struct nvme_dev *dev;
1ab0cd69 165 spinlock_t sq_lock;
c1e0cc7e 166 void *sq_cmds;
3a7afd8e
CH		 167 /* only used for poll queues: */
168 spinlock_t cq_poll_lock ____cacheline_aligned_in_smp;
b60503ba 169 volatile struct nvme_completion *cqes;
42483228 170 struct blk_mq_tags **tags;
b60503ba
MW		 171 dma_addr_t sq_dma_addr;
172 dma_addr_t cq_dma_addr;
b60503ba
MW		 173 u32 __iomem *q_db;
174 u16 q_depth;
7c349dde 175 u16 cq_vector;
b60503ba 176 u16 sq_tail;
04f3eafd 177 u16 last_sq_tail;
b60503ba 178 u16 cq_head;
68fa9dbe 179 u16 last_cq_head;
c30341dc 180 u16 qid;
e9539f47 181 u8 cq_phase;
c1e0cc7e 182 u8 sqes;
4e224106
CH		 183 unsigned long flags;
184#define NVMEQ_ENABLED 0
63223078 185#define NVMEQ_SQ_CMB 1
d1ed6aa1 186#define NVMEQ_DELETE_ERROR 2
7c349dde 187#define NVMEQ_POLLED 3
f9f38e33
HK		 188 u32 *dbbuf_sq_db;
189 u32 *dbbuf_cq_db;
190 u32 *dbbuf_sq_ei;
191 u32 *dbbuf_cq_ei;
d1ed6aa1 192 struct completion delete_done;
b60503ba
MW		 193};
194
71bd150c 195/*
9b048119
CH		 196 * The nvme_iod describes the data in an I/O.
197 *
198 * The sg pointer contains the list of PRP/SGL chunk allocations in addition
199 * to the actual struct scatterlist.
71bd150c
CH		 200 */
201struct nvme_iod {
d49187e9 202 struct nvme_request req;
f4800d6d 203 struct nvme_queue *nvmeq;
a7a7cbe3 204 bool use_sgl;
f4800d6d 205 int aborted;
71bd150c 206 int npages; /* In the PRP list. 0 means small pool in use */
71bd150c 207 int nents; /* Used in scatterlist */
71bd150c 208 dma_addr_t first_dma;
dff824b2 209 unsigned int dma_len; /* length of single DMA segment mapping */
783b94bd 210 dma_addr_t meta_dma;
f4800d6d 211 struct scatterlist *sg;
b60503ba
MW		 212};
213
3b6592f7
JA		 214static unsigned int max_io_queues(void)
215{
4b04cc6a 216 return num_possible_cpus() + write_queues + poll_queues;
3b6592f7
JA		 217}
218
219static unsigned int max_queue_count(void)
220{
221 /* IO queues + admin queue */
222 return 1 + max_io_queues();
223}
224
f9f38e33
HK		 225static inline unsigned int nvme_dbbuf_size(u32 stride)
226{
3b6592f7 227 return (max_queue_count() * 8 * stride);
f9f38e33
HK		 228}
229
230static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
231{
232 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
233
234 if (dev->dbbuf_dbs)
235 return 0;
236
237 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
238 &dev->dbbuf_dbs_dma_addr,
239 GFP_KERNEL);
240 if (!dev->dbbuf_dbs)
241 return -ENOMEM;
242 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
243 &dev->dbbuf_eis_dma_addr,
244 GFP_KERNEL);
245 if (!dev->dbbuf_eis) {
246 dma_free_coherent(dev->dev, mem_size,
247 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
248 dev->dbbuf_dbs = NULL;
249 return -ENOMEM;
250 }
251
252 return 0;
253}
254
255static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
256{
257 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
258
259 if (dev->dbbuf_dbs) {
260 dma_free_coherent(dev->dev, mem_size,
261 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
262 dev->dbbuf_dbs = NULL;
263 }
264 if (dev->dbbuf_eis) {
265 dma_free_coherent(dev->dev, mem_size,
266 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
267 dev->dbbuf_eis = NULL;
268 }
269}
270
271static void nvme_dbbuf_init(struct nvme_dev *dev,
272 struct nvme_queue *nvmeq, int qid)
273{
274 if (!dev->dbbuf_dbs || !qid)
275 return;
276
277 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
278 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
279 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
280 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
281}
282
283static void nvme_dbbuf_set(struct nvme_dev *dev)
284{
285 struct nvme_command c;
286
287 if (!dev->dbbuf_dbs)
288 return;
289
290 memset(&c, 0, sizeof(c));
291 c.dbbuf.opcode = nvme_admin_dbbuf;
292 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
293 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
294
295 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
9bdcfb10 296 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
f9f38e33
HK		 297 /* Free memory and continue on */
298 nvme_dbbuf_dma_free(dev);
299 }
300}
301
302static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
303{
304 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
305}
306
307/* Update dbbuf and return true if an MMIO is required */
308static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
309 volatile u32 *dbbuf_ei)
310{
311 if (dbbuf_db) {
312 u16 old_value;
313
314 /*
315 * Ensure that the queue is written before updating
316 * the doorbell in memory
317 */
318 wmb();
319
320 old_value = *dbbuf_db;
321 *dbbuf_db = value;
322
f1ed3df2
MW		 323 /*
324 * Ensure that the doorbell is updated before reading the event
325 * index from memory. The controller needs to provide similar
326 * ordering to ensure the envent index is updated before reading
327 * the doorbell.
328 */
329 mb();
330
f9f38e33
HK		 331 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value))
332 return false;
333 }
334
335 return true;
b60503ba
MW		 336}
337
ac3dd5bd
JA		 338/*
339 * Will slightly overestimate the number of pages needed. This is OK
340 * as it only leads to a small amount of wasted memory for the lifetime of
341 * the I/O.
342 */
343static int nvme_npages(unsigned size, struct nvme_dev *dev)
344{
5fd4ce1b
CH		 345 unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size,
346 dev->ctrl.page_size);
ac3dd5bd
JA		 347 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
348}
349
a7a7cbe3
CK		 350/*
351 * Calculates the number of pages needed for the SGL segments. For example a 4k
352 * page can accommodate 256 SGL descriptors.
353 */
354static int nvme_pci_npages_sgl(unsigned int num_seg)
ac3dd5bd 355{
a7a7cbe3 356 return DIV_ROUND_UP(num_seg * sizeof(struct nvme_sgl_desc), PAGE_SIZE);
f4800d6d 357}
ac3dd5bd 358
a7a7cbe3
CK		 359static unsigned int nvme_pci_iod_alloc_size(struct nvme_dev *dev,
360 unsigned int size, unsigned int nseg, bool use_sgl)
f4800d6d 361{
a7a7cbe3
CK		 362 size_t alloc_size;
363
364 if (use_sgl)
365 alloc_size = sizeof(__le64 *) * nvme_pci_npages_sgl(nseg);
366 else
367 alloc_size = sizeof(__le64 *) * nvme_npages(size, dev);
368
369 return alloc_size + sizeof(struct scatterlist) * nseg;
f4800d6d 370}
ac3dd5bd 371
a4aea562
MB		 372static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
373 unsigned int hctx_idx)
e85248e5 374{
a4aea562 375 struct nvme_dev *dev = data;
147b27e4 376 struct nvme_queue *nvmeq = &dev->queues[0];
a4aea562 377
42483228
KB		 378 WARN_ON(hctx_idx != 0);
379 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
380 WARN_ON(nvmeq->tags);
381
a4aea562 382 hctx->driver_data = nvmeq;
42483228 383 nvmeq->tags = &dev->admin_tagset.tags[0];
a4aea562 384 return 0;
e85248e5
MW		 385}
386
4af0e21c
KB		 387static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
388{
389 struct nvme_queue *nvmeq = hctx->driver_data;
390
391 nvmeq->tags = NULL;
392}
393
a4aea562
MB		 394static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
395 unsigned int hctx_idx)
b60503ba 396{
a4aea562 397 struct nvme_dev *dev = data;
147b27e4 398 struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
a4aea562 399
42483228
KB		 400 if (!nvmeq->tags)
401 nvmeq->tags = &dev->tagset.tags[hctx_idx];
b60503ba 402
42483228 403 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
a4aea562
MB		 404 hctx->driver_data = nvmeq;
405 return 0;
b60503ba
MW		 406}
407
d6296d39
CH		 408static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req,
409 unsigned int hctx_idx, unsigned int numa_node)
b60503ba 410{
d6296d39 411 struct nvme_dev *dev = set->driver_data;
f4800d6d 412 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
0350815a 413 int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0;
147b27e4 414 struct nvme_queue *nvmeq = &dev->queues[queue_idx];
a4aea562
MB		 415
416 BUG_ON(!nvmeq);
f4800d6d 417 iod->nvmeq = nvmeq;
59e29ce6
SG		 418
419 nvme_req(req)->ctrl = &dev->ctrl;
a4aea562
MB		 420 return 0;
421}
422
3b6592f7
JA		 423static int queue_irq_offset(struct nvme_dev *dev)
424{
425 /* if we have more than 1 vec, admin queue offsets us by 1 */
426 if (dev->num_vecs > 1)
427 return 1;
428
429 return 0;
430}
431
dca51e78
CH		 432static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
433{
434 struct nvme_dev *dev = set->driver_data;
3b6592f7
JA		 435 int i, qoff, offset;
436
437 offset = queue_irq_offset(dev);
438 for (i = 0, qoff = 0; i < set->nr_maps; i++) {
439 struct blk_mq_queue_map *map = &set->map[i];
440
441 map->nr_queues = dev->io_queues[i];
442 if (!map->nr_queues) {
e20ba6e1 443 BUG_ON(i == HCTX_TYPE_DEFAULT);
7e849dd9 444 continue;
3b6592f7
JA		 445 }
446
4b04cc6a
JA		 447 /*
448 * The poll queue(s) doesn't have an IRQ (and hence IRQ
449 * affinity), so use the regular blk-mq cpu mapping
450 */
3b6592f7 451 map->queue_offset = qoff;
cb9e0e50 452 if (i != HCTX_TYPE_POLL && offset)
4b04cc6a
JA		 453 blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset);
454 else
455 blk_mq_map_queues(map);
3b6592f7
JA		 456 qoff += map->nr_queues;
457 offset += map->nr_queues;
458 }
459
460 return 0;
dca51e78
CH		 461}
462
04f3eafd
JA		 463/*
464 * Write sq tail if we are asked to, or if the next command would wrap.
465 */
466static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq)
467{
468 if (!write_sq) {
469 u16 next_tail = nvmeq->sq_tail + 1;
470
471 if (next_tail == nvmeq->q_depth)
472 next_tail = 0;
473 if (next_tail != nvmeq->last_sq_tail)
474 return;
475 }
476
477 if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail,
478 nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei))
479 writel(nvmeq->sq_tail, nvmeq->q_db);
480 nvmeq->last_sq_tail = nvmeq->sq_tail;
481}
482
b60503ba 483/**
90ea5ca4 484 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
b60503ba
MW		 485 * @nvmeq: The queue to use
486 * @cmd: The command to send
04f3eafd 487 * @write_sq: whether to write to the SQ doorbell
b60503ba 488 */
04f3eafd
JA		 489static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd,
490 bool write_sq)
b60503ba 491{
90ea5ca4 492 spin_lock(&nvmeq->sq_lock);
c1e0cc7e
BH		 493 memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes),
494 cmd, sizeof(*cmd));
90ea5ca4
CH		 495 if (++nvmeq->sq_tail == nvmeq->q_depth)
496 nvmeq->sq_tail = 0;
04f3eafd
JA		 497 nvme_write_sq_db(nvmeq, write_sq);
498 spin_unlock(&nvmeq->sq_lock);
499}
500
501static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx)
502{
503 struct nvme_queue *nvmeq = hctx->driver_data;
504
505 spin_lock(&nvmeq->sq_lock);
506 if (nvmeq->sq_tail != nvmeq->last_sq_tail)
507 nvme_write_sq_db(nvmeq, true);
90ea5ca4 508 spin_unlock(&nvmeq->sq_lock);
b60503ba
MW		 509}
510
a7a7cbe3 511static void **nvme_pci_iod_list(struct request *req)
b60503ba 512{
f4800d6d 513 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3 514 return (void **)(iod->sg + blk_rq_nr_phys_segments(req));
b60503ba
MW		 515}
516
955b1b5a
MI		 517static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req)
518{
519 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
20469a37 520 int nseg = blk_rq_nr_phys_segments(req);
955b1b5a
MI		 521 unsigned int avg_seg_size;
522
20469a37
KB		 523 if (nseg == 0)
524 return false;
525
526 avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
955b1b5a
MI		 527
528 if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1))))
529 return false;
530 if (!iod->nvmeq->qid)
531 return false;
532 if (!sgl_threshold || avg_seg_size < sgl_threshold)
533 return false;
534 return true;
535}
536
7fe07d14 537static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
b60503ba 538{
f4800d6d 539 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3
CK		 540 const int last_prp = dev->ctrl.page_size / sizeof(__le64) - 1;
541 dma_addr_t dma_addr = iod->first_dma, next_dma_addr;
eca18b23 542 int i;
eca18b23 543
dff824b2 544 if (iod->dma_len) {
f2fa006f
IR		 545 dma_unmap_page(dev->dev, dma_addr, iod->dma_len,
546 rq_dma_dir(req));
dff824b2 547 return;
7fe07d14
CH		 548 }
549
dff824b2
CH		 550 WARN_ON_ONCE(!iod->nents);
551
7f73eac3
LG		 552 if (is_pci_p2pdma_page(sg_page(iod->sg)))
553 pci_p2pdma_unmap_sg(dev->dev, iod->sg, iod->nents,
554 rq_dma_dir(req));
555 else
dff824b2
CH		 556 dma_unmap_sg(dev->dev, iod->sg, iod->nents, rq_dma_dir(req));
557
558
eca18b23 559 if (iod->npages == 0)
a7a7cbe3
CK		 560 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0],
561 dma_addr);
562
eca18b23 563 for (i = 0; i < iod->npages; i++) {
a7a7cbe3
CK		 564 void *addr = nvme_pci_iod_list(req)[i];
565
566 if (iod->use_sgl) {
567 struct nvme_sgl_desc *sg_list = addr;
568
569 next_dma_addr =
570 le64_to_cpu((sg_list[SGES_PER_PAGE - 1]).addr);
571 } else {
572 __le64 *prp_list = addr;
573
574 next_dma_addr = le64_to_cpu(prp_list[last_prp]);
575 }
576
577 dma_pool_free(dev->prp_page_pool, addr, dma_addr);
578 dma_addr = next_dma_addr;
eca18b23 579 }
ac3dd5bd 580
d43f1ccf 581 mempool_free(iod->sg, dev->iod_mempool);
b4ff9c8d
KB		 582}
583
d0877473
KB		 584static void nvme_print_sgl(struct scatterlist *sgl, int nents)
585{
586 int i;
587 struct scatterlist *sg;
588
589 for_each_sg(sgl, sg, nents, i) {
590 dma_addr_t phys = sg_phys(sg);
591 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
592 "dma_address:%pad dma_length:%d\n",
593 i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
594 sg_dma_len(sg));
595 }
596}
597
a7a7cbe3
CK		 598static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
599 struct request *req, struct nvme_rw_command *cmnd)
ff22b54f 600{
f4800d6d 601 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
99802a7a 602 struct dma_pool *pool;
b131c61d 603 int length = blk_rq_payload_bytes(req);
eca18b23 604 struct scatterlist *sg = iod->sg;
ff22b54f
MW		 605 int dma_len = sg_dma_len(sg);
606 u64 dma_addr = sg_dma_address(sg);
5fd4ce1b 607 u32 page_size = dev->ctrl.page_size;
f137e0f1 608 int offset = dma_addr & (page_size - 1);
e025344c 609 __le64 *prp_list;
a7a7cbe3 610 void **list = nvme_pci_iod_list(req);
e025344c 611 dma_addr_t prp_dma;
eca18b23 612 int nprps, i;
ff22b54f 613
1d090624 614 length -= (page_size - offset);
5228b328
JS		 615 if (length <= 0) {
616 iod->first_dma = 0;
a7a7cbe3 617 goto done;
5228b328 618 }
ff22b54f 619
1d090624 620 dma_len -= (page_size - offset);
ff22b54f 621 if (dma_len) {
1d090624 622 dma_addr += (page_size - offset);
ff22b54f
MW		 623 } else {
624 sg = sg_next(sg);
625 dma_addr = sg_dma_address(sg);
626 dma_len = sg_dma_len(sg);
627 }
628
1d090624 629 if (length <= page_size) {
edd10d33 630 iod->first_dma = dma_addr;
a7a7cbe3 631 goto done;
e025344c
SMM		 632 }
633
1d090624 634 nprps = DIV_ROUND_UP(length, page_size);
99802a7a
MW		 635 if (nprps <= (256 / 8)) {
636 pool = dev->prp_small_pool;
eca18b23 637 iod->npages = 0;
99802a7a
MW		 638 } else {
639 pool = dev->prp_page_pool;
eca18b23 640 iod->npages = 1;
99802a7a
MW		 641 }
642
69d2b571 643 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
b77954cb 644 if (!prp_list) {
edd10d33 645 iod->first_dma = dma_addr;
eca18b23 646 iod->npages = -1;
86eea289 647 return BLK_STS_RESOURCE;
b77954cb 648 }
eca18b23
MW		 649 list[0] = prp_list;
650 iod->first_dma = prp_dma;
e025344c
SMM		 651 i = 0;
652 for (;;) {
1d090624 653 if (i == page_size >> 3) {
e025344c 654 __le64 *old_prp_list = prp_list;
69d2b571 655 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
eca18b23 656 if (!prp_list)
86eea289 657 return BLK_STS_RESOURCE;
eca18b23 658 list[iod->npages++] = prp_list;
7523d834
MW		 659 prp_list[0] = old_prp_list[i - 1];
660 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
661 i = 1;
e025344c
SMM		 662 }
663 prp_list[i++] = cpu_to_le64(dma_addr);
1d090624
KB		 664 dma_len -= page_size;
665 dma_addr += page_size;
666 length -= page_size;
e025344c
SMM		 667 if (length <= 0)
668 break;
669 if (dma_len > 0)
670 continue;
86eea289
KB		 671 if (unlikely(dma_len < 0))
672 goto bad_sgl;
e025344c
SMM		 673 sg = sg_next(sg);
674 dma_addr = sg_dma_address(sg);
675 dma_len = sg_dma_len(sg);
ff22b54f
MW		 676 }
677
a7a7cbe3
CK		 678done:
679 cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
680 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
681
86eea289
KB		 682 return BLK_STS_OK;
683
684 bad_sgl:
d0877473
KB		 685 WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents),
686 "Invalid SGL for payload:%d nents:%d\n",
687 blk_rq_payload_bytes(req), iod->nents);
86eea289 688 return BLK_STS_IOERR;
ff22b54f
MW		 689}
690
a7a7cbe3
CK		 691static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
692 struct scatterlist *sg)
693{
694 sge->addr = cpu_to_le64(sg_dma_address(sg));
695 sge->length = cpu_to_le32(sg_dma_len(sg));
696 sge->type = NVME_SGL_FMT_DATA_DESC << 4;
697}
698
699static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
700 dma_addr_t dma_addr, int entries)
701{
702 sge->addr = cpu_to_le64(dma_addr);
703 if (entries < SGES_PER_PAGE) {
704 sge->length = cpu_to_le32(entries * sizeof(*sge));
705 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
706 } else {
707 sge->length = cpu_to_le32(PAGE_SIZE);
708 sge->type = NVME_SGL_FMT_SEG_DESC << 4;
709 }
710}
711
712static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
b0f2853b 713 struct request *req, struct nvme_rw_command *cmd, int entries)
a7a7cbe3
CK		 714{
715 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3
CK		 716 struct dma_pool *pool;
717 struct nvme_sgl_desc *sg_list;
718 struct scatterlist *sg = iod->sg;
a7a7cbe3 719 dma_addr_t sgl_dma;
b0f2853b 720 int i = 0;
a7a7cbe3 721
a7a7cbe3
CK		 722 /* setting the transfer type as SGL */
723 cmd->flags = NVME_CMD_SGL_METABUF;
724
b0f2853b 725 if (entries == 1) {
a7a7cbe3
CK		 726 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
727 return BLK_STS_OK;
728 }
729
730 if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
731 pool = dev->prp_small_pool;
732 iod->npages = 0;
733 } else {
734 pool = dev->prp_page_pool;
735 iod->npages = 1;
736 }
737
738 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
739 if (!sg_list) {
740 iod->npages = -1;
741 return BLK_STS_RESOURCE;
742 }
743
744 nvme_pci_iod_list(req)[0] = sg_list;
745 iod->first_dma = sgl_dma;
746
747 nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
748
749 do {
750 if (i == SGES_PER_PAGE) {
751 struct nvme_sgl_desc *old_sg_desc = sg_list;
752 struct nvme_sgl_desc *link = &old_sg_desc[i - 1];
753
754 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
755 if (!sg_list)
756 return BLK_STS_RESOURCE;
757
758 i = 0;
759 nvme_pci_iod_list(req)[iod->npages++] = sg_list;
760 sg_list[i++] = *link;
761 nvme_pci_sgl_set_seg(link, sgl_dma, entries);
762 }
763
764 nvme_pci_sgl_set_data(&sg_list[i++], sg);
a7a7cbe3 765 sg = sg_next(sg);
b0f2853b 766 } while (--entries > 0);
a7a7cbe3 767
a7a7cbe3
CK		 768 return BLK_STS_OK;
769}
770
dff824b2
CH		 771static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev,
772 struct request *req, struct nvme_rw_command *cmnd,
773 struct bio_vec *bv)
774{
775 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
776 unsigned int first_prp_len = dev->ctrl.page_size - bv->bv_offset;
777
778 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
779 if (dma_mapping_error(dev->dev, iod->first_dma))
780 return BLK_STS_RESOURCE;
781 iod->dma_len = bv->bv_len;
782
783 cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma);
784 if (bv->bv_len > first_prp_len)
785 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len);
786 return 0;
787}
788
29791057
CH		 789static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev,
790 struct request *req, struct nvme_rw_command *cmnd,
791 struct bio_vec *bv)
792{
793 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
794
795 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
796 if (dma_mapping_error(dev->dev, iod->first_dma))
797 return BLK_STS_RESOURCE;
798 iod->dma_len = bv->bv_len;
799
049bf372 800 cmnd->flags = NVME_CMD_SGL_METABUF;
29791057
CH		 801 cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma);
802 cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len);
803 cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4;
804 return 0;
805}
806
fc17b653 807static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
b131c61d 808 struct nvme_command *cmnd)
d29ec824 809{
f4800d6d 810 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
70479b71 811 blk_status_t ret = BLK_STS_RESOURCE;
b0f2853b 812 int nr_mapped;
d29ec824 813
dff824b2
CH		 814 if (blk_rq_nr_phys_segments(req) == 1) {
815 struct bio_vec bv = req_bvec(req);
816
817 if (!is_pci_p2pdma_page(bv.bv_page)) {
818 if (bv.bv_offset + bv.bv_len <= dev->ctrl.page_size * 2)
819 return nvme_setup_prp_simple(dev, req,
820 &cmnd->rw, &bv);
29791057
CH		 821
822 if (iod->nvmeq->qid &&
823 dev->ctrl.sgls & ((1 << 0) | (1 << 1)))
824 return nvme_setup_sgl_simple(dev, req,
825 &cmnd->rw, &bv);
dff824b2
CH		 826 }
827 }
828
829 iod->dma_len = 0;
d43f1ccf
CH		 830 iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC);
831 if (!iod->sg)
832 return BLK_STS_RESOURCE;
f9d03f96 833 sg_init_table(iod->sg, blk_rq_nr_phys_segments(req));
70479b71 834 iod->nents = blk_rq_map_sg(req->q, req, iod->sg);
ba1ca37e
CH		 835 if (!iod->nents)
836 goto out;
d29ec824 837
e0596ab2 838 if (is_pci_p2pdma_page(sg_page(iod->sg)))
2b9f4bb2
LG		 839 nr_mapped = pci_p2pdma_map_sg_attrs(dev->dev, iod->sg,
840 iod->nents, rq_dma_dir(req), DMA_ATTR_NO_WARN);
e0596ab2
LG		 841 else
842 nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents,
70479b71 843 rq_dma_dir(req), DMA_ATTR_NO_WARN);
b0f2853b 844 if (!nr_mapped)
ba1ca37e 845 goto out;
d29ec824 846
70479b71 847 iod->use_sgl = nvme_pci_use_sgls(dev, req);
955b1b5a 848 if (iod->use_sgl)
b0f2853b 849 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped);
a7a7cbe3
CK		 850 else
851 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
4aedb705 852out:
86eea289 853 if (ret != BLK_STS_OK)
4aedb705
CH		 854 nvme_unmap_data(dev, req);
855 return ret;
856}
3045c0d0 857
4aedb705
CH		 858static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req,
859 struct nvme_command *cmnd)
860{
861 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
00df5cb4 862
4aedb705
CH		 863 iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req),
864 rq_dma_dir(req), 0);
865 if (dma_mapping_error(dev->dev, iod->meta_dma))
866 return BLK_STS_IOERR;
867 cmnd->rw.metadata = cpu_to_le64(iod->meta_dma);
868 return 0;
00df5cb4
MW		 869}
870
d29ec824
CH		 871/*
872 * NOTE: ns is NULL when called on the admin queue.
873 */
fc17b653 874static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
a4aea562 875 const struct blk_mq_queue_data *bd)
edd10d33 876{
a4aea562
MB		 877 struct nvme_ns *ns = hctx->queue->queuedata;
878 struct nvme_queue *nvmeq = hctx->driver_data;
d29ec824 879 struct nvme_dev *dev = nvmeq->dev;
a4aea562 880 struct request *req = bd->rq;
9b048119 881 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
ba1ca37e 882 struct nvme_command cmnd;
ebe6d874 883 blk_status_t ret;
e1e5e564 884
9b048119
CH		 885 iod->aborted = 0;
886 iod->npages = -1;
887 iod->nents = 0;
888
d1f06f4a
JA		 889 /*
890 * We should not need to do this, but we're still using this to
891 * ensure we can drain requests on a dying queue.
892 */
4e224106 893 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
d1f06f4a
JA		 894 return BLK_STS_IOERR;
895
f9d03f96 896 ret = nvme_setup_cmd(ns, req, &cmnd);
fc17b653 897 if (ret)
f4800d6d 898 return ret;
a4aea562 899
fc17b653 900 if (blk_rq_nr_phys_segments(req)) {
b131c61d 901 ret = nvme_map_data(dev, req, &cmnd);
fc17b653 902 if (ret)
9b048119 903 goto out_free_cmd;
fc17b653 904 }
a4aea562 905
4aedb705
CH		 906 if (blk_integrity_rq(req)) {
907 ret = nvme_map_metadata(dev, req, &cmnd);
908 if (ret)
909 goto out_unmap_data;
910 }
911
aae239e1 912 blk_mq_start_request(req);
04f3eafd 913 nvme_submit_cmd(nvmeq, &cmnd, bd->last);
fc17b653 914 return BLK_STS_OK;
4aedb705
CH		 915out_unmap_data:
916 nvme_unmap_data(dev, req);
f9d03f96
CH		 917out_free_cmd:
918 nvme_cleanup_cmd(req);
ba1ca37e 919 return ret;
b60503ba 920}
e1e5e564 921
77f02a7a 922static void nvme_pci_complete_rq(struct request *req)
eee417b0 923{
f4800d6d 924 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
4aedb705 925 struct nvme_dev *dev = iod->nvmeq->dev;
a4aea562 926
915f04c9 927 nvme_cleanup_cmd(req);
4aedb705
CH		 928 if (blk_integrity_rq(req))
929 dma_unmap_page(dev->dev, iod->meta_dma,
930 rq_integrity_vec(req)->bv_len, rq_data_dir(req));
b15c592d 931 if (blk_rq_nr_phys_segments(req))
4aedb705 932 nvme_unmap_data(dev, req);
77f02a7a 933 nvme_complete_rq(req);
b60503ba
MW		 934}
935
d783e0bd 936/* We read the CQE phase first to check if the rest of the entry is valid */
750dde44 937static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq)
d783e0bd 938{
750dde44
CH		 939 return (le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) ==
940 nvmeq->cq_phase;
d783e0bd
MR		 941}
942
eb281c82 943static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
b60503ba 944{
eb281c82 945 u16 head = nvmeq->cq_head;
adf68f21 946
397c699f
KB		 947 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
948 nvmeq->dbbuf_cq_ei))
949 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
eb281c82 950}
aae239e1 951
5cb525c8 952static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx)
83a12fb7 953{
5cb525c8 954 volatile struct nvme_completion *cqe = &nvmeq->cqes[idx];
83a12fb7 955 struct request *req;
adf68f21 956
83a12fb7
SG		 957 if (unlikely(cqe->command_id >= nvmeq->q_depth)) {
958 dev_warn(nvmeq->dev->ctrl.device,
959 "invalid id %d completed on queue %d\n",
960 cqe->command_id, le16_to_cpu(cqe->sq_id));
961 return;
b60503ba
MW		 962 }
963
83a12fb7
SG		 964 /*
965 * AEN requests are special as they don't time out and can
966 * survive any kind of queue freeze and often don't respond to
967 * aborts. We don't even bother to allocate a struct request
968 * for them but rather special case them here.
969 */
970 if (unlikely(nvmeq->qid == 0 &&
38dabe21 971 cqe->command_id >= NVME_AQ_BLK_MQ_DEPTH)) {
83a12fb7
SG		 972 nvme_complete_async_event(&nvmeq->dev->ctrl,
973 cqe->status, &cqe->result);
a0fa9647 974 return;
83a12fb7 975 }
b60503ba 976
83a12fb7 977 req = blk_mq_tag_to_rq(*nvmeq->tags, cqe->command_id);
604c01d5 978 trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail);
83a12fb7
SG		 979 nvme_end_request(req, cqe->status, cqe->result);
980}
b60503ba 981
5cb525c8 982static void nvme_complete_cqes(struct nvme_queue *nvmeq, u16 start, u16 end)
b60503ba 983{
5cb525c8
JA		 984 while (start != end) {
985 nvme_handle_cqe(nvmeq, start);
986 if (++start == nvmeq->q_depth)
987 start = 0;
988 }
989}
adf68f21 990
5cb525c8
JA		 991static inline void nvme_update_cq_head(struct nvme_queue *nvmeq)
992{
dcca1662 993 if (nvmeq->cq_head == nvmeq->q_depth - 1) {
5cb525c8
JA		 994 nvmeq->cq_head = 0;
995 nvmeq->cq_phase = !nvmeq->cq_phase;
dcca1662
HY		 996 } else {
997 nvmeq->cq_head++;
b60503ba 998 }
a0fa9647
JA		 999}
1000
1052b8ac
JA		 1001static inline int nvme_process_cq(struct nvme_queue *nvmeq, u16 *start,
1002 u16 *end, unsigned int tag)
a0fa9647 1003{
1052b8ac 1004 int found = 0;
b60503ba 1005
5cb525c8 1006 *start = nvmeq->cq_head;
1052b8ac
JA		 1007 while (nvme_cqe_pending(nvmeq)) {
1008 if (tag == -1U || nvmeq->cqes[nvmeq->cq_head].command_id == tag)
1009 found++;
5cb525c8 1010 nvme_update_cq_head(nvmeq);
920d13a8 1011 }
5cb525c8 1012 *end = nvmeq->cq_head;
eb281c82 1013
5cb525c8 1014 if (*start != *end)
920d13a8 1015 nvme_ring_cq_doorbell(nvmeq);
5cb525c8 1016 return found;
b60503ba
MW		 1017}
1018
1019static irqreturn_t nvme_irq(int irq, void *data)
58ffacb5 1020{
58ffacb5 1021 struct nvme_queue *nvmeq = data;
68fa9dbe 1022 irqreturn_t ret = IRQ_NONE;
5cb525c8
JA		 1023 u16 start, end;
1024
3a7afd8e
CH		 1025 /*
1026 * The rmb/wmb pair ensures we see all updates from a previous run of
1027 * the irq handler, even if that was on another CPU.
1028 */
1029 rmb();
68fa9dbe
JA		 1030 if (nvmeq->cq_head != nvmeq->last_cq_head)
1031 ret = IRQ_HANDLED;
5cb525c8 1032 nvme_process_cq(nvmeq, &start, &end, -1);
68fa9dbe 1033 nvmeq->last_cq_head = nvmeq->cq_head;
3a7afd8e 1034 wmb();
5cb525c8 1035
68fa9dbe
JA		 1036 if (start != end) {
1037 nvme_complete_cqes(nvmeq, start, end);
1038 return IRQ_HANDLED;
1039 }
1040
1041 return ret;
58ffacb5
MW		 1042}
1043
1044static irqreturn_t nvme_irq_check(int irq, void *data)
1045{
1046 struct nvme_queue *nvmeq = data;
750dde44 1047 if (nvme_cqe_pending(nvmeq))
d783e0bd
MR		 1048 return IRQ_WAKE_THREAD;
1049 return IRQ_NONE;
58ffacb5
MW		 1050}
1051
0b2a8a9f
CH		 1052/*
1053 * Poll for completions any queue, including those not dedicated to polling.
1054 * Can be called from any context.
1055 */
1056static int nvme_poll_irqdisable(struct nvme_queue *nvmeq, unsigned int tag)
a0fa9647 1057{
3a7afd8e 1058 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
5cb525c8 1059 u16 start, end;
1052b8ac 1060 int found;
a0fa9647 1061
3a7afd8e
CH		 1062 /*
1063 * For a poll queue we need to protect against the polling thread
1064 * using the CQ lock. For normal interrupt driven threads we have
1065 * to disable the interrupt to avoid racing with it.
1066 */
7c349dde 1067 if (test_bit(NVMEQ_POLLED, &nvmeq->flags)) {
3a7afd8e 1068 spin_lock(&nvmeq->cq_poll_lock);
91a509f8 1069 found = nvme_process_cq(nvmeq, &start, &end, tag);
3a7afd8e 1070 spin_unlock(&nvmeq->cq_poll_lock);
91a509f8
CH		 1071 } else {
1072 disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1073 found = nvme_process_cq(nvmeq, &start, &end, tag);
3a7afd8e 1074 enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
91a509f8 1075 }
442e19b7 1076
5cb525c8 1077 nvme_complete_cqes(nvmeq, start, end);
442e19b7 1078 return found;
a0fa9647
JA		 1079}
1080
9743139c 1081static int nvme_poll(struct blk_mq_hw_ctx *hctx)
dabcefab
JA		 1082{
1083 struct nvme_queue *nvmeq = hctx->driver_data;
1084 u16 start, end;
1085 bool found;
1086
1087 if (!nvme_cqe_pending(nvmeq))
1088 return 0;
1089
3a7afd8e 1090 spin_lock(&nvmeq->cq_poll_lock);
9743139c 1091 found = nvme_process_cq(nvmeq, &start, &end, -1);
3a7afd8e 1092 spin_unlock(&nvmeq->cq_poll_lock);
dabcefab
JA		 1093
1094 nvme_complete_cqes(nvmeq, start, end);
1095 return found;
1096}
1097
ad22c355 1098static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
b60503ba 1099{
f866fc42 1100 struct nvme_dev *dev = to_nvme_dev(ctrl);
147b27e4 1101 struct nvme_queue *nvmeq = &dev->queues[0];
a4aea562 1102 struct nvme_command c;
b60503ba 1103
a4aea562
MB		 1104 memset(&c, 0, sizeof(c));
1105 c.common.opcode = nvme_admin_async_event;
ad22c355 1106 c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
04f3eafd 1107 nvme_submit_cmd(nvmeq, &c, true);
f705f837
CH		 1108}
1109
b60503ba 1110static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
f705f837 1111{
b60503ba
MW		 1112 struct nvme_command c;
1113
1114 memset(&c, 0, sizeof(c));
1115 c.delete_queue.opcode = opcode;
1116 c.delete_queue.qid = cpu_to_le16(id);
1117
1c63dc66 1118 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1119}
1120
b60503ba 1121static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
a8e3e0bb 1122 struct nvme_queue *nvmeq, s16 vector)
b60503ba 1123{
b60503ba 1124 struct nvme_command c;
4b04cc6a
JA		 1125 int flags = NVME_QUEUE_PHYS_CONTIG;
1126
7c349dde 1127 if (!test_bit(NVMEQ_POLLED, &nvmeq->flags))
4b04cc6a 1128 flags |= NVME_CQ_IRQ_ENABLED;
b60503ba 1129
d29ec824 1130 /*
16772ae6 1131 * Note: we (ab)use the fact that the prp fields survive if no data
d29ec824
CH		 1132 * is attached to the request.
1133 */
b60503ba
MW		 1134 memset(&c, 0, sizeof(c));
1135 c.create_cq.opcode = nvme_admin_create_cq;
1136 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1137 c.create_cq.cqid = cpu_to_le16(qid);
1138 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1139 c.create_cq.cq_flags = cpu_to_le16(flags);
7c349dde 1140 c.create_cq.irq_vector = cpu_to_le16(vector);
b60503ba 1141
1c63dc66 1142 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1143}
1144
1145static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1146 struct nvme_queue *nvmeq)
1147{
9abd68ef 1148 struct nvme_ctrl *ctrl = &dev->ctrl;
b60503ba 1149 struct nvme_command c;
81c1cd98 1150 int flags = NVME_QUEUE_PHYS_CONTIG;
b60503ba 1151
9abd68ef
JA		 1152 /*
1153 * Some drives have a bug that auto-enables WRRU if MEDIUM isn't
1154 * set. Since URGENT priority is zeroes, it makes all queues
1155 * URGENT.
1156 */
1157 if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ)
1158 flags |= NVME_SQ_PRIO_MEDIUM;
1159
d29ec824 1160 /*
16772ae6 1161 * Note: we (ab)use the fact that the prp fields survive if no data
d29ec824
CH		 1162 * is attached to the request.
1163 */
b60503ba
MW		 1164 memset(&c, 0, sizeof(c));
1165 c.create_sq.opcode = nvme_admin_create_sq;
1166 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1167 c.create_sq.sqid = cpu_to_le16(qid);
1168 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1169 c.create_sq.sq_flags = cpu_to_le16(flags);
1170 c.create_sq.cqid = cpu_to_le16(qid);
1171
1c63dc66 1172 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1173}
1174
1175static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1176{
1177 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1178}
1179
1180static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1181{
1182 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1183}
1184
2a842aca 1185static void abort_endio(struct request *req, blk_status_t error)
bc5fc7e4 1186{
f4800d6d
CH		 1187 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1188 struct nvme_queue *nvmeq = iod->nvmeq;
e44ac588 1189
27fa9bc5
CH		 1190 dev_warn(nvmeq->dev->ctrl.device,
1191 "Abort status: 0x%x", nvme_req(req)->status);
e7a2a87d 1192 atomic_inc(&nvmeq->dev->ctrl.abort_limit);
e7a2a87d 1193 blk_mq_free_request(req);
bc5fc7e4
MW		 1194}
1195
b2a0eb1a
KB		 1196static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1197{
1198
1199 /* If true, indicates loss of adapter communication, possibly by a
1200 * NVMe Subsystem reset.
1201 */
1202 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1203
ad70062c
JW		 1204 /* If there is a reset/reinit ongoing, we shouldn't reset again. */
1205 switch (dev->ctrl.state) {
1206 case NVME_CTRL_RESETTING:
ad6a0a52 1207 case NVME_CTRL_CONNECTING:
b2a0eb1a 1208 return false;
ad70062c
JW		 1209 default:
1210 break;
1211 }
b2a0eb1a
KB		 1212
1213 /* We shouldn't reset unless the controller is on fatal error state
1214 * _or_ if we lost the communication with it.
1215 */
1216 if (!(csts & NVME_CSTS_CFS) && !nssro)
1217 return false;
1218
b2a0eb1a
KB		 1219 return true;
1220}
1221
1222static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1223{
1224 /* Read a config register to help see what died. */
1225 u16 pci_status;
1226 int result;
1227
1228 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1229 &pci_status);
1230 if (result == PCIBIOS_SUCCESSFUL)
1231 dev_warn(dev->ctrl.device,
1232 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1233 csts, pci_status);
1234 else
1235 dev_warn(dev->ctrl.device,
1236 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1237 csts, result);
1238}
1239
31c7c7d2 1240static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
c30341dc 1241{
f4800d6d
CH		 1242 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1243 struct nvme_queue *nvmeq = iod->nvmeq;
c30341dc 1244 struct nvme_dev *dev = nvmeq->dev;
a4aea562 1245 struct request *abort_req;
a4aea562 1246 struct nvme_command cmd;
b2a0eb1a
KB		 1247 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1248
651438bb
WX		 1249 /* If PCI error recovery process is happening, we cannot reset or
1250 * the recovery mechanism will surely fail.
1251 */
1252 mb();
1253 if (pci_channel_offline(to_pci_dev(dev->dev)))
1254 return BLK_EH_RESET_TIMER;
1255
b2a0eb1a
KB		 1256 /*
1257 * Reset immediately if the controller is failed
1258 */
1259 if (nvme_should_reset(dev, csts)) {
1260 nvme_warn_reset(dev, csts);
1261 nvme_dev_disable(dev, false);
d86c4d8e 1262 nvme_reset_ctrl(&dev->ctrl);
db8c48e4 1263 return BLK_EH_DONE;
b2a0eb1a 1264 }
c30341dc 1265
7776db1c
KB		 1266 /*
1267 * Did we miss an interrupt?
1268 */
0b2a8a9f 1269 if (nvme_poll_irqdisable(nvmeq, req->tag)) {
7776db1c
KB		 1270 dev_warn(dev->ctrl.device,
1271 "I/O %d QID %d timeout, completion polled\n",
1272 req->tag, nvmeq->qid);
db8c48e4 1273 return BLK_EH_DONE;
7776db1c
KB		 1274 }
1275
31c7c7d2 1276 /*
fd634f41
CH		 1277 * Shutdown immediately if controller times out while starting. The
1278 * reset work will see the pci device disabled when it gets the forced
1279 * cancellation error. All outstanding requests are completed on
db8c48e4 1280 * shutdown, so we return BLK_EH_DONE.
fd634f41 1281 */
4244140d
KB		 1282 switch (dev->ctrl.state) {
1283 case NVME_CTRL_CONNECTING:
2036f726
KB		 1284 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
1285 /* fall through */
1286 case NVME_CTRL_DELETING:
b9cac43c 1287 dev_warn_ratelimited(dev->ctrl.device,
fd634f41
CH		 1288 "I/O %d QID %d timeout, disable controller\n",
1289 req->tag, nvmeq->qid);
2036f726 1290 nvme_dev_disable(dev, true);
27fa9bc5 1291 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
db8c48e4 1292 return BLK_EH_DONE;
39a9dd81
KB		 1293 case NVME_CTRL_RESETTING:
1294 return BLK_EH_RESET_TIMER;
4244140d
KB		 1295 default:
1296 break;
c30341dc
KB		 1297 }
1298
fd634f41
CH		 1299 /*
1300 * Shutdown the controller immediately and schedule a reset if the
1301 * command was already aborted once before and still hasn't been
1302 * returned to the driver, or if this is the admin queue.
31c7c7d2 1303 */
f4800d6d 1304 if (!nvmeq->qid || iod->aborted) {
1b3c47c1 1305 dev_warn(dev->ctrl.device,
e1569a16
KB		 1306 "I/O %d QID %d timeout, reset controller\n",
1307 req->tag, nvmeq->qid);
a5cdb68c 1308 nvme_dev_disable(dev, false);
d86c4d8e 1309 nvme_reset_ctrl(&dev->ctrl);
c30341dc 1310
27fa9bc5 1311 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
db8c48e4 1312 return BLK_EH_DONE;
c30341dc 1313 }
c30341dc 1314
e7a2a87d 1315 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
6bf25d16 1316 atomic_inc(&dev->ctrl.abort_limit);
31c7c7d2 1317 return BLK_EH_RESET_TIMER;
6bf25d16 1318 }
7bf7d778 1319 iod->aborted = 1;
a4aea562 1320
c30341dc
KB		 1321 memset(&cmd, 0, sizeof(cmd));
1322 cmd.abort.opcode = nvme_admin_abort_cmd;
a4aea562 1323 cmd.abort.cid = req->tag;
c30341dc 1324 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
c30341dc 1325
1b3c47c1
SG		 1326 dev_warn(nvmeq->dev->ctrl.device,
1327 "I/O %d QID %d timeout, aborting\n",
1328 req->tag, nvmeq->qid);
e7a2a87d
CH		 1329
1330 abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
eb71f435 1331 BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
e7a2a87d
CH		 1332 if (IS_ERR(abort_req)) {
1333 atomic_inc(&dev->ctrl.abort_limit);
1334 return BLK_EH_RESET_TIMER;
1335 }
1336
1337 abort_req->timeout = ADMIN_TIMEOUT;
1338 abort_req->end_io_data = NULL;
1339 blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio);
c30341dc 1340
31c7c7d2
CH		 1341 /*
1342 * The aborted req will be completed on receiving the abort req.
1343 * We enable the timer again. If hit twice, it'll cause a device reset,
1344 * as the device then is in a faulty state.
1345 */
1346 return BLK_EH_RESET_TIMER;
c30341dc
KB		 1347}
1348
a4aea562
MB		 1349static void nvme_free_queue(struct nvme_queue *nvmeq)
1350{
8a1d09a6 1351 dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq),
9e866774 1352 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
63223078
CH		 1353 if (!nvmeq->sq_cmds)
1354 return;
0f238ff5 1355
63223078 1356 if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) {
88a041f4 1357 pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev),
8a1d09a6 1358 nvmeq->sq_cmds, SQ_SIZE(nvmeq));
63223078 1359 } else {
8a1d09a6 1360 dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq),
63223078 1361 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
0f238ff5 1362 }
9e866774
MW		 1363}
1364
a1a5ef99 1365static void nvme_free_queues(struct nvme_dev *dev, int lowest)
22404274
KB		 1366{
1367 int i;
1368
d858e5f0 1369 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
d858e5f0 1370 dev->ctrl.queue_count--;
147b27e4 1371 nvme_free_queue(&dev->queues[i]);
121c7ad4 1372 }
22404274
KB		 1373}
1374
4d115420
KB		 1375/**
1376 * nvme_suspend_queue - put queue into suspended state
40581d1a 1377 * @nvmeq: queue to suspend
4d115420
KB		 1378 */
1379static int nvme_suspend_queue(struct nvme_queue *nvmeq)
b60503ba 1380{
4e224106 1381 if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags))
2b25d981 1382 return 1;
a09115b2 1383
4e224106 1384 /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */
d1f06f4a 1385 mb();
a09115b2 1386
4e224106 1387 nvmeq->dev->online_queues--;
1c63dc66 1388 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
c81545f9 1389 blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q);
7c349dde
KB		 1390 if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags))
1391 pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq);
4d115420
KB		 1392 return 0;
1393}
b60503ba 1394
8fae268b
KB		 1395static void nvme_suspend_io_queues(struct nvme_dev *dev)
1396{
1397 int i;
1398
1399 for (i = dev->ctrl.queue_count - 1; i > 0; i--)
1400 nvme_suspend_queue(&dev->queues[i]);
1401}
1402
a5cdb68c 1403static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
4d115420 1404{
147b27e4 1405 struct nvme_queue *nvmeq = &dev->queues[0];
4d115420 1406
a5cdb68c
KB		 1407 if (shutdown)
1408 nvme_shutdown_ctrl(&dev->ctrl);
1409 else
b5b05048 1410 nvme_disable_ctrl(&dev->ctrl);
07836e65 1411
0b2a8a9f 1412 nvme_poll_irqdisable(nvmeq, -1);
b60503ba
MW		 1413}
1414
8ffaadf7
JD		 1415static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1416 int entry_size)
1417{
1418 int q_depth = dev->q_depth;
5fd4ce1b
CH		 1419 unsigned q_size_aligned = roundup(q_depth * entry_size,
1420 dev->ctrl.page_size);
8ffaadf7
JD		 1421
1422 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
c45f5c99 1423 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
5fd4ce1b 1424 mem_per_q = round_down(mem_per_q, dev->ctrl.page_size);
c45f5c99 1425 q_depth = div_u64(mem_per_q, entry_size);
8ffaadf7
JD		 1426
1427 /*
1428 * Ensure the reduced q_depth is above some threshold where it
1429 * would be better to map queues in system memory with the
1430 * original depth
1431 */
1432 if (q_depth < 64)
1433 return -ENOMEM;
1434 }
1435
1436 return q_depth;
1437}
1438
1439static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
8a1d09a6 1440 int qid)
8ffaadf7 1441{
0f238ff5
LG		 1442 struct pci_dev *pdev = to_pci_dev(dev->dev);
1443
1444 if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
8a1d09a6 1445 nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq));
bfac8e9f
AM		 1446 if (nvmeq->sq_cmds) {
1447 nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev,
1448 nvmeq->sq_cmds);
1449 if (nvmeq->sq_dma_addr) {
1450 set_bit(NVMEQ_SQ_CMB, &nvmeq->flags);
1451 return 0;
1452 }
1453
8a1d09a6 1454 pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq));
63223078 1455 }
0f238ff5 1456 }
8ffaadf7 1457
8a1d09a6 1458 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq),
63223078 1459 &nvmeq->sq_dma_addr, GFP_KERNEL);
815c6704
KB		 1460 if (!nvmeq->sq_cmds)
1461 return -ENOMEM;
8ffaadf7
JD		 1462 return 0;
1463}
1464
a6ff7262 1465static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
b60503ba 1466{
147b27e4 1467 struct nvme_queue *nvmeq = &dev->queues[qid];
b60503ba 1468
62314e40
KB		 1469 if (dev->ctrl.queue_count > qid)
1470 return 0;
b60503ba 1471
c1e0cc7e 1472 nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES;
8a1d09a6
BH		 1473 nvmeq->q_depth = depth;
1474 nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq),
750afb08 1475 &nvmeq->cq_dma_addr, GFP_KERNEL);
b60503ba
MW		 1476 if (!nvmeq->cqes)
1477 goto free_nvmeq;
b60503ba 1478
8a1d09a6 1479 if (nvme_alloc_sq_cmds(dev, nvmeq, qid))
b60503ba
MW		 1480 goto free_cqdma;
1481
091b6092 1482 nvmeq->dev = dev;
1ab0cd69 1483 spin_lock_init(&nvmeq->sq_lock);
3a7afd8e 1484 spin_lock_init(&nvmeq->cq_poll_lock);
b60503ba 1485 nvmeq->cq_head = 0;
82123460 1486 nvmeq->cq_phase = 1;
b80d5ccc 1487 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
c30341dc 1488 nvmeq->qid = qid;
d858e5f0 1489 dev->ctrl.queue_count++;
36a7e993 1490
147b27e4 1491 return 0;
b60503ba
MW		 1492
1493 free_cqdma:
8a1d09a6
BH		 1494 dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes,
1495 nvmeq->cq_dma_addr);
b60503ba 1496 free_nvmeq:
147b27e4 1497 return -ENOMEM;
b60503ba
MW		 1498}
1499
dca51e78 1500static int queue_request_irq(struct nvme_queue *nvmeq)
3001082c 1501{
0ff199cb
CH		 1502 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1503 int nr = nvmeq->dev->ctrl.instance;
1504
1505 if (use_threaded_interrupts) {
1506 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1507 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1508 } else {
1509 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1510 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1511 }
3001082c
MW		 1512}
1513
22404274 1514static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
b60503ba 1515{
22404274 1516 struct nvme_dev *dev = nvmeq->dev;
b60503ba 1517
22404274 1518 nvmeq->sq_tail = 0;
04f3eafd 1519 nvmeq->last_sq_tail = 0;
22404274
KB		 1520 nvmeq->cq_head = 0;
1521 nvmeq->cq_phase = 1;
b80d5ccc 1522 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
8a1d09a6 1523 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq));
f9f38e33 1524 nvme_dbbuf_init(dev, nvmeq, qid);
42f61420 1525 dev->online_queues++;
3a7afd8e 1526 wmb(); /* ensure the first interrupt sees the initialization */
22404274
KB		 1527}
1528
4b04cc6a 1529static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled)
22404274
KB		 1530{
1531 struct nvme_dev *dev = nvmeq->dev;
1532 int result;
7c349dde 1533 u16 vector = 0;
3f85d50b 1534
d1ed6aa1
CH		 1535 clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
1536
22b55601
KB		 1537 /*
1538 * A queue's vector matches the queue identifier unless the controller
1539 * has only one vector available.
1540 */
4b04cc6a
JA		 1541 if (!polled)
1542 vector = dev->num_vecs == 1 ? 0 : qid;
1543 else
7c349dde 1544 set_bit(NVMEQ_POLLED, &nvmeq->flags);
4b04cc6a 1545
a8e3e0bb 1546 result = adapter_alloc_cq(dev, qid, nvmeq, vector);
ded45505
KB		 1547 if (result)
1548 return result;
b60503ba
MW		 1549
1550 result = adapter_alloc_sq(dev, qid, nvmeq);
1551 if (result < 0)
ded45505
KB		 1552 return result;
1553 else if (result)
b60503ba
MW		 1554 goto release_cq;
1555
a8e3e0bb 1556 nvmeq->cq_vector = vector;
161b8be2 1557 nvme_init_queue(nvmeq, qid);
4b04cc6a 1558
7c349dde 1559 if (!polled) {
4b04cc6a
JA		 1560 result = queue_request_irq(nvmeq);
1561 if (result < 0)
1562 goto release_sq;
1563 }
b60503ba 1564
4e224106 1565 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
22404274 1566 return result;
b60503ba 1567
a8e3e0bb 1568release_sq:
f25a2dfc 1569 dev->online_queues--;
b60503ba 1570 adapter_delete_sq(dev, qid);
a8e3e0bb 1571release_cq:
b60503ba 1572 adapter_delete_cq(dev, qid);
22404274 1573 return result;
b60503ba
MW		 1574}
1575
f363b089 1576static const struct blk_mq_ops nvme_mq_admin_ops = {
d29ec824 1577 .queue_rq = nvme_queue_rq,
77f02a7a 1578 .complete = nvme_pci_complete_rq,
a4aea562 1579 .init_hctx = nvme_admin_init_hctx,
4af0e21c 1580 .exit_hctx = nvme_admin_exit_hctx,
0350815a 1581 .init_request = nvme_init_request,
a4aea562
MB		 1582 .timeout = nvme_timeout,
1583};
1584
f363b089 1585static const struct blk_mq_ops nvme_mq_ops = {
376f7ef8
CH		 1586 .queue_rq = nvme_queue_rq,
1587 .complete = nvme_pci_complete_rq,
1588 .commit_rqs = nvme_commit_rqs,
1589 .init_hctx = nvme_init_hctx,
1590 .init_request = nvme_init_request,
1591 .map_queues = nvme_pci_map_queues,
1592 .timeout = nvme_timeout,
1593 .poll = nvme_poll,
dabcefab
JA		 1594};
1595
ea191d2f
KB		 1596static void nvme_dev_remove_admin(struct nvme_dev *dev)
1597{
1c63dc66 1598 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
69d9a99c
KB		 1599 /*
1600 * If the controller was reset during removal, it's possible
1601 * user requests may be waiting on a stopped queue. Start the
1602 * queue to flush these to completion.
1603 */
c81545f9 1604 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1c63dc66 1605 blk_cleanup_queue(dev->ctrl.admin_q);
ea191d2f
KB		 1606 blk_mq_free_tag_set(&dev->admin_tagset);
1607 }
1608}
1609
a4aea562
MB		 1610static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1611{
1c63dc66 1612 if (!dev->ctrl.admin_q) {
a4aea562
MB		 1613 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1614 dev->admin_tagset.nr_hw_queues = 1;
e3e9d50c 1615
38dabe21 1616 dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH;
a4aea562 1617 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
e75ec752 1618 dev->admin_tagset.numa_node = dev_to_node(dev->dev);
d43f1ccf 1619 dev->admin_tagset.cmd_size = sizeof(struct nvme_iod);
d3484991 1620 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED;
a4aea562
MB		 1621 dev->admin_tagset.driver_data = dev;
1622
1623 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1624 return -ENOMEM;
34b6c231 1625 dev->ctrl.admin_tagset = &dev->admin_tagset;
a4aea562 1626
1c63dc66
CH		 1627 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1628 if (IS_ERR(dev->ctrl.admin_q)) {
a4aea562
MB		 1629 blk_mq_free_tag_set(&dev->admin_tagset);
1630 return -ENOMEM;
1631 }
1c63dc66 1632 if (!blk_get_queue(dev->ctrl.admin_q)) {
ea191d2f 1633 nvme_dev_remove_admin(dev);
1c63dc66 1634 dev->ctrl.admin_q = NULL;
ea191d2f
KB		 1635 return -ENODEV;
1636 }
0fb59cbc 1637 } else
c81545f9 1638 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
a4aea562
MB		 1639
1640 return 0;
1641}
1642
97f6ef64
XY		 1643static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1644{
1645 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1646}
1647
1648static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1649{
1650 struct pci_dev *pdev = to_pci_dev(dev->dev);
1651
1652 if (size <= dev->bar_mapped_size)
1653 return 0;
1654 if (size > pci_resource_len(pdev, 0))
1655 return -ENOMEM;
1656 if (dev->bar)
1657 iounmap(dev->bar);
1658 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1659 if (!dev->bar) {
1660 dev->bar_mapped_size = 0;
1661 return -ENOMEM;
1662 }
1663 dev->bar_mapped_size = size;
1664 dev->dbs = dev->bar + NVME_REG_DBS;
1665
1666 return 0;
1667}
1668
01ad0990 1669static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
b60503ba 1670{
ba47e386 1671 int result;
b60503ba
MW		 1672 u32 aqa;
1673 struct nvme_queue *nvmeq;
1674
97f6ef64
XY		 1675 result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1676 if (result < 0)
1677 return result;
1678
8ef2074d 1679 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
20d0dfe6 1680 NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
dfbac8c7 1681
7a67cbea
CH		 1682 if (dev->subsystem &&
1683 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1684 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
dfbac8c7 1685
b5b05048 1686 result = nvme_disable_ctrl(&dev->ctrl);
ba47e386
MW		 1687 if (result < 0)
1688 return result;
b60503ba 1689
a6ff7262 1690 result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
147b27e4
SG		 1691 if (result)
1692 return result;
b60503ba 1693
147b27e4 1694 nvmeq = &dev->queues[0];
b60503ba
MW		 1695 aqa = nvmeq->q_depth - 1;
1696 aqa |= aqa << 16;
1697
7a67cbea
CH		 1698 writel(aqa, dev->bar + NVME_REG_AQA);
1699 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1700 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
b60503ba 1701
c0f2f45b 1702 result = nvme_enable_ctrl(&dev->ctrl);
025c557a 1703 if (result)
d4875622 1704 return result;
a4aea562 1705
2b25d981 1706 nvmeq->cq_vector = 0;
161b8be2 1707 nvme_init_queue(nvmeq, 0);
dca51e78 1708 result = queue_request_irq(nvmeq);
758dd7fd 1709 if (result) {
7c349dde 1710 dev->online_queues--;
d4875622 1711 return result;
758dd7fd 1712 }
025c557a 1713
4e224106 1714 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
b60503ba
MW		 1715 return result;
1716}
1717
749941f2 1718static int nvme_create_io_queues(struct nvme_dev *dev)
42f61420 1719{
4b04cc6a 1720 unsigned i, max, rw_queues;
749941f2 1721 int ret = 0;
42f61420 1722
d858e5f0 1723 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
a6ff7262 1724 if (nvme_alloc_queue(dev, i, dev->q_depth)) {
749941f2 1725 ret = -ENOMEM;
42f61420 1726 break;
749941f2
CH		 1727 }
1728 }
42f61420 1729
d858e5f0 1730 max = min(dev->max_qid, dev->ctrl.queue_count - 1);
e20ba6e1
CH		 1731 if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) {
1732 rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] +
1733 dev->io_queues[HCTX_TYPE_READ];
4b04cc6a
JA		 1734 } else {
1735 rw_queues = max;
1736 }
1737
949928c1 1738 for (i = dev->online_queues; i <= max; i++) {
4b04cc6a
JA		 1739 bool polled = i > rw_queues;
1740
1741 ret = nvme_create_queue(&dev->queues[i], i, polled);
d4875622 1742 if (ret)
42f61420 1743 break;
27e8166c 1744 }
749941f2
CH		 1745
1746 /*
1747 * Ignore failing Create SQ/CQ commands, we can continue with less
8adb8c14
MI		 1748 * than the desired amount of queues, and even a controller without
1749 * I/O queues can still be used to issue admin commands. This might
749941f2
CH		 1750 * be useful to upgrade a buggy firmware for example.
1751 */
1752 return ret >= 0 ? 0 : ret;
b60503ba
MW		 1753}
1754
202021c1
SB		 1755static ssize_t nvme_cmb_show(struct device *dev,
1756 struct device_attribute *attr,
1757 char *buf)
1758{
1759 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
1760
c965809c 1761 return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n",
202021c1
SB		 1762 ndev->cmbloc, ndev->cmbsz);
1763}
1764static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL);
1765
88de4598 1766static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
8ffaadf7 1767{
88de4598
CH		 1768 u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
1769
1770 return 1ULL << (12 + 4 * szu);
1771}
1772
1773static u32 nvme_cmb_size(struct nvme_dev *dev)
1774{
1775 return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
1776}
1777
f65efd6d 1778static void nvme_map_cmb(struct nvme_dev *dev)
8ffaadf7 1779{
88de4598 1780 u64 size, offset;
8ffaadf7
JD		 1781 resource_size_t bar_size;
1782 struct pci_dev *pdev = to_pci_dev(dev->dev);
8969f1f8 1783 int bar;
8ffaadf7 1784
9fe5c59f
KB		 1785 if (dev->cmb_size)
1786 return;
1787
7a67cbea 1788 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
f65efd6d
CH		 1789 if (!dev->cmbsz)
1790 return;
202021c1 1791 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
8ffaadf7 1792
88de4598
CH		 1793 size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
1794 offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
8969f1f8
CH		 1795 bar = NVME_CMB_BIR(dev->cmbloc);
1796 bar_size = pci_resource_len(pdev, bar);
8ffaadf7
JD		 1797
1798 if (offset > bar_size)
f65efd6d 1799 return;
8ffaadf7
JD		 1800
1801 /*
1802 * Controllers may support a CMB size larger than their BAR,
1803 * for example, due to being behind a bridge. Reduce the CMB to
1804 * the reported size of the BAR
1805 */
1806 if (size > bar_size - offset)
1807 size = bar_size - offset;
1808
0f238ff5
LG		 1809 if (pci_p2pdma_add_resource(pdev, bar, size, offset)) {
1810 dev_warn(dev->ctrl.device,
1811 "failed to register the CMB\n");
f65efd6d 1812 return;
0f238ff5
LG		 1813 }
1814
8ffaadf7 1815 dev->cmb_size = size;
0f238ff5
LG		 1816 dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS);
1817
1818 if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) ==
1819 (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS))
1820 pci_p2pmem_publish(pdev, true);
f65efd6d
CH		 1821
1822 if (sysfs_add_file_to_group(&dev->ctrl.device->kobj,
1823 &dev_attr_cmb.attr, NULL))
1824 dev_warn(dev->ctrl.device,
1825 "failed to add sysfs attribute for CMB\n");
8ffaadf7
JD		 1826}
1827
1828static inline void nvme_release_cmb(struct nvme_dev *dev)
1829{
0f238ff5 1830 if (dev->cmb_size) {
1c78f773
MG		 1831 sysfs_remove_file_from_group(&dev->ctrl.device->kobj,
1832 &dev_attr_cmb.attr, NULL);
0f238ff5 1833 dev->cmb_size = 0;
8ffaadf7
JD		 1834 }
1835}
1836
87ad72a5
CH		 1837static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1838{
4033f35d 1839 u64 dma_addr = dev->host_mem_descs_dma;
87ad72a5 1840 struct nvme_command c;
87ad72a5
CH		 1841 int ret;
1842
87ad72a5
CH		 1843 memset(&c, 0, sizeof(c));
1844 c.features.opcode = nvme_admin_set_features;
1845 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1846 c.features.dword11 = cpu_to_le32(bits);
1847 c.features.dword12 = cpu_to_le32(dev->host_mem_size >>
1848 ilog2(dev->ctrl.page_size));
1849 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr));
1850 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr));
1851 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs);
1852
1853 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1854 if (ret) {
1855 dev_warn(dev->ctrl.device,
1856 "failed to set host mem (err %d, flags %#x).\n",
1857 ret, bits);
1858 }
87ad72a5
CH		 1859 return ret;
1860}
1861
1862static void nvme_free_host_mem(struct nvme_dev *dev)
1863{
1864 int i;
1865
1866 for (i = 0; i < dev->nr_host_mem_descs; i++) {
1867 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
1868 size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size;
1869
cc667f6d
LD		 1870 dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i],
1871 le64_to_cpu(desc->addr),
1872 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
87ad72a5
CH		 1873 }
1874
1875 kfree(dev->host_mem_desc_bufs);
1876 dev->host_mem_desc_bufs = NULL;
4033f35d
CH		 1877 dma_free_coherent(dev->dev,
1878 dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
1879 dev->host_mem_descs, dev->host_mem_descs_dma);
87ad72a5 1880 dev->host_mem_descs = NULL;
7e5dd57e 1881 dev->nr_host_mem_descs = 0;
87ad72a5
CH		 1882}
1883
92dc6895
CH		 1884static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
1885 u32 chunk_size)
9d713c2b 1886{
87ad72a5 1887 struct nvme_host_mem_buf_desc *descs;
92dc6895 1888 u32 max_entries, len;
4033f35d 1889 dma_addr_t descs_dma;
2ee0e4ed 1890 int i = 0;
87ad72a5 1891 void **bufs;
6fbcde66 1892 u64 size, tmp;
87ad72a5 1893
87ad72a5
CH		 1894 tmp = (preferred + chunk_size - 1);
1895 do_div(tmp, chunk_size);
1896 max_entries = tmp;
044a9df1
CH		 1897
1898 if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
1899 max_entries = dev->ctrl.hmmaxd;
1900
750afb08
LC		 1901 descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs),
1902 &descs_dma, GFP_KERNEL);
87ad72a5
CH		 1903 if (!descs)
1904 goto out;
1905
1906 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
1907 if (!bufs)
1908 goto out_free_descs;
1909
244a8fe4 1910 for (size = 0; size < preferred && i < max_entries; size += len) {
87ad72a5
CH		 1911 dma_addr_t dma_addr;
1912
50cdb7c6 1913 len = min_t(u64, chunk_size, preferred - size);
87ad72a5
CH		 1914 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
1915 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1916 if (!bufs[i])
1917 break;
1918
1919 descs[i].addr = cpu_to_le64(dma_addr);
1920 descs[i].size = cpu_to_le32(len / dev->ctrl.page_size);
1921 i++;
1922 }
1923
92dc6895 1924 if (!size)
87ad72a5 1925 goto out_free_bufs;
87ad72a5 1926
87ad72a5
CH		 1927 dev->nr_host_mem_descs = i;
1928 dev->host_mem_size = size;
1929 dev->host_mem_descs = descs;
4033f35d 1930 dev->host_mem_descs_dma = descs_dma;
87ad72a5
CH		 1931 dev->host_mem_desc_bufs = bufs;
1932 return 0;
1933
1934out_free_bufs:
1935 while (--i >= 0) {
1936 size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size;
1937
cc667f6d
LD		 1938 dma_free_attrs(dev->dev, size, bufs[i],
1939 le64_to_cpu(descs[i].addr),
1940 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
87ad72a5
CH		 1941 }
1942
1943 kfree(bufs);
1944out_free_descs:
4033f35d
CH		 1945 dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
1946 descs_dma);
87ad72a5 1947out:
87ad72a5
CH		 1948 dev->host_mem_descs = NULL;
1949 return -ENOMEM;
1950}
1951
92dc6895
CH		 1952static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
1953{
1954 u32 chunk_size;
1955
1956 /* start big and work our way down */
30f92d62 1957 for (chunk_size = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
044a9df1 1958 chunk_size >= max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
92dc6895
CH		 1959 chunk_size /= 2) {
1960 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
1961 if (!min || dev->host_mem_size >= min)
1962 return 0;
1963 nvme_free_host_mem(dev);
1964 }
1965 }
1966
1967 return -ENOMEM;
1968}
1969
9620cfba 1970static int nvme_setup_host_mem(struct nvme_dev *dev)
87ad72a5
CH		 1971{
1972 u64 max = (u64)max_host_mem_size_mb * SZ_1M;
1973 u64 preferred = (u64)dev->ctrl.hmpre * 4096;
1974 u64 min = (u64)dev->ctrl.hmmin * 4096;
1975 u32 enable_bits = NVME_HOST_MEM_ENABLE;
6fbcde66 1976 int ret;
87ad72a5
CH		 1977
1978 preferred = min(preferred, max);
1979 if (min > max) {
1980 dev_warn(dev->ctrl.device,
1981 "min host memory (%lld MiB) above limit (%d MiB).\n",
1982 min >> ilog2(SZ_1M), max_host_mem_size_mb);
1983 nvme_free_host_mem(dev);
9620cfba 1984 return 0;
87ad72a5
CH		 1985 }
1986
1987 /*
1988 * If we already have a buffer allocated check if we can reuse it.
1989 */
1990 if (dev->host_mem_descs) {
1991 if (dev->host_mem_size >= min)
1992 enable_bits |= NVME_HOST_MEM_RETURN;
1993 else
1994 nvme_free_host_mem(dev);
1995 }
1996
1997 if (!dev->host_mem_descs) {
92dc6895
CH		 1998 if (nvme_alloc_host_mem(dev, min, preferred)) {
1999 dev_warn(dev->ctrl.device,
2000 "failed to allocate host memory buffer.\n");
9620cfba 2001 return 0; /* controller must work without HMB */
92dc6895
CH		 2002 }
2003
2004 dev_info(dev->ctrl.device,
2005 "allocated %lld MiB host memory buffer.\n",
2006 dev->host_mem_size >> ilog2(SZ_1M));
87ad72a5
CH		 2007 }
2008
9620cfba
CH		 2009 ret = nvme_set_host_mem(dev, enable_bits);
2010 if (ret)
87ad72a5 2011 nvme_free_host_mem(dev);
9620cfba 2012 return ret;
9d713c2b
KB		 2013}
2014
612b7286
ML		 2015/*
2016 * nirqs is the number of interrupts available for write and read
2017 * queues. The core already reserved an interrupt for the admin queue.
2018 */
2019static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs)
3b6592f7 2020{
612b7286
ML		 2021 struct nvme_dev *dev = affd->priv;
2022 unsigned int nr_read_queues;
3b6592f7
JA		 2023
2024 /*
612b7286
ML		 2025 * If there is no interupt available for queues, ensure that
2026 * the default queue is set to 1. The affinity set size is
2027 * also set to one, but the irq core ignores it for this case.
2028 *
2029 * If only one interrupt is available or 'write_queue' == 0, combine
2030 * write and read queues.
2031 *
2032 * If 'write_queues' > 0, ensure it leaves room for at least one read
2033 * queue.
3b6592f7 2034 */
612b7286
ML		 2035 if (!nrirqs) {
2036 nrirqs = 1;
2037 nr_read_queues = 0;
2038 } else if (nrirqs == 1 || !write_queues) {
2039 nr_read_queues = 0;
2040 } else if (write_queues >= nrirqs) {
2041 nr_read_queues = 1;
3b6592f7 2042 } else {
612b7286 2043 nr_read_queues = nrirqs - write_queues;
3b6592f7 2044 }
612b7286
ML		 2045
2046 dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2047 affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2048 dev->io_queues[HCTX_TYPE_READ] = nr_read_queues;
2049 affd->set_size[HCTX_TYPE_READ] = nr_read_queues;
2050 affd->nr_sets = nr_read_queues ? 2 : 1;
3b6592f7
JA		 2051}
2052
6451fe73 2053static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues)
3b6592f7
JA		 2054{
2055 struct pci_dev *pdev = to_pci_dev(dev->dev);
3b6592f7 2056 struct irq_affinity affd = {
9cfef55b 2057 .pre_vectors = 1,
612b7286
ML		 2058 .calc_sets = nvme_calc_irq_sets,
2059 .priv = dev,
3b6592f7 2060 };
6451fe73 2061 unsigned int irq_queues, this_p_queues;
dad77d63 2062 unsigned int nr_cpus = num_possible_cpus();
6451fe73
JA		 2063
2064 /*
2065 * Poll queues don't need interrupts, but we need at least one IO
2066 * queue left over for non-polled IO.
2067 */
2068 this_p_queues = poll_queues;
2069 if (this_p_queues >= nr_io_queues) {
2070 this_p_queues = nr_io_queues - 1;
2071 irq_queues = 1;
2072 } else {
dad77d63
MI		 2073 if (nr_cpus < nr_io_queues - this_p_queues)
2074 irq_queues = nr_cpus + 1;
2075 else
2076 irq_queues = nr_io_queues - this_p_queues + 1;
6451fe73
JA		 2077 }
2078 dev->io_queues[HCTX_TYPE_POLL] = this_p_queues;
3b6592f7 2079
612b7286
ML		 2080 /* Initialize for the single interrupt case */
2081 dev->io_queues[HCTX_TYPE_DEFAULT] = 1;
2082 dev->io_queues[HCTX_TYPE_READ] = 0;
3b6592f7 2083
66341331
BH		 2084 /*
2085 * Some Apple controllers require all queues to use the
2086 * first vector.
2087 */
2088 if (dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR)
2089 irq_queues = 1;
2090
612b7286
ML		 2091 return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues,
2092 PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd);
3b6592f7
JA		 2093}
2094
8fae268b
KB		 2095static void nvme_disable_io_queues(struct nvme_dev *dev)
2096{
2097 if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq))
2098 __nvme_disable_io_queues(dev, nvme_admin_delete_cq);
2099}
2100
8d85fce7 2101static int nvme_setup_io_queues(struct nvme_dev *dev)
b60503ba 2102{
147b27e4 2103 struct nvme_queue *adminq = &dev->queues[0];
e75ec752 2104 struct pci_dev *pdev = to_pci_dev(dev->dev);
97f6ef64
XY		 2105 int result, nr_io_queues;
2106 unsigned long size;
b60503ba 2107
3b6592f7 2108 nr_io_queues = max_io_queues();
d38e9f04
BH		 2109
2110 /*
2111 * If tags are shared with admin queue (Apple bug), then
2112 * make sure we only use one IO queue.
2113 */
2114 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2115 nr_io_queues = 1;
2116
9a0be7ab
CH		 2117 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
2118 if (result < 0)
1b23484b 2119 return result;
9a0be7ab 2120
f5fa90dc 2121 if (nr_io_queues == 0)
a5229050 2122 return 0;
4e224106
CH		 2123
2124 clear_bit(NVMEQ_ENABLED, &adminq->flags);
b60503ba 2125
0f238ff5 2126 if (dev->cmb_use_sqes) {
8ffaadf7
JD		 2127 result = nvme_cmb_qdepth(dev, nr_io_queues,
2128 sizeof(struct nvme_command));
2129 if (result > 0)
2130 dev->q_depth = result;
2131 else
0f238ff5 2132 dev->cmb_use_sqes = false;
8ffaadf7
JD		 2133 }
2134
97f6ef64
XY		 2135 do {
2136 size = db_bar_size(dev, nr_io_queues);
2137 result = nvme_remap_bar(dev, size);
2138 if (!result)
2139 break;
2140 if (!--nr_io_queues)
2141 return -ENOMEM;
2142 } while (1);
2143 adminq->q_db = dev->dbs;
f1938f6e 2144
8fae268b 2145 retry:
9d713c2b 2146 /* Deregister the admin queue's interrupt */
0ff199cb 2147 pci_free_irq(pdev, 0, adminq);
9d713c2b 2148
e32efbfc
JA		 2149 /*
2150 * If we enable msix early due to not intx, disable it again before
2151 * setting up the full range we need.
2152 */
dca51e78 2153 pci_free_irq_vectors(pdev);
3b6592f7
JA		 2154
2155 result = nvme_setup_irqs(dev, nr_io_queues);
22b55601 2156 if (result <= 0)
dca51e78 2157 return -EIO;
3b6592f7 2158
22b55601 2159 dev->num_vecs = result;
4b04cc6a 2160 result = max(result - 1, 1);
e20ba6e1 2161 dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL];
fa08a396 2162
063a8096
MW		 2163 /*
2164 * Should investigate if there's a performance win from allocating
2165 * more queues than interrupt vectors; it might allow the submission
2166 * path to scale better, even if the receive path is limited by the
2167 * number of interrupts.
2168 */
dca51e78 2169 result = queue_request_irq(adminq);
7c349dde 2170 if (result)
d4875622 2171 return result;
4e224106 2172 set_bit(NVMEQ_ENABLED, &adminq->flags);
8fae268b
KB		 2173
2174 result = nvme_create_io_queues(dev);
2175 if (result || dev->online_queues < 2)
2176 return result;
2177
2178 if (dev->online_queues - 1 < dev->max_qid) {
2179 nr_io_queues = dev->online_queues - 1;
2180 nvme_disable_io_queues(dev);
2181 nvme_suspend_io_queues(dev);
2182 goto retry;
2183 }
2184 dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n",
2185 dev->io_queues[HCTX_TYPE_DEFAULT],
2186 dev->io_queues[HCTX_TYPE_READ],
2187 dev->io_queues[HCTX_TYPE_POLL]);
2188 return 0;
b60503ba
MW		 2189}
2190
2a842aca 2191static void nvme_del_queue_end(struct request *req, blk_status_t error)
a5768aa8 2192{
db3cbfff 2193 struct nvme_queue *nvmeq = req->end_io_data;
b5875222 2194
db3cbfff 2195 blk_mq_free_request(req);
d1ed6aa1 2196 complete(&nvmeq->delete_done);
a5768aa8
KB		 2197}
2198
2a842aca 2199static void nvme_del_cq_end(struct request *req, blk_status_t error)
a5768aa8 2200{
db3cbfff 2201 struct nvme_queue *nvmeq = req->end_io_data;
a5768aa8 2202
d1ed6aa1
CH		 2203 if (error)
2204 set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
db3cbfff
KB		 2205
2206 nvme_del_queue_end(req, error);
a5768aa8
KB		 2207}
2208
db3cbfff 2209static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
bda4e0fb 2210{
db3cbfff
KB		 2211 struct request_queue *q = nvmeq->dev->ctrl.admin_q;
2212 struct request *req;
2213 struct nvme_command cmd;
bda4e0fb 2214
db3cbfff
KB		 2215 memset(&cmd, 0, sizeof(cmd));
2216 cmd.delete_queue.opcode = opcode;
2217 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
bda4e0fb 2218
eb71f435 2219 req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
db3cbfff
KB		 2220 if (IS_ERR(req))
2221 return PTR_ERR(req);
bda4e0fb 2222
db3cbfff
KB		 2223 req->timeout = ADMIN_TIMEOUT;
2224 req->end_io_data = nvmeq;
2225
d1ed6aa1 2226 init_completion(&nvmeq->delete_done);
db3cbfff
KB		 2227 blk_execute_rq_nowait(q, NULL, req, false,
2228 opcode == nvme_admin_delete_cq ?
2229 nvme_del_cq_end : nvme_del_queue_end);
2230 return 0;
bda4e0fb
KB		 2231}
2232
8fae268b 2233static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode)
a5768aa8 2234{
5271edd4 2235 int nr_queues = dev->online_queues - 1, sent = 0;
db3cbfff 2236 unsigned long timeout;
a5768aa8 2237
db3cbfff 2238 retry:
5271edd4
CH		 2239 timeout = ADMIN_TIMEOUT;
2240 while (nr_queues > 0) {
2241 if (nvme_delete_queue(&dev->queues[nr_queues], opcode))
2242 break;
2243 nr_queues--;
2244 sent++;
db3cbfff 2245 }
d1ed6aa1
CH		 2246 while (sent) {
2247 struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent];
2248
2249 timeout = wait_for_completion_io_timeout(&nvmeq->delete_done,
5271edd4
CH		 2250 timeout);
2251 if (timeout == 0)
2252 return false;
d1ed6aa1
CH		 2253
2254 /* handle any remaining CQEs */
2255 if (opcode == nvme_admin_delete_cq &&
2256 !test_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags))
2257 nvme_poll_irqdisable(nvmeq, -1);
2258
2259 sent--;
5271edd4
CH		 2260 if (nr_queues)
2261 goto retry;
2262 }
2263 return true;
a5768aa8
KB		 2264}
2265
422ef0c7 2266/*
2b1b7e78 2267 * return error value only when tagset allocation failed
422ef0c7 2268 */
8d85fce7 2269static int nvme_dev_add(struct nvme_dev *dev)
b60503ba 2270{
2b1b7e78
JW		 2271 int ret;
2272
5bae7f73 2273 if (!dev->ctrl.tagset) {
376f7ef8 2274 dev->tagset.ops = &nvme_mq_ops;
ffe7704d 2275 dev->tagset.nr_hw_queues = dev->online_queues - 1;
8fe34be1 2276 dev->tagset.nr_maps = 2; /* default + read */
ed92ad37
CH		 2277 if (dev->io_queues[HCTX_TYPE_POLL])
2278 dev->tagset.nr_maps++;
ffe7704d
KB		 2279 dev->tagset.timeout = NVME_IO_TIMEOUT;
2280 dev->tagset.numa_node = dev_to_node(dev->dev);
2281 dev->tagset.queue_depth =
a4aea562 2282 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
d43f1ccf 2283 dev->tagset.cmd_size = sizeof(struct nvme_iod);
ffe7704d
KB		 2284 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2285 dev->tagset.driver_data = dev;
b60503ba 2286
d38e9f04
BH		 2287 /*
2288 * Some Apple controllers requires tags to be unique
2289 * across admin and IO queue, so reserve the first 32
2290 * tags of the IO queue.
2291 */
2292 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2293 dev->tagset.reserved_tags = NVME_AQ_DEPTH;
2294
2b1b7e78
JW		 2295 ret = blk_mq_alloc_tag_set(&dev->tagset);
2296 if (ret) {
2297 dev_warn(dev->ctrl.device,
2298 "IO queues tagset allocation failed %d\n", ret);
2299 return ret;
2300 }
5bae7f73 2301 dev->ctrl.tagset = &dev->tagset;
949928c1
KB		 2302 } else {
2303 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2304
2305 /* Free previously allocated queues that are no longer usable */
2306 nvme_free_queues(dev, dev->online_queues);
ffe7704d 2307 }
949928c1 2308
e8fd41bb 2309 nvme_dbbuf_set(dev);
e1e5e564 2310 return 0;
b60503ba
MW		 2311}
2312
b00a726a 2313static int nvme_pci_enable(struct nvme_dev *dev)
0877cb0d 2314{
b00a726a 2315 int result = -ENOMEM;
e75ec752 2316 struct pci_dev *pdev = to_pci_dev(dev->dev);
0877cb0d
KB		 2317
2318 if (pci_enable_device_mem(pdev))
2319 return result;
2320
0877cb0d 2321 pci_set_master(pdev);
0877cb0d 2322
4fe06923 2323 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)))
052d0efa 2324 goto disable;
0877cb0d 2325
7a67cbea 2326 if (readl(dev->bar + NVME_REG_CSTS) == -1) {
0e53d180 2327 result = -ENODEV;
b00a726a 2328 goto disable;
0e53d180 2329 }
e32efbfc
JA		 2330
2331 /*
a5229050
KB		 2332 * Some devices and/or platforms don't advertise or work with INTx
2333 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2334 * adjust this later.
e32efbfc 2335 */
dca51e78
CH		 2336 result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
2337 if (result < 0)
2338 return result;
e32efbfc 2339
20d0dfe6 2340 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
7a67cbea 2341
20d0dfe6 2342 dev->q_depth = min_t(int, NVME_CAP_MQES(dev->ctrl.cap) + 1,
b27c1e68 2343 io_queue_depth);
aa22c8e6 2344 dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */
20d0dfe6 2345 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
7a67cbea 2346 dev->dbs = dev->bar + 4096;
1f390c1f 2347
66341331
BH		 2348 /*
2349 * Some Apple controllers require a non-standard SQE size.
2350 * Interestingly they also seem to ignore the CC:IOSQES register
2351 * so we don't bother updating it here.
2352 */
2353 if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES)
2354 dev->io_sqes = 7;
2355 else
2356 dev->io_sqes = NVME_NVM_IOSQES;
1f390c1f
SG		 2357
2358 /*
2359 * Temporary fix for the Apple controller found in the MacBook8,1 and
2360 * some MacBook7,1 to avoid controller resets and data loss.
2361 */
2362 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
2363 dev->q_depth = 2;
9bdcfb10
CH		 2364 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
2365 "set queue depth=%u to work around controller resets\n",
1f390c1f 2366 dev->q_depth);
d554b5e1
MP		 2367 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2368 (pdev->device == 0xa821 || pdev->device == 0xa822) &&
20d0dfe6 2369 NVME_CAP_MQES(dev->ctrl.cap) == 0) {
d554b5e1
MP		 2370 dev->q_depth = 64;
2371 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2372 "set queue depth=%u\n", dev->q_depth);
1f390c1f
SG		 2373 }
2374
d38e9f04
BH		 2375 /*
2376 * Controllers with the shared tags quirk need the IO queue to be
2377 * big enough so that we get 32 tags for the admin queue
2378 */
2379 if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) &&
2380 (dev->q_depth < (NVME_AQ_DEPTH + 2))) {
2381 dev->q_depth = NVME_AQ_DEPTH + 2;
2382 dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n",
2383 dev->q_depth);
2384 }
2385
2386
f65efd6d 2387 nvme_map_cmb(dev);
202021c1 2388
a0a3408e
KB		 2389 pci_enable_pcie_error_reporting(pdev);
2390 pci_save_state(pdev);
0877cb0d
KB		 2391 return 0;
2392
2393 disable:
0877cb0d
KB		 2394 pci_disable_device(pdev);
2395 return result;
2396}
2397
2398static void nvme_dev_unmap(struct nvme_dev *dev)
b00a726a
KB		 2399{
2400 if (dev->bar)
2401 iounmap(dev->bar);
a1f447b3 2402 pci_release_mem_regions(to_pci_dev(dev->dev));
b00a726a
KB		 2403}
2404
2405static void nvme_pci_disable(struct nvme_dev *dev)
0877cb0d 2406{
e75ec752
CH		 2407 struct pci_dev *pdev = to_pci_dev(dev->dev);
2408
dca51e78 2409 pci_free_irq_vectors(pdev);
0877cb0d 2410
a0a3408e
KB		 2411 if (pci_is_enabled(pdev)) {
2412 pci_disable_pcie_error_reporting(pdev);
e75ec752 2413 pci_disable_device(pdev);
4d115420 2414 }
4d115420
KB		 2415}
2416
a5cdb68c 2417static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
b60503ba 2418{
e43269e6 2419 bool dead = true, freeze = false;
302ad8cc 2420 struct pci_dev *pdev = to_pci_dev(dev->dev);
22404274 2421
77bf25ea 2422 mutex_lock(&dev->shutdown_lock);
302ad8cc
KB		 2423 if (pci_is_enabled(pdev)) {
2424 u32 csts = readl(dev->bar + NVME_REG_CSTS);
2425
ebef7368 2426 if (dev->ctrl.state == NVME_CTRL_LIVE ||
e43269e6
KB		 2427 dev->ctrl.state == NVME_CTRL_RESETTING) {
2428 freeze = true;
302ad8cc 2429 nvme_start_freeze(&dev->ctrl);
e43269e6 2430 }
302ad8cc
KB		 2431 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
2432 pdev->error_state != pci_channel_io_normal);
c9d3bf88 2433 }
c21377f8 2434
302ad8cc
KB		 2435 /*
2436 * Give the controller a chance to complete all entered requests if
2437 * doing a safe shutdown.
2438 */
e43269e6
KB		 2439 if (!dead && shutdown && freeze)
2440 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
9a915a5b
JW		 2441
2442 nvme_stop_queues(&dev->ctrl);
87ad72a5 2443
64ee0ac0 2444 if (!dead && dev->ctrl.queue_count > 0) {
8fae268b 2445 nvme_disable_io_queues(dev);
a5cdb68c 2446 nvme_disable_admin_queue(dev, shutdown);
4d115420 2447 }
8fae268b
KB		 2448 nvme_suspend_io_queues(dev);
2449 nvme_suspend_queue(&dev->queues[0]);
b00a726a 2450 nvme_pci_disable(dev);
07836e65 2451
e1958e65
ML		 2452 blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
2453 blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
622b8b68
ML		 2454 blk_mq_tagset_wait_completed_request(&dev->tagset);
2455 blk_mq_tagset_wait_completed_request(&dev->admin_tagset);
302ad8cc
KB		 2456
2457 /*
2458 * The driver will not be starting up queues again if shutting down so
2459 * must flush all entered requests to their failed completion to avoid
2460 * deadlocking blk-mq hot-cpu notifier.
2461 */
c8e9e9b7 2462 if (shutdown) {
302ad8cc 2463 nvme_start_queues(&dev->ctrl);
c8e9e9b7
KB		 2464 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q))
2465 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
2466 }
77bf25ea 2467 mutex_unlock(&dev->shutdown_lock);
b60503ba
MW		 2468}
2469
091b6092
MW		 2470static int nvme_setup_prp_pools(struct nvme_dev *dev)
2471{
e75ec752 2472 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
091b6092
MW		 2473 PAGE_SIZE, PAGE_SIZE, 0);
2474 if (!dev->prp_page_pool)
2475 return -ENOMEM;
2476
99802a7a 2477 /* Optimisation for I/Os between 4k and 128k */
e75ec752 2478 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
99802a7a
MW		 2479 256, 256, 0);
2480 if (!dev->prp_small_pool) {
2481 dma_pool_destroy(dev->prp_page_pool);
2482 return -ENOMEM;
2483 }
091b6092
MW		 2484 return 0;
2485}
2486
2487static void nvme_release_prp_pools(struct nvme_dev *dev)
2488{
2489 dma_pool_destroy(dev->prp_page_pool);
99802a7a 2490 dma_pool_destroy(dev->prp_small_pool);
091b6092
MW		 2491}
2492
770597ec
KB		 2493static void nvme_free_tagset(struct nvme_dev *dev)
2494{
2495 if (dev->tagset.tags)
2496 blk_mq_free_tag_set(&dev->tagset);
2497 dev->ctrl.tagset = NULL;
2498}
2499
1673f1f0 2500static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
5e82e952 2501{
1673f1f0 2502 struct nvme_dev *dev = to_nvme_dev(ctrl);
9ac27090 2503
f9f38e33 2504 nvme_dbbuf_dma_free(dev);
e75ec752 2505 put_device(dev->dev);
770597ec 2506 nvme_free_tagset(dev);
1c63dc66
CH		 2507 if (dev->ctrl.admin_q)
2508 blk_put_queue(dev->ctrl.admin_q);
5e82e952 2509 kfree(dev->queues);
e286bcfc 2510 free_opal_dev(dev->ctrl.opal_dev);
943e942e 2511 mempool_destroy(dev->iod_mempool);
5e82e952
KB		 2512 kfree(dev);
2513}
2514
7c1ce408 2515static void nvme_remove_dead_ctrl(struct nvme_dev *dev)
f58944e2 2516{
d22524a4 2517 nvme_get_ctrl(&dev->ctrl);
69d9a99c 2518 nvme_dev_disable(dev, false);
9f9cafc1 2519 nvme_kill_queues(&dev->ctrl);
03e0f3a6 2520 if (!queue_work(nvme_wq, &dev->remove_work))
f58944e2
KB		 2521 nvme_put_ctrl(&dev->ctrl);
2522}
2523
fd634f41 2524static void nvme_reset_work(struct work_struct *work)
5e82e952 2525{
d86c4d8e
CH		 2526 struct nvme_dev *dev =
2527 container_of(work, struct nvme_dev, ctrl.reset_work);
a98e58e5 2528 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
e71afda4 2529 int result;
2b1b7e78 2530 enum nvme_ctrl_state new_state = NVME_CTRL_LIVE;
5e82e952 2531
e71afda4
CK		 2532 if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING)) {
2533 result = -ENODEV;
fd634f41 2534 goto out;
e71afda4 2535 }
5e82e952 2536
fd634f41
CH		 2537 /*
2538 * If we're called to reset a live controller first shut it down before
2539 * moving on.
2540 */
b00a726a 2541 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
a5cdb68c 2542 nvme_dev_disable(dev, false);
d6135c3a 2543 nvme_sync_queues(&dev->ctrl);
5e82e952 2544
5c959d73 2545 mutex_lock(&dev->shutdown_lock);
b00a726a 2546 result = nvme_pci_enable(dev);
f0b50732 2547 if (result)
4726bcf3 2548 goto out_unlock;
f0b50732 2549
01ad0990 2550 result = nvme_pci_configure_admin_queue(dev);
f0b50732 2551 if (result)
4726bcf3 2552 goto out_unlock;
f0b50732 2553
0fb59cbc
KB		 2554 result = nvme_alloc_admin_tags(dev);
2555 if (result)
4726bcf3 2556 goto out_unlock;
b9afca3e 2557
943e942e
JA		 2558 /*
2559 * Limit the max command size to prevent iod->sg allocations going
2560 * over a single page.
2561 */
7637de31
CH		 2562 dev->ctrl.max_hw_sectors = min_t(u32,
2563 NVME_MAX_KB_SZ << 1, dma_max_mapping_size(dev->dev) >> 9);
943e942e 2564 dev->ctrl.max_segments = NVME_MAX_SEGS;
a48bc520
CH		 2565
2566 /*
2567 * Don't limit the IOMMU merged segment size.
2568 */
2569 dma_set_max_seg_size(dev->dev, 0xffffffff);
2570
5c959d73
KB		 2571 mutex_unlock(&dev->shutdown_lock);
2572
2573 /*
2574 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
2575 * initializing procedure here.
2576 */
2577 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
2578 dev_warn(dev->ctrl.device,
2579 "failed to mark controller CONNECTING\n");
cee6c269 2580 result = -EBUSY;
5c959d73
KB		 2581 goto out;
2582 }
943e942e 2583
ce4541f4
CH		 2584 result = nvme_init_identify(&dev->ctrl);
2585 if (result)
f58944e2 2586 goto out;
ce4541f4 2587
e286bcfc
SB		 2588 if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
2589 if (!dev->ctrl.opal_dev)
2590 dev->ctrl.opal_dev =
2591 init_opal_dev(&dev->ctrl, &nvme_sec_submit);
2592 else if (was_suspend)
2593 opal_unlock_from_suspend(dev->ctrl.opal_dev);
2594 } else {
2595 free_opal_dev(dev->ctrl.opal_dev);
2596 dev->ctrl.opal_dev = NULL;
4f1244c8 2597 }
a98e58e5 2598
f9f38e33
HK		 2599 if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) {
2600 result = nvme_dbbuf_dma_alloc(dev);
2601 if (result)
2602 dev_warn(dev->dev,
2603 "unable to allocate dma for dbbuf\n");
2604 }
2605
9620cfba
CH		 2606 if (dev->ctrl.hmpre) {
2607 result = nvme_setup_host_mem(dev);
2608 if (result < 0)
2609 goto out;
2610 }
87ad72a5 2611
f0b50732 2612 result = nvme_setup_io_queues(dev);
badc34d4 2613 if (result)
f58944e2 2614 goto out;
f0b50732 2615
2659e57b
CH		 2616 /*
2617 * Keep the controller around but remove all namespaces if we don't have
2618 * any working I/O queue.
2619 */
3cf519b5 2620 if (dev->online_queues < 2) {
1b3c47c1 2621 dev_warn(dev->ctrl.device, "IO queues not created\n");
3b24774e 2622 nvme_kill_queues(&dev->ctrl);
5bae7f73 2623 nvme_remove_namespaces(&dev->ctrl);
2b1b7e78 2624 new_state = NVME_CTRL_ADMIN_ONLY;
770597ec 2625 nvme_free_tagset(dev);
3cf519b5 2626 } else {
25646264 2627 nvme_start_queues(&dev->ctrl);
302ad8cc 2628 nvme_wait_freeze(&dev->ctrl);
2b1b7e78
JW		 2629 /* hit this only when allocate tagset fails */
2630 if (nvme_dev_add(dev))
2631 new_state = NVME_CTRL_ADMIN_ONLY;
302ad8cc 2632 nvme_unfreeze(&dev->ctrl);
3cf519b5
CH		 2633 }
2634
2b1b7e78
JW		 2635 /*
2636 * If only admin queue live, keep it to do further investigation or
2637 * recovery.
2638 */
2639 if (!nvme_change_ctrl_state(&dev->ctrl, new_state)) {
2640 dev_warn(dev->ctrl.device,
2641 "failed to mark controller state %d\n", new_state);
e71afda4 2642 result = -ENODEV;
bb8d261e
CH		 2643 goto out;
2644 }
92911a55 2645
d09f2b45 2646 nvme_start_ctrl(&dev->ctrl);
3cf519b5 2647 return;
f0b50732 2648
4726bcf3
KB		 2649 out_unlock:
2650 mutex_unlock(&dev->shutdown_lock);
3cf519b5 2651 out:
7c1ce408
CK		 2652 if (result)
2653 dev_warn(dev->ctrl.device,
2654 "Removing after probe failure status: %d\n", result);
2655 nvme_remove_dead_ctrl(dev);
f0b50732
KB		 2656}
2657
5c8809e6 2658static void nvme_remove_dead_ctrl_work(struct work_struct *work)
9a6b9458 2659{
5c8809e6 2660 struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
e75ec752 2661 struct pci_dev *pdev = to_pci_dev(dev->dev);
9a6b9458
KB		 2662
2663 if (pci_get_drvdata(pdev))
921920ab 2664 device_release_driver(&pdev->dev);
1673f1f0 2665 nvme_put_ctrl(&dev->ctrl);
9a6b9458
KB		 2666}
2667
1c63dc66 2668static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
9ca97374 2669{
1c63dc66 2670 *val = readl(to_nvme_dev(ctrl)->bar + off);
90667892 2671 return 0;
9ca97374
TH		 2672}
2673
5fd4ce1b 2674static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
4cc06521 2675{
5fd4ce1b
CH		 2676 writel(val, to_nvme_dev(ctrl)->bar + off);
2677 return 0;
2678}
4cc06521 2679
7fd8930f
CH		 2680static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2681{
3a8ecc93 2682 *val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off);
7fd8930f 2683 return 0;
4cc06521
KB		 2684}
2685
97c12223
KB		 2686static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
2687{
2688 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2689
2690 return snprintf(buf, size, "%s", dev_name(&pdev->dev));
2691}
2692
1c63dc66 2693static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
1a353d85 2694 .name = "pcie",
e439bb12 2695 .module = THIS_MODULE,
e0596ab2
LG		 2696 .flags = NVME_F_METADATA_SUPPORTED |
2697 NVME_F_PCI_P2PDMA,
1c63dc66 2698 .reg_read32 = nvme_pci_reg_read32,
5fd4ce1b 2699 .reg_write32 = nvme_pci_reg_write32,
7fd8930f 2700 .reg_read64 = nvme_pci_reg_read64,
1673f1f0 2701 .free_ctrl = nvme_pci_free_ctrl,
f866fc42 2702 .submit_async_event = nvme_pci_submit_async_event,
97c12223 2703 .get_address = nvme_pci_get_address,
1c63dc66 2704};
4cc06521 2705
b00a726a
KB		 2706static int nvme_dev_map(struct nvme_dev *dev)
2707{
b00a726a
KB		 2708 struct pci_dev *pdev = to_pci_dev(dev->dev);
2709
a1f447b3 2710 if (pci_request_mem_regions(pdev, "nvme"))
b00a726a
KB		 2711 return -ENODEV;
2712
97f6ef64 2713 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
b00a726a
KB		 2714 goto release;
2715
9fa196e7 2716 return 0;
b00a726a 2717 release:
9fa196e7
MG		 2718 pci_release_mem_regions(pdev);
2719 return -ENODEV;
b00a726a
KB		 2720}
2721
8427bbc2 2722static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
ff5350a8
AL		 2723{
2724 if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
2725 /*
2726 * Several Samsung devices seem to drop off the PCIe bus
2727 * randomly when APST is on and uses the deepest sleep state.
2728 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2729 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2730 * 950 PRO 256GB", but it seems to be restricted to two Dell
2731 * laptops.
2732 */
2733 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
2734 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
2735 dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
2736 return NVME_QUIRK_NO_DEEPEST_PS;
8427bbc2
KHF		 2737 } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
2738 /*
2739 * Samsung SSD 960 EVO drops off the PCIe bus after system
467c77d4
JJ		 2740 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
2741 * within few minutes after bootup on a Coffee Lake board -
2742 * ASUS PRIME Z370-A
8427bbc2
KHF		 2743 */
2744 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
467c77d4
JJ		 2745 (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") ||
2746 dmi_match(DMI_BOARD_NAME, "PRIME Z370-A")))
8427bbc2 2747 return NVME_QUIRK_NO_APST;
ff5350a8
AL		 2748 }
2749
2750 return 0;
2751}
2752
18119775
KB		 2753static void nvme_async_probe(void *data, async_cookie_t cookie)
2754{
2755 struct nvme_dev *dev = data;
80f513b5 2756
bd46a906 2757 flush_work(&dev->ctrl.reset_work);
18119775 2758 flush_work(&dev->ctrl.scan_work);
80f513b5 2759 nvme_put_ctrl(&dev->ctrl);
18119775
KB		 2760}
2761
8d85fce7 2762static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
b60503ba 2763{
a4aea562 2764 int node, result = -ENOMEM;
b60503ba 2765 struct nvme_dev *dev;
ff5350a8 2766 unsigned long quirks = id->driver_data;
943e942e 2767 size_t alloc_size;
b60503ba 2768
a4aea562
MB		 2769 node = dev_to_node(&pdev->dev);
2770 if (node == NUMA_NO_NODE)
2fa84351 2771 set_dev_node(&pdev->dev, first_memory_node);
a4aea562
MB		 2772
2773 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
b60503ba
MW		 2774 if (!dev)
2775 return -ENOMEM;
147b27e4 2776
3b6592f7
JA		 2777 dev->queues = kcalloc_node(max_queue_count(), sizeof(struct nvme_queue),
2778 GFP_KERNEL, node);
b60503ba
MW		 2779 if (!dev->queues)
2780 goto free;
2781
e75ec752 2782 dev->dev = get_device(&pdev->dev);
9a6b9458 2783 pci_set_drvdata(pdev, dev);
1c63dc66 2784
b00a726a
KB		 2785 result = nvme_dev_map(dev);
2786 if (result)
b00c9b7a 2787 goto put_pci;
b00a726a 2788
d86c4d8e 2789 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
5c8809e6 2790 INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
77bf25ea 2791 mutex_init(&dev->shutdown_lock);
b60503ba 2792
091b6092
MW		 2793 result = nvme_setup_prp_pools(dev);
2794 if (result)
b00c9b7a 2795 goto unmap;
4cc06521 2796
8427bbc2 2797 quirks |= check_vendor_combination_bug(pdev);
ff5350a8 2798
943e942e
JA		 2799 /*
2800 * Double check that our mempool alloc size will cover the biggest
2801 * command we support.
2802 */
2803 alloc_size = nvme_pci_iod_alloc_size(dev, NVME_MAX_KB_SZ,
2804 NVME_MAX_SEGS, true);
2805 WARN_ON_ONCE(alloc_size > PAGE_SIZE);
2806
2807 dev->iod_mempool = mempool_create_node(1, mempool_kmalloc,
2808 mempool_kfree,
2809 (void *) alloc_size,
2810 GFP_KERNEL, node);
2811 if (!dev->iod_mempool) {
2812 result = -ENOMEM;
2813 goto release_pools;
2814 }
2815
b6e44b4c
KB		 2816 result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
2817 quirks);
2818 if (result)
2819 goto release_mempool;
2820
1b3c47c1
SG		 2821 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
2822
bd46a906 2823 nvme_reset_ctrl(&dev->ctrl);
80f513b5 2824 nvme_get_ctrl(&dev->ctrl);
18119775 2825 async_schedule(nvme_async_probe, dev);
4caff8fc 2826
b60503ba
MW		 2827 return 0;
2828
b6e44b4c
KB		 2829 release_mempool:
2830 mempool_destroy(dev->iod_mempool);
0877cb0d 2831 release_pools:
091b6092 2832 nvme_release_prp_pools(dev);
b00c9b7a
CJ		 2833 unmap:
2834 nvme_dev_unmap(dev);
a96d4f5c 2835 put_pci:
e75ec752 2836 put_device(dev->dev);
b60503ba
MW		 2837 free:
2838 kfree(dev->queues);
b60503ba
MW		 2839 kfree(dev);
2840 return result;
2841}
2842
775755ed 2843static void nvme_reset_prepare(struct pci_dev *pdev)
f0d54a54 2844{
a6739479 2845 struct nvme_dev *dev = pci_get_drvdata(pdev);
f263fbb8 2846 nvme_dev_disable(dev, false);
775755ed 2847}
f0d54a54 2848
775755ed
CH		 2849static void nvme_reset_done(struct pci_dev *pdev)
2850{
f263fbb8 2851 struct nvme_dev *dev = pci_get_drvdata(pdev);
79c48ccf 2852 nvme_reset_ctrl_sync(&dev->ctrl);
f0d54a54
KB		 2853}
2854
09ece142
KB		 2855static void nvme_shutdown(struct pci_dev *pdev)
2856{
2857 struct nvme_dev *dev = pci_get_drvdata(pdev);
a5cdb68c 2858 nvme_dev_disable(dev, true);
09ece142
KB		 2859}
2860
f58944e2
KB		 2861/*
2862 * The driver's remove may be called on a device in a partially initialized
2863 * state. This function must not have any dependencies on the device state in
2864 * order to proceed.
2865 */
8d85fce7 2866static void nvme_remove(struct pci_dev *pdev)
b60503ba
MW		 2867{
2868 struct nvme_dev *dev = pci_get_drvdata(pdev);
9a6b9458 2869
bb8d261e 2870 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
9a6b9458 2871 pci_set_drvdata(pdev, NULL);
0ff9d4e1 2872
6db28eda 2873 if (!pci_device_is_present(pdev)) {
0ff9d4e1 2874 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
1d39e692 2875 nvme_dev_disable(dev, true);
cb4bfda6 2876 nvme_dev_remove_admin(dev);
6db28eda 2877 }
0ff9d4e1 2878
d86c4d8e 2879 flush_work(&dev->ctrl.reset_work);
d09f2b45
SG		 2880 nvme_stop_ctrl(&dev->ctrl);
2881 nvme_remove_namespaces(&dev->ctrl);
a5cdb68c 2882 nvme_dev_disable(dev, true);
9fe5c59f 2883 nvme_release_cmb(dev);
87ad72a5 2884 nvme_free_host_mem(dev);
a4aea562 2885 nvme_dev_remove_admin(dev);
a1a5ef99 2886 nvme_free_queues(dev, 0);
d09f2b45 2887 nvme_uninit_ctrl(&dev->ctrl);
9a6b9458 2888 nvme_release_prp_pools(dev);
b00a726a 2889 nvme_dev_unmap(dev);
1673f1f0 2890 nvme_put_ctrl(&dev->ctrl);
b60503ba
MW		 2891}
2892
671a6018 2893#ifdef CONFIG_PM_SLEEP
d916b1be
KB		 2894static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps)
2895{
2896 return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps);
2897}
2898
2899static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps)
2900{
2901 return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL);
2902}
2903
2904static int nvme_resume(struct device *dev)
2905{
2906 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
2907 struct nvme_ctrl *ctrl = &ndev->ctrl;
2908
4eaefe8c 2909 if (ndev->last_ps == U32_MAX ||
d916b1be
KB		 2910 nvme_set_power_state(ctrl, ndev->last_ps) != 0)
2911 nvme_reset_ctrl(ctrl);
2912 return 0;
2913}
2914
cd638946
KB		 2915static int nvme_suspend(struct device *dev)
2916{
2917 struct pci_dev *pdev = to_pci_dev(dev);
2918 struct nvme_dev *ndev = pci_get_drvdata(pdev);
d916b1be
KB		 2919 struct nvme_ctrl *ctrl = &ndev->ctrl;
2920 int ret = -EBUSY;
2921
4eaefe8c
RW		 2922 ndev->last_ps = U32_MAX;
2923
d916b1be
KB		 2924 /*
2925 * The platform does not remove power for a kernel managed suspend so
2926 * use host managed nvme power settings for lowest idle power if
2927 * possible. This should have quicker resume latency than a full device
2928 * shutdown. But if the firmware is involved after the suspend or the
2929 * device does not support any non-default power states, shut down the
2930 * device fully.
4eaefe8c
RW		 2931 *
2932 * If ASPM is not enabled for the device, shut down the device and allow
2933 * the PCI bus layer to put it into D3 in order to take the PCIe link
2934 * down, so as to allow the platform to achieve its minimum low-power
2935 * state (which may not be possible if the link is up).
d916b1be 2936 */
4eaefe8c 2937 if (pm_suspend_via_firmware() || !ctrl->npss ||
cb32de1b
ML		 2938 !pcie_aspm_enabled(pdev) ||
2939 (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND)) {
d916b1be
KB		 2940 nvme_dev_disable(ndev, true);
2941 return 0;
2942 }
2943
2944 nvme_start_freeze(ctrl);
2945 nvme_wait_freeze(ctrl);
2946 nvme_sync_queues(ctrl);
2947
2948 if (ctrl->state != NVME_CTRL_LIVE &&
2949 ctrl->state != NVME_CTRL_ADMIN_ONLY)
2950 goto unfreeze;
2951
d916b1be
KB		 2952 ret = nvme_get_power_state(ctrl, &ndev->last_ps);
2953 if (ret < 0)
2954 goto unfreeze;
2955
7cbb5c6f
ML		 2956 /*
2957 * A saved state prevents pci pm from generically controlling the
2958 * device's power. If we're using protocol specific settings, we don't
2959 * want pci interfering.
2960 */
2961 pci_save_state(pdev);
2962
d916b1be
KB		 2963 ret = nvme_set_power_state(ctrl, ctrl->npss);
2964 if (ret < 0)
2965 goto unfreeze;
2966
2967 if (ret) {
7cbb5c6f
ML		 2968 /* discard the saved state */
2969 pci_load_saved_state(pdev, NULL);
2970
d916b1be
KB		 2971 /*
2972 * Clearing npss forces a controller reset on resume. The
2973 * correct value will be resdicovered then.
2974 */
2975 nvme_dev_disable(ndev, true);
2976 ctrl->npss = 0;
2977 ret = 0;
d916b1be 2978 }
d916b1be
KB		 2979unfreeze:
2980 nvme_unfreeze(ctrl);
2981 return ret;
2982}
2983
2984static int nvme_simple_suspend(struct device *dev)
2985{
2986 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
cd638946 2987
a5cdb68c 2988 nvme_dev_disable(ndev, true);
cd638946
KB		 2989 return 0;
2990}
2991
d916b1be 2992static int nvme_simple_resume(struct device *dev)
cd638946
KB		 2993{
2994 struct pci_dev *pdev = to_pci_dev(dev);
2995 struct nvme_dev *ndev = pci_get_drvdata(pdev);
cd638946 2996
d86c4d8e 2997 nvme_reset_ctrl(&ndev->ctrl);
9a6b9458 2998 return 0;
cd638946
KB		 2999}
3000
21774222 3001static const struct dev_pm_ops nvme_dev_pm_ops = {
d916b1be
KB		 3002 .suspend = nvme_suspend,
3003 .resume = nvme_resume,
3004 .freeze = nvme_simple_suspend,
3005 .thaw = nvme_simple_resume,
3006 .poweroff = nvme_simple_suspend,
3007 .restore = nvme_simple_resume,
3008};
3009#endif /* CONFIG_PM_SLEEP */
b60503ba 3010
a0a3408e
KB		 3011static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
3012 pci_channel_state_t state)
3013{
3014 struct nvme_dev *dev = pci_get_drvdata(pdev);
3015
3016 /*
3017 * A frozen channel requires a reset. When detected, this method will
3018 * shutdown the controller to quiesce. The controller will be restarted
3019 * after the slot reset through driver's slot_reset callback.
3020 */
a0a3408e
KB		 3021 switch (state) {
3022 case pci_channel_io_normal:
3023 return PCI_ERS_RESULT_CAN_RECOVER;
3024 case pci_channel_io_frozen:
d011fb31
KB		 3025 dev_warn(dev->ctrl.device,
3026 "frozen state error detected, reset controller\n");
a5cdb68c 3027 nvme_dev_disable(dev, false);
a0a3408e
KB		 3028 return PCI_ERS_RESULT_NEED_RESET;
3029 case pci_channel_io_perm_failure:
d011fb31
KB		 3030 dev_warn(dev->ctrl.device,
3031 "failure state error detected, request disconnect\n");
a0a3408e
KB		 3032 return PCI_ERS_RESULT_DISCONNECT;
3033 }
3034 return PCI_ERS_RESULT_NEED_RESET;
3035}
3036
3037static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
3038{
3039 struct nvme_dev *dev = pci_get_drvdata(pdev);
3040
1b3c47c1 3041 dev_info(dev->ctrl.device, "restart after slot reset\n");
a0a3408e 3042 pci_restore_state(pdev);
d86c4d8e 3043 nvme_reset_ctrl(&dev->ctrl);
a0a3408e
KB		 3044 return PCI_ERS_RESULT_RECOVERED;
3045}
3046
3047static void nvme_error_resume(struct pci_dev *pdev)
3048{
72cd4cc2
KB		 3049 struct nvme_dev *dev = pci_get_drvdata(pdev);
3050
3051 flush_work(&dev->ctrl.reset_work);
a0a3408e
KB		 3052}
3053
1d352035 3054static const struct pci_error_handlers nvme_err_handler = {
b60503ba 3055 .error_detected = nvme_error_detected,
b60503ba
MW		 3056 .slot_reset = nvme_slot_reset,
3057 .resume = nvme_error_resume,
775755ed
CH		 3058 .reset_prepare = nvme_reset_prepare,
3059 .reset_done = nvme_reset_done,
b60503ba
MW		 3060};
3061
6eb0d698 3062static const struct pci_device_id nvme_id_table[] = {
106198ed 3063 { PCI_VDEVICE(INTEL, 0x0953),
08095e70 3064 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 3065 NVME_QUIRK_DEALLOCATE_ZEROES, },
99466e70
KB		 3066 { PCI_VDEVICE(INTEL, 0x0a53),
3067 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 3068 NVME_QUIRK_DEALLOCATE_ZEROES, },
99466e70
KB		 3069 { PCI_VDEVICE(INTEL, 0x0a54),
3070 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 3071 NVME_QUIRK_DEALLOCATE_ZEROES, },
f99cb7af
DWF		 3072 { PCI_VDEVICE(INTEL, 0x0a55),
3073 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3074 NVME_QUIRK_DEALLOCATE_ZEROES, },
50af47d0 3075 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */
9abd68ef
JA		 3076 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3077 NVME_QUIRK_MEDIUM_PRIO_SQ },
6299358d
JD		 3078 { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */
3079 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
540c801c 3080 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */
7b210e4e
CH		 3081 .driver_data = NVME_QUIRK_IDENTIFY_CNS |
3082 NVME_QUIRK_DISABLE_WRITE_ZEROES, },
0302ae60
MP		 3083 { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */
3084 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
54adc010
GP		 3085 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
3086 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
8c97eecc
JL		 3087 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */
3088 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
015282c9
WW		 3089 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
3090 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
d554b5e1
MP		 3091 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */
3092 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3093 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */
3094 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
608cc4b1
CH		 3095 { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */
3096 .driver_data = NVME_QUIRK_LIGHTNVM, },
3097 { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */
3098 .driver_data = NVME_QUIRK_LIGHTNVM, },
ea48e877
WX		 3099 { PCI_DEVICE(0x1d1d, 0x2601), /* CNEX Granby */
3100 .driver_data = NVME_QUIRK_LIGHTNVM, },
08b903b5
MN		 3101 { PCI_DEVICE(0x10ec, 0x5762), /* ADATA SX6000LNP */
3102 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
f03e42c6
GC		 3103 { PCI_DEVICE(0x1cc1, 0x8201), /* ADATA SX8200PNP 512GB */
3104 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3105 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
b60503ba 3106 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
c74dc780 3107 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) },
124298bd 3108 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
66341331
BH		 3109 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005),
3110 .driver_data = NVME_QUIRK_SINGLE_VECTOR |
d38e9f04
BH		 3111 NVME_QUIRK_128_BYTES_SQES |
3112 NVME_QUIRK_SHARED_TAGS },
b60503ba
MW		 3113 { 0, }
3114};
3115MODULE_DEVICE_TABLE(pci, nvme_id_table);
3116
3117static struct pci_driver nvme_driver = {
3118 .name = "nvme",
3119 .id_table = nvme_id_table,
3120 .probe = nvme_probe,
8d85fce7 3121 .remove = nvme_remove,
09ece142 3122 .shutdown = nvme_shutdown,
d916b1be 3123#ifdef CONFIG_PM_SLEEP
cd638946
KB		 3124 .driver = {
3125 .pm = &nvme_dev_pm_ops,
3126 },
d916b1be 3127#endif
74d986ab 3128 .sriov_configure = pci_sriov_configure_simple,
b60503ba
MW		 3129 .err_handler = &nvme_err_handler,
3130};
3131
3132static int __init nvme_init(void)
3133{
81101540
CH		 3134 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
3135 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
3136 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
612b7286 3137 BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2);
9a6327d2 3138 return pci_register_driver(&nvme_driver);
b60503ba
MW		 3139}
3140
3141static void __exit nvme_exit(void)
3142{
3143 pci_unregister_driver(&nvme_driver);
03e0f3a6 3144 flush_workqueue(nvme_wq);
b60503ba
MW		 3145}
3146
3147MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3148MODULE_LICENSE("GPL");
c78b4713 3149MODULE_VERSION("1.0");
b60503ba
MW		 3150module_init(nvme_init);
3151module_exit(nvme_exit);
Linux 6.x block layer and io_uring tree(s)