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nvme-pci: remove volatile cqes
[linux-2.6-block.git] / drivers / nvme / host / pci.c
CommitLineData
5f37396d 1// SPDX-License-Identifier: GPL-2.0
b60503ba
MW		 2/*
3 * NVM Express device driver
6eb0d698 4 * Copyright (c) 2011-2014, Intel Corporation.
b60503ba
MW		 5 */
6
a0a3408e 7#include <linux/aer.h>
18119775 8#include <linux/async.h>
b60503ba 9#include <linux/blkdev.h>
a4aea562 10#include <linux/blk-mq.h>
dca51e78 11#include <linux/blk-mq-pci.h>
ff5350a8 12#include <linux/dmi.h>
b60503ba
MW		 13#include <linux/init.h>
14#include <linux/interrupt.h>
15#include <linux/io.h>
b60503ba
MW		 16#include <linux/mm.h>
17#include <linux/module.h>
77bf25ea 18#include <linux/mutex.h>
d0877473 19#include <linux/once.h>
b60503ba 20#include <linux/pci.h>
d916b1be 21#include <linux/suspend.h>
e1e5e564 22#include <linux/t10-pi.h>
b60503ba 23#include <linux/types.h>
2f8e2c87 24#include <linux/io-64-nonatomic-lo-hi.h>
a98e58e5 25#include <linux/sed-opal.h>
0f238ff5 26#include <linux/pci-p2pdma.h>
797a796a 27
604c01d5 28#include "trace.h"
f11bb3e2
CH		 29#include "nvme.h"
30
c1e0cc7e 31#define SQ_SIZE(q) ((q)->q_depth << (q)->sqes)
8a1d09a6 32#define CQ_SIZE(q) ((q)->q_depth * sizeof(struct nvme_completion))
c965809c 33
a7a7cbe3 34#define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc))
9d43cf64 35
943e942e
JA		 36/*
37 * These can be higher, but we need to ensure that any command doesn't
38 * require an sg allocation that needs more than a page of data.
39 */
40#define NVME_MAX_KB_SZ 4096
41#define NVME_MAX_SEGS 127
42
58ffacb5
MW		 43static int use_threaded_interrupts;
44module_param(use_threaded_interrupts, int, 0);
45
8ffaadf7 46static bool use_cmb_sqes = true;
69f4eb9f 47module_param(use_cmb_sqes, bool, 0444);
8ffaadf7
JD		 48MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
49
87ad72a5
CH		 50static unsigned int max_host_mem_size_mb = 128;
51module_param(max_host_mem_size_mb, uint, 0444);
52MODULE_PARM_DESC(max_host_mem_size_mb,
53 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
1fa6aead 54
a7a7cbe3
CK		 55static unsigned int sgl_threshold = SZ_32K;
56module_param(sgl_threshold, uint, 0644);
57MODULE_PARM_DESC(sgl_threshold,
58 "Use SGLs when average request segment size is larger or equal to "
59 "this size. Use 0 to disable SGLs.");
60
b27c1e68 61static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
62static const struct kernel_param_ops io_queue_depth_ops = {
63 .set = io_queue_depth_set,
64 .get = param_get_int,
65};
66
67static int io_queue_depth = 1024;
68module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
69MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2");
70
3f68baf7
KB		 71static unsigned int write_queues;
72module_param(write_queues, uint, 0644);
3b6592f7
JA		 73MODULE_PARM_DESC(write_queues,
74 "Number of queues to use for writes. If not set, reads and writes "
75 "will share a queue set.");
76
3f68baf7
KB		 77static unsigned int poll_queues;
78module_param(poll_queues, uint, 0644);
4b04cc6a
JA		 79MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO.");
80
1c63dc66
CH		 81struct nvme_dev;
82struct nvme_queue;
b3fffdef 83
a5cdb68c 84static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
8fae268b 85static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode);
d4b4ff8e 86
1c63dc66
CH		 87/*
88 * Represents an NVM Express device. Each nvme_dev is a PCI function.
89 */
90struct nvme_dev {
147b27e4 91 struct nvme_queue *queues;
1c63dc66
CH		 92 struct blk_mq_tag_set tagset;
93 struct blk_mq_tag_set admin_tagset;
94 u32 __iomem *dbs;
95 struct device *dev;
96 struct dma_pool *prp_page_pool;
97 struct dma_pool *prp_small_pool;
1c63dc66
CH		 98 unsigned online_queues;
99 unsigned max_qid;
e20ba6e1 100 unsigned io_queues[HCTX_MAX_TYPES];
22b55601 101 unsigned int num_vecs;
1c63dc66 102 int q_depth;
c1e0cc7e 103 int io_sqes;
1c63dc66 104 u32 db_stride;
1c63dc66 105 void __iomem *bar;
97f6ef64 106 unsigned long bar_mapped_size;
5c8809e6 107 struct work_struct remove_work;
77bf25ea 108 struct mutex shutdown_lock;
1c63dc66 109 bool subsystem;
1c63dc66 110 u64 cmb_size;
0f238ff5 111 bool cmb_use_sqes;
1c63dc66 112 u32 cmbsz;
202021c1 113 u32 cmbloc;
1c63dc66 114 struct nvme_ctrl ctrl;
d916b1be 115 u32 last_ps;
87ad72a5 116
943e942e
JA		 117 mempool_t *iod_mempool;
118
87ad72a5 119 /* shadow doorbell buffer support: */
f9f38e33
HK		 120 u32 *dbbuf_dbs;
121 dma_addr_t dbbuf_dbs_dma_addr;
122 u32 *dbbuf_eis;
123 dma_addr_t dbbuf_eis_dma_addr;
87ad72a5
CH		 124
125 /* host memory buffer support: */
126 u64 host_mem_size;
127 u32 nr_host_mem_descs;
4033f35d 128 dma_addr_t host_mem_descs_dma;
87ad72a5
CH		 129 struct nvme_host_mem_buf_desc *host_mem_descs;
130 void **host_mem_desc_bufs;
4d115420 131};
1fa6aead 132
b27c1e68 133static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
134{
135 int n = 0, ret;
136
137 ret = kstrtoint(val, 10, &n);
138 if (ret != 0 || n < 2)
139 return -EINVAL;
140
141 return param_set_int(val, kp);
142}
143
f9f38e33
HK		 144static inline unsigned int sq_idx(unsigned int qid, u32 stride)
145{
146 return qid * 2 * stride;
147}
148
149static inline unsigned int cq_idx(unsigned int qid, u32 stride)
150{
151 return (qid * 2 + 1) * stride;
152}
153
1c63dc66
CH		 154static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
155{
156 return container_of(ctrl, struct nvme_dev, ctrl);
157}
158
b60503ba
MW		 159/*
160 * An NVM Express queue. Each device has at least two (one for admin
161 * commands and one for I/O commands).
162 */
163struct nvme_queue {
091b6092 164 struct nvme_dev *dev;
1ab0cd69 165 spinlock_t sq_lock;
c1e0cc7e 166 void *sq_cmds;
3a7afd8e
CH		 167 /* only used for poll queues: */
168 spinlock_t cq_poll_lock ____cacheline_aligned_in_smp;
74943d45 169 struct nvme_completion *cqes;
b60503ba
MW		 170 dma_addr_t sq_dma_addr;
171 dma_addr_t cq_dma_addr;
b60503ba
MW		 172 u32 __iomem *q_db;
173 u16 q_depth;
7c349dde 174 u16 cq_vector;
b60503ba 175 u16 sq_tail;
04f3eafd 176 u16 last_sq_tail;
b60503ba 177 u16 cq_head;
c30341dc 178 u16 qid;
e9539f47 179 u8 cq_phase;
c1e0cc7e 180 u8 sqes;
4e224106
CH		 181 unsigned long flags;
182#define NVMEQ_ENABLED 0
63223078 183#define NVMEQ_SQ_CMB 1
d1ed6aa1 184#define NVMEQ_DELETE_ERROR 2
7c349dde 185#define NVMEQ_POLLED 3
f9f38e33
HK		 186 u32 *dbbuf_sq_db;
187 u32 *dbbuf_cq_db;
188 u32 *dbbuf_sq_ei;
189 u32 *dbbuf_cq_ei;
d1ed6aa1 190 struct completion delete_done;
b60503ba
MW		 191};
192
71bd150c 193/*
9b048119
CH		 194 * The nvme_iod describes the data in an I/O.
195 *
196 * The sg pointer contains the list of PRP/SGL chunk allocations in addition
197 * to the actual struct scatterlist.
71bd150c
CH		 198 */
199struct nvme_iod {
d49187e9 200 struct nvme_request req;
f4800d6d 201 struct nvme_queue *nvmeq;
a7a7cbe3 202 bool use_sgl;
f4800d6d 203 int aborted;
71bd150c 204 int npages; /* In the PRP list. 0 means small pool in use */
71bd150c 205 int nents; /* Used in scatterlist */
71bd150c 206 dma_addr_t first_dma;
dff824b2 207 unsigned int dma_len; /* length of single DMA segment mapping */
783b94bd 208 dma_addr_t meta_dma;
f4800d6d 209 struct scatterlist *sg;
b60503ba
MW		 210};
211
3b6592f7
JA		 212static unsigned int max_io_queues(void)
213{
4b04cc6a 214 return num_possible_cpus() + write_queues + poll_queues;
3b6592f7
JA		 215}
216
217static unsigned int max_queue_count(void)
218{
219 /* IO queues + admin queue */
220 return 1 + max_io_queues();
221}
222
f9f38e33
HK		 223static inline unsigned int nvme_dbbuf_size(u32 stride)
224{
3b6592f7 225 return (max_queue_count() * 8 * stride);
f9f38e33
HK		 226}
227
228static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
229{
230 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
231
232 if (dev->dbbuf_dbs)
233 return 0;
234
235 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
236 &dev->dbbuf_dbs_dma_addr,
237 GFP_KERNEL);
238 if (!dev->dbbuf_dbs)
239 return -ENOMEM;
240 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
241 &dev->dbbuf_eis_dma_addr,
242 GFP_KERNEL);
243 if (!dev->dbbuf_eis) {
244 dma_free_coherent(dev->dev, mem_size,
245 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
246 dev->dbbuf_dbs = NULL;
247 return -ENOMEM;
248 }
249
250 return 0;
251}
252
253static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
254{
255 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
256
257 if (dev->dbbuf_dbs) {
258 dma_free_coherent(dev->dev, mem_size,
259 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
260 dev->dbbuf_dbs = NULL;
261 }
262 if (dev->dbbuf_eis) {
263 dma_free_coherent(dev->dev, mem_size,
264 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
265 dev->dbbuf_eis = NULL;
266 }
267}
268
269static void nvme_dbbuf_init(struct nvme_dev *dev,
270 struct nvme_queue *nvmeq, int qid)
271{
272 if (!dev->dbbuf_dbs || !qid)
273 return;
274
275 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
276 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
277 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
278 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
279}
280
281static void nvme_dbbuf_set(struct nvme_dev *dev)
282{
283 struct nvme_command c;
284
285 if (!dev->dbbuf_dbs)
286 return;
287
288 memset(&c, 0, sizeof(c));
289 c.dbbuf.opcode = nvme_admin_dbbuf;
290 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
291 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
292
293 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
9bdcfb10 294 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
f9f38e33
HK		 295 /* Free memory and continue on */
296 nvme_dbbuf_dma_free(dev);
297 }
298}
299
300static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
301{
302 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
303}
304
305/* Update dbbuf and return true if an MMIO is required */
306static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
307 volatile u32 *dbbuf_ei)
308{
309 if (dbbuf_db) {
310 u16 old_value;
311
312 /*
313 * Ensure that the queue is written before updating
314 * the doorbell in memory
315 */
316 wmb();
317
318 old_value = *dbbuf_db;
319 *dbbuf_db = value;
320
f1ed3df2
MW		 321 /*
322 * Ensure that the doorbell is updated before reading the event
323 * index from memory. The controller needs to provide similar
324 * ordering to ensure the envent index is updated before reading
325 * the doorbell.
326 */
327 mb();
328
f9f38e33
HK		 329 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value))
330 return false;
331 }
332
333 return true;
b60503ba
MW		 334}
335
ac3dd5bd
JA		 336/*
337 * Will slightly overestimate the number of pages needed. This is OK
338 * as it only leads to a small amount of wasted memory for the lifetime of
339 * the I/O.
340 */
341static int nvme_npages(unsigned size, struct nvme_dev *dev)
342{
5fd4ce1b
CH		 343 unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size,
344 dev->ctrl.page_size);
ac3dd5bd
JA		 345 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
346}
347
a7a7cbe3
CK		 348/*
349 * Calculates the number of pages needed for the SGL segments. For example a 4k
350 * page can accommodate 256 SGL descriptors.
351 */
352static int nvme_pci_npages_sgl(unsigned int num_seg)
ac3dd5bd 353{
a7a7cbe3 354 return DIV_ROUND_UP(num_seg * sizeof(struct nvme_sgl_desc), PAGE_SIZE);
f4800d6d 355}
ac3dd5bd 356
a7a7cbe3
CK		 357static unsigned int nvme_pci_iod_alloc_size(struct nvme_dev *dev,
358 unsigned int size, unsigned int nseg, bool use_sgl)
f4800d6d 359{
a7a7cbe3
CK		 360 size_t alloc_size;
361
362 if (use_sgl)
363 alloc_size = sizeof(__le64 *) * nvme_pci_npages_sgl(nseg);
364 else
365 alloc_size = sizeof(__le64 *) * nvme_npages(size, dev);
366
367 return alloc_size + sizeof(struct scatterlist) * nseg;
f4800d6d 368}
ac3dd5bd 369
a4aea562
MB		 370static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
371 unsigned int hctx_idx)
e85248e5 372{
a4aea562 373 struct nvme_dev *dev = data;
147b27e4 374 struct nvme_queue *nvmeq = &dev->queues[0];
a4aea562 375
42483228
KB		 376 WARN_ON(hctx_idx != 0);
377 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
42483228 378
a4aea562
MB		 379 hctx->driver_data = nvmeq;
380 return 0;
e85248e5
MW		 381}
382
a4aea562
MB		 383static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
384 unsigned int hctx_idx)
b60503ba 385{
a4aea562 386 struct nvme_dev *dev = data;
147b27e4 387 struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
a4aea562 388
42483228 389 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
a4aea562
MB		 390 hctx->driver_data = nvmeq;
391 return 0;
b60503ba
MW		 392}
393
d6296d39
CH		 394static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req,
395 unsigned int hctx_idx, unsigned int numa_node)
b60503ba 396{
d6296d39 397 struct nvme_dev *dev = set->driver_data;
f4800d6d 398 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
0350815a 399 int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0;
147b27e4 400 struct nvme_queue *nvmeq = &dev->queues[queue_idx];
a4aea562
MB		 401
402 BUG_ON(!nvmeq);
f4800d6d 403 iod->nvmeq = nvmeq;
59e29ce6
SG		 404
405 nvme_req(req)->ctrl = &dev->ctrl;
a4aea562
MB		 406 return 0;
407}
408
3b6592f7
JA		 409static int queue_irq_offset(struct nvme_dev *dev)
410{
411 /* if we have more than 1 vec, admin queue offsets us by 1 */
412 if (dev->num_vecs > 1)
413 return 1;
414
415 return 0;
416}
417
dca51e78
CH		 418static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
419{
420 struct nvme_dev *dev = set->driver_data;
3b6592f7
JA		 421 int i, qoff, offset;
422
423 offset = queue_irq_offset(dev);
424 for (i = 0, qoff = 0; i < set->nr_maps; i++) {
425 struct blk_mq_queue_map *map = &set->map[i];
426
427 map->nr_queues = dev->io_queues[i];
428 if (!map->nr_queues) {
e20ba6e1 429 BUG_ON(i == HCTX_TYPE_DEFAULT);
7e849dd9 430 continue;
3b6592f7
JA		 431 }
432
4b04cc6a
JA		 433 /*
434 * The poll queue(s) doesn't have an IRQ (and hence IRQ
435 * affinity), so use the regular blk-mq cpu mapping
436 */
3b6592f7 437 map->queue_offset = qoff;
cb9e0e50 438 if (i != HCTX_TYPE_POLL && offset)
4b04cc6a
JA		 439 blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset);
440 else
441 blk_mq_map_queues(map);
3b6592f7
JA		 442 qoff += map->nr_queues;
443 offset += map->nr_queues;
444 }
445
446 return 0;
dca51e78
CH		 447}
448
04f3eafd
JA		 449/*
450 * Write sq tail if we are asked to, or if the next command would wrap.
451 */
452static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq)
453{
454 if (!write_sq) {
455 u16 next_tail = nvmeq->sq_tail + 1;
456
457 if (next_tail == nvmeq->q_depth)
458 next_tail = 0;
459 if (next_tail != nvmeq->last_sq_tail)
460 return;
461 }
462
463 if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail,
464 nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei))
465 writel(nvmeq->sq_tail, nvmeq->q_db);
466 nvmeq->last_sq_tail = nvmeq->sq_tail;
467}
468
b60503ba 469/**
90ea5ca4 470 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
b60503ba
MW		 471 * @nvmeq: The queue to use
472 * @cmd: The command to send
04f3eafd 473 * @write_sq: whether to write to the SQ doorbell
b60503ba 474 */
04f3eafd
JA		 475static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd,
476 bool write_sq)
b60503ba 477{
90ea5ca4 478 spin_lock(&nvmeq->sq_lock);
c1e0cc7e
BH		 479 memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes),
480 cmd, sizeof(*cmd));
90ea5ca4
CH		 481 if (++nvmeq->sq_tail == nvmeq->q_depth)
482 nvmeq->sq_tail = 0;
04f3eafd
JA		 483 nvme_write_sq_db(nvmeq, write_sq);
484 spin_unlock(&nvmeq->sq_lock);
485}
486
487static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx)
488{
489 struct nvme_queue *nvmeq = hctx->driver_data;
490
491 spin_lock(&nvmeq->sq_lock);
492 if (nvmeq->sq_tail != nvmeq->last_sq_tail)
493 nvme_write_sq_db(nvmeq, true);
90ea5ca4 494 spin_unlock(&nvmeq->sq_lock);
b60503ba
MW		 495}
496
a7a7cbe3 497static void **nvme_pci_iod_list(struct request *req)
b60503ba 498{
f4800d6d 499 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3 500 return (void **)(iod->sg + blk_rq_nr_phys_segments(req));
b60503ba
MW		 501}
502
955b1b5a
MI		 503static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req)
504{
505 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
20469a37 506 int nseg = blk_rq_nr_phys_segments(req);
955b1b5a
MI		 507 unsigned int avg_seg_size;
508
20469a37
KB		 509 if (nseg == 0)
510 return false;
511
512 avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
955b1b5a
MI		 513
514 if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1))))
515 return false;
516 if (!iod->nvmeq->qid)
517 return false;
518 if (!sgl_threshold || avg_seg_size < sgl_threshold)
519 return false;
520 return true;
521}
522
7fe07d14 523static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
b60503ba 524{
f4800d6d 525 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3
CK		 526 const int last_prp = dev->ctrl.page_size / sizeof(__le64) - 1;
527 dma_addr_t dma_addr = iod->first_dma, next_dma_addr;
eca18b23 528 int i;
eca18b23 529
dff824b2 530 if (iod->dma_len) {
f2fa006f
IR		 531 dma_unmap_page(dev->dev, dma_addr, iod->dma_len,
532 rq_dma_dir(req));
dff824b2 533 return;
7fe07d14
CH		 534 }
535
dff824b2
CH		 536 WARN_ON_ONCE(!iod->nents);
537
7f73eac3
LG		 538 if (is_pci_p2pdma_page(sg_page(iod->sg)))
539 pci_p2pdma_unmap_sg(dev->dev, iod->sg, iod->nents,
540 rq_dma_dir(req));
541 else
dff824b2
CH		 542 dma_unmap_sg(dev->dev, iod->sg, iod->nents, rq_dma_dir(req));
543
544
eca18b23 545 if (iod->npages == 0)
a7a7cbe3
CK		 546 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0],
547 dma_addr);
548
eca18b23 549 for (i = 0; i < iod->npages; i++) {
a7a7cbe3
CK		 550 void *addr = nvme_pci_iod_list(req)[i];
551
552 if (iod->use_sgl) {
553 struct nvme_sgl_desc *sg_list = addr;
554
555 next_dma_addr =
556 le64_to_cpu((sg_list[SGES_PER_PAGE - 1]).addr);
557 } else {
558 __le64 *prp_list = addr;
559
560 next_dma_addr = le64_to_cpu(prp_list[last_prp]);
561 }
562
563 dma_pool_free(dev->prp_page_pool, addr, dma_addr);
564 dma_addr = next_dma_addr;
eca18b23 565 }
ac3dd5bd 566
d43f1ccf 567 mempool_free(iod->sg, dev->iod_mempool);
b4ff9c8d
KB		 568}
569
d0877473
KB		 570static void nvme_print_sgl(struct scatterlist *sgl, int nents)
571{
572 int i;
573 struct scatterlist *sg;
574
575 for_each_sg(sgl, sg, nents, i) {
576 dma_addr_t phys = sg_phys(sg);
577 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
578 "dma_address:%pad dma_length:%d\n",
579 i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
580 sg_dma_len(sg));
581 }
582}
583
a7a7cbe3
CK		 584static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
585 struct request *req, struct nvme_rw_command *cmnd)
ff22b54f 586{
f4800d6d 587 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
99802a7a 588 struct dma_pool *pool;
b131c61d 589 int length = blk_rq_payload_bytes(req);
eca18b23 590 struct scatterlist *sg = iod->sg;
ff22b54f
MW		 591 int dma_len = sg_dma_len(sg);
592 u64 dma_addr = sg_dma_address(sg);
5fd4ce1b 593 u32 page_size = dev->ctrl.page_size;
f137e0f1 594 int offset = dma_addr & (page_size - 1);
e025344c 595 __le64 *prp_list;
a7a7cbe3 596 void **list = nvme_pci_iod_list(req);
e025344c 597 dma_addr_t prp_dma;
eca18b23 598 int nprps, i;
ff22b54f 599
1d090624 600 length -= (page_size - offset);
5228b328
JS		 601 if (length <= 0) {
602 iod->first_dma = 0;
a7a7cbe3 603 goto done;
5228b328 604 }
ff22b54f 605
1d090624 606 dma_len -= (page_size - offset);
ff22b54f 607 if (dma_len) {
1d090624 608 dma_addr += (page_size - offset);
ff22b54f
MW		 609 } else {
610 sg = sg_next(sg);
611 dma_addr = sg_dma_address(sg);
612 dma_len = sg_dma_len(sg);
613 }
614
1d090624 615 if (length <= page_size) {
edd10d33 616 iod->first_dma = dma_addr;
a7a7cbe3 617 goto done;
e025344c
SMM		 618 }
619
1d090624 620 nprps = DIV_ROUND_UP(length, page_size);
99802a7a
MW		 621 if (nprps <= (256 / 8)) {
622 pool = dev->prp_small_pool;
eca18b23 623 iod->npages = 0;
99802a7a
MW		 624 } else {
625 pool = dev->prp_page_pool;
eca18b23 626 iod->npages = 1;
99802a7a
MW		 627 }
628
69d2b571 629 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
b77954cb 630 if (!prp_list) {
edd10d33 631 iod->first_dma = dma_addr;
eca18b23 632 iod->npages = -1;
86eea289 633 return BLK_STS_RESOURCE;
b77954cb 634 }
eca18b23
MW		 635 list[0] = prp_list;
636 iod->first_dma = prp_dma;
e025344c
SMM		 637 i = 0;
638 for (;;) {
1d090624 639 if (i == page_size >> 3) {
e025344c 640 __le64 *old_prp_list = prp_list;
69d2b571 641 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
eca18b23 642 if (!prp_list)
86eea289 643 return BLK_STS_RESOURCE;
eca18b23 644 list[iod->npages++] = prp_list;
7523d834
MW		 645 prp_list[0] = old_prp_list[i - 1];
646 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
647 i = 1;
e025344c
SMM		 648 }
649 prp_list[i++] = cpu_to_le64(dma_addr);
1d090624
KB		 650 dma_len -= page_size;
651 dma_addr += page_size;
652 length -= page_size;
e025344c
SMM		 653 if (length <= 0)
654 break;
655 if (dma_len > 0)
656 continue;
86eea289
KB		 657 if (unlikely(dma_len < 0))
658 goto bad_sgl;
e025344c
SMM		 659 sg = sg_next(sg);
660 dma_addr = sg_dma_address(sg);
661 dma_len = sg_dma_len(sg);
ff22b54f
MW		 662 }
663
a7a7cbe3
CK		 664done:
665 cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
666 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
667
86eea289
KB		 668 return BLK_STS_OK;
669
670 bad_sgl:
d0877473
KB		 671 WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents),
672 "Invalid SGL for payload:%d nents:%d\n",
673 blk_rq_payload_bytes(req), iod->nents);
86eea289 674 return BLK_STS_IOERR;
ff22b54f
MW		 675}
676
a7a7cbe3
CK		 677static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
678 struct scatterlist *sg)
679{
680 sge->addr = cpu_to_le64(sg_dma_address(sg));
681 sge->length = cpu_to_le32(sg_dma_len(sg));
682 sge->type = NVME_SGL_FMT_DATA_DESC << 4;
683}
684
685static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
686 dma_addr_t dma_addr, int entries)
687{
688 sge->addr = cpu_to_le64(dma_addr);
689 if (entries < SGES_PER_PAGE) {
690 sge->length = cpu_to_le32(entries * sizeof(*sge));
691 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
692 } else {
693 sge->length = cpu_to_le32(PAGE_SIZE);
694 sge->type = NVME_SGL_FMT_SEG_DESC << 4;
695 }
696}
697
698static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
b0f2853b 699 struct request *req, struct nvme_rw_command *cmd, int entries)
a7a7cbe3
CK		 700{
701 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3
CK		 702 struct dma_pool *pool;
703 struct nvme_sgl_desc *sg_list;
704 struct scatterlist *sg = iod->sg;
a7a7cbe3 705 dma_addr_t sgl_dma;
b0f2853b 706 int i = 0;
a7a7cbe3 707
a7a7cbe3
CK		 708 /* setting the transfer type as SGL */
709 cmd->flags = NVME_CMD_SGL_METABUF;
710
b0f2853b 711 if (entries == 1) {
a7a7cbe3
CK		 712 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
713 return BLK_STS_OK;
714 }
715
716 if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
717 pool = dev->prp_small_pool;
718 iod->npages = 0;
719 } else {
720 pool = dev->prp_page_pool;
721 iod->npages = 1;
722 }
723
724 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
725 if (!sg_list) {
726 iod->npages = -1;
727 return BLK_STS_RESOURCE;
728 }
729
730 nvme_pci_iod_list(req)[0] = sg_list;
731 iod->first_dma = sgl_dma;
732
733 nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
734
735 do {
736 if (i == SGES_PER_PAGE) {
737 struct nvme_sgl_desc *old_sg_desc = sg_list;
738 struct nvme_sgl_desc *link = &old_sg_desc[i - 1];
739
740 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
741 if (!sg_list)
742 return BLK_STS_RESOURCE;
743
744 i = 0;
745 nvme_pci_iod_list(req)[iod->npages++] = sg_list;
746 sg_list[i++] = *link;
747 nvme_pci_sgl_set_seg(link, sgl_dma, entries);
748 }
749
750 nvme_pci_sgl_set_data(&sg_list[i++], sg);
a7a7cbe3 751 sg = sg_next(sg);
b0f2853b 752 } while (--entries > 0);
a7a7cbe3 753
a7a7cbe3
CK		 754 return BLK_STS_OK;
755}
756
dff824b2
CH		 757static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev,
758 struct request *req, struct nvme_rw_command *cmnd,
759 struct bio_vec *bv)
760{
761 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a4f40484
KH		 762 unsigned int offset = bv->bv_offset & (dev->ctrl.page_size - 1);
763 unsigned int first_prp_len = dev->ctrl.page_size - offset;
dff824b2
CH		 764
765 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
766 if (dma_mapping_error(dev->dev, iod->first_dma))
767 return BLK_STS_RESOURCE;
768 iod->dma_len = bv->bv_len;
769
770 cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma);
771 if (bv->bv_len > first_prp_len)
772 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len);
773 return 0;
774}
775
29791057
CH		 776static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev,
777 struct request *req, struct nvme_rw_command *cmnd,
778 struct bio_vec *bv)
779{
780 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
781
782 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
783 if (dma_mapping_error(dev->dev, iod->first_dma))
784 return BLK_STS_RESOURCE;
785 iod->dma_len = bv->bv_len;
786
049bf372 787 cmnd->flags = NVME_CMD_SGL_METABUF;
29791057
CH		 788 cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma);
789 cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len);
790 cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4;
791 return 0;
792}
793
fc17b653 794static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
b131c61d 795 struct nvme_command *cmnd)
d29ec824 796{
f4800d6d 797 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
70479b71 798 blk_status_t ret = BLK_STS_RESOURCE;
b0f2853b 799 int nr_mapped;
d29ec824 800
dff824b2
CH		 801 if (blk_rq_nr_phys_segments(req) == 1) {
802 struct bio_vec bv = req_bvec(req);
803
804 if (!is_pci_p2pdma_page(bv.bv_page)) {
805 if (bv.bv_offset + bv.bv_len <= dev->ctrl.page_size * 2)
806 return nvme_setup_prp_simple(dev, req,
807 &cmnd->rw, &bv);
29791057
CH		 808
809 if (iod->nvmeq->qid &&
810 dev->ctrl.sgls & ((1 << 0) | (1 << 1)))
811 return nvme_setup_sgl_simple(dev, req,
812 &cmnd->rw, &bv);
dff824b2
CH		 813 }
814 }
815
816 iod->dma_len = 0;
d43f1ccf
CH		 817 iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC);
818 if (!iod->sg)
819 return BLK_STS_RESOURCE;
f9d03f96 820 sg_init_table(iod->sg, blk_rq_nr_phys_segments(req));
70479b71 821 iod->nents = blk_rq_map_sg(req->q, req, iod->sg);
ba1ca37e
CH		 822 if (!iod->nents)
823 goto out;
d29ec824 824
e0596ab2 825 if (is_pci_p2pdma_page(sg_page(iod->sg)))
2b9f4bb2
LG		 826 nr_mapped = pci_p2pdma_map_sg_attrs(dev->dev, iod->sg,
827 iod->nents, rq_dma_dir(req), DMA_ATTR_NO_WARN);
e0596ab2
LG		 828 else
829 nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents,
70479b71 830 rq_dma_dir(req), DMA_ATTR_NO_WARN);
b0f2853b 831 if (!nr_mapped)
ba1ca37e 832 goto out;
d29ec824 833
70479b71 834 iod->use_sgl = nvme_pci_use_sgls(dev, req);
955b1b5a 835 if (iod->use_sgl)
b0f2853b 836 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped);
a7a7cbe3
CK		 837 else
838 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
4aedb705 839out:
86eea289 840 if (ret != BLK_STS_OK)
4aedb705
CH		 841 nvme_unmap_data(dev, req);
842 return ret;
843}
3045c0d0 844
4aedb705
CH		 845static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req,
846 struct nvme_command *cmnd)
847{
848 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
00df5cb4 849
4aedb705
CH		 850 iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req),
851 rq_dma_dir(req), 0);
852 if (dma_mapping_error(dev->dev, iod->meta_dma))
853 return BLK_STS_IOERR;
854 cmnd->rw.metadata = cpu_to_le64(iod->meta_dma);
855 return 0;
00df5cb4
MW		 856}
857
d29ec824
CH		 858/*
859 * NOTE: ns is NULL when called on the admin queue.
860 */
fc17b653 861static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
a4aea562 862 const struct blk_mq_queue_data *bd)
edd10d33 863{
a4aea562
MB		 864 struct nvme_ns *ns = hctx->queue->queuedata;
865 struct nvme_queue *nvmeq = hctx->driver_data;
d29ec824 866 struct nvme_dev *dev = nvmeq->dev;
a4aea562 867 struct request *req = bd->rq;
9b048119 868 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
ba1ca37e 869 struct nvme_command cmnd;
ebe6d874 870 blk_status_t ret;
e1e5e564 871
9b048119
CH		 872 iod->aborted = 0;
873 iod->npages = -1;
874 iod->nents = 0;
875
d1f06f4a
JA		 876 /*
877 * We should not need to do this, but we're still using this to
878 * ensure we can drain requests on a dying queue.
879 */
4e224106 880 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
d1f06f4a
JA		 881 return BLK_STS_IOERR;
882
f9d03f96 883 ret = nvme_setup_cmd(ns, req, &cmnd);
fc17b653 884 if (ret)
f4800d6d 885 return ret;
a4aea562 886
fc17b653 887 if (blk_rq_nr_phys_segments(req)) {
b131c61d 888 ret = nvme_map_data(dev, req, &cmnd);
fc17b653 889 if (ret)
9b048119 890 goto out_free_cmd;
fc17b653 891 }
a4aea562 892
4aedb705
CH		 893 if (blk_integrity_rq(req)) {
894 ret = nvme_map_metadata(dev, req, &cmnd);
895 if (ret)
896 goto out_unmap_data;
897 }
898
aae239e1 899 blk_mq_start_request(req);
04f3eafd 900 nvme_submit_cmd(nvmeq, &cmnd, bd->last);
fc17b653 901 return BLK_STS_OK;
4aedb705
CH		 902out_unmap_data:
903 nvme_unmap_data(dev, req);
f9d03f96
CH		 904out_free_cmd:
905 nvme_cleanup_cmd(req);
ba1ca37e 906 return ret;
b60503ba 907}
e1e5e564 908
77f02a7a 909static void nvme_pci_complete_rq(struct request *req)
eee417b0 910{
f4800d6d 911 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
4aedb705 912 struct nvme_dev *dev = iod->nvmeq->dev;
a4aea562 913
4aedb705
CH		 914 if (blk_integrity_rq(req))
915 dma_unmap_page(dev->dev, iod->meta_dma,
916 rq_integrity_vec(req)->bv_len, rq_data_dir(req));
b15c592d 917 if (blk_rq_nr_phys_segments(req))
4aedb705 918 nvme_unmap_data(dev, req);
77f02a7a 919 nvme_complete_rq(req);
b60503ba
MW		 920}
921
d783e0bd 922/* We read the CQE phase first to check if the rest of the entry is valid */
750dde44 923static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq)
d783e0bd 924{
74943d45
KB		 925 struct nvme_completion *hcqe = &nvmeq->cqes[nvmeq->cq_head];
926
927 return (le16_to_cpu(READ_ONCE(hcqe->status)) & 1) == nvmeq->cq_phase;
d783e0bd
MR		 928}
929
eb281c82 930static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
b60503ba 931{
eb281c82 932 u16 head = nvmeq->cq_head;
adf68f21 933
397c699f
KB		 934 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
935 nvmeq->dbbuf_cq_ei))
936 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
eb281c82 937}
aae239e1 938
cfa27356
CH		 939static inline struct blk_mq_tags *nvme_queue_tagset(struct nvme_queue *nvmeq)
940{
941 if (!nvmeq->qid)
942 return nvmeq->dev->admin_tagset.tags[0];
943 return nvmeq->dev->tagset.tags[nvmeq->qid - 1];
944}
945
5cb525c8 946static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx)
83a12fb7 947{
74943d45 948 struct nvme_completion *cqe = &nvmeq->cqes[idx];
83a12fb7 949 struct request *req;
adf68f21 950
83a12fb7
SG		 951 if (unlikely(cqe->command_id >= nvmeq->q_depth)) {
952 dev_warn(nvmeq->dev->ctrl.device,
953 "invalid id %d completed on queue %d\n",
954 cqe->command_id, le16_to_cpu(cqe->sq_id));
955 return;
b60503ba
MW		 956 }
957
83a12fb7
SG		 958 /*
959 * AEN requests are special as they don't time out and can
960 * survive any kind of queue freeze and often don't respond to
961 * aborts. We don't even bother to allocate a struct request
962 * for them but rather special case them here.
963 */
58a8df67 964 if (unlikely(nvme_is_aen_req(nvmeq->qid, cqe->command_id))) {
83a12fb7
SG		 965 nvme_complete_async_event(&nvmeq->dev->ctrl,
966 cqe->status, &cqe->result);
a0fa9647 967 return;
83a12fb7 968 }
b60503ba 969
cfa27356 970 req = blk_mq_tag_to_rq(nvme_queue_tagset(nvmeq), cqe->command_id);
604c01d5 971 trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail);
83a12fb7
SG		 972 nvme_end_request(req, cqe->status, cqe->result);
973}
b60503ba 974
5cb525c8
JA		 975static inline void nvme_update_cq_head(struct nvme_queue *nvmeq)
976{
a8de6639
AD		 977 u16 tmp = nvmeq->cq_head + 1;
978
979 if (tmp == nvmeq->q_depth) {
5cb525c8 980 nvmeq->cq_head = 0;
e2a366a4 981 nvmeq->cq_phase ^= 1;
a8de6639
AD		 982 } else {
983 nvmeq->cq_head = tmp;
b60503ba 984 }
a0fa9647
JA		 985}
986
324b494c 987static inline int nvme_process_cq(struct nvme_queue *nvmeq)
a0fa9647 988{
1052b8ac 989 int found = 0;
b60503ba 990
1052b8ac 991 while (nvme_cqe_pending(nvmeq)) {
bf392a5d 992 found++;
324b494c 993 nvme_handle_cqe(nvmeq, nvmeq->cq_head);
5cb525c8 994 nvme_update_cq_head(nvmeq);
920d13a8 995 }
eb281c82 996
324b494c 997 if (found)
920d13a8 998 nvme_ring_cq_doorbell(nvmeq);
5cb525c8 999 return found;
b60503ba
MW		 1000}
1001
1002static irqreturn_t nvme_irq(int irq, void *data)
58ffacb5 1003{
58ffacb5 1004 struct nvme_queue *nvmeq = data;
68fa9dbe 1005 irqreturn_t ret = IRQ_NONE;
5cb525c8 1006
3a7afd8e
CH		 1007 /*
1008 * The rmb/wmb pair ensures we see all updates from a previous run of
1009 * the irq handler, even if that was on another CPU.
1010 */
1011 rmb();
324b494c
KB		 1012 if (nvme_process_cq(nvmeq))
1013 ret = IRQ_HANDLED;
3a7afd8e 1014 wmb();
5cb525c8 1015
68fa9dbe 1016 return ret;
58ffacb5
MW		 1017}
1018
1019static irqreturn_t nvme_irq_check(int irq, void *data)
1020{
1021 struct nvme_queue *nvmeq = data;
750dde44 1022 if (nvme_cqe_pending(nvmeq))
d783e0bd
MR		 1023 return IRQ_WAKE_THREAD;
1024 return IRQ_NONE;
58ffacb5
MW		 1025}
1026
0b2a8a9f 1027/*
fa059b85 1028 * Poll for completions for any interrupt driven queue
0b2a8a9f
CH		 1029 * Can be called from any context.
1030 */
fa059b85 1031static void nvme_poll_irqdisable(struct nvme_queue *nvmeq)
a0fa9647 1032{
3a7afd8e 1033 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
a0fa9647 1034
fa059b85 1035 WARN_ON_ONCE(test_bit(NVMEQ_POLLED, &nvmeq->flags));
442e19b7 1036
fa059b85
KB		 1037 disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1038 nvme_process_cq(nvmeq);
1039 enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
a0fa9647
JA		 1040}
1041
9743139c 1042static int nvme_poll(struct blk_mq_hw_ctx *hctx)
dabcefab
JA		 1043{
1044 struct nvme_queue *nvmeq = hctx->driver_data;
dabcefab
JA		 1045 bool found;
1046
1047 if (!nvme_cqe_pending(nvmeq))
1048 return 0;
1049
3a7afd8e 1050 spin_lock(&nvmeq->cq_poll_lock);
324b494c 1051 found = nvme_process_cq(nvmeq);
3a7afd8e 1052 spin_unlock(&nvmeq->cq_poll_lock);
dabcefab 1053
dabcefab
JA		 1054 return found;
1055}
1056
ad22c355 1057static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
b60503ba 1058{
f866fc42 1059 struct nvme_dev *dev = to_nvme_dev(ctrl);
147b27e4 1060 struct nvme_queue *nvmeq = &dev->queues[0];
a4aea562 1061 struct nvme_command c;
b60503ba 1062
a4aea562
MB		 1063 memset(&c, 0, sizeof(c));
1064 c.common.opcode = nvme_admin_async_event;
ad22c355 1065 c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
04f3eafd 1066 nvme_submit_cmd(nvmeq, &c, true);
f705f837
CH		 1067}
1068
b60503ba 1069static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
f705f837 1070{
b60503ba
MW		 1071 struct nvme_command c;
1072
1073 memset(&c, 0, sizeof(c));
1074 c.delete_queue.opcode = opcode;
1075 c.delete_queue.qid = cpu_to_le16(id);
1076
1c63dc66 1077 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1078}
1079
b60503ba 1080static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
a8e3e0bb 1081 struct nvme_queue *nvmeq, s16 vector)
b60503ba 1082{
b60503ba 1083 struct nvme_command c;
4b04cc6a
JA		 1084 int flags = NVME_QUEUE_PHYS_CONTIG;
1085
7c349dde 1086 if (!test_bit(NVMEQ_POLLED, &nvmeq->flags))
4b04cc6a 1087 flags |= NVME_CQ_IRQ_ENABLED;
b60503ba 1088
d29ec824 1089 /*
16772ae6 1090 * Note: we (ab)use the fact that the prp fields survive if no data
d29ec824
CH		 1091 * is attached to the request.
1092 */
b60503ba
MW		 1093 memset(&c, 0, sizeof(c));
1094 c.create_cq.opcode = nvme_admin_create_cq;
1095 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1096 c.create_cq.cqid = cpu_to_le16(qid);
1097 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1098 c.create_cq.cq_flags = cpu_to_le16(flags);
7c349dde 1099 c.create_cq.irq_vector = cpu_to_le16(vector);
b60503ba 1100
1c63dc66 1101 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1102}
1103
1104static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1105 struct nvme_queue *nvmeq)
1106{
9abd68ef 1107 struct nvme_ctrl *ctrl = &dev->ctrl;
b60503ba 1108 struct nvme_command c;
81c1cd98 1109 int flags = NVME_QUEUE_PHYS_CONTIG;
b60503ba 1110
9abd68ef
JA		 1111 /*
1112 * Some drives have a bug that auto-enables WRRU if MEDIUM isn't
1113 * set. Since URGENT priority is zeroes, it makes all queues
1114 * URGENT.
1115 */
1116 if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ)
1117 flags |= NVME_SQ_PRIO_MEDIUM;
1118
d29ec824 1119 /*
16772ae6 1120 * Note: we (ab)use the fact that the prp fields survive if no data
d29ec824
CH		 1121 * is attached to the request.
1122 */
b60503ba
MW		 1123 memset(&c, 0, sizeof(c));
1124 c.create_sq.opcode = nvme_admin_create_sq;
1125 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1126 c.create_sq.sqid = cpu_to_le16(qid);
1127 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1128 c.create_sq.sq_flags = cpu_to_le16(flags);
1129 c.create_sq.cqid = cpu_to_le16(qid);
1130
1c63dc66 1131 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1132}
1133
1134static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1135{
1136 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1137}
1138
1139static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1140{
1141 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1142}
1143
2a842aca 1144static void abort_endio(struct request *req, blk_status_t error)
bc5fc7e4 1145{
f4800d6d
CH		 1146 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1147 struct nvme_queue *nvmeq = iod->nvmeq;
e44ac588 1148
27fa9bc5
CH		 1149 dev_warn(nvmeq->dev->ctrl.device,
1150 "Abort status: 0x%x", nvme_req(req)->status);
e7a2a87d 1151 atomic_inc(&nvmeq->dev->ctrl.abort_limit);
e7a2a87d 1152 blk_mq_free_request(req);
bc5fc7e4
MW		 1153}
1154
b2a0eb1a
KB		 1155static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1156{
1157
1158 /* If true, indicates loss of adapter communication, possibly by a
1159 * NVMe Subsystem reset.
1160 */
1161 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1162
ad70062c
JW		 1163 /* If there is a reset/reinit ongoing, we shouldn't reset again. */
1164 switch (dev->ctrl.state) {
1165 case NVME_CTRL_RESETTING:
ad6a0a52 1166 case NVME_CTRL_CONNECTING:
b2a0eb1a 1167 return false;
ad70062c
JW		 1168 default:
1169 break;
1170 }
b2a0eb1a
KB		 1171
1172 /* We shouldn't reset unless the controller is on fatal error state
1173 * _or_ if we lost the communication with it.
1174 */
1175 if (!(csts & NVME_CSTS_CFS) && !nssro)
1176 return false;
1177
b2a0eb1a
KB		 1178 return true;
1179}
1180
1181static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1182{
1183 /* Read a config register to help see what died. */
1184 u16 pci_status;
1185 int result;
1186
1187 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1188 &pci_status);
1189 if (result == PCIBIOS_SUCCESSFUL)
1190 dev_warn(dev->ctrl.device,
1191 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1192 csts, pci_status);
1193 else
1194 dev_warn(dev->ctrl.device,
1195 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1196 csts, result);
1197}
1198
31c7c7d2 1199static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
c30341dc 1200{
f4800d6d
CH		 1201 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1202 struct nvme_queue *nvmeq = iod->nvmeq;
c30341dc 1203 struct nvme_dev *dev = nvmeq->dev;
a4aea562 1204 struct request *abort_req;
a4aea562 1205 struct nvme_command cmd;
b2a0eb1a
KB		 1206 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1207
651438bb
WX		 1208 /* If PCI error recovery process is happening, we cannot reset or
1209 * the recovery mechanism will surely fail.
1210 */
1211 mb();
1212 if (pci_channel_offline(to_pci_dev(dev->dev)))
1213 return BLK_EH_RESET_TIMER;
1214
b2a0eb1a
KB		 1215 /*
1216 * Reset immediately if the controller is failed
1217 */
1218 if (nvme_should_reset(dev, csts)) {
1219 nvme_warn_reset(dev, csts);
1220 nvme_dev_disable(dev, false);
d86c4d8e 1221 nvme_reset_ctrl(&dev->ctrl);
db8c48e4 1222 return BLK_EH_DONE;
b2a0eb1a 1223 }
c30341dc 1224
7776db1c
KB		 1225 /*
1226 * Did we miss an interrupt?
1227 */
fa059b85
KB		 1228 if (test_bit(NVMEQ_POLLED, &nvmeq->flags))
1229 nvme_poll(req->mq_hctx);
1230 else
1231 nvme_poll_irqdisable(nvmeq);
1232
bf392a5d 1233 if (blk_mq_request_completed(req)) {
7776db1c
KB		 1234 dev_warn(dev->ctrl.device,
1235 "I/O %d QID %d timeout, completion polled\n",
1236 req->tag, nvmeq->qid);
db8c48e4 1237 return BLK_EH_DONE;
7776db1c
KB		 1238 }
1239
31c7c7d2 1240 /*
fd634f41
CH		 1241 * Shutdown immediately if controller times out while starting. The
1242 * reset work will see the pci device disabled when it gets the forced
1243 * cancellation error. All outstanding requests are completed on
db8c48e4 1244 * shutdown, so we return BLK_EH_DONE.
fd634f41 1245 */
4244140d
KB		 1246 switch (dev->ctrl.state) {
1247 case NVME_CTRL_CONNECTING:
2036f726
KB		 1248 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
1249 /* fall through */
1250 case NVME_CTRL_DELETING:
b9cac43c 1251 dev_warn_ratelimited(dev->ctrl.device,
fd634f41
CH		 1252 "I/O %d QID %d timeout, disable controller\n",
1253 req->tag, nvmeq->qid);
2036f726 1254 nvme_dev_disable(dev, true);
27fa9bc5 1255 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
db8c48e4 1256 return BLK_EH_DONE;
39a9dd81
KB		 1257 case NVME_CTRL_RESETTING:
1258 return BLK_EH_RESET_TIMER;
4244140d
KB		 1259 default:
1260 break;
c30341dc
KB		 1261 }
1262
fd634f41
CH		 1263 /*
1264 * Shutdown the controller immediately and schedule a reset if the
1265 * command was already aborted once before and still hasn't been
1266 * returned to the driver, or if this is the admin queue.
31c7c7d2 1267 */
f4800d6d 1268 if (!nvmeq->qid || iod->aborted) {
1b3c47c1 1269 dev_warn(dev->ctrl.device,
e1569a16
KB		 1270 "I/O %d QID %d timeout, reset controller\n",
1271 req->tag, nvmeq->qid);
a5cdb68c 1272 nvme_dev_disable(dev, false);
d86c4d8e 1273 nvme_reset_ctrl(&dev->ctrl);
c30341dc 1274
27fa9bc5 1275 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
db8c48e4 1276 return BLK_EH_DONE;
c30341dc 1277 }
c30341dc 1278
e7a2a87d 1279 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
6bf25d16 1280 atomic_inc(&dev->ctrl.abort_limit);
31c7c7d2 1281 return BLK_EH_RESET_TIMER;
6bf25d16 1282 }
7bf7d778 1283 iod->aborted = 1;
a4aea562 1284
c30341dc
KB		 1285 memset(&cmd, 0, sizeof(cmd));
1286 cmd.abort.opcode = nvme_admin_abort_cmd;
a4aea562 1287 cmd.abort.cid = req->tag;
c30341dc 1288 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
c30341dc 1289
1b3c47c1
SG		 1290 dev_warn(nvmeq->dev->ctrl.device,
1291 "I/O %d QID %d timeout, aborting\n",
1292 req->tag, nvmeq->qid);
e7a2a87d
CH		 1293
1294 abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
eb71f435 1295 BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
e7a2a87d
CH		 1296 if (IS_ERR(abort_req)) {
1297 atomic_inc(&dev->ctrl.abort_limit);
1298 return BLK_EH_RESET_TIMER;
1299 }
1300
1301 abort_req->timeout = ADMIN_TIMEOUT;
1302 abort_req->end_io_data = NULL;
1303 blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio);
c30341dc 1304
31c7c7d2
CH		 1305 /*
1306 * The aborted req will be completed on receiving the abort req.
1307 * We enable the timer again. If hit twice, it'll cause a device reset,
1308 * as the device then is in a faulty state.
1309 */
1310 return BLK_EH_RESET_TIMER;
c30341dc
KB		 1311}
1312
a4aea562
MB		 1313static void nvme_free_queue(struct nvme_queue *nvmeq)
1314{
8a1d09a6 1315 dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq),
9e866774 1316 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
63223078
CH		 1317 if (!nvmeq->sq_cmds)
1318 return;
0f238ff5 1319
63223078 1320 if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) {
88a041f4 1321 pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev),
8a1d09a6 1322 nvmeq->sq_cmds, SQ_SIZE(nvmeq));
63223078 1323 } else {
8a1d09a6 1324 dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq),
63223078 1325 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
0f238ff5 1326 }
9e866774
MW		 1327}
1328
a1a5ef99 1329static void nvme_free_queues(struct nvme_dev *dev, int lowest)
22404274
KB		 1330{
1331 int i;
1332
d858e5f0 1333 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
d858e5f0 1334 dev->ctrl.queue_count--;
147b27e4 1335 nvme_free_queue(&dev->queues[i]);
121c7ad4 1336 }
22404274
KB		 1337}
1338
4d115420
KB		 1339/**
1340 * nvme_suspend_queue - put queue into suspended state
40581d1a 1341 * @nvmeq: queue to suspend
4d115420
KB		 1342 */
1343static int nvme_suspend_queue(struct nvme_queue *nvmeq)
b60503ba 1344{
4e224106 1345 if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags))
2b25d981 1346 return 1;
a09115b2 1347
4e224106 1348 /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */
d1f06f4a 1349 mb();
a09115b2 1350
4e224106 1351 nvmeq->dev->online_queues--;
1c63dc66 1352 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
c81545f9 1353 blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q);
7c349dde
KB		 1354 if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags))
1355 pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq);
4d115420
KB		 1356 return 0;
1357}
b60503ba 1358
8fae268b
KB		 1359static void nvme_suspend_io_queues(struct nvme_dev *dev)
1360{
1361 int i;
1362
1363 for (i = dev->ctrl.queue_count - 1; i > 0; i--)
1364 nvme_suspend_queue(&dev->queues[i]);
1365}
1366
a5cdb68c 1367static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
4d115420 1368{
147b27e4 1369 struct nvme_queue *nvmeq = &dev->queues[0];
4d115420 1370
a5cdb68c
KB		 1371 if (shutdown)
1372 nvme_shutdown_ctrl(&dev->ctrl);
1373 else
b5b05048 1374 nvme_disable_ctrl(&dev->ctrl);
07836e65 1375
bf392a5d 1376 nvme_poll_irqdisable(nvmeq);
b60503ba
MW		 1377}
1378
fa46c6fb
KB		 1379/*
1380 * Called only on a device that has been disabled and after all other threads
1381 * that can check this device's completion queues have synced. This is the
1382 * last chance for the driver to see a natural completion before
1383 * nvme_cancel_request() terminates all incomplete requests.
1384 */
1385static void nvme_reap_pending_cqes(struct nvme_dev *dev)
1386{
fa46c6fb
KB		 1387 int i;
1388
324b494c
KB		 1389 for (i = dev->ctrl.queue_count - 1; i > 0; i--)
1390 nvme_process_cq(&dev->queues[i]);
fa46c6fb
KB		 1391}
1392
8ffaadf7
JD		 1393static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1394 int entry_size)
1395{
1396 int q_depth = dev->q_depth;
5fd4ce1b
CH		 1397 unsigned q_size_aligned = roundup(q_depth * entry_size,
1398 dev->ctrl.page_size);
8ffaadf7
JD		 1399
1400 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
c45f5c99 1401 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
5fd4ce1b 1402 mem_per_q = round_down(mem_per_q, dev->ctrl.page_size);
c45f5c99 1403 q_depth = div_u64(mem_per_q, entry_size);
8ffaadf7
JD		 1404
1405 /*
1406 * Ensure the reduced q_depth is above some threshold where it
1407 * would be better to map queues in system memory with the
1408 * original depth
1409 */
1410 if (q_depth < 64)
1411 return -ENOMEM;
1412 }
1413
1414 return q_depth;
1415}
1416
1417static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
8a1d09a6 1418 int qid)
8ffaadf7 1419{
0f238ff5
LG		 1420 struct pci_dev *pdev = to_pci_dev(dev->dev);
1421
1422 if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
8a1d09a6 1423 nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq));
bfac8e9f
AM		 1424 if (nvmeq->sq_cmds) {
1425 nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev,
1426 nvmeq->sq_cmds);
1427 if (nvmeq->sq_dma_addr) {
1428 set_bit(NVMEQ_SQ_CMB, &nvmeq->flags);
1429 return 0;
1430 }
1431
8a1d09a6 1432 pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq));
63223078 1433 }
0f238ff5 1434 }
8ffaadf7 1435
8a1d09a6 1436 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq),
63223078 1437 &nvmeq->sq_dma_addr, GFP_KERNEL);
815c6704
KB		 1438 if (!nvmeq->sq_cmds)
1439 return -ENOMEM;
8ffaadf7
JD		 1440 return 0;
1441}
1442
a6ff7262 1443static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
b60503ba 1444{
147b27e4 1445 struct nvme_queue *nvmeq = &dev->queues[qid];
b60503ba 1446
62314e40
KB		 1447 if (dev->ctrl.queue_count > qid)
1448 return 0;
b60503ba 1449
c1e0cc7e 1450 nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES;
8a1d09a6
BH		 1451 nvmeq->q_depth = depth;
1452 nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq),
750afb08 1453 &nvmeq->cq_dma_addr, GFP_KERNEL);
b60503ba
MW		 1454 if (!nvmeq->cqes)
1455 goto free_nvmeq;
b60503ba 1456
8a1d09a6 1457 if (nvme_alloc_sq_cmds(dev, nvmeq, qid))
b60503ba
MW		 1458 goto free_cqdma;
1459
091b6092 1460 nvmeq->dev = dev;
1ab0cd69 1461 spin_lock_init(&nvmeq->sq_lock);
3a7afd8e 1462 spin_lock_init(&nvmeq->cq_poll_lock);
b60503ba 1463 nvmeq->cq_head = 0;
82123460 1464 nvmeq->cq_phase = 1;
b80d5ccc 1465 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
c30341dc 1466 nvmeq->qid = qid;
d858e5f0 1467 dev->ctrl.queue_count++;
36a7e993 1468
147b27e4 1469 return 0;
b60503ba
MW		 1470
1471 free_cqdma:
8a1d09a6
BH		 1472 dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes,
1473 nvmeq->cq_dma_addr);
b60503ba 1474 free_nvmeq:
147b27e4 1475 return -ENOMEM;
b60503ba
MW		 1476}
1477
dca51e78 1478static int queue_request_irq(struct nvme_queue *nvmeq)
3001082c 1479{
0ff199cb
CH		 1480 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1481 int nr = nvmeq->dev->ctrl.instance;
1482
1483 if (use_threaded_interrupts) {
1484 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1485 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1486 } else {
1487 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1488 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1489 }
3001082c
MW		 1490}
1491
22404274 1492static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
b60503ba 1493{
22404274 1494 struct nvme_dev *dev = nvmeq->dev;
b60503ba 1495
22404274 1496 nvmeq->sq_tail = 0;
04f3eafd 1497 nvmeq->last_sq_tail = 0;
22404274
KB		 1498 nvmeq->cq_head = 0;
1499 nvmeq->cq_phase = 1;
b80d5ccc 1500 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
8a1d09a6 1501 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq));
f9f38e33 1502 nvme_dbbuf_init(dev, nvmeq, qid);
42f61420 1503 dev->online_queues++;
3a7afd8e 1504 wmb(); /* ensure the first interrupt sees the initialization */
22404274
KB		 1505}
1506
4b04cc6a 1507static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled)
22404274
KB		 1508{
1509 struct nvme_dev *dev = nvmeq->dev;
1510 int result;
7c349dde 1511 u16 vector = 0;
3f85d50b 1512
d1ed6aa1
CH		 1513 clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
1514
22b55601
KB		 1515 /*
1516 * A queue's vector matches the queue identifier unless the controller
1517 * has only one vector available.
1518 */
4b04cc6a
JA		 1519 if (!polled)
1520 vector = dev->num_vecs == 1 ? 0 : qid;
1521 else
7c349dde 1522 set_bit(NVMEQ_POLLED, &nvmeq->flags);
4b04cc6a 1523
a8e3e0bb 1524 result = adapter_alloc_cq(dev, qid, nvmeq, vector);
ded45505
KB		 1525 if (result)
1526 return result;
b60503ba
MW		 1527
1528 result = adapter_alloc_sq(dev, qid, nvmeq);
1529 if (result < 0)
ded45505 1530 return result;
c80b36cd 1531 if (result)
b60503ba
MW		 1532 goto release_cq;
1533
a8e3e0bb 1534 nvmeq->cq_vector = vector;
161b8be2 1535 nvme_init_queue(nvmeq, qid);
4b04cc6a 1536
7c349dde 1537 if (!polled) {
4b04cc6a
JA		 1538 result = queue_request_irq(nvmeq);
1539 if (result < 0)
1540 goto release_sq;
1541 }
b60503ba 1542
4e224106 1543 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
22404274 1544 return result;
b60503ba 1545
a8e3e0bb 1546release_sq:
f25a2dfc 1547 dev->online_queues--;
b60503ba 1548 adapter_delete_sq(dev, qid);
a8e3e0bb 1549release_cq:
b60503ba 1550 adapter_delete_cq(dev, qid);
22404274 1551 return result;
b60503ba
MW		 1552}
1553
f363b089 1554static const struct blk_mq_ops nvme_mq_admin_ops = {
d29ec824 1555 .queue_rq = nvme_queue_rq,
77f02a7a 1556 .complete = nvme_pci_complete_rq,
a4aea562 1557 .init_hctx = nvme_admin_init_hctx,
0350815a 1558 .init_request = nvme_init_request,
a4aea562
MB		 1559 .timeout = nvme_timeout,
1560};
1561
f363b089 1562static const struct blk_mq_ops nvme_mq_ops = {
376f7ef8
CH		 1563 .queue_rq = nvme_queue_rq,
1564 .complete = nvme_pci_complete_rq,
1565 .commit_rqs = nvme_commit_rqs,
1566 .init_hctx = nvme_init_hctx,
1567 .init_request = nvme_init_request,
1568 .map_queues = nvme_pci_map_queues,
1569 .timeout = nvme_timeout,
1570 .poll = nvme_poll,
dabcefab
JA		 1571};
1572
ea191d2f
KB		 1573static void nvme_dev_remove_admin(struct nvme_dev *dev)
1574{
1c63dc66 1575 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
69d9a99c
KB		 1576 /*
1577 * If the controller was reset during removal, it's possible
1578 * user requests may be waiting on a stopped queue. Start the
1579 * queue to flush these to completion.
1580 */
c81545f9 1581 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1c63dc66 1582 blk_cleanup_queue(dev->ctrl.admin_q);
ea191d2f
KB		 1583 blk_mq_free_tag_set(&dev->admin_tagset);
1584 }
1585}
1586
a4aea562
MB		 1587static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1588{
1c63dc66 1589 if (!dev->ctrl.admin_q) {
a4aea562
MB		 1590 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1591 dev->admin_tagset.nr_hw_queues = 1;
e3e9d50c 1592
38dabe21 1593 dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH;
a4aea562 1594 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
e75ec752 1595 dev->admin_tagset.numa_node = dev_to_node(dev->dev);
d43f1ccf 1596 dev->admin_tagset.cmd_size = sizeof(struct nvme_iod);
d3484991 1597 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED;
a4aea562
MB		 1598 dev->admin_tagset.driver_data = dev;
1599
1600 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1601 return -ENOMEM;
34b6c231 1602 dev->ctrl.admin_tagset = &dev->admin_tagset;
a4aea562 1603
1c63dc66
CH		 1604 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1605 if (IS_ERR(dev->ctrl.admin_q)) {
a4aea562
MB		 1606 blk_mq_free_tag_set(&dev->admin_tagset);
1607 return -ENOMEM;
1608 }
1c63dc66 1609 if (!blk_get_queue(dev->ctrl.admin_q)) {
ea191d2f 1610 nvme_dev_remove_admin(dev);
1c63dc66 1611 dev->ctrl.admin_q = NULL;
ea191d2f
KB		 1612 return -ENODEV;
1613 }
0fb59cbc 1614 } else
c81545f9 1615 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
a4aea562
MB		 1616
1617 return 0;
1618}
1619
97f6ef64
XY		 1620static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1621{
1622 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1623}
1624
1625static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1626{
1627 struct pci_dev *pdev = to_pci_dev(dev->dev);
1628
1629 if (size <= dev->bar_mapped_size)
1630 return 0;
1631 if (size > pci_resource_len(pdev, 0))
1632 return -ENOMEM;
1633 if (dev->bar)
1634 iounmap(dev->bar);
1635 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1636 if (!dev->bar) {
1637 dev->bar_mapped_size = 0;
1638 return -ENOMEM;
1639 }
1640 dev->bar_mapped_size = size;
1641 dev->dbs = dev->bar + NVME_REG_DBS;
1642
1643 return 0;
1644}
1645
01ad0990 1646static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
b60503ba 1647{
ba47e386 1648 int result;
b60503ba
MW		 1649 u32 aqa;
1650 struct nvme_queue *nvmeq;
1651
97f6ef64
XY		 1652 result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1653 if (result < 0)
1654 return result;
1655
8ef2074d 1656 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
20d0dfe6 1657 NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
dfbac8c7 1658
7a67cbea
CH		 1659 if (dev->subsystem &&
1660 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1661 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
dfbac8c7 1662
b5b05048 1663 result = nvme_disable_ctrl(&dev->ctrl);
ba47e386
MW		 1664 if (result < 0)
1665 return result;
b60503ba 1666
a6ff7262 1667 result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
147b27e4
SG		 1668 if (result)
1669 return result;
b60503ba 1670
147b27e4 1671 nvmeq = &dev->queues[0];
b60503ba
MW		 1672 aqa = nvmeq->q_depth - 1;
1673 aqa |= aqa << 16;
1674
7a67cbea
CH		 1675 writel(aqa, dev->bar + NVME_REG_AQA);
1676 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1677 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
b60503ba 1678
c0f2f45b 1679 result = nvme_enable_ctrl(&dev->ctrl);
025c557a 1680 if (result)
d4875622 1681 return result;
a4aea562 1682
2b25d981 1683 nvmeq->cq_vector = 0;
161b8be2 1684 nvme_init_queue(nvmeq, 0);
dca51e78 1685 result = queue_request_irq(nvmeq);
758dd7fd 1686 if (result) {
7c349dde 1687 dev->online_queues--;
d4875622 1688 return result;
758dd7fd 1689 }
025c557a 1690
4e224106 1691 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
b60503ba
MW		 1692 return result;
1693}
1694
749941f2 1695static int nvme_create_io_queues(struct nvme_dev *dev)
42f61420 1696{
4b04cc6a 1697 unsigned i, max, rw_queues;
749941f2 1698 int ret = 0;
42f61420 1699
d858e5f0 1700 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
a6ff7262 1701 if (nvme_alloc_queue(dev, i, dev->q_depth)) {
749941f2 1702 ret = -ENOMEM;
42f61420 1703 break;
749941f2
CH		 1704 }
1705 }
42f61420 1706
d858e5f0 1707 max = min(dev->max_qid, dev->ctrl.queue_count - 1);
e20ba6e1
CH		 1708 if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) {
1709 rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] +
1710 dev->io_queues[HCTX_TYPE_READ];
4b04cc6a
JA		 1711 } else {
1712 rw_queues = max;
1713 }
1714
949928c1 1715 for (i = dev->online_queues; i <= max; i++) {
4b04cc6a
JA		 1716 bool polled = i > rw_queues;
1717
1718 ret = nvme_create_queue(&dev->queues[i], i, polled);
d4875622 1719 if (ret)
42f61420 1720 break;
27e8166c 1721 }
749941f2
CH		 1722
1723 /*
1724 * Ignore failing Create SQ/CQ commands, we can continue with less
8adb8c14
MI		 1725 * than the desired amount of queues, and even a controller without
1726 * I/O queues can still be used to issue admin commands. This might
749941f2
CH		 1727 * be useful to upgrade a buggy firmware for example.
1728 */
1729 return ret >= 0 ? 0 : ret;
b60503ba
MW		 1730}
1731
202021c1
SB		 1732static ssize_t nvme_cmb_show(struct device *dev,
1733 struct device_attribute *attr,
1734 char *buf)
1735{
1736 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
1737
c965809c 1738 return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n",
202021c1
SB		 1739 ndev->cmbloc, ndev->cmbsz);
1740}
1741static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL);
1742
88de4598 1743static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
8ffaadf7 1744{
88de4598
CH		 1745 u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
1746
1747 return 1ULL << (12 + 4 * szu);
1748}
1749
1750static u32 nvme_cmb_size(struct nvme_dev *dev)
1751{
1752 return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
1753}
1754
f65efd6d 1755static void nvme_map_cmb(struct nvme_dev *dev)
8ffaadf7 1756{
88de4598 1757 u64 size, offset;
8ffaadf7
JD		 1758 resource_size_t bar_size;
1759 struct pci_dev *pdev = to_pci_dev(dev->dev);
8969f1f8 1760 int bar;
8ffaadf7 1761
9fe5c59f
KB		 1762 if (dev->cmb_size)
1763 return;
1764
7a67cbea 1765 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
f65efd6d
CH		 1766 if (!dev->cmbsz)
1767 return;
202021c1 1768 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
8ffaadf7 1769
88de4598
CH		 1770 size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
1771 offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
8969f1f8
CH		 1772 bar = NVME_CMB_BIR(dev->cmbloc);
1773 bar_size = pci_resource_len(pdev, bar);
8ffaadf7
JD		 1774
1775 if (offset > bar_size)
f65efd6d 1776 return;
8ffaadf7
JD		 1777
1778 /*
1779 * Controllers may support a CMB size larger than their BAR,
1780 * for example, due to being behind a bridge. Reduce the CMB to
1781 * the reported size of the BAR
1782 */
1783 if (size > bar_size - offset)
1784 size = bar_size - offset;
1785
0f238ff5
LG		 1786 if (pci_p2pdma_add_resource(pdev, bar, size, offset)) {
1787 dev_warn(dev->ctrl.device,
1788 "failed to register the CMB\n");
f65efd6d 1789 return;
0f238ff5
LG		 1790 }
1791
8ffaadf7 1792 dev->cmb_size = size;
0f238ff5
LG		 1793 dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS);
1794
1795 if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) ==
1796 (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS))
1797 pci_p2pmem_publish(pdev, true);
f65efd6d
CH		 1798
1799 if (sysfs_add_file_to_group(&dev->ctrl.device->kobj,
1800 &dev_attr_cmb.attr, NULL))
1801 dev_warn(dev->ctrl.device,
1802 "failed to add sysfs attribute for CMB\n");
8ffaadf7
JD		 1803}
1804
1805static inline void nvme_release_cmb(struct nvme_dev *dev)
1806{
0f238ff5 1807 if (dev->cmb_size) {
1c78f773
MG		 1808 sysfs_remove_file_from_group(&dev->ctrl.device->kobj,
1809 &dev_attr_cmb.attr, NULL);
0f238ff5 1810 dev->cmb_size = 0;
8ffaadf7
JD		 1811 }
1812}
1813
87ad72a5
CH		 1814static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1815{
4033f35d 1816 u64 dma_addr = dev->host_mem_descs_dma;
87ad72a5 1817 struct nvme_command c;
87ad72a5
CH		 1818 int ret;
1819
87ad72a5
CH		 1820 memset(&c, 0, sizeof(c));
1821 c.features.opcode = nvme_admin_set_features;
1822 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1823 c.features.dword11 = cpu_to_le32(bits);
1824 c.features.dword12 = cpu_to_le32(dev->host_mem_size >>
1825 ilog2(dev->ctrl.page_size));
1826 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr));
1827 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr));
1828 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs);
1829
1830 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1831 if (ret) {
1832 dev_warn(dev->ctrl.device,
1833 "failed to set host mem (err %d, flags %#x).\n",
1834 ret, bits);
1835 }
87ad72a5
CH		 1836 return ret;
1837}
1838
1839static void nvme_free_host_mem(struct nvme_dev *dev)
1840{
1841 int i;
1842
1843 for (i = 0; i < dev->nr_host_mem_descs; i++) {
1844 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
1845 size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size;
1846
cc667f6d
LD		 1847 dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i],
1848 le64_to_cpu(desc->addr),
1849 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
87ad72a5
CH		 1850 }
1851
1852 kfree(dev->host_mem_desc_bufs);
1853 dev->host_mem_desc_bufs = NULL;
4033f35d
CH		 1854 dma_free_coherent(dev->dev,
1855 dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
1856 dev->host_mem_descs, dev->host_mem_descs_dma);
87ad72a5 1857 dev->host_mem_descs = NULL;
7e5dd57e 1858 dev->nr_host_mem_descs = 0;
87ad72a5
CH		 1859}
1860
92dc6895
CH		 1861static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
1862 u32 chunk_size)
9d713c2b 1863{
87ad72a5 1864 struct nvme_host_mem_buf_desc *descs;
92dc6895 1865 u32 max_entries, len;
4033f35d 1866 dma_addr_t descs_dma;
2ee0e4ed 1867 int i = 0;
87ad72a5 1868 void **bufs;
6fbcde66 1869 u64 size, tmp;
87ad72a5 1870
87ad72a5
CH		 1871 tmp = (preferred + chunk_size - 1);
1872 do_div(tmp, chunk_size);
1873 max_entries = tmp;
044a9df1
CH		 1874
1875 if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
1876 max_entries = dev->ctrl.hmmaxd;
1877
750afb08
LC		 1878 descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs),
1879 &descs_dma, GFP_KERNEL);
87ad72a5
CH		 1880 if (!descs)
1881 goto out;
1882
1883 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
1884 if (!bufs)
1885 goto out_free_descs;
1886
244a8fe4 1887 for (size = 0; size < preferred && i < max_entries; size += len) {
87ad72a5
CH		 1888 dma_addr_t dma_addr;
1889
50cdb7c6 1890 len = min_t(u64, chunk_size, preferred - size);
87ad72a5
CH		 1891 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
1892 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1893 if (!bufs[i])
1894 break;
1895
1896 descs[i].addr = cpu_to_le64(dma_addr);
1897 descs[i].size = cpu_to_le32(len / dev->ctrl.page_size);
1898 i++;
1899 }
1900
92dc6895 1901 if (!size)
87ad72a5 1902 goto out_free_bufs;
87ad72a5 1903
87ad72a5
CH		 1904 dev->nr_host_mem_descs = i;
1905 dev->host_mem_size = size;
1906 dev->host_mem_descs = descs;
4033f35d 1907 dev->host_mem_descs_dma = descs_dma;
87ad72a5
CH		 1908 dev->host_mem_desc_bufs = bufs;
1909 return 0;
1910
1911out_free_bufs:
1912 while (--i >= 0) {
1913 size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size;
1914
cc667f6d
LD		 1915 dma_free_attrs(dev->dev, size, bufs[i],
1916 le64_to_cpu(descs[i].addr),
1917 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
87ad72a5
CH		 1918 }
1919
1920 kfree(bufs);
1921out_free_descs:
4033f35d
CH		 1922 dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
1923 descs_dma);
87ad72a5 1924out:
87ad72a5
CH		 1925 dev->host_mem_descs = NULL;
1926 return -ENOMEM;
1927}
1928
92dc6895
CH		 1929static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
1930{
1931 u32 chunk_size;
1932
1933 /* start big and work our way down */
30f92d62 1934 for (chunk_size = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
044a9df1 1935 chunk_size >= max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
92dc6895
CH		 1936 chunk_size /= 2) {
1937 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
1938 if (!min || dev->host_mem_size >= min)
1939 return 0;
1940 nvme_free_host_mem(dev);
1941 }
1942 }
1943
1944 return -ENOMEM;
1945}
1946
9620cfba 1947static int nvme_setup_host_mem(struct nvme_dev *dev)
87ad72a5
CH		 1948{
1949 u64 max = (u64)max_host_mem_size_mb * SZ_1M;
1950 u64 preferred = (u64)dev->ctrl.hmpre * 4096;
1951 u64 min = (u64)dev->ctrl.hmmin * 4096;
1952 u32 enable_bits = NVME_HOST_MEM_ENABLE;
6fbcde66 1953 int ret;
87ad72a5
CH		 1954
1955 preferred = min(preferred, max);
1956 if (min > max) {
1957 dev_warn(dev->ctrl.device,
1958 "min host memory (%lld MiB) above limit (%d MiB).\n",
1959 min >> ilog2(SZ_1M), max_host_mem_size_mb);
1960 nvme_free_host_mem(dev);
9620cfba 1961 return 0;
87ad72a5
CH		 1962 }
1963
1964 /*
1965 * If we already have a buffer allocated check if we can reuse it.
1966 */
1967 if (dev->host_mem_descs) {
1968 if (dev->host_mem_size >= min)
1969 enable_bits |= NVME_HOST_MEM_RETURN;
1970 else
1971 nvme_free_host_mem(dev);
1972 }
1973
1974 if (!dev->host_mem_descs) {
92dc6895
CH		 1975 if (nvme_alloc_host_mem(dev, min, preferred)) {
1976 dev_warn(dev->ctrl.device,
1977 "failed to allocate host memory buffer.\n");
9620cfba 1978 return 0; /* controller must work without HMB */
92dc6895
CH		 1979 }
1980
1981 dev_info(dev->ctrl.device,
1982 "allocated %lld MiB host memory buffer.\n",
1983 dev->host_mem_size >> ilog2(SZ_1M));
87ad72a5
CH		 1984 }
1985
9620cfba
CH		 1986 ret = nvme_set_host_mem(dev, enable_bits);
1987 if (ret)
87ad72a5 1988 nvme_free_host_mem(dev);
9620cfba 1989 return ret;
9d713c2b
KB		 1990}
1991
612b7286
ML		 1992/*
1993 * nirqs is the number of interrupts available for write and read
1994 * queues. The core already reserved an interrupt for the admin queue.
1995 */
1996static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs)
3b6592f7 1997{
612b7286
ML		 1998 struct nvme_dev *dev = affd->priv;
1999 unsigned int nr_read_queues;
3b6592f7
JA		 2000
2001 /*
612b7286
ML		 2002 * If there is no interupt available for queues, ensure that
2003 * the default queue is set to 1. The affinity set size is
2004 * also set to one, but the irq core ignores it for this case.
2005 *
2006 * If only one interrupt is available or 'write_queue' == 0, combine
2007 * write and read queues.
2008 *
2009 * If 'write_queues' > 0, ensure it leaves room for at least one read
2010 * queue.
3b6592f7 2011 */
612b7286
ML		 2012 if (!nrirqs) {
2013 nrirqs = 1;
2014 nr_read_queues = 0;
2015 } else if (nrirqs == 1 || !write_queues) {
2016 nr_read_queues = 0;
2017 } else if (write_queues >= nrirqs) {
2018 nr_read_queues = 1;
3b6592f7 2019 } else {
612b7286 2020 nr_read_queues = nrirqs - write_queues;
3b6592f7 2021 }
612b7286
ML		 2022
2023 dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2024 affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2025 dev->io_queues[HCTX_TYPE_READ] = nr_read_queues;
2026 affd->set_size[HCTX_TYPE_READ] = nr_read_queues;
2027 affd->nr_sets = nr_read_queues ? 2 : 1;
3b6592f7
JA		 2028}
2029
6451fe73 2030static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues)
3b6592f7
JA		 2031{
2032 struct pci_dev *pdev = to_pci_dev(dev->dev);
3b6592f7 2033 struct irq_affinity affd = {
9cfef55b 2034 .pre_vectors = 1,
612b7286
ML		 2035 .calc_sets = nvme_calc_irq_sets,
2036 .priv = dev,
3b6592f7 2037 };
6451fe73
JA		 2038 unsigned int irq_queues, this_p_queues;
2039
2040 /*
2041 * Poll queues don't need interrupts, but we need at least one IO
2042 * queue left over for non-polled IO.
2043 */
2044 this_p_queues = poll_queues;
2045 if (this_p_queues >= nr_io_queues) {
2046 this_p_queues = nr_io_queues - 1;
2047 irq_queues = 1;
2048 } else {
7e4c6b9a 2049 irq_queues = nr_io_queues - this_p_queues + 1;
6451fe73
JA		 2050 }
2051 dev->io_queues[HCTX_TYPE_POLL] = this_p_queues;
3b6592f7 2052
612b7286
ML		 2053 /* Initialize for the single interrupt case */
2054 dev->io_queues[HCTX_TYPE_DEFAULT] = 1;
2055 dev->io_queues[HCTX_TYPE_READ] = 0;
3b6592f7 2056
66341331
BH		 2057 /*
2058 * Some Apple controllers require all queues to use the
2059 * first vector.
2060 */
2061 if (dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR)
2062 irq_queues = 1;
2063
612b7286
ML		 2064 return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues,
2065 PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd);
3b6592f7
JA		 2066}
2067
8fae268b
KB		 2068static void nvme_disable_io_queues(struct nvme_dev *dev)
2069{
2070 if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq))
2071 __nvme_disable_io_queues(dev, nvme_admin_delete_cq);
2072}
2073
8d85fce7 2074static int nvme_setup_io_queues(struct nvme_dev *dev)
b60503ba 2075{
147b27e4 2076 struct nvme_queue *adminq = &dev->queues[0];
e75ec752 2077 struct pci_dev *pdev = to_pci_dev(dev->dev);
97f6ef64
XY		 2078 int result, nr_io_queues;
2079 unsigned long size;
b60503ba 2080
3b6592f7 2081 nr_io_queues = max_io_queues();
d38e9f04
BH		 2082
2083 /*
2084 * If tags are shared with admin queue (Apple bug), then
2085 * make sure we only use one IO queue.
2086 */
2087 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2088 nr_io_queues = 1;
2089
9a0be7ab
CH		 2090 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
2091 if (result < 0)
1b23484b 2092 return result;
9a0be7ab 2093
f5fa90dc 2094 if (nr_io_queues == 0)
a5229050 2095 return 0;
4e224106
CH		 2096
2097 clear_bit(NVMEQ_ENABLED, &adminq->flags);
b60503ba 2098
0f238ff5 2099 if (dev->cmb_use_sqes) {
8ffaadf7
JD		 2100 result = nvme_cmb_qdepth(dev, nr_io_queues,
2101 sizeof(struct nvme_command));
2102 if (result > 0)
2103 dev->q_depth = result;
2104 else
0f238ff5 2105 dev->cmb_use_sqes = false;
8ffaadf7
JD		 2106 }
2107
97f6ef64
XY		 2108 do {
2109 size = db_bar_size(dev, nr_io_queues);
2110 result = nvme_remap_bar(dev, size);
2111 if (!result)
2112 break;
2113 if (!--nr_io_queues)
2114 return -ENOMEM;
2115 } while (1);
2116 adminq->q_db = dev->dbs;
f1938f6e 2117
8fae268b 2118 retry:
9d713c2b 2119 /* Deregister the admin queue's interrupt */
0ff199cb 2120 pci_free_irq(pdev, 0, adminq);
9d713c2b 2121
e32efbfc
JA		 2122 /*
2123 * If we enable msix early due to not intx, disable it again before
2124 * setting up the full range we need.
2125 */
dca51e78 2126 pci_free_irq_vectors(pdev);
3b6592f7
JA		 2127
2128 result = nvme_setup_irqs(dev, nr_io_queues);
22b55601 2129 if (result <= 0)
dca51e78 2130 return -EIO;
3b6592f7 2131
22b55601 2132 dev->num_vecs = result;
4b04cc6a 2133 result = max(result - 1, 1);
e20ba6e1 2134 dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL];
fa08a396 2135
063a8096
MW		 2136 /*
2137 * Should investigate if there's a performance win from allocating
2138 * more queues than interrupt vectors; it might allow the submission
2139 * path to scale better, even if the receive path is limited by the
2140 * number of interrupts.
2141 */
dca51e78 2142 result = queue_request_irq(adminq);
7c349dde 2143 if (result)
d4875622 2144 return result;
4e224106 2145 set_bit(NVMEQ_ENABLED, &adminq->flags);
8fae268b
KB		 2146
2147 result = nvme_create_io_queues(dev);
2148 if (result || dev->online_queues < 2)
2149 return result;
2150
2151 if (dev->online_queues - 1 < dev->max_qid) {
2152 nr_io_queues = dev->online_queues - 1;
2153 nvme_disable_io_queues(dev);
2154 nvme_suspend_io_queues(dev);
2155 goto retry;
2156 }
2157 dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n",
2158 dev->io_queues[HCTX_TYPE_DEFAULT],
2159 dev->io_queues[HCTX_TYPE_READ],
2160 dev->io_queues[HCTX_TYPE_POLL]);
2161 return 0;
b60503ba
MW		 2162}
2163
2a842aca 2164static void nvme_del_queue_end(struct request *req, blk_status_t error)
a5768aa8 2165{
db3cbfff 2166 struct nvme_queue *nvmeq = req->end_io_data;
b5875222 2167
db3cbfff 2168 blk_mq_free_request(req);
d1ed6aa1 2169 complete(&nvmeq->delete_done);
a5768aa8
KB		 2170}
2171
2a842aca 2172static void nvme_del_cq_end(struct request *req, blk_status_t error)
a5768aa8 2173{
db3cbfff 2174 struct nvme_queue *nvmeq = req->end_io_data;
a5768aa8 2175
d1ed6aa1
CH		 2176 if (error)
2177 set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
db3cbfff
KB		 2178
2179 nvme_del_queue_end(req, error);
a5768aa8
KB		 2180}
2181
db3cbfff 2182static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
bda4e0fb 2183{
db3cbfff
KB		 2184 struct request_queue *q = nvmeq->dev->ctrl.admin_q;
2185 struct request *req;
2186 struct nvme_command cmd;
bda4e0fb 2187
db3cbfff
KB		 2188 memset(&cmd, 0, sizeof(cmd));
2189 cmd.delete_queue.opcode = opcode;
2190 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
bda4e0fb 2191
eb71f435 2192 req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
db3cbfff
KB		 2193 if (IS_ERR(req))
2194 return PTR_ERR(req);
bda4e0fb 2195
db3cbfff
KB		 2196 req->timeout = ADMIN_TIMEOUT;
2197 req->end_io_data = nvmeq;
2198
d1ed6aa1 2199 init_completion(&nvmeq->delete_done);
db3cbfff
KB		 2200 blk_execute_rq_nowait(q, NULL, req, false,
2201 opcode == nvme_admin_delete_cq ?
2202 nvme_del_cq_end : nvme_del_queue_end);
2203 return 0;
bda4e0fb
KB		 2204}
2205
8fae268b 2206static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode)
a5768aa8 2207{
5271edd4 2208 int nr_queues = dev->online_queues - 1, sent = 0;
db3cbfff 2209 unsigned long timeout;
a5768aa8 2210
db3cbfff 2211 retry:
5271edd4
CH		 2212 timeout = ADMIN_TIMEOUT;
2213 while (nr_queues > 0) {
2214 if (nvme_delete_queue(&dev->queues[nr_queues], opcode))
2215 break;
2216 nr_queues--;
2217 sent++;
db3cbfff 2218 }
d1ed6aa1
CH		 2219 while (sent) {
2220 struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent];
2221
2222 timeout = wait_for_completion_io_timeout(&nvmeq->delete_done,
5271edd4
CH		 2223 timeout);
2224 if (timeout == 0)
2225 return false;
d1ed6aa1 2226
d1ed6aa1 2227 sent--;
5271edd4
CH		 2228 if (nr_queues)
2229 goto retry;
2230 }
2231 return true;
a5768aa8
KB		 2232}
2233
5d02a5c1 2234static void nvme_dev_add(struct nvme_dev *dev)
b60503ba 2235{
2b1b7e78
JW		 2236 int ret;
2237
5bae7f73 2238 if (!dev->ctrl.tagset) {
376f7ef8 2239 dev->tagset.ops = &nvme_mq_ops;
ffe7704d 2240 dev->tagset.nr_hw_queues = dev->online_queues - 1;
8fe34be1 2241 dev->tagset.nr_maps = 2; /* default + read */
ed92ad37
CH		 2242 if (dev->io_queues[HCTX_TYPE_POLL])
2243 dev->tagset.nr_maps++;
ffe7704d
KB		 2244 dev->tagset.timeout = NVME_IO_TIMEOUT;
2245 dev->tagset.numa_node = dev_to_node(dev->dev);
2246 dev->tagset.queue_depth =
a4aea562 2247 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
d43f1ccf 2248 dev->tagset.cmd_size = sizeof(struct nvme_iod);
ffe7704d
KB		 2249 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2250 dev->tagset.driver_data = dev;
b60503ba 2251
d38e9f04
BH		 2252 /*
2253 * Some Apple controllers requires tags to be unique
2254 * across admin and IO queue, so reserve the first 32
2255 * tags of the IO queue.
2256 */
2257 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2258 dev->tagset.reserved_tags = NVME_AQ_DEPTH;
2259
2b1b7e78
JW		 2260 ret = blk_mq_alloc_tag_set(&dev->tagset);
2261 if (ret) {
2262 dev_warn(dev->ctrl.device,
2263 "IO queues tagset allocation failed %d\n", ret);
5d02a5c1 2264 return;
2b1b7e78 2265 }
5bae7f73 2266 dev->ctrl.tagset = &dev->tagset;
949928c1
KB		 2267 } else {
2268 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2269
2270 /* Free previously allocated queues that are no longer usable */
2271 nvme_free_queues(dev, dev->online_queues);
ffe7704d 2272 }
949928c1 2273
e8fd41bb 2274 nvme_dbbuf_set(dev);
b60503ba
MW		 2275}
2276
b00a726a 2277static int nvme_pci_enable(struct nvme_dev *dev)
0877cb0d 2278{
b00a726a 2279 int result = -ENOMEM;
e75ec752 2280 struct pci_dev *pdev = to_pci_dev(dev->dev);
0877cb0d
KB		 2281
2282 if (pci_enable_device_mem(pdev))
2283 return result;
2284
0877cb0d 2285 pci_set_master(pdev);
0877cb0d 2286
4fe06923 2287 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)))
052d0efa 2288 goto disable;
0877cb0d 2289
7a67cbea 2290 if (readl(dev->bar + NVME_REG_CSTS) == -1) {
0e53d180 2291 result = -ENODEV;
b00a726a 2292 goto disable;
0e53d180 2293 }
e32efbfc
JA		 2294
2295 /*
a5229050
KB		 2296 * Some devices and/or platforms don't advertise or work with INTx
2297 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2298 * adjust this later.
e32efbfc 2299 */
dca51e78
CH		 2300 result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
2301 if (result < 0)
2302 return result;
e32efbfc 2303
20d0dfe6 2304 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
7a67cbea 2305
20d0dfe6 2306 dev->q_depth = min_t(int, NVME_CAP_MQES(dev->ctrl.cap) + 1,
b27c1e68 2307 io_queue_depth);
aa22c8e6 2308 dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */
20d0dfe6 2309 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
7a67cbea 2310 dev->dbs = dev->bar + 4096;
1f390c1f 2311
66341331
BH		 2312 /*
2313 * Some Apple controllers require a non-standard SQE size.
2314 * Interestingly they also seem to ignore the CC:IOSQES register
2315 * so we don't bother updating it here.
2316 */
2317 if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES)
2318 dev->io_sqes = 7;
2319 else
2320 dev->io_sqes = NVME_NVM_IOSQES;
1f390c1f
SG		 2321
2322 /*
2323 * Temporary fix for the Apple controller found in the MacBook8,1 and
2324 * some MacBook7,1 to avoid controller resets and data loss.
2325 */
2326 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
2327 dev->q_depth = 2;
9bdcfb10
CH		 2328 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
2329 "set queue depth=%u to work around controller resets\n",
1f390c1f 2330 dev->q_depth);
d554b5e1
MP		 2331 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2332 (pdev->device == 0xa821 || pdev->device == 0xa822) &&
20d0dfe6 2333 NVME_CAP_MQES(dev->ctrl.cap) == 0) {
d554b5e1
MP		 2334 dev->q_depth = 64;
2335 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2336 "set queue depth=%u\n", dev->q_depth);
1f390c1f
SG		 2337 }
2338
d38e9f04
BH		 2339 /*
2340 * Controllers with the shared tags quirk need the IO queue to be
2341 * big enough so that we get 32 tags for the admin queue
2342 */
2343 if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) &&
2344 (dev->q_depth < (NVME_AQ_DEPTH + 2))) {
2345 dev->q_depth = NVME_AQ_DEPTH + 2;
2346 dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n",
2347 dev->q_depth);
2348 }
2349
2350
f65efd6d 2351 nvme_map_cmb(dev);
202021c1 2352
a0a3408e
KB		 2353 pci_enable_pcie_error_reporting(pdev);
2354 pci_save_state(pdev);
0877cb0d
KB		 2355 return 0;
2356
2357 disable:
0877cb0d
KB		 2358 pci_disable_device(pdev);
2359 return result;
2360}
2361
2362static void nvme_dev_unmap(struct nvme_dev *dev)
b00a726a
KB		 2363{
2364 if (dev->bar)
2365 iounmap(dev->bar);
a1f447b3 2366 pci_release_mem_regions(to_pci_dev(dev->dev));
b00a726a
KB		 2367}
2368
2369static void nvme_pci_disable(struct nvme_dev *dev)
0877cb0d 2370{
e75ec752
CH		 2371 struct pci_dev *pdev = to_pci_dev(dev->dev);
2372
dca51e78 2373 pci_free_irq_vectors(pdev);
0877cb0d 2374
a0a3408e
KB		 2375 if (pci_is_enabled(pdev)) {
2376 pci_disable_pcie_error_reporting(pdev);
e75ec752 2377 pci_disable_device(pdev);
4d115420 2378 }
4d115420
KB		 2379}
2380
a5cdb68c 2381static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
b60503ba 2382{
e43269e6 2383 bool dead = true, freeze = false;
302ad8cc 2384 struct pci_dev *pdev = to_pci_dev(dev->dev);
22404274 2385
77bf25ea 2386 mutex_lock(&dev->shutdown_lock);
302ad8cc
KB		 2387 if (pci_is_enabled(pdev)) {
2388 u32 csts = readl(dev->bar + NVME_REG_CSTS);
2389
ebef7368 2390 if (dev->ctrl.state == NVME_CTRL_LIVE ||
e43269e6
KB		 2391 dev->ctrl.state == NVME_CTRL_RESETTING) {
2392 freeze = true;
302ad8cc 2393 nvme_start_freeze(&dev->ctrl);
e43269e6 2394 }
302ad8cc
KB		 2395 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
2396 pdev->error_state != pci_channel_io_normal);
c9d3bf88 2397 }
c21377f8 2398
302ad8cc
KB		 2399 /*
2400 * Give the controller a chance to complete all entered requests if
2401 * doing a safe shutdown.
2402 */
e43269e6
KB		 2403 if (!dead && shutdown && freeze)
2404 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
9a915a5b
JW		 2405
2406 nvme_stop_queues(&dev->ctrl);
87ad72a5 2407
64ee0ac0 2408 if (!dead && dev->ctrl.queue_count > 0) {
8fae268b 2409 nvme_disable_io_queues(dev);
a5cdb68c 2410 nvme_disable_admin_queue(dev, shutdown);
4d115420 2411 }
8fae268b
KB		 2412 nvme_suspend_io_queues(dev);
2413 nvme_suspend_queue(&dev->queues[0]);
b00a726a 2414 nvme_pci_disable(dev);
fa46c6fb 2415 nvme_reap_pending_cqes(dev);
07836e65 2416
e1958e65
ML		 2417 blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
2418 blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
622b8b68
ML		 2419 blk_mq_tagset_wait_completed_request(&dev->tagset);
2420 blk_mq_tagset_wait_completed_request(&dev->admin_tagset);
302ad8cc
KB		 2421
2422 /*
2423 * The driver will not be starting up queues again if shutting down so
2424 * must flush all entered requests to their failed completion to avoid
2425 * deadlocking blk-mq hot-cpu notifier.
2426 */
c8e9e9b7 2427 if (shutdown) {
302ad8cc 2428 nvme_start_queues(&dev->ctrl);
c8e9e9b7
KB		 2429 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q))
2430 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
2431 }
77bf25ea 2432 mutex_unlock(&dev->shutdown_lock);
b60503ba
MW		 2433}
2434
c1ac9a4b
KB		 2435static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown)
2436{
2437 if (!nvme_wait_reset(&dev->ctrl))
2438 return -EBUSY;
2439 nvme_dev_disable(dev, shutdown);
2440 return 0;
2441}
2442
091b6092
MW		 2443static int nvme_setup_prp_pools(struct nvme_dev *dev)
2444{
e75ec752 2445 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
091b6092
MW		 2446 PAGE_SIZE, PAGE_SIZE, 0);
2447 if (!dev->prp_page_pool)
2448 return -ENOMEM;
2449
99802a7a 2450 /* Optimisation for I/Os between 4k and 128k */
e75ec752 2451 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
99802a7a
MW		 2452 256, 256, 0);
2453 if (!dev->prp_small_pool) {
2454 dma_pool_destroy(dev->prp_page_pool);
2455 return -ENOMEM;
2456 }
091b6092
MW		 2457 return 0;
2458}
2459
2460static void nvme_release_prp_pools(struct nvme_dev *dev)
2461{
2462 dma_pool_destroy(dev->prp_page_pool);
99802a7a 2463 dma_pool_destroy(dev->prp_small_pool);
091b6092
MW		 2464}
2465
770597ec
KB		 2466static void nvme_free_tagset(struct nvme_dev *dev)
2467{
2468 if (dev->tagset.tags)
2469 blk_mq_free_tag_set(&dev->tagset);
2470 dev->ctrl.tagset = NULL;
2471}
2472
1673f1f0 2473static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
5e82e952 2474{
1673f1f0 2475 struct nvme_dev *dev = to_nvme_dev(ctrl);
9ac27090 2476
f9f38e33 2477 nvme_dbbuf_dma_free(dev);
770597ec 2478 nvme_free_tagset(dev);
1c63dc66
CH		 2479 if (dev->ctrl.admin_q)
2480 blk_put_queue(dev->ctrl.admin_q);
e286bcfc 2481 free_opal_dev(dev->ctrl.opal_dev);
943e942e 2482 mempool_destroy(dev->iod_mempool);
253fd4ac
IR		 2483 put_device(dev->dev);
2484 kfree(dev->queues);
5e82e952
KB		 2485 kfree(dev);
2486}
2487
7c1ce408 2488static void nvme_remove_dead_ctrl(struct nvme_dev *dev)
f58944e2 2489{
c1ac9a4b
KB		 2490 /*
2491 * Set state to deleting now to avoid blocking nvme_wait_reset(), which
2492 * may be holding this pci_dev's device lock.
2493 */
2494 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
d22524a4 2495 nvme_get_ctrl(&dev->ctrl);
69d9a99c 2496 nvme_dev_disable(dev, false);
9f9cafc1 2497 nvme_kill_queues(&dev->ctrl);
03e0f3a6 2498 if (!queue_work(nvme_wq, &dev->remove_work))
f58944e2
KB		 2499 nvme_put_ctrl(&dev->ctrl);
2500}
2501
fd634f41 2502static void nvme_reset_work(struct work_struct *work)
5e82e952 2503{
d86c4d8e
CH		 2504 struct nvme_dev *dev =
2505 container_of(work, struct nvme_dev, ctrl.reset_work);
a98e58e5 2506 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
e71afda4 2507 int result;
5e82e952 2508
e71afda4
CK		 2509 if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING)) {
2510 result = -ENODEV;
fd634f41 2511 goto out;
e71afda4 2512 }
5e82e952 2513
fd634f41
CH		 2514 /*
2515 * If we're called to reset a live controller first shut it down before
2516 * moving on.
2517 */
b00a726a 2518 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
a5cdb68c 2519 nvme_dev_disable(dev, false);
d6135c3a 2520 nvme_sync_queues(&dev->ctrl);
5e82e952 2521
5c959d73 2522 mutex_lock(&dev->shutdown_lock);
b00a726a 2523 result = nvme_pci_enable(dev);
f0b50732 2524 if (result)
4726bcf3 2525 goto out_unlock;
f0b50732 2526
01ad0990 2527 result = nvme_pci_configure_admin_queue(dev);
f0b50732 2528 if (result)
4726bcf3 2529 goto out_unlock;
f0b50732 2530
0fb59cbc
KB		 2531 result = nvme_alloc_admin_tags(dev);
2532 if (result)
4726bcf3 2533 goto out_unlock;
b9afca3e 2534
943e942e
JA		 2535 /*
2536 * Limit the max command size to prevent iod->sg allocations going
2537 * over a single page.
2538 */
7637de31
CH		 2539 dev->ctrl.max_hw_sectors = min_t(u32,
2540 NVME_MAX_KB_SZ << 1, dma_max_mapping_size(dev->dev) >> 9);
943e942e 2541 dev->ctrl.max_segments = NVME_MAX_SEGS;
a48bc520
CH		 2542
2543 /*
2544 * Don't limit the IOMMU merged segment size.
2545 */
2546 dma_set_max_seg_size(dev->dev, 0xffffffff);
2547
5c959d73
KB		 2548 mutex_unlock(&dev->shutdown_lock);
2549
2550 /*
2551 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
2552 * initializing procedure here.
2553 */
2554 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
2555 dev_warn(dev->ctrl.device,
2556 "failed to mark controller CONNECTING\n");
cee6c269 2557 result = -EBUSY;
5c959d73
KB		 2558 goto out;
2559 }
943e942e 2560
ce4541f4
CH		 2561 result = nvme_init_identify(&dev->ctrl);
2562 if (result)
f58944e2 2563 goto out;
ce4541f4 2564
e286bcfc
SB		 2565 if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
2566 if (!dev->ctrl.opal_dev)
2567 dev->ctrl.opal_dev =
2568 init_opal_dev(&dev->ctrl, &nvme_sec_submit);
2569 else if (was_suspend)
2570 opal_unlock_from_suspend(dev->ctrl.opal_dev);
2571 } else {
2572 free_opal_dev(dev->ctrl.opal_dev);
2573 dev->ctrl.opal_dev = NULL;
4f1244c8 2574 }
a98e58e5 2575
f9f38e33
HK		 2576 if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) {
2577 result = nvme_dbbuf_dma_alloc(dev);
2578 if (result)
2579 dev_warn(dev->dev,
2580 "unable to allocate dma for dbbuf\n");
2581 }
2582
9620cfba
CH		 2583 if (dev->ctrl.hmpre) {
2584 result = nvme_setup_host_mem(dev);
2585 if (result < 0)
2586 goto out;
2587 }
87ad72a5 2588
f0b50732 2589 result = nvme_setup_io_queues(dev);
badc34d4 2590 if (result)
f58944e2 2591 goto out;
f0b50732 2592
2659e57b
CH		 2593 /*
2594 * Keep the controller around but remove all namespaces if we don't have
2595 * any working I/O queue.
2596 */
3cf519b5 2597 if (dev->online_queues < 2) {
1b3c47c1 2598 dev_warn(dev->ctrl.device, "IO queues not created\n");
3b24774e 2599 nvme_kill_queues(&dev->ctrl);
5bae7f73 2600 nvme_remove_namespaces(&dev->ctrl);
770597ec 2601 nvme_free_tagset(dev);
3cf519b5 2602 } else {
25646264 2603 nvme_start_queues(&dev->ctrl);
302ad8cc 2604 nvme_wait_freeze(&dev->ctrl);
5d02a5c1 2605 nvme_dev_add(dev);
302ad8cc 2606 nvme_unfreeze(&dev->ctrl);
3cf519b5
CH		 2607 }
2608
2b1b7e78
JW		 2609 /*
2610 * If only admin queue live, keep it to do further investigation or
2611 * recovery.
2612 */
5d02a5c1 2613 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
2b1b7e78 2614 dev_warn(dev->ctrl.device,
5d02a5c1 2615 "failed to mark controller live state\n");
e71afda4 2616 result = -ENODEV;
bb8d261e
CH		 2617 goto out;
2618 }
92911a55 2619
d09f2b45 2620 nvme_start_ctrl(&dev->ctrl);
3cf519b5 2621 return;
f0b50732 2622
4726bcf3
KB		 2623 out_unlock:
2624 mutex_unlock(&dev->shutdown_lock);
3cf519b5 2625 out:
7c1ce408
CK		 2626 if (result)
2627 dev_warn(dev->ctrl.device,
2628 "Removing after probe failure status: %d\n", result);
2629 nvme_remove_dead_ctrl(dev);
f0b50732
KB		 2630}
2631
5c8809e6 2632static void nvme_remove_dead_ctrl_work(struct work_struct *work)
9a6b9458 2633{
5c8809e6 2634 struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
e75ec752 2635 struct pci_dev *pdev = to_pci_dev(dev->dev);
9a6b9458
KB		 2636
2637 if (pci_get_drvdata(pdev))
921920ab 2638 device_release_driver(&pdev->dev);
1673f1f0 2639 nvme_put_ctrl(&dev->ctrl);
9a6b9458
KB		 2640}
2641
1c63dc66 2642static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
9ca97374 2643{
1c63dc66 2644 *val = readl(to_nvme_dev(ctrl)->bar + off);
90667892 2645 return 0;
9ca97374
TH		 2646}
2647
5fd4ce1b 2648static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
4cc06521 2649{
5fd4ce1b
CH		 2650 writel(val, to_nvme_dev(ctrl)->bar + off);
2651 return 0;
2652}
4cc06521 2653
7fd8930f
CH		 2654static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2655{
3a8ecc93 2656 *val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off);
7fd8930f 2657 return 0;
4cc06521
KB		 2658}
2659
97c12223
KB		 2660static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
2661{
2662 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2663
2db24e4a 2664 return snprintf(buf, size, "%s\n", dev_name(&pdev->dev));
97c12223
KB		 2665}
2666
1c63dc66 2667static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
1a353d85 2668 .name = "pcie",
e439bb12 2669 .module = THIS_MODULE,
e0596ab2
LG		 2670 .flags = NVME_F_METADATA_SUPPORTED |
2671 NVME_F_PCI_P2PDMA,
1c63dc66 2672 .reg_read32 = nvme_pci_reg_read32,
5fd4ce1b 2673 .reg_write32 = nvme_pci_reg_write32,
7fd8930f 2674 .reg_read64 = nvme_pci_reg_read64,
1673f1f0 2675 .free_ctrl = nvme_pci_free_ctrl,
f866fc42 2676 .submit_async_event = nvme_pci_submit_async_event,
97c12223 2677 .get_address = nvme_pci_get_address,
1c63dc66 2678};
4cc06521 2679
b00a726a
KB		 2680static int nvme_dev_map(struct nvme_dev *dev)
2681{
b00a726a
KB		 2682 struct pci_dev *pdev = to_pci_dev(dev->dev);
2683
a1f447b3 2684 if (pci_request_mem_regions(pdev, "nvme"))
b00a726a
KB		 2685 return -ENODEV;
2686
97f6ef64 2687 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
b00a726a
KB		 2688 goto release;
2689
9fa196e7 2690 return 0;
b00a726a 2691 release:
9fa196e7
MG		 2692 pci_release_mem_regions(pdev);
2693 return -ENODEV;
b00a726a
KB		 2694}
2695
8427bbc2 2696static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
ff5350a8
AL		 2697{
2698 if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
2699 /*
2700 * Several Samsung devices seem to drop off the PCIe bus
2701 * randomly when APST is on and uses the deepest sleep state.
2702 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2703 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2704 * 950 PRO 256GB", but it seems to be restricted to two Dell
2705 * laptops.
2706 */
2707 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
2708 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
2709 dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
2710 return NVME_QUIRK_NO_DEEPEST_PS;
8427bbc2
KHF		 2711 } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
2712 /*
2713 * Samsung SSD 960 EVO drops off the PCIe bus after system
467c77d4
JJ		 2714 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
2715 * within few minutes after bootup on a Coffee Lake board -
2716 * ASUS PRIME Z370-A
8427bbc2
KHF		 2717 */
2718 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
467c77d4
JJ		 2719 (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") ||
2720 dmi_match(DMI_BOARD_NAME, "PRIME Z370-A")))
8427bbc2 2721 return NVME_QUIRK_NO_APST;
1fae37ac
S		 2722 } else if ((pdev->vendor == 0x144d && (pdev->device == 0xa801 ||
2723 pdev->device == 0xa808 || pdev->device == 0xa809)) ||
2724 (pdev->vendor == 0x1e0f && pdev->device == 0x0001)) {
2725 /*
2726 * Forcing to use host managed nvme power settings for
2727 * lowest idle power with quick resume latency on
2728 * Samsung and Toshiba SSDs based on suspend behavior
2729 * on Coffee Lake board for LENOVO C640
2730 */
2731 if ((dmi_match(DMI_BOARD_VENDOR, "LENOVO")) &&
2732 dmi_match(DMI_BOARD_NAME, "LNVNB161216"))
2733 return NVME_QUIRK_SIMPLE_SUSPEND;
ff5350a8
AL		 2734 }
2735
2736 return 0;
2737}
2738
18119775
KB		 2739static void nvme_async_probe(void *data, async_cookie_t cookie)
2740{
2741 struct nvme_dev *dev = data;
80f513b5 2742
bd46a906 2743 flush_work(&dev->ctrl.reset_work);
18119775 2744 flush_work(&dev->ctrl.scan_work);
80f513b5 2745 nvme_put_ctrl(&dev->ctrl);
18119775
KB		 2746}
2747
8d85fce7 2748static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
b60503ba 2749{
a4aea562 2750 int node, result = -ENOMEM;
b60503ba 2751 struct nvme_dev *dev;
ff5350a8 2752 unsigned long quirks = id->driver_data;
943e942e 2753 size_t alloc_size;
b60503ba 2754
a4aea562
MB		 2755 node = dev_to_node(&pdev->dev);
2756 if (node == NUMA_NO_NODE)
2fa84351 2757 set_dev_node(&pdev->dev, first_memory_node);
a4aea562
MB		 2758
2759 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
b60503ba
MW		 2760 if (!dev)
2761 return -ENOMEM;
147b27e4 2762
3b6592f7
JA		 2763 dev->queues = kcalloc_node(max_queue_count(), sizeof(struct nvme_queue),
2764 GFP_KERNEL, node);
b60503ba
MW		 2765 if (!dev->queues)
2766 goto free;
2767
e75ec752 2768 dev->dev = get_device(&pdev->dev);
9a6b9458 2769 pci_set_drvdata(pdev, dev);
1c63dc66 2770
b00a726a
KB		 2771 result = nvme_dev_map(dev);
2772 if (result)
b00c9b7a 2773 goto put_pci;
b00a726a 2774
d86c4d8e 2775 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
5c8809e6 2776 INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
77bf25ea 2777 mutex_init(&dev->shutdown_lock);
b60503ba 2778
091b6092
MW		 2779 result = nvme_setup_prp_pools(dev);
2780 if (result)
b00c9b7a 2781 goto unmap;
4cc06521 2782
8427bbc2 2783 quirks |= check_vendor_combination_bug(pdev);
ff5350a8 2784
943e942e
JA		 2785 /*
2786 * Double check that our mempool alloc size will cover the biggest
2787 * command we support.
2788 */
2789 alloc_size = nvme_pci_iod_alloc_size(dev, NVME_MAX_KB_SZ,
2790 NVME_MAX_SEGS, true);
2791 WARN_ON_ONCE(alloc_size > PAGE_SIZE);
2792
2793 dev->iod_mempool = mempool_create_node(1, mempool_kmalloc,
2794 mempool_kfree,
2795 (void *) alloc_size,
2796 GFP_KERNEL, node);
2797 if (!dev->iod_mempool) {
2798 result = -ENOMEM;
2799 goto release_pools;
2800 }
2801
b6e44b4c
KB		 2802 result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
2803 quirks);
2804 if (result)
2805 goto release_mempool;
2806
1b3c47c1
SG		 2807 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
2808
bd46a906 2809 nvme_reset_ctrl(&dev->ctrl);
18119775 2810 async_schedule(nvme_async_probe, dev);
4caff8fc 2811
b60503ba
MW		 2812 return 0;
2813
b6e44b4c
KB		 2814 release_mempool:
2815 mempool_destroy(dev->iod_mempool);
0877cb0d 2816 release_pools:
091b6092 2817 nvme_release_prp_pools(dev);
b00c9b7a
CJ		 2818 unmap:
2819 nvme_dev_unmap(dev);
a96d4f5c 2820 put_pci:
e75ec752 2821 put_device(dev->dev);
b60503ba
MW		 2822 free:
2823 kfree(dev->queues);
b60503ba
MW		 2824 kfree(dev);
2825 return result;
2826}
2827
775755ed 2828static void nvme_reset_prepare(struct pci_dev *pdev)
f0d54a54 2829{
a6739479 2830 struct nvme_dev *dev = pci_get_drvdata(pdev);
c1ac9a4b
KB		 2831
2832 /*
2833 * We don't need to check the return value from waiting for the reset
2834 * state as pci_dev device lock is held, making it impossible to race
2835 * with ->remove().
2836 */
2837 nvme_disable_prepare_reset(dev, false);
2838 nvme_sync_queues(&dev->ctrl);
775755ed 2839}
f0d54a54 2840
775755ed
CH		 2841static void nvme_reset_done(struct pci_dev *pdev)
2842{
f263fbb8 2843 struct nvme_dev *dev = pci_get_drvdata(pdev);
c1ac9a4b
KB		 2844
2845 if (!nvme_try_sched_reset(&dev->ctrl))
2846 flush_work(&dev->ctrl.reset_work);
f0d54a54
KB		 2847}
2848
09ece142
KB		 2849static void nvme_shutdown(struct pci_dev *pdev)
2850{
2851 struct nvme_dev *dev = pci_get_drvdata(pdev);
c1ac9a4b 2852 nvme_disable_prepare_reset(dev, true);
09ece142
KB		 2853}
2854
f58944e2
KB		 2855/*
2856 * The driver's remove may be called on a device in a partially initialized
2857 * state. This function must not have any dependencies on the device state in
2858 * order to proceed.
2859 */
8d85fce7 2860static void nvme_remove(struct pci_dev *pdev)
b60503ba
MW		 2861{
2862 struct nvme_dev *dev = pci_get_drvdata(pdev);
9a6b9458 2863
bb8d261e 2864 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
9a6b9458 2865 pci_set_drvdata(pdev, NULL);
0ff9d4e1 2866
6db28eda 2867 if (!pci_device_is_present(pdev)) {
0ff9d4e1 2868 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
1d39e692 2869 nvme_dev_disable(dev, true);
cb4bfda6 2870 nvme_dev_remove_admin(dev);
6db28eda 2871 }
0ff9d4e1 2872
d86c4d8e 2873 flush_work(&dev->ctrl.reset_work);
d09f2b45
SG		 2874 nvme_stop_ctrl(&dev->ctrl);
2875 nvme_remove_namespaces(&dev->ctrl);
a5cdb68c 2876 nvme_dev_disable(dev, true);
9fe5c59f 2877 nvme_release_cmb(dev);
87ad72a5 2878 nvme_free_host_mem(dev);
a4aea562 2879 nvme_dev_remove_admin(dev);
a1a5ef99 2880 nvme_free_queues(dev, 0);
9a6b9458 2881 nvme_release_prp_pools(dev);
b00a726a 2882 nvme_dev_unmap(dev);
726612b6 2883 nvme_uninit_ctrl(&dev->ctrl);
b60503ba
MW		 2884}
2885
671a6018 2886#ifdef CONFIG_PM_SLEEP
d916b1be
KB		 2887static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps)
2888{
2889 return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps);
2890}
2891
2892static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps)
2893{
2894 return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL);
2895}
2896
2897static int nvme_resume(struct device *dev)
2898{
2899 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
2900 struct nvme_ctrl *ctrl = &ndev->ctrl;
2901
4eaefe8c 2902 if (ndev->last_ps == U32_MAX ||
d916b1be 2903 nvme_set_power_state(ctrl, ndev->last_ps) != 0)
c1ac9a4b 2904 return nvme_try_sched_reset(&ndev->ctrl);
d916b1be
KB		 2905 return 0;
2906}
2907
cd638946
KB		 2908static int nvme_suspend(struct device *dev)
2909{
2910 struct pci_dev *pdev = to_pci_dev(dev);
2911 struct nvme_dev *ndev = pci_get_drvdata(pdev);
d916b1be
KB		 2912 struct nvme_ctrl *ctrl = &ndev->ctrl;
2913 int ret = -EBUSY;
2914
4eaefe8c
RW		 2915 ndev->last_ps = U32_MAX;
2916
d916b1be
KB		 2917 /*
2918 * The platform does not remove power for a kernel managed suspend so
2919 * use host managed nvme power settings for lowest idle power if
2920 * possible. This should have quicker resume latency than a full device
2921 * shutdown. But if the firmware is involved after the suspend or the
2922 * device does not support any non-default power states, shut down the
2923 * device fully.
4eaefe8c
RW		 2924 *
2925 * If ASPM is not enabled for the device, shut down the device and allow
2926 * the PCI bus layer to put it into D3 in order to take the PCIe link
2927 * down, so as to allow the platform to achieve its minimum low-power
2928 * state (which may not be possible if the link is up).
d916b1be 2929 */
4eaefe8c 2930 if (pm_suspend_via_firmware() || !ctrl->npss ||
cb32de1b 2931 !pcie_aspm_enabled(pdev) ||
c1ac9a4b
KB		 2932 (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND))
2933 return nvme_disable_prepare_reset(ndev, true);
d916b1be
KB		 2934
2935 nvme_start_freeze(ctrl);
2936 nvme_wait_freeze(ctrl);
2937 nvme_sync_queues(ctrl);
2938
5d02a5c1 2939 if (ctrl->state != NVME_CTRL_LIVE)
d916b1be
KB		 2940 goto unfreeze;
2941
d916b1be
KB		 2942 ret = nvme_get_power_state(ctrl, &ndev->last_ps);
2943 if (ret < 0)
2944 goto unfreeze;
2945
7cbb5c6f
ML		 2946 /*
2947 * A saved state prevents pci pm from generically controlling the
2948 * device's power. If we're using protocol specific settings, we don't
2949 * want pci interfering.
2950 */
2951 pci_save_state(pdev);
2952
d916b1be
KB		 2953 ret = nvme_set_power_state(ctrl, ctrl->npss);
2954 if (ret < 0)
2955 goto unfreeze;
2956
2957 if (ret) {
7cbb5c6f
ML		 2958 /* discard the saved state */
2959 pci_load_saved_state(pdev, NULL);
2960
d916b1be
KB		 2961 /*
2962 * Clearing npss forces a controller reset on resume. The
05d3046f 2963 * correct value will be rediscovered then.
d916b1be 2964 */
c1ac9a4b 2965 ret = nvme_disable_prepare_reset(ndev, true);
d916b1be 2966 ctrl->npss = 0;
d916b1be 2967 }
d916b1be
KB		 2968unfreeze:
2969 nvme_unfreeze(ctrl);
2970 return ret;
2971}
2972
2973static int nvme_simple_suspend(struct device *dev)
2974{
2975 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
c1ac9a4b 2976 return nvme_disable_prepare_reset(ndev, true);
cd638946
KB		 2977}
2978
d916b1be 2979static int nvme_simple_resume(struct device *dev)
cd638946
KB		 2980{
2981 struct pci_dev *pdev = to_pci_dev(dev);
2982 struct nvme_dev *ndev = pci_get_drvdata(pdev);
cd638946 2983
c1ac9a4b 2984 return nvme_try_sched_reset(&ndev->ctrl);
cd638946
KB		 2985}
2986
21774222 2987static const struct dev_pm_ops nvme_dev_pm_ops = {
d916b1be
KB		 2988 .suspend = nvme_suspend,
2989 .resume = nvme_resume,
2990 .freeze = nvme_simple_suspend,
2991 .thaw = nvme_simple_resume,
2992 .poweroff = nvme_simple_suspend,
2993 .restore = nvme_simple_resume,
2994};
2995#endif /* CONFIG_PM_SLEEP */
b60503ba 2996
a0a3408e
KB		 2997static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
2998 pci_channel_state_t state)
2999{
3000 struct nvme_dev *dev = pci_get_drvdata(pdev);
3001
3002 /*
3003 * A frozen channel requires a reset. When detected, this method will
3004 * shutdown the controller to quiesce. The controller will be restarted
3005 * after the slot reset through driver's slot_reset callback.
3006 */
a0a3408e
KB		 3007 switch (state) {
3008 case pci_channel_io_normal:
3009 return PCI_ERS_RESULT_CAN_RECOVER;
3010 case pci_channel_io_frozen:
d011fb31
KB		 3011 dev_warn(dev->ctrl.device,
3012 "frozen state error detected, reset controller\n");
a5cdb68c 3013 nvme_dev_disable(dev, false);
a0a3408e
KB		 3014 return PCI_ERS_RESULT_NEED_RESET;
3015 case pci_channel_io_perm_failure:
d011fb31
KB		 3016 dev_warn(dev->ctrl.device,
3017 "failure state error detected, request disconnect\n");
a0a3408e
KB		 3018 return PCI_ERS_RESULT_DISCONNECT;
3019 }
3020 return PCI_ERS_RESULT_NEED_RESET;
3021}
3022
3023static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
3024{
3025 struct nvme_dev *dev = pci_get_drvdata(pdev);
3026
1b3c47c1 3027 dev_info(dev->ctrl.device, "restart after slot reset\n");
a0a3408e 3028 pci_restore_state(pdev);
d86c4d8e 3029 nvme_reset_ctrl(&dev->ctrl);
a0a3408e
KB		 3030 return PCI_ERS_RESULT_RECOVERED;
3031}
3032
3033static void nvme_error_resume(struct pci_dev *pdev)
3034{
72cd4cc2
KB		 3035 struct nvme_dev *dev = pci_get_drvdata(pdev);
3036
3037 flush_work(&dev->ctrl.reset_work);
a0a3408e
KB		 3038}
3039
1d352035 3040static const struct pci_error_handlers nvme_err_handler = {
b60503ba 3041 .error_detected = nvme_error_detected,
b60503ba
MW		 3042 .slot_reset = nvme_slot_reset,
3043 .resume = nvme_error_resume,
775755ed
CH		 3044 .reset_prepare = nvme_reset_prepare,
3045 .reset_done = nvme_reset_done,
b60503ba
MW		 3046};
3047
6eb0d698 3048static const struct pci_device_id nvme_id_table[] = {
106198ed 3049 { PCI_VDEVICE(INTEL, 0x0953),
08095e70 3050 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 3051 NVME_QUIRK_DEALLOCATE_ZEROES, },
99466e70
KB		 3052 { PCI_VDEVICE(INTEL, 0x0a53),
3053 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 3054 NVME_QUIRK_DEALLOCATE_ZEROES, },
99466e70
KB		 3055 { PCI_VDEVICE(INTEL, 0x0a54),
3056 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 3057 NVME_QUIRK_DEALLOCATE_ZEROES, },
f99cb7af
DWF		 3058 { PCI_VDEVICE(INTEL, 0x0a55),
3059 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3060 NVME_QUIRK_DEALLOCATE_ZEROES, },
50af47d0 3061 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */
9abd68ef 3062 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
6c6aa2f2
AM		 3063 NVME_QUIRK_MEDIUM_PRIO_SQ |
3064 NVME_QUIRK_NO_TEMP_THRESH_CHANGE },
6299358d
JD		 3065 { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */
3066 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
540c801c 3067 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */
7b210e4e
CH		 3068 .driver_data = NVME_QUIRK_IDENTIFY_CNS |
3069 NVME_QUIRK_DISABLE_WRITE_ZEROES, },
0302ae60
MP		 3070 { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */
3071 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
54adc010
GP		 3072 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
3073 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
8c97eecc
JL		 3074 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */
3075 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
015282c9
WW		 3076 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
3077 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
d554b5e1
MP		 3078 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */
3079 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3080 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */
3081 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
608cc4b1
CH		 3082 { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */
3083 .driver_data = NVME_QUIRK_LIGHTNVM, },
3084 { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */
3085 .driver_data = NVME_QUIRK_LIGHTNVM, },
ea48e877
WX		 3086 { PCI_DEVICE(0x1d1d, 0x2601), /* CNEX Granby */
3087 .driver_data = NVME_QUIRK_LIGHTNVM, },
08b903b5
MN		 3088 { PCI_DEVICE(0x10ec, 0x5762), /* ADATA SX6000LNP */
3089 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
f03e42c6
GC		 3090 { PCI_DEVICE(0x1cc1, 0x8201), /* ADATA SX8200PNP 512GB */
3091 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3092 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
b60503ba 3093 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
98f7b86a
AS		 3094 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001),
3095 .driver_data = NVME_QUIRK_SINGLE_VECTOR },
124298bd 3096 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
66341331
BH		 3097 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005),
3098 .driver_data = NVME_QUIRK_SINGLE_VECTOR |
d38e9f04
BH		 3099 NVME_QUIRK_128_BYTES_SQES |
3100 NVME_QUIRK_SHARED_TAGS },
b60503ba
MW		 3101 { 0, }
3102};
3103MODULE_DEVICE_TABLE(pci, nvme_id_table);
3104
3105static struct pci_driver nvme_driver = {
3106 .name = "nvme",
3107 .id_table = nvme_id_table,
3108 .probe = nvme_probe,
8d85fce7 3109 .remove = nvme_remove,
09ece142 3110 .shutdown = nvme_shutdown,
d916b1be 3111#ifdef CONFIG_PM_SLEEP
cd638946
KB		 3112 .driver = {
3113 .pm = &nvme_dev_pm_ops,
3114 },
d916b1be 3115#endif
74d986ab 3116 .sriov_configure = pci_sriov_configure_simple,
b60503ba
MW		 3117 .err_handler = &nvme_err_handler,
3118};
3119
3120static int __init nvme_init(void)
3121{
81101540
CH		 3122 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
3123 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
3124 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
612b7286 3125 BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2);
17c33167
KB		 3126
3127 write_queues = min(write_queues, num_possible_cpus());
3128 poll_queues = min(poll_queues, num_possible_cpus());
9a6327d2 3129 return pci_register_driver(&nvme_driver);
b60503ba
MW		 3130}
3131
3132static void __exit nvme_exit(void)
3133{
3134 pci_unregister_driver(&nvme_driver);
03e0f3a6 3135 flush_workqueue(nvme_wq);
b60503ba
MW		 3136}
3137
3138MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3139MODULE_LICENSE("GPL");
c78b4713 3140MODULE_VERSION("1.0");
b60503ba
MW		 3141module_init(nvme_init);
3142module_exit(nvme_exit);
Linux 6.x block layer and io_uring tree(s)