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nvme: fix the read-only state for zoned namespaces with unsupposed features
[linux-2.6-block.git] / drivers / nvme / host / pci.c
CommitLineData
5f37396d 1// SPDX-License-Identifier: GPL-2.0
b60503ba
MW		 2/*
3 * NVM Express device driver
6eb0d698 4 * Copyright (c) 2011-2014, Intel Corporation.
b60503ba
MW		 5 */
6
df4f9bc4 7#include <linux/acpi.h>
a0a3408e 8#include <linux/aer.h>
18119775 9#include <linux/async.h>
b60503ba 10#include <linux/blkdev.h>
a4aea562 11#include <linux/blk-mq.h>
dca51e78 12#include <linux/blk-mq-pci.h>
fe45e630 13#include <linux/blk-integrity.h>
ff5350a8 14#include <linux/dmi.h>
b60503ba
MW		 15#include <linux/init.h>
16#include <linux/interrupt.h>
17#include <linux/io.h>
b60503ba
MW		 18#include <linux/mm.h>
19#include <linux/module.h>
77bf25ea 20#include <linux/mutex.h>
d0877473 21#include <linux/once.h>
b60503ba 22#include <linux/pci.h>
d916b1be 23#include <linux/suspend.h>
e1e5e564 24#include <linux/t10-pi.h>
b60503ba 25#include <linux/types.h>
2f8e2c87 26#include <linux/io-64-nonatomic-lo-hi.h>
20d3bb92 27#include <linux/io-64-nonatomic-hi-lo.h>
a98e58e5 28#include <linux/sed-opal.h>
0f238ff5 29#include <linux/pci-p2pdma.h>
797a796a 30
604c01d5 31#include "trace.h"
f11bb3e2
CH		 32#include "nvme.h"
33
c1e0cc7e 34#define SQ_SIZE(q) ((q)->q_depth << (q)->sqes)
8a1d09a6 35#define CQ_SIZE(q) ((q)->q_depth * sizeof(struct nvme_completion))
c965809c 36
a7a7cbe3 37#define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc))
9d43cf64 38
943e942e
JA		 39/*
40 * These can be higher, but we need to ensure that any command doesn't
41 * require an sg allocation that needs more than a page of data.
42 */
43#define NVME_MAX_KB_SZ 4096
44#define NVME_MAX_SEGS 127
45
58ffacb5
MW		 46static int use_threaded_interrupts;
47module_param(use_threaded_interrupts, int, 0);
48
8ffaadf7 49static bool use_cmb_sqes = true;
69f4eb9f 50module_param(use_cmb_sqes, bool, 0444);
8ffaadf7
JD		 51MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
52
87ad72a5
CH		 53static unsigned int max_host_mem_size_mb = 128;
54module_param(max_host_mem_size_mb, uint, 0444);
55MODULE_PARM_DESC(max_host_mem_size_mb,
56 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
1fa6aead 57
a7a7cbe3
CK		 58static unsigned int sgl_threshold = SZ_32K;
59module_param(sgl_threshold, uint, 0644);
60MODULE_PARM_DESC(sgl_threshold,
61 "Use SGLs when average request segment size is larger or equal to "
62 "this size. Use 0 to disable SGLs.");
63
27453b45
SG		 64#define NVME_PCI_MIN_QUEUE_SIZE 2
65#define NVME_PCI_MAX_QUEUE_SIZE 4095
b27c1e68 66static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
67static const struct kernel_param_ops io_queue_depth_ops = {
68 .set = io_queue_depth_set,
61f3b896 69 .get = param_get_uint,
b27c1e68 70};
71
61f3b896 72static unsigned int io_queue_depth = 1024;
b27c1e68 73module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
27453b45 74MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2 and < 4096");
b27c1e68 75
9c9e76d5
WZ		 76static int io_queue_count_set(const char *val, const struct kernel_param *kp)
77{
78 unsigned int n;
79 int ret;
80
81 ret = kstrtouint(val, 10, &n);
82 if (ret != 0 || n > num_possible_cpus())
83 return -EINVAL;
84 return param_set_uint(val, kp);
85}
86
87static const struct kernel_param_ops io_queue_count_ops = {
88 .set = io_queue_count_set,
89 .get = param_get_uint,
90};
91
3f68baf7 92static unsigned int write_queues;
9c9e76d5 93module_param_cb(write_queues, &io_queue_count_ops, &write_queues, 0644);
3b6592f7
JA		 94MODULE_PARM_DESC(write_queues,
95 "Number of queues to use for writes. If not set, reads and writes "
96 "will share a queue set.");
97
3f68baf7 98static unsigned int poll_queues;
9c9e76d5 99module_param_cb(poll_queues, &io_queue_count_ops, &poll_queues, 0644);
4b04cc6a
JA		 100MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO.");
101
df4f9bc4
DB		 102static bool noacpi;
103module_param(noacpi, bool, 0444);
104MODULE_PARM_DESC(noacpi, "disable acpi bios quirks");
105
1c63dc66
CH		 106struct nvme_dev;
107struct nvme_queue;
b3fffdef 108
a5cdb68c 109static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
8fae268b 110static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode);
d4b4ff8e 111
1c63dc66
CH		 112/*
113 * Represents an NVM Express device. Each nvme_dev is a PCI function.
114 */
115struct nvme_dev {
147b27e4 116 struct nvme_queue *queues;
1c63dc66
CH		 117 struct blk_mq_tag_set tagset;
118 struct blk_mq_tag_set admin_tagset;
119 u32 __iomem *dbs;
120 struct device *dev;
121 struct dma_pool *prp_page_pool;
122 struct dma_pool *prp_small_pool;
1c63dc66
CH		 123 unsigned online_queues;
124 unsigned max_qid;
e20ba6e1 125 unsigned io_queues[HCTX_MAX_TYPES];
22b55601 126 unsigned int num_vecs;
7442ddce 127 u32 q_depth;
c1e0cc7e 128 int io_sqes;
1c63dc66 129 u32 db_stride;
1c63dc66 130 void __iomem *bar;
97f6ef64 131 unsigned long bar_mapped_size;
5c8809e6 132 struct work_struct remove_work;
77bf25ea 133 struct mutex shutdown_lock;
1c63dc66 134 bool subsystem;
1c63dc66 135 u64 cmb_size;
0f238ff5 136 bool cmb_use_sqes;
1c63dc66 137 u32 cmbsz;
202021c1 138 u32 cmbloc;
1c63dc66 139 struct nvme_ctrl ctrl;
d916b1be 140 u32 last_ps;
a5df5e79 141 bool hmb;
87ad72a5 142
943e942e
JA		 143 mempool_t *iod_mempool;
144
87ad72a5 145 /* shadow doorbell buffer support: */
f9f38e33
HK		 146 u32 *dbbuf_dbs;
147 dma_addr_t dbbuf_dbs_dma_addr;
148 u32 *dbbuf_eis;
149 dma_addr_t dbbuf_eis_dma_addr;
87ad72a5
CH		 150
151 /* host memory buffer support: */
152 u64 host_mem_size;
153 u32 nr_host_mem_descs;
4033f35d 154 dma_addr_t host_mem_descs_dma;
87ad72a5
CH		 155 struct nvme_host_mem_buf_desc *host_mem_descs;
156 void **host_mem_desc_bufs;
2a5bcfdd
WZ		 157 unsigned int nr_allocated_queues;
158 unsigned int nr_write_queues;
159 unsigned int nr_poll_queues;
0521905e
KB		 160
161 bool attrs_added;
4d115420 162};
1fa6aead 163
b27c1e68 164static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
165{
27453b45
SG		 166 return param_set_uint_minmax(val, kp, NVME_PCI_MIN_QUEUE_SIZE,
167 NVME_PCI_MAX_QUEUE_SIZE);
b27c1e68 168}
169
f9f38e33
HK		 170static inline unsigned int sq_idx(unsigned int qid, u32 stride)
171{
172 return qid * 2 * stride;
173}
174
175static inline unsigned int cq_idx(unsigned int qid, u32 stride)
176{
177 return (qid * 2 + 1) * stride;
178}
179
1c63dc66
CH		 180static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
181{
182 return container_of(ctrl, struct nvme_dev, ctrl);
183}
184
b60503ba
MW		 185/*
186 * An NVM Express queue. Each device has at least two (one for admin
187 * commands and one for I/O commands).
188 */
189struct nvme_queue {
091b6092 190 struct nvme_dev *dev;
1ab0cd69 191 spinlock_t sq_lock;
c1e0cc7e 192 void *sq_cmds;
3a7afd8e
CH		 193 /* only used for poll queues: */
194 spinlock_t cq_poll_lock ____cacheline_aligned_in_smp;
74943d45 195 struct nvme_completion *cqes;
b60503ba
MW		 196 dma_addr_t sq_dma_addr;
197 dma_addr_t cq_dma_addr;
b60503ba 198 u32 __iomem *q_db;
7442ddce 199 u32 q_depth;
7c349dde 200 u16 cq_vector;
b60503ba 201 u16 sq_tail;
38210800 202 u16 last_sq_tail;
b60503ba 203 u16 cq_head;
c30341dc 204 u16 qid;
e9539f47 205 u8 cq_phase;
c1e0cc7e 206 u8 sqes;
4e224106
CH		 207 unsigned long flags;
208#define NVMEQ_ENABLED 0
63223078 209#define NVMEQ_SQ_CMB 1
d1ed6aa1 210#define NVMEQ_DELETE_ERROR 2
7c349dde 211#define NVMEQ_POLLED 3
f9f38e33
HK		 212 u32 *dbbuf_sq_db;
213 u32 *dbbuf_cq_db;
214 u32 *dbbuf_sq_ei;
215 u32 *dbbuf_cq_ei;
d1ed6aa1 216 struct completion delete_done;
b60503ba
MW		 217};
218
71bd150c 219/*
9b048119
CH		 220 * The nvme_iod describes the data in an I/O.
221 *
222 * The sg pointer contains the list of PRP/SGL chunk allocations in addition
223 * to the actual struct scatterlist.
71bd150c
CH		 224 */
225struct nvme_iod {
d49187e9 226 struct nvme_request req;
af7fae85 227 struct nvme_command cmd;
f4800d6d 228 struct nvme_queue *nvmeq;
a7a7cbe3 229 bool use_sgl;
f4800d6d 230 int aborted;
71bd150c 231 int npages; /* In the PRP list. 0 means small pool in use */
71bd150c 232 int nents; /* Used in scatterlist */
71bd150c 233 dma_addr_t first_dma;
dff824b2 234 unsigned int dma_len; /* length of single DMA segment mapping */
783b94bd 235 dma_addr_t meta_dma;
f4800d6d 236 struct scatterlist *sg;
b60503ba
MW		 237};
238
2a5bcfdd 239static inline unsigned int nvme_dbbuf_size(struct nvme_dev *dev)
3b6592f7 240{
2a5bcfdd 241 return dev->nr_allocated_queues * 8 * dev->db_stride;
f9f38e33
HK		 242}
243
244static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
245{
2a5bcfdd 246 unsigned int mem_size = nvme_dbbuf_size(dev);
f9f38e33 247
58847f12
KB		 248 if (dev->dbbuf_dbs) {
249 /*
250 * Clear the dbbuf memory so the driver doesn't observe stale
251 * values from the previous instantiation.
252 */
253 memset(dev->dbbuf_dbs, 0, mem_size);
254 memset(dev->dbbuf_eis, 0, mem_size);
f9f38e33 255 return 0;
58847f12 256 }
f9f38e33
HK		 257
258 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
259 &dev->dbbuf_dbs_dma_addr,
260 GFP_KERNEL);
261 if (!dev->dbbuf_dbs)
262 return -ENOMEM;
263 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
264 &dev->dbbuf_eis_dma_addr,
265 GFP_KERNEL);
266 if (!dev->dbbuf_eis) {
267 dma_free_coherent(dev->dev, mem_size,
268 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
269 dev->dbbuf_dbs = NULL;
270 return -ENOMEM;
271 }
272
273 return 0;
274}
275
276static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
277{
2a5bcfdd 278 unsigned int mem_size = nvme_dbbuf_size(dev);
f9f38e33
HK		 279
280 if (dev->dbbuf_dbs) {
281 dma_free_coherent(dev->dev, mem_size,
282 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
283 dev->dbbuf_dbs = NULL;
284 }
285 if (dev->dbbuf_eis) {
286 dma_free_coherent(dev->dev, mem_size,
287 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
288 dev->dbbuf_eis = NULL;
289 }
290}
291
292static void nvme_dbbuf_init(struct nvme_dev *dev,
293 struct nvme_queue *nvmeq, int qid)
294{
295 if (!dev->dbbuf_dbs || !qid)
296 return;
297
298 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
299 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
300 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
301 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
302}
303
0f0d2c87
MI		 304static void nvme_dbbuf_free(struct nvme_queue *nvmeq)
305{
306 if (!nvmeq->qid)
307 return;
308
309 nvmeq->dbbuf_sq_db = NULL;
310 nvmeq->dbbuf_cq_db = NULL;
311 nvmeq->dbbuf_sq_ei = NULL;
312 nvmeq->dbbuf_cq_ei = NULL;
313}
314
f9f38e33
HK		 315static void nvme_dbbuf_set(struct nvme_dev *dev)
316{
f66e2804 317 struct nvme_command c = { };
0f0d2c87 318 unsigned int i;
f9f38e33
HK		 319
320 if (!dev->dbbuf_dbs)
321 return;
322
f9f38e33
HK		 323 c.dbbuf.opcode = nvme_admin_dbbuf;
324 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
325 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
326
327 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
9bdcfb10 328 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
f9f38e33
HK		 329 /* Free memory and continue on */
330 nvme_dbbuf_dma_free(dev);
0f0d2c87
MI		 331
332 for (i = 1; i <= dev->online_queues; i++)
333 nvme_dbbuf_free(&dev->queues[i]);
f9f38e33
HK		 334 }
335}
336
337static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
338{
339 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
340}
341
342/* Update dbbuf and return true if an MMIO is required */
343static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
344 volatile u32 *dbbuf_ei)
345{
346 if (dbbuf_db) {
347 u16 old_value;
348
349 /*
350 * Ensure that the queue is written before updating
351 * the doorbell in memory
352 */
353 wmb();
354
355 old_value = *dbbuf_db;
356 *dbbuf_db = value;
357
f1ed3df2
MW		 358 /*
359 * Ensure that the doorbell is updated before reading the event
360 * index from memory. The controller needs to provide similar
361 * ordering to ensure the envent index is updated before reading
362 * the doorbell.
363 */
364 mb();
365
f9f38e33
HK		 366 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value))
367 return false;
368 }
369
370 return true;
b60503ba
MW		 371}
372
ac3dd5bd
JA		 373/*
374 * Will slightly overestimate the number of pages needed. This is OK
375 * as it only leads to a small amount of wasted memory for the lifetime of
376 * the I/O.
377 */
b13c6393 378static int nvme_pci_npages_prp(void)
ac3dd5bd 379{
b13c6393 380 unsigned nprps = DIV_ROUND_UP(NVME_MAX_KB_SZ + NVME_CTRL_PAGE_SIZE,
6c3c05b0 381 NVME_CTRL_PAGE_SIZE);
ac3dd5bd
JA		 382 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
383}
384
a7a7cbe3
CK		 385/*
386 * Calculates the number of pages needed for the SGL segments. For example a 4k
387 * page can accommodate 256 SGL descriptors.
388 */
b13c6393 389static int nvme_pci_npages_sgl(void)
ac3dd5bd 390{
b13c6393
CK		 391 return DIV_ROUND_UP(NVME_MAX_SEGS * sizeof(struct nvme_sgl_desc),
392 PAGE_SIZE);
f4800d6d 393}
ac3dd5bd 394
b13c6393 395static size_t nvme_pci_iod_alloc_size(void)
f4800d6d 396{
b13c6393 397 size_t npages = max(nvme_pci_npages_prp(), nvme_pci_npages_sgl());
a7a7cbe3 398
b13c6393
CK		 399 return sizeof(__le64 *) * npages +
400 sizeof(struct scatterlist) * NVME_MAX_SEGS;
f4800d6d 401}
ac3dd5bd 402
a4aea562
MB		 403static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
404 unsigned int hctx_idx)
e85248e5 405{
a4aea562 406 struct nvme_dev *dev = data;
147b27e4 407 struct nvme_queue *nvmeq = &dev->queues[0];
a4aea562 408
42483228
KB		 409 WARN_ON(hctx_idx != 0);
410 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
42483228 411
a4aea562
MB		 412 hctx->driver_data = nvmeq;
413 return 0;
e85248e5
MW		 414}
415
a4aea562
MB		 416static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
417 unsigned int hctx_idx)
b60503ba 418{
a4aea562 419 struct nvme_dev *dev = data;
147b27e4 420 struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
a4aea562 421
42483228 422 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
a4aea562
MB		 423 hctx->driver_data = nvmeq;
424 return 0;
b60503ba
MW		 425}
426
e559398f
CH		 427static int nvme_pci_init_request(struct blk_mq_tag_set *set,
428 struct request *req, unsigned int hctx_idx,
429 unsigned int numa_node)
b60503ba 430{
d6296d39 431 struct nvme_dev *dev = set->driver_data;
f4800d6d 432 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
0350815a 433 int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0;
147b27e4 434 struct nvme_queue *nvmeq = &dev->queues[queue_idx];
a4aea562
MB		 435
436 BUG_ON(!nvmeq);
f4800d6d 437 iod->nvmeq = nvmeq;
59e29ce6
SG		 438
439 nvme_req(req)->ctrl = &dev->ctrl;
f4b9e6c9 440 nvme_req(req)->cmd = &iod->cmd;
a4aea562
MB		 441 return 0;
442}
443
3b6592f7
JA		 444static int queue_irq_offset(struct nvme_dev *dev)
445{
446 /* if we have more than 1 vec, admin queue offsets us by 1 */
447 if (dev->num_vecs > 1)
448 return 1;
449
450 return 0;
451}
452
dca51e78
CH		 453static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
454{
455 struct nvme_dev *dev = set->driver_data;
3b6592f7
JA		 456 int i, qoff, offset;
457
458 offset = queue_irq_offset(dev);
459 for (i = 0, qoff = 0; i < set->nr_maps; i++) {
460 struct blk_mq_queue_map *map = &set->map[i];
461
462 map->nr_queues = dev->io_queues[i];
463 if (!map->nr_queues) {
e20ba6e1 464 BUG_ON(i == HCTX_TYPE_DEFAULT);
7e849dd9 465 continue;
3b6592f7
JA		 466 }
467
4b04cc6a
JA		 468 /*
469 * The poll queue(s) doesn't have an IRQ (and hence IRQ
470 * affinity), so use the regular blk-mq cpu mapping
471 */
3b6592f7 472 map->queue_offset = qoff;
cb9e0e50 473 if (i != HCTX_TYPE_POLL && offset)
4b04cc6a
JA		 474 blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset);
475 else
476 blk_mq_map_queues(map);
3b6592f7
JA		 477 qoff += map->nr_queues;
478 offset += map->nr_queues;
479 }
480
481 return 0;
dca51e78
CH		 482}
483
38210800
KB		 484/*
485 * Write sq tail if we are asked to, or if the next command would wrap.
486 */
487static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq)
04f3eafd 488{
38210800
KB		 489 if (!write_sq) {
490 u16 next_tail = nvmeq->sq_tail + 1;
491
492 if (next_tail == nvmeq->q_depth)
493 next_tail = 0;
494 if (next_tail != nvmeq->last_sq_tail)
495 return;
496 }
497
04f3eafd
JA		 498 if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail,
499 nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei))
500 writel(nvmeq->sq_tail, nvmeq->q_db);
38210800 501 nvmeq->last_sq_tail = nvmeq->sq_tail;
04f3eafd
JA		 502}
503
3233b94c
JA		 504static inline void nvme_sq_copy_cmd(struct nvme_queue *nvmeq,
505 struct nvme_command *cmd)
b60503ba 506{
c1e0cc7e 507 memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes),
3233b94c 508 absolute_pointer(cmd), sizeof(*cmd));
90ea5ca4
CH		 509 if (++nvmeq->sq_tail == nvmeq->q_depth)
510 nvmeq->sq_tail = 0;
04f3eafd
JA		 511}
512
513static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx)
514{
515 struct nvme_queue *nvmeq = hctx->driver_data;
516
517 spin_lock(&nvmeq->sq_lock);
38210800
KB		 518 if (nvmeq->sq_tail != nvmeq->last_sq_tail)
519 nvme_write_sq_db(nvmeq, true);
90ea5ca4 520 spin_unlock(&nvmeq->sq_lock);
b60503ba
MW		 521}
522
a7a7cbe3 523static void **nvme_pci_iod_list(struct request *req)
b60503ba 524{
f4800d6d 525 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3 526 return (void **)(iod->sg + blk_rq_nr_phys_segments(req));
b60503ba
MW		 527}
528
955b1b5a
MI		 529static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req)
530{
531 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
20469a37 532 int nseg = blk_rq_nr_phys_segments(req);
955b1b5a
MI		 533 unsigned int avg_seg_size;
534
20469a37 535 avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
955b1b5a 536
253a0b76 537 if (!nvme_ctrl_sgl_supported(&dev->ctrl))
955b1b5a
MI		 538 return false;
539 if (!iod->nvmeq->qid)
540 return false;
541 if (!sgl_threshold || avg_seg_size < sgl_threshold)
542 return false;
543 return true;
544}
545
9275c206 546static void nvme_free_prps(struct nvme_dev *dev, struct request *req)
b60503ba 547{
6c3c05b0 548 const int last_prp = NVME_CTRL_PAGE_SIZE / sizeof(__le64) - 1;
9275c206
CH		 549 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
550 dma_addr_t dma_addr = iod->first_dma;
eca18b23 551 int i;
eca18b23 552
9275c206
CH		 553 for (i = 0; i < iod->npages; i++) {
554 __le64 *prp_list = nvme_pci_iod_list(req)[i];
555 dma_addr_t next_dma_addr = le64_to_cpu(prp_list[last_prp]);
556
557 dma_pool_free(dev->prp_page_pool, prp_list, dma_addr);
558 dma_addr = next_dma_addr;
7fe07d14 559 }
9275c206 560}
dff824b2 561
9275c206
CH		 562static void nvme_free_sgls(struct nvme_dev *dev, struct request *req)
563{
564 const int last_sg = SGES_PER_PAGE - 1;
565 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
566 dma_addr_t dma_addr = iod->first_dma;
567 int i;
dff824b2 568
9275c206
CH		 569 for (i = 0; i < iod->npages; i++) {
570 struct nvme_sgl_desc *sg_list = nvme_pci_iod_list(req)[i];
571 dma_addr_t next_dma_addr = le64_to_cpu((sg_list[last_sg]).addr);
dff824b2 572
9275c206
CH		 573 dma_pool_free(dev->prp_page_pool, sg_list, dma_addr);
574 dma_addr = next_dma_addr;
575 }
9275c206 576}
a7a7cbe3 577
9275c206
CH		 578static void nvme_unmap_sg(struct nvme_dev *dev, struct request *req)
579{
580 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3 581
9275c206
CH		 582 if (is_pci_p2pdma_page(sg_page(iod->sg)))
583 pci_p2pdma_unmap_sg(dev->dev, iod->sg, iod->nents,
584 rq_dma_dir(req));
585 else
586 dma_unmap_sg(dev->dev, iod->sg, iod->nents, rq_dma_dir(req));
587}
a7a7cbe3 588
9275c206
CH		 589static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
590{
591 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3 592
9275c206
CH		 593 if (iod->dma_len) {
594 dma_unmap_page(dev->dev, iod->first_dma, iod->dma_len,
595 rq_dma_dir(req));
596 return;
eca18b23 597 }
ac3dd5bd 598
9275c206
CH		 599 WARN_ON_ONCE(!iod->nents);
600
601 nvme_unmap_sg(dev, req);
602 if (iod->npages == 0)
603 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0],
604 iod->first_dma);
605 else if (iod->use_sgl)
606 nvme_free_sgls(dev, req);
607 else
608 nvme_free_prps(dev, req);
d43f1ccf 609 mempool_free(iod->sg, dev->iod_mempool);
b4ff9c8d
KB		 610}
611
d0877473
KB		 612static void nvme_print_sgl(struct scatterlist *sgl, int nents)
613{
614 int i;
615 struct scatterlist *sg;
616
617 for_each_sg(sgl, sg, nents, i) {
618 dma_addr_t phys = sg_phys(sg);
619 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
620 "dma_address:%pad dma_length:%d\n",
621 i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
622 sg_dma_len(sg));
623 }
624}
625
a7a7cbe3
CK		 626static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
627 struct request *req, struct nvme_rw_command *cmnd)
ff22b54f 628{
f4800d6d 629 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
99802a7a 630 struct dma_pool *pool;
b131c61d 631 int length = blk_rq_payload_bytes(req);
eca18b23 632 struct scatterlist *sg = iod->sg;
ff22b54f
MW		 633 int dma_len = sg_dma_len(sg);
634 u64 dma_addr = sg_dma_address(sg);
6c3c05b0 635 int offset = dma_addr & (NVME_CTRL_PAGE_SIZE - 1);
e025344c 636 __le64 *prp_list;
a7a7cbe3 637 void **list = nvme_pci_iod_list(req);
e025344c 638 dma_addr_t prp_dma;
eca18b23 639 int nprps, i;
ff22b54f 640
6c3c05b0 641 length -= (NVME_CTRL_PAGE_SIZE - offset);
5228b328
JS		 642 if (length <= 0) {
643 iod->first_dma = 0;
a7a7cbe3 644 goto done;
5228b328 645 }
ff22b54f 646
6c3c05b0 647 dma_len -= (NVME_CTRL_PAGE_SIZE - offset);
ff22b54f 648 if (dma_len) {
6c3c05b0 649 dma_addr += (NVME_CTRL_PAGE_SIZE - offset);
ff22b54f
MW		 650 } else {
651 sg = sg_next(sg);
652 dma_addr = sg_dma_address(sg);
653 dma_len = sg_dma_len(sg);
654 }
655
6c3c05b0 656 if (length <= NVME_CTRL_PAGE_SIZE) {
edd10d33 657 iod->first_dma = dma_addr;
a7a7cbe3 658 goto done;
e025344c
SMM		 659 }
660
6c3c05b0 661 nprps = DIV_ROUND_UP(length, NVME_CTRL_PAGE_SIZE);
99802a7a
MW		 662 if (nprps <= (256 / 8)) {
663 pool = dev->prp_small_pool;
eca18b23 664 iod->npages = 0;
99802a7a
MW		 665 } else {
666 pool = dev->prp_page_pool;
eca18b23 667 iod->npages = 1;
99802a7a
MW		 668 }
669
69d2b571 670 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
b77954cb 671 if (!prp_list) {
edd10d33 672 iod->first_dma = dma_addr;
eca18b23 673 iod->npages = -1;
86eea289 674 return BLK_STS_RESOURCE;
b77954cb 675 }
eca18b23
MW		 676 list[0] = prp_list;
677 iod->first_dma = prp_dma;
e025344c
SMM		 678 i = 0;
679 for (;;) {
6c3c05b0 680 if (i == NVME_CTRL_PAGE_SIZE >> 3) {
e025344c 681 __le64 *old_prp_list = prp_list;
69d2b571 682 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
eca18b23 683 if (!prp_list)
fa073216 684 goto free_prps;
eca18b23 685 list[iod->npages++] = prp_list;
7523d834
MW		 686 prp_list[0] = old_prp_list[i - 1];
687 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
688 i = 1;
e025344c
SMM		 689 }
690 prp_list[i++] = cpu_to_le64(dma_addr);
6c3c05b0
CK		 691 dma_len -= NVME_CTRL_PAGE_SIZE;
692 dma_addr += NVME_CTRL_PAGE_SIZE;
693 length -= NVME_CTRL_PAGE_SIZE;
e025344c
SMM		 694 if (length <= 0)
695 break;
696 if (dma_len > 0)
697 continue;
86eea289
KB		 698 if (unlikely(dma_len < 0))
699 goto bad_sgl;
e025344c
SMM		 700 sg = sg_next(sg);
701 dma_addr = sg_dma_address(sg);
702 dma_len = sg_dma_len(sg);
ff22b54f 703 }
a7a7cbe3
CK		 704done:
705 cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
706 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
86eea289 707 return BLK_STS_OK;
fa073216
CH		 708free_prps:
709 nvme_free_prps(dev, req);
710 return BLK_STS_RESOURCE;
711bad_sgl:
d0877473
KB		 712 WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents),
713 "Invalid SGL for payload:%d nents:%d\n",
714 blk_rq_payload_bytes(req), iod->nents);
86eea289 715 return BLK_STS_IOERR;
ff22b54f
MW		 716}
717
a7a7cbe3
CK		 718static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
719 struct scatterlist *sg)
720{
721 sge->addr = cpu_to_le64(sg_dma_address(sg));
722 sge->length = cpu_to_le32(sg_dma_len(sg));
723 sge->type = NVME_SGL_FMT_DATA_DESC << 4;
724}
725
726static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
727 dma_addr_t dma_addr, int entries)
728{
729 sge->addr = cpu_to_le64(dma_addr);
730 if (entries < SGES_PER_PAGE) {
731 sge->length = cpu_to_le32(entries * sizeof(*sge));
732 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
733 } else {
734 sge->length = cpu_to_le32(PAGE_SIZE);
735 sge->type = NVME_SGL_FMT_SEG_DESC << 4;
736 }
737}
738
739static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
b0f2853b 740 struct request *req, struct nvme_rw_command *cmd, int entries)
a7a7cbe3
CK		 741{
742 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3
CK		 743 struct dma_pool *pool;
744 struct nvme_sgl_desc *sg_list;
745 struct scatterlist *sg = iod->sg;
a7a7cbe3 746 dma_addr_t sgl_dma;
b0f2853b 747 int i = 0;
a7a7cbe3 748
a7a7cbe3
CK		 749 /* setting the transfer type as SGL */
750 cmd->flags = NVME_CMD_SGL_METABUF;
751
b0f2853b 752 if (entries == 1) {
a7a7cbe3
CK		 753 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
754 return BLK_STS_OK;
755 }
756
757 if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
758 pool = dev->prp_small_pool;
759 iod->npages = 0;
760 } else {
761 pool = dev->prp_page_pool;
762 iod->npages = 1;
763 }
764
765 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
766 if (!sg_list) {
767 iod->npages = -1;
768 return BLK_STS_RESOURCE;
769 }
770
771 nvme_pci_iod_list(req)[0] = sg_list;
772 iod->first_dma = sgl_dma;
773
774 nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
775
776 do {
777 if (i == SGES_PER_PAGE) {
778 struct nvme_sgl_desc *old_sg_desc = sg_list;
779 struct nvme_sgl_desc *link = &old_sg_desc[i - 1];
780
781 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
782 if (!sg_list)
fa073216 783 goto free_sgls;
a7a7cbe3
CK		 784
785 i = 0;
786 nvme_pci_iod_list(req)[iod->npages++] = sg_list;
787 sg_list[i++] = *link;
788 nvme_pci_sgl_set_seg(link, sgl_dma, entries);
789 }
790
791 nvme_pci_sgl_set_data(&sg_list[i++], sg);
a7a7cbe3 792 sg = sg_next(sg);
b0f2853b 793 } while (--entries > 0);
a7a7cbe3 794
a7a7cbe3 795 return BLK_STS_OK;
fa073216
CH		 796free_sgls:
797 nvme_free_sgls(dev, req);
798 return BLK_STS_RESOURCE;
a7a7cbe3
CK		 799}
800
dff824b2
CH		 801static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev,
802 struct request *req, struct nvme_rw_command *cmnd,
803 struct bio_vec *bv)
804{
805 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
6c3c05b0
CK		 806 unsigned int offset = bv->bv_offset & (NVME_CTRL_PAGE_SIZE - 1);
807 unsigned int first_prp_len = NVME_CTRL_PAGE_SIZE - offset;
dff824b2
CH		 808
809 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
810 if (dma_mapping_error(dev->dev, iod->first_dma))
811 return BLK_STS_RESOURCE;
812 iod->dma_len = bv->bv_len;
813
814 cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma);
815 if (bv->bv_len > first_prp_len)
816 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len);
359c1f88 817 return BLK_STS_OK;
dff824b2
CH		 818}
819
29791057
CH		 820static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev,
821 struct request *req, struct nvme_rw_command *cmnd,
822 struct bio_vec *bv)
823{
824 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
825
826 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
827 if (dma_mapping_error(dev->dev, iod->first_dma))
828 return BLK_STS_RESOURCE;
829 iod->dma_len = bv->bv_len;
830
049bf372 831 cmnd->flags = NVME_CMD_SGL_METABUF;
29791057
CH		 832 cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma);
833 cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len);
834 cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4;
359c1f88 835 return BLK_STS_OK;
29791057
CH		 836}
837
fc17b653 838static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
b131c61d 839 struct nvme_command *cmnd)
d29ec824 840{
f4800d6d 841 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
70479b71 842 blk_status_t ret = BLK_STS_RESOURCE;
b0f2853b 843 int nr_mapped;
d29ec824 844
dff824b2
CH		 845 if (blk_rq_nr_phys_segments(req) == 1) {
846 struct bio_vec bv = req_bvec(req);
847
848 if (!is_pci_p2pdma_page(bv.bv_page)) {
6c3c05b0 849 if (bv.bv_offset + bv.bv_len <= NVME_CTRL_PAGE_SIZE * 2)
dff824b2
CH		 850 return nvme_setup_prp_simple(dev, req,
851 &cmnd->rw, &bv);
29791057 852
e51183be 853 if (iod->nvmeq->qid && sgl_threshold &&
253a0b76 854 nvme_ctrl_sgl_supported(&dev->ctrl))
29791057
CH		 855 return nvme_setup_sgl_simple(dev, req,
856 &cmnd->rw, &bv);
dff824b2
CH		 857 }
858 }
859
860 iod->dma_len = 0;
d43f1ccf
CH		 861 iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC);
862 if (!iod->sg)
863 return BLK_STS_RESOURCE;
f9d03f96 864 sg_init_table(iod->sg, blk_rq_nr_phys_segments(req));
70479b71 865 iod->nents = blk_rq_map_sg(req->q, req, iod->sg);
ba1ca37e 866 if (!iod->nents)
fa073216 867 goto out_free_sg;
d29ec824 868
e0596ab2 869 if (is_pci_p2pdma_page(sg_page(iod->sg)))
2b9f4bb2
LG		 870 nr_mapped = pci_p2pdma_map_sg_attrs(dev->dev, iod->sg,
871 iod->nents, rq_dma_dir(req), DMA_ATTR_NO_WARN);
e0596ab2
LG		 872 else
873 nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents,
70479b71 874 rq_dma_dir(req), DMA_ATTR_NO_WARN);
b0f2853b 875 if (!nr_mapped)
fa073216 876 goto out_free_sg;
d29ec824 877
70479b71 878 iod->use_sgl = nvme_pci_use_sgls(dev, req);
955b1b5a 879 if (iod->use_sgl)
b0f2853b 880 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped);
a7a7cbe3
CK		 881 else
882 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
86eea289 883 if (ret != BLK_STS_OK)
fa073216
CH		 884 goto out_unmap_sg;
885 return BLK_STS_OK;
886
887out_unmap_sg:
888 nvme_unmap_sg(dev, req);
889out_free_sg:
890 mempool_free(iod->sg, dev->iod_mempool);
4aedb705
CH		 891 return ret;
892}
3045c0d0 893
4aedb705
CH		 894static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req,
895 struct nvme_command *cmnd)
896{
897 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
00df5cb4 898
4aedb705
CH		 899 iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req),
900 rq_dma_dir(req), 0);
901 if (dma_mapping_error(dev->dev, iod->meta_dma))
902 return BLK_STS_IOERR;
903 cmnd->rw.metadata = cpu_to_le64(iod->meta_dma);
359c1f88 904 return BLK_STS_OK;
00df5cb4
MW		 905}
906
62451a2b 907static blk_status_t nvme_prep_rq(struct nvme_dev *dev, struct request *req)
edd10d33 908{
9b048119 909 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
ebe6d874 910 blk_status_t ret;
e1e5e564 911
9b048119
CH		 912 iod->aborted = 0;
913 iod->npages = -1;
914 iod->nents = 0;
915
62451a2b 916 ret = nvme_setup_cmd(req->q->queuedata, req);
fc17b653 917 if (ret)
f4800d6d 918 return ret;
a4aea562 919
fc17b653 920 if (blk_rq_nr_phys_segments(req)) {
62451a2b 921 ret = nvme_map_data(dev, req, &iod->cmd);
fc17b653 922 if (ret)
9b048119 923 goto out_free_cmd;
fc17b653 924 }
a4aea562 925
4aedb705 926 if (blk_integrity_rq(req)) {
62451a2b 927 ret = nvme_map_metadata(dev, req, &iod->cmd);
4aedb705
CH		 928 if (ret)
929 goto out_unmap_data;
930 }
931
aae239e1 932 blk_mq_start_request(req);
fc17b653 933 return BLK_STS_OK;
4aedb705
CH		 934out_unmap_data:
935 nvme_unmap_data(dev, req);
f9d03f96
CH		 936out_free_cmd:
937 nvme_cleanup_cmd(req);
ba1ca37e 938 return ret;
b60503ba 939}
e1e5e564 940
62451a2b
JA		 941/*
942 * NOTE: ns is NULL when called on the admin queue.
943 */
944static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
945 const struct blk_mq_queue_data *bd)
946{
947 struct nvme_queue *nvmeq = hctx->driver_data;
948 struct nvme_dev *dev = nvmeq->dev;
949 struct request *req = bd->rq;
950 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
951 blk_status_t ret;
952
953 /*
954 * We should not need to do this, but we're still using this to
955 * ensure we can drain requests on a dying queue.
956 */
957 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
958 return BLK_STS_IOERR;
959
960 if (unlikely(!nvme_check_ready(&dev->ctrl, req, true)))
961 return nvme_fail_nonready_command(&dev->ctrl, req);
962
963 ret = nvme_prep_rq(dev, req);
964 if (unlikely(ret))
965 return ret;
966 spin_lock(&nvmeq->sq_lock);
967 nvme_sq_copy_cmd(nvmeq, &iod->cmd);
968 nvme_write_sq_db(nvmeq, bd->last);
969 spin_unlock(&nvmeq->sq_lock);
970 return BLK_STS_OK;
971}
972
d62cbcf6
JA		 973static void nvme_submit_cmds(struct nvme_queue *nvmeq, struct request **rqlist)
974{
975 spin_lock(&nvmeq->sq_lock);
976 while (!rq_list_empty(*rqlist)) {
977 struct request *req = rq_list_pop(rqlist);
978 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
979
980 nvme_sq_copy_cmd(nvmeq, &iod->cmd);
981 }
982 nvme_write_sq_db(nvmeq, true);
983 spin_unlock(&nvmeq->sq_lock);
984}
985
986static bool nvme_prep_rq_batch(struct nvme_queue *nvmeq, struct request *req)
987{
988 /*
989 * We should not need to do this, but we're still using this to
990 * ensure we can drain requests on a dying queue.
991 */
992 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
993 return false;
994 if (unlikely(!nvme_check_ready(&nvmeq->dev->ctrl, req, true)))
995 return false;
996
997 req->mq_hctx->tags->rqs[req->tag] = req;
998 return nvme_prep_rq(nvmeq->dev, req) == BLK_STS_OK;
999}
1000
1001static void nvme_queue_rqs(struct request **rqlist)
1002{
6bfec799 1003 struct request *req, *next, *prev = NULL;
d62cbcf6
JA		 1004 struct request *requeue_list = NULL;
1005
6bfec799 1006 rq_list_for_each_safe(rqlist, req, next) {
d62cbcf6
JA		 1007 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
1008
1009 if (!nvme_prep_rq_batch(nvmeq, req)) {
1010 /* detach 'req' and add to remainder list */
6bfec799
KB		 1011 rq_list_move(rqlist, &requeue_list, req, prev);
1012
1013 req = prev;
1014 if (!req)
1015 continue;
d62cbcf6
JA		 1016 }
1017
6bfec799 1018 if (!next || req->mq_hctx != next->mq_hctx) {
d62cbcf6 1019 /* detach rest of list, and submit */
6bfec799 1020 req->rq_next = NULL;
d62cbcf6 1021 nvme_submit_cmds(nvmeq, rqlist);
6bfec799
KB		 1022 *rqlist = next;
1023 prev = NULL;
1024 } else
1025 prev = req;
1026 }
d62cbcf6
JA		 1027
1028 *rqlist = requeue_list;
1029}
1030
c234a653 1031static __always_inline void nvme_pci_unmap_rq(struct request *req)
eee417b0 1032{
f4800d6d 1033 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
4aedb705 1034 struct nvme_dev *dev = iod->nvmeq->dev;
a4aea562 1035
4aedb705
CH		 1036 if (blk_integrity_rq(req))
1037 dma_unmap_page(dev->dev, iod->meta_dma,
1038 rq_integrity_vec(req)->bv_len, rq_data_dir(req));
b15c592d 1039 if (blk_rq_nr_phys_segments(req))
4aedb705 1040 nvme_unmap_data(dev, req);
c234a653
JA		 1041}
1042
1043static void nvme_pci_complete_rq(struct request *req)
1044{
1045 nvme_pci_unmap_rq(req);
77f02a7a 1046 nvme_complete_rq(req);
b60503ba
MW		 1047}
1048
c234a653
JA		 1049static void nvme_pci_complete_batch(struct io_comp_batch *iob)
1050{
1051 nvme_complete_batch(iob, nvme_pci_unmap_rq);
1052}
1053
d783e0bd 1054/* We read the CQE phase first to check if the rest of the entry is valid */
750dde44 1055static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq)
d783e0bd 1056{
74943d45
KB		 1057 struct nvme_completion *hcqe = &nvmeq->cqes[nvmeq->cq_head];
1058
1059 return (le16_to_cpu(READ_ONCE(hcqe->status)) & 1) == nvmeq->cq_phase;
d783e0bd
MR		 1060}
1061
eb281c82 1062static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
b60503ba 1063{
eb281c82 1064 u16 head = nvmeq->cq_head;
adf68f21 1065
397c699f
KB		 1066 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
1067 nvmeq->dbbuf_cq_ei))
1068 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
eb281c82 1069}
aae239e1 1070
cfa27356
CH		 1071static inline struct blk_mq_tags *nvme_queue_tagset(struct nvme_queue *nvmeq)
1072{
1073 if (!nvmeq->qid)
1074 return nvmeq->dev->admin_tagset.tags[0];
1075 return nvmeq->dev->tagset.tags[nvmeq->qid - 1];
1076}
1077
c234a653
JA		 1078static inline void nvme_handle_cqe(struct nvme_queue *nvmeq,
1079 struct io_comp_batch *iob, u16 idx)
83a12fb7 1080{
74943d45 1081 struct nvme_completion *cqe = &nvmeq->cqes[idx];
62df8016 1082 __u16 command_id = READ_ONCE(cqe->command_id);
83a12fb7 1083 struct request *req;
adf68f21 1084
83a12fb7
SG		 1085 /*
1086 * AEN requests are special as they don't time out and can
1087 * survive any kind of queue freeze and often don't respond to
1088 * aborts. We don't even bother to allocate a struct request
1089 * for them but rather special case them here.
1090 */
62df8016 1091 if (unlikely(nvme_is_aen_req(nvmeq->qid, command_id))) {
83a12fb7
SG		 1092 nvme_complete_async_event(&nvmeq->dev->ctrl,
1093 cqe->status, &cqe->result);
a0fa9647 1094 return;
83a12fb7 1095 }
b60503ba 1096
e7006de6 1097 req = nvme_find_rq(nvme_queue_tagset(nvmeq), command_id);
50b7c243
XT		 1098 if (unlikely(!req)) {
1099 dev_warn(nvmeq->dev->ctrl.device,
1100 "invalid id %d completed on queue %d\n",
62df8016 1101 command_id, le16_to_cpu(cqe->sq_id));
50b7c243
XT		 1102 return;
1103 }
1104
604c01d5 1105 trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail);
c234a653
JA		 1106 if (!nvme_try_complete_req(req, cqe->status, cqe->result) &&
1107 !blk_mq_add_to_batch(req, iob, nvme_req(req)->status,
1108 nvme_pci_complete_batch))
ff029451 1109 nvme_pci_complete_rq(req);
83a12fb7 1110}
b60503ba 1111
5cb525c8
JA		 1112static inline void nvme_update_cq_head(struct nvme_queue *nvmeq)
1113{
a0aac973 1114 u32 tmp = nvmeq->cq_head + 1;
a8de6639
AD		 1115
1116 if (tmp == nvmeq->q_depth) {
5cb525c8 1117 nvmeq->cq_head = 0;
e2a366a4 1118 nvmeq->cq_phase ^= 1;
a8de6639
AD		 1119 } else {
1120 nvmeq->cq_head = tmp;
b60503ba 1121 }
a0fa9647
JA		 1122}
1123
c234a653
JA		 1124static inline int nvme_poll_cq(struct nvme_queue *nvmeq,
1125 struct io_comp_batch *iob)
a0fa9647 1126{
1052b8ac 1127 int found = 0;
b60503ba 1128
1052b8ac 1129 while (nvme_cqe_pending(nvmeq)) {
bf392a5d 1130 found++;
b69e2ef2
KB		 1131 /*
1132 * load-load control dependency between phase and the rest of
1133 * the cqe requires a full read memory barrier
1134 */
1135 dma_rmb();
c234a653 1136 nvme_handle_cqe(nvmeq, iob, nvmeq->cq_head);
5cb525c8 1137 nvme_update_cq_head(nvmeq);
920d13a8 1138 }
eb281c82 1139
324b494c 1140 if (found)
920d13a8 1141 nvme_ring_cq_doorbell(nvmeq);
5cb525c8 1142 return found;
b60503ba
MW		 1143}
1144
1145static irqreturn_t nvme_irq(int irq, void *data)
58ffacb5 1146{
58ffacb5 1147 struct nvme_queue *nvmeq = data;
4f502245 1148 DEFINE_IO_COMP_BATCH(iob);
5cb525c8 1149
4f502245
JA		 1150 if (nvme_poll_cq(nvmeq, &iob)) {
1151 if (!rq_list_empty(iob.req_list))
1152 nvme_pci_complete_batch(&iob);
05fae499 1153 return IRQ_HANDLED;
4f502245 1154 }
05fae499 1155 return IRQ_NONE;
58ffacb5
MW		 1156}
1157
1158static irqreturn_t nvme_irq_check(int irq, void *data)
1159{
1160 struct nvme_queue *nvmeq = data;
4e523547 1161
750dde44 1162 if (nvme_cqe_pending(nvmeq))
d783e0bd
MR		 1163 return IRQ_WAKE_THREAD;
1164 return IRQ_NONE;
58ffacb5
MW		 1165}
1166
0b2a8a9f 1167/*
fa059b85 1168 * Poll for completions for any interrupt driven queue
0b2a8a9f
CH		 1169 * Can be called from any context.
1170 */
fa059b85 1171static void nvme_poll_irqdisable(struct nvme_queue *nvmeq)
a0fa9647 1172{
3a7afd8e 1173 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
a0fa9647 1174
fa059b85 1175 WARN_ON_ONCE(test_bit(NVMEQ_POLLED, &nvmeq->flags));
442e19b7 1176
fa059b85 1177 disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
c234a653 1178 nvme_poll_cq(nvmeq, NULL);
fa059b85 1179 enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
a0fa9647
JA		 1180}
1181
5a72e899 1182static int nvme_poll(struct blk_mq_hw_ctx *hctx, struct io_comp_batch *iob)
dabcefab
JA		 1183{
1184 struct nvme_queue *nvmeq = hctx->driver_data;
dabcefab
JA		 1185 bool found;
1186
1187 if (!nvme_cqe_pending(nvmeq))
1188 return 0;
1189
3a7afd8e 1190 spin_lock(&nvmeq->cq_poll_lock);
c234a653 1191 found = nvme_poll_cq(nvmeq, iob);
3a7afd8e 1192 spin_unlock(&nvmeq->cq_poll_lock);
dabcefab 1193
dabcefab
JA		 1194 return found;
1195}
1196
ad22c355 1197static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
b60503ba 1198{
f866fc42 1199 struct nvme_dev *dev = to_nvme_dev(ctrl);
147b27e4 1200 struct nvme_queue *nvmeq = &dev->queues[0];
f66e2804 1201 struct nvme_command c = { };
b60503ba 1202
a4aea562 1203 c.common.opcode = nvme_admin_async_event;
ad22c355 1204 c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
3233b94c
JA		 1205
1206 spin_lock(&nvmeq->sq_lock);
1207 nvme_sq_copy_cmd(nvmeq, &c);
1208 nvme_write_sq_db(nvmeq, true);
1209 spin_unlock(&nvmeq->sq_lock);
f705f837
CH		 1210}
1211
b60503ba 1212static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
f705f837 1213{
f66e2804 1214 struct nvme_command c = { };
b60503ba 1215
b60503ba
MW		 1216 c.delete_queue.opcode = opcode;
1217 c.delete_queue.qid = cpu_to_le16(id);
1218
1c63dc66 1219 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1220}
1221
b60503ba 1222static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
a8e3e0bb 1223 struct nvme_queue *nvmeq, s16 vector)
b60503ba 1224{
f66e2804 1225 struct nvme_command c = { };
4b04cc6a
JA		 1226 int flags = NVME_QUEUE_PHYS_CONTIG;
1227
7c349dde 1228 if (!test_bit(NVMEQ_POLLED, &nvmeq->flags))
4b04cc6a 1229 flags |= NVME_CQ_IRQ_ENABLED;
b60503ba 1230
d29ec824 1231 /*
16772ae6 1232 * Note: we (ab)use the fact that the prp fields survive if no data
d29ec824
CH		 1233 * is attached to the request.
1234 */
b60503ba
MW		 1235 c.create_cq.opcode = nvme_admin_create_cq;
1236 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1237 c.create_cq.cqid = cpu_to_le16(qid);
1238 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1239 c.create_cq.cq_flags = cpu_to_le16(flags);
7c349dde 1240 c.create_cq.irq_vector = cpu_to_le16(vector);
b60503ba 1241
1c63dc66 1242 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1243}
1244
1245static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1246 struct nvme_queue *nvmeq)
1247{
9abd68ef 1248 struct nvme_ctrl *ctrl = &dev->ctrl;
f66e2804 1249 struct nvme_command c = { };
81c1cd98 1250 int flags = NVME_QUEUE_PHYS_CONTIG;
b60503ba 1251
9abd68ef
JA		 1252 /*
1253 * Some drives have a bug that auto-enables WRRU if MEDIUM isn't
1254 * set. Since URGENT priority is zeroes, it makes all queues
1255 * URGENT.
1256 */
1257 if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ)
1258 flags |= NVME_SQ_PRIO_MEDIUM;
1259
d29ec824 1260 /*
16772ae6 1261 * Note: we (ab)use the fact that the prp fields survive if no data
d29ec824
CH		 1262 * is attached to the request.
1263 */
b60503ba
MW		 1264 c.create_sq.opcode = nvme_admin_create_sq;
1265 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1266 c.create_sq.sqid = cpu_to_le16(qid);
1267 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1268 c.create_sq.sq_flags = cpu_to_le16(flags);
1269 c.create_sq.cqid = cpu_to_le16(qid);
1270
1c63dc66 1271 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1272}
1273
1274static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1275{
1276 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1277}
1278
1279static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1280{
1281 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1282}
1283
2a842aca 1284static void abort_endio(struct request *req, blk_status_t error)
bc5fc7e4 1285{
f4800d6d
CH		 1286 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1287 struct nvme_queue *nvmeq = iod->nvmeq;
e44ac588 1288
27fa9bc5
CH		 1289 dev_warn(nvmeq->dev->ctrl.device,
1290 "Abort status: 0x%x", nvme_req(req)->status);
e7a2a87d 1291 atomic_inc(&nvmeq->dev->ctrl.abort_limit);
e7a2a87d 1292 blk_mq_free_request(req);
bc5fc7e4
MW		 1293}
1294
b2a0eb1a
KB		 1295static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1296{
b2a0eb1a
KB		 1297 /* If true, indicates loss of adapter communication, possibly by a
1298 * NVMe Subsystem reset.
1299 */
1300 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1301
ad70062c
JW		 1302 /* If there is a reset/reinit ongoing, we shouldn't reset again. */
1303 switch (dev->ctrl.state) {
1304 case NVME_CTRL_RESETTING:
ad6a0a52 1305 case NVME_CTRL_CONNECTING:
b2a0eb1a 1306 return false;
ad70062c
JW		 1307 default:
1308 break;
1309 }
b2a0eb1a
KB		 1310
1311 /* We shouldn't reset unless the controller is on fatal error state
1312 * _or_ if we lost the communication with it.
1313 */
1314 if (!(csts & NVME_CSTS_CFS) && !nssro)
1315 return false;
1316
b2a0eb1a
KB		 1317 return true;
1318}
1319
1320static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1321{
1322 /* Read a config register to help see what died. */
1323 u16 pci_status;
1324 int result;
1325
1326 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1327 &pci_status);
1328 if (result == PCIBIOS_SUCCESSFUL)
1329 dev_warn(dev->ctrl.device,
1330 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1331 csts, pci_status);
1332 else
1333 dev_warn(dev->ctrl.device,
1334 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1335 csts, result);
1336}
1337
31c7c7d2 1338static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
c30341dc 1339{
f4800d6d
CH		 1340 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1341 struct nvme_queue *nvmeq = iod->nvmeq;
c30341dc 1342 struct nvme_dev *dev = nvmeq->dev;
a4aea562 1343 struct request *abort_req;
f66e2804 1344 struct nvme_command cmd = { };
b2a0eb1a
KB		 1345 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1346
651438bb
WX		 1347 /* If PCI error recovery process is happening, we cannot reset or
1348 * the recovery mechanism will surely fail.
1349 */
1350 mb();
1351 if (pci_channel_offline(to_pci_dev(dev->dev)))
1352 return BLK_EH_RESET_TIMER;
1353
b2a0eb1a
KB		 1354 /*
1355 * Reset immediately if the controller is failed
1356 */
1357 if (nvme_should_reset(dev, csts)) {
1358 nvme_warn_reset(dev, csts);
1359 nvme_dev_disable(dev, false);
d86c4d8e 1360 nvme_reset_ctrl(&dev->ctrl);
db8c48e4 1361 return BLK_EH_DONE;
b2a0eb1a 1362 }
c30341dc 1363
7776db1c
KB		 1364 /*
1365 * Did we miss an interrupt?
1366 */
fa059b85 1367 if (test_bit(NVMEQ_POLLED, &nvmeq->flags))
5a72e899 1368 nvme_poll(req->mq_hctx, NULL);
fa059b85
KB		 1369 else
1370 nvme_poll_irqdisable(nvmeq);
1371
bf392a5d 1372 if (blk_mq_request_completed(req)) {
7776db1c
KB		 1373 dev_warn(dev->ctrl.device,
1374 "I/O %d QID %d timeout, completion polled\n",
1375 req->tag, nvmeq->qid);
db8c48e4 1376 return BLK_EH_DONE;
7776db1c
KB		 1377 }
1378
31c7c7d2 1379 /*
fd634f41
CH		 1380 * Shutdown immediately if controller times out while starting. The
1381 * reset work will see the pci device disabled when it gets the forced
1382 * cancellation error. All outstanding requests are completed on
db8c48e4 1383 * shutdown, so we return BLK_EH_DONE.
fd634f41 1384 */
4244140d
KB		 1385 switch (dev->ctrl.state) {
1386 case NVME_CTRL_CONNECTING:
2036f726 1387 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
df561f66 1388 fallthrough;
2036f726 1389 case NVME_CTRL_DELETING:
b9cac43c 1390 dev_warn_ratelimited(dev->ctrl.device,
fd634f41
CH		 1391 "I/O %d QID %d timeout, disable controller\n",
1392 req->tag, nvmeq->qid);
27fa9bc5 1393 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
7ad92f65 1394 nvme_dev_disable(dev, true);
db8c48e4 1395 return BLK_EH_DONE;
39a9dd81
KB		 1396 case NVME_CTRL_RESETTING:
1397 return BLK_EH_RESET_TIMER;
4244140d
KB		 1398 default:
1399 break;
c30341dc
KB		 1400 }
1401
fd634f41 1402 /*
ee0d96d3
BW		 1403 * Shutdown the controller immediately and schedule a reset if the
1404 * command was already aborted once before and still hasn't been
1405 * returned to the driver, or if this is the admin queue.
31c7c7d2 1406 */
f4800d6d 1407 if (!nvmeq->qid || iod->aborted) {
1b3c47c1 1408 dev_warn(dev->ctrl.device,
e1569a16
KB		 1409 "I/O %d QID %d timeout, reset controller\n",
1410 req->tag, nvmeq->qid);
7ad92f65 1411 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
a5cdb68c 1412 nvme_dev_disable(dev, false);
d86c4d8e 1413 nvme_reset_ctrl(&dev->ctrl);
c30341dc 1414
db8c48e4 1415 return BLK_EH_DONE;
c30341dc 1416 }
c30341dc 1417
e7a2a87d 1418 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
6bf25d16 1419 atomic_inc(&dev->ctrl.abort_limit);
31c7c7d2 1420 return BLK_EH_RESET_TIMER;
6bf25d16 1421 }
7bf7d778 1422 iod->aborted = 1;
a4aea562 1423
c30341dc 1424 cmd.abort.opcode = nvme_admin_abort_cmd;
85f74acf 1425 cmd.abort.cid = nvme_cid(req);
c30341dc 1426 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
c30341dc 1427
1b3c47c1
SG		 1428 dev_warn(nvmeq->dev->ctrl.device,
1429 "I/O %d QID %d timeout, aborting\n",
1430 req->tag, nvmeq->qid);
e7a2a87d 1431
e559398f
CH		 1432 abort_req = blk_mq_alloc_request(dev->ctrl.admin_q, nvme_req_op(&cmd),
1433 BLK_MQ_REQ_NOWAIT);
e7a2a87d
CH		 1434 if (IS_ERR(abort_req)) {
1435 atomic_inc(&dev->ctrl.abort_limit);
1436 return BLK_EH_RESET_TIMER;
1437 }
e559398f 1438 nvme_init_request(abort_req, &cmd);
e7a2a87d 1439
e7a2a87d 1440 abort_req->end_io_data = NULL;
b84ba30b 1441 blk_execute_rq_nowait(abort_req, false, abort_endio);
c30341dc 1442
31c7c7d2
CH		 1443 /*
1444 * The aborted req will be completed on receiving the abort req.
1445 * We enable the timer again. If hit twice, it'll cause a device reset,
1446 * as the device then is in a faulty state.
1447 */
1448 return BLK_EH_RESET_TIMER;
c30341dc
KB		 1449}
1450
a4aea562
MB		 1451static void nvme_free_queue(struct nvme_queue *nvmeq)
1452{
8a1d09a6 1453 dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq),
9e866774 1454 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
63223078
CH		 1455 if (!nvmeq->sq_cmds)
1456 return;
0f238ff5 1457
63223078 1458 if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) {
88a041f4 1459 pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev),
8a1d09a6 1460 nvmeq->sq_cmds, SQ_SIZE(nvmeq));
63223078 1461 } else {
8a1d09a6 1462 dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq),
63223078 1463 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
0f238ff5 1464 }
9e866774
MW		 1465}
1466
a1a5ef99 1467static void nvme_free_queues(struct nvme_dev *dev, int lowest)
22404274
KB		 1468{
1469 int i;
1470
d858e5f0 1471 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
d858e5f0 1472 dev->ctrl.queue_count--;
147b27e4 1473 nvme_free_queue(&dev->queues[i]);
121c7ad4 1474 }
22404274
KB		 1475}
1476
4d115420
KB		 1477/**
1478 * nvme_suspend_queue - put queue into suspended state
40581d1a 1479 * @nvmeq: queue to suspend
4d115420
KB		 1480 */
1481static int nvme_suspend_queue(struct nvme_queue *nvmeq)
b60503ba 1482{
4e224106 1483 if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags))
2b25d981 1484 return 1;
a09115b2 1485
4e224106 1486 /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */
d1f06f4a 1487 mb();
a09115b2 1488
4e224106 1489 nvmeq->dev->online_queues--;
1c63dc66 1490 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
6ca1d902 1491 nvme_stop_admin_queue(&nvmeq->dev->ctrl);
7c349dde
KB		 1492 if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags))
1493 pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq);
4d115420
KB		 1494 return 0;
1495}
b60503ba 1496
8fae268b
KB		 1497static void nvme_suspend_io_queues(struct nvme_dev *dev)
1498{
1499 int i;
1500
1501 for (i = dev->ctrl.queue_count - 1; i > 0; i--)
1502 nvme_suspend_queue(&dev->queues[i]);
1503}
1504
a5cdb68c 1505static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
4d115420 1506{
147b27e4 1507 struct nvme_queue *nvmeq = &dev->queues[0];
4d115420 1508
a5cdb68c
KB		 1509 if (shutdown)
1510 nvme_shutdown_ctrl(&dev->ctrl);
1511 else
b5b05048 1512 nvme_disable_ctrl(&dev->ctrl);
07836e65 1513
bf392a5d 1514 nvme_poll_irqdisable(nvmeq);
b60503ba
MW		 1515}
1516
fa46c6fb
KB		 1517/*
1518 * Called only on a device that has been disabled and after all other threads
9210c075
DZ		 1519 * that can check this device's completion queues have synced, except
1520 * nvme_poll(). This is the last chance for the driver to see a natural
1521 * completion before nvme_cancel_request() terminates all incomplete requests.
fa46c6fb
KB		 1522 */
1523static void nvme_reap_pending_cqes(struct nvme_dev *dev)
1524{
fa46c6fb
KB		 1525 int i;
1526
9210c075
DZ		 1527 for (i = dev->ctrl.queue_count - 1; i > 0; i--) {
1528 spin_lock(&dev->queues[i].cq_poll_lock);
c234a653 1529 nvme_poll_cq(&dev->queues[i], NULL);
9210c075
DZ		 1530 spin_unlock(&dev->queues[i].cq_poll_lock);
1531 }
fa46c6fb
KB		 1532}
1533
8ffaadf7
JD		 1534static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1535 int entry_size)
1536{
1537 int q_depth = dev->q_depth;
5fd4ce1b 1538 unsigned q_size_aligned = roundup(q_depth * entry_size,
6c3c05b0 1539 NVME_CTRL_PAGE_SIZE);
8ffaadf7
JD		 1540
1541 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
c45f5c99 1542 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
4e523547 1543
6c3c05b0 1544 mem_per_q = round_down(mem_per_q, NVME_CTRL_PAGE_SIZE);
c45f5c99 1545 q_depth = div_u64(mem_per_q, entry_size);
8ffaadf7
JD		 1546
1547 /*
1548 * Ensure the reduced q_depth is above some threshold where it
1549 * would be better to map queues in system memory with the
1550 * original depth
1551 */
1552 if (q_depth < 64)
1553 return -ENOMEM;
1554 }
1555
1556 return q_depth;
1557}
1558
1559static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
8a1d09a6 1560 int qid)
8ffaadf7 1561{
0f238ff5
LG		 1562 struct pci_dev *pdev = to_pci_dev(dev->dev);
1563
1564 if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
8a1d09a6 1565 nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq));
bfac8e9f
AM		 1566 if (nvmeq->sq_cmds) {
1567 nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev,
1568 nvmeq->sq_cmds);
1569 if (nvmeq->sq_dma_addr) {
1570 set_bit(NVMEQ_SQ_CMB, &nvmeq->flags);
1571 return 0;
1572 }
1573
8a1d09a6 1574 pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq));
63223078 1575 }
0f238ff5 1576 }
8ffaadf7 1577
8a1d09a6 1578 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq),
63223078 1579 &nvmeq->sq_dma_addr, GFP_KERNEL);
815c6704
KB		 1580 if (!nvmeq->sq_cmds)
1581 return -ENOMEM;
8ffaadf7
JD		 1582 return 0;
1583}
1584
a6ff7262 1585static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
b60503ba 1586{
147b27e4 1587 struct nvme_queue *nvmeq = &dev->queues[qid];
b60503ba 1588
62314e40
KB		 1589 if (dev->ctrl.queue_count > qid)
1590 return 0;
b60503ba 1591
c1e0cc7e 1592 nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES;
8a1d09a6
BH		 1593 nvmeq->q_depth = depth;
1594 nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq),
750afb08 1595 &nvmeq->cq_dma_addr, GFP_KERNEL);
b60503ba
MW		 1596 if (!nvmeq->cqes)
1597 goto free_nvmeq;
b60503ba 1598
8a1d09a6 1599 if (nvme_alloc_sq_cmds(dev, nvmeq, qid))
b60503ba
MW		 1600 goto free_cqdma;
1601
091b6092 1602 nvmeq->dev = dev;
1ab0cd69 1603 spin_lock_init(&nvmeq->sq_lock);
3a7afd8e 1604 spin_lock_init(&nvmeq->cq_poll_lock);
b60503ba 1605 nvmeq->cq_head = 0;
82123460 1606 nvmeq->cq_phase = 1;
b80d5ccc 1607 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
c30341dc 1608 nvmeq->qid = qid;
d858e5f0 1609 dev->ctrl.queue_count++;
36a7e993 1610
147b27e4 1611 return 0;
b60503ba
MW		 1612
1613 free_cqdma:
8a1d09a6
BH		 1614 dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes,
1615 nvmeq->cq_dma_addr);
b60503ba 1616 free_nvmeq:
147b27e4 1617 return -ENOMEM;
b60503ba
MW		 1618}
1619
dca51e78 1620static int queue_request_irq(struct nvme_queue *nvmeq)
3001082c 1621{
0ff199cb
CH		 1622 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1623 int nr = nvmeq->dev->ctrl.instance;
1624
1625 if (use_threaded_interrupts) {
1626 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1627 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1628 } else {
1629 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1630 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1631 }
3001082c
MW		 1632}
1633
22404274 1634static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
b60503ba 1635{
22404274 1636 struct nvme_dev *dev = nvmeq->dev;
b60503ba 1637
22404274 1638 nvmeq->sq_tail = 0;
38210800 1639 nvmeq->last_sq_tail = 0;
22404274
KB		 1640 nvmeq->cq_head = 0;
1641 nvmeq->cq_phase = 1;
b80d5ccc 1642 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
8a1d09a6 1643 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq));
f9f38e33 1644 nvme_dbbuf_init(dev, nvmeq, qid);
42f61420 1645 dev->online_queues++;
3a7afd8e 1646 wmb(); /* ensure the first interrupt sees the initialization */
22404274
KB		 1647}
1648
e4b9852a
CC		 1649/*
1650 * Try getting shutdown_lock while setting up IO queues.
1651 */
1652static int nvme_setup_io_queues_trylock(struct nvme_dev *dev)
1653{
1654 /*
1655 * Give up if the lock is being held by nvme_dev_disable.
1656 */
1657 if (!mutex_trylock(&dev->shutdown_lock))
1658 return -ENODEV;
1659
1660 /*
1661 * Controller is in wrong state, fail early.
1662 */
1663 if (dev->ctrl.state != NVME_CTRL_CONNECTING) {
1664 mutex_unlock(&dev->shutdown_lock);
1665 return -ENODEV;
1666 }
1667
1668 return 0;
1669}
1670
4b04cc6a 1671static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled)
22404274
KB		 1672{
1673 struct nvme_dev *dev = nvmeq->dev;
1674 int result;
7c349dde 1675 u16 vector = 0;
3f85d50b 1676
d1ed6aa1
CH		 1677 clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
1678
22b55601
KB		 1679 /*
1680 * A queue's vector matches the queue identifier unless the controller
1681 * has only one vector available.
1682 */
4b04cc6a
JA		 1683 if (!polled)
1684 vector = dev->num_vecs == 1 ? 0 : qid;
1685 else
7c349dde 1686 set_bit(NVMEQ_POLLED, &nvmeq->flags);
4b04cc6a 1687
a8e3e0bb 1688 result = adapter_alloc_cq(dev, qid, nvmeq, vector);
ded45505
KB		 1689 if (result)
1690 return result;
b60503ba
MW		 1691
1692 result = adapter_alloc_sq(dev, qid, nvmeq);
1693 if (result < 0)
ded45505 1694 return result;
c80b36cd 1695 if (result)
b60503ba
MW		 1696 goto release_cq;
1697
a8e3e0bb 1698 nvmeq->cq_vector = vector;
4b04cc6a 1699
e4b9852a
CC		 1700 result = nvme_setup_io_queues_trylock(dev);
1701 if (result)
1702 return result;
1703 nvme_init_queue(nvmeq, qid);
7c349dde 1704 if (!polled) {
4b04cc6a
JA		 1705 result = queue_request_irq(nvmeq);
1706 if (result < 0)
1707 goto release_sq;
1708 }
b60503ba 1709
4e224106 1710 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
e4b9852a 1711 mutex_unlock(&dev->shutdown_lock);
22404274 1712 return result;
b60503ba 1713
a8e3e0bb 1714release_sq:
f25a2dfc 1715 dev->online_queues--;
e4b9852a 1716 mutex_unlock(&dev->shutdown_lock);
b60503ba 1717 adapter_delete_sq(dev, qid);
a8e3e0bb 1718release_cq:
b60503ba 1719 adapter_delete_cq(dev, qid);
22404274 1720 return result;
b60503ba
MW		 1721}
1722
f363b089 1723static const struct blk_mq_ops nvme_mq_admin_ops = {
d29ec824 1724 .queue_rq = nvme_queue_rq,
77f02a7a 1725 .complete = nvme_pci_complete_rq,
a4aea562 1726 .init_hctx = nvme_admin_init_hctx,
e559398f 1727 .init_request = nvme_pci_init_request,
a4aea562
MB		 1728 .timeout = nvme_timeout,
1729};
1730
f363b089 1731static const struct blk_mq_ops nvme_mq_ops = {
376f7ef8 1732 .queue_rq = nvme_queue_rq,
d62cbcf6 1733 .queue_rqs = nvme_queue_rqs,
376f7ef8
CH		 1734 .complete = nvme_pci_complete_rq,
1735 .commit_rqs = nvme_commit_rqs,
1736 .init_hctx = nvme_init_hctx,
e559398f 1737 .init_request = nvme_pci_init_request,
376f7ef8
CH		 1738 .map_queues = nvme_pci_map_queues,
1739 .timeout = nvme_timeout,
1740 .poll = nvme_poll,
dabcefab
JA		 1741};
1742
ea191d2f
KB		 1743static void nvme_dev_remove_admin(struct nvme_dev *dev)
1744{
1c63dc66 1745 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
69d9a99c
KB		 1746 /*
1747 * If the controller was reset during removal, it's possible
1748 * user requests may be waiting on a stopped queue. Start the
1749 * queue to flush these to completion.
1750 */
6ca1d902 1751 nvme_start_admin_queue(&dev->ctrl);
1c63dc66 1752 blk_cleanup_queue(dev->ctrl.admin_q);
ea191d2f
KB		 1753 blk_mq_free_tag_set(&dev->admin_tagset);
1754 }
1755}
1756
a4aea562
MB		 1757static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1758{
1c63dc66 1759 if (!dev->ctrl.admin_q) {
a4aea562
MB		 1760 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1761 dev->admin_tagset.nr_hw_queues = 1;
e3e9d50c 1762
38dabe21 1763 dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH;
dc96f938 1764 dev->admin_tagset.timeout = NVME_ADMIN_TIMEOUT;
d4ec47f1 1765 dev->admin_tagset.numa_node = dev->ctrl.numa_node;
d43f1ccf 1766 dev->admin_tagset.cmd_size = sizeof(struct nvme_iod);
d3484991 1767 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED;
a4aea562
MB		 1768 dev->admin_tagset.driver_data = dev;
1769
1770 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1771 return -ENOMEM;
34b6c231 1772 dev->ctrl.admin_tagset = &dev->admin_tagset;
a4aea562 1773
1c63dc66
CH		 1774 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1775 if (IS_ERR(dev->ctrl.admin_q)) {
a4aea562
MB		 1776 blk_mq_free_tag_set(&dev->admin_tagset);
1777 return -ENOMEM;
1778 }
1c63dc66 1779 if (!blk_get_queue(dev->ctrl.admin_q)) {
ea191d2f 1780 nvme_dev_remove_admin(dev);
1c63dc66 1781 dev->ctrl.admin_q = NULL;
ea191d2f
KB		 1782 return -ENODEV;
1783 }
0fb59cbc 1784 } else
6ca1d902 1785 nvme_start_admin_queue(&dev->ctrl);
a4aea562
MB		 1786
1787 return 0;
1788}
1789
97f6ef64
XY		 1790static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1791{
1792 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1793}
1794
1795static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1796{
1797 struct pci_dev *pdev = to_pci_dev(dev->dev);
1798
1799 if (size <= dev->bar_mapped_size)
1800 return 0;
1801 if (size > pci_resource_len(pdev, 0))
1802 return -ENOMEM;
1803 if (dev->bar)
1804 iounmap(dev->bar);
1805 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1806 if (!dev->bar) {
1807 dev->bar_mapped_size = 0;
1808 return -ENOMEM;
1809 }
1810 dev->bar_mapped_size = size;
1811 dev->dbs = dev->bar + NVME_REG_DBS;
1812
1813 return 0;
1814}
1815
01ad0990 1816static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
b60503ba 1817{
ba47e386 1818 int result;
b60503ba
MW		 1819 u32 aqa;
1820 struct nvme_queue *nvmeq;
1821
97f6ef64
XY		 1822 result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1823 if (result < 0)
1824 return result;
1825
8ef2074d 1826 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
20d0dfe6 1827 NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
dfbac8c7 1828
7a67cbea
CH		 1829 if (dev->subsystem &&
1830 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1831 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
dfbac8c7 1832
b5b05048 1833 result = nvme_disable_ctrl(&dev->ctrl);
ba47e386
MW		 1834 if (result < 0)
1835 return result;
b60503ba 1836
a6ff7262 1837 result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
147b27e4
SG		 1838 if (result)
1839 return result;
b60503ba 1840
635333e4
MG		 1841 dev->ctrl.numa_node = dev_to_node(dev->dev);
1842
147b27e4 1843 nvmeq = &dev->queues[0];
b60503ba
MW		 1844 aqa = nvmeq->q_depth - 1;
1845 aqa |= aqa << 16;
1846
7a67cbea
CH		 1847 writel(aqa, dev->bar + NVME_REG_AQA);
1848 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1849 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
b60503ba 1850
c0f2f45b 1851 result = nvme_enable_ctrl(&dev->ctrl);
025c557a 1852 if (result)
d4875622 1853 return result;
a4aea562 1854
2b25d981 1855 nvmeq->cq_vector = 0;
161b8be2 1856 nvme_init_queue(nvmeq, 0);
dca51e78 1857 result = queue_request_irq(nvmeq);
758dd7fd 1858 if (result) {
7c349dde 1859 dev->online_queues--;
d4875622 1860 return result;
758dd7fd 1861 }
025c557a 1862
4e224106 1863 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
b60503ba
MW		 1864 return result;
1865}
1866
749941f2 1867static int nvme_create_io_queues(struct nvme_dev *dev)
42f61420 1868{
4b04cc6a 1869 unsigned i, max, rw_queues;
749941f2 1870 int ret = 0;
42f61420 1871
d858e5f0 1872 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
a6ff7262 1873 if (nvme_alloc_queue(dev, i, dev->q_depth)) {
749941f2 1874 ret = -ENOMEM;
42f61420 1875 break;
749941f2
CH		 1876 }
1877 }
42f61420 1878
d858e5f0 1879 max = min(dev->max_qid, dev->ctrl.queue_count - 1);
e20ba6e1
CH		 1880 if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) {
1881 rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] +
1882 dev->io_queues[HCTX_TYPE_READ];
4b04cc6a
JA		 1883 } else {
1884 rw_queues = max;
1885 }
1886
949928c1 1887 for (i = dev->online_queues; i <= max; i++) {
4b04cc6a
JA		 1888 bool polled = i > rw_queues;
1889
1890 ret = nvme_create_queue(&dev->queues[i], i, polled);
d4875622 1891 if (ret)
42f61420 1892 break;
27e8166c 1893 }
749941f2
CH		 1894
1895 /*
1896 * Ignore failing Create SQ/CQ commands, we can continue with less
8adb8c14
MI		 1897 * than the desired amount of queues, and even a controller without
1898 * I/O queues can still be used to issue admin commands. This might
749941f2
CH		 1899 * be useful to upgrade a buggy firmware for example.
1900 */
1901 return ret >= 0 ? 0 : ret;
b60503ba
MW		 1902}
1903
88de4598 1904static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
8ffaadf7 1905{
88de4598
CH		 1906 u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
1907
1908 return 1ULL << (12 + 4 * szu);
1909}
1910
1911static u32 nvme_cmb_size(struct nvme_dev *dev)
1912{
1913 return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
1914}
1915
f65efd6d 1916static void nvme_map_cmb(struct nvme_dev *dev)
8ffaadf7 1917{
88de4598 1918 u64 size, offset;
8ffaadf7
JD		 1919 resource_size_t bar_size;
1920 struct pci_dev *pdev = to_pci_dev(dev->dev);
8969f1f8 1921 int bar;
8ffaadf7 1922
9fe5c59f
KB		 1923 if (dev->cmb_size)
1924 return;
1925
20d3bb92
KJ		 1926 if (NVME_CAP_CMBS(dev->ctrl.cap))
1927 writel(NVME_CMBMSC_CRE, dev->bar + NVME_REG_CMBMSC);
1928
7a67cbea 1929 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
f65efd6d
CH		 1930 if (!dev->cmbsz)
1931 return;
202021c1 1932 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
8ffaadf7 1933
88de4598
CH		 1934 size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
1935 offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
8969f1f8
CH		 1936 bar = NVME_CMB_BIR(dev->cmbloc);
1937 bar_size = pci_resource_len(pdev, bar);
8ffaadf7
JD		 1938
1939 if (offset > bar_size)
f65efd6d 1940 return;
8ffaadf7 1941
20d3bb92
KJ		 1942 /*
1943 * Tell the controller about the host side address mapping the CMB,
1944 * and enable CMB decoding for the NVMe 1.4+ scheme:
1945 */
1946 if (NVME_CAP_CMBS(dev->ctrl.cap)) {
1947 hi_lo_writeq(NVME_CMBMSC_CRE | NVME_CMBMSC_CMSE |
1948 (pci_bus_address(pdev, bar) + offset),
1949 dev->bar + NVME_REG_CMBMSC);
1950 }
1951
8ffaadf7
JD		 1952 /*
1953 * Controllers may support a CMB size larger than their BAR,
1954 * for example, due to being behind a bridge. Reduce the CMB to
1955 * the reported size of the BAR
1956 */
1957 if (size > bar_size - offset)
1958 size = bar_size - offset;
1959
0f238ff5
LG		 1960 if (pci_p2pdma_add_resource(pdev, bar, size, offset)) {
1961 dev_warn(dev->ctrl.device,
1962 "failed to register the CMB\n");
f65efd6d 1963 return;
0f238ff5
LG		 1964 }
1965
8ffaadf7 1966 dev->cmb_size = size;
0f238ff5
LG		 1967 dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS);
1968
1969 if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) ==
1970 (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS))
1971 pci_p2pmem_publish(pdev, true);
8ffaadf7
JD		 1972}
1973
87ad72a5
CH		 1974static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1975{
6c3c05b0 1976 u32 host_mem_size = dev->host_mem_size >> NVME_CTRL_PAGE_SHIFT;
4033f35d 1977 u64 dma_addr = dev->host_mem_descs_dma;
f66e2804 1978 struct nvme_command c = { };
87ad72a5
CH		 1979 int ret;
1980
87ad72a5
CH		 1981 c.features.opcode = nvme_admin_set_features;
1982 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1983 c.features.dword11 = cpu_to_le32(bits);
6c3c05b0 1984 c.features.dword12 = cpu_to_le32(host_mem_size);
87ad72a5
CH		 1985 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr));
1986 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr));
1987 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs);
1988
1989 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1990 if (ret) {
1991 dev_warn(dev->ctrl.device,
1992 "failed to set host mem (err %d, flags %#x).\n",
1993 ret, bits);
a5df5e79
KB		 1994 } else
1995 dev->hmb = bits & NVME_HOST_MEM_ENABLE;
1996
87ad72a5
CH		 1997 return ret;
1998}
1999
2000static void nvme_free_host_mem(struct nvme_dev *dev)
2001{
2002 int i;
2003
2004 for (i = 0; i < dev->nr_host_mem_descs; i++) {
2005 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
6c3c05b0 2006 size_t size = le32_to_cpu(desc->size) * NVME_CTRL_PAGE_SIZE;
87ad72a5 2007
cc667f6d
LD		 2008 dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i],
2009 le64_to_cpu(desc->addr),
2010 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
87ad72a5
CH		 2011 }
2012
2013 kfree(dev->host_mem_desc_bufs);
2014 dev->host_mem_desc_bufs = NULL;
4033f35d
CH		 2015 dma_free_coherent(dev->dev,
2016 dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
2017 dev->host_mem_descs, dev->host_mem_descs_dma);
87ad72a5 2018 dev->host_mem_descs = NULL;
7e5dd57e 2019 dev->nr_host_mem_descs = 0;
87ad72a5
CH		 2020}
2021
92dc6895
CH		 2022static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
2023 u32 chunk_size)
9d713c2b 2024{
87ad72a5 2025 struct nvme_host_mem_buf_desc *descs;
92dc6895 2026 u32 max_entries, len;
4033f35d 2027 dma_addr_t descs_dma;
2ee0e4ed 2028 int i = 0;
87ad72a5 2029 void **bufs;
6fbcde66 2030 u64 size, tmp;
87ad72a5 2031
87ad72a5
CH		 2032 tmp = (preferred + chunk_size - 1);
2033 do_div(tmp, chunk_size);
2034 max_entries = tmp;
044a9df1
CH		 2035
2036 if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
2037 max_entries = dev->ctrl.hmmaxd;
2038
750afb08
LC		 2039 descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs),
2040 &descs_dma, GFP_KERNEL);
87ad72a5
CH		 2041 if (!descs)
2042 goto out;
2043
2044 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
2045 if (!bufs)
2046 goto out_free_descs;
2047
244a8fe4 2048 for (size = 0; size < preferred && i < max_entries; size += len) {
87ad72a5
CH		 2049 dma_addr_t dma_addr;
2050
50cdb7c6 2051 len = min_t(u64, chunk_size, preferred - size);
87ad72a5
CH		 2052 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
2053 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
2054 if (!bufs[i])
2055 break;
2056
2057 descs[i].addr = cpu_to_le64(dma_addr);
6c3c05b0 2058 descs[i].size = cpu_to_le32(len / NVME_CTRL_PAGE_SIZE);
87ad72a5
CH		 2059 i++;
2060 }
2061
92dc6895 2062 if (!size)
87ad72a5 2063 goto out_free_bufs;
87ad72a5 2064
87ad72a5
CH		 2065 dev->nr_host_mem_descs = i;
2066 dev->host_mem_size = size;
2067 dev->host_mem_descs = descs;
4033f35d 2068 dev->host_mem_descs_dma = descs_dma;
87ad72a5
CH		 2069 dev->host_mem_desc_bufs = bufs;
2070 return 0;
2071
2072out_free_bufs:
2073 while (--i >= 0) {
6c3c05b0 2074 size_t size = le32_to_cpu(descs[i].size) * NVME_CTRL_PAGE_SIZE;
87ad72a5 2075
cc667f6d
LD		 2076 dma_free_attrs(dev->dev, size, bufs[i],
2077 le64_to_cpu(descs[i].addr),
2078 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
87ad72a5
CH		 2079 }
2080
2081 kfree(bufs);
2082out_free_descs:
4033f35d
CH		 2083 dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
2084 descs_dma);
87ad72a5 2085out:
87ad72a5
CH		 2086 dev->host_mem_descs = NULL;
2087 return -ENOMEM;
2088}
2089
92dc6895
CH		 2090static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
2091{
9dc54a0d
CK		 2092 u64 min_chunk = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
2093 u64 hmminds = max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
2094 u64 chunk_size;
92dc6895
CH		 2095
2096 /* start big and work our way down */
9dc54a0d 2097 for (chunk_size = min_chunk; chunk_size >= hmminds; chunk_size /= 2) {
92dc6895
CH		 2098 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
2099 if (!min || dev->host_mem_size >= min)
2100 return 0;
2101 nvme_free_host_mem(dev);
2102 }
2103 }
2104
2105 return -ENOMEM;
2106}
2107
9620cfba 2108static int nvme_setup_host_mem(struct nvme_dev *dev)
87ad72a5
CH		 2109{
2110 u64 max = (u64)max_host_mem_size_mb * SZ_1M;
2111 u64 preferred = (u64)dev->ctrl.hmpre * 4096;
2112 u64 min = (u64)dev->ctrl.hmmin * 4096;
2113 u32 enable_bits = NVME_HOST_MEM_ENABLE;
6fbcde66 2114 int ret;
87ad72a5
CH		 2115
2116 preferred = min(preferred, max);
2117 if (min > max) {
2118 dev_warn(dev->ctrl.device,
2119 "min host memory (%lld MiB) above limit (%d MiB).\n",
2120 min >> ilog2(SZ_1M), max_host_mem_size_mb);
2121 nvme_free_host_mem(dev);
9620cfba 2122 return 0;
87ad72a5
CH		 2123 }
2124
2125 /*
2126 * If we already have a buffer allocated check if we can reuse it.
2127 */
2128 if (dev->host_mem_descs) {
2129 if (dev->host_mem_size >= min)
2130 enable_bits |= NVME_HOST_MEM_RETURN;
2131 else
2132 nvme_free_host_mem(dev);
2133 }
2134
2135 if (!dev->host_mem_descs) {
92dc6895
CH		 2136 if (nvme_alloc_host_mem(dev, min, preferred)) {
2137 dev_warn(dev->ctrl.device,
2138 "failed to allocate host memory buffer.\n");
9620cfba 2139 return 0; /* controller must work without HMB */
92dc6895
CH		 2140 }
2141
2142 dev_info(dev->ctrl.device,
2143 "allocated %lld MiB host memory buffer.\n",
2144 dev->host_mem_size >> ilog2(SZ_1M));
87ad72a5
CH		 2145 }
2146
9620cfba
CH		 2147 ret = nvme_set_host_mem(dev, enable_bits);
2148 if (ret)
87ad72a5 2149 nvme_free_host_mem(dev);
9620cfba 2150 return ret;
9d713c2b
KB		 2151}
2152
0521905e
KB		 2153static ssize_t cmb_show(struct device *dev, struct device_attribute *attr,
2154 char *buf)
2155{
2156 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2157
2158 return sysfs_emit(buf, "cmbloc : x%08x\ncmbsz : x%08x\n",
2159 ndev->cmbloc, ndev->cmbsz);
2160}
2161static DEVICE_ATTR_RO(cmb);
2162
1751e97a
KB		 2163static ssize_t cmbloc_show(struct device *dev, struct device_attribute *attr,
2164 char *buf)
2165{
2166 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2167
2168 return sysfs_emit(buf, "%u\n", ndev->cmbloc);
2169}
2170static DEVICE_ATTR_RO(cmbloc);
2171
2172static ssize_t cmbsz_show(struct device *dev, struct device_attribute *attr,
2173 char *buf)
2174{
2175 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2176
2177 return sysfs_emit(buf, "%u\n", ndev->cmbsz);
2178}
2179static DEVICE_ATTR_RO(cmbsz);
2180
a5df5e79
KB		 2181static ssize_t hmb_show(struct device *dev, struct device_attribute *attr,
2182 char *buf)
2183{
2184 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2185
2186 return sysfs_emit(buf, "%d\n", ndev->hmb);
2187}
2188
2189static ssize_t hmb_store(struct device *dev, struct device_attribute *attr,
2190 const char *buf, size_t count)
2191{
2192 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2193 bool new;
2194 int ret;
2195
2196 if (strtobool(buf, &new) < 0)
2197 return -EINVAL;
2198
2199 if (new == ndev->hmb)
2200 return count;
2201
2202 if (new) {
2203 ret = nvme_setup_host_mem(ndev);
2204 } else {
2205 ret = nvme_set_host_mem(ndev, 0);
2206 if (!ret)
2207 nvme_free_host_mem(ndev);
2208 }
2209
2210 if (ret < 0)
2211 return ret;
2212
2213 return count;
2214}
2215static DEVICE_ATTR_RW(hmb);
2216
0521905e
KB		 2217static umode_t nvme_pci_attrs_are_visible(struct kobject *kobj,
2218 struct attribute *a, int n)
2219{
2220 struct nvme_ctrl *ctrl =
2221 dev_get_drvdata(container_of(kobj, struct device, kobj));
2222 struct nvme_dev *dev = to_nvme_dev(ctrl);
2223
1751e97a
KB		 2224 if (a == &dev_attr_cmb.attr ||
2225 a == &dev_attr_cmbloc.attr ||
2226 a == &dev_attr_cmbsz.attr) {
2227 if (!dev->cmbsz)
2228 return 0;
2229 }
a5df5e79
KB		 2230 if (a == &dev_attr_hmb.attr && !ctrl->hmpre)
2231 return 0;
2232
0521905e
KB		 2233 return a->mode;
2234}
2235
2236static struct attribute *nvme_pci_attrs[] = {
2237 &dev_attr_cmb.attr,
1751e97a
KB		 2238 &dev_attr_cmbloc.attr,
2239 &dev_attr_cmbsz.attr,
a5df5e79 2240 &dev_attr_hmb.attr,
0521905e
KB		 2241 NULL,
2242};
2243
2244static const struct attribute_group nvme_pci_attr_group = {
2245 .attrs = nvme_pci_attrs,
2246 .is_visible = nvme_pci_attrs_are_visible,
2247};
2248
612b7286
ML		 2249/*
2250 * nirqs is the number of interrupts available for write and read
2251 * queues. The core already reserved an interrupt for the admin queue.
2252 */
2253static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs)
3b6592f7 2254{
612b7286 2255 struct nvme_dev *dev = affd->priv;
2a5bcfdd 2256 unsigned int nr_read_queues, nr_write_queues = dev->nr_write_queues;
3b6592f7
JA		 2257
2258 /*
ee0d96d3 2259 * If there is no interrupt available for queues, ensure that
612b7286
ML		 2260 * the default queue is set to 1. The affinity set size is
2261 * also set to one, but the irq core ignores it for this case.
2262 *
2263 * If only one interrupt is available or 'write_queue' == 0, combine
2264 * write and read queues.
2265 *
2266 * If 'write_queues' > 0, ensure it leaves room for at least one read
2267 * queue.
3b6592f7 2268 */
612b7286
ML		 2269 if (!nrirqs) {
2270 nrirqs = 1;
2271 nr_read_queues = 0;
2a5bcfdd 2272 } else if (nrirqs == 1 || !nr_write_queues) {
612b7286 2273 nr_read_queues = 0;
2a5bcfdd 2274 } else if (nr_write_queues >= nrirqs) {
612b7286 2275 nr_read_queues = 1;
3b6592f7 2276 } else {
2a5bcfdd 2277 nr_read_queues = nrirqs - nr_write_queues;
3b6592f7 2278 }
612b7286
ML		 2279
2280 dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2281 affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2282 dev->io_queues[HCTX_TYPE_READ] = nr_read_queues;
2283 affd->set_size[HCTX_TYPE_READ] = nr_read_queues;
2284 affd->nr_sets = nr_read_queues ? 2 : 1;
3b6592f7
JA		 2285}
2286
6451fe73 2287static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues)
3b6592f7
JA		 2288{
2289 struct pci_dev *pdev = to_pci_dev(dev->dev);
3b6592f7 2290 struct irq_affinity affd = {
9cfef55b 2291 .pre_vectors = 1,
612b7286
ML		 2292 .calc_sets = nvme_calc_irq_sets,
2293 .priv = dev,
3b6592f7 2294 };
21cc2f3f 2295 unsigned int irq_queues, poll_queues;
6451fe73
JA		 2296
2297 /*
21cc2f3f
JX		 2298 * Poll queues don't need interrupts, but we need at least one I/O queue
2299 * left over for non-polled I/O.
6451fe73 2300 */
21cc2f3f
JX		 2301 poll_queues = min(dev->nr_poll_queues, nr_io_queues - 1);
2302 dev->io_queues[HCTX_TYPE_POLL] = poll_queues;
3b6592f7 2303
21cc2f3f
JX		 2304 /*
2305 * Initialize for the single interrupt case, will be updated in
2306 * nvme_calc_irq_sets().
2307 */
612b7286
ML		 2308 dev->io_queues[HCTX_TYPE_DEFAULT] = 1;
2309 dev->io_queues[HCTX_TYPE_READ] = 0;
3b6592f7 2310
66341331 2311 /*
21cc2f3f
JX		 2312 * We need interrupts for the admin queue and each non-polled I/O queue,
2313 * but some Apple controllers require all queues to use the first
2314 * vector.
66341331 2315 */
21cc2f3f
JX		 2316 irq_queues = 1;
2317 if (!(dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR))
2318 irq_queues += (nr_io_queues - poll_queues);
612b7286
ML		 2319 return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues,
2320 PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd);
3b6592f7
JA		 2321}
2322
8fae268b
KB		 2323static void nvme_disable_io_queues(struct nvme_dev *dev)
2324{
2325 if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq))
2326 __nvme_disable_io_queues(dev, nvme_admin_delete_cq);
2327}
2328
2a5bcfdd
WZ		 2329static unsigned int nvme_max_io_queues(struct nvme_dev *dev)
2330{
e3aef095
NS		 2331 /*
2332 * If tags are shared with admin queue (Apple bug), then
2333 * make sure we only use one IO queue.
2334 */
2335 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2336 return 1;
2a5bcfdd
WZ		 2337 return num_possible_cpus() + dev->nr_write_queues + dev->nr_poll_queues;
2338}
2339
8d85fce7 2340static int nvme_setup_io_queues(struct nvme_dev *dev)
b60503ba 2341{
147b27e4 2342 struct nvme_queue *adminq = &dev->queues[0];
e75ec752 2343 struct pci_dev *pdev = to_pci_dev(dev->dev);
2a5bcfdd 2344 unsigned int nr_io_queues;
97f6ef64 2345 unsigned long size;
2a5bcfdd 2346 int result;
b60503ba 2347
2a5bcfdd
WZ		 2348 /*
2349 * Sample the module parameters once at reset time so that we have
2350 * stable values to work with.
2351 */
2352 dev->nr_write_queues = write_queues;
2353 dev->nr_poll_queues = poll_queues;
d38e9f04 2354
e3aef095 2355 nr_io_queues = dev->nr_allocated_queues - 1;
9a0be7ab
CH		 2356 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
2357 if (result < 0)
1b23484b 2358 return result;
9a0be7ab 2359
f5fa90dc 2360 if (nr_io_queues == 0)
a5229050 2361 return 0;
53dc180e 2362
e4b9852a
CC		 2363 /*
2364 * Free IRQ resources as soon as NVMEQ_ENABLED bit transitions
2365 * from set to unset. If there is a window to it is truely freed,
2366 * pci_free_irq_vectors() jumping into this window will crash.
2367 * And take lock to avoid racing with pci_free_irq_vectors() in
2368 * nvme_dev_disable() path.
2369 */
2370 result = nvme_setup_io_queues_trylock(dev);
2371 if (result)
2372 return result;
2373 if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags))
2374 pci_free_irq(pdev, 0, adminq);
b60503ba 2375
0f238ff5 2376 if (dev->cmb_use_sqes) {
8ffaadf7
JD		 2377 result = nvme_cmb_qdepth(dev, nr_io_queues,
2378 sizeof(struct nvme_command));
2379 if (result > 0)
2380 dev->q_depth = result;
2381 else
0f238ff5 2382 dev->cmb_use_sqes = false;
8ffaadf7
JD		 2383 }
2384
97f6ef64
XY		 2385 do {
2386 size = db_bar_size(dev, nr_io_queues);
2387 result = nvme_remap_bar(dev, size);
2388 if (!result)
2389 break;
e4b9852a
CC		 2390 if (!--nr_io_queues) {
2391 result = -ENOMEM;
2392 goto out_unlock;
2393 }
97f6ef64
XY		 2394 } while (1);
2395 adminq->q_db = dev->dbs;
f1938f6e 2396
8fae268b 2397 retry:
9d713c2b 2398 /* Deregister the admin queue's interrupt */
e4b9852a
CC		 2399 if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags))
2400 pci_free_irq(pdev, 0, adminq);
9d713c2b 2401
e32efbfc
JA		 2402 /*
2403 * If we enable msix early due to not intx, disable it again before
2404 * setting up the full range we need.
2405 */
dca51e78 2406 pci_free_irq_vectors(pdev);
3b6592f7
JA		 2407
2408 result = nvme_setup_irqs(dev, nr_io_queues);
e4b9852a
CC		 2409 if (result <= 0) {
2410 result = -EIO;
2411 goto out_unlock;
2412 }
3b6592f7 2413
22b55601 2414 dev->num_vecs = result;
4b04cc6a 2415 result = max(result - 1, 1);
e20ba6e1 2416 dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL];
fa08a396 2417
063a8096
MW		 2418 /*
2419 * Should investigate if there's a performance win from allocating
2420 * more queues than interrupt vectors; it might allow the submission
2421 * path to scale better, even if the receive path is limited by the
2422 * number of interrupts.
2423 */
dca51e78 2424 result = queue_request_irq(adminq);
7c349dde 2425 if (result)
e4b9852a 2426 goto out_unlock;
4e224106 2427 set_bit(NVMEQ_ENABLED, &adminq->flags);
e4b9852a 2428 mutex_unlock(&dev->shutdown_lock);
8fae268b
KB		 2429
2430 result = nvme_create_io_queues(dev);
2431 if (result || dev->online_queues < 2)
2432 return result;
2433
2434 if (dev->online_queues - 1 < dev->max_qid) {
2435 nr_io_queues = dev->online_queues - 1;
2436 nvme_disable_io_queues(dev);
e4b9852a
CC		 2437 result = nvme_setup_io_queues_trylock(dev);
2438 if (result)
2439 return result;
8fae268b
KB		 2440 nvme_suspend_io_queues(dev);
2441 goto retry;
2442 }
2443 dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n",
2444 dev->io_queues[HCTX_TYPE_DEFAULT],
2445 dev->io_queues[HCTX_TYPE_READ],
2446 dev->io_queues[HCTX_TYPE_POLL]);
2447 return 0;
e4b9852a
CC		 2448out_unlock:
2449 mutex_unlock(&dev->shutdown_lock);
2450 return result;
b60503ba
MW		 2451}
2452
2a842aca 2453static void nvme_del_queue_end(struct request *req, blk_status_t error)
a5768aa8 2454{
db3cbfff 2455 struct nvme_queue *nvmeq = req->end_io_data;
b5875222 2456
db3cbfff 2457 blk_mq_free_request(req);
d1ed6aa1 2458 complete(&nvmeq->delete_done);
a5768aa8
KB		 2459}
2460
2a842aca 2461static void nvme_del_cq_end(struct request *req, blk_status_t error)
a5768aa8 2462{
db3cbfff 2463 struct nvme_queue *nvmeq = req->end_io_data;
a5768aa8 2464
d1ed6aa1
CH		 2465 if (error)
2466 set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
db3cbfff
KB		 2467
2468 nvme_del_queue_end(req, error);
a5768aa8
KB		 2469}
2470
db3cbfff 2471static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
bda4e0fb 2472{
db3cbfff
KB		 2473 struct request_queue *q = nvmeq->dev->ctrl.admin_q;
2474 struct request *req;
f66e2804 2475 struct nvme_command cmd = { };
bda4e0fb 2476
db3cbfff
KB		 2477 cmd.delete_queue.opcode = opcode;
2478 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
bda4e0fb 2479
e559398f 2480 req = blk_mq_alloc_request(q, nvme_req_op(&cmd), BLK_MQ_REQ_NOWAIT);
db3cbfff
KB		 2481 if (IS_ERR(req))
2482 return PTR_ERR(req);
e559398f 2483 nvme_init_request(req, &cmd);
bda4e0fb 2484
db3cbfff
KB		 2485 req->end_io_data = nvmeq;
2486
d1ed6aa1 2487 init_completion(&nvmeq->delete_done);
b84ba30b
CH		 2488 blk_execute_rq_nowait(req, false, opcode == nvme_admin_delete_cq ?
2489 nvme_del_cq_end : nvme_del_queue_end);
db3cbfff 2490 return 0;
bda4e0fb
KB		 2491}
2492
8fae268b 2493static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode)
a5768aa8 2494{
5271edd4 2495 int nr_queues = dev->online_queues - 1, sent = 0;
db3cbfff 2496 unsigned long timeout;
a5768aa8 2497
db3cbfff 2498 retry:
dc96f938 2499 timeout = NVME_ADMIN_TIMEOUT;
5271edd4
CH		 2500 while (nr_queues > 0) {
2501 if (nvme_delete_queue(&dev->queues[nr_queues], opcode))
2502 break;
2503 nr_queues--;
2504 sent++;
db3cbfff 2505 }
d1ed6aa1
CH		 2506 while (sent) {
2507 struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent];
2508
2509 timeout = wait_for_completion_io_timeout(&nvmeq->delete_done,
5271edd4
CH		 2510 timeout);
2511 if (timeout == 0)
2512 return false;
d1ed6aa1 2513
d1ed6aa1 2514 sent--;
5271edd4
CH		 2515 if (nr_queues)
2516 goto retry;
2517 }
2518 return true;
a5768aa8
KB		 2519}
2520
5d02a5c1 2521static void nvme_dev_add(struct nvme_dev *dev)
b60503ba 2522{
2b1b7e78
JW		 2523 int ret;
2524
5bae7f73 2525 if (!dev->ctrl.tagset) {
376f7ef8 2526 dev->tagset.ops = &nvme_mq_ops;
ffe7704d 2527 dev->tagset.nr_hw_queues = dev->online_queues - 1;
8fe34be1 2528 dev->tagset.nr_maps = 2; /* default + read */
ed92ad37
CH		 2529 if (dev->io_queues[HCTX_TYPE_POLL])
2530 dev->tagset.nr_maps++;
ffe7704d 2531 dev->tagset.timeout = NVME_IO_TIMEOUT;
d4ec47f1 2532 dev->tagset.numa_node = dev->ctrl.numa_node;
61f3b896
CK		 2533 dev->tagset.queue_depth = min_t(unsigned int, dev->q_depth,
2534 BLK_MQ_MAX_DEPTH) - 1;
d43f1ccf 2535 dev->tagset.cmd_size = sizeof(struct nvme_iod);
ffe7704d
KB		 2536 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2537 dev->tagset.driver_data = dev;
b60503ba 2538
d38e9f04
BH		 2539 /*
2540 * Some Apple controllers requires tags to be unique
2541 * across admin and IO queue, so reserve the first 32
2542 * tags of the IO queue.
2543 */
2544 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2545 dev->tagset.reserved_tags = NVME_AQ_DEPTH;
2546
2b1b7e78
JW		 2547 ret = blk_mq_alloc_tag_set(&dev->tagset);
2548 if (ret) {
2549 dev_warn(dev->ctrl.device,
2550 "IO queues tagset allocation failed %d\n", ret);
5d02a5c1 2551 return;
2b1b7e78 2552 }
5bae7f73 2553 dev->ctrl.tagset = &dev->tagset;
949928c1
KB		 2554 } else {
2555 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2556
2557 /* Free previously allocated queues that are no longer usable */
2558 nvme_free_queues(dev, dev->online_queues);
ffe7704d 2559 }
949928c1 2560
e8fd41bb 2561 nvme_dbbuf_set(dev);
b60503ba
MW		 2562}
2563
b00a726a 2564static int nvme_pci_enable(struct nvme_dev *dev)
0877cb0d 2565{
b00a726a 2566 int result = -ENOMEM;
e75ec752 2567 struct pci_dev *pdev = to_pci_dev(dev->dev);
4bdf2603 2568 int dma_address_bits = 64;
0877cb0d
KB		 2569
2570 if (pci_enable_device_mem(pdev))
2571 return result;
2572
0877cb0d 2573 pci_set_master(pdev);
0877cb0d 2574
4bdf2603
FS		 2575 if (dev->ctrl.quirks & NVME_QUIRK_DMA_ADDRESS_BITS_48)
2576 dma_address_bits = 48;
2577 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(dma_address_bits)))
052d0efa 2578 goto disable;
0877cb0d 2579
7a67cbea 2580 if (readl(dev->bar + NVME_REG_CSTS) == -1) {
0e53d180 2581 result = -ENODEV;
b00a726a 2582 goto disable;
0e53d180 2583 }
e32efbfc
JA		 2584
2585 /*
a5229050
KB		 2586 * Some devices and/or platforms don't advertise or work with INTx
2587 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2588 * adjust this later.
e32efbfc 2589 */
dca51e78
CH		 2590 result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
2591 if (result < 0)
2592 return result;
e32efbfc 2593
20d0dfe6 2594 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
7a67cbea 2595
7442ddce 2596 dev->q_depth = min_t(u32, NVME_CAP_MQES(dev->ctrl.cap) + 1,
b27c1e68 2597 io_queue_depth);
aa22c8e6 2598 dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */
20d0dfe6 2599 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
7a67cbea 2600 dev->dbs = dev->bar + 4096;
1f390c1f 2601
66341331
BH		 2602 /*
2603 * Some Apple controllers require a non-standard SQE size.
2604 * Interestingly they also seem to ignore the CC:IOSQES register
2605 * so we don't bother updating it here.
2606 */
2607 if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES)
2608 dev->io_sqes = 7;
2609 else
2610 dev->io_sqes = NVME_NVM_IOSQES;
1f390c1f
SG		 2611
2612 /*
2613 * Temporary fix for the Apple controller found in the MacBook8,1 and
2614 * some MacBook7,1 to avoid controller resets and data loss.
2615 */
2616 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
2617 dev->q_depth = 2;
9bdcfb10
CH		 2618 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
2619 "set queue depth=%u to work around controller resets\n",
1f390c1f 2620 dev->q_depth);
d554b5e1
MP		 2621 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2622 (pdev->device == 0xa821 || pdev->device == 0xa822) &&
20d0dfe6 2623 NVME_CAP_MQES(dev->ctrl.cap) == 0) {
d554b5e1
MP		 2624 dev->q_depth = 64;
2625 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2626 "set queue depth=%u\n", dev->q_depth);
1f390c1f
SG		 2627 }
2628
d38e9f04
BH		 2629 /*
2630 * Controllers with the shared tags quirk need the IO queue to be
2631 * big enough so that we get 32 tags for the admin queue
2632 */
2633 if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) &&
2634 (dev->q_depth < (NVME_AQ_DEPTH + 2))) {
2635 dev->q_depth = NVME_AQ_DEPTH + 2;
2636 dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n",
2637 dev->q_depth);
2638 }
2639
2640
f65efd6d 2641 nvme_map_cmb(dev);
202021c1 2642
a0a3408e
KB		 2643 pci_enable_pcie_error_reporting(pdev);
2644 pci_save_state(pdev);
0877cb0d
KB		 2645 return 0;
2646
2647 disable:
0877cb0d
KB		 2648 pci_disable_device(pdev);
2649 return result;
2650}
2651
2652static void nvme_dev_unmap(struct nvme_dev *dev)
b00a726a
KB		 2653{
2654 if (dev->bar)
2655 iounmap(dev->bar);
a1f447b3 2656 pci_release_mem_regions(to_pci_dev(dev->dev));
b00a726a
KB		 2657}
2658
2659static void nvme_pci_disable(struct nvme_dev *dev)
0877cb0d 2660{
e75ec752
CH		 2661 struct pci_dev *pdev = to_pci_dev(dev->dev);
2662
dca51e78 2663 pci_free_irq_vectors(pdev);
0877cb0d 2664
a0a3408e
KB		 2665 if (pci_is_enabled(pdev)) {
2666 pci_disable_pcie_error_reporting(pdev);
e75ec752 2667 pci_disable_device(pdev);
4d115420 2668 }
4d115420
KB		 2669}
2670
a5cdb68c 2671static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
b60503ba 2672{
e43269e6 2673 bool dead = true, freeze = false;
302ad8cc 2674 struct pci_dev *pdev = to_pci_dev(dev->dev);
22404274 2675
77bf25ea 2676 mutex_lock(&dev->shutdown_lock);
302ad8cc
KB		 2677 if (pci_is_enabled(pdev)) {
2678 u32 csts = readl(dev->bar + NVME_REG_CSTS);
2679
ebef7368 2680 if (dev->ctrl.state == NVME_CTRL_LIVE ||
e43269e6
KB		 2681 dev->ctrl.state == NVME_CTRL_RESETTING) {
2682 freeze = true;
302ad8cc 2683 nvme_start_freeze(&dev->ctrl);
e43269e6 2684 }
302ad8cc
KB		 2685 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
2686 pdev->error_state != pci_channel_io_normal);
c9d3bf88 2687 }
c21377f8 2688
302ad8cc
KB		 2689 /*
2690 * Give the controller a chance to complete all entered requests if
2691 * doing a safe shutdown.
2692 */
e43269e6
KB		 2693 if (!dead && shutdown && freeze)
2694 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
9a915a5b
JW		 2695
2696 nvme_stop_queues(&dev->ctrl);
87ad72a5 2697
64ee0ac0 2698 if (!dead && dev->ctrl.queue_count > 0) {
8fae268b 2699 nvme_disable_io_queues(dev);
a5cdb68c 2700 nvme_disable_admin_queue(dev, shutdown);
4d115420 2701 }
8fae268b
KB		 2702 nvme_suspend_io_queues(dev);
2703 nvme_suspend_queue(&dev->queues[0]);
b00a726a 2704 nvme_pci_disable(dev);
fa46c6fb 2705 nvme_reap_pending_cqes(dev);
07836e65 2706
e1958e65
ML		 2707 blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
2708 blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
622b8b68
ML		 2709 blk_mq_tagset_wait_completed_request(&dev->tagset);
2710 blk_mq_tagset_wait_completed_request(&dev->admin_tagset);
302ad8cc
KB		 2711
2712 /*
2713 * The driver will not be starting up queues again if shutting down so
2714 * must flush all entered requests to their failed completion to avoid
2715 * deadlocking blk-mq hot-cpu notifier.
2716 */
c8e9e9b7 2717 if (shutdown) {
302ad8cc 2718 nvme_start_queues(&dev->ctrl);
c8e9e9b7 2719 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q))
6ca1d902 2720 nvme_start_admin_queue(&dev->ctrl);
c8e9e9b7 2721 }
77bf25ea 2722 mutex_unlock(&dev->shutdown_lock);
b60503ba
MW		 2723}
2724
c1ac9a4b
KB		 2725static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown)
2726{
2727 if (!nvme_wait_reset(&dev->ctrl))
2728 return -EBUSY;
2729 nvme_dev_disable(dev, shutdown);
2730 return 0;
2731}
2732
091b6092
MW		 2733static int nvme_setup_prp_pools(struct nvme_dev *dev)
2734{
e75ec752 2735 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
c61b82c7
CH		 2736 NVME_CTRL_PAGE_SIZE,
2737 NVME_CTRL_PAGE_SIZE, 0);
091b6092
MW		 2738 if (!dev->prp_page_pool)
2739 return -ENOMEM;
2740
99802a7a 2741 /* Optimisation for I/Os between 4k and 128k */
e75ec752 2742 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
99802a7a
MW		 2743 256, 256, 0);
2744 if (!dev->prp_small_pool) {
2745 dma_pool_destroy(dev->prp_page_pool);
2746 return -ENOMEM;
2747 }
091b6092
MW		 2748 return 0;
2749}
2750
2751static void nvme_release_prp_pools(struct nvme_dev *dev)
2752{
2753 dma_pool_destroy(dev->prp_page_pool);
99802a7a 2754 dma_pool_destroy(dev->prp_small_pool);
091b6092
MW		 2755}
2756
770597ec
KB		 2757static void nvme_free_tagset(struct nvme_dev *dev)
2758{
2759 if (dev->tagset.tags)
2760 blk_mq_free_tag_set(&dev->tagset);
2761 dev->ctrl.tagset = NULL;
2762}
2763
1673f1f0 2764static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
5e82e952 2765{
1673f1f0 2766 struct nvme_dev *dev = to_nvme_dev(ctrl);
9ac27090 2767
f9f38e33 2768 nvme_dbbuf_dma_free(dev);
770597ec 2769 nvme_free_tagset(dev);
1c63dc66
CH		 2770 if (dev->ctrl.admin_q)
2771 blk_put_queue(dev->ctrl.admin_q);
e286bcfc 2772 free_opal_dev(dev->ctrl.opal_dev);
943e942e 2773 mempool_destroy(dev->iod_mempool);
253fd4ac
IR		 2774 put_device(dev->dev);
2775 kfree(dev->queues);
5e82e952
KB		 2776 kfree(dev);
2777}
2778
7c1ce408 2779static void nvme_remove_dead_ctrl(struct nvme_dev *dev)
f58944e2 2780{
c1ac9a4b
KB		 2781 /*
2782 * Set state to deleting now to avoid blocking nvme_wait_reset(), which
2783 * may be holding this pci_dev's device lock.
2784 */
2785 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
d22524a4 2786 nvme_get_ctrl(&dev->ctrl);
69d9a99c 2787 nvme_dev_disable(dev, false);
9f9cafc1 2788 nvme_kill_queues(&dev->ctrl);
03e0f3a6 2789 if (!queue_work(nvme_wq, &dev->remove_work))
f58944e2
KB		 2790 nvme_put_ctrl(&dev->ctrl);
2791}
2792
fd634f41 2793static void nvme_reset_work(struct work_struct *work)
5e82e952 2794{
d86c4d8e
CH		 2795 struct nvme_dev *dev =
2796 container_of(work, struct nvme_dev, ctrl.reset_work);
a98e58e5 2797 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
e71afda4 2798 int result;
5e82e952 2799
7764656b
ZC		 2800 if (dev->ctrl.state != NVME_CTRL_RESETTING) {
2801 dev_warn(dev->ctrl.device, "ctrl state %d is not RESETTING\n",
2802 dev->ctrl.state);
e71afda4 2803 result = -ENODEV;
fd634f41 2804 goto out;
e71afda4 2805 }
5e82e952 2806
fd634f41
CH		 2807 /*
2808 * If we're called to reset a live controller first shut it down before
2809 * moving on.
2810 */
b00a726a 2811 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
a5cdb68c 2812 nvme_dev_disable(dev, false);
d6135c3a 2813 nvme_sync_queues(&dev->ctrl);
5e82e952 2814
5c959d73 2815 mutex_lock(&dev->shutdown_lock);
b00a726a 2816 result = nvme_pci_enable(dev);
f0b50732 2817 if (result)
4726bcf3 2818 goto out_unlock;
f0b50732 2819
01ad0990 2820 result = nvme_pci_configure_admin_queue(dev);
f0b50732 2821 if (result)
4726bcf3 2822 goto out_unlock;
f0b50732 2823
0fb59cbc
KB		 2824 result = nvme_alloc_admin_tags(dev);
2825 if (result)
4726bcf3 2826 goto out_unlock;
b9afca3e 2827
943e942e
JA		 2828 /*
2829 * Limit the max command size to prevent iod->sg allocations going
2830 * over a single page.
2831 */
7637de31
CH		 2832 dev->ctrl.max_hw_sectors = min_t(u32,
2833 NVME_MAX_KB_SZ << 1, dma_max_mapping_size(dev->dev) >> 9);
943e942e 2834 dev->ctrl.max_segments = NVME_MAX_SEGS;
a48bc520
CH		 2835
2836 /*
2837 * Don't limit the IOMMU merged segment size.
2838 */
2839 dma_set_max_seg_size(dev->dev, 0xffffffff);
3d2d861e 2840 dma_set_min_align_mask(dev->dev, NVME_CTRL_PAGE_SIZE - 1);
a48bc520 2841
5c959d73
KB		 2842 mutex_unlock(&dev->shutdown_lock);
2843
2844 /*
2845 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
2846 * initializing procedure here.
2847 */
2848 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
2849 dev_warn(dev->ctrl.device,
2850 "failed to mark controller CONNECTING\n");
cee6c269 2851 result = -EBUSY;
5c959d73
KB		 2852 goto out;
2853 }
943e942e 2854
95093350
MG		 2855 /*
2856 * We do not support an SGL for metadata (yet), so we are limited to a
2857 * single integrity segment for the separate metadata pointer.
2858 */
2859 dev->ctrl.max_integrity_segments = 1;
2860
f21c4769 2861 result = nvme_init_ctrl_finish(&dev->ctrl);
ce4541f4 2862 if (result)
f58944e2 2863 goto out;
ce4541f4 2864
e286bcfc
SB		 2865 if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
2866 if (!dev->ctrl.opal_dev)
2867 dev->ctrl.opal_dev =
2868 init_opal_dev(&dev->ctrl, &nvme_sec_submit);
2869 else if (was_suspend)
2870 opal_unlock_from_suspend(dev->ctrl.opal_dev);
2871 } else {
2872 free_opal_dev(dev->ctrl.opal_dev);
2873 dev->ctrl.opal_dev = NULL;
4f1244c8 2874 }
a98e58e5 2875
f9f38e33
HK		 2876 if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) {
2877 result = nvme_dbbuf_dma_alloc(dev);
2878 if (result)
2879 dev_warn(dev->dev,
2880 "unable to allocate dma for dbbuf\n");
2881 }
2882
9620cfba
CH		 2883 if (dev->ctrl.hmpre) {
2884 result = nvme_setup_host_mem(dev);
2885 if (result < 0)
2886 goto out;
2887 }
87ad72a5 2888
f0b50732 2889 result = nvme_setup_io_queues(dev);
badc34d4 2890 if (result)
f58944e2 2891 goto out;
f0b50732 2892
2659e57b
CH		 2893 /*
2894 * Keep the controller around but remove all namespaces if we don't have
2895 * any working I/O queue.
2896 */
3cf519b5 2897 if (dev->online_queues < 2) {
1b3c47c1 2898 dev_warn(dev->ctrl.device, "IO queues not created\n");
3b24774e 2899 nvme_kill_queues(&dev->ctrl);
5bae7f73 2900 nvme_remove_namespaces(&dev->ctrl);
770597ec 2901 nvme_free_tagset(dev);
3cf519b5 2902 } else {
25646264 2903 nvme_start_queues(&dev->ctrl);
302ad8cc 2904 nvme_wait_freeze(&dev->ctrl);
5d02a5c1 2905 nvme_dev_add(dev);
302ad8cc 2906 nvme_unfreeze(&dev->ctrl);
3cf519b5
CH		 2907 }
2908
2b1b7e78
JW		 2909 /*
2910 * If only admin queue live, keep it to do further investigation or
2911 * recovery.
2912 */
5d02a5c1 2913 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
2b1b7e78 2914 dev_warn(dev->ctrl.device,
5d02a5c1 2915 "failed to mark controller live state\n");
e71afda4 2916 result = -ENODEV;
bb8d261e
CH		 2917 goto out;
2918 }
92911a55 2919
0521905e
KB		 2920 if (!dev->attrs_added && !sysfs_create_group(&dev->ctrl.device->kobj,
2921 &nvme_pci_attr_group))
2922 dev->attrs_added = true;
2923
d09f2b45 2924 nvme_start_ctrl(&dev->ctrl);
3cf519b5 2925 return;
f0b50732 2926
4726bcf3
KB		 2927 out_unlock:
2928 mutex_unlock(&dev->shutdown_lock);
3cf519b5 2929 out:
7c1ce408
CK		 2930 if (result)
2931 dev_warn(dev->ctrl.device,
2932 "Removing after probe failure status: %d\n", result);
2933 nvme_remove_dead_ctrl(dev);
f0b50732
KB		 2934}
2935
5c8809e6 2936static void nvme_remove_dead_ctrl_work(struct work_struct *work)
9a6b9458 2937{
5c8809e6 2938 struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
e75ec752 2939 struct pci_dev *pdev = to_pci_dev(dev->dev);
9a6b9458
KB		 2940
2941 if (pci_get_drvdata(pdev))
921920ab 2942 device_release_driver(&pdev->dev);
1673f1f0 2943 nvme_put_ctrl(&dev->ctrl);
9a6b9458
KB		 2944}
2945
1c63dc66 2946static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
9ca97374 2947{
1c63dc66 2948 *val = readl(to_nvme_dev(ctrl)->bar + off);
90667892 2949 return 0;
9ca97374
TH		 2950}
2951
5fd4ce1b 2952static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
4cc06521 2953{
5fd4ce1b
CH		 2954 writel(val, to_nvme_dev(ctrl)->bar + off);
2955 return 0;
2956}
4cc06521 2957
7fd8930f
CH		 2958static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2959{
3a8ecc93 2960 *val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off);
7fd8930f 2961 return 0;
4cc06521
KB		 2962}
2963
97c12223
KB		 2964static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
2965{
2966 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2967
2db24e4a 2968 return snprintf(buf, size, "%s\n", dev_name(&pdev->dev));
97c12223
KB		 2969}
2970
1c63dc66 2971static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
1a353d85 2972 .name = "pcie",
e439bb12 2973 .module = THIS_MODULE,
e0596ab2
LG		 2974 .flags = NVME_F_METADATA_SUPPORTED |
2975 NVME_F_PCI_P2PDMA,
1c63dc66 2976 .reg_read32 = nvme_pci_reg_read32,
5fd4ce1b 2977 .reg_write32 = nvme_pci_reg_write32,
7fd8930f 2978 .reg_read64 = nvme_pci_reg_read64,
1673f1f0 2979 .free_ctrl = nvme_pci_free_ctrl,
f866fc42 2980 .submit_async_event = nvme_pci_submit_async_event,
97c12223 2981 .get_address = nvme_pci_get_address,
1c63dc66 2982};
4cc06521 2983
b00a726a
KB		 2984static int nvme_dev_map(struct nvme_dev *dev)
2985{
b00a726a
KB		 2986 struct pci_dev *pdev = to_pci_dev(dev->dev);
2987
a1f447b3 2988 if (pci_request_mem_regions(pdev, "nvme"))
b00a726a
KB		 2989 return -ENODEV;
2990
97f6ef64 2991 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
b00a726a
KB		 2992 goto release;
2993
9fa196e7 2994 return 0;
b00a726a 2995 release:
9fa196e7
MG		 2996 pci_release_mem_regions(pdev);
2997 return -ENODEV;
b00a726a
KB		 2998}
2999
8427bbc2 3000static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
ff5350a8
AL		 3001{
3002 if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
3003 /*
3004 * Several Samsung devices seem to drop off the PCIe bus
3005 * randomly when APST is on and uses the deepest sleep state.
3006 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
3007 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
3008 * 950 PRO 256GB", but it seems to be restricted to two Dell
3009 * laptops.
3010 */
3011 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
3012 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
3013 dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
3014 return NVME_QUIRK_NO_DEEPEST_PS;
8427bbc2
KHF		 3015 } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
3016 /*
3017 * Samsung SSD 960 EVO drops off the PCIe bus after system
467c77d4
JJ		 3018 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
3019 * within few minutes after bootup on a Coffee Lake board -
3020 * ASUS PRIME Z370-A
8427bbc2
KHF		 3021 */
3022 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
467c77d4
JJ		 3023 (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") ||
3024 dmi_match(DMI_BOARD_NAME, "PRIME Z370-A")))
8427bbc2 3025 return NVME_QUIRK_NO_APST;
1fae37ac
S		 3026 } else if ((pdev->vendor == 0x144d && (pdev->device == 0xa801 ||
3027 pdev->device == 0xa808 || pdev->device == 0xa809)) ||
3028 (pdev->vendor == 0x1e0f && pdev->device == 0x0001)) {
3029 /*
3030 * Forcing to use host managed nvme power settings for
3031 * lowest idle power with quick resume latency on
3032 * Samsung and Toshiba SSDs based on suspend behavior
3033 * on Coffee Lake board for LENOVO C640
3034 */
3035 if ((dmi_match(DMI_BOARD_VENDOR, "LENOVO")) &&
3036 dmi_match(DMI_BOARD_NAME, "LNVNB161216"))
3037 return NVME_QUIRK_SIMPLE_SUSPEND;
ff5350a8
AL		 3038 }
3039
3040 return 0;
3041}
3042
18119775
KB		 3043static void nvme_async_probe(void *data, async_cookie_t cookie)
3044{
3045 struct nvme_dev *dev = data;
80f513b5 3046
bd46a906 3047 flush_work(&dev->ctrl.reset_work);
18119775 3048 flush_work(&dev->ctrl.scan_work);
80f513b5 3049 nvme_put_ctrl(&dev->ctrl);
18119775
KB		 3050}
3051
8d85fce7 3052static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
b60503ba 3053{
a4aea562 3054 int node, result = -ENOMEM;
b60503ba 3055 struct nvme_dev *dev;
ff5350a8 3056 unsigned long quirks = id->driver_data;
943e942e 3057 size_t alloc_size;
b60503ba 3058
a4aea562
MB		 3059 node = dev_to_node(&pdev->dev);
3060 if (node == NUMA_NO_NODE)
2fa84351 3061 set_dev_node(&pdev->dev, first_memory_node);
a4aea562
MB		 3062
3063 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
b60503ba
MW		 3064 if (!dev)
3065 return -ENOMEM;
147b27e4 3066
2a5bcfdd
WZ		 3067 dev->nr_write_queues = write_queues;
3068 dev->nr_poll_queues = poll_queues;
3069 dev->nr_allocated_queues = nvme_max_io_queues(dev) + 1;
3070 dev->queues = kcalloc_node(dev->nr_allocated_queues,
3071 sizeof(struct nvme_queue), GFP_KERNEL, node);
b60503ba
MW		 3072 if (!dev->queues)
3073 goto free;
3074
e75ec752 3075 dev->dev = get_device(&pdev->dev);
9a6b9458 3076 pci_set_drvdata(pdev, dev);
1c63dc66 3077
b00a726a
KB		 3078 result = nvme_dev_map(dev);
3079 if (result)
b00c9b7a 3080 goto put_pci;
b00a726a 3081
d86c4d8e 3082 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
5c8809e6 3083 INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
77bf25ea 3084 mutex_init(&dev->shutdown_lock);
b60503ba 3085
091b6092
MW		 3086 result = nvme_setup_prp_pools(dev);
3087 if (result)
b00c9b7a 3088 goto unmap;
4cc06521 3089
8427bbc2 3090 quirks |= check_vendor_combination_bug(pdev);
ff5350a8 3091
2744d7a0 3092 if (!noacpi && acpi_storage_d3(&pdev->dev)) {
df4f9bc4
DB		 3093 /*
3094 * Some systems use a bios work around to ask for D3 on
3095 * platforms that support kernel managed suspend.
3096 */
3097 dev_info(&pdev->dev,
3098 "platform quirk: setting simple suspend\n");
3099 quirks |= NVME_QUIRK_SIMPLE_SUSPEND;
3100 }
3101
943e942e
JA		 3102 /*
3103 * Double check that our mempool alloc size will cover the biggest
3104 * command we support.
3105 */
b13c6393 3106 alloc_size = nvme_pci_iod_alloc_size();
943e942e
JA		 3107 WARN_ON_ONCE(alloc_size > PAGE_SIZE);
3108
3109 dev->iod_mempool = mempool_create_node(1, mempool_kmalloc,
3110 mempool_kfree,
3111 (void *) alloc_size,
3112 GFP_KERNEL, node);
3113 if (!dev->iod_mempool) {
3114 result = -ENOMEM;
3115 goto release_pools;
3116 }
3117
b6e44b4c
KB		 3118 result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
3119 quirks);
3120 if (result)
3121 goto release_mempool;
3122
1b3c47c1
SG		 3123 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
3124
bd46a906 3125 nvme_reset_ctrl(&dev->ctrl);
18119775 3126 async_schedule(nvme_async_probe, dev);
4caff8fc 3127
b60503ba
MW		 3128 return 0;
3129
b6e44b4c
KB		 3130 release_mempool:
3131 mempool_destroy(dev->iod_mempool);
0877cb0d 3132 release_pools:
091b6092 3133 nvme_release_prp_pools(dev);
b00c9b7a
CJ		 3134 unmap:
3135 nvme_dev_unmap(dev);
a96d4f5c 3136 put_pci:
e75ec752 3137 put_device(dev->dev);
b60503ba
MW		 3138 free:
3139 kfree(dev->queues);
b60503ba
MW		 3140 kfree(dev);
3141 return result;
3142}
3143
775755ed 3144static void nvme_reset_prepare(struct pci_dev *pdev)
f0d54a54 3145{
a6739479 3146 struct nvme_dev *dev = pci_get_drvdata(pdev);
c1ac9a4b
KB		 3147
3148 /*
3149 * We don't need to check the return value from waiting for the reset
3150 * state as pci_dev device lock is held, making it impossible to race
3151 * with ->remove().
3152 */
3153 nvme_disable_prepare_reset(dev, false);
3154 nvme_sync_queues(&dev->ctrl);
775755ed 3155}
f0d54a54 3156
775755ed
CH		 3157static void nvme_reset_done(struct pci_dev *pdev)
3158{
f263fbb8 3159 struct nvme_dev *dev = pci_get_drvdata(pdev);
c1ac9a4b
KB		 3160
3161 if (!nvme_try_sched_reset(&dev->ctrl))
3162 flush_work(&dev->ctrl.reset_work);
f0d54a54
KB		 3163}
3164
09ece142
KB		 3165static void nvme_shutdown(struct pci_dev *pdev)
3166{
3167 struct nvme_dev *dev = pci_get_drvdata(pdev);
4e523547 3168
c1ac9a4b 3169 nvme_disable_prepare_reset(dev, true);
09ece142
KB		 3170}
3171
0521905e
KB		 3172static void nvme_remove_attrs(struct nvme_dev *dev)
3173{
3174 if (dev->attrs_added)
3175 sysfs_remove_group(&dev->ctrl.device->kobj,
3176 &nvme_pci_attr_group);
3177}
3178
f58944e2
KB		 3179/*
3180 * The driver's remove may be called on a device in a partially initialized
3181 * state. This function must not have any dependencies on the device state in
3182 * order to proceed.
3183 */
8d85fce7 3184static void nvme_remove(struct pci_dev *pdev)
b60503ba
MW		 3185{
3186 struct nvme_dev *dev = pci_get_drvdata(pdev);
9a6b9458 3187
bb8d261e 3188 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
9a6b9458 3189 pci_set_drvdata(pdev, NULL);
0ff9d4e1 3190
6db28eda 3191 if (!pci_device_is_present(pdev)) {
0ff9d4e1 3192 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
1d39e692 3193 nvme_dev_disable(dev, true);
6db28eda 3194 }
0ff9d4e1 3195
d86c4d8e 3196 flush_work(&dev->ctrl.reset_work);
d09f2b45
SG		 3197 nvme_stop_ctrl(&dev->ctrl);
3198 nvme_remove_namespaces(&dev->ctrl);
a5cdb68c 3199 nvme_dev_disable(dev, true);
0521905e 3200 nvme_remove_attrs(dev);
87ad72a5 3201 nvme_free_host_mem(dev);
a4aea562 3202 nvme_dev_remove_admin(dev);
a1a5ef99 3203 nvme_free_queues(dev, 0);
9a6b9458 3204 nvme_release_prp_pools(dev);
b00a726a 3205 nvme_dev_unmap(dev);
726612b6 3206 nvme_uninit_ctrl(&dev->ctrl);
b60503ba
MW		 3207}
3208
671a6018 3209#ifdef CONFIG_PM_SLEEP
d916b1be
KB		 3210static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps)
3211{
3212 return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps);
3213}
3214
3215static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps)
3216{
3217 return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL);
3218}
3219
3220static int nvme_resume(struct device *dev)
3221{
3222 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
3223 struct nvme_ctrl *ctrl = &ndev->ctrl;
3224
4eaefe8c 3225 if (ndev->last_ps == U32_MAX ||
d916b1be 3226 nvme_set_power_state(ctrl, ndev->last_ps) != 0)
e5ad96f3
KB		 3227 goto reset;
3228 if (ctrl->hmpre && nvme_setup_host_mem(ndev))
3229 goto reset;
3230
d916b1be 3231 return 0;
e5ad96f3
KB		 3232reset:
3233 return nvme_try_sched_reset(ctrl);
d916b1be
KB		 3234}
3235
cd638946
KB		 3236static int nvme_suspend(struct device *dev)
3237{
3238 struct pci_dev *pdev = to_pci_dev(dev);
3239 struct nvme_dev *ndev = pci_get_drvdata(pdev);
d916b1be
KB		 3240 struct nvme_ctrl *ctrl = &ndev->ctrl;
3241 int ret = -EBUSY;
3242
4eaefe8c
RW		 3243 ndev->last_ps = U32_MAX;
3244
d916b1be
KB		 3245 /*
3246 * The platform does not remove power for a kernel managed suspend so
3247 * use host managed nvme power settings for lowest idle power if
3248 * possible. This should have quicker resume latency than a full device
3249 * shutdown. But if the firmware is involved after the suspend or the
3250 * device does not support any non-default power states, shut down the
3251 * device fully.
4eaefe8c
RW		 3252 *
3253 * If ASPM is not enabled for the device, shut down the device and allow
3254 * the PCI bus layer to put it into D3 in order to take the PCIe link
3255 * down, so as to allow the platform to achieve its minimum low-power
3256 * state (which may not be possible if the link is up).
d916b1be 3257 */
4eaefe8c 3258 if (pm_suspend_via_firmware() || !ctrl->npss ||
cb32de1b 3259 !pcie_aspm_enabled(pdev) ||
c1ac9a4b
KB		 3260 (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND))
3261 return nvme_disable_prepare_reset(ndev, true);
d916b1be
KB		 3262
3263 nvme_start_freeze(ctrl);
3264 nvme_wait_freeze(ctrl);
3265 nvme_sync_queues(ctrl);
3266
5d02a5c1 3267 if (ctrl->state != NVME_CTRL_LIVE)
d916b1be
KB		 3268 goto unfreeze;
3269
e5ad96f3
KB		 3270 /*
3271 * Host memory access may not be successful in a system suspend state,
3272 * but the specification allows the controller to access memory in a
3273 * non-operational power state.
3274 */
3275 if (ndev->hmb) {
3276 ret = nvme_set_host_mem(ndev, 0);
3277 if (ret < 0)
3278 goto unfreeze;
3279 }
3280
d916b1be
KB		 3281 ret = nvme_get_power_state(ctrl, &ndev->last_ps);
3282 if (ret < 0)
3283 goto unfreeze;
3284
7cbb5c6f
ML		 3285 /*
3286 * A saved state prevents pci pm from generically controlling the
3287 * device's power. If we're using protocol specific settings, we don't
3288 * want pci interfering.
3289 */
3290 pci_save_state(pdev);
3291
d916b1be
KB		 3292 ret = nvme_set_power_state(ctrl, ctrl->npss);
3293 if (ret < 0)
3294 goto unfreeze;
3295
3296 if (ret) {
7cbb5c6f
ML		 3297 /* discard the saved state */
3298 pci_load_saved_state(pdev, NULL);
3299
d916b1be
KB		 3300 /*
3301 * Clearing npss forces a controller reset on resume. The
05d3046f 3302 * correct value will be rediscovered then.
d916b1be 3303 */
c1ac9a4b 3304 ret = nvme_disable_prepare_reset(ndev, true);
d916b1be 3305 ctrl->npss = 0;
d916b1be 3306 }
d916b1be
KB		 3307unfreeze:
3308 nvme_unfreeze(ctrl);
3309 return ret;
3310}
3311
3312static int nvme_simple_suspend(struct device *dev)
3313{
3314 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
4e523547 3315
c1ac9a4b 3316 return nvme_disable_prepare_reset(ndev, true);
cd638946
KB		 3317}
3318
d916b1be 3319static int nvme_simple_resume(struct device *dev)
cd638946
KB		 3320{
3321 struct pci_dev *pdev = to_pci_dev(dev);
3322 struct nvme_dev *ndev = pci_get_drvdata(pdev);
cd638946 3323
c1ac9a4b 3324 return nvme_try_sched_reset(&ndev->ctrl);
cd638946
KB		 3325}
3326
21774222 3327static const struct dev_pm_ops nvme_dev_pm_ops = {
d916b1be
KB		 3328 .suspend = nvme_suspend,
3329 .resume = nvme_resume,
3330 .freeze = nvme_simple_suspend,
3331 .thaw = nvme_simple_resume,
3332 .poweroff = nvme_simple_suspend,
3333 .restore = nvme_simple_resume,
3334};
3335#endif /* CONFIG_PM_SLEEP */
b60503ba 3336
a0a3408e
KB		 3337static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
3338 pci_channel_state_t state)
3339{
3340 struct nvme_dev *dev = pci_get_drvdata(pdev);
3341
3342 /*
3343 * A frozen channel requires a reset. When detected, this method will
3344 * shutdown the controller to quiesce. The controller will be restarted
3345 * after the slot reset through driver's slot_reset callback.
3346 */
a0a3408e
KB		 3347 switch (state) {
3348 case pci_channel_io_normal:
3349 return PCI_ERS_RESULT_CAN_RECOVER;
3350 case pci_channel_io_frozen:
d011fb31
KB		 3351 dev_warn(dev->ctrl.device,
3352 "frozen state error detected, reset controller\n");
a5cdb68c 3353 nvme_dev_disable(dev, false);
a0a3408e
KB		 3354 return PCI_ERS_RESULT_NEED_RESET;
3355 case pci_channel_io_perm_failure:
d011fb31
KB		 3356 dev_warn(dev->ctrl.device,
3357 "failure state error detected, request disconnect\n");
a0a3408e
KB		 3358 return PCI_ERS_RESULT_DISCONNECT;
3359 }
3360 return PCI_ERS_RESULT_NEED_RESET;
3361}
3362
3363static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
3364{
3365 struct nvme_dev *dev = pci_get_drvdata(pdev);
3366
1b3c47c1 3367 dev_info(dev->ctrl.device, "restart after slot reset\n");
a0a3408e 3368 pci_restore_state(pdev);
d86c4d8e 3369 nvme_reset_ctrl(&dev->ctrl);
a0a3408e
KB		 3370 return PCI_ERS_RESULT_RECOVERED;
3371}
3372
3373static void nvme_error_resume(struct pci_dev *pdev)
3374{
72cd4cc2
KB		 3375 struct nvme_dev *dev = pci_get_drvdata(pdev);
3376
3377 flush_work(&dev->ctrl.reset_work);
a0a3408e
KB		 3378}
3379
1d352035 3380static const struct pci_error_handlers nvme_err_handler = {
b60503ba 3381 .error_detected = nvme_error_detected,
b60503ba
MW		 3382 .slot_reset = nvme_slot_reset,
3383 .resume = nvme_error_resume,
775755ed
CH		 3384 .reset_prepare = nvme_reset_prepare,
3385 .reset_done = nvme_reset_done,
b60503ba
MW		 3386};
3387
6eb0d698 3388static const struct pci_device_id nvme_id_table[] = {
972b13e2 3389 { PCI_VDEVICE(INTEL, 0x0953), /* Intel 750/P3500/P3600/P3700 */
08095e70 3390 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 3391 NVME_QUIRK_DEALLOCATE_ZEROES, },
972b13e2 3392 { PCI_VDEVICE(INTEL, 0x0a53), /* Intel P3520 */
99466e70 3393 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 3394 NVME_QUIRK_DEALLOCATE_ZEROES, },
972b13e2 3395 { PCI_VDEVICE(INTEL, 0x0a54), /* Intel P4500/P4600 */
99466e70 3396 .driver_data = NVME_QUIRK_STRIPE_SIZE |
25e58af4
WZ		 3397 NVME_QUIRK_DEALLOCATE_ZEROES |
3398 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
972b13e2 3399 { PCI_VDEVICE(INTEL, 0x0a55), /* Dell Express Flash P4600 */
f99cb7af
DWF		 3400 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3401 NVME_QUIRK_DEALLOCATE_ZEROES, },
50af47d0 3402 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */
9abd68ef 3403 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
6c6aa2f2 3404 NVME_QUIRK_MEDIUM_PRIO_SQ |
ce4cc313
DM		 3405 NVME_QUIRK_NO_TEMP_THRESH_CHANGE |
3406 NVME_QUIRK_DISABLE_WRITE_ZEROES, },
6299358d
JD		 3407 { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */
3408 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
540c801c 3409 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */
7b210e4e
CH		 3410 .driver_data = NVME_QUIRK_IDENTIFY_CNS |
3411 NVME_QUIRK_DISABLE_WRITE_ZEROES, },
5bedd3af
CH		 3412 { PCI_DEVICE(0x126f, 0x2263), /* Silicon Motion unidentified */
3413 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST, },
0302ae60 3414 { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */
5e112d3f
JE		 3415 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
3416 NVME_QUIRK_NO_NS_DESC_LIST, },
54adc010
GP		 3417 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
3418 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
8c97eecc
JL		 3419 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */
3420 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
015282c9
WW		 3421 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
3422 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
d554b5e1
MP		 3423 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */
3424 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3425 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */
7ee5c78c 3426 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
abbb5f59 3427 NVME_QUIRK_DISABLE_WRITE_ZEROES|
7ee5c78c 3428 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
c9e95c39
CS		 3429 { PCI_DEVICE(0x1987, 0x5016), /* Phison E16 */
3430 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
6e6a6828
PT		 3431 { PCI_DEVICE(0x1b4b, 0x1092), /* Lexar 256 GB SSD */
3432 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST |
3433 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
08b903b5
MN		 3434 { PCI_DEVICE(0x10ec, 0x5762), /* ADATA SX6000LNP */
3435 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
f03e42c6
GC		 3436 { PCI_DEVICE(0x1cc1, 0x8201), /* ADATA SX8200PNP 512GB */
3437 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3438 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
5611ec2b
KHF		 3439 { PCI_DEVICE(0x1c5c, 0x1504), /* SK Hynix PC400 */
3440 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
02ca079c
KHF		 3441 { PCI_DEVICE(0x15b7, 0x2001), /* Sandisk Skyhawk */
3442 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
89919929
CK		 3443 { PCI_DEVICE(0x1d97, 0x2263), /* SPCC */
3444 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
dc22c1c0
ZB		 3445 { PCI_DEVICE(0x2646, 0x2262), /* KINGSTON SKC2000 NVMe SSD */
3446 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
538e4a8c
TL		 3447 { PCI_DEVICE(0x2646, 0x2263), /* KINGSTON A2000 NVMe SSD */
3448 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
4bdf2603
FS		 3449 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0061),
3450 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3451 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0065),
3452 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3453 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x8061),
3454 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3455 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd00),
3456 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3457 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd01),
3458 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3459 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd02),
3460 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
98f7b86a
AS		 3461 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001),
3462 .driver_data = NVME_QUIRK_SINGLE_VECTOR },
124298bd 3463 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
66341331
BH		 3464 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005),
3465 .driver_data = NVME_QUIRK_SINGLE_VECTOR |
d38e9f04 3466 NVME_QUIRK_128_BYTES_SQES |
a2941f6a
KB		 3467 NVME_QUIRK_SHARED_TAGS |
3468 NVME_QUIRK_SKIP_CID_GEN },
0b85f59d
AS		 3469
3470 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
b60503ba
MW		 3471 { 0, }
3472};
3473MODULE_DEVICE_TABLE(pci, nvme_id_table);
3474
3475static struct pci_driver nvme_driver = {
3476 .name = "nvme",
3477 .id_table = nvme_id_table,
3478 .probe = nvme_probe,
8d85fce7 3479 .remove = nvme_remove,
09ece142 3480 .shutdown = nvme_shutdown,
d916b1be 3481#ifdef CONFIG_PM_SLEEP
cd638946
KB		 3482 .driver = {
3483 .pm = &nvme_dev_pm_ops,
3484 },
d916b1be 3485#endif
74d986ab 3486 .sriov_configure = pci_sriov_configure_simple,
b60503ba
MW		 3487 .err_handler = &nvme_err_handler,
3488};
3489
3490static int __init nvme_init(void)
3491{
81101540
CH		 3492 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
3493 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
3494 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
612b7286 3495 BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2);
17c33167 3496
9a6327d2 3497 return pci_register_driver(&nvme_driver);
b60503ba
MW		 3498}
3499
3500static void __exit nvme_exit(void)
3501{
3502 pci_unregister_driver(&nvme_driver);
03e0f3a6 3503 flush_workqueue(nvme_wq);
b60503ba
MW		 3504}
3505
3506MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3507MODULE_LICENSE("GPL");
c78b4713 3508MODULE_VERSION("1.0");
b60503ba
MW		 3509module_init(nvme_init);
3510module_exit(nvme_exit);
Linux 6.x block layer and io_uring tree(s)