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nvme: implement log page low/high offset and dwords
[linux-2.6-block.git] / drivers / nvme / host / pci.c
CommitLineData
b60503ba
MW		 1/*
2 * NVM Express device driver
6eb0d698 3 * Copyright (c) 2011-2014, Intel Corporation.
b60503ba
MW		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
b60503ba
MW		 13 */
14
a0a3408e 15#include <linux/aer.h>
b60503ba 16#include <linux/blkdev.h>
a4aea562 17#include <linux/blk-mq.h>
dca51e78 18#include <linux/blk-mq-pci.h>
ff5350a8 19#include <linux/dmi.h>
b60503ba
MW		 20#include <linux/init.h>
21#include <linux/interrupt.h>
22#include <linux/io.h>
b60503ba
MW		 23#include <linux/mm.h>
24#include <linux/module.h>
77bf25ea 25#include <linux/mutex.h>
d0877473 26#include <linux/once.h>
b60503ba 27#include <linux/pci.h>
e1e5e564 28#include <linux/t10-pi.h>
b60503ba 29#include <linux/types.h>
2f8e2c87 30#include <linux/io-64-nonatomic-lo-hi.h>
a98e58e5 31#include <linux/sed-opal.h>
797a796a 32
f11bb3e2
CH		 33#include "nvme.h"
34
b60503ba
MW		 35#define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
36#define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
c965809c 37
a7a7cbe3 38#define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc))
9d43cf64 39
58ffacb5
MW		 40static int use_threaded_interrupts;
41module_param(use_threaded_interrupts, int, 0);
42
8ffaadf7
JD		 43static bool use_cmb_sqes = true;
44module_param(use_cmb_sqes, bool, 0644);
45MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
46
87ad72a5
CH		 47static unsigned int max_host_mem_size_mb = 128;
48module_param(max_host_mem_size_mb, uint, 0444);
49MODULE_PARM_DESC(max_host_mem_size_mb,
50 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
1fa6aead 51
a7a7cbe3
CK		 52static unsigned int sgl_threshold = SZ_32K;
53module_param(sgl_threshold, uint, 0644);
54MODULE_PARM_DESC(sgl_threshold,
55 "Use SGLs when average request segment size is larger or equal to "
56 "this size. Use 0 to disable SGLs.");
57
b27c1e68 58static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
59static const struct kernel_param_ops io_queue_depth_ops = {
60 .set = io_queue_depth_set,
61 .get = param_get_int,
62};
63
64static int io_queue_depth = 1024;
65module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
66MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2");
67
1c63dc66
CH		 68struct nvme_dev;
69struct nvme_queue;
b3fffdef 70
a0fa9647 71static void nvme_process_cq(struct nvme_queue *nvmeq);
a5cdb68c 72static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
d4b4ff8e 73
1c63dc66
CH		 74/*
75 * Represents an NVM Express device. Each nvme_dev is a PCI function.
76 */
77struct nvme_dev {
147b27e4 78 struct nvme_queue *queues;
1c63dc66
CH		 79 struct blk_mq_tag_set tagset;
80 struct blk_mq_tag_set admin_tagset;
81 u32 __iomem *dbs;
82 struct device *dev;
83 struct dma_pool *prp_page_pool;
84 struct dma_pool *prp_small_pool;
1c63dc66
CH		 85 unsigned online_queues;
86 unsigned max_qid;
87 int q_depth;
88 u32 db_stride;
1c63dc66 89 void __iomem *bar;
97f6ef64 90 unsigned long bar_mapped_size;
5c8809e6 91 struct work_struct remove_work;
77bf25ea 92 struct mutex shutdown_lock;
1c63dc66 93 bool subsystem;
1c63dc66 94 void __iomem *cmb;
8969f1f8 95 pci_bus_addr_t cmb_bus_addr;
1c63dc66
CH		 96 u64 cmb_size;
97 u32 cmbsz;
202021c1 98 u32 cmbloc;
1c63dc66 99 struct nvme_ctrl ctrl;
db3cbfff 100 struct completion ioq_wait;
87ad72a5
CH		 101
102 /* shadow doorbell buffer support: */
f9f38e33
HK		 103 u32 *dbbuf_dbs;
104 dma_addr_t dbbuf_dbs_dma_addr;
105 u32 *dbbuf_eis;
106 dma_addr_t dbbuf_eis_dma_addr;
87ad72a5
CH		 107
108 /* host memory buffer support: */
109 u64 host_mem_size;
110 u32 nr_host_mem_descs;
4033f35d 111 dma_addr_t host_mem_descs_dma;
87ad72a5
CH		 112 struct nvme_host_mem_buf_desc *host_mem_descs;
113 void **host_mem_desc_bufs;
4d115420 114};
1fa6aead 115
b27c1e68 116static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
117{
118 int n = 0, ret;
119
120 ret = kstrtoint(val, 10, &n);
121 if (ret != 0 || n < 2)
122 return -EINVAL;
123
124 return param_set_int(val, kp);
125}
126
f9f38e33
HK		 127static inline unsigned int sq_idx(unsigned int qid, u32 stride)
128{
129 return qid * 2 * stride;
130}
131
132static inline unsigned int cq_idx(unsigned int qid, u32 stride)
133{
134 return (qid * 2 + 1) * stride;
135}
136
1c63dc66
CH		 137static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
138{
139 return container_of(ctrl, struct nvme_dev, ctrl);
140}
141
b60503ba
MW		 142/*
143 * An NVM Express queue. Each device has at least two (one for admin
144 * commands and one for I/O commands).
145 */
146struct nvme_queue {
147 struct device *q_dmadev;
091b6092 148 struct nvme_dev *dev;
b60503ba
MW		 149 spinlock_t q_lock;
150 struct nvme_command *sq_cmds;
8ffaadf7 151 struct nvme_command __iomem *sq_cmds_io;
b60503ba 152 volatile struct nvme_completion *cqes;
42483228 153 struct blk_mq_tags **tags;
b60503ba
MW		 154 dma_addr_t sq_dma_addr;
155 dma_addr_t cq_dma_addr;
b60503ba
MW		 156 u32 __iomem *q_db;
157 u16 q_depth;
6222d172 158 s16 cq_vector;
b60503ba
MW		 159 u16 sq_tail;
160 u16 cq_head;
c30341dc 161 u16 qid;
e9539f47
MW		 162 u8 cq_phase;
163 u8 cqe_seen;
f9f38e33
HK		 164 u32 *dbbuf_sq_db;
165 u32 *dbbuf_cq_db;
166 u32 *dbbuf_sq_ei;
167 u32 *dbbuf_cq_ei;
b60503ba
MW		 168};
169
71bd150c
CH		 170/*
171 * The nvme_iod describes the data in an I/O, including the list of PRP
172 * entries. You can't see it in this data structure because C doesn't let
f4800d6d 173 * me express that. Use nvme_init_iod to ensure there's enough space
71bd150c
CH		 174 * allocated to store the PRP list.
175 */
176struct nvme_iod {
d49187e9 177 struct nvme_request req;
f4800d6d 178 struct nvme_queue *nvmeq;
a7a7cbe3 179 bool use_sgl;
f4800d6d 180 int aborted;
71bd150c 181 int npages; /* In the PRP list. 0 means small pool in use */
71bd150c
CH		 182 int nents; /* Used in scatterlist */
183 int length; /* Of data, in bytes */
184 dma_addr_t first_dma;
bf684057 185 struct scatterlist meta_sg; /* metadata requires single contiguous buffer */
f4800d6d
CH		 186 struct scatterlist *sg;
187 struct scatterlist inline_sg[0];
b60503ba
MW		 188};
189
190/*
191 * Check we didin't inadvertently grow the command struct
192 */
193static inline void _nvme_check_size(void)
194{
195 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
196 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
197 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
198 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
199 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
f8ebf840 200 BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
c30341dc 201 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
b60503ba 202 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
0add5e8e
JT		 203 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != NVME_IDENTIFY_DATA_SIZE);
204 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != NVME_IDENTIFY_DATA_SIZE);
b60503ba 205 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
6ecec745 206 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
f9f38e33
HK		 207 BUILD_BUG_ON(sizeof(struct nvme_dbbuf) != 64);
208}
209
210static inline unsigned int nvme_dbbuf_size(u32 stride)
211{
212 return ((num_possible_cpus() + 1) * 8 * stride);
213}
214
215static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
216{
217 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
218
219 if (dev->dbbuf_dbs)
220 return 0;
221
222 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
223 &dev->dbbuf_dbs_dma_addr,
224 GFP_KERNEL);
225 if (!dev->dbbuf_dbs)
226 return -ENOMEM;
227 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
228 &dev->dbbuf_eis_dma_addr,
229 GFP_KERNEL);
230 if (!dev->dbbuf_eis) {
231 dma_free_coherent(dev->dev, mem_size,
232 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
233 dev->dbbuf_dbs = NULL;
234 return -ENOMEM;
235 }
236
237 return 0;
238}
239
240static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
241{
242 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
243
244 if (dev->dbbuf_dbs) {
245 dma_free_coherent(dev->dev, mem_size,
246 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
247 dev->dbbuf_dbs = NULL;
248 }
249 if (dev->dbbuf_eis) {
250 dma_free_coherent(dev->dev, mem_size,
251 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
252 dev->dbbuf_eis = NULL;
253 }
254}
255
256static void nvme_dbbuf_init(struct nvme_dev *dev,
257 struct nvme_queue *nvmeq, int qid)
258{
259 if (!dev->dbbuf_dbs || !qid)
260 return;
261
262 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
263 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
264 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
265 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
266}
267
268static void nvme_dbbuf_set(struct nvme_dev *dev)
269{
270 struct nvme_command c;
271
272 if (!dev->dbbuf_dbs)
273 return;
274
275 memset(&c, 0, sizeof(c));
276 c.dbbuf.opcode = nvme_admin_dbbuf;
277 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
278 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
279
280 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
9bdcfb10 281 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
f9f38e33
HK		 282 /* Free memory and continue on */
283 nvme_dbbuf_dma_free(dev);
284 }
285}
286
287static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
288{
289 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
290}
291
292/* Update dbbuf and return true if an MMIO is required */
293static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
294 volatile u32 *dbbuf_ei)
295{
296 if (dbbuf_db) {
297 u16 old_value;
298
299 /*
300 * Ensure that the queue is written before updating
301 * the doorbell in memory
302 */
303 wmb();
304
305 old_value = *dbbuf_db;
306 *dbbuf_db = value;
307
308 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value))
309 return false;
310 }
311
312 return true;
b60503ba
MW		 313}
314
ac3dd5bd
JA		 315/*
316 * Max size of iod being embedded in the request payload
317 */
318#define NVME_INT_PAGES 2
5fd4ce1b 319#define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size)
ac3dd5bd
JA		 320
321/*
322 * Will slightly overestimate the number of pages needed. This is OK
323 * as it only leads to a small amount of wasted memory for the lifetime of
324 * the I/O.
325 */
326static int nvme_npages(unsigned size, struct nvme_dev *dev)
327{
5fd4ce1b
CH		 328 unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size,
329 dev->ctrl.page_size);
ac3dd5bd
JA		 330 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
331}
332
a7a7cbe3
CK		 333/*
334 * Calculates the number of pages needed for the SGL segments. For example a 4k
335 * page can accommodate 256 SGL descriptors.
336 */
337static int nvme_pci_npages_sgl(unsigned int num_seg)
ac3dd5bd 338{
a7a7cbe3 339 return DIV_ROUND_UP(num_seg * sizeof(struct nvme_sgl_desc), PAGE_SIZE);
f4800d6d 340}
ac3dd5bd 341
a7a7cbe3
CK		 342static unsigned int nvme_pci_iod_alloc_size(struct nvme_dev *dev,
343 unsigned int size, unsigned int nseg, bool use_sgl)
f4800d6d 344{
a7a7cbe3
CK		 345 size_t alloc_size;
346
347 if (use_sgl)
348 alloc_size = sizeof(__le64 *) * nvme_pci_npages_sgl(nseg);
349 else
350 alloc_size = sizeof(__le64 *) * nvme_npages(size, dev);
351
352 return alloc_size + sizeof(struct scatterlist) * nseg;
f4800d6d 353}
ac3dd5bd 354
a7a7cbe3 355static unsigned int nvme_pci_cmd_size(struct nvme_dev *dev, bool use_sgl)
f4800d6d 356{
a7a7cbe3
CK		 357 unsigned int alloc_size = nvme_pci_iod_alloc_size(dev,
358 NVME_INT_BYTES(dev), NVME_INT_PAGES,
359 use_sgl);
360
361 return sizeof(struct nvme_iod) + alloc_size;
ac3dd5bd
JA		 362}
363
a4aea562
MB		 364static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
365 unsigned int hctx_idx)
e85248e5 366{
a4aea562 367 struct nvme_dev *dev = data;
147b27e4 368 struct nvme_queue *nvmeq = &dev->queues[0];
a4aea562 369
42483228
KB		 370 WARN_ON(hctx_idx != 0);
371 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
372 WARN_ON(nvmeq->tags);
373
a4aea562 374 hctx->driver_data = nvmeq;
42483228 375 nvmeq->tags = &dev->admin_tagset.tags[0];
a4aea562 376 return 0;
e85248e5
MW		 377}
378
4af0e21c
KB		 379static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
380{
381 struct nvme_queue *nvmeq = hctx->driver_data;
382
383 nvmeq->tags = NULL;
384}
385
a4aea562
MB		 386static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
387 unsigned int hctx_idx)
b60503ba 388{
a4aea562 389 struct nvme_dev *dev = data;
147b27e4 390 struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
a4aea562 391
42483228
KB		 392 if (!nvmeq->tags)
393 nvmeq->tags = &dev->tagset.tags[hctx_idx];
b60503ba 394
42483228 395 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
a4aea562
MB		 396 hctx->driver_data = nvmeq;
397 return 0;
b60503ba
MW		 398}
399
d6296d39
CH		 400static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req,
401 unsigned int hctx_idx, unsigned int numa_node)
b60503ba 402{
d6296d39 403 struct nvme_dev *dev = set->driver_data;
f4800d6d 404 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
0350815a 405 int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0;
147b27e4 406 struct nvme_queue *nvmeq = &dev->queues[queue_idx];
a4aea562
MB		 407
408 BUG_ON(!nvmeq);
f4800d6d 409 iod->nvmeq = nvmeq;
a4aea562
MB		 410 return 0;
411}
412
dca51e78
CH		 413static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
414{
415 struct nvme_dev *dev = set->driver_data;
416
417 return blk_mq_pci_map_queues(set, to_pci_dev(dev->dev));
418}
419
b60503ba 420/**
adf68f21 421 * __nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
b60503ba
MW		 422 * @nvmeq: The queue to use
423 * @cmd: The command to send
424 *
425 * Safe to use from interrupt context
426 */
e3f879bf
SB		 427static void __nvme_submit_cmd(struct nvme_queue *nvmeq,
428 struct nvme_command *cmd)
b60503ba 429{
a4aea562
MB		 430 u16 tail = nvmeq->sq_tail;
431
8ffaadf7
JD		 432 if (nvmeq->sq_cmds_io)
433 memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd));
434 else
435 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
436
b60503ba
MW		 437 if (++tail == nvmeq->q_depth)
438 tail = 0;
f9f38e33
HK		 439 if (nvme_dbbuf_update_and_check_event(tail, nvmeq->dbbuf_sq_db,
440 nvmeq->dbbuf_sq_ei))
441 writel(tail, nvmeq->q_db);
b60503ba 442 nvmeq->sq_tail = tail;
b60503ba
MW		 443}
444
a7a7cbe3 445static void **nvme_pci_iod_list(struct request *req)
b60503ba 446{
f4800d6d 447 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3 448 return (void **)(iod->sg + blk_rq_nr_phys_segments(req));
b60503ba
MW		 449}
450
955b1b5a
MI		 451static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req)
452{
453 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
20469a37 454 int nseg = blk_rq_nr_phys_segments(req);
955b1b5a
MI		 455 unsigned int avg_seg_size;
456
20469a37
KB		 457 if (nseg == 0)
458 return false;
459
460 avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
955b1b5a
MI		 461
462 if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1))))
463 return false;
464 if (!iod->nvmeq->qid)
465 return false;
466 if (!sgl_threshold || avg_seg_size < sgl_threshold)
467 return false;
468 return true;
469}
470
fc17b653 471static blk_status_t nvme_init_iod(struct request *rq, struct nvme_dev *dev)
ac3dd5bd 472{
f4800d6d 473 struct nvme_iod *iod = blk_mq_rq_to_pdu(rq);
f9d03f96 474 int nseg = blk_rq_nr_phys_segments(rq);
b131c61d 475 unsigned int size = blk_rq_payload_bytes(rq);
ac3dd5bd 476
955b1b5a
MI		 477 iod->use_sgl = nvme_pci_use_sgls(dev, rq);
478
f4800d6d 479 if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) {
a7a7cbe3
CK		 480 size_t alloc_size = nvme_pci_iod_alloc_size(dev, size, nseg,
481 iod->use_sgl);
482
483 iod->sg = kmalloc(alloc_size, GFP_ATOMIC);
f4800d6d 484 if (!iod->sg)
fc17b653 485 return BLK_STS_RESOURCE;
f4800d6d
CH		 486 } else {
487 iod->sg = iod->inline_sg;
ac3dd5bd
JA		 488 }
489
f4800d6d
CH		 490 iod->aborted = 0;
491 iod->npages = -1;
492 iod->nents = 0;
493 iod->length = size;
f80ec966 494
fc17b653 495 return BLK_STS_OK;
ac3dd5bd
JA		 496}
497
f4800d6d 498static void nvme_free_iod(struct nvme_dev *dev, struct request *req)
b60503ba 499{
f4800d6d 500 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3
CK		 501 const int last_prp = dev->ctrl.page_size / sizeof(__le64) - 1;
502 dma_addr_t dma_addr = iod->first_dma, next_dma_addr;
503
eca18b23 504 int i;
eca18b23
MW		 505
506 if (iod->npages == 0)
a7a7cbe3
CK		 507 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0],
508 dma_addr);
509
eca18b23 510 for (i = 0; i < iod->npages; i++) {
a7a7cbe3
CK		 511 void *addr = nvme_pci_iod_list(req)[i];
512
513 if (iod->use_sgl) {
514 struct nvme_sgl_desc *sg_list = addr;
515
516 next_dma_addr =
517 le64_to_cpu((sg_list[SGES_PER_PAGE - 1]).addr);
518 } else {
519 __le64 *prp_list = addr;
520
521 next_dma_addr = le64_to_cpu(prp_list[last_prp]);
522 }
523
524 dma_pool_free(dev->prp_page_pool, addr, dma_addr);
525 dma_addr = next_dma_addr;
eca18b23 526 }
ac3dd5bd 527
f4800d6d
CH		 528 if (iod->sg != iod->inline_sg)
529 kfree(iod->sg);
b4ff9c8d
KB		 530}
531
52b68d7e 532#ifdef CONFIG_BLK_DEV_INTEGRITY
e1e5e564
KB		 533static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
534{
535 if (be32_to_cpu(pi->ref_tag) == v)
536 pi->ref_tag = cpu_to_be32(p);
537}
538
539static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
540{
541 if (be32_to_cpu(pi->ref_tag) == p)
542 pi->ref_tag = cpu_to_be32(v);
543}
544
545/**
546 * nvme_dif_remap - remaps ref tags to bip seed and physical lba
547 *
548 * The virtual start sector is the one that was originally submitted by the
549 * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical
550 * start sector may be different. Remap protection information to match the
551 * physical LBA on writes, and back to the original seed on reads.
552 *
553 * Type 0 and 3 do not have a ref tag, so no remapping required.
554 */
555static void nvme_dif_remap(struct request *req,
556 void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
557{
558 struct nvme_ns *ns = req->rq_disk->private_data;
559 struct bio_integrity_payload *bip;
560 struct t10_pi_tuple *pi;
561 void *p, *pmap;
562 u32 i, nlb, ts, phys, virt;
563
564 if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3)
565 return;
566
567 bip = bio_integrity(req->bio);
568 if (!bip)
569 return;
570
571 pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset;
e1e5e564
KB		 572
573 p = pmap;
574 virt = bip_get_seed(bip);
575 phys = nvme_block_nr(ns, blk_rq_pos(req));
576 nlb = (blk_rq_bytes(req) >> ns->lba_shift);
ac6fc48c 577 ts = ns->disk->queue->integrity.tuple_size;
e1e5e564
KB		 578
579 for (i = 0; i < nlb; i++, virt++, phys++) {
580 pi = (struct t10_pi_tuple *)p;
581 dif_swap(phys, virt, pi);
582 p += ts;
583 }
584 kunmap_atomic(pmap);
585}
52b68d7e
KB		 586#else /* CONFIG_BLK_DEV_INTEGRITY */
587static void nvme_dif_remap(struct request *req,
588 void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
589{
590}
591static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
592{
593}
594static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
595{
596}
52b68d7e
KB		 597#endif
598
d0877473
KB		 599static void nvme_print_sgl(struct scatterlist *sgl, int nents)
600{
601 int i;
602 struct scatterlist *sg;
603
604 for_each_sg(sgl, sg, nents, i) {
605 dma_addr_t phys = sg_phys(sg);
606 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
607 "dma_address:%pad dma_length:%d\n",
608 i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
609 sg_dma_len(sg));
610 }
611}
612
a7a7cbe3
CK		 613static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
614 struct request *req, struct nvme_rw_command *cmnd)
ff22b54f 615{
f4800d6d 616 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
99802a7a 617 struct dma_pool *pool;
b131c61d 618 int length = blk_rq_payload_bytes(req);
eca18b23 619 struct scatterlist *sg = iod->sg;
ff22b54f
MW		 620 int dma_len = sg_dma_len(sg);
621 u64 dma_addr = sg_dma_address(sg);
5fd4ce1b 622 u32 page_size = dev->ctrl.page_size;
f137e0f1 623 int offset = dma_addr & (page_size - 1);
e025344c 624 __le64 *prp_list;
a7a7cbe3 625 void **list = nvme_pci_iod_list(req);
e025344c 626 dma_addr_t prp_dma;
eca18b23 627 int nprps, i;
ff22b54f 628
1d090624 629 length -= (page_size - offset);
5228b328
JS		 630 if (length <= 0) {
631 iod->first_dma = 0;
a7a7cbe3 632 goto done;
5228b328 633 }
ff22b54f 634
1d090624 635 dma_len -= (page_size - offset);
ff22b54f 636 if (dma_len) {
1d090624 637 dma_addr += (page_size - offset);
ff22b54f
MW		 638 } else {
639 sg = sg_next(sg);
640 dma_addr = sg_dma_address(sg);
641 dma_len = sg_dma_len(sg);
642 }
643
1d090624 644 if (length <= page_size) {
edd10d33 645 iod->first_dma = dma_addr;
a7a7cbe3 646 goto done;
e025344c
SMM		 647 }
648
1d090624 649 nprps = DIV_ROUND_UP(length, page_size);
99802a7a
MW		 650 if (nprps <= (256 / 8)) {
651 pool = dev->prp_small_pool;
eca18b23 652 iod->npages = 0;
99802a7a
MW		 653 } else {
654 pool = dev->prp_page_pool;
eca18b23 655 iod->npages = 1;
99802a7a
MW		 656 }
657
69d2b571 658 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
b77954cb 659 if (!prp_list) {
edd10d33 660 iod->first_dma = dma_addr;
eca18b23 661 iod->npages = -1;
86eea289 662 return BLK_STS_RESOURCE;
b77954cb 663 }
eca18b23
MW		 664 list[0] = prp_list;
665 iod->first_dma = prp_dma;
e025344c
SMM		 666 i = 0;
667 for (;;) {
1d090624 668 if (i == page_size >> 3) {
e025344c 669 __le64 *old_prp_list = prp_list;
69d2b571 670 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
eca18b23 671 if (!prp_list)
86eea289 672 return BLK_STS_RESOURCE;
eca18b23 673 list[iod->npages++] = prp_list;
7523d834
MW		 674 prp_list[0] = old_prp_list[i - 1];
675 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
676 i = 1;
e025344c
SMM		 677 }
678 prp_list[i++] = cpu_to_le64(dma_addr);
1d090624
KB		 679 dma_len -= page_size;
680 dma_addr += page_size;
681 length -= page_size;
e025344c
SMM		 682 if (length <= 0)
683 break;
684 if (dma_len > 0)
685 continue;
86eea289
KB		 686 if (unlikely(dma_len < 0))
687 goto bad_sgl;
e025344c
SMM		 688 sg = sg_next(sg);
689 dma_addr = sg_dma_address(sg);
690 dma_len = sg_dma_len(sg);
ff22b54f
MW		 691 }
692
a7a7cbe3
CK		 693done:
694 cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
695 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
696
86eea289
KB		 697 return BLK_STS_OK;
698
699 bad_sgl:
d0877473
KB		 700 WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents),
701 "Invalid SGL for payload:%d nents:%d\n",
702 blk_rq_payload_bytes(req), iod->nents);
86eea289 703 return BLK_STS_IOERR;
ff22b54f
MW		 704}
705
a7a7cbe3
CK		 706static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
707 struct scatterlist *sg)
708{
709 sge->addr = cpu_to_le64(sg_dma_address(sg));
710 sge->length = cpu_to_le32(sg_dma_len(sg));
711 sge->type = NVME_SGL_FMT_DATA_DESC << 4;
712}
713
714static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
715 dma_addr_t dma_addr, int entries)
716{
717 sge->addr = cpu_to_le64(dma_addr);
718 if (entries < SGES_PER_PAGE) {
719 sge->length = cpu_to_le32(entries * sizeof(*sge));
720 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
721 } else {
722 sge->length = cpu_to_le32(PAGE_SIZE);
723 sge->type = NVME_SGL_FMT_SEG_DESC << 4;
724 }
725}
726
727static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
b0f2853b 728 struct request *req, struct nvme_rw_command *cmd, int entries)
a7a7cbe3
CK		 729{
730 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3
CK		 731 struct dma_pool *pool;
732 struct nvme_sgl_desc *sg_list;
733 struct scatterlist *sg = iod->sg;
a7a7cbe3 734 dma_addr_t sgl_dma;
b0f2853b 735 int i = 0;
a7a7cbe3 736
a7a7cbe3
CK		 737 /* setting the transfer type as SGL */
738 cmd->flags = NVME_CMD_SGL_METABUF;
739
b0f2853b 740 if (entries == 1) {
a7a7cbe3
CK		 741 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
742 return BLK_STS_OK;
743 }
744
745 if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
746 pool = dev->prp_small_pool;
747 iod->npages = 0;
748 } else {
749 pool = dev->prp_page_pool;
750 iod->npages = 1;
751 }
752
753 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
754 if (!sg_list) {
755 iod->npages = -1;
756 return BLK_STS_RESOURCE;
757 }
758
759 nvme_pci_iod_list(req)[0] = sg_list;
760 iod->first_dma = sgl_dma;
761
762 nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
763
764 do {
765 if (i == SGES_PER_PAGE) {
766 struct nvme_sgl_desc *old_sg_desc = sg_list;
767 struct nvme_sgl_desc *link = &old_sg_desc[i - 1];
768
769 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
770 if (!sg_list)
771 return BLK_STS_RESOURCE;
772
773 i = 0;
774 nvme_pci_iod_list(req)[iod->npages++] = sg_list;
775 sg_list[i++] = *link;
776 nvme_pci_sgl_set_seg(link, sgl_dma, entries);
777 }
778
779 nvme_pci_sgl_set_data(&sg_list[i++], sg);
a7a7cbe3 780 sg = sg_next(sg);
b0f2853b 781 } while (--entries > 0);
a7a7cbe3 782
a7a7cbe3
CK		 783 return BLK_STS_OK;
784}
785
fc17b653 786static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
b131c61d 787 struct nvme_command *cmnd)
d29ec824 788{
f4800d6d 789 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
ba1ca37e
CH		 790 struct request_queue *q = req->q;
791 enum dma_data_direction dma_dir = rq_data_dir(req) ?
792 DMA_TO_DEVICE : DMA_FROM_DEVICE;
fc17b653 793 blk_status_t ret = BLK_STS_IOERR;
b0f2853b 794 int nr_mapped;
d29ec824 795
f9d03f96 796 sg_init_table(iod->sg, blk_rq_nr_phys_segments(req));
ba1ca37e
CH		 797 iod->nents = blk_rq_map_sg(q, req, iod->sg);
798 if (!iod->nents)
799 goto out;
d29ec824 800
fc17b653 801 ret = BLK_STS_RESOURCE;
b0f2853b
CH		 802 nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, dma_dir,
803 DMA_ATTR_NO_WARN);
804 if (!nr_mapped)
ba1ca37e 805 goto out;
d29ec824 806
955b1b5a 807 if (iod->use_sgl)
b0f2853b 808 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped);
a7a7cbe3
CK		 809 else
810 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
811
86eea289 812 if (ret != BLK_STS_OK)
ba1ca37e 813 goto out_unmap;
0e5e4f0e 814
fc17b653 815 ret = BLK_STS_IOERR;
ba1ca37e
CH		 816 if (blk_integrity_rq(req)) {
817 if (blk_rq_count_integrity_sg(q, req->bio) != 1)
818 goto out_unmap;
0e5e4f0e 819
bf684057
CH		 820 sg_init_table(&iod->meta_sg, 1);
821 if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1)
ba1ca37e 822 goto out_unmap;
0e5e4f0e 823
b5d8af5b 824 if (req_op(req) == REQ_OP_WRITE)
ba1ca37e 825 nvme_dif_remap(req, nvme_dif_prep);
0e5e4f0e 826
bf684057 827 if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir))
ba1ca37e 828 goto out_unmap;
d29ec824 829 }
00df5cb4 830
ba1ca37e 831 if (blk_integrity_rq(req))
bf684057 832 cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg));
fc17b653 833 return BLK_STS_OK;
00df5cb4 834
ba1ca37e
CH		 835out_unmap:
836 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
837out:
838 return ret;
00df5cb4
MW		 839}
840
f4800d6d 841static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
b60503ba 842{
f4800d6d 843 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
d4f6c3ab
CH		 844 enum dma_data_direction dma_dir = rq_data_dir(req) ?
845 DMA_TO_DEVICE : DMA_FROM_DEVICE;
846
847 if (iod->nents) {
848 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
849 if (blk_integrity_rq(req)) {
b5d8af5b 850 if (req_op(req) == REQ_OP_READ)
d4f6c3ab 851 nvme_dif_remap(req, nvme_dif_complete);
bf684057 852 dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir);
e1e5e564 853 }
e19b127f 854 }
e1e5e564 855
f9d03f96 856 nvme_cleanup_cmd(req);
f4800d6d 857 nvme_free_iod(dev, req);
d4f6c3ab 858}
b60503ba 859
d29ec824
CH		 860/*
861 * NOTE: ns is NULL when called on the admin queue.
862 */
fc17b653 863static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
a4aea562 864 const struct blk_mq_queue_data *bd)
edd10d33 865{
a4aea562
MB		 866 struct nvme_ns *ns = hctx->queue->queuedata;
867 struct nvme_queue *nvmeq = hctx->driver_data;
d29ec824 868 struct nvme_dev *dev = nvmeq->dev;
a4aea562 869 struct request *req = bd->rq;
ba1ca37e 870 struct nvme_command cmnd;
ebe6d874 871 blk_status_t ret;
e1e5e564 872
f9d03f96 873 ret = nvme_setup_cmd(ns, req, &cmnd);
fc17b653 874 if (ret)
f4800d6d 875 return ret;
a4aea562 876
b131c61d 877 ret = nvme_init_iod(req, dev);
fc17b653 878 if (ret)
f9d03f96 879 goto out_free_cmd;
a4aea562 880
fc17b653 881 if (blk_rq_nr_phys_segments(req)) {
b131c61d 882 ret = nvme_map_data(dev, req, &cmnd);
fc17b653
CH		 883 if (ret)
884 goto out_cleanup_iod;
885 }
a4aea562 886
aae239e1 887 blk_mq_start_request(req);
a4aea562 888
ba1ca37e 889 spin_lock_irq(&nvmeq->q_lock);
ae1fba20 890 if (unlikely(nvmeq->cq_vector < 0)) {
fc17b653 891 ret = BLK_STS_IOERR;
ae1fba20 892 spin_unlock_irq(&nvmeq->q_lock);
f9d03f96 893 goto out_cleanup_iod;
ae1fba20 894 }
ba1ca37e 895 __nvme_submit_cmd(nvmeq, &cmnd);
a4aea562
MB		 896 nvme_process_cq(nvmeq);
897 spin_unlock_irq(&nvmeq->q_lock);
fc17b653 898 return BLK_STS_OK;
f9d03f96 899out_cleanup_iod:
f4800d6d 900 nvme_free_iod(dev, req);
f9d03f96
CH		 901out_free_cmd:
902 nvme_cleanup_cmd(req);
ba1ca37e 903 return ret;
b60503ba 904}
e1e5e564 905
77f02a7a 906static void nvme_pci_complete_rq(struct request *req)
eee417b0 907{
f4800d6d 908 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a4aea562 909
77f02a7a
CH		 910 nvme_unmap_data(iod->nvmeq->dev, req);
911 nvme_complete_rq(req);
b60503ba
MW		 912}
913
d783e0bd
MR		 914/* We read the CQE phase first to check if the rest of the entry is valid */
915static inline bool nvme_cqe_valid(struct nvme_queue *nvmeq, u16 head,
916 u16 phase)
917{
918 return (le16_to_cpu(nvmeq->cqes[head].status) & 1) == phase;
919}
920
eb281c82 921static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
b60503ba 922{
eb281c82 923 u16 head = nvmeq->cq_head;
adf68f21 924
eb281c82
SG		 925 if (likely(nvmeq->cq_vector >= 0)) {
926 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
927 nvmeq->dbbuf_cq_ei))
928 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
929 }
930}
aae239e1 931
83a12fb7
SG		 932static inline void nvme_handle_cqe(struct nvme_queue *nvmeq,
933 struct nvme_completion *cqe)
934{
935 struct request *req;
adf68f21 936
83a12fb7
SG		 937 if (unlikely(cqe->command_id >= nvmeq->q_depth)) {
938 dev_warn(nvmeq->dev->ctrl.device,
939 "invalid id %d completed on queue %d\n",
940 cqe->command_id, le16_to_cpu(cqe->sq_id));
941 return;
b60503ba
MW		 942 }
943
83a12fb7
SG		 944 /*
945 * AEN requests are special as they don't time out and can
946 * survive any kind of queue freeze and often don't respond to
947 * aborts. We don't even bother to allocate a struct request
948 * for them but rather special case them here.
949 */
950 if (unlikely(nvmeq->qid == 0 &&
38dabe21 951 cqe->command_id >= NVME_AQ_BLK_MQ_DEPTH)) {
83a12fb7
SG		 952 nvme_complete_async_event(&nvmeq->dev->ctrl,
953 cqe->status, &cqe->result);
a0fa9647 954 return;
83a12fb7 955 }
b60503ba 956
e9d8a0fd 957 nvmeq->cqe_seen = 1;
83a12fb7
SG		 958 req = blk_mq_tag_to_rq(*nvmeq->tags, cqe->command_id);
959 nvme_end_request(req, cqe->status, cqe->result);
960}
b60503ba 961
920d13a8
SG		 962static inline bool nvme_read_cqe(struct nvme_queue *nvmeq,
963 struct nvme_completion *cqe)
b60503ba 964{
920d13a8
SG		 965 if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase)) {
966 *cqe = nvmeq->cqes[nvmeq->cq_head];
adf68f21 967
920d13a8
SG		 968 if (++nvmeq->cq_head == nvmeq->q_depth) {
969 nvmeq->cq_head = 0;
970 nvmeq->cq_phase = !nvmeq->cq_phase;
b60503ba 971 }
920d13a8 972 return true;
b60503ba 973 }
920d13a8 974 return false;
a0fa9647
JA		 975}
976
977static void nvme_process_cq(struct nvme_queue *nvmeq)
978{
920d13a8
SG		 979 struct nvme_completion cqe;
980 int consumed = 0;
b60503ba 981
920d13a8
SG		 982 while (nvme_read_cqe(nvmeq, &cqe)) {
983 nvme_handle_cqe(nvmeq, &cqe);
984 consumed++;
920d13a8 985 }
eb281c82 986
e9d8a0fd 987 if (consumed)
920d13a8 988 nvme_ring_cq_doorbell(nvmeq);
b60503ba
MW		 989}
990
991static irqreturn_t nvme_irq(int irq, void *data)
58ffacb5
MW		 992{
993 irqreturn_t result;
994 struct nvme_queue *nvmeq = data;
995 spin_lock(&nvmeq->q_lock);
e9539f47
MW		 996 nvme_process_cq(nvmeq);
997 result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE;
998 nvmeq->cqe_seen = 0;
58ffacb5
MW		 999 spin_unlock(&nvmeq->q_lock);
1000 return result;
1001}
1002
1003static irqreturn_t nvme_irq_check(int irq, void *data)
1004{
1005 struct nvme_queue *nvmeq = data;
d783e0bd
MR		 1006 if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase))
1007 return IRQ_WAKE_THREAD;
1008 return IRQ_NONE;
58ffacb5
MW		 1009}
1010
7776db1c 1011static int __nvme_poll(struct nvme_queue *nvmeq, unsigned int tag)
a0fa9647 1012{
442e19b7
SG		 1013 struct nvme_completion cqe;
1014 int found = 0, consumed = 0;
a0fa9647 1015
442e19b7
SG		 1016 if (!nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase))
1017 return 0;
a0fa9647 1018
442e19b7
SG		 1019 spin_lock_irq(&nvmeq->q_lock);
1020 while (nvme_read_cqe(nvmeq, &cqe)) {
1021 nvme_handle_cqe(nvmeq, &cqe);
1022 consumed++;
1023
1024 if (tag == cqe.command_id) {
1025 found = 1;
1026 break;
1027 }
1028 }
1029
1030 if (consumed)
1031 nvme_ring_cq_doorbell(nvmeq);
1032 spin_unlock_irq(&nvmeq->q_lock);
1033
1034 return found;
a0fa9647
JA		 1035}
1036
7776db1c
KB		 1037static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag)
1038{
1039 struct nvme_queue *nvmeq = hctx->driver_data;
1040
1041 return __nvme_poll(nvmeq, tag);
1042}
1043
ad22c355 1044static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
b60503ba 1045{
f866fc42 1046 struct nvme_dev *dev = to_nvme_dev(ctrl);
147b27e4 1047 struct nvme_queue *nvmeq = &dev->queues[0];
a4aea562 1048 struct nvme_command c;
b60503ba 1049
a4aea562
MB		 1050 memset(&c, 0, sizeof(c));
1051 c.common.opcode = nvme_admin_async_event;
ad22c355 1052 c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
3c0cf138 1053
9396dec9 1054 spin_lock_irq(&nvmeq->q_lock);
f866fc42 1055 __nvme_submit_cmd(nvmeq, &c);
9396dec9 1056 spin_unlock_irq(&nvmeq->q_lock);
f705f837
CH		 1057}
1058
b60503ba 1059static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
f705f837 1060{
b60503ba
MW		 1061 struct nvme_command c;
1062
1063 memset(&c, 0, sizeof(c));
1064 c.delete_queue.opcode = opcode;
1065 c.delete_queue.qid = cpu_to_le16(id);
1066
1c63dc66 1067 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1068}
1069
b60503ba
MW		 1070static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
1071 struct nvme_queue *nvmeq)
1072{
b60503ba
MW		 1073 struct nvme_command c;
1074 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
1075
d29ec824 1076 /*
16772ae6 1077 * Note: we (ab)use the fact that the prp fields survive if no data
d29ec824
CH		 1078 * is attached to the request.
1079 */
b60503ba
MW		 1080 memset(&c, 0, sizeof(c));
1081 c.create_cq.opcode = nvme_admin_create_cq;
1082 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1083 c.create_cq.cqid = cpu_to_le16(qid);
1084 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1085 c.create_cq.cq_flags = cpu_to_le16(flags);
1086 c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
1087
1c63dc66 1088 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1089}
1090
1091static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1092 struct nvme_queue *nvmeq)
1093{
b60503ba 1094 struct nvme_command c;
81c1cd98 1095 int flags = NVME_QUEUE_PHYS_CONTIG;
b60503ba 1096
d29ec824 1097 /*
16772ae6 1098 * Note: we (ab)use the fact that the prp fields survive if no data
d29ec824
CH		 1099 * is attached to the request.
1100 */
b60503ba
MW		 1101 memset(&c, 0, sizeof(c));
1102 c.create_sq.opcode = nvme_admin_create_sq;
1103 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1104 c.create_sq.sqid = cpu_to_le16(qid);
1105 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1106 c.create_sq.sq_flags = cpu_to_le16(flags);
1107 c.create_sq.cqid = cpu_to_le16(qid);
1108
1c63dc66 1109 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1110}
1111
1112static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1113{
1114 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1115}
1116
1117static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1118{
1119 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1120}
1121
2a842aca 1122static void abort_endio(struct request *req, blk_status_t error)
bc5fc7e4 1123{
f4800d6d
CH		 1124 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1125 struct nvme_queue *nvmeq = iod->nvmeq;
e44ac588 1126
27fa9bc5
CH		 1127 dev_warn(nvmeq->dev->ctrl.device,
1128 "Abort status: 0x%x", nvme_req(req)->status);
e7a2a87d 1129 atomic_inc(&nvmeq->dev->ctrl.abort_limit);
e7a2a87d 1130 blk_mq_free_request(req);
bc5fc7e4
MW		 1131}
1132
b2a0eb1a
KB		 1133static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1134{
1135
1136 /* If true, indicates loss of adapter communication, possibly by a
1137 * NVMe Subsystem reset.
1138 */
1139 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1140
ad70062c
JW		 1141 /* If there is a reset/reinit ongoing, we shouldn't reset again. */
1142 switch (dev->ctrl.state) {
1143 case NVME_CTRL_RESETTING:
ad6a0a52 1144 case NVME_CTRL_CONNECTING:
b2a0eb1a 1145 return false;
ad70062c
JW		 1146 default:
1147 break;
1148 }
b2a0eb1a
KB		 1149
1150 /* We shouldn't reset unless the controller is on fatal error state
1151 * _or_ if we lost the communication with it.
1152 */
1153 if (!(csts & NVME_CSTS_CFS) && !nssro)
1154 return false;
1155
1156 /* If PCI error recovery process is happening, we cannot reset or
1157 * the recovery mechanism will surely fail.
1158 */
1159 if (pci_channel_offline(to_pci_dev(dev->dev)))
1160 return false;
1161
1162 return true;
1163}
1164
1165static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1166{
1167 /* Read a config register to help see what died. */
1168 u16 pci_status;
1169 int result;
1170
1171 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1172 &pci_status);
1173 if (result == PCIBIOS_SUCCESSFUL)
1174 dev_warn(dev->ctrl.device,
1175 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1176 csts, pci_status);
1177 else
1178 dev_warn(dev->ctrl.device,
1179 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1180 csts, result);
1181}
1182
31c7c7d2 1183static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
c30341dc 1184{
f4800d6d
CH		 1185 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1186 struct nvme_queue *nvmeq = iod->nvmeq;
c30341dc 1187 struct nvme_dev *dev = nvmeq->dev;
a4aea562 1188 struct request *abort_req;
a4aea562 1189 struct nvme_command cmd;
b2a0eb1a
KB		 1190 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1191
1192 /*
1193 * Reset immediately if the controller is failed
1194 */
1195 if (nvme_should_reset(dev, csts)) {
1196 nvme_warn_reset(dev, csts);
1197 nvme_dev_disable(dev, false);
d86c4d8e 1198 nvme_reset_ctrl(&dev->ctrl);
b2a0eb1a
KB		 1199 return BLK_EH_HANDLED;
1200 }
c30341dc 1201
7776db1c
KB		 1202 /*
1203 * Did we miss an interrupt?
1204 */
1205 if (__nvme_poll(nvmeq, req->tag)) {
1206 dev_warn(dev->ctrl.device,
1207 "I/O %d QID %d timeout, completion polled\n",
1208 req->tag, nvmeq->qid);
1209 return BLK_EH_HANDLED;
1210 }
1211
31c7c7d2 1212 /*
fd634f41
CH		 1213 * Shutdown immediately if controller times out while starting. The
1214 * reset work will see the pci device disabled when it gets the forced
1215 * cancellation error. All outstanding requests are completed on
1216 * shutdown, so we return BLK_EH_HANDLED.
1217 */
4244140d
KB		 1218 switch (dev->ctrl.state) {
1219 case NVME_CTRL_CONNECTING:
1220 case NVME_CTRL_RESETTING:
1b3c47c1 1221 dev_warn(dev->ctrl.device,
fd634f41
CH		 1222 "I/O %d QID %d timeout, disable controller\n",
1223 req->tag, nvmeq->qid);
a5cdb68c 1224 nvme_dev_disable(dev, false);
27fa9bc5 1225 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
fd634f41 1226 return BLK_EH_HANDLED;
4244140d
KB		 1227 default:
1228 break;
c30341dc
KB		 1229 }
1230
fd634f41
CH		 1231 /*
1232 * Shutdown the controller immediately and schedule a reset if the
1233 * command was already aborted once before and still hasn't been
1234 * returned to the driver, or if this is the admin queue.
31c7c7d2 1235 */
f4800d6d 1236 if (!nvmeq->qid || iod->aborted) {
1b3c47c1 1237 dev_warn(dev->ctrl.device,
e1569a16
KB		 1238 "I/O %d QID %d timeout, reset controller\n",
1239 req->tag, nvmeq->qid);
a5cdb68c 1240 nvme_dev_disable(dev, false);
d86c4d8e 1241 nvme_reset_ctrl(&dev->ctrl);
c30341dc 1242
e1569a16
KB		 1243 /*
1244 * Mark the request as handled, since the inline shutdown
1245 * forces all outstanding requests to complete.
1246 */
27fa9bc5 1247 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
e1569a16 1248 return BLK_EH_HANDLED;
c30341dc 1249 }
c30341dc 1250
e7a2a87d 1251 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
6bf25d16 1252 atomic_inc(&dev->ctrl.abort_limit);
31c7c7d2 1253 return BLK_EH_RESET_TIMER;
6bf25d16 1254 }
7bf7d778 1255 iod->aborted = 1;
a4aea562 1256
c30341dc
KB		 1257 memset(&cmd, 0, sizeof(cmd));
1258 cmd.abort.opcode = nvme_admin_abort_cmd;
a4aea562 1259 cmd.abort.cid = req->tag;
c30341dc 1260 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
c30341dc 1261
1b3c47c1
SG		 1262 dev_warn(nvmeq->dev->ctrl.device,
1263 "I/O %d QID %d timeout, aborting\n",
1264 req->tag, nvmeq->qid);
e7a2a87d
CH		 1265
1266 abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
eb71f435 1267 BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
e7a2a87d
CH		 1268 if (IS_ERR(abort_req)) {
1269 atomic_inc(&dev->ctrl.abort_limit);
1270 return BLK_EH_RESET_TIMER;
1271 }
1272
1273 abort_req->timeout = ADMIN_TIMEOUT;
1274 abort_req->end_io_data = NULL;
1275 blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio);
c30341dc 1276
31c7c7d2
CH		 1277 /*
1278 * The aborted req will be completed on receiving the abort req.
1279 * We enable the timer again. If hit twice, it'll cause a device reset,
1280 * as the device then is in a faulty state.
1281 */
1282 return BLK_EH_RESET_TIMER;
c30341dc
KB		 1283}
1284
a4aea562
MB		 1285static void nvme_free_queue(struct nvme_queue *nvmeq)
1286{
9e866774
MW		 1287 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1288 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
8ffaadf7
JD		 1289 if (nvmeq->sq_cmds)
1290 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
9e866774 1291 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
9e866774
MW		 1292}
1293
a1a5ef99 1294static void nvme_free_queues(struct nvme_dev *dev, int lowest)
22404274
KB		 1295{
1296 int i;
1297
d858e5f0 1298 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
d858e5f0 1299 dev->ctrl.queue_count--;
147b27e4 1300 nvme_free_queue(&dev->queues[i]);
121c7ad4 1301 }
22404274
KB		 1302}
1303
4d115420
KB		 1304/**
1305 * nvme_suspend_queue - put queue into suspended state
1306 * @nvmeq - queue to suspend
4d115420
KB		 1307 */
1308static int nvme_suspend_queue(struct nvme_queue *nvmeq)
b60503ba 1309{
2b25d981 1310 int vector;
b60503ba 1311
a09115b2 1312 spin_lock_irq(&nvmeq->q_lock);
2b25d981
KB		 1313 if (nvmeq->cq_vector == -1) {
1314 spin_unlock_irq(&nvmeq->q_lock);
1315 return 1;
1316 }
0ff199cb 1317 vector = nvmeq->cq_vector;
42f61420 1318 nvmeq->dev->online_queues--;
2b25d981 1319 nvmeq->cq_vector = -1;
a09115b2
MW		 1320 spin_unlock_irq(&nvmeq->q_lock);
1321
1c63dc66 1322 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
c81545f9 1323 blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q);
6df3dbc8 1324
0ff199cb 1325 pci_free_irq(to_pci_dev(nvmeq->dev->dev), vector, nvmeq);
b60503ba 1326
4d115420
KB		 1327 return 0;
1328}
b60503ba 1329
a5cdb68c 1330static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
4d115420 1331{
147b27e4 1332 struct nvme_queue *nvmeq = &dev->queues[0];
4d115420 1333
a5cdb68c
KB		 1334 if (shutdown)
1335 nvme_shutdown_ctrl(&dev->ctrl);
1336 else
20d0dfe6 1337 nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap);
07836e65
KB		 1338
1339 spin_lock_irq(&nvmeq->q_lock);
1340 nvme_process_cq(nvmeq);
1341 spin_unlock_irq(&nvmeq->q_lock);
b60503ba
MW		 1342}
1343
8ffaadf7
JD		 1344static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1345 int entry_size)
1346{
1347 int q_depth = dev->q_depth;
5fd4ce1b
CH		 1348 unsigned q_size_aligned = roundup(q_depth * entry_size,
1349 dev->ctrl.page_size);
8ffaadf7
JD		 1350
1351 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
c45f5c99 1352 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
5fd4ce1b 1353 mem_per_q = round_down(mem_per_q, dev->ctrl.page_size);
c45f5c99 1354 q_depth = div_u64(mem_per_q, entry_size);
8ffaadf7
JD		 1355
1356 /*
1357 * Ensure the reduced q_depth is above some threshold where it
1358 * would be better to map queues in system memory with the
1359 * original depth
1360 */
1361 if (q_depth < 64)
1362 return -ENOMEM;
1363 }
1364
1365 return q_depth;
1366}
1367
1368static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1369 int qid, int depth)
1370{
815c6704
KB		 1371 /* CMB SQEs will be mapped before creation */
1372 if (qid && dev->cmb && use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS))
1373 return 0;
8ffaadf7 1374
815c6704
KB		 1375 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
1376 &nvmeq->sq_dma_addr, GFP_KERNEL);
1377 if (!nvmeq->sq_cmds)
1378 return -ENOMEM;
8ffaadf7
JD		 1379 return 0;
1380}
1381
147b27e4
SG		 1382static int nvme_alloc_queue(struct nvme_dev *dev, int qid,
1383 int depth, int node)
b60503ba 1384{
147b27e4 1385 struct nvme_queue *nvmeq = &dev->queues[qid];
b60503ba 1386
62314e40
KB		 1387 if (dev->ctrl.queue_count > qid)
1388 return 0;
b60503ba 1389
e75ec752 1390 nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth),
4d51abf9 1391 &nvmeq->cq_dma_addr, GFP_KERNEL);
b60503ba
MW		 1392 if (!nvmeq->cqes)
1393 goto free_nvmeq;
b60503ba 1394
8ffaadf7 1395 if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth))
b60503ba
MW		 1396 goto free_cqdma;
1397
e75ec752 1398 nvmeq->q_dmadev = dev->dev;
091b6092 1399 nvmeq->dev = dev;
b60503ba
MW		 1400 spin_lock_init(&nvmeq->q_lock);
1401 nvmeq->cq_head = 0;
82123460 1402 nvmeq->cq_phase = 1;
b80d5ccc 1403 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
b60503ba 1404 nvmeq->q_depth = depth;
c30341dc 1405 nvmeq->qid = qid;
758dd7fd 1406 nvmeq->cq_vector = -1;
d858e5f0 1407 dev->ctrl.queue_count++;
36a7e993 1408
147b27e4 1409 return 0;
b60503ba
MW		 1410
1411 free_cqdma:
e75ec752 1412 dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes,
b60503ba
MW		 1413 nvmeq->cq_dma_addr);
1414 free_nvmeq:
147b27e4 1415 return -ENOMEM;
b60503ba
MW		 1416}
1417
dca51e78 1418static int queue_request_irq(struct nvme_queue *nvmeq)
3001082c 1419{
0ff199cb
CH		 1420 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1421 int nr = nvmeq->dev->ctrl.instance;
1422
1423 if (use_threaded_interrupts) {
1424 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1425 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1426 } else {
1427 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1428 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1429 }
3001082c
MW		 1430}
1431
22404274 1432static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
b60503ba 1433{
22404274 1434 struct nvme_dev *dev = nvmeq->dev;
b60503ba 1435
7be50e93 1436 spin_lock_irq(&nvmeq->q_lock);
22404274
KB		 1437 nvmeq->sq_tail = 0;
1438 nvmeq->cq_head = 0;
1439 nvmeq->cq_phase = 1;
b80d5ccc 1440 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
22404274 1441 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
f9f38e33 1442 nvme_dbbuf_init(dev, nvmeq, qid);
42f61420 1443 dev->online_queues++;
7be50e93 1444 spin_unlock_irq(&nvmeq->q_lock);
22404274
KB		 1445}
1446
1447static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1448{
1449 struct nvme_dev *dev = nvmeq->dev;
1450 int result;
3f85d50b 1451
815c6704
KB		 1452 if (dev->cmb && use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
1453 unsigned offset = (qid - 1) * roundup(SQ_SIZE(nvmeq->q_depth),
1454 dev->ctrl.page_size);
1455 nvmeq->sq_dma_addr = dev->cmb_bus_addr + offset;
1456 nvmeq->sq_cmds_io = dev->cmb + offset;
1457 }
1458
2b25d981 1459 nvmeq->cq_vector = qid - 1;
b60503ba
MW		 1460 result = adapter_alloc_cq(dev, qid, nvmeq);
1461 if (result < 0)
f25a2dfc 1462 goto release_vector;
b60503ba
MW		 1463
1464 result = adapter_alloc_sq(dev, qid, nvmeq);
1465 if (result < 0)
1466 goto release_cq;
1467
161b8be2 1468 nvme_init_queue(nvmeq, qid);
dca51e78 1469 result = queue_request_irq(nvmeq);
b60503ba
MW		 1470 if (result < 0)
1471 goto release_sq;
1472
22404274 1473 return result;
b60503ba
MW		 1474
1475 release_sq:
f25a2dfc 1476 dev->online_queues--;
b60503ba
MW		 1477 adapter_delete_sq(dev, qid);
1478 release_cq:
1479 adapter_delete_cq(dev, qid);
f25a2dfc
JW		 1480 release_vector:
1481 nvmeq->cq_vector = -1;
22404274 1482 return result;
b60503ba
MW		 1483}
1484
f363b089 1485static const struct blk_mq_ops nvme_mq_admin_ops = {
d29ec824 1486 .queue_rq = nvme_queue_rq,
77f02a7a 1487 .complete = nvme_pci_complete_rq,
a4aea562 1488 .init_hctx = nvme_admin_init_hctx,
4af0e21c 1489 .exit_hctx = nvme_admin_exit_hctx,
0350815a 1490 .init_request = nvme_init_request,
a4aea562
MB		 1491 .timeout = nvme_timeout,
1492};
1493
f363b089 1494static const struct blk_mq_ops nvme_mq_ops = {
a4aea562 1495 .queue_rq = nvme_queue_rq,
77f02a7a 1496 .complete = nvme_pci_complete_rq,
a4aea562
MB		 1497 .init_hctx = nvme_init_hctx,
1498 .init_request = nvme_init_request,
dca51e78 1499 .map_queues = nvme_pci_map_queues,
a4aea562 1500 .timeout = nvme_timeout,
a0fa9647 1501 .poll = nvme_poll,
a4aea562
MB		 1502};
1503
ea191d2f
KB		 1504static void nvme_dev_remove_admin(struct nvme_dev *dev)
1505{
1c63dc66 1506 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
69d9a99c
KB		 1507 /*
1508 * If the controller was reset during removal, it's possible
1509 * user requests may be waiting on a stopped queue. Start the
1510 * queue to flush these to completion.
1511 */
c81545f9 1512 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1c63dc66 1513 blk_cleanup_queue(dev->ctrl.admin_q);
ea191d2f
KB		 1514 blk_mq_free_tag_set(&dev->admin_tagset);
1515 }
1516}
1517
a4aea562
MB		 1518static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1519{
1c63dc66 1520 if (!dev->ctrl.admin_q) {
a4aea562
MB		 1521 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1522 dev->admin_tagset.nr_hw_queues = 1;
e3e9d50c 1523
38dabe21 1524 dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH;
a4aea562 1525 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
e75ec752 1526 dev->admin_tagset.numa_node = dev_to_node(dev->dev);
a7a7cbe3 1527 dev->admin_tagset.cmd_size = nvme_pci_cmd_size(dev, false);
d3484991 1528 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED;
a4aea562
MB		 1529 dev->admin_tagset.driver_data = dev;
1530
1531 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1532 return -ENOMEM;
34b6c231 1533 dev->ctrl.admin_tagset = &dev->admin_tagset;
a4aea562 1534
1c63dc66
CH		 1535 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1536 if (IS_ERR(dev->ctrl.admin_q)) {
a4aea562
MB		 1537 blk_mq_free_tag_set(&dev->admin_tagset);
1538 return -ENOMEM;
1539 }
1c63dc66 1540 if (!blk_get_queue(dev->ctrl.admin_q)) {
ea191d2f 1541 nvme_dev_remove_admin(dev);
1c63dc66 1542 dev->ctrl.admin_q = NULL;
ea191d2f
KB		 1543 return -ENODEV;
1544 }
0fb59cbc 1545 } else
c81545f9 1546 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
a4aea562
MB		 1547
1548 return 0;
1549}
1550
97f6ef64
XY		 1551static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1552{
1553 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1554}
1555
1556static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1557{
1558 struct pci_dev *pdev = to_pci_dev(dev->dev);
1559
1560 if (size <= dev->bar_mapped_size)
1561 return 0;
1562 if (size > pci_resource_len(pdev, 0))
1563 return -ENOMEM;
1564 if (dev->bar)
1565 iounmap(dev->bar);
1566 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1567 if (!dev->bar) {
1568 dev->bar_mapped_size = 0;
1569 return -ENOMEM;
1570 }
1571 dev->bar_mapped_size = size;
1572 dev->dbs = dev->bar + NVME_REG_DBS;
1573
1574 return 0;
1575}
1576
01ad0990 1577static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
b60503ba 1578{
ba47e386 1579 int result;
b60503ba
MW		 1580 u32 aqa;
1581 struct nvme_queue *nvmeq;
1582
97f6ef64
XY		 1583 result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1584 if (result < 0)
1585 return result;
1586
8ef2074d 1587 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
20d0dfe6 1588 NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
dfbac8c7 1589
7a67cbea
CH		 1590 if (dev->subsystem &&
1591 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1592 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
dfbac8c7 1593
20d0dfe6 1594 result = nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap);
ba47e386
MW		 1595 if (result < 0)
1596 return result;
b60503ba 1597
147b27e4
SG		 1598 result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH,
1599 dev_to_node(dev->dev));
1600 if (result)
1601 return result;
b60503ba 1602
147b27e4 1603 nvmeq = &dev->queues[0];
b60503ba
MW		 1604 aqa = nvmeq->q_depth - 1;
1605 aqa |= aqa << 16;
1606
7a67cbea
CH		 1607 writel(aqa, dev->bar + NVME_REG_AQA);
1608 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1609 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
b60503ba 1610
20d0dfe6 1611 result = nvme_enable_ctrl(&dev->ctrl, dev->ctrl.cap);
025c557a 1612 if (result)
d4875622 1613 return result;
a4aea562 1614
2b25d981 1615 nvmeq->cq_vector = 0;
161b8be2 1616 nvme_init_queue(nvmeq, 0);
dca51e78 1617 result = queue_request_irq(nvmeq);
758dd7fd
JD		 1618 if (result) {
1619 nvmeq->cq_vector = -1;
d4875622 1620 return result;
758dd7fd 1621 }
025c557a 1622
b60503ba
MW		 1623 return result;
1624}
1625
749941f2 1626static int nvme_create_io_queues(struct nvme_dev *dev)
42f61420 1627{
949928c1 1628 unsigned i, max;
749941f2 1629 int ret = 0;
42f61420 1630
d858e5f0 1631 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
d3af3ecd 1632 /* vector == qid - 1, match nvme_create_queue */
147b27e4 1633 if (nvme_alloc_queue(dev, i, dev->q_depth,
d3af3ecd 1634 pci_irq_get_node(to_pci_dev(dev->dev), i - 1))) {
749941f2 1635 ret = -ENOMEM;
42f61420 1636 break;
749941f2
CH		 1637 }
1638 }
42f61420 1639
d858e5f0 1640 max = min(dev->max_qid, dev->ctrl.queue_count - 1);
949928c1 1641 for (i = dev->online_queues; i <= max; i++) {
147b27e4 1642 ret = nvme_create_queue(&dev->queues[i], i);
d4875622 1643 if (ret)
42f61420 1644 break;
27e8166c 1645 }
749941f2
CH		 1646
1647 /*
1648 * Ignore failing Create SQ/CQ commands, we can continue with less
8adb8c14
MI		 1649 * than the desired amount of queues, and even a controller without
1650 * I/O queues can still be used to issue admin commands. This might
749941f2
CH		 1651 * be useful to upgrade a buggy firmware for example.
1652 */
1653 return ret >= 0 ? 0 : ret;
b60503ba
MW		 1654}
1655
202021c1
SB		 1656static ssize_t nvme_cmb_show(struct device *dev,
1657 struct device_attribute *attr,
1658 char *buf)
1659{
1660 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
1661
c965809c 1662 return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n",
202021c1
SB		 1663 ndev->cmbloc, ndev->cmbsz);
1664}
1665static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL);
1666
88de4598 1667static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
8ffaadf7 1668{
88de4598
CH		 1669 u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
1670
1671 return 1ULL << (12 + 4 * szu);
1672}
1673
1674static u32 nvme_cmb_size(struct nvme_dev *dev)
1675{
1676 return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
1677}
1678
f65efd6d 1679static void nvme_map_cmb(struct nvme_dev *dev)
8ffaadf7 1680{
88de4598 1681 u64 size, offset;
8ffaadf7
JD		 1682 resource_size_t bar_size;
1683 struct pci_dev *pdev = to_pci_dev(dev->dev);
8969f1f8 1684 int bar;
8ffaadf7 1685
7a67cbea 1686 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
f65efd6d
CH		 1687 if (!dev->cmbsz)
1688 return;
202021c1 1689 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
8ffaadf7 1690
202021c1 1691 if (!use_cmb_sqes)
f65efd6d 1692 return;
8ffaadf7 1693
88de4598
CH		 1694 size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
1695 offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
8969f1f8
CH		 1696 bar = NVME_CMB_BIR(dev->cmbloc);
1697 bar_size = pci_resource_len(pdev, bar);
8ffaadf7
JD		 1698
1699 if (offset > bar_size)
f65efd6d 1700 return;
8ffaadf7
JD		 1701
1702 /*
1703 * Controllers may support a CMB size larger than their BAR,
1704 * for example, due to being behind a bridge. Reduce the CMB to
1705 * the reported size of the BAR
1706 */
1707 if (size > bar_size - offset)
1708 size = bar_size - offset;
1709
f65efd6d
CH		 1710 dev->cmb = ioremap_wc(pci_resource_start(pdev, bar) + offset, size);
1711 if (!dev->cmb)
1712 return;
8969f1f8 1713 dev->cmb_bus_addr = pci_bus_address(pdev, bar) + offset;
8ffaadf7 1714 dev->cmb_size = size;
f65efd6d
CH		 1715
1716 if (sysfs_add_file_to_group(&dev->ctrl.device->kobj,
1717 &dev_attr_cmb.attr, NULL))
1718 dev_warn(dev->ctrl.device,
1719 "failed to add sysfs attribute for CMB\n");
8ffaadf7
JD		 1720}
1721
1722static inline void nvme_release_cmb(struct nvme_dev *dev)
1723{
1724 if (dev->cmb) {
1725 iounmap(dev->cmb);
1726 dev->cmb = NULL;
1c78f773
MG		 1727 sysfs_remove_file_from_group(&dev->ctrl.device->kobj,
1728 &dev_attr_cmb.attr, NULL);
1729 dev->cmbsz = 0;
8ffaadf7
JD		 1730 }
1731}
1732
87ad72a5
CH		 1733static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1734{
4033f35d 1735 u64 dma_addr = dev->host_mem_descs_dma;
87ad72a5 1736 struct nvme_command c;
87ad72a5
CH		 1737 int ret;
1738
87ad72a5
CH		 1739 memset(&c, 0, sizeof(c));
1740 c.features.opcode = nvme_admin_set_features;
1741 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1742 c.features.dword11 = cpu_to_le32(bits);
1743 c.features.dword12 = cpu_to_le32(dev->host_mem_size >>
1744 ilog2(dev->ctrl.page_size));
1745 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr));
1746 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr));
1747 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs);
1748
1749 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1750 if (ret) {
1751 dev_warn(dev->ctrl.device,
1752 "failed to set host mem (err %d, flags %#x).\n",
1753 ret, bits);
1754 }
87ad72a5
CH		 1755 return ret;
1756}
1757
1758static void nvme_free_host_mem(struct nvme_dev *dev)
1759{
1760 int i;
1761
1762 for (i = 0; i < dev->nr_host_mem_descs; i++) {
1763 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
1764 size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size;
1765
1766 dma_free_coherent(dev->dev, size, dev->host_mem_desc_bufs[i],
1767 le64_to_cpu(desc->addr));
1768 }
1769
1770 kfree(dev->host_mem_desc_bufs);
1771 dev->host_mem_desc_bufs = NULL;
4033f35d
CH		 1772 dma_free_coherent(dev->dev,
1773 dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
1774 dev->host_mem_descs, dev->host_mem_descs_dma);
87ad72a5 1775 dev->host_mem_descs = NULL;
7e5dd57e 1776 dev->nr_host_mem_descs = 0;
87ad72a5
CH		 1777}
1778
92dc6895
CH		 1779static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
1780 u32 chunk_size)
9d713c2b 1781{
87ad72a5 1782 struct nvme_host_mem_buf_desc *descs;
92dc6895 1783 u32 max_entries, len;
4033f35d 1784 dma_addr_t descs_dma;
2ee0e4ed 1785 int i = 0;
87ad72a5 1786 void **bufs;
6fbcde66 1787 u64 size, tmp;
87ad72a5 1788
87ad72a5
CH		 1789 tmp = (preferred + chunk_size - 1);
1790 do_div(tmp, chunk_size);
1791 max_entries = tmp;
044a9df1
CH		 1792
1793 if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
1794 max_entries = dev->ctrl.hmmaxd;
1795
4033f35d
CH		 1796 descs = dma_zalloc_coherent(dev->dev, max_entries * sizeof(*descs),
1797 &descs_dma, GFP_KERNEL);
87ad72a5
CH		 1798 if (!descs)
1799 goto out;
1800
1801 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
1802 if (!bufs)
1803 goto out_free_descs;
1804
244a8fe4 1805 for (size = 0; size < preferred && i < max_entries; size += len) {
87ad72a5
CH		 1806 dma_addr_t dma_addr;
1807
50cdb7c6 1808 len = min_t(u64, chunk_size, preferred - size);
87ad72a5
CH		 1809 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
1810 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1811 if (!bufs[i])
1812 break;
1813
1814 descs[i].addr = cpu_to_le64(dma_addr);
1815 descs[i].size = cpu_to_le32(len / dev->ctrl.page_size);
1816 i++;
1817 }
1818
92dc6895 1819 if (!size)
87ad72a5 1820 goto out_free_bufs;
87ad72a5 1821
87ad72a5
CH		 1822 dev->nr_host_mem_descs = i;
1823 dev->host_mem_size = size;
1824 dev->host_mem_descs = descs;
4033f35d 1825 dev->host_mem_descs_dma = descs_dma;
87ad72a5
CH		 1826 dev->host_mem_desc_bufs = bufs;
1827 return 0;
1828
1829out_free_bufs:
1830 while (--i >= 0) {
1831 size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size;
1832
1833 dma_free_coherent(dev->dev, size, bufs[i],
1834 le64_to_cpu(descs[i].addr));
1835 }
1836
1837 kfree(bufs);
1838out_free_descs:
4033f35d
CH		 1839 dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
1840 descs_dma);
87ad72a5 1841out:
87ad72a5
CH		 1842 dev->host_mem_descs = NULL;
1843 return -ENOMEM;
1844}
1845
92dc6895
CH		 1846static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
1847{
1848 u32 chunk_size;
1849
1850 /* start big and work our way down */
30f92d62 1851 for (chunk_size = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
044a9df1 1852 chunk_size >= max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
92dc6895
CH		 1853 chunk_size /= 2) {
1854 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
1855 if (!min || dev->host_mem_size >= min)
1856 return 0;
1857 nvme_free_host_mem(dev);
1858 }
1859 }
1860
1861 return -ENOMEM;
1862}
1863
9620cfba 1864static int nvme_setup_host_mem(struct nvme_dev *dev)
87ad72a5
CH		 1865{
1866 u64 max = (u64)max_host_mem_size_mb * SZ_1M;
1867 u64 preferred = (u64)dev->ctrl.hmpre * 4096;
1868 u64 min = (u64)dev->ctrl.hmmin * 4096;
1869 u32 enable_bits = NVME_HOST_MEM_ENABLE;
6fbcde66 1870 int ret;
87ad72a5
CH		 1871
1872 preferred = min(preferred, max);
1873 if (min > max) {
1874 dev_warn(dev->ctrl.device,
1875 "min host memory (%lld MiB) above limit (%d MiB).\n",
1876 min >> ilog2(SZ_1M), max_host_mem_size_mb);
1877 nvme_free_host_mem(dev);
9620cfba 1878 return 0;
87ad72a5
CH		 1879 }
1880
1881 /*
1882 * If we already have a buffer allocated check if we can reuse it.
1883 */
1884 if (dev->host_mem_descs) {
1885 if (dev->host_mem_size >= min)
1886 enable_bits |= NVME_HOST_MEM_RETURN;
1887 else
1888 nvme_free_host_mem(dev);
1889 }
1890
1891 if (!dev->host_mem_descs) {
92dc6895
CH		 1892 if (nvme_alloc_host_mem(dev, min, preferred)) {
1893 dev_warn(dev->ctrl.device,
1894 "failed to allocate host memory buffer.\n");
9620cfba 1895 return 0; /* controller must work without HMB */
92dc6895
CH		 1896 }
1897
1898 dev_info(dev->ctrl.device,
1899 "allocated %lld MiB host memory buffer.\n",
1900 dev->host_mem_size >> ilog2(SZ_1M));
87ad72a5
CH		 1901 }
1902
9620cfba
CH		 1903 ret = nvme_set_host_mem(dev, enable_bits);
1904 if (ret)
87ad72a5 1905 nvme_free_host_mem(dev);
9620cfba 1906 return ret;
9d713c2b
KB		 1907}
1908
8d85fce7 1909static int nvme_setup_io_queues(struct nvme_dev *dev)
b60503ba 1910{
147b27e4 1911 struct nvme_queue *adminq = &dev->queues[0];
e75ec752 1912 struct pci_dev *pdev = to_pci_dev(dev->dev);
97f6ef64
XY		 1913 int result, nr_io_queues;
1914 unsigned long size;
b60503ba 1915
425a17cb 1916 nr_io_queues = num_present_cpus();
9a0be7ab
CH		 1917 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
1918 if (result < 0)
1b23484b 1919 return result;
9a0be7ab 1920
f5fa90dc 1921 if (nr_io_queues == 0)
a5229050 1922 return 0;
b60503ba 1923
88de4598 1924 if (dev->cmb && (dev->cmbsz & NVME_CMBSZ_SQS)) {
8ffaadf7
JD		 1925 result = nvme_cmb_qdepth(dev, nr_io_queues,
1926 sizeof(struct nvme_command));
1927 if (result > 0)
1928 dev->q_depth = result;
1929 else
1930 nvme_release_cmb(dev);
1931 }
1932
97f6ef64
XY		 1933 do {
1934 size = db_bar_size(dev, nr_io_queues);
1935 result = nvme_remap_bar(dev, size);
1936 if (!result)
1937 break;
1938 if (!--nr_io_queues)
1939 return -ENOMEM;
1940 } while (1);
1941 adminq->q_db = dev->dbs;
f1938f6e 1942
9d713c2b 1943 /* Deregister the admin queue's interrupt */
0ff199cb 1944 pci_free_irq(pdev, 0, adminq);
9d713c2b 1945
e32efbfc
JA		 1946 /*
1947 * If we enable msix early due to not intx, disable it again before
1948 * setting up the full range we need.
1949 */
dca51e78
CH		 1950 pci_free_irq_vectors(pdev);
1951 nr_io_queues = pci_alloc_irq_vectors(pdev, 1, nr_io_queues,
1952 PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY);
1953 if (nr_io_queues <= 0)
1954 return -EIO;
1955 dev->max_qid = nr_io_queues;
fa08a396 1956
063a8096
MW		 1957 /*
1958 * Should investigate if there's a performance win from allocating
1959 * more queues than interrupt vectors; it might allow the submission
1960 * path to scale better, even if the receive path is limited by the
1961 * number of interrupts.
1962 */
063a8096 1963
dca51e78 1964 result = queue_request_irq(adminq);
758dd7fd
JD		 1965 if (result) {
1966 adminq->cq_vector = -1;
d4875622 1967 return result;
758dd7fd 1968 }
749941f2 1969 return nvme_create_io_queues(dev);
b60503ba
MW		 1970}
1971
2a842aca 1972static void nvme_del_queue_end(struct request *req, blk_status_t error)
a5768aa8 1973{
db3cbfff 1974 struct nvme_queue *nvmeq = req->end_io_data;
b5875222 1975
db3cbfff
KB		 1976 blk_mq_free_request(req);
1977 complete(&nvmeq->dev->ioq_wait);
a5768aa8
KB		 1978}
1979
2a842aca 1980static void nvme_del_cq_end(struct request *req, blk_status_t error)
a5768aa8 1981{
db3cbfff 1982 struct nvme_queue *nvmeq = req->end_io_data;
a5768aa8 1983
db3cbfff
KB		 1984 if (!error) {
1985 unsigned long flags;
1986
2e39e0f6
ML		 1987 /*
1988 * We might be called with the AQ q_lock held
1989 * and the I/O queue q_lock should always
1990 * nest inside the AQ one.
1991 */
1992 spin_lock_irqsave_nested(&nvmeq->q_lock, flags,
1993 SINGLE_DEPTH_NESTING);
db3cbfff
KB		 1994 nvme_process_cq(nvmeq);
1995 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
a5768aa8 1996 }
db3cbfff
KB		 1997
1998 nvme_del_queue_end(req, error);
a5768aa8
KB		 1999}
2000
db3cbfff 2001static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
bda4e0fb 2002{
db3cbfff
KB		 2003 struct request_queue *q = nvmeq->dev->ctrl.admin_q;
2004 struct request *req;
2005 struct nvme_command cmd;
bda4e0fb 2006
db3cbfff
KB		 2007 memset(&cmd, 0, sizeof(cmd));
2008 cmd.delete_queue.opcode = opcode;
2009 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
bda4e0fb 2010
eb71f435 2011 req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
db3cbfff
KB		 2012 if (IS_ERR(req))
2013 return PTR_ERR(req);
bda4e0fb 2014
db3cbfff
KB		 2015 req->timeout = ADMIN_TIMEOUT;
2016 req->end_io_data = nvmeq;
2017
2018 blk_execute_rq_nowait(q, NULL, req, false,
2019 opcode == nvme_admin_delete_cq ?
2020 nvme_del_cq_end : nvme_del_queue_end);
2021 return 0;
bda4e0fb
KB		 2022}
2023
ee9aebb2 2024static void nvme_disable_io_queues(struct nvme_dev *dev)
a5768aa8 2025{
ee9aebb2 2026 int pass, queues = dev->online_queues - 1;
db3cbfff
KB		 2027 unsigned long timeout;
2028 u8 opcode = nvme_admin_delete_sq;
a5768aa8 2029
db3cbfff 2030 for (pass = 0; pass < 2; pass++) {
014a0d60 2031 int sent = 0, i = queues;
db3cbfff
KB		 2032
2033 reinit_completion(&dev->ioq_wait);
2034 retry:
2035 timeout = ADMIN_TIMEOUT;
c21377f8 2036 for (; i > 0; i--, sent++)
147b27e4 2037 if (nvme_delete_queue(&dev->queues[i], opcode))
db3cbfff 2038 break;
c21377f8 2039
db3cbfff
KB		 2040 while (sent--) {
2041 timeout = wait_for_completion_io_timeout(&dev->ioq_wait, timeout);
2042 if (timeout == 0)
2043 return;
2044 if (i)
2045 goto retry;
2046 }
2047 opcode = nvme_admin_delete_cq;
2048 }
a5768aa8
KB		 2049}
2050
422ef0c7 2051/*
2b1b7e78 2052 * return error value only when tagset allocation failed
422ef0c7 2053 */
8d85fce7 2054static int nvme_dev_add(struct nvme_dev *dev)
b60503ba 2055{
2b1b7e78
JW		 2056 int ret;
2057
5bae7f73 2058 if (!dev->ctrl.tagset) {
ffe7704d
KB		 2059 dev->tagset.ops = &nvme_mq_ops;
2060 dev->tagset.nr_hw_queues = dev->online_queues - 1;
2061 dev->tagset.timeout = NVME_IO_TIMEOUT;
2062 dev->tagset.numa_node = dev_to_node(dev->dev);
2063 dev->tagset.queue_depth =
a4aea562 2064 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
a7a7cbe3
CK		 2065 dev->tagset.cmd_size = nvme_pci_cmd_size(dev, false);
2066 if ((dev->ctrl.sgls & ((1 << 0) | (1 << 1))) && sgl_threshold) {
2067 dev->tagset.cmd_size = max(dev->tagset.cmd_size,
2068 nvme_pci_cmd_size(dev, true));
2069 }
ffe7704d
KB		 2070 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2071 dev->tagset.driver_data = dev;
b60503ba 2072
2b1b7e78
JW		 2073 ret = blk_mq_alloc_tag_set(&dev->tagset);
2074 if (ret) {
2075 dev_warn(dev->ctrl.device,
2076 "IO queues tagset allocation failed %d\n", ret);
2077 return ret;
2078 }
5bae7f73 2079 dev->ctrl.tagset = &dev->tagset;
f9f38e33
HK		 2080
2081 nvme_dbbuf_set(dev);
949928c1
KB		 2082 } else {
2083 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2084
2085 /* Free previously allocated queues that are no longer usable */
2086 nvme_free_queues(dev, dev->online_queues);
ffe7704d 2087 }
949928c1 2088
e1e5e564 2089 return 0;
b60503ba
MW		 2090}
2091
b00a726a 2092static int nvme_pci_enable(struct nvme_dev *dev)
0877cb0d 2093{
b00a726a 2094 int result = -ENOMEM;
e75ec752 2095 struct pci_dev *pdev = to_pci_dev(dev->dev);
0877cb0d
KB		 2096
2097 if (pci_enable_device_mem(pdev))
2098 return result;
2099
0877cb0d 2100 pci_set_master(pdev);
0877cb0d 2101
e75ec752
CH		 2102 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) &&
2103 dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32)))
052d0efa 2104 goto disable;
0877cb0d 2105
7a67cbea 2106 if (readl(dev->bar + NVME_REG_CSTS) == -1) {
0e53d180 2107 result = -ENODEV;
b00a726a 2108 goto disable;
0e53d180 2109 }
e32efbfc
JA		 2110
2111 /*
a5229050
KB		 2112 * Some devices and/or platforms don't advertise or work with INTx
2113 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2114 * adjust this later.
e32efbfc 2115 */
dca51e78
CH		 2116 result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
2117 if (result < 0)
2118 return result;
e32efbfc 2119
20d0dfe6 2120 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
7a67cbea 2121
20d0dfe6 2122 dev->q_depth = min_t(int, NVME_CAP_MQES(dev->ctrl.cap) + 1,
b27c1e68 2123 io_queue_depth);
20d0dfe6 2124 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
7a67cbea 2125 dev->dbs = dev->bar + 4096;
1f390c1f
SG		 2126
2127 /*
2128 * Temporary fix for the Apple controller found in the MacBook8,1 and
2129 * some MacBook7,1 to avoid controller resets and data loss.
2130 */
2131 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
2132 dev->q_depth = 2;
9bdcfb10
CH		 2133 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
2134 "set queue depth=%u to work around controller resets\n",
1f390c1f 2135 dev->q_depth);
d554b5e1
MP		 2136 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2137 (pdev->device == 0xa821 || pdev->device == 0xa822) &&
20d0dfe6 2138 NVME_CAP_MQES(dev->ctrl.cap) == 0) {
d554b5e1
MP		 2139 dev->q_depth = 64;
2140 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2141 "set queue depth=%u\n", dev->q_depth);
1f390c1f
SG		 2142 }
2143
f65efd6d 2144 nvme_map_cmb(dev);
202021c1 2145
a0a3408e
KB		 2146 pci_enable_pcie_error_reporting(pdev);
2147 pci_save_state(pdev);
0877cb0d
KB		 2148 return 0;
2149
2150 disable:
0877cb0d
KB		 2151 pci_disable_device(pdev);
2152 return result;
2153}
2154
2155static void nvme_dev_unmap(struct nvme_dev *dev)
b00a726a
KB		 2156{
2157 if (dev->bar)
2158 iounmap(dev->bar);
a1f447b3 2159 pci_release_mem_regions(to_pci_dev(dev->dev));
b00a726a
KB		 2160}
2161
2162static void nvme_pci_disable(struct nvme_dev *dev)
0877cb0d 2163{
e75ec752
CH		 2164 struct pci_dev *pdev = to_pci_dev(dev->dev);
2165
f63572df 2166 nvme_release_cmb(dev);
dca51e78 2167 pci_free_irq_vectors(pdev);
0877cb0d 2168
a0a3408e
KB		 2169 if (pci_is_enabled(pdev)) {
2170 pci_disable_pcie_error_reporting(pdev);
e75ec752 2171 pci_disable_device(pdev);
4d115420 2172 }
4d115420
KB		 2173}
2174
a5cdb68c 2175static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
b60503ba 2176{
ee9aebb2 2177 int i;
302ad8cc
KB		 2178 bool dead = true;
2179 struct pci_dev *pdev = to_pci_dev(dev->dev);
22404274 2180
77bf25ea 2181 mutex_lock(&dev->shutdown_lock);
302ad8cc
KB		 2182 if (pci_is_enabled(pdev)) {
2183 u32 csts = readl(dev->bar + NVME_REG_CSTS);
2184
ebef7368
KB		 2185 if (dev->ctrl.state == NVME_CTRL_LIVE ||
2186 dev->ctrl.state == NVME_CTRL_RESETTING)
302ad8cc
KB		 2187 nvme_start_freeze(&dev->ctrl);
2188 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
2189 pdev->error_state != pci_channel_io_normal);
c9d3bf88 2190 }
c21377f8 2191
302ad8cc
KB		 2192 /*
2193 * Give the controller a chance to complete all entered requests if
2194 * doing a safe shutdown.
2195 */
87ad72a5
CH		 2196 if (!dead) {
2197 if (shutdown)
2198 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
9a915a5b
JW		 2199 }
2200
2201 nvme_stop_queues(&dev->ctrl);
87ad72a5 2202
9a915a5b 2203 if (!dead) {
87ad72a5
CH		 2204 /*
2205 * If the controller is still alive tell it to stop using the
2206 * host memory buffer. In theory the shutdown / reset should
2207 * make sure that it doesn't access the host memoery anymore,
2208 * but I'd rather be safe than sorry..
2209 */
2210 if (dev->host_mem_descs)
2211 nvme_set_host_mem(dev, 0);
ee9aebb2 2212 nvme_disable_io_queues(dev);
a5cdb68c 2213 nvme_disable_admin_queue(dev, shutdown);
4d115420 2214 }
ee9aebb2
KB		 2215 for (i = dev->ctrl.queue_count - 1; i >= 0; i--)
2216 nvme_suspend_queue(&dev->queues[i]);
2217
b00a726a 2218 nvme_pci_disable(dev);
07836e65 2219
e1958e65
ML		 2220 blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
2221 blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
302ad8cc
KB		 2222
2223 /*
2224 * The driver will not be starting up queues again if shutting down so
2225 * must flush all entered requests to their failed completion to avoid
2226 * deadlocking blk-mq hot-cpu notifier.
2227 */
2228 if (shutdown)
2229 nvme_start_queues(&dev->ctrl);
77bf25ea 2230 mutex_unlock(&dev->shutdown_lock);
b60503ba
MW		 2231}
2232
091b6092
MW		 2233static int nvme_setup_prp_pools(struct nvme_dev *dev)
2234{
e75ec752 2235 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
091b6092
MW		 2236 PAGE_SIZE, PAGE_SIZE, 0);
2237 if (!dev->prp_page_pool)
2238 return -ENOMEM;
2239
99802a7a 2240 /* Optimisation for I/Os between 4k and 128k */
e75ec752 2241 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
99802a7a
MW		 2242 256, 256, 0);
2243 if (!dev->prp_small_pool) {
2244 dma_pool_destroy(dev->prp_page_pool);
2245 return -ENOMEM;
2246 }
091b6092
MW		 2247 return 0;
2248}
2249
2250static void nvme_release_prp_pools(struct nvme_dev *dev)
2251{
2252 dma_pool_destroy(dev->prp_page_pool);
99802a7a 2253 dma_pool_destroy(dev->prp_small_pool);
091b6092
MW		 2254}
2255
1673f1f0 2256static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
5e82e952 2257{
1673f1f0 2258 struct nvme_dev *dev = to_nvme_dev(ctrl);
9ac27090 2259
f9f38e33 2260 nvme_dbbuf_dma_free(dev);
e75ec752 2261 put_device(dev->dev);
4af0e21c
KB		 2262 if (dev->tagset.tags)
2263 blk_mq_free_tag_set(&dev->tagset);
1c63dc66
CH		 2264 if (dev->ctrl.admin_q)
2265 blk_put_queue(dev->ctrl.admin_q);
5e82e952 2266 kfree(dev->queues);
e286bcfc 2267 free_opal_dev(dev->ctrl.opal_dev);
5e82e952
KB		 2268 kfree(dev);
2269}
2270
f58944e2
KB		 2271static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status)
2272{
237045fc 2273 dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status);
f58944e2 2274
d22524a4 2275 nvme_get_ctrl(&dev->ctrl);
69d9a99c 2276 nvme_dev_disable(dev, false);
03e0f3a6 2277 if (!queue_work(nvme_wq, &dev->remove_work))
f58944e2
KB		 2278 nvme_put_ctrl(&dev->ctrl);
2279}
2280
fd634f41 2281static void nvme_reset_work(struct work_struct *work)
5e82e952 2282{
d86c4d8e
CH		 2283 struct nvme_dev *dev =
2284 container_of(work, struct nvme_dev, ctrl.reset_work);
a98e58e5 2285 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
f58944e2 2286 int result = -ENODEV;
2b1b7e78 2287 enum nvme_ctrl_state new_state = NVME_CTRL_LIVE;
5e82e952 2288
82b057ca 2289 if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING))
fd634f41 2290 goto out;
5e82e952 2291
fd634f41
CH		 2292 /*
2293 * If we're called to reset a live controller first shut it down before
2294 * moving on.
2295 */
b00a726a 2296 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
a5cdb68c 2297 nvme_dev_disable(dev, false);
5e82e952 2298
ad70062c 2299 /*
ad6a0a52 2300 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
ad70062c
JW		 2301 * initializing procedure here.
2302 */
ad6a0a52 2303 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
ad70062c 2304 dev_warn(dev->ctrl.device,
ad6a0a52 2305 "failed to mark controller CONNECTING\n");
ad70062c
JW		 2306 goto out;
2307 }
2308
b00a726a 2309 result = nvme_pci_enable(dev);
f0b50732 2310 if (result)
3cf519b5 2311 goto out;
f0b50732 2312
01ad0990 2313 result = nvme_pci_configure_admin_queue(dev);
f0b50732 2314 if (result)
f58944e2 2315 goto out;
f0b50732 2316
0fb59cbc
KB		 2317 result = nvme_alloc_admin_tags(dev);
2318 if (result)
f58944e2 2319 goto out;
b9afca3e 2320
ce4541f4
CH		 2321 result = nvme_init_identify(&dev->ctrl);
2322 if (result)
f58944e2 2323 goto out;
ce4541f4 2324
e286bcfc
SB		 2325 if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
2326 if (!dev->ctrl.opal_dev)
2327 dev->ctrl.opal_dev =
2328 init_opal_dev(&dev->ctrl, &nvme_sec_submit);
2329 else if (was_suspend)
2330 opal_unlock_from_suspend(dev->ctrl.opal_dev);
2331 } else {
2332 free_opal_dev(dev->ctrl.opal_dev);
2333 dev->ctrl.opal_dev = NULL;
4f1244c8 2334 }
a98e58e5 2335
f9f38e33
HK		 2336 if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) {
2337 result = nvme_dbbuf_dma_alloc(dev);
2338 if (result)
2339 dev_warn(dev->dev,
2340 "unable to allocate dma for dbbuf\n");
2341 }
2342
9620cfba
CH		 2343 if (dev->ctrl.hmpre) {
2344 result = nvme_setup_host_mem(dev);
2345 if (result < 0)
2346 goto out;
2347 }
87ad72a5 2348
f0b50732 2349 result = nvme_setup_io_queues(dev);
badc34d4 2350 if (result)
f58944e2 2351 goto out;
f0b50732 2352
2659e57b
CH		 2353 /*
2354 * Keep the controller around but remove all namespaces if we don't have
2355 * any working I/O queue.
2356 */
3cf519b5 2357 if (dev->online_queues < 2) {
1b3c47c1 2358 dev_warn(dev->ctrl.device, "IO queues not created\n");
3b24774e 2359 nvme_kill_queues(&dev->ctrl);
5bae7f73 2360 nvme_remove_namespaces(&dev->ctrl);
2b1b7e78 2361 new_state = NVME_CTRL_ADMIN_ONLY;
3cf519b5 2362 } else {
25646264 2363 nvme_start_queues(&dev->ctrl);
302ad8cc 2364 nvme_wait_freeze(&dev->ctrl);
2b1b7e78
JW		 2365 /* hit this only when allocate tagset fails */
2366 if (nvme_dev_add(dev))
2367 new_state = NVME_CTRL_ADMIN_ONLY;
302ad8cc 2368 nvme_unfreeze(&dev->ctrl);
3cf519b5
CH		 2369 }
2370
2b1b7e78
JW		 2371 /*
2372 * If only admin queue live, keep it to do further investigation or
2373 * recovery.
2374 */
2375 if (!nvme_change_ctrl_state(&dev->ctrl, new_state)) {
2376 dev_warn(dev->ctrl.device,
2377 "failed to mark controller state %d\n", new_state);
bb8d261e
CH		 2378 goto out;
2379 }
92911a55 2380
d09f2b45 2381 nvme_start_ctrl(&dev->ctrl);
3cf519b5 2382 return;
f0b50732 2383
3cf519b5 2384 out:
f58944e2 2385 nvme_remove_dead_ctrl(dev, result);
f0b50732
KB		 2386}
2387
5c8809e6 2388static void nvme_remove_dead_ctrl_work(struct work_struct *work)
9a6b9458 2389{
5c8809e6 2390 struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
e75ec752 2391 struct pci_dev *pdev = to_pci_dev(dev->dev);
9a6b9458 2392
69d9a99c 2393 nvme_kill_queues(&dev->ctrl);
9a6b9458 2394 if (pci_get_drvdata(pdev))
921920ab 2395 device_release_driver(&pdev->dev);
1673f1f0 2396 nvme_put_ctrl(&dev->ctrl);
9a6b9458
KB		 2397}
2398
1c63dc66 2399static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
9ca97374 2400{
1c63dc66 2401 *val = readl(to_nvme_dev(ctrl)->bar + off);
90667892 2402 return 0;
9ca97374
TH		 2403}
2404
5fd4ce1b 2405static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
4cc06521 2406{
5fd4ce1b
CH		 2407 writel(val, to_nvme_dev(ctrl)->bar + off);
2408 return 0;
2409}
4cc06521 2410
7fd8930f
CH		 2411static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2412{
2413 *val = readq(to_nvme_dev(ctrl)->bar + off);
2414 return 0;
4cc06521
KB		 2415}
2416
1c63dc66 2417static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
1a353d85 2418 .name = "pcie",
e439bb12 2419 .module = THIS_MODULE,
c81bfba9 2420 .flags = NVME_F_METADATA_SUPPORTED,
1c63dc66 2421 .reg_read32 = nvme_pci_reg_read32,
5fd4ce1b 2422 .reg_write32 = nvme_pci_reg_write32,
7fd8930f 2423 .reg_read64 = nvme_pci_reg_read64,
1673f1f0 2424 .free_ctrl = nvme_pci_free_ctrl,
f866fc42 2425 .submit_async_event = nvme_pci_submit_async_event,
1c63dc66 2426};
4cc06521 2427
b00a726a
KB		 2428static int nvme_dev_map(struct nvme_dev *dev)
2429{
b00a726a
KB		 2430 struct pci_dev *pdev = to_pci_dev(dev->dev);
2431
a1f447b3 2432 if (pci_request_mem_regions(pdev, "nvme"))
b00a726a
KB		 2433 return -ENODEV;
2434
97f6ef64 2435 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
b00a726a
KB		 2436 goto release;
2437
9fa196e7 2438 return 0;
b00a726a 2439 release:
9fa196e7
MG		 2440 pci_release_mem_regions(pdev);
2441 return -ENODEV;
b00a726a
KB		 2442}
2443
8427bbc2 2444static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
ff5350a8
AL		 2445{
2446 if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
2447 /*
2448 * Several Samsung devices seem to drop off the PCIe bus
2449 * randomly when APST is on and uses the deepest sleep state.
2450 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2451 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2452 * 950 PRO 256GB", but it seems to be restricted to two Dell
2453 * laptops.
2454 */
2455 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
2456 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
2457 dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
2458 return NVME_QUIRK_NO_DEEPEST_PS;
8427bbc2
KHF		 2459 } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
2460 /*
2461 * Samsung SSD 960 EVO drops off the PCIe bus after system
2462 * suspend on a Ryzen board, ASUS PRIME B350M-A.
2463 */
2464 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
2465 dmi_match(DMI_BOARD_NAME, "PRIME B350M-A"))
2466 return NVME_QUIRK_NO_APST;
ff5350a8
AL		 2467 }
2468
2469 return 0;
2470}
2471
8d85fce7 2472static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
b60503ba 2473{
a4aea562 2474 int node, result = -ENOMEM;
b60503ba 2475 struct nvme_dev *dev;
ff5350a8 2476 unsigned long quirks = id->driver_data;
b60503ba 2477
a4aea562
MB		 2478 node = dev_to_node(&pdev->dev);
2479 if (node == NUMA_NO_NODE)
2fa84351 2480 set_dev_node(&pdev->dev, first_memory_node);
a4aea562
MB		 2481
2482 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
b60503ba
MW		 2483 if (!dev)
2484 return -ENOMEM;
147b27e4
SG		 2485
2486 dev->queues = kcalloc_node(num_possible_cpus() + 1,
2487 sizeof(struct nvme_queue), GFP_KERNEL, node);
b60503ba
MW		 2488 if (!dev->queues)
2489 goto free;
2490
e75ec752 2491 dev->dev = get_device(&pdev->dev);
9a6b9458 2492 pci_set_drvdata(pdev, dev);
1c63dc66 2493
b00a726a
KB		 2494 result = nvme_dev_map(dev);
2495 if (result)
b00c9b7a 2496 goto put_pci;
b00a726a 2497
d86c4d8e 2498 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
5c8809e6 2499 INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
77bf25ea 2500 mutex_init(&dev->shutdown_lock);
db3cbfff 2501 init_completion(&dev->ioq_wait);
b60503ba 2502
091b6092
MW		 2503 result = nvme_setup_prp_pools(dev);
2504 if (result)
b00c9b7a 2505 goto unmap;
4cc06521 2506
8427bbc2 2507 quirks |= check_vendor_combination_bug(pdev);
ff5350a8 2508
f3ca80fc 2509 result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
ff5350a8 2510 quirks);
4cc06521 2511 if (result)
2e1d8448 2512 goto release_pools;
740216fc 2513
1b3c47c1
SG		 2514 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
2515
4caff8fc
SG		 2516 nvme_reset_ctrl(&dev->ctrl);
2517
b60503ba
MW		 2518 return 0;
2519
0877cb0d 2520 release_pools:
091b6092 2521 nvme_release_prp_pools(dev);
b00c9b7a
CJ		 2522 unmap:
2523 nvme_dev_unmap(dev);
a96d4f5c 2524 put_pci:
e75ec752 2525 put_device(dev->dev);
b60503ba
MW		 2526 free:
2527 kfree(dev->queues);
b60503ba
MW		 2528 kfree(dev);
2529 return result;
2530}
2531
775755ed 2532static void nvme_reset_prepare(struct pci_dev *pdev)
f0d54a54 2533{
a6739479 2534 struct nvme_dev *dev = pci_get_drvdata(pdev);
f263fbb8 2535 nvme_dev_disable(dev, false);
775755ed 2536}
f0d54a54 2537
775755ed
CH		 2538static void nvme_reset_done(struct pci_dev *pdev)
2539{
f263fbb8 2540 struct nvme_dev *dev = pci_get_drvdata(pdev);
79c48ccf 2541 nvme_reset_ctrl_sync(&dev->ctrl);
f0d54a54
KB		 2542}
2543
09ece142
KB		 2544static void nvme_shutdown(struct pci_dev *pdev)
2545{
2546 struct nvme_dev *dev = pci_get_drvdata(pdev);
a5cdb68c 2547 nvme_dev_disable(dev, true);
09ece142
KB		 2548}
2549
f58944e2
KB		 2550/*
2551 * The driver's remove may be called on a device in a partially initialized
2552 * state. This function must not have any dependencies on the device state in
2553 * order to proceed.
2554 */
8d85fce7 2555static void nvme_remove(struct pci_dev *pdev)
b60503ba
MW		 2556{
2557 struct nvme_dev *dev = pci_get_drvdata(pdev);
9a6b9458 2558
bb8d261e
CH		 2559 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
2560
d86c4d8e 2561 cancel_work_sync(&dev->ctrl.reset_work);
9a6b9458 2562 pci_set_drvdata(pdev, NULL);
0ff9d4e1 2563
6db28eda 2564 if (!pci_device_is_present(pdev)) {
0ff9d4e1 2565 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
6db28eda
KB		 2566 nvme_dev_disable(dev, false);
2567 }
0ff9d4e1 2568
d86c4d8e 2569 flush_work(&dev->ctrl.reset_work);
d09f2b45
SG		 2570 nvme_stop_ctrl(&dev->ctrl);
2571 nvme_remove_namespaces(&dev->ctrl);
a5cdb68c 2572 nvme_dev_disable(dev, true);
87ad72a5 2573 nvme_free_host_mem(dev);
a4aea562 2574 nvme_dev_remove_admin(dev);
a1a5ef99 2575 nvme_free_queues(dev, 0);
d09f2b45 2576 nvme_uninit_ctrl(&dev->ctrl);
9a6b9458 2577 nvme_release_prp_pools(dev);
b00a726a 2578 nvme_dev_unmap(dev);
1673f1f0 2579 nvme_put_ctrl(&dev->ctrl);
b60503ba
MW		 2580}
2581
13880f5b
KB		 2582static int nvme_pci_sriov_configure(struct pci_dev *pdev, int numvfs)
2583{
2584 int ret = 0;
2585
2586 if (numvfs == 0) {
2587 if (pci_vfs_assigned(pdev)) {
2588 dev_warn(&pdev->dev,
2589 "Cannot disable SR-IOV VFs while assigned\n");
2590 return -EPERM;
2591 }
2592 pci_disable_sriov(pdev);
2593 return 0;
2594 }
2595
2596 ret = pci_enable_sriov(pdev, numvfs);
2597 return ret ? ret : numvfs;
2598}
2599
671a6018 2600#ifdef CONFIG_PM_SLEEP
cd638946
KB		 2601static int nvme_suspend(struct device *dev)
2602{
2603 struct pci_dev *pdev = to_pci_dev(dev);
2604 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2605
a5cdb68c 2606 nvme_dev_disable(ndev, true);
cd638946
KB		 2607 return 0;
2608}
2609
2610static int nvme_resume(struct device *dev)
2611{
2612 struct pci_dev *pdev = to_pci_dev(dev);
2613 struct nvme_dev *ndev = pci_get_drvdata(pdev);
cd638946 2614
d86c4d8e 2615 nvme_reset_ctrl(&ndev->ctrl);
9a6b9458 2616 return 0;
cd638946 2617}
671a6018 2618#endif
cd638946
KB		 2619
2620static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
b60503ba 2621
a0a3408e
KB		 2622static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
2623 pci_channel_state_t state)
2624{
2625 struct nvme_dev *dev = pci_get_drvdata(pdev);
2626
2627 /*
2628 * A frozen channel requires a reset. When detected, this method will
2629 * shutdown the controller to quiesce. The controller will be restarted
2630 * after the slot reset through driver's slot_reset callback.
2631 */
a0a3408e
KB		 2632 switch (state) {
2633 case pci_channel_io_normal:
2634 return PCI_ERS_RESULT_CAN_RECOVER;
2635 case pci_channel_io_frozen:
d011fb31
KB		 2636 dev_warn(dev->ctrl.device,
2637 "frozen state error detected, reset controller\n");
a5cdb68c 2638 nvme_dev_disable(dev, false);
a0a3408e
KB		 2639 return PCI_ERS_RESULT_NEED_RESET;
2640 case pci_channel_io_perm_failure:
d011fb31
KB		 2641 dev_warn(dev->ctrl.device,
2642 "failure state error detected, request disconnect\n");
a0a3408e
KB		 2643 return PCI_ERS_RESULT_DISCONNECT;
2644 }
2645 return PCI_ERS_RESULT_NEED_RESET;
2646}
2647
2648static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
2649{
2650 struct nvme_dev *dev = pci_get_drvdata(pdev);
2651
1b3c47c1 2652 dev_info(dev->ctrl.device, "restart after slot reset\n");
a0a3408e 2653 pci_restore_state(pdev);
d86c4d8e 2654 nvme_reset_ctrl(&dev->ctrl);
a0a3408e
KB		 2655 return PCI_ERS_RESULT_RECOVERED;
2656}
2657
2658static void nvme_error_resume(struct pci_dev *pdev)
2659{
2660 pci_cleanup_aer_uncorrect_error_status(pdev);
2661}
2662
1d352035 2663static const struct pci_error_handlers nvme_err_handler = {
b60503ba 2664 .error_detected = nvme_error_detected,
b60503ba
MW		 2665 .slot_reset = nvme_slot_reset,
2666 .resume = nvme_error_resume,
775755ed
CH		 2667 .reset_prepare = nvme_reset_prepare,
2668 .reset_done = nvme_reset_done,
b60503ba
MW		 2669};
2670
6eb0d698 2671static const struct pci_device_id nvme_id_table[] = {
106198ed 2672 { PCI_VDEVICE(INTEL, 0x0953),
08095e70 2673 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 2674 NVME_QUIRK_DEALLOCATE_ZEROES, },
99466e70
KB		 2675 { PCI_VDEVICE(INTEL, 0x0a53),
2676 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 2677 NVME_QUIRK_DEALLOCATE_ZEROES, },
99466e70
KB		 2678 { PCI_VDEVICE(INTEL, 0x0a54),
2679 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 2680 NVME_QUIRK_DEALLOCATE_ZEROES, },
f99cb7af
DWF		 2681 { PCI_VDEVICE(INTEL, 0x0a55),
2682 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2683 NVME_QUIRK_DEALLOCATE_ZEROES, },
50af47d0
AL		 2684 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */
2685 .driver_data = NVME_QUIRK_NO_DEEPEST_PS },
540c801c
KB		 2686 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */
2687 .driver_data = NVME_QUIRK_IDENTIFY_CNS, },
54adc010
GP		 2688 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
2689 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
8c97eecc
JL		 2690 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */
2691 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
015282c9
WW		 2692 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
2693 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
d554b5e1
MP		 2694 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */
2695 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2696 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */
2697 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
608cc4b1
CH		 2698 { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */
2699 .driver_data = NVME_QUIRK_LIGHTNVM, },
2700 { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */
2701 .driver_data = NVME_QUIRK_LIGHTNVM, },
b60503ba 2702 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
c74dc780 2703 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) },
124298bd 2704 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
b60503ba
MW		 2705 { 0, }
2706};
2707MODULE_DEVICE_TABLE(pci, nvme_id_table);
2708
2709static struct pci_driver nvme_driver = {
2710 .name = "nvme",
2711 .id_table = nvme_id_table,
2712 .probe = nvme_probe,
8d85fce7 2713 .remove = nvme_remove,
09ece142 2714 .shutdown = nvme_shutdown,
cd638946
KB		 2715 .driver = {
2716 .pm = &nvme_dev_pm_ops,
2717 },
13880f5b 2718 .sriov_configure = nvme_pci_sriov_configure,
b60503ba
MW		 2719 .err_handler = &nvme_err_handler,
2720};
2721
2722static int __init nvme_init(void)
2723{
9a6327d2 2724 return pci_register_driver(&nvme_driver);
b60503ba
MW		 2725}
2726
2727static void __exit nvme_exit(void)
2728{
2729 pci_unregister_driver(&nvme_driver);
03e0f3a6 2730 flush_workqueue(nvme_wq);
21bd78bc 2731 _nvme_check_size();
b60503ba
MW		 2732}
2733
2734MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2735MODULE_LICENSE("GPL");
c78b4713 2736MODULE_VERSION("1.0");
b60503ba
MW		 2737module_init(nvme_init);
2738module_exit(nvme_exit);
Linux 6.x block layer and io_uring tree(s)