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nvmet-tcp: implement C2HData SUCCESS optimization
[linux-2.6-block.git] / drivers / nvme / host / pci.c
CommitLineData
5f37396d 1// SPDX-License-Identifier: GPL-2.0
b60503ba
MW		 2/*
3 * NVM Express device driver
6eb0d698 4 * Copyright (c) 2011-2014, Intel Corporation.
b60503ba
MW		 5 */
6
a0a3408e 7#include <linux/aer.h>
18119775 8#include <linux/async.h>
b60503ba 9#include <linux/blkdev.h>
a4aea562 10#include <linux/blk-mq.h>
dca51e78 11#include <linux/blk-mq-pci.h>
ff5350a8 12#include <linux/dmi.h>
b60503ba
MW		 13#include <linux/init.h>
14#include <linux/interrupt.h>
15#include <linux/io.h>
b60503ba
MW		 16#include <linux/mm.h>
17#include <linux/module.h>
77bf25ea 18#include <linux/mutex.h>
d0877473 19#include <linux/once.h>
b60503ba 20#include <linux/pci.h>
e1e5e564 21#include <linux/t10-pi.h>
b60503ba 22#include <linux/types.h>
2f8e2c87 23#include <linux/io-64-nonatomic-lo-hi.h>
a98e58e5 24#include <linux/sed-opal.h>
0f238ff5 25#include <linux/pci-p2pdma.h>
797a796a 26
604c01d5 27#include "trace.h"
f11bb3e2
CH		 28#include "nvme.h"
29
b60503ba
MW		 30#define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
31#define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
c965809c 32
a7a7cbe3 33#define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc))
9d43cf64 34
943e942e
JA		 35/*
36 * These can be higher, but we need to ensure that any command doesn't
37 * require an sg allocation that needs more than a page of data.
38 */
39#define NVME_MAX_KB_SZ 4096
40#define NVME_MAX_SEGS 127
41
58ffacb5
MW		 42static int use_threaded_interrupts;
43module_param(use_threaded_interrupts, int, 0);
44
8ffaadf7 45static bool use_cmb_sqes = true;
69f4eb9f 46module_param(use_cmb_sqes, bool, 0444);
8ffaadf7
JD		 47MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
48
87ad72a5
CH		 49static unsigned int max_host_mem_size_mb = 128;
50module_param(max_host_mem_size_mb, uint, 0444);
51MODULE_PARM_DESC(max_host_mem_size_mb,
52 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
1fa6aead 53
a7a7cbe3
CK		 54static unsigned int sgl_threshold = SZ_32K;
55module_param(sgl_threshold, uint, 0644);
56MODULE_PARM_DESC(sgl_threshold,
57 "Use SGLs when average request segment size is larger or equal to "
58 "this size. Use 0 to disable SGLs.");
59
b27c1e68 60static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
61static const struct kernel_param_ops io_queue_depth_ops = {
62 .set = io_queue_depth_set,
63 .get = param_get_int,
64};
65
66static int io_queue_depth = 1024;
67module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
68MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2");
69
3b6592f7
JA		 70static int queue_count_set(const char *val, const struct kernel_param *kp);
71static const struct kernel_param_ops queue_count_ops = {
72 .set = queue_count_set,
73 .get = param_get_int,
74};
75
76static int write_queues;
77module_param_cb(write_queues, &queue_count_ops, &write_queues, 0644);
78MODULE_PARM_DESC(write_queues,
79 "Number of queues to use for writes. If not set, reads and writes "
80 "will share a queue set.");
81
a4668d9b 82static int poll_queues = 0;
4b04cc6a
JA		 83module_param_cb(poll_queues, &queue_count_ops, &poll_queues, 0644);
84MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO.");
85
1c63dc66
CH		 86struct nvme_dev;
87struct nvme_queue;
b3fffdef 88
a5cdb68c 89static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
8fae268b 90static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode);
d4b4ff8e 91
1c63dc66
CH		 92/*
93 * Represents an NVM Express device. Each nvme_dev is a PCI function.
94 */
95struct nvme_dev {
147b27e4 96 struct nvme_queue *queues;
1c63dc66
CH		 97 struct blk_mq_tag_set tagset;
98 struct blk_mq_tag_set admin_tagset;
99 u32 __iomem *dbs;
100 struct device *dev;
101 struct dma_pool *prp_page_pool;
102 struct dma_pool *prp_small_pool;
1c63dc66
CH		 103 unsigned online_queues;
104 unsigned max_qid;
e20ba6e1 105 unsigned io_queues[HCTX_MAX_TYPES];
22b55601 106 unsigned int num_vecs;
1c63dc66
CH		 107 int q_depth;
108 u32 db_stride;
1c63dc66 109 void __iomem *bar;
97f6ef64 110 unsigned long bar_mapped_size;
5c8809e6 111 struct work_struct remove_work;
77bf25ea 112 struct mutex shutdown_lock;
1c63dc66 113 bool subsystem;
1c63dc66 114 u64 cmb_size;
0f238ff5 115 bool cmb_use_sqes;
1c63dc66 116 u32 cmbsz;
202021c1 117 u32 cmbloc;
1c63dc66 118 struct nvme_ctrl ctrl;
87ad72a5 119
943e942e
JA		 120 mempool_t *iod_mempool;
121
87ad72a5 122 /* shadow doorbell buffer support: */
f9f38e33
HK		 123 u32 *dbbuf_dbs;
124 dma_addr_t dbbuf_dbs_dma_addr;
125 u32 *dbbuf_eis;
126 dma_addr_t dbbuf_eis_dma_addr;
87ad72a5
CH		 127
128 /* host memory buffer support: */
129 u64 host_mem_size;
130 u32 nr_host_mem_descs;
4033f35d 131 dma_addr_t host_mem_descs_dma;
87ad72a5
CH		 132 struct nvme_host_mem_buf_desc *host_mem_descs;
133 void **host_mem_desc_bufs;
4d115420 134};
1fa6aead 135
b27c1e68 136static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
137{
138 int n = 0, ret;
139
140 ret = kstrtoint(val, 10, &n);
141 if (ret != 0 || n < 2)
142 return -EINVAL;
143
144 return param_set_int(val, kp);
145}
146
3b6592f7
JA		 147static int queue_count_set(const char *val, const struct kernel_param *kp)
148{
149 int n = 0, ret;
150
151 ret = kstrtoint(val, 10, &n);
e895fedf
BVA		 152 if (ret)
153 return ret;
3b6592f7
JA		 154 if (n > num_possible_cpus())
155 n = num_possible_cpus();
156
157 return param_set_int(val, kp);
158}
159
f9f38e33
HK		 160static inline unsigned int sq_idx(unsigned int qid, u32 stride)
161{
162 return qid * 2 * stride;
163}
164
165static inline unsigned int cq_idx(unsigned int qid, u32 stride)
166{
167 return (qid * 2 + 1) * stride;
168}
169
1c63dc66
CH		 170static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
171{
172 return container_of(ctrl, struct nvme_dev, ctrl);
173}
174
b60503ba
MW		 175/*
176 * An NVM Express queue. Each device has at least two (one for admin
177 * commands and one for I/O commands).
178 */
179struct nvme_queue {
180 struct device *q_dmadev;
091b6092 181 struct nvme_dev *dev;
1ab0cd69 182 spinlock_t sq_lock;
b60503ba 183 struct nvme_command *sq_cmds;
3a7afd8e
CH		 184 /* only used for poll queues: */
185 spinlock_t cq_poll_lock ____cacheline_aligned_in_smp;
b60503ba 186 volatile struct nvme_completion *cqes;
42483228 187 struct blk_mq_tags **tags;
b60503ba
MW		 188 dma_addr_t sq_dma_addr;
189 dma_addr_t cq_dma_addr;
b60503ba
MW		 190 u32 __iomem *q_db;
191 u16 q_depth;
6222d172 192 s16 cq_vector;
b60503ba 193 u16 sq_tail;
04f3eafd 194 u16 last_sq_tail;
b60503ba 195 u16 cq_head;
68fa9dbe 196 u16 last_cq_head;
c30341dc 197 u16 qid;
e9539f47 198 u8 cq_phase;
4e224106
CH		 199 unsigned long flags;
200#define NVMEQ_ENABLED 0
63223078 201#define NVMEQ_SQ_CMB 1
d1ed6aa1 202#define NVMEQ_DELETE_ERROR 2
f9f38e33
HK		 203 u32 *dbbuf_sq_db;
204 u32 *dbbuf_cq_db;
205 u32 *dbbuf_sq_ei;
206 u32 *dbbuf_cq_ei;
d1ed6aa1 207 struct completion delete_done;
b60503ba
MW		 208};
209
71bd150c
CH		 210/*
211 * The nvme_iod describes the data in an I/O, including the list of PRP
212 * entries. You can't see it in this data structure because C doesn't let
f4800d6d 213 * me express that. Use nvme_init_iod to ensure there's enough space
71bd150c
CH		 214 * allocated to store the PRP list.
215 */
216struct nvme_iod {
d49187e9 217 struct nvme_request req;
f4800d6d 218 struct nvme_queue *nvmeq;
a7a7cbe3 219 bool use_sgl;
f4800d6d 220 int aborted;
71bd150c 221 int npages; /* In the PRP list. 0 means small pool in use */
71bd150c
CH		 222 int nents; /* Used in scatterlist */
223 int length; /* Of data, in bytes */
224 dma_addr_t first_dma;
bf684057 225 struct scatterlist meta_sg; /* metadata requires single contiguous buffer */
f4800d6d
CH		 226 struct scatterlist *sg;
227 struct scatterlist inline_sg[0];
b60503ba
MW		 228};
229
230/*
231 * Check we didin't inadvertently grow the command struct
232 */
233static inline void _nvme_check_size(void)
234{
235 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
236 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
237 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
238 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
239 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
f8ebf840 240 BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
c30341dc 241 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
b60503ba 242 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
0add5e8e
JT		 243 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != NVME_IDENTIFY_DATA_SIZE);
244 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != NVME_IDENTIFY_DATA_SIZE);
b60503ba 245 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
6ecec745 246 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
f9f38e33
HK		 247 BUILD_BUG_ON(sizeof(struct nvme_dbbuf) != 64);
248}
249
3b6592f7
JA		 250static unsigned int max_io_queues(void)
251{
4b04cc6a 252 return num_possible_cpus() + write_queues + poll_queues;
3b6592f7
JA		 253}
254
255static unsigned int max_queue_count(void)
256{
257 /* IO queues + admin queue */
258 return 1 + max_io_queues();
259}
260
f9f38e33
HK		 261static inline unsigned int nvme_dbbuf_size(u32 stride)
262{
3b6592f7 263 return (max_queue_count() * 8 * stride);
f9f38e33
HK		 264}
265
266static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
267{
268 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
269
270 if (dev->dbbuf_dbs)
271 return 0;
272
273 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
274 &dev->dbbuf_dbs_dma_addr,
275 GFP_KERNEL);
276 if (!dev->dbbuf_dbs)
277 return -ENOMEM;
278 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
279 &dev->dbbuf_eis_dma_addr,
280 GFP_KERNEL);
281 if (!dev->dbbuf_eis) {
282 dma_free_coherent(dev->dev, mem_size,
283 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
284 dev->dbbuf_dbs = NULL;
285 return -ENOMEM;
286 }
287
288 return 0;
289}
290
291static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
292{
293 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
294
295 if (dev->dbbuf_dbs) {
296 dma_free_coherent(dev->dev, mem_size,
297 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
298 dev->dbbuf_dbs = NULL;
299 }
300 if (dev->dbbuf_eis) {
301 dma_free_coherent(dev->dev, mem_size,
302 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
303 dev->dbbuf_eis = NULL;
304 }
305}
306
307static void nvme_dbbuf_init(struct nvme_dev *dev,
308 struct nvme_queue *nvmeq, int qid)
309{
310 if (!dev->dbbuf_dbs || !qid)
311 return;
312
313 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
314 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
315 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
316 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
317}
318
319static void nvme_dbbuf_set(struct nvme_dev *dev)
320{
321 struct nvme_command c;
322
323 if (!dev->dbbuf_dbs)
324 return;
325
326 memset(&c, 0, sizeof(c));
327 c.dbbuf.opcode = nvme_admin_dbbuf;
328 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
329 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
330
331 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
9bdcfb10 332 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
f9f38e33
HK		 333 /* Free memory and continue on */
334 nvme_dbbuf_dma_free(dev);
335 }
336}
337
338static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
339{
340 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
341}
342
343/* Update dbbuf and return true if an MMIO is required */
344static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
345 volatile u32 *dbbuf_ei)
346{
347 if (dbbuf_db) {
348 u16 old_value;
349
350 /*
351 * Ensure that the queue is written before updating
352 * the doorbell in memory
353 */
354 wmb();
355
356 old_value = *dbbuf_db;
357 *dbbuf_db = value;
358
f1ed3df2
MW		 359 /*
360 * Ensure that the doorbell is updated before reading the event
361 * index from memory. The controller needs to provide similar
362 * ordering to ensure the envent index is updated before reading
363 * the doorbell.
364 */
365 mb();
366
f9f38e33
HK		 367 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value))
368 return false;
369 }
370
371 return true;
b60503ba
MW		 372}
373
ac3dd5bd
JA		 374/*
375 * Max size of iod being embedded in the request payload
376 */
377#define NVME_INT_PAGES 2
5fd4ce1b 378#define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size)
ac3dd5bd
JA		 379
380/*
381 * Will slightly overestimate the number of pages needed. This is OK
382 * as it only leads to a small amount of wasted memory for the lifetime of
383 * the I/O.
384 */
385static int nvme_npages(unsigned size, struct nvme_dev *dev)
386{
5fd4ce1b
CH		 387 unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size,
388 dev->ctrl.page_size);
ac3dd5bd
JA		 389 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
390}
391
a7a7cbe3
CK		 392/*
393 * Calculates the number of pages needed for the SGL segments. For example a 4k
394 * page can accommodate 256 SGL descriptors.
395 */
396static int nvme_pci_npages_sgl(unsigned int num_seg)
ac3dd5bd 397{
a7a7cbe3 398 return DIV_ROUND_UP(num_seg * sizeof(struct nvme_sgl_desc), PAGE_SIZE);
f4800d6d 399}
ac3dd5bd 400
a7a7cbe3
CK		 401static unsigned int nvme_pci_iod_alloc_size(struct nvme_dev *dev,
402 unsigned int size, unsigned int nseg, bool use_sgl)
f4800d6d 403{
a7a7cbe3
CK		 404 size_t alloc_size;
405
406 if (use_sgl)
407 alloc_size = sizeof(__le64 *) * nvme_pci_npages_sgl(nseg);
408 else
409 alloc_size = sizeof(__le64 *) * nvme_npages(size, dev);
410
411 return alloc_size + sizeof(struct scatterlist) * nseg;
f4800d6d 412}
ac3dd5bd 413
a7a7cbe3 414static unsigned int nvme_pci_cmd_size(struct nvme_dev *dev, bool use_sgl)
f4800d6d 415{
a7a7cbe3
CK		 416 unsigned int alloc_size = nvme_pci_iod_alloc_size(dev,
417 NVME_INT_BYTES(dev), NVME_INT_PAGES,
418 use_sgl);
419
420 return sizeof(struct nvme_iod) + alloc_size;
ac3dd5bd
JA		 421}
422
a4aea562
MB		 423static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
424 unsigned int hctx_idx)
e85248e5 425{
a4aea562 426 struct nvme_dev *dev = data;
147b27e4 427 struct nvme_queue *nvmeq = &dev->queues[0];
a4aea562 428
42483228
KB		 429 WARN_ON(hctx_idx != 0);
430 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
431 WARN_ON(nvmeq->tags);
432
a4aea562 433 hctx->driver_data = nvmeq;
42483228 434 nvmeq->tags = &dev->admin_tagset.tags[0];
a4aea562 435 return 0;
e85248e5
MW		 436}
437
4af0e21c
KB		 438static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
439{
440 struct nvme_queue *nvmeq = hctx->driver_data;
441
442 nvmeq->tags = NULL;
443}
444
a4aea562
MB		 445static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
446 unsigned int hctx_idx)
b60503ba 447{
a4aea562 448 struct nvme_dev *dev = data;
147b27e4 449 struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
a4aea562 450
42483228
KB		 451 if (!nvmeq->tags)
452 nvmeq->tags = &dev->tagset.tags[hctx_idx];
b60503ba 453
42483228 454 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
a4aea562
MB		 455 hctx->driver_data = nvmeq;
456 return 0;
b60503ba
MW		 457}
458
d6296d39
CH		 459static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req,
460 unsigned int hctx_idx, unsigned int numa_node)
b60503ba 461{
d6296d39 462 struct nvme_dev *dev = set->driver_data;
f4800d6d 463 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
0350815a 464 int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0;
147b27e4 465 struct nvme_queue *nvmeq = &dev->queues[queue_idx];
a4aea562
MB		 466
467 BUG_ON(!nvmeq);
f4800d6d 468 iod->nvmeq = nvmeq;
59e29ce6
SG		 469
470 nvme_req(req)->ctrl = &dev->ctrl;
a4aea562
MB		 471 return 0;
472}
473
3b6592f7
JA		 474static int queue_irq_offset(struct nvme_dev *dev)
475{
476 /* if we have more than 1 vec, admin queue offsets us by 1 */
477 if (dev->num_vecs > 1)
478 return 1;
479
480 return 0;
481}
482
dca51e78
CH		 483static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
484{
485 struct nvme_dev *dev = set->driver_data;
3b6592f7
JA		 486 int i, qoff, offset;
487
488 offset = queue_irq_offset(dev);
489 for (i = 0, qoff = 0; i < set->nr_maps; i++) {
490 struct blk_mq_queue_map *map = &set->map[i];
491
492 map->nr_queues = dev->io_queues[i];
493 if (!map->nr_queues) {
e20ba6e1 494 BUG_ON(i == HCTX_TYPE_DEFAULT);
7e849dd9 495 continue;
3b6592f7
JA		 496 }
497
4b04cc6a
JA		 498 /*
499 * The poll queue(s) doesn't have an IRQ (and hence IRQ
500 * affinity), so use the regular blk-mq cpu mapping
501 */
3b6592f7 502 map->queue_offset = qoff;
e20ba6e1 503 if (i != HCTX_TYPE_POLL)
4b04cc6a
JA		 504 blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset);
505 else
506 blk_mq_map_queues(map);
3b6592f7
JA		 507 qoff += map->nr_queues;
508 offset += map->nr_queues;
509 }
510
511 return 0;
dca51e78
CH		 512}
513
04f3eafd
JA		 514/*
515 * Write sq tail if we are asked to, or if the next command would wrap.
516 */
517static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq)
518{
519 if (!write_sq) {
520 u16 next_tail = nvmeq->sq_tail + 1;
521
522 if (next_tail == nvmeq->q_depth)
523 next_tail = 0;
524 if (next_tail != nvmeq->last_sq_tail)
525 return;
526 }
527
528 if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail,
529 nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei))
530 writel(nvmeq->sq_tail, nvmeq->q_db);
531 nvmeq->last_sq_tail = nvmeq->sq_tail;
532}
533
b60503ba 534/**
90ea5ca4 535 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
b60503ba
MW		 536 * @nvmeq: The queue to use
537 * @cmd: The command to send
04f3eafd 538 * @write_sq: whether to write to the SQ doorbell
b60503ba 539 */
04f3eafd
JA		 540static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd,
541 bool write_sq)
b60503ba 542{
90ea5ca4 543 spin_lock(&nvmeq->sq_lock);
0f238ff5 544 memcpy(&nvmeq->sq_cmds[nvmeq->sq_tail], cmd, sizeof(*cmd));
90ea5ca4
CH		 545 if (++nvmeq->sq_tail == nvmeq->q_depth)
546 nvmeq->sq_tail = 0;
04f3eafd
JA		 547 nvme_write_sq_db(nvmeq, write_sq);
548 spin_unlock(&nvmeq->sq_lock);
549}
550
551static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx)
552{
553 struct nvme_queue *nvmeq = hctx->driver_data;
554
555 spin_lock(&nvmeq->sq_lock);
556 if (nvmeq->sq_tail != nvmeq->last_sq_tail)
557 nvme_write_sq_db(nvmeq, true);
90ea5ca4 558 spin_unlock(&nvmeq->sq_lock);
b60503ba
MW		 559}
560
a7a7cbe3 561static void **nvme_pci_iod_list(struct request *req)
b60503ba 562{
f4800d6d 563 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3 564 return (void **)(iod->sg + blk_rq_nr_phys_segments(req));
b60503ba
MW		 565}
566
955b1b5a
MI		 567static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req)
568{
569 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
20469a37 570 int nseg = blk_rq_nr_phys_segments(req);
955b1b5a
MI		 571 unsigned int avg_seg_size;
572
20469a37
KB		 573 if (nseg == 0)
574 return false;
575
576 avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
955b1b5a
MI		 577
578 if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1))))
579 return false;
580 if (!iod->nvmeq->qid)
581 return false;
582 if (!sgl_threshold || avg_seg_size < sgl_threshold)
583 return false;
584 return true;
585}
586
fc17b653 587static blk_status_t nvme_init_iod(struct request *rq, struct nvme_dev *dev)
ac3dd5bd 588{
f4800d6d 589 struct nvme_iod *iod = blk_mq_rq_to_pdu(rq);
f9d03f96 590 int nseg = blk_rq_nr_phys_segments(rq);
b131c61d 591 unsigned int size = blk_rq_payload_bytes(rq);
ac3dd5bd 592
955b1b5a
MI		 593 iod->use_sgl = nvme_pci_use_sgls(dev, rq);
594
f4800d6d 595 if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) {
943e942e 596 iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC);
f4800d6d 597 if (!iod->sg)
fc17b653 598 return BLK_STS_RESOURCE;
f4800d6d
CH		 599 } else {
600 iod->sg = iod->inline_sg;
ac3dd5bd
JA		 601 }
602
f4800d6d
CH		 603 iod->aborted = 0;
604 iod->npages = -1;
605 iod->nents = 0;
606 iod->length = size;
f80ec966 607
fc17b653 608 return BLK_STS_OK;
ac3dd5bd
JA		 609}
610
f4800d6d 611static void nvme_free_iod(struct nvme_dev *dev, struct request *req)
b60503ba 612{
f4800d6d 613 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3
CK		 614 const int last_prp = dev->ctrl.page_size / sizeof(__le64) - 1;
615 dma_addr_t dma_addr = iod->first_dma, next_dma_addr;
616
eca18b23 617 int i;
eca18b23
MW		 618
619 if (iod->npages == 0)
a7a7cbe3
CK		 620 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0],
621 dma_addr);
622
eca18b23 623 for (i = 0; i < iod->npages; i++) {
a7a7cbe3
CK		 624 void *addr = nvme_pci_iod_list(req)[i];
625
626 if (iod->use_sgl) {
627 struct nvme_sgl_desc *sg_list = addr;
628
629 next_dma_addr =
630 le64_to_cpu((sg_list[SGES_PER_PAGE - 1]).addr);
631 } else {
632 __le64 *prp_list = addr;
633
634 next_dma_addr = le64_to_cpu(prp_list[last_prp]);
635 }
636
637 dma_pool_free(dev->prp_page_pool, addr, dma_addr);
638 dma_addr = next_dma_addr;
eca18b23 639 }
ac3dd5bd 640
f4800d6d 641 if (iod->sg != iod->inline_sg)
943e942e 642 mempool_free(iod->sg, dev->iod_mempool);
b4ff9c8d
KB		 643}
644
d0877473
KB		 645static void nvme_print_sgl(struct scatterlist *sgl, int nents)
646{
647 int i;
648 struct scatterlist *sg;
649
650 for_each_sg(sgl, sg, nents, i) {
651 dma_addr_t phys = sg_phys(sg);
652 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
653 "dma_address:%pad dma_length:%d\n",
654 i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
655 sg_dma_len(sg));
656 }
657}
658
a7a7cbe3
CK		 659static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
660 struct request *req, struct nvme_rw_command *cmnd)
ff22b54f 661{
f4800d6d 662 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
99802a7a 663 struct dma_pool *pool;
b131c61d 664 int length = blk_rq_payload_bytes(req);
eca18b23 665 struct scatterlist *sg = iod->sg;
ff22b54f
MW		 666 int dma_len = sg_dma_len(sg);
667 u64 dma_addr = sg_dma_address(sg);
5fd4ce1b 668 u32 page_size = dev->ctrl.page_size;
f137e0f1 669 int offset = dma_addr & (page_size - 1);
e025344c 670 __le64 *prp_list;
a7a7cbe3 671 void **list = nvme_pci_iod_list(req);
e025344c 672 dma_addr_t prp_dma;
eca18b23 673 int nprps, i;
ff22b54f 674
1d090624 675 length -= (page_size - offset);
5228b328
JS		 676 if (length <= 0) {
677 iod->first_dma = 0;
a7a7cbe3 678 goto done;
5228b328 679 }
ff22b54f 680
1d090624 681 dma_len -= (page_size - offset);
ff22b54f 682 if (dma_len) {
1d090624 683 dma_addr += (page_size - offset);
ff22b54f
MW		 684 } else {
685 sg = sg_next(sg);
686 dma_addr = sg_dma_address(sg);
687 dma_len = sg_dma_len(sg);
688 }
689
1d090624 690 if (length <= page_size) {
edd10d33 691 iod->first_dma = dma_addr;
a7a7cbe3 692 goto done;
e025344c
SMM		 693 }
694
1d090624 695 nprps = DIV_ROUND_UP(length, page_size);
99802a7a
MW		 696 if (nprps <= (256 / 8)) {
697 pool = dev->prp_small_pool;
eca18b23 698 iod->npages = 0;
99802a7a
MW		 699 } else {
700 pool = dev->prp_page_pool;
eca18b23 701 iod->npages = 1;
99802a7a
MW		 702 }
703
69d2b571 704 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
b77954cb 705 if (!prp_list) {
edd10d33 706 iod->first_dma = dma_addr;
eca18b23 707 iod->npages = -1;
86eea289 708 return BLK_STS_RESOURCE;
b77954cb 709 }
eca18b23
MW		 710 list[0] = prp_list;
711 iod->first_dma = prp_dma;
e025344c
SMM		 712 i = 0;
713 for (;;) {
1d090624 714 if (i == page_size >> 3) {
e025344c 715 __le64 *old_prp_list = prp_list;
69d2b571 716 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
eca18b23 717 if (!prp_list)
86eea289 718 return BLK_STS_RESOURCE;
eca18b23 719 list[iod->npages++] = prp_list;
7523d834
MW		 720 prp_list[0] = old_prp_list[i - 1];
721 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
722 i = 1;
e025344c
SMM		 723 }
724 prp_list[i++] = cpu_to_le64(dma_addr);
1d090624
KB		 725 dma_len -= page_size;
726 dma_addr += page_size;
727 length -= page_size;
e025344c
SMM		 728 if (length <= 0)
729 break;
730 if (dma_len > 0)
731 continue;
86eea289
KB		 732 if (unlikely(dma_len < 0))
733 goto bad_sgl;
e025344c
SMM		 734 sg = sg_next(sg);
735 dma_addr = sg_dma_address(sg);
736 dma_len = sg_dma_len(sg);
ff22b54f
MW		 737 }
738
a7a7cbe3
CK		 739done:
740 cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
741 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
742
86eea289
KB		 743 return BLK_STS_OK;
744
745 bad_sgl:
d0877473
KB		 746 WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents),
747 "Invalid SGL for payload:%d nents:%d\n",
748 blk_rq_payload_bytes(req), iod->nents);
86eea289 749 return BLK_STS_IOERR;
ff22b54f
MW		 750}
751
a7a7cbe3
CK		 752static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
753 struct scatterlist *sg)
754{
755 sge->addr = cpu_to_le64(sg_dma_address(sg));
756 sge->length = cpu_to_le32(sg_dma_len(sg));
757 sge->type = NVME_SGL_FMT_DATA_DESC << 4;
758}
759
760static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
761 dma_addr_t dma_addr, int entries)
762{
763 sge->addr = cpu_to_le64(dma_addr);
764 if (entries < SGES_PER_PAGE) {
765 sge->length = cpu_to_le32(entries * sizeof(*sge));
766 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
767 } else {
768 sge->length = cpu_to_le32(PAGE_SIZE);
769 sge->type = NVME_SGL_FMT_SEG_DESC << 4;
770 }
771}
772
773static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
b0f2853b 774 struct request *req, struct nvme_rw_command *cmd, int entries)
a7a7cbe3
CK		 775{
776 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3
CK		 777 struct dma_pool *pool;
778 struct nvme_sgl_desc *sg_list;
779 struct scatterlist *sg = iod->sg;
a7a7cbe3 780 dma_addr_t sgl_dma;
b0f2853b 781 int i = 0;
a7a7cbe3 782
a7a7cbe3
CK		 783 /* setting the transfer type as SGL */
784 cmd->flags = NVME_CMD_SGL_METABUF;
785
b0f2853b 786 if (entries == 1) {
a7a7cbe3
CK		 787 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
788 return BLK_STS_OK;
789 }
790
791 if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
792 pool = dev->prp_small_pool;
793 iod->npages = 0;
794 } else {
795 pool = dev->prp_page_pool;
796 iod->npages = 1;
797 }
798
799 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
800 if (!sg_list) {
801 iod->npages = -1;
802 return BLK_STS_RESOURCE;
803 }
804
805 nvme_pci_iod_list(req)[0] = sg_list;
806 iod->first_dma = sgl_dma;
807
808 nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
809
810 do {
811 if (i == SGES_PER_PAGE) {
812 struct nvme_sgl_desc *old_sg_desc = sg_list;
813 struct nvme_sgl_desc *link = &old_sg_desc[i - 1];
814
815 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
816 if (!sg_list)
817 return BLK_STS_RESOURCE;
818
819 i = 0;
820 nvme_pci_iod_list(req)[iod->npages++] = sg_list;
821 sg_list[i++] = *link;
822 nvme_pci_sgl_set_seg(link, sgl_dma, entries);
823 }
824
825 nvme_pci_sgl_set_data(&sg_list[i++], sg);
a7a7cbe3 826 sg = sg_next(sg);
b0f2853b 827 } while (--entries > 0);
a7a7cbe3 828
a7a7cbe3
CK		 829 return BLK_STS_OK;
830}
831
fc17b653 832static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
b131c61d 833 struct nvme_command *cmnd)
d29ec824 834{
f4800d6d 835 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
ba1ca37e
CH		 836 struct request_queue *q = req->q;
837 enum dma_data_direction dma_dir = rq_data_dir(req) ?
838 DMA_TO_DEVICE : DMA_FROM_DEVICE;
fc17b653 839 blk_status_t ret = BLK_STS_IOERR;
b0f2853b 840 int nr_mapped;
d29ec824 841
f9d03f96 842 sg_init_table(iod->sg, blk_rq_nr_phys_segments(req));
ba1ca37e
CH		 843 iod->nents = blk_rq_map_sg(q, req, iod->sg);
844 if (!iod->nents)
845 goto out;
d29ec824 846
fc17b653 847 ret = BLK_STS_RESOURCE;
e0596ab2
LG		 848
849 if (is_pci_p2pdma_page(sg_page(iod->sg)))
850 nr_mapped = pci_p2pdma_map_sg(dev->dev, iod->sg, iod->nents,
851 dma_dir);
852 else
853 nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents,
854 dma_dir, DMA_ATTR_NO_WARN);
b0f2853b 855 if (!nr_mapped)
ba1ca37e 856 goto out;
d29ec824 857
955b1b5a 858 if (iod->use_sgl)
b0f2853b 859 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped);
a7a7cbe3
CK		 860 else
861 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
862
86eea289 863 if (ret != BLK_STS_OK)
ba1ca37e 864 goto out_unmap;
0e5e4f0e 865
fc17b653 866 ret = BLK_STS_IOERR;
ba1ca37e
CH		 867 if (blk_integrity_rq(req)) {
868 if (blk_rq_count_integrity_sg(q, req->bio) != 1)
869 goto out_unmap;
0e5e4f0e 870
bf684057
CH		 871 sg_init_table(&iod->meta_sg, 1);
872 if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1)
ba1ca37e 873 goto out_unmap;
0e5e4f0e 874
bf684057 875 if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir))
ba1ca37e 876 goto out_unmap;
00df5cb4 877
bf684057 878 cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg));
3045c0d0
CK		 879 }
880
fc17b653 881 return BLK_STS_OK;
00df5cb4 882
ba1ca37e
CH		 883out_unmap:
884 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
885out:
886 return ret;
00df5cb4
MW		 887}
888
f4800d6d 889static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
b60503ba 890{
f4800d6d 891 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
d4f6c3ab
CH		 892 enum dma_data_direction dma_dir = rq_data_dir(req) ?
893 DMA_TO_DEVICE : DMA_FROM_DEVICE;
894
895 if (iod->nents) {
e0596ab2
LG		 896 /* P2PDMA requests do not need to be unmapped */
897 if (!is_pci_p2pdma_page(sg_page(iod->sg)))
898 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
899
f7f1fc36 900 if (blk_integrity_rq(req))
bf684057 901 dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir);
e19b127f 902 }
e1e5e564 903
f9d03f96 904 nvme_cleanup_cmd(req);
f4800d6d 905 nvme_free_iod(dev, req);
d4f6c3ab 906}
b60503ba 907
d29ec824
CH		 908/*
909 * NOTE: ns is NULL when called on the admin queue.
910 */
fc17b653 911static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
a4aea562 912 const struct blk_mq_queue_data *bd)
edd10d33 913{
a4aea562
MB		 914 struct nvme_ns *ns = hctx->queue->queuedata;
915 struct nvme_queue *nvmeq = hctx->driver_data;
d29ec824 916 struct nvme_dev *dev = nvmeq->dev;
a4aea562 917 struct request *req = bd->rq;
ba1ca37e 918 struct nvme_command cmnd;
ebe6d874 919 blk_status_t ret;
e1e5e564 920
d1f06f4a
JA		 921 /*
922 * We should not need to do this, but we're still using this to
923 * ensure we can drain requests on a dying queue.
924 */
4e224106 925 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
d1f06f4a
JA		 926 return BLK_STS_IOERR;
927
f9d03f96 928 ret = nvme_setup_cmd(ns, req, &cmnd);
fc17b653 929 if (ret)
f4800d6d 930 return ret;
a4aea562 931
b131c61d 932 ret = nvme_init_iod(req, dev);
fc17b653 933 if (ret)
f9d03f96 934 goto out_free_cmd;
a4aea562 935
fc17b653 936 if (blk_rq_nr_phys_segments(req)) {
b131c61d 937 ret = nvme_map_data(dev, req, &cmnd);
fc17b653
CH		 938 if (ret)
939 goto out_cleanup_iod;
940 }
a4aea562 941
aae239e1 942 blk_mq_start_request(req);
04f3eafd 943 nvme_submit_cmd(nvmeq, &cmnd, bd->last);
fc17b653 944 return BLK_STS_OK;
f9d03f96 945out_cleanup_iod:
f4800d6d 946 nvme_free_iod(dev, req);
f9d03f96
CH		 947out_free_cmd:
948 nvme_cleanup_cmd(req);
ba1ca37e 949 return ret;
b60503ba 950}
e1e5e564 951
77f02a7a 952static void nvme_pci_complete_rq(struct request *req)
eee417b0 953{
f4800d6d 954 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a4aea562 955
77f02a7a
CH		 956 nvme_unmap_data(iod->nvmeq->dev, req);
957 nvme_complete_rq(req);
b60503ba
MW		 958}
959
d783e0bd 960/* We read the CQE phase first to check if the rest of the entry is valid */
750dde44 961static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq)
d783e0bd 962{
750dde44
CH		 963 return (le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) ==
964 nvmeq->cq_phase;
d783e0bd
MR		 965}
966
eb281c82 967static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
b60503ba 968{
eb281c82 969 u16 head = nvmeq->cq_head;
adf68f21 970
397c699f
KB		 971 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
972 nvmeq->dbbuf_cq_ei))
973 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
eb281c82 974}
aae239e1 975
5cb525c8 976static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx)
83a12fb7 977{
5cb525c8 978 volatile struct nvme_completion *cqe = &nvmeq->cqes[idx];
83a12fb7 979 struct request *req;
adf68f21 980
83a12fb7
SG		 981 if (unlikely(cqe->command_id >= nvmeq->q_depth)) {
982 dev_warn(nvmeq->dev->ctrl.device,
983 "invalid id %d completed on queue %d\n",
984 cqe->command_id, le16_to_cpu(cqe->sq_id));
985 return;
b60503ba
MW		 986 }
987
83a12fb7
SG		 988 /*
989 * AEN requests are special as they don't time out and can
990 * survive any kind of queue freeze and often don't respond to
991 * aborts. We don't even bother to allocate a struct request
992 * for them but rather special case them here.
993 */
994 if (unlikely(nvmeq->qid == 0 &&
38dabe21 995 cqe->command_id >= NVME_AQ_BLK_MQ_DEPTH)) {
83a12fb7
SG		 996 nvme_complete_async_event(&nvmeq->dev->ctrl,
997 cqe->status, &cqe->result);
a0fa9647 998 return;
83a12fb7 999 }
b60503ba 1000
83a12fb7 1001 req = blk_mq_tag_to_rq(*nvmeq->tags, cqe->command_id);
604c01d5 1002 trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail);
83a12fb7
SG		 1003 nvme_end_request(req, cqe->status, cqe->result);
1004}
b60503ba 1005
5cb525c8 1006static void nvme_complete_cqes(struct nvme_queue *nvmeq, u16 start, u16 end)
b60503ba 1007{
5cb525c8
JA		 1008 while (start != end) {
1009 nvme_handle_cqe(nvmeq, start);
1010 if (++start == nvmeq->q_depth)
1011 start = 0;
1012 }
1013}
adf68f21 1014
5cb525c8
JA		 1015static inline void nvme_update_cq_head(struct nvme_queue *nvmeq)
1016{
dcca1662 1017 if (nvmeq->cq_head == nvmeq->q_depth - 1) {
5cb525c8
JA		 1018 nvmeq->cq_head = 0;
1019 nvmeq->cq_phase = !nvmeq->cq_phase;
dcca1662
HY		 1020 } else {
1021 nvmeq->cq_head++;
b60503ba 1022 }
a0fa9647
JA		 1023}
1024
1052b8ac
JA		 1025static inline int nvme_process_cq(struct nvme_queue *nvmeq, u16 *start,
1026 u16 *end, unsigned int tag)
a0fa9647 1027{
1052b8ac 1028 int found = 0;
b60503ba 1029
5cb525c8 1030 *start = nvmeq->cq_head;
1052b8ac
JA		 1031 while (nvme_cqe_pending(nvmeq)) {
1032 if (tag == -1U || nvmeq->cqes[nvmeq->cq_head].command_id == tag)
1033 found++;
5cb525c8 1034 nvme_update_cq_head(nvmeq);
920d13a8 1035 }
5cb525c8 1036 *end = nvmeq->cq_head;
eb281c82 1037
5cb525c8 1038 if (*start != *end)
920d13a8 1039 nvme_ring_cq_doorbell(nvmeq);
5cb525c8 1040 return found;
b60503ba
MW		 1041}
1042
1043static irqreturn_t nvme_irq(int irq, void *data)
58ffacb5 1044{
58ffacb5 1045 struct nvme_queue *nvmeq = data;
68fa9dbe 1046 irqreturn_t ret = IRQ_NONE;
5cb525c8
JA		 1047 u16 start, end;
1048
3a7afd8e
CH		 1049 /*
1050 * The rmb/wmb pair ensures we see all updates from a previous run of
1051 * the irq handler, even if that was on another CPU.
1052 */
1053 rmb();
68fa9dbe
JA		 1054 if (nvmeq->cq_head != nvmeq->last_cq_head)
1055 ret = IRQ_HANDLED;
5cb525c8 1056 nvme_process_cq(nvmeq, &start, &end, -1);
68fa9dbe 1057 nvmeq->last_cq_head = nvmeq->cq_head;
3a7afd8e 1058 wmb();
5cb525c8 1059
68fa9dbe
JA		 1060 if (start != end) {
1061 nvme_complete_cqes(nvmeq, start, end);
1062 return IRQ_HANDLED;
1063 }
1064
1065 return ret;
58ffacb5
MW		 1066}
1067
1068static irqreturn_t nvme_irq_check(int irq, void *data)
1069{
1070 struct nvme_queue *nvmeq = data;
750dde44 1071 if (nvme_cqe_pending(nvmeq))
d783e0bd
MR		 1072 return IRQ_WAKE_THREAD;
1073 return IRQ_NONE;
58ffacb5
MW		 1074}
1075
0b2a8a9f
CH		 1076/*
1077 * Poll for completions any queue, including those not dedicated to polling.
1078 * Can be called from any context.
1079 */
1080static int nvme_poll_irqdisable(struct nvme_queue *nvmeq, unsigned int tag)
a0fa9647 1081{
3a7afd8e 1082 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
5cb525c8 1083 u16 start, end;
1052b8ac 1084 int found;
a0fa9647 1085
3a7afd8e
CH		 1086 /*
1087 * For a poll queue we need to protect against the polling thread
1088 * using the CQ lock. For normal interrupt driven threads we have
1089 * to disable the interrupt to avoid racing with it.
1090 */
91a509f8 1091 if (nvmeq->cq_vector == -1) {
3a7afd8e 1092 spin_lock(&nvmeq->cq_poll_lock);
91a509f8 1093 found = nvme_process_cq(nvmeq, &start, &end, tag);
3a7afd8e 1094 spin_unlock(&nvmeq->cq_poll_lock);
91a509f8
CH		 1095 } else {
1096 disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1097 found = nvme_process_cq(nvmeq, &start, &end, tag);
3a7afd8e 1098 enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
91a509f8 1099 }
442e19b7 1100
5cb525c8 1101 nvme_complete_cqes(nvmeq, start, end);
442e19b7 1102 return found;
a0fa9647
JA		 1103}
1104
9743139c 1105static int nvme_poll(struct blk_mq_hw_ctx *hctx)
dabcefab
JA		 1106{
1107 struct nvme_queue *nvmeq = hctx->driver_data;
1108 u16 start, end;
1109 bool found;
1110
1111 if (!nvme_cqe_pending(nvmeq))
1112 return 0;
1113
3a7afd8e 1114 spin_lock(&nvmeq->cq_poll_lock);
9743139c 1115 found = nvme_process_cq(nvmeq, &start, &end, -1);
3a7afd8e 1116 spin_unlock(&nvmeq->cq_poll_lock);
dabcefab
JA		 1117
1118 nvme_complete_cqes(nvmeq, start, end);
1119 return found;
1120}
1121
ad22c355 1122static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
b60503ba 1123{
f866fc42 1124 struct nvme_dev *dev = to_nvme_dev(ctrl);
147b27e4 1125 struct nvme_queue *nvmeq = &dev->queues[0];
a4aea562 1126 struct nvme_command c;
b60503ba 1127
a4aea562
MB		 1128 memset(&c, 0, sizeof(c));
1129 c.common.opcode = nvme_admin_async_event;
ad22c355 1130 c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
04f3eafd 1131 nvme_submit_cmd(nvmeq, &c, true);
f705f837
CH		 1132}
1133
b60503ba 1134static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
f705f837 1135{
b60503ba
MW		 1136 struct nvme_command c;
1137
1138 memset(&c, 0, sizeof(c));
1139 c.delete_queue.opcode = opcode;
1140 c.delete_queue.qid = cpu_to_le16(id);
1141
1c63dc66 1142 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1143}
1144
b60503ba 1145static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
a8e3e0bb 1146 struct nvme_queue *nvmeq, s16 vector)
b60503ba 1147{
b60503ba 1148 struct nvme_command c;
4b04cc6a
JA		 1149 int flags = NVME_QUEUE_PHYS_CONTIG;
1150
1151 if (vector != -1)
1152 flags |= NVME_CQ_IRQ_ENABLED;
b60503ba 1153
d29ec824 1154 /*
16772ae6 1155 * Note: we (ab)use the fact that the prp fields survive if no data
d29ec824
CH		 1156 * is attached to the request.
1157 */
b60503ba
MW		 1158 memset(&c, 0, sizeof(c));
1159 c.create_cq.opcode = nvme_admin_create_cq;
1160 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1161 c.create_cq.cqid = cpu_to_le16(qid);
1162 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1163 c.create_cq.cq_flags = cpu_to_le16(flags);
4b04cc6a
JA		 1164 if (vector != -1)
1165 c.create_cq.irq_vector = cpu_to_le16(vector);
1166 else
1167 c.create_cq.irq_vector = 0;
b60503ba 1168
1c63dc66 1169 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1170}
1171
1172static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1173 struct nvme_queue *nvmeq)
1174{
9abd68ef 1175 struct nvme_ctrl *ctrl = &dev->ctrl;
b60503ba 1176 struct nvme_command c;
81c1cd98 1177 int flags = NVME_QUEUE_PHYS_CONTIG;
b60503ba 1178
9abd68ef
JA		 1179 /*
1180 * Some drives have a bug that auto-enables WRRU if MEDIUM isn't
1181 * set. Since URGENT priority is zeroes, it makes all queues
1182 * URGENT.
1183 */
1184 if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ)
1185 flags |= NVME_SQ_PRIO_MEDIUM;
1186
d29ec824 1187 /*
16772ae6 1188 * Note: we (ab)use the fact that the prp fields survive if no data
d29ec824
CH		 1189 * is attached to the request.
1190 */
b60503ba
MW		 1191 memset(&c, 0, sizeof(c));
1192 c.create_sq.opcode = nvme_admin_create_sq;
1193 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1194 c.create_sq.sqid = cpu_to_le16(qid);
1195 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1196 c.create_sq.sq_flags = cpu_to_le16(flags);
1197 c.create_sq.cqid = cpu_to_le16(qid);
1198
1c63dc66 1199 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1200}
1201
1202static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1203{
1204 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1205}
1206
1207static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1208{
1209 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1210}
1211
2a842aca 1212static void abort_endio(struct request *req, blk_status_t error)
bc5fc7e4 1213{
f4800d6d
CH		 1214 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1215 struct nvme_queue *nvmeq = iod->nvmeq;
e44ac588 1216
27fa9bc5
CH		 1217 dev_warn(nvmeq->dev->ctrl.device,
1218 "Abort status: 0x%x", nvme_req(req)->status);
e7a2a87d 1219 atomic_inc(&nvmeq->dev->ctrl.abort_limit);
e7a2a87d 1220 blk_mq_free_request(req);
bc5fc7e4
MW		 1221}
1222
b2a0eb1a
KB		 1223static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1224{
1225
1226 /* If true, indicates loss of adapter communication, possibly by a
1227 * NVMe Subsystem reset.
1228 */
1229 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1230
ad70062c
JW		 1231 /* If there is a reset/reinit ongoing, we shouldn't reset again. */
1232 switch (dev->ctrl.state) {
1233 case NVME_CTRL_RESETTING:
ad6a0a52 1234 case NVME_CTRL_CONNECTING:
b2a0eb1a 1235 return false;
ad70062c
JW		 1236 default:
1237 break;
1238 }
b2a0eb1a
KB		 1239
1240 /* We shouldn't reset unless the controller is on fatal error state
1241 * _or_ if we lost the communication with it.
1242 */
1243 if (!(csts & NVME_CSTS_CFS) && !nssro)
1244 return false;
1245
b2a0eb1a
KB		 1246 return true;
1247}
1248
1249static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1250{
1251 /* Read a config register to help see what died. */
1252 u16 pci_status;
1253 int result;
1254
1255 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1256 &pci_status);
1257 if (result == PCIBIOS_SUCCESSFUL)
1258 dev_warn(dev->ctrl.device,
1259 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1260 csts, pci_status);
1261 else
1262 dev_warn(dev->ctrl.device,
1263 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1264 csts, result);
1265}
1266
31c7c7d2 1267static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
c30341dc 1268{
f4800d6d
CH		 1269 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1270 struct nvme_queue *nvmeq = iod->nvmeq;
c30341dc 1271 struct nvme_dev *dev = nvmeq->dev;
a4aea562 1272 struct request *abort_req;
a4aea562 1273 struct nvme_command cmd;
b2a0eb1a
KB		 1274 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1275
651438bb
WX		 1276 /* If PCI error recovery process is happening, we cannot reset or
1277 * the recovery mechanism will surely fail.
1278 */
1279 mb();
1280 if (pci_channel_offline(to_pci_dev(dev->dev)))
1281 return BLK_EH_RESET_TIMER;
1282
b2a0eb1a
KB		 1283 /*
1284 * Reset immediately if the controller is failed
1285 */
1286 if (nvme_should_reset(dev, csts)) {
1287 nvme_warn_reset(dev, csts);
1288 nvme_dev_disable(dev, false);
d86c4d8e 1289 nvme_reset_ctrl(&dev->ctrl);
db8c48e4 1290 return BLK_EH_DONE;
b2a0eb1a 1291 }
c30341dc 1292
7776db1c
KB		 1293 /*
1294 * Did we miss an interrupt?
1295 */
0b2a8a9f 1296 if (nvme_poll_irqdisable(nvmeq, req->tag)) {
7776db1c
KB		 1297 dev_warn(dev->ctrl.device,
1298 "I/O %d QID %d timeout, completion polled\n",
1299 req->tag, nvmeq->qid);
db8c48e4 1300 return BLK_EH_DONE;
7776db1c
KB		 1301 }
1302
31c7c7d2 1303 /*
fd634f41
CH		 1304 * Shutdown immediately if controller times out while starting. The
1305 * reset work will see the pci device disabled when it gets the forced
1306 * cancellation error. All outstanding requests are completed on
db8c48e4 1307 * shutdown, so we return BLK_EH_DONE.
fd634f41 1308 */
4244140d
KB		 1309 switch (dev->ctrl.state) {
1310 case NVME_CTRL_CONNECTING:
1311 case NVME_CTRL_RESETTING:
b9cac43c 1312 dev_warn_ratelimited(dev->ctrl.device,
fd634f41
CH		 1313 "I/O %d QID %d timeout, disable controller\n",
1314 req->tag, nvmeq->qid);
a5cdb68c 1315 nvme_dev_disable(dev, false);
27fa9bc5 1316 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
db8c48e4 1317 return BLK_EH_DONE;
4244140d
KB		 1318 default:
1319 break;
c30341dc
KB		 1320 }
1321
fd634f41
CH		 1322 /*
1323 * Shutdown the controller immediately and schedule a reset if the
1324 * command was already aborted once before and still hasn't been
1325 * returned to the driver, or if this is the admin queue.
31c7c7d2 1326 */
f4800d6d 1327 if (!nvmeq->qid || iod->aborted) {
1b3c47c1 1328 dev_warn(dev->ctrl.device,
e1569a16
KB		 1329 "I/O %d QID %d timeout, reset controller\n",
1330 req->tag, nvmeq->qid);
a5cdb68c 1331 nvme_dev_disable(dev, false);
d86c4d8e 1332 nvme_reset_ctrl(&dev->ctrl);
c30341dc 1333
27fa9bc5 1334 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
db8c48e4 1335 return BLK_EH_DONE;
c30341dc 1336 }
c30341dc 1337
e7a2a87d 1338 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
6bf25d16 1339 atomic_inc(&dev->ctrl.abort_limit);
31c7c7d2 1340 return BLK_EH_RESET_TIMER;
6bf25d16 1341 }
7bf7d778 1342 iod->aborted = 1;
a4aea562 1343
c30341dc
KB		 1344 memset(&cmd, 0, sizeof(cmd));
1345 cmd.abort.opcode = nvme_admin_abort_cmd;
a4aea562 1346 cmd.abort.cid = req->tag;
c30341dc 1347 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
c30341dc 1348
1b3c47c1
SG		 1349 dev_warn(nvmeq->dev->ctrl.device,
1350 "I/O %d QID %d timeout, aborting\n",
1351 req->tag, nvmeq->qid);
e7a2a87d
CH		 1352
1353 abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
eb71f435 1354 BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
e7a2a87d
CH		 1355 if (IS_ERR(abort_req)) {
1356 atomic_inc(&dev->ctrl.abort_limit);
1357 return BLK_EH_RESET_TIMER;
1358 }
1359
1360 abort_req->timeout = ADMIN_TIMEOUT;
1361 abort_req->end_io_data = NULL;
1362 blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio);
c30341dc 1363
31c7c7d2
CH		 1364 /*
1365 * The aborted req will be completed on receiving the abort req.
1366 * We enable the timer again. If hit twice, it'll cause a device reset,
1367 * as the device then is in a faulty state.
1368 */
1369 return BLK_EH_RESET_TIMER;
c30341dc
KB		 1370}
1371
a4aea562
MB		 1372static void nvme_free_queue(struct nvme_queue *nvmeq)
1373{
9e866774
MW		 1374 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1375 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
63223078
CH		 1376 if (!nvmeq->sq_cmds)
1377 return;
0f238ff5 1378
63223078
CH		 1379 if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) {
1380 pci_free_p2pmem(to_pci_dev(nvmeq->q_dmadev),
1381 nvmeq->sq_cmds, SQ_SIZE(nvmeq->q_depth));
1382 } else {
1383 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
1384 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
0f238ff5 1385 }
9e866774
MW		 1386}
1387
a1a5ef99 1388static void nvme_free_queues(struct nvme_dev *dev, int lowest)
22404274
KB		 1389{
1390 int i;
1391
d858e5f0 1392 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
d858e5f0 1393 dev->ctrl.queue_count--;
147b27e4 1394 nvme_free_queue(&dev->queues[i]);
121c7ad4 1395 }
22404274
KB		 1396}
1397
4d115420
KB		 1398/**
1399 * nvme_suspend_queue - put queue into suspended state
40581d1a 1400 * @nvmeq: queue to suspend
4d115420
KB		 1401 */
1402static int nvme_suspend_queue(struct nvme_queue *nvmeq)
b60503ba 1403{
4e224106 1404 if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags))
2b25d981 1405 return 1;
a09115b2 1406
4e224106 1407 /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */
d1f06f4a 1408 mb();
a09115b2 1409
4e224106 1410 nvmeq->dev->online_queues--;
1c63dc66 1411 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
c81545f9 1412 blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q);
4e224106
CH		 1413 if (nvmeq->cq_vector == -1)
1414 return 0;
1415 pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq);
1416 nvmeq->cq_vector = -1;
4d115420
KB		 1417 return 0;
1418}
b60503ba 1419
8fae268b
KB		 1420static void nvme_suspend_io_queues(struct nvme_dev *dev)
1421{
1422 int i;
1423
1424 for (i = dev->ctrl.queue_count - 1; i > 0; i--)
1425 nvme_suspend_queue(&dev->queues[i]);
1426}
1427
a5cdb68c 1428static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
4d115420 1429{
147b27e4 1430 struct nvme_queue *nvmeq = &dev->queues[0];
4d115420 1431
a5cdb68c
KB		 1432 if (shutdown)
1433 nvme_shutdown_ctrl(&dev->ctrl);
1434 else
20d0dfe6 1435 nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap);
07836e65 1436
0b2a8a9f 1437 nvme_poll_irqdisable(nvmeq, -1);
b60503ba
MW		 1438}
1439
8ffaadf7
JD		 1440static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1441 int entry_size)
1442{
1443 int q_depth = dev->q_depth;
5fd4ce1b
CH		 1444 unsigned q_size_aligned = roundup(q_depth * entry_size,
1445 dev->ctrl.page_size);
8ffaadf7
JD		 1446
1447 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
c45f5c99 1448 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
5fd4ce1b 1449 mem_per_q = round_down(mem_per_q, dev->ctrl.page_size);
c45f5c99 1450 q_depth = div_u64(mem_per_q, entry_size);
8ffaadf7
JD		 1451
1452 /*
1453 * Ensure the reduced q_depth is above some threshold where it
1454 * would be better to map queues in system memory with the
1455 * original depth
1456 */
1457 if (q_depth < 64)
1458 return -ENOMEM;
1459 }
1460
1461 return q_depth;
1462}
1463
1464static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1465 int qid, int depth)
1466{
0f238ff5
LG		 1467 struct pci_dev *pdev = to_pci_dev(dev->dev);
1468
1469 if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
1470 nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(depth));
1471 nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev,
1472 nvmeq->sq_cmds);
63223078
CH		 1473 if (nvmeq->sq_dma_addr) {
1474 set_bit(NVMEQ_SQ_CMB, &nvmeq->flags);
1475 return 0;
1476 }
0f238ff5 1477 }
8ffaadf7 1478
63223078
CH		 1479 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
1480 &nvmeq->sq_dma_addr, GFP_KERNEL);
815c6704
KB		 1481 if (!nvmeq->sq_cmds)
1482 return -ENOMEM;
8ffaadf7
JD		 1483 return 0;
1484}
1485
a6ff7262 1486static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
b60503ba 1487{
147b27e4 1488 struct nvme_queue *nvmeq = &dev->queues[qid];
b60503ba 1489
62314e40
KB		 1490 if (dev->ctrl.queue_count > qid)
1491 return 0;
b60503ba 1492
750afb08
LC		 1493 nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(depth),
1494 &nvmeq->cq_dma_addr, GFP_KERNEL);
b60503ba
MW		 1495 if (!nvmeq->cqes)
1496 goto free_nvmeq;
b60503ba 1497
8ffaadf7 1498 if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth))
b60503ba
MW		 1499 goto free_cqdma;
1500
e75ec752 1501 nvmeq->q_dmadev = dev->dev;
091b6092 1502 nvmeq->dev = dev;
1ab0cd69 1503 spin_lock_init(&nvmeq->sq_lock);
3a7afd8e 1504 spin_lock_init(&nvmeq->cq_poll_lock);
b60503ba 1505 nvmeq->cq_head = 0;
82123460 1506 nvmeq->cq_phase = 1;
b80d5ccc 1507 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
b60503ba 1508 nvmeq->q_depth = depth;
c30341dc 1509 nvmeq->qid = qid;
758dd7fd 1510 nvmeq->cq_vector = -1;
d858e5f0 1511 dev->ctrl.queue_count++;
36a7e993 1512
147b27e4 1513 return 0;
b60503ba
MW		 1514
1515 free_cqdma:
e75ec752 1516 dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes,
b60503ba
MW		 1517 nvmeq->cq_dma_addr);
1518 free_nvmeq:
147b27e4 1519 return -ENOMEM;
b60503ba
MW		 1520}
1521
dca51e78 1522static int queue_request_irq(struct nvme_queue *nvmeq)
3001082c 1523{
0ff199cb
CH		 1524 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1525 int nr = nvmeq->dev->ctrl.instance;
1526
1527 if (use_threaded_interrupts) {
1528 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1529 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1530 } else {
1531 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1532 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1533 }
3001082c
MW		 1534}
1535
22404274 1536static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
b60503ba 1537{
22404274 1538 struct nvme_dev *dev = nvmeq->dev;
b60503ba 1539
22404274 1540 nvmeq->sq_tail = 0;
04f3eafd 1541 nvmeq->last_sq_tail = 0;
22404274
KB		 1542 nvmeq->cq_head = 0;
1543 nvmeq->cq_phase = 1;
b80d5ccc 1544 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
22404274 1545 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
f9f38e33 1546 nvme_dbbuf_init(dev, nvmeq, qid);
42f61420 1547 dev->online_queues++;
3a7afd8e 1548 wmb(); /* ensure the first interrupt sees the initialization */
22404274
KB		 1549}
1550
4b04cc6a 1551static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled)
22404274
KB		 1552{
1553 struct nvme_dev *dev = nvmeq->dev;
1554 int result;
a8e3e0bb 1555 s16 vector;
3f85d50b 1556
d1ed6aa1
CH		 1557 clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
1558
22b55601
KB		 1559 /*
1560 * A queue's vector matches the queue identifier unless the controller
1561 * has only one vector available.
1562 */
4b04cc6a
JA		 1563 if (!polled)
1564 vector = dev->num_vecs == 1 ? 0 : qid;
1565 else
1566 vector = -1;
1567
a8e3e0bb 1568 result = adapter_alloc_cq(dev, qid, nvmeq, vector);
ded45505
KB		 1569 if (result)
1570 return result;
b60503ba
MW		 1571
1572 result = adapter_alloc_sq(dev, qid, nvmeq);
1573 if (result < 0)
ded45505
KB		 1574 return result;
1575 else if (result)
b60503ba
MW		 1576 goto release_cq;
1577
a8e3e0bb 1578 nvmeq->cq_vector = vector;
161b8be2 1579 nvme_init_queue(nvmeq, qid);
4b04cc6a
JA		 1580
1581 if (vector != -1) {
1582 result = queue_request_irq(nvmeq);
1583 if (result < 0)
1584 goto release_sq;
1585 }
b60503ba 1586
4e224106 1587 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
22404274 1588 return result;
b60503ba 1589
a8e3e0bb
JW		 1590release_sq:
1591 nvmeq->cq_vector = -1;
f25a2dfc 1592 dev->online_queues--;
b60503ba 1593 adapter_delete_sq(dev, qid);
a8e3e0bb 1594release_cq:
b60503ba 1595 adapter_delete_cq(dev, qid);
22404274 1596 return result;
b60503ba
MW		 1597}
1598
f363b089 1599static const struct blk_mq_ops nvme_mq_admin_ops = {
d29ec824 1600 .queue_rq = nvme_queue_rq,
77f02a7a 1601 .complete = nvme_pci_complete_rq,
a4aea562 1602 .init_hctx = nvme_admin_init_hctx,
4af0e21c 1603 .exit_hctx = nvme_admin_exit_hctx,
0350815a 1604 .init_request = nvme_init_request,
a4aea562
MB		 1605 .timeout = nvme_timeout,
1606};
1607
f363b089 1608static const struct blk_mq_ops nvme_mq_ops = {
376f7ef8
CH		 1609 .queue_rq = nvme_queue_rq,
1610 .complete = nvme_pci_complete_rq,
1611 .commit_rqs = nvme_commit_rqs,
1612 .init_hctx = nvme_init_hctx,
1613 .init_request = nvme_init_request,
1614 .map_queues = nvme_pci_map_queues,
1615 .timeout = nvme_timeout,
1616 .poll = nvme_poll,
dabcefab
JA		 1617};
1618
ea191d2f
KB		 1619static void nvme_dev_remove_admin(struct nvme_dev *dev)
1620{
1c63dc66 1621 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
69d9a99c
KB		 1622 /*
1623 * If the controller was reset during removal, it's possible
1624 * user requests may be waiting on a stopped queue. Start the
1625 * queue to flush these to completion.
1626 */
c81545f9 1627 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1c63dc66 1628 blk_cleanup_queue(dev->ctrl.admin_q);
ea191d2f
KB		 1629 blk_mq_free_tag_set(&dev->admin_tagset);
1630 }
1631}
1632
a4aea562
MB		 1633static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1634{
1c63dc66 1635 if (!dev->ctrl.admin_q) {
a4aea562
MB		 1636 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1637 dev->admin_tagset.nr_hw_queues = 1;
e3e9d50c 1638
38dabe21 1639 dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH;
a4aea562 1640 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
e75ec752 1641 dev->admin_tagset.numa_node = dev_to_node(dev->dev);
a7a7cbe3 1642 dev->admin_tagset.cmd_size = nvme_pci_cmd_size(dev, false);
d3484991 1643 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED;
a4aea562
MB		 1644 dev->admin_tagset.driver_data = dev;
1645
1646 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1647 return -ENOMEM;
34b6c231 1648 dev->ctrl.admin_tagset = &dev->admin_tagset;
a4aea562 1649
1c63dc66
CH		 1650 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1651 if (IS_ERR(dev->ctrl.admin_q)) {
a4aea562
MB		 1652 blk_mq_free_tag_set(&dev->admin_tagset);
1653 return -ENOMEM;
1654 }
1c63dc66 1655 if (!blk_get_queue(dev->ctrl.admin_q)) {
ea191d2f 1656 nvme_dev_remove_admin(dev);
1c63dc66 1657 dev->ctrl.admin_q = NULL;
ea191d2f
KB		 1658 return -ENODEV;
1659 }
0fb59cbc 1660 } else
c81545f9 1661 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
a4aea562
MB		 1662
1663 return 0;
1664}
1665
97f6ef64
XY		 1666static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1667{
1668 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1669}
1670
1671static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1672{
1673 struct pci_dev *pdev = to_pci_dev(dev->dev);
1674
1675 if (size <= dev->bar_mapped_size)
1676 return 0;
1677 if (size > pci_resource_len(pdev, 0))
1678 return -ENOMEM;
1679 if (dev->bar)
1680 iounmap(dev->bar);
1681 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1682 if (!dev->bar) {
1683 dev->bar_mapped_size = 0;
1684 return -ENOMEM;
1685 }
1686 dev->bar_mapped_size = size;
1687 dev->dbs = dev->bar + NVME_REG_DBS;
1688
1689 return 0;
1690}
1691
01ad0990 1692static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
b60503ba 1693{
ba47e386 1694 int result;
b60503ba
MW		 1695 u32 aqa;
1696 struct nvme_queue *nvmeq;
1697
97f6ef64
XY		 1698 result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1699 if (result < 0)
1700 return result;
1701
8ef2074d 1702 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
20d0dfe6 1703 NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
dfbac8c7 1704
7a67cbea
CH		 1705 if (dev->subsystem &&
1706 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1707 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
dfbac8c7 1708
20d0dfe6 1709 result = nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap);
ba47e386
MW		 1710 if (result < 0)
1711 return result;
b60503ba 1712
a6ff7262 1713 result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
147b27e4
SG		 1714 if (result)
1715 return result;
b60503ba 1716
147b27e4 1717 nvmeq = &dev->queues[0];
b60503ba
MW		 1718 aqa = nvmeq->q_depth - 1;
1719 aqa |= aqa << 16;
1720
7a67cbea
CH		 1721 writel(aqa, dev->bar + NVME_REG_AQA);
1722 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1723 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
b60503ba 1724
20d0dfe6 1725 result = nvme_enable_ctrl(&dev->ctrl, dev->ctrl.cap);
025c557a 1726 if (result)
d4875622 1727 return result;
a4aea562 1728
2b25d981 1729 nvmeq->cq_vector = 0;
161b8be2 1730 nvme_init_queue(nvmeq, 0);
dca51e78 1731 result = queue_request_irq(nvmeq);
758dd7fd
JD		 1732 if (result) {
1733 nvmeq->cq_vector = -1;
d4875622 1734 return result;
758dd7fd 1735 }
025c557a 1736
4e224106 1737 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
b60503ba
MW		 1738 return result;
1739}
1740
749941f2 1741static int nvme_create_io_queues(struct nvme_dev *dev)
42f61420 1742{
4b04cc6a 1743 unsigned i, max, rw_queues;
749941f2 1744 int ret = 0;
42f61420 1745
d858e5f0 1746 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
a6ff7262 1747 if (nvme_alloc_queue(dev, i, dev->q_depth)) {
749941f2 1748 ret = -ENOMEM;
42f61420 1749 break;
749941f2
CH		 1750 }
1751 }
42f61420 1752
d858e5f0 1753 max = min(dev->max_qid, dev->ctrl.queue_count - 1);
e20ba6e1
CH		 1754 if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) {
1755 rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] +
1756 dev->io_queues[HCTX_TYPE_READ];
4b04cc6a
JA		 1757 } else {
1758 rw_queues = max;
1759 }
1760
949928c1 1761 for (i = dev->online_queues; i <= max; i++) {
4b04cc6a
JA		 1762 bool polled = i > rw_queues;
1763
1764 ret = nvme_create_queue(&dev->queues[i], i, polled);
d4875622 1765 if (ret)
42f61420 1766 break;
27e8166c 1767 }
749941f2
CH		 1768
1769 /*
1770 * Ignore failing Create SQ/CQ commands, we can continue with less
8adb8c14
MI		 1771 * than the desired amount of queues, and even a controller without
1772 * I/O queues can still be used to issue admin commands. This might
749941f2
CH		 1773 * be useful to upgrade a buggy firmware for example.
1774 */
1775 return ret >= 0 ? 0 : ret;
b60503ba
MW		 1776}
1777
202021c1
SB		 1778static ssize_t nvme_cmb_show(struct device *dev,
1779 struct device_attribute *attr,
1780 char *buf)
1781{
1782 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
1783
c965809c 1784 return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n",
202021c1
SB		 1785 ndev->cmbloc, ndev->cmbsz);
1786}
1787static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL);
1788
88de4598 1789static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
8ffaadf7 1790{
88de4598
CH		 1791 u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
1792
1793 return 1ULL << (12 + 4 * szu);
1794}
1795
1796static u32 nvme_cmb_size(struct nvme_dev *dev)
1797{
1798 return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
1799}
1800
f65efd6d 1801static void nvme_map_cmb(struct nvme_dev *dev)
8ffaadf7 1802{
88de4598 1803 u64 size, offset;
8ffaadf7
JD		 1804 resource_size_t bar_size;
1805 struct pci_dev *pdev = to_pci_dev(dev->dev);
8969f1f8 1806 int bar;
8ffaadf7 1807
9fe5c59f
KB		 1808 if (dev->cmb_size)
1809 return;
1810
7a67cbea 1811 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
f65efd6d
CH		 1812 if (!dev->cmbsz)
1813 return;
202021c1 1814 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
8ffaadf7 1815
88de4598
CH		 1816 size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
1817 offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
8969f1f8
CH		 1818 bar = NVME_CMB_BIR(dev->cmbloc);
1819 bar_size = pci_resource_len(pdev, bar);
8ffaadf7
JD		 1820
1821 if (offset > bar_size)
f65efd6d 1822 return;
8ffaadf7
JD		 1823
1824 /*
1825 * Controllers may support a CMB size larger than their BAR,
1826 * for example, due to being behind a bridge. Reduce the CMB to
1827 * the reported size of the BAR
1828 */
1829 if (size > bar_size - offset)
1830 size = bar_size - offset;
1831
0f238ff5
LG		 1832 if (pci_p2pdma_add_resource(pdev, bar, size, offset)) {
1833 dev_warn(dev->ctrl.device,
1834 "failed to register the CMB\n");
f65efd6d 1835 return;
0f238ff5
LG		 1836 }
1837
8ffaadf7 1838 dev->cmb_size = size;
0f238ff5
LG		 1839 dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS);
1840
1841 if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) ==
1842 (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS))
1843 pci_p2pmem_publish(pdev, true);
f65efd6d
CH		 1844
1845 if (sysfs_add_file_to_group(&dev->ctrl.device->kobj,
1846 &dev_attr_cmb.attr, NULL))
1847 dev_warn(dev->ctrl.device,
1848 "failed to add sysfs attribute for CMB\n");
8ffaadf7
JD		 1849}
1850
1851static inline void nvme_release_cmb(struct nvme_dev *dev)
1852{
0f238ff5 1853 if (dev->cmb_size) {
1c78f773
MG		 1854 sysfs_remove_file_from_group(&dev->ctrl.device->kobj,
1855 &dev_attr_cmb.attr, NULL);
0f238ff5 1856 dev->cmb_size = 0;
8ffaadf7
JD		 1857 }
1858}
1859
87ad72a5
CH		 1860static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1861{
4033f35d 1862 u64 dma_addr = dev->host_mem_descs_dma;
87ad72a5 1863 struct nvme_command c;
87ad72a5
CH		 1864 int ret;
1865
87ad72a5
CH		 1866 memset(&c, 0, sizeof(c));
1867 c.features.opcode = nvme_admin_set_features;
1868 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1869 c.features.dword11 = cpu_to_le32(bits);
1870 c.features.dword12 = cpu_to_le32(dev->host_mem_size >>
1871 ilog2(dev->ctrl.page_size));
1872 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr));
1873 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr));
1874 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs);
1875
1876 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1877 if (ret) {
1878 dev_warn(dev->ctrl.device,
1879 "failed to set host mem (err %d, flags %#x).\n",
1880 ret, bits);
1881 }
87ad72a5
CH		 1882 return ret;
1883}
1884
1885static void nvme_free_host_mem(struct nvme_dev *dev)
1886{
1887 int i;
1888
1889 for (i = 0; i < dev->nr_host_mem_descs; i++) {
1890 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
1891 size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size;
1892
cc667f6d
LD		 1893 dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i],
1894 le64_to_cpu(desc->addr),
1895 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
87ad72a5
CH		 1896 }
1897
1898 kfree(dev->host_mem_desc_bufs);
1899 dev->host_mem_desc_bufs = NULL;
4033f35d
CH		 1900 dma_free_coherent(dev->dev,
1901 dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
1902 dev->host_mem_descs, dev->host_mem_descs_dma);
87ad72a5 1903 dev->host_mem_descs = NULL;
7e5dd57e 1904 dev->nr_host_mem_descs = 0;
87ad72a5
CH		 1905}
1906
92dc6895
CH		 1907static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
1908 u32 chunk_size)
9d713c2b 1909{
87ad72a5 1910 struct nvme_host_mem_buf_desc *descs;
92dc6895 1911 u32 max_entries, len;
4033f35d 1912 dma_addr_t descs_dma;
2ee0e4ed 1913 int i = 0;
87ad72a5 1914 void **bufs;
6fbcde66 1915 u64 size, tmp;
87ad72a5 1916
87ad72a5
CH		 1917 tmp = (preferred + chunk_size - 1);
1918 do_div(tmp, chunk_size);
1919 max_entries = tmp;
044a9df1
CH		 1920
1921 if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
1922 max_entries = dev->ctrl.hmmaxd;
1923
750afb08
LC		 1924 descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs),
1925 &descs_dma, GFP_KERNEL);
87ad72a5
CH		 1926 if (!descs)
1927 goto out;
1928
1929 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
1930 if (!bufs)
1931 goto out_free_descs;
1932
244a8fe4 1933 for (size = 0; size < preferred && i < max_entries; size += len) {
87ad72a5
CH		 1934 dma_addr_t dma_addr;
1935
50cdb7c6 1936 len = min_t(u64, chunk_size, preferred - size);
87ad72a5
CH		 1937 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
1938 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1939 if (!bufs[i])
1940 break;
1941
1942 descs[i].addr = cpu_to_le64(dma_addr);
1943 descs[i].size = cpu_to_le32(len / dev->ctrl.page_size);
1944 i++;
1945 }
1946
92dc6895 1947 if (!size)
87ad72a5 1948 goto out_free_bufs;
87ad72a5 1949
87ad72a5
CH		 1950 dev->nr_host_mem_descs = i;
1951 dev->host_mem_size = size;
1952 dev->host_mem_descs = descs;
4033f35d 1953 dev->host_mem_descs_dma = descs_dma;
87ad72a5
CH		 1954 dev->host_mem_desc_bufs = bufs;
1955 return 0;
1956
1957out_free_bufs:
1958 while (--i >= 0) {
1959 size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size;
1960
cc667f6d
LD		 1961 dma_free_attrs(dev->dev, size, bufs[i],
1962 le64_to_cpu(descs[i].addr),
1963 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
87ad72a5
CH		 1964 }
1965
1966 kfree(bufs);
1967out_free_descs:
4033f35d
CH		 1968 dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
1969 descs_dma);
87ad72a5 1970out:
87ad72a5
CH		 1971 dev->host_mem_descs = NULL;
1972 return -ENOMEM;
1973}
1974
92dc6895
CH		 1975static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
1976{
1977 u32 chunk_size;
1978
1979 /* start big and work our way down */
30f92d62 1980 for (chunk_size = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
044a9df1 1981 chunk_size >= max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
92dc6895
CH		 1982 chunk_size /= 2) {
1983 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
1984 if (!min || dev->host_mem_size >= min)
1985 return 0;
1986 nvme_free_host_mem(dev);
1987 }
1988 }
1989
1990 return -ENOMEM;
1991}
1992
9620cfba 1993static int nvme_setup_host_mem(struct nvme_dev *dev)
87ad72a5
CH		 1994{
1995 u64 max = (u64)max_host_mem_size_mb * SZ_1M;
1996 u64 preferred = (u64)dev->ctrl.hmpre * 4096;
1997 u64 min = (u64)dev->ctrl.hmmin * 4096;
1998 u32 enable_bits = NVME_HOST_MEM_ENABLE;
6fbcde66 1999 int ret;
87ad72a5
CH		 2000
2001 preferred = min(preferred, max);
2002 if (min > max) {
2003 dev_warn(dev->ctrl.device,
2004 "min host memory (%lld MiB) above limit (%d MiB).\n",
2005 min >> ilog2(SZ_1M), max_host_mem_size_mb);
2006 nvme_free_host_mem(dev);
9620cfba 2007 return 0;
87ad72a5
CH		 2008 }
2009
2010 /*
2011 * If we already have a buffer allocated check if we can reuse it.
2012 */
2013 if (dev->host_mem_descs) {
2014 if (dev->host_mem_size >= min)
2015 enable_bits |= NVME_HOST_MEM_RETURN;
2016 else
2017 nvme_free_host_mem(dev);
2018 }
2019
2020 if (!dev->host_mem_descs) {
92dc6895
CH		 2021 if (nvme_alloc_host_mem(dev, min, preferred)) {
2022 dev_warn(dev->ctrl.device,
2023 "failed to allocate host memory buffer.\n");
9620cfba 2024 return 0; /* controller must work without HMB */
92dc6895
CH		 2025 }
2026
2027 dev_info(dev->ctrl.device,
2028 "allocated %lld MiB host memory buffer.\n",
2029 dev->host_mem_size >> ilog2(SZ_1M));
87ad72a5
CH		 2030 }
2031
9620cfba
CH		 2032 ret = nvme_set_host_mem(dev, enable_bits);
2033 if (ret)
87ad72a5 2034 nvme_free_host_mem(dev);
9620cfba 2035 return ret;
9d713c2b
KB		 2036}
2037
612b7286
ML		 2038/*
2039 * nirqs is the number of interrupts available for write and read
2040 * queues. The core already reserved an interrupt for the admin queue.
2041 */
2042static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs)
3b6592f7 2043{
612b7286
ML		 2044 struct nvme_dev *dev = affd->priv;
2045 unsigned int nr_read_queues;
3b6592f7
JA		 2046
2047 /*
612b7286
ML		 2048 * If there is no interupt available for queues, ensure that
2049 * the default queue is set to 1. The affinity set size is
2050 * also set to one, but the irq core ignores it for this case.
2051 *
2052 * If only one interrupt is available or 'write_queue' == 0, combine
2053 * write and read queues.
2054 *
2055 * If 'write_queues' > 0, ensure it leaves room for at least one read
2056 * queue.
3b6592f7 2057 */
612b7286
ML		 2058 if (!nrirqs) {
2059 nrirqs = 1;
2060 nr_read_queues = 0;
2061 } else if (nrirqs == 1 || !write_queues) {
2062 nr_read_queues = 0;
2063 } else if (write_queues >= nrirqs) {
2064 nr_read_queues = 1;
3b6592f7 2065 } else {
612b7286 2066 nr_read_queues = nrirqs - write_queues;
3b6592f7 2067 }
612b7286
ML		 2068
2069 dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2070 affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2071 dev->io_queues[HCTX_TYPE_READ] = nr_read_queues;
2072 affd->set_size[HCTX_TYPE_READ] = nr_read_queues;
2073 affd->nr_sets = nr_read_queues ? 2 : 1;
3b6592f7
JA		 2074}
2075
6451fe73 2076static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues)
3b6592f7
JA		 2077{
2078 struct pci_dev *pdev = to_pci_dev(dev->dev);
3b6592f7 2079 struct irq_affinity affd = {
9cfef55b 2080 .pre_vectors = 1,
612b7286
ML		 2081 .calc_sets = nvme_calc_irq_sets,
2082 .priv = dev,
3b6592f7 2083 };
6451fe73
JA		 2084 unsigned int irq_queues, this_p_queues;
2085
2086 /*
2087 * Poll queues don't need interrupts, but we need at least one IO
2088 * queue left over for non-polled IO.
2089 */
2090 this_p_queues = poll_queues;
2091 if (this_p_queues >= nr_io_queues) {
2092 this_p_queues = nr_io_queues - 1;
2093 irq_queues = 1;
2094 } else {
c45b1fa2 2095 irq_queues = nr_io_queues - this_p_queues + 1;
6451fe73
JA		 2096 }
2097 dev->io_queues[HCTX_TYPE_POLL] = this_p_queues;
3b6592f7 2098
612b7286
ML		 2099 /* Initialize for the single interrupt case */
2100 dev->io_queues[HCTX_TYPE_DEFAULT] = 1;
2101 dev->io_queues[HCTX_TYPE_READ] = 0;
3b6592f7 2102
612b7286
ML		 2103 return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues,
2104 PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd);
3b6592f7
JA		 2105}
2106
8fae268b
KB		 2107static void nvme_disable_io_queues(struct nvme_dev *dev)
2108{
2109 if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq))
2110 __nvme_disable_io_queues(dev, nvme_admin_delete_cq);
2111}
2112
8d85fce7 2113static int nvme_setup_io_queues(struct nvme_dev *dev)
b60503ba 2114{
147b27e4 2115 struct nvme_queue *adminq = &dev->queues[0];
e75ec752 2116 struct pci_dev *pdev = to_pci_dev(dev->dev);
97f6ef64
XY		 2117 int result, nr_io_queues;
2118 unsigned long size;
b60503ba 2119
3b6592f7 2120 nr_io_queues = max_io_queues();
9a0be7ab
CH		 2121 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
2122 if (result < 0)
1b23484b 2123 return result;
9a0be7ab 2124
f5fa90dc 2125 if (nr_io_queues == 0)
a5229050 2126 return 0;
4e224106
CH		 2127
2128 clear_bit(NVMEQ_ENABLED, &adminq->flags);
b60503ba 2129
0f238ff5 2130 if (dev->cmb_use_sqes) {
8ffaadf7
JD		 2131 result = nvme_cmb_qdepth(dev, nr_io_queues,
2132 sizeof(struct nvme_command));
2133 if (result > 0)
2134 dev->q_depth = result;
2135 else
0f238ff5 2136 dev->cmb_use_sqes = false;
8ffaadf7
JD		 2137 }
2138
97f6ef64
XY		 2139 do {
2140 size = db_bar_size(dev, nr_io_queues);
2141 result = nvme_remap_bar(dev, size);
2142 if (!result)
2143 break;
2144 if (!--nr_io_queues)
2145 return -ENOMEM;
2146 } while (1);
2147 adminq->q_db = dev->dbs;
f1938f6e 2148
8fae268b 2149 retry:
9d713c2b 2150 /* Deregister the admin queue's interrupt */
0ff199cb 2151 pci_free_irq(pdev, 0, adminq);
9d713c2b 2152
e32efbfc
JA		 2153 /*
2154 * If we enable msix early due to not intx, disable it again before
2155 * setting up the full range we need.
2156 */
dca51e78 2157 pci_free_irq_vectors(pdev);
3b6592f7
JA		 2158
2159 result = nvme_setup_irqs(dev, nr_io_queues);
22b55601 2160 if (result <= 0)
dca51e78 2161 return -EIO;
3b6592f7 2162
22b55601 2163 dev->num_vecs = result;
4b04cc6a 2164 result = max(result - 1, 1);
e20ba6e1 2165 dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL];
fa08a396 2166
063a8096
MW		 2167 /*
2168 * Should investigate if there's a performance win from allocating
2169 * more queues than interrupt vectors; it might allow the submission
2170 * path to scale better, even if the receive path is limited by the
2171 * number of interrupts.
2172 */
dca51e78 2173 result = queue_request_irq(adminq);
758dd7fd
JD		 2174 if (result) {
2175 adminq->cq_vector = -1;
d4875622 2176 return result;
758dd7fd 2177 }
4e224106 2178 set_bit(NVMEQ_ENABLED, &adminq->flags);
8fae268b
KB		 2179
2180 result = nvme_create_io_queues(dev);
2181 if (result || dev->online_queues < 2)
2182 return result;
2183
2184 if (dev->online_queues - 1 < dev->max_qid) {
2185 nr_io_queues = dev->online_queues - 1;
2186 nvme_disable_io_queues(dev);
2187 nvme_suspend_io_queues(dev);
2188 goto retry;
2189 }
2190 dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n",
2191 dev->io_queues[HCTX_TYPE_DEFAULT],
2192 dev->io_queues[HCTX_TYPE_READ],
2193 dev->io_queues[HCTX_TYPE_POLL]);
2194 return 0;
b60503ba
MW		 2195}
2196
2a842aca 2197static void nvme_del_queue_end(struct request *req, blk_status_t error)
a5768aa8 2198{
db3cbfff 2199 struct nvme_queue *nvmeq = req->end_io_data;
b5875222 2200
db3cbfff 2201 blk_mq_free_request(req);
d1ed6aa1 2202 complete(&nvmeq->delete_done);
a5768aa8
KB		 2203}
2204
2a842aca 2205static void nvme_del_cq_end(struct request *req, blk_status_t error)
a5768aa8 2206{
db3cbfff 2207 struct nvme_queue *nvmeq = req->end_io_data;
a5768aa8 2208
d1ed6aa1
CH		 2209 if (error)
2210 set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
db3cbfff
KB		 2211
2212 nvme_del_queue_end(req, error);
a5768aa8
KB		 2213}
2214
db3cbfff 2215static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
bda4e0fb 2216{
db3cbfff
KB		 2217 struct request_queue *q = nvmeq->dev->ctrl.admin_q;
2218 struct request *req;
2219 struct nvme_command cmd;
bda4e0fb 2220
db3cbfff
KB		 2221 memset(&cmd, 0, sizeof(cmd));
2222 cmd.delete_queue.opcode = opcode;
2223 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
bda4e0fb 2224
eb71f435 2225 req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
db3cbfff
KB		 2226 if (IS_ERR(req))
2227 return PTR_ERR(req);
bda4e0fb 2228
db3cbfff
KB		 2229 req->timeout = ADMIN_TIMEOUT;
2230 req->end_io_data = nvmeq;
2231
d1ed6aa1 2232 init_completion(&nvmeq->delete_done);
db3cbfff
KB		 2233 blk_execute_rq_nowait(q, NULL, req, false,
2234 opcode == nvme_admin_delete_cq ?
2235 nvme_del_cq_end : nvme_del_queue_end);
2236 return 0;
bda4e0fb
KB		 2237}
2238
8fae268b 2239static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode)
a5768aa8 2240{
5271edd4 2241 int nr_queues = dev->online_queues - 1, sent = 0;
db3cbfff 2242 unsigned long timeout;
a5768aa8 2243
db3cbfff 2244 retry:
5271edd4
CH		 2245 timeout = ADMIN_TIMEOUT;
2246 while (nr_queues > 0) {
2247 if (nvme_delete_queue(&dev->queues[nr_queues], opcode))
2248 break;
2249 nr_queues--;
2250 sent++;
db3cbfff 2251 }
d1ed6aa1
CH		 2252 while (sent) {
2253 struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent];
2254
2255 timeout = wait_for_completion_io_timeout(&nvmeq->delete_done,
5271edd4
CH		 2256 timeout);
2257 if (timeout == 0)
2258 return false;
d1ed6aa1
CH		 2259
2260 /* handle any remaining CQEs */
2261 if (opcode == nvme_admin_delete_cq &&
2262 !test_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags))
2263 nvme_poll_irqdisable(nvmeq, -1);
2264
2265 sent--;
5271edd4
CH		 2266 if (nr_queues)
2267 goto retry;
2268 }
2269 return true;
a5768aa8
KB		 2270}
2271
422ef0c7 2272/*
2b1b7e78 2273 * return error value only when tagset allocation failed
422ef0c7 2274 */
8d85fce7 2275static int nvme_dev_add(struct nvme_dev *dev)
b60503ba 2276{
2b1b7e78
JW		 2277 int ret;
2278
5bae7f73 2279 if (!dev->ctrl.tagset) {
376f7ef8 2280 dev->tagset.ops = &nvme_mq_ops;
ffe7704d 2281 dev->tagset.nr_hw_queues = dev->online_queues - 1;
ed92ad37
CH		 2282 dev->tagset.nr_maps = 2; /* default + read */
2283 if (dev->io_queues[HCTX_TYPE_POLL])
2284 dev->tagset.nr_maps++;
ffe7704d
KB		 2285 dev->tagset.timeout = NVME_IO_TIMEOUT;
2286 dev->tagset.numa_node = dev_to_node(dev->dev);
2287 dev->tagset.queue_depth =
a4aea562 2288 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
a7a7cbe3
CK		 2289 dev->tagset.cmd_size = nvme_pci_cmd_size(dev, false);
2290 if ((dev->ctrl.sgls & ((1 << 0) | (1 << 1))) && sgl_threshold) {
2291 dev->tagset.cmd_size = max(dev->tagset.cmd_size,
2292 nvme_pci_cmd_size(dev, true));
2293 }
ffe7704d
KB		 2294 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2295 dev->tagset.driver_data = dev;
b60503ba 2296
2b1b7e78
JW		 2297 ret = blk_mq_alloc_tag_set(&dev->tagset);
2298 if (ret) {
2299 dev_warn(dev->ctrl.device,
2300 "IO queues tagset allocation failed %d\n", ret);
2301 return ret;
2302 }
5bae7f73 2303 dev->ctrl.tagset = &dev->tagset;
f9f38e33
HK		 2304
2305 nvme_dbbuf_set(dev);
949928c1
KB		 2306 } else {
2307 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2308
2309 /* Free previously allocated queues that are no longer usable */
2310 nvme_free_queues(dev, dev->online_queues);
ffe7704d 2311 }
949928c1 2312
e1e5e564 2313 return 0;
b60503ba
MW		 2314}
2315
b00a726a 2316static int nvme_pci_enable(struct nvme_dev *dev)
0877cb0d 2317{
b00a726a 2318 int result = -ENOMEM;
e75ec752 2319 struct pci_dev *pdev = to_pci_dev(dev->dev);
0877cb0d
KB		 2320
2321 if (pci_enable_device_mem(pdev))
2322 return result;
2323
0877cb0d 2324 pci_set_master(pdev);
0877cb0d 2325
e75ec752
CH		 2326 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) &&
2327 dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32)))
052d0efa 2328 goto disable;
0877cb0d 2329
7a67cbea 2330 if (readl(dev->bar + NVME_REG_CSTS) == -1) {
0e53d180 2331 result = -ENODEV;
b00a726a 2332 goto disable;
0e53d180 2333 }
e32efbfc
JA		 2334
2335 /*
a5229050
KB		 2336 * Some devices and/or platforms don't advertise or work with INTx
2337 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2338 * adjust this later.
e32efbfc 2339 */
dca51e78
CH		 2340 result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
2341 if (result < 0)
2342 return result;
e32efbfc 2343
20d0dfe6 2344 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
7a67cbea 2345
20d0dfe6 2346 dev->q_depth = min_t(int, NVME_CAP_MQES(dev->ctrl.cap) + 1,
b27c1e68 2347 io_queue_depth);
20d0dfe6 2348 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
7a67cbea 2349 dev->dbs = dev->bar + 4096;
1f390c1f
SG		 2350
2351 /*
2352 * Temporary fix for the Apple controller found in the MacBook8,1 and
2353 * some MacBook7,1 to avoid controller resets and data loss.
2354 */
2355 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
2356 dev->q_depth = 2;
9bdcfb10
CH		 2357 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
2358 "set queue depth=%u to work around controller resets\n",
1f390c1f 2359 dev->q_depth);
d554b5e1
MP		 2360 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2361 (pdev->device == 0xa821 || pdev->device == 0xa822) &&
20d0dfe6 2362 NVME_CAP_MQES(dev->ctrl.cap) == 0) {
d554b5e1
MP		 2363 dev->q_depth = 64;
2364 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2365 "set queue depth=%u\n", dev->q_depth);
1f390c1f
SG		 2366 }
2367
f65efd6d 2368 nvme_map_cmb(dev);
202021c1 2369
a0a3408e
KB		 2370 pci_enable_pcie_error_reporting(pdev);
2371 pci_save_state(pdev);
0877cb0d
KB		 2372 return 0;
2373
2374 disable:
0877cb0d
KB		 2375 pci_disable_device(pdev);
2376 return result;
2377}
2378
2379static void nvme_dev_unmap(struct nvme_dev *dev)
b00a726a
KB		 2380{
2381 if (dev->bar)
2382 iounmap(dev->bar);
a1f447b3 2383 pci_release_mem_regions(to_pci_dev(dev->dev));
b00a726a
KB		 2384}
2385
2386static void nvme_pci_disable(struct nvme_dev *dev)
0877cb0d 2387{
e75ec752
CH		 2388 struct pci_dev *pdev = to_pci_dev(dev->dev);
2389
dca51e78 2390 pci_free_irq_vectors(pdev);
0877cb0d 2391
a0a3408e
KB		 2392 if (pci_is_enabled(pdev)) {
2393 pci_disable_pcie_error_reporting(pdev);
e75ec752 2394 pci_disable_device(pdev);
4d115420 2395 }
4d115420
KB		 2396}
2397
a5cdb68c 2398static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
b60503ba 2399{
302ad8cc
KB		 2400 bool dead = true;
2401 struct pci_dev *pdev = to_pci_dev(dev->dev);
22404274 2402
77bf25ea 2403 mutex_lock(&dev->shutdown_lock);
302ad8cc
KB		 2404 if (pci_is_enabled(pdev)) {
2405 u32 csts = readl(dev->bar + NVME_REG_CSTS);
2406
ebef7368
KB		 2407 if (dev->ctrl.state == NVME_CTRL_LIVE ||
2408 dev->ctrl.state == NVME_CTRL_RESETTING)
302ad8cc
KB		 2409 nvme_start_freeze(&dev->ctrl);
2410 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
2411 pdev->error_state != pci_channel_io_normal);
c9d3bf88 2412 }
c21377f8 2413
302ad8cc
KB		 2414 /*
2415 * Give the controller a chance to complete all entered requests if
2416 * doing a safe shutdown.
2417 */
87ad72a5
CH		 2418 if (!dead) {
2419 if (shutdown)
2420 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
9a915a5b
JW		 2421 }
2422
2423 nvme_stop_queues(&dev->ctrl);
87ad72a5 2424
64ee0ac0 2425 if (!dead && dev->ctrl.queue_count > 0) {
8fae268b 2426 nvme_disable_io_queues(dev);
a5cdb68c 2427 nvme_disable_admin_queue(dev, shutdown);
4d115420 2428 }
8fae268b
KB		 2429 nvme_suspend_io_queues(dev);
2430 nvme_suspend_queue(&dev->queues[0]);
b00a726a 2431 nvme_pci_disable(dev);
07836e65 2432
e1958e65
ML		 2433 blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
2434 blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
302ad8cc
KB		 2435
2436 /*
2437 * The driver will not be starting up queues again if shutting down so
2438 * must flush all entered requests to their failed completion to avoid
2439 * deadlocking blk-mq hot-cpu notifier.
2440 */
2441 if (shutdown)
2442 nvme_start_queues(&dev->ctrl);
77bf25ea 2443 mutex_unlock(&dev->shutdown_lock);
b60503ba
MW		 2444}
2445
091b6092
MW		 2446static int nvme_setup_prp_pools(struct nvme_dev *dev)
2447{
e75ec752 2448 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
091b6092
MW		 2449 PAGE_SIZE, PAGE_SIZE, 0);
2450 if (!dev->prp_page_pool)
2451 return -ENOMEM;
2452
99802a7a 2453 /* Optimisation for I/Os between 4k and 128k */
e75ec752 2454 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
99802a7a
MW		 2455 256, 256, 0);
2456 if (!dev->prp_small_pool) {
2457 dma_pool_destroy(dev->prp_page_pool);
2458 return -ENOMEM;
2459 }
091b6092
MW		 2460 return 0;
2461}
2462
2463static void nvme_release_prp_pools(struct nvme_dev *dev)
2464{
2465 dma_pool_destroy(dev->prp_page_pool);
99802a7a 2466 dma_pool_destroy(dev->prp_small_pool);
091b6092
MW		 2467}
2468
1673f1f0 2469static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
5e82e952 2470{
1673f1f0 2471 struct nvme_dev *dev = to_nvme_dev(ctrl);
9ac27090 2472
f9f38e33 2473 nvme_dbbuf_dma_free(dev);
e75ec752 2474 put_device(dev->dev);
4af0e21c
KB		 2475 if (dev->tagset.tags)
2476 blk_mq_free_tag_set(&dev->tagset);
1c63dc66
CH		 2477 if (dev->ctrl.admin_q)
2478 blk_put_queue(dev->ctrl.admin_q);
5e82e952 2479 kfree(dev->queues);
e286bcfc 2480 free_opal_dev(dev->ctrl.opal_dev);
943e942e 2481 mempool_destroy(dev->iod_mempool);
5e82e952
KB		 2482 kfree(dev);
2483}
2484
f58944e2
KB		 2485static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status)
2486{
237045fc 2487 dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status);
f58944e2 2488
d22524a4 2489 nvme_get_ctrl(&dev->ctrl);
69d9a99c 2490 nvme_dev_disable(dev, false);
9f9cafc1 2491 nvme_kill_queues(&dev->ctrl);
03e0f3a6 2492 if (!queue_work(nvme_wq, &dev->remove_work))
f58944e2
KB		 2493 nvme_put_ctrl(&dev->ctrl);
2494}
2495
fd634f41 2496static void nvme_reset_work(struct work_struct *work)
5e82e952 2497{
d86c4d8e
CH		 2498 struct nvme_dev *dev =
2499 container_of(work, struct nvme_dev, ctrl.reset_work);
a98e58e5 2500 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
f58944e2 2501 int result = -ENODEV;
2b1b7e78 2502 enum nvme_ctrl_state new_state = NVME_CTRL_LIVE;
5e82e952 2503
82b057ca 2504 if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING))
fd634f41 2505 goto out;
5e82e952 2506
fd634f41
CH		 2507 /*
2508 * If we're called to reset a live controller first shut it down before
2509 * moving on.
2510 */
b00a726a 2511 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
a5cdb68c 2512 nvme_dev_disable(dev, false);
5e82e952 2513
5c959d73 2514 mutex_lock(&dev->shutdown_lock);
b00a726a 2515 result = nvme_pci_enable(dev);
f0b50732 2516 if (result)
4726bcf3 2517 goto out_unlock;
f0b50732 2518
01ad0990 2519 result = nvme_pci_configure_admin_queue(dev);
f0b50732 2520 if (result)
4726bcf3 2521 goto out_unlock;
f0b50732 2522
0fb59cbc
KB		 2523 result = nvme_alloc_admin_tags(dev);
2524 if (result)
4726bcf3 2525 goto out_unlock;
b9afca3e 2526
943e942e
JA		 2527 /*
2528 * Limit the max command size to prevent iod->sg allocations going
2529 * over a single page.
2530 */
2531 dev->ctrl.max_hw_sectors = NVME_MAX_KB_SZ << 1;
2532 dev->ctrl.max_segments = NVME_MAX_SEGS;
5c959d73
KB		 2533 mutex_unlock(&dev->shutdown_lock);
2534
2535 /*
2536 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
2537 * initializing procedure here.
2538 */
2539 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
2540 dev_warn(dev->ctrl.device,
2541 "failed to mark controller CONNECTING\n");
2542 goto out;
2543 }
943e942e 2544
ce4541f4
CH		 2545 result = nvme_init_identify(&dev->ctrl);
2546 if (result)
f58944e2 2547 goto out;
ce4541f4 2548
e286bcfc
SB		 2549 if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
2550 if (!dev->ctrl.opal_dev)
2551 dev->ctrl.opal_dev =
2552 init_opal_dev(&dev->ctrl, &nvme_sec_submit);
2553 else if (was_suspend)
2554 opal_unlock_from_suspend(dev->ctrl.opal_dev);
2555 } else {
2556 free_opal_dev(dev->ctrl.opal_dev);
2557 dev->ctrl.opal_dev = NULL;
4f1244c8 2558 }
a98e58e5 2559
f9f38e33
HK		 2560 if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) {
2561 result = nvme_dbbuf_dma_alloc(dev);
2562 if (result)
2563 dev_warn(dev->dev,
2564 "unable to allocate dma for dbbuf\n");
2565 }
2566
9620cfba
CH		 2567 if (dev->ctrl.hmpre) {
2568 result = nvme_setup_host_mem(dev);
2569 if (result < 0)
2570 goto out;
2571 }
87ad72a5 2572
f0b50732 2573 result = nvme_setup_io_queues(dev);
badc34d4 2574 if (result)
f58944e2 2575 goto out;
f0b50732 2576
2659e57b
CH		 2577 /*
2578 * Keep the controller around but remove all namespaces if we don't have
2579 * any working I/O queue.
2580 */
3cf519b5 2581 if (dev->online_queues < 2) {
1b3c47c1 2582 dev_warn(dev->ctrl.device, "IO queues not created\n");
3b24774e 2583 nvme_kill_queues(&dev->ctrl);
5bae7f73 2584 nvme_remove_namespaces(&dev->ctrl);
2b1b7e78 2585 new_state = NVME_CTRL_ADMIN_ONLY;
3cf519b5 2586 } else {
25646264 2587 nvme_start_queues(&dev->ctrl);
302ad8cc 2588 nvme_wait_freeze(&dev->ctrl);
2b1b7e78
JW		 2589 /* hit this only when allocate tagset fails */
2590 if (nvme_dev_add(dev))
2591 new_state = NVME_CTRL_ADMIN_ONLY;
302ad8cc 2592 nvme_unfreeze(&dev->ctrl);
3cf519b5
CH		 2593 }
2594
2b1b7e78
JW		 2595 /*
2596 * If only admin queue live, keep it to do further investigation or
2597 * recovery.
2598 */
2599 if (!nvme_change_ctrl_state(&dev->ctrl, new_state)) {
2600 dev_warn(dev->ctrl.device,
2601 "failed to mark controller state %d\n", new_state);
bb8d261e
CH		 2602 goto out;
2603 }
92911a55 2604
d09f2b45 2605 nvme_start_ctrl(&dev->ctrl);
3cf519b5 2606 return;
f0b50732 2607
4726bcf3
KB		 2608 out_unlock:
2609 mutex_unlock(&dev->shutdown_lock);
3cf519b5 2610 out:
f58944e2 2611 nvme_remove_dead_ctrl(dev, result);
f0b50732
KB		 2612}
2613
5c8809e6 2614static void nvme_remove_dead_ctrl_work(struct work_struct *work)
9a6b9458 2615{
5c8809e6 2616 struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
e75ec752 2617 struct pci_dev *pdev = to_pci_dev(dev->dev);
9a6b9458
KB		 2618
2619 if (pci_get_drvdata(pdev))
921920ab 2620 device_release_driver(&pdev->dev);
1673f1f0 2621 nvme_put_ctrl(&dev->ctrl);
9a6b9458
KB		 2622}
2623
1c63dc66 2624static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
9ca97374 2625{
1c63dc66 2626 *val = readl(to_nvme_dev(ctrl)->bar + off);
90667892 2627 return 0;
9ca97374
TH		 2628}
2629
5fd4ce1b 2630static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
4cc06521 2631{
5fd4ce1b
CH		 2632 writel(val, to_nvme_dev(ctrl)->bar + off);
2633 return 0;
2634}
4cc06521 2635
7fd8930f
CH		 2636static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2637{
2638 *val = readq(to_nvme_dev(ctrl)->bar + off);
2639 return 0;
4cc06521
KB		 2640}
2641
97c12223
KB		 2642static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
2643{
2644 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2645
2646 return snprintf(buf, size, "%s", dev_name(&pdev->dev));
2647}
2648
1c63dc66 2649static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
1a353d85 2650 .name = "pcie",
e439bb12 2651 .module = THIS_MODULE,
e0596ab2
LG		 2652 .flags = NVME_F_METADATA_SUPPORTED |
2653 NVME_F_PCI_P2PDMA,
1c63dc66 2654 .reg_read32 = nvme_pci_reg_read32,
5fd4ce1b 2655 .reg_write32 = nvme_pci_reg_write32,
7fd8930f 2656 .reg_read64 = nvme_pci_reg_read64,
1673f1f0 2657 .free_ctrl = nvme_pci_free_ctrl,
f866fc42 2658 .submit_async_event = nvme_pci_submit_async_event,
97c12223 2659 .get_address = nvme_pci_get_address,
1c63dc66 2660};
4cc06521 2661
b00a726a
KB		 2662static int nvme_dev_map(struct nvme_dev *dev)
2663{
b00a726a
KB		 2664 struct pci_dev *pdev = to_pci_dev(dev->dev);
2665
a1f447b3 2666 if (pci_request_mem_regions(pdev, "nvme"))
b00a726a
KB		 2667 return -ENODEV;
2668
97f6ef64 2669 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
b00a726a
KB		 2670 goto release;
2671
9fa196e7 2672 return 0;
b00a726a 2673 release:
9fa196e7
MG		 2674 pci_release_mem_regions(pdev);
2675 return -ENODEV;
b00a726a
KB		 2676}
2677
8427bbc2 2678static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
ff5350a8
AL		 2679{
2680 if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
2681 /*
2682 * Several Samsung devices seem to drop off the PCIe bus
2683 * randomly when APST is on and uses the deepest sleep state.
2684 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2685 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2686 * 950 PRO 256GB", but it seems to be restricted to two Dell
2687 * laptops.
2688 */
2689 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
2690 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
2691 dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
2692 return NVME_QUIRK_NO_DEEPEST_PS;
8427bbc2
KHF		 2693 } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
2694 /*
2695 * Samsung SSD 960 EVO drops off the PCIe bus after system
467c77d4
JJ		 2696 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
2697 * within few minutes after bootup on a Coffee Lake board -
2698 * ASUS PRIME Z370-A
8427bbc2
KHF		 2699 */
2700 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
467c77d4
JJ		 2701 (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") ||
2702 dmi_match(DMI_BOARD_NAME, "PRIME Z370-A")))
8427bbc2 2703 return NVME_QUIRK_NO_APST;
ff5350a8
AL		 2704 }
2705
2706 return 0;
2707}
2708
18119775
KB		 2709static void nvme_async_probe(void *data, async_cookie_t cookie)
2710{
2711 struct nvme_dev *dev = data;
80f513b5 2712
18119775
KB		 2713 nvme_reset_ctrl_sync(&dev->ctrl);
2714 flush_work(&dev->ctrl.scan_work);
80f513b5 2715 nvme_put_ctrl(&dev->ctrl);
18119775
KB		 2716}
2717
8d85fce7 2718static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
b60503ba 2719{
a4aea562 2720 int node, result = -ENOMEM;
b60503ba 2721 struct nvme_dev *dev;
ff5350a8 2722 unsigned long quirks = id->driver_data;
943e942e 2723 size_t alloc_size;
b60503ba 2724
a4aea562
MB		 2725 node = dev_to_node(&pdev->dev);
2726 if (node == NUMA_NO_NODE)
2fa84351 2727 set_dev_node(&pdev->dev, first_memory_node);
a4aea562
MB		 2728
2729 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
b60503ba
MW		 2730 if (!dev)
2731 return -ENOMEM;
147b27e4 2732
3b6592f7
JA		 2733 dev->queues = kcalloc_node(max_queue_count(), sizeof(struct nvme_queue),
2734 GFP_KERNEL, node);
b60503ba
MW		 2735 if (!dev->queues)
2736 goto free;
2737
e75ec752 2738 dev->dev = get_device(&pdev->dev);
9a6b9458 2739 pci_set_drvdata(pdev, dev);
1c63dc66 2740
b00a726a
KB		 2741 result = nvme_dev_map(dev);
2742 if (result)
b00c9b7a 2743 goto put_pci;
b00a726a 2744
d86c4d8e 2745 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
5c8809e6 2746 INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
77bf25ea 2747 mutex_init(&dev->shutdown_lock);
b60503ba 2748
091b6092
MW		 2749 result = nvme_setup_prp_pools(dev);
2750 if (result)
b00c9b7a 2751 goto unmap;
4cc06521 2752
8427bbc2 2753 quirks |= check_vendor_combination_bug(pdev);
ff5350a8 2754
943e942e
JA		 2755 /*
2756 * Double check that our mempool alloc size will cover the biggest
2757 * command we support.
2758 */
2759 alloc_size = nvme_pci_iod_alloc_size(dev, NVME_MAX_KB_SZ,
2760 NVME_MAX_SEGS, true);
2761 WARN_ON_ONCE(alloc_size > PAGE_SIZE);
2762
2763 dev->iod_mempool = mempool_create_node(1, mempool_kmalloc,
2764 mempool_kfree,
2765 (void *) alloc_size,
2766 GFP_KERNEL, node);
2767 if (!dev->iod_mempool) {
2768 result = -ENOMEM;
2769 goto release_pools;
2770 }
2771
b6e44b4c
KB		 2772 result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
2773 quirks);
2774 if (result)
2775 goto release_mempool;
2776
1b3c47c1
SG		 2777 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
2778
80f513b5 2779 nvme_get_ctrl(&dev->ctrl);
18119775 2780 async_schedule(nvme_async_probe, dev);
4caff8fc 2781
b60503ba
MW		 2782 return 0;
2783
b6e44b4c
KB		 2784 release_mempool:
2785 mempool_destroy(dev->iod_mempool);
0877cb0d 2786 release_pools:
091b6092 2787 nvme_release_prp_pools(dev);
b00c9b7a
CJ		 2788 unmap:
2789 nvme_dev_unmap(dev);
a96d4f5c 2790 put_pci:
e75ec752 2791 put_device(dev->dev);
b60503ba
MW		 2792 free:
2793 kfree(dev->queues);
b60503ba
MW		 2794 kfree(dev);
2795 return result;
2796}
2797
775755ed 2798static void nvme_reset_prepare(struct pci_dev *pdev)
f0d54a54 2799{
a6739479 2800 struct nvme_dev *dev = pci_get_drvdata(pdev);
f263fbb8 2801 nvme_dev_disable(dev, false);
775755ed 2802}
f0d54a54 2803
775755ed
CH		 2804static void nvme_reset_done(struct pci_dev *pdev)
2805{
f263fbb8 2806 struct nvme_dev *dev = pci_get_drvdata(pdev);
79c48ccf 2807 nvme_reset_ctrl_sync(&dev->ctrl);
f0d54a54
KB		 2808}
2809
09ece142
KB		 2810static void nvme_shutdown(struct pci_dev *pdev)
2811{
2812 struct nvme_dev *dev = pci_get_drvdata(pdev);
a5cdb68c 2813 nvme_dev_disable(dev, true);
09ece142
KB		 2814}
2815
f58944e2
KB		 2816/*
2817 * The driver's remove may be called on a device in a partially initialized
2818 * state. This function must not have any dependencies on the device state in
2819 * order to proceed.
2820 */
8d85fce7 2821static void nvme_remove(struct pci_dev *pdev)
b60503ba
MW		 2822{
2823 struct nvme_dev *dev = pci_get_drvdata(pdev);
9a6b9458 2824
bb8d261e 2825 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
9a6b9458 2826 pci_set_drvdata(pdev, NULL);
0ff9d4e1 2827
6db28eda 2828 if (!pci_device_is_present(pdev)) {
0ff9d4e1 2829 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
1d39e692 2830 nvme_dev_disable(dev, true);
cb4bfda6 2831 nvme_dev_remove_admin(dev);
6db28eda 2832 }
0ff9d4e1 2833
d86c4d8e 2834 flush_work(&dev->ctrl.reset_work);
d09f2b45
SG		 2835 nvme_stop_ctrl(&dev->ctrl);
2836 nvme_remove_namespaces(&dev->ctrl);
a5cdb68c 2837 nvme_dev_disable(dev, true);
9fe5c59f 2838 nvme_release_cmb(dev);
87ad72a5 2839 nvme_free_host_mem(dev);
a4aea562 2840 nvme_dev_remove_admin(dev);
a1a5ef99 2841 nvme_free_queues(dev, 0);
d09f2b45 2842 nvme_uninit_ctrl(&dev->ctrl);
9a6b9458 2843 nvme_release_prp_pools(dev);
b00a726a 2844 nvme_dev_unmap(dev);
1673f1f0 2845 nvme_put_ctrl(&dev->ctrl);
b60503ba
MW		 2846}
2847
671a6018 2848#ifdef CONFIG_PM_SLEEP
cd638946
KB		 2849static int nvme_suspend(struct device *dev)
2850{
2851 struct pci_dev *pdev = to_pci_dev(dev);
2852 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2853
a5cdb68c 2854 nvme_dev_disable(ndev, true);
cd638946
KB		 2855 return 0;
2856}
2857
2858static int nvme_resume(struct device *dev)
2859{
2860 struct pci_dev *pdev = to_pci_dev(dev);
2861 struct nvme_dev *ndev = pci_get_drvdata(pdev);
cd638946 2862
d86c4d8e 2863 nvme_reset_ctrl(&ndev->ctrl);
9a6b9458 2864 return 0;
cd638946 2865}
671a6018 2866#endif
cd638946
KB		 2867
2868static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
b60503ba 2869
a0a3408e
KB		 2870static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
2871 pci_channel_state_t state)
2872{
2873 struct nvme_dev *dev = pci_get_drvdata(pdev);
2874
2875 /*
2876 * A frozen channel requires a reset. When detected, this method will
2877 * shutdown the controller to quiesce. The controller will be restarted
2878 * after the slot reset through driver's slot_reset callback.
2879 */
a0a3408e
KB		 2880 switch (state) {
2881 case pci_channel_io_normal:
2882 return PCI_ERS_RESULT_CAN_RECOVER;
2883 case pci_channel_io_frozen:
d011fb31
KB		 2884 dev_warn(dev->ctrl.device,
2885 "frozen state error detected, reset controller\n");
a5cdb68c 2886 nvme_dev_disable(dev, false);
a0a3408e
KB		 2887 return PCI_ERS_RESULT_NEED_RESET;
2888 case pci_channel_io_perm_failure:
d011fb31
KB		 2889 dev_warn(dev->ctrl.device,
2890 "failure state error detected, request disconnect\n");
a0a3408e
KB		 2891 return PCI_ERS_RESULT_DISCONNECT;
2892 }
2893 return PCI_ERS_RESULT_NEED_RESET;
2894}
2895
2896static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
2897{
2898 struct nvme_dev *dev = pci_get_drvdata(pdev);
2899
1b3c47c1 2900 dev_info(dev->ctrl.device, "restart after slot reset\n");
a0a3408e 2901 pci_restore_state(pdev);
d86c4d8e 2902 nvme_reset_ctrl(&dev->ctrl);
a0a3408e
KB		 2903 return PCI_ERS_RESULT_RECOVERED;
2904}
2905
2906static void nvme_error_resume(struct pci_dev *pdev)
2907{
72cd4cc2
KB		 2908 struct nvme_dev *dev = pci_get_drvdata(pdev);
2909
2910 flush_work(&dev->ctrl.reset_work);
a0a3408e
KB		 2911}
2912
1d352035 2913static const struct pci_error_handlers nvme_err_handler = {
b60503ba 2914 .error_detected = nvme_error_detected,
b60503ba
MW		 2915 .slot_reset = nvme_slot_reset,
2916 .resume = nvme_error_resume,
775755ed
CH		 2917 .reset_prepare = nvme_reset_prepare,
2918 .reset_done = nvme_reset_done,
b60503ba
MW		 2919};
2920
6eb0d698 2921static const struct pci_device_id nvme_id_table[] = {
106198ed 2922 { PCI_VDEVICE(INTEL, 0x0953),
08095e70 2923 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 2924 NVME_QUIRK_DEALLOCATE_ZEROES, },
99466e70
KB		 2925 { PCI_VDEVICE(INTEL, 0x0a53),
2926 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 2927 NVME_QUIRK_DEALLOCATE_ZEROES, },
99466e70
KB		 2928 { PCI_VDEVICE(INTEL, 0x0a54),
2929 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 2930 NVME_QUIRK_DEALLOCATE_ZEROES, },
f99cb7af
DWF		 2931 { PCI_VDEVICE(INTEL, 0x0a55),
2932 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2933 NVME_QUIRK_DEALLOCATE_ZEROES, },
50af47d0 2934 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */
9abd68ef
JA		 2935 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
2936 NVME_QUIRK_MEDIUM_PRIO_SQ },
6299358d
JD		 2937 { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */
2938 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
540c801c 2939 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */
7b210e4e
CH		 2940 .driver_data = NVME_QUIRK_IDENTIFY_CNS |
2941 NVME_QUIRK_DISABLE_WRITE_ZEROES, },
0302ae60
MP		 2942 { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */
2943 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
54adc010
GP		 2944 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
2945 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
8c97eecc
JL		 2946 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */
2947 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
015282c9
WW		 2948 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
2949 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
d554b5e1
MP		 2950 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */
2951 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2952 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */
2953 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
608cc4b1
CH		 2954 { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */
2955 .driver_data = NVME_QUIRK_LIGHTNVM, },
2956 { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */
2957 .driver_data = NVME_QUIRK_LIGHTNVM, },
ea48e877
WX		 2958 { PCI_DEVICE(0x1d1d, 0x2601), /* CNEX Granby */
2959 .driver_data = NVME_QUIRK_LIGHTNVM, },
b60503ba 2960 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
c74dc780 2961 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) },
124298bd 2962 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
b60503ba
MW		 2963 { 0, }
2964};
2965MODULE_DEVICE_TABLE(pci, nvme_id_table);
2966
2967static struct pci_driver nvme_driver = {
2968 .name = "nvme",
2969 .id_table = nvme_id_table,
2970 .probe = nvme_probe,
8d85fce7 2971 .remove = nvme_remove,
09ece142 2972 .shutdown = nvme_shutdown,
cd638946
KB		 2973 .driver = {
2974 .pm = &nvme_dev_pm_ops,
2975 },
74d986ab 2976 .sriov_configure = pci_sriov_configure_simple,
b60503ba
MW		 2977 .err_handler = &nvme_err_handler,
2978};
2979
2980static int __init nvme_init(void)
2981{
612b7286 2982 BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2);
9a6327d2 2983 return pci_register_driver(&nvme_driver);
b60503ba
MW		 2984}
2985
2986static void __exit nvme_exit(void)
2987{
2988 pci_unregister_driver(&nvme_driver);
03e0f3a6 2989 flush_workqueue(nvme_wq);
21bd78bc 2990 _nvme_check_size();
b60503ba
MW		 2991}
2992
2993MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2994MODULE_LICENSE("GPL");
c78b4713 2995MODULE_VERSION("1.0");
b60503ba
MW		 2996module_init(nvme_init);
2997module_exit(nvme_exit);
Linux 6.x block layer and io_uring tree(s)