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nvme: separate command prep and issue
[linux-2.6-block.git] / drivers / nvme / host / pci.c
CommitLineData
5f37396d 1// SPDX-License-Identifier: GPL-2.0
b60503ba
MW		 2/*
3 * NVM Express device driver
6eb0d698 4 * Copyright (c) 2011-2014, Intel Corporation.
b60503ba
MW		 5 */
6
df4f9bc4 7#include <linux/acpi.h>
a0a3408e 8#include <linux/aer.h>
18119775 9#include <linux/async.h>
b60503ba 10#include <linux/blkdev.h>
a4aea562 11#include <linux/blk-mq.h>
dca51e78 12#include <linux/blk-mq-pci.h>
fe45e630 13#include <linux/blk-integrity.h>
ff5350a8 14#include <linux/dmi.h>
b60503ba
MW		 15#include <linux/init.h>
16#include <linux/interrupt.h>
17#include <linux/io.h>
b60503ba
MW		 18#include <linux/mm.h>
19#include <linux/module.h>
77bf25ea 20#include <linux/mutex.h>
d0877473 21#include <linux/once.h>
b60503ba 22#include <linux/pci.h>
d916b1be 23#include <linux/suspend.h>
e1e5e564 24#include <linux/t10-pi.h>
b60503ba 25#include <linux/types.h>
2f8e2c87 26#include <linux/io-64-nonatomic-lo-hi.h>
20d3bb92 27#include <linux/io-64-nonatomic-hi-lo.h>
a98e58e5 28#include <linux/sed-opal.h>
0f238ff5 29#include <linux/pci-p2pdma.h>
797a796a 30
604c01d5 31#include "trace.h"
f11bb3e2
CH		 32#include "nvme.h"
33
c1e0cc7e 34#define SQ_SIZE(q) ((q)->q_depth << (q)->sqes)
8a1d09a6 35#define CQ_SIZE(q) ((q)->q_depth * sizeof(struct nvme_completion))
c965809c 36
a7a7cbe3 37#define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc))
9d43cf64 38
943e942e
JA		 39/*
40 * These can be higher, but we need to ensure that any command doesn't
41 * require an sg allocation that needs more than a page of data.
42 */
43#define NVME_MAX_KB_SZ 4096
44#define NVME_MAX_SEGS 127
45
58ffacb5
MW		 46static int use_threaded_interrupts;
47module_param(use_threaded_interrupts, int, 0);
48
8ffaadf7 49static bool use_cmb_sqes = true;
69f4eb9f 50module_param(use_cmb_sqes, bool, 0444);
8ffaadf7
JD		 51MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
52
87ad72a5
CH		 53static unsigned int max_host_mem_size_mb = 128;
54module_param(max_host_mem_size_mb, uint, 0444);
55MODULE_PARM_DESC(max_host_mem_size_mb,
56 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
1fa6aead 57
a7a7cbe3
CK		 58static unsigned int sgl_threshold = SZ_32K;
59module_param(sgl_threshold, uint, 0644);
60MODULE_PARM_DESC(sgl_threshold,
61 "Use SGLs when average request segment size is larger or equal to "
62 "this size. Use 0 to disable SGLs.");
63
27453b45
SG		 64#define NVME_PCI_MIN_QUEUE_SIZE 2
65#define NVME_PCI_MAX_QUEUE_SIZE 4095
b27c1e68 66static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
67static const struct kernel_param_ops io_queue_depth_ops = {
68 .set = io_queue_depth_set,
61f3b896 69 .get = param_get_uint,
b27c1e68 70};
71
61f3b896 72static unsigned int io_queue_depth = 1024;
b27c1e68 73module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
27453b45 74MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2 and < 4096");
b27c1e68 75
9c9e76d5
WZ		 76static int io_queue_count_set(const char *val, const struct kernel_param *kp)
77{
78 unsigned int n;
79 int ret;
80
81 ret = kstrtouint(val, 10, &n);
82 if (ret != 0 || n > num_possible_cpus())
83 return -EINVAL;
84 return param_set_uint(val, kp);
85}
86
87static const struct kernel_param_ops io_queue_count_ops = {
88 .set = io_queue_count_set,
89 .get = param_get_uint,
90};
91
3f68baf7 92static unsigned int write_queues;
9c9e76d5 93module_param_cb(write_queues, &io_queue_count_ops, &write_queues, 0644);
3b6592f7
JA		 94MODULE_PARM_DESC(write_queues,
95 "Number of queues to use for writes. If not set, reads and writes "
96 "will share a queue set.");
97
3f68baf7 98static unsigned int poll_queues;
9c9e76d5 99module_param_cb(poll_queues, &io_queue_count_ops, &poll_queues, 0644);
4b04cc6a
JA		 100MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO.");
101
df4f9bc4
DB		 102static bool noacpi;
103module_param(noacpi, bool, 0444);
104MODULE_PARM_DESC(noacpi, "disable acpi bios quirks");
105
1c63dc66
CH		 106struct nvme_dev;
107struct nvme_queue;
b3fffdef 108
a5cdb68c 109static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
8fae268b 110static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode);
d4b4ff8e 111
1c63dc66
CH		 112/*
113 * Represents an NVM Express device. Each nvme_dev is a PCI function.
114 */
115struct nvme_dev {
147b27e4 116 struct nvme_queue *queues;
1c63dc66
CH		 117 struct blk_mq_tag_set tagset;
118 struct blk_mq_tag_set admin_tagset;
119 u32 __iomem *dbs;
120 struct device *dev;
121 struct dma_pool *prp_page_pool;
122 struct dma_pool *prp_small_pool;
1c63dc66
CH		 123 unsigned online_queues;
124 unsigned max_qid;
e20ba6e1 125 unsigned io_queues[HCTX_MAX_TYPES];
22b55601 126 unsigned int num_vecs;
7442ddce 127 u32 q_depth;
c1e0cc7e 128 int io_sqes;
1c63dc66 129 u32 db_stride;
1c63dc66 130 void __iomem *bar;
97f6ef64 131 unsigned long bar_mapped_size;
5c8809e6 132 struct work_struct remove_work;
77bf25ea 133 struct mutex shutdown_lock;
1c63dc66 134 bool subsystem;
1c63dc66 135 u64 cmb_size;
0f238ff5 136 bool cmb_use_sqes;
1c63dc66 137 u32 cmbsz;
202021c1 138 u32 cmbloc;
1c63dc66 139 struct nvme_ctrl ctrl;
d916b1be 140 u32 last_ps;
a5df5e79 141 bool hmb;
87ad72a5 142
943e942e
JA		 143 mempool_t *iod_mempool;
144
87ad72a5 145 /* shadow doorbell buffer support: */
f9f38e33
HK		 146 u32 *dbbuf_dbs;
147 dma_addr_t dbbuf_dbs_dma_addr;
148 u32 *dbbuf_eis;
149 dma_addr_t dbbuf_eis_dma_addr;
87ad72a5
CH		 150
151 /* host memory buffer support: */
152 u64 host_mem_size;
153 u32 nr_host_mem_descs;
4033f35d 154 dma_addr_t host_mem_descs_dma;
87ad72a5
CH		 155 struct nvme_host_mem_buf_desc *host_mem_descs;
156 void **host_mem_desc_bufs;
2a5bcfdd
WZ		 157 unsigned int nr_allocated_queues;
158 unsigned int nr_write_queues;
159 unsigned int nr_poll_queues;
0521905e
KB		 160
161 bool attrs_added;
4d115420 162};
1fa6aead 163
b27c1e68 164static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
165{
27453b45
SG		 166 return param_set_uint_minmax(val, kp, NVME_PCI_MIN_QUEUE_SIZE,
167 NVME_PCI_MAX_QUEUE_SIZE);
b27c1e68 168}
169
f9f38e33
HK		 170static inline unsigned int sq_idx(unsigned int qid, u32 stride)
171{
172 return qid * 2 * stride;
173}
174
175static inline unsigned int cq_idx(unsigned int qid, u32 stride)
176{
177 return (qid * 2 + 1) * stride;
178}
179
1c63dc66
CH		 180static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
181{
182 return container_of(ctrl, struct nvme_dev, ctrl);
183}
184
b60503ba
MW		 185/*
186 * An NVM Express queue. Each device has at least two (one for admin
187 * commands and one for I/O commands).
188 */
189struct nvme_queue {
091b6092 190 struct nvme_dev *dev;
1ab0cd69 191 spinlock_t sq_lock;
c1e0cc7e 192 void *sq_cmds;
3a7afd8e
CH		 193 /* only used for poll queues: */
194 spinlock_t cq_poll_lock ____cacheline_aligned_in_smp;
74943d45 195 struct nvme_completion *cqes;
b60503ba
MW		 196 dma_addr_t sq_dma_addr;
197 dma_addr_t cq_dma_addr;
b60503ba 198 u32 __iomem *q_db;
7442ddce 199 u32 q_depth;
7c349dde 200 u16 cq_vector;
b60503ba 201 u16 sq_tail;
38210800 202 u16 last_sq_tail;
b60503ba 203 u16 cq_head;
c30341dc 204 u16 qid;
e9539f47 205 u8 cq_phase;
c1e0cc7e 206 u8 sqes;
4e224106
CH		 207 unsigned long flags;
208#define NVMEQ_ENABLED 0
63223078 209#define NVMEQ_SQ_CMB 1
d1ed6aa1 210#define NVMEQ_DELETE_ERROR 2
7c349dde 211#define NVMEQ_POLLED 3
f9f38e33
HK		 212 u32 *dbbuf_sq_db;
213 u32 *dbbuf_cq_db;
214 u32 *dbbuf_sq_ei;
215 u32 *dbbuf_cq_ei;
d1ed6aa1 216 struct completion delete_done;
b60503ba
MW		 217};
218
71bd150c 219/*
9b048119
CH		 220 * The nvme_iod describes the data in an I/O.
221 *
222 * The sg pointer contains the list of PRP/SGL chunk allocations in addition
223 * to the actual struct scatterlist.
71bd150c
CH		 224 */
225struct nvme_iod {
d49187e9 226 struct nvme_request req;
af7fae85 227 struct nvme_command cmd;
f4800d6d 228 struct nvme_queue *nvmeq;
a7a7cbe3 229 bool use_sgl;
f4800d6d 230 int aborted;
71bd150c 231 int npages; /* In the PRP list. 0 means small pool in use */
71bd150c 232 int nents; /* Used in scatterlist */
71bd150c 233 dma_addr_t first_dma;
dff824b2 234 unsigned int dma_len; /* length of single DMA segment mapping */
783b94bd 235 dma_addr_t meta_dma;
f4800d6d 236 struct scatterlist *sg;
b60503ba
MW		 237};
238
2a5bcfdd 239static inline unsigned int nvme_dbbuf_size(struct nvme_dev *dev)
3b6592f7 240{
2a5bcfdd 241 return dev->nr_allocated_queues * 8 * dev->db_stride;
f9f38e33
HK		 242}
243
244static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
245{
2a5bcfdd 246 unsigned int mem_size = nvme_dbbuf_size(dev);
f9f38e33 247
58847f12
KB		 248 if (dev->dbbuf_dbs) {
249 /*
250 * Clear the dbbuf memory so the driver doesn't observe stale
251 * values from the previous instantiation.
252 */
253 memset(dev->dbbuf_dbs, 0, mem_size);
254 memset(dev->dbbuf_eis, 0, mem_size);
f9f38e33 255 return 0;
58847f12 256 }
f9f38e33
HK		 257
258 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
259 &dev->dbbuf_dbs_dma_addr,
260 GFP_KERNEL);
261 if (!dev->dbbuf_dbs)
262 return -ENOMEM;
263 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
264 &dev->dbbuf_eis_dma_addr,
265 GFP_KERNEL);
266 if (!dev->dbbuf_eis) {
267 dma_free_coherent(dev->dev, mem_size,
268 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
269 dev->dbbuf_dbs = NULL;
270 return -ENOMEM;
271 }
272
273 return 0;
274}
275
276static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
277{
2a5bcfdd 278 unsigned int mem_size = nvme_dbbuf_size(dev);
f9f38e33
HK		 279
280 if (dev->dbbuf_dbs) {
281 dma_free_coherent(dev->dev, mem_size,
282 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
283 dev->dbbuf_dbs = NULL;
284 }
285 if (dev->dbbuf_eis) {
286 dma_free_coherent(dev->dev, mem_size,
287 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
288 dev->dbbuf_eis = NULL;
289 }
290}
291
292static void nvme_dbbuf_init(struct nvme_dev *dev,
293 struct nvme_queue *nvmeq, int qid)
294{
295 if (!dev->dbbuf_dbs || !qid)
296 return;
297
298 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
299 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
300 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
301 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
302}
303
0f0d2c87
MI		 304static void nvme_dbbuf_free(struct nvme_queue *nvmeq)
305{
306 if (!nvmeq->qid)
307 return;
308
309 nvmeq->dbbuf_sq_db = NULL;
310 nvmeq->dbbuf_cq_db = NULL;
311 nvmeq->dbbuf_sq_ei = NULL;
312 nvmeq->dbbuf_cq_ei = NULL;
313}
314
f9f38e33
HK		 315static void nvme_dbbuf_set(struct nvme_dev *dev)
316{
f66e2804 317 struct nvme_command c = { };
0f0d2c87 318 unsigned int i;
f9f38e33
HK		 319
320 if (!dev->dbbuf_dbs)
321 return;
322
f9f38e33
HK		 323 c.dbbuf.opcode = nvme_admin_dbbuf;
324 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
325 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
326
327 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
9bdcfb10 328 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
f9f38e33
HK		 329 /* Free memory and continue on */
330 nvme_dbbuf_dma_free(dev);
0f0d2c87
MI		 331
332 for (i = 1; i <= dev->online_queues; i++)
333 nvme_dbbuf_free(&dev->queues[i]);
f9f38e33
HK		 334 }
335}
336
337static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
338{
339 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
340}
341
342/* Update dbbuf and return true if an MMIO is required */
343static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
344 volatile u32 *dbbuf_ei)
345{
346 if (dbbuf_db) {
347 u16 old_value;
348
349 /*
350 * Ensure that the queue is written before updating
351 * the doorbell in memory
352 */
353 wmb();
354
355 old_value = *dbbuf_db;
356 *dbbuf_db = value;
357
f1ed3df2
MW		 358 /*
359 * Ensure that the doorbell is updated before reading the event
360 * index from memory. The controller needs to provide similar
361 * ordering to ensure the envent index is updated before reading
362 * the doorbell.
363 */
364 mb();
365
f9f38e33
HK		 366 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value))
367 return false;
368 }
369
370 return true;
b60503ba
MW		 371}
372
ac3dd5bd
JA		 373/*
374 * Will slightly overestimate the number of pages needed. This is OK
375 * as it only leads to a small amount of wasted memory for the lifetime of
376 * the I/O.
377 */
b13c6393 378static int nvme_pci_npages_prp(void)
ac3dd5bd 379{
b13c6393 380 unsigned nprps = DIV_ROUND_UP(NVME_MAX_KB_SZ + NVME_CTRL_PAGE_SIZE,
6c3c05b0 381 NVME_CTRL_PAGE_SIZE);
ac3dd5bd
JA		 382 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
383}
384
a7a7cbe3
CK		 385/*
386 * Calculates the number of pages needed for the SGL segments. For example a 4k
387 * page can accommodate 256 SGL descriptors.
388 */
b13c6393 389static int nvme_pci_npages_sgl(void)
ac3dd5bd 390{
b13c6393
CK		 391 return DIV_ROUND_UP(NVME_MAX_SEGS * sizeof(struct nvme_sgl_desc),
392 PAGE_SIZE);
f4800d6d 393}
ac3dd5bd 394
b13c6393 395static size_t nvme_pci_iod_alloc_size(void)
f4800d6d 396{
b13c6393 397 size_t npages = max(nvme_pci_npages_prp(), nvme_pci_npages_sgl());
a7a7cbe3 398
b13c6393
CK		 399 return sizeof(__le64 *) * npages +
400 sizeof(struct scatterlist) * NVME_MAX_SEGS;
f4800d6d 401}
ac3dd5bd 402
a4aea562
MB		 403static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
404 unsigned int hctx_idx)
e85248e5 405{
a4aea562 406 struct nvme_dev *dev = data;
147b27e4 407 struct nvme_queue *nvmeq = &dev->queues[0];
a4aea562 408
42483228
KB		 409 WARN_ON(hctx_idx != 0);
410 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
42483228 411
a4aea562
MB		 412 hctx->driver_data = nvmeq;
413 return 0;
e85248e5
MW		 414}
415
a4aea562
MB		 416static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
417 unsigned int hctx_idx)
b60503ba 418{
a4aea562 419 struct nvme_dev *dev = data;
147b27e4 420 struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
a4aea562 421
42483228 422 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
a4aea562
MB		 423 hctx->driver_data = nvmeq;
424 return 0;
b60503ba
MW		 425}
426
d6296d39
CH		 427static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req,
428 unsigned int hctx_idx, unsigned int numa_node)
b60503ba 429{
d6296d39 430 struct nvme_dev *dev = set->driver_data;
f4800d6d 431 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
0350815a 432 int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0;
147b27e4 433 struct nvme_queue *nvmeq = &dev->queues[queue_idx];
a4aea562
MB		 434
435 BUG_ON(!nvmeq);
f4800d6d 436 iod->nvmeq = nvmeq;
59e29ce6
SG		 437
438 nvme_req(req)->ctrl = &dev->ctrl;
f4b9e6c9 439 nvme_req(req)->cmd = &iod->cmd;
a4aea562
MB		 440 return 0;
441}
442
3b6592f7
JA		 443static int queue_irq_offset(struct nvme_dev *dev)
444{
445 /* if we have more than 1 vec, admin queue offsets us by 1 */
446 if (dev->num_vecs > 1)
447 return 1;
448
449 return 0;
450}
451
dca51e78
CH		 452static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
453{
454 struct nvme_dev *dev = set->driver_data;
3b6592f7
JA		 455 int i, qoff, offset;
456
457 offset = queue_irq_offset(dev);
458 for (i = 0, qoff = 0; i < set->nr_maps; i++) {
459 struct blk_mq_queue_map *map = &set->map[i];
460
461 map->nr_queues = dev->io_queues[i];
462 if (!map->nr_queues) {
e20ba6e1 463 BUG_ON(i == HCTX_TYPE_DEFAULT);
7e849dd9 464 continue;
3b6592f7
JA		 465 }
466
4b04cc6a
JA		 467 /*
468 * The poll queue(s) doesn't have an IRQ (and hence IRQ
469 * affinity), so use the regular blk-mq cpu mapping
470 */
3b6592f7 471 map->queue_offset = qoff;
cb9e0e50 472 if (i != HCTX_TYPE_POLL && offset)
4b04cc6a
JA		 473 blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset);
474 else
475 blk_mq_map_queues(map);
3b6592f7
JA		 476 qoff += map->nr_queues;
477 offset += map->nr_queues;
478 }
479
480 return 0;
dca51e78
CH		 481}
482
38210800
KB		 483/*
484 * Write sq tail if we are asked to, or if the next command would wrap.
485 */
486static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq)
04f3eafd 487{
38210800
KB		 488 if (!write_sq) {
489 u16 next_tail = nvmeq->sq_tail + 1;
490
491 if (next_tail == nvmeq->q_depth)
492 next_tail = 0;
493 if (next_tail != nvmeq->last_sq_tail)
494 return;
495 }
496
04f3eafd
JA		 497 if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail,
498 nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei))
499 writel(nvmeq->sq_tail, nvmeq->q_db);
38210800 500 nvmeq->last_sq_tail = nvmeq->sq_tail;
04f3eafd
JA		 501}
502
3233b94c
JA		 503static inline void nvme_sq_copy_cmd(struct nvme_queue *nvmeq,
504 struct nvme_command *cmd)
b60503ba 505{
c1e0cc7e 506 memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes),
3233b94c 507 absolute_pointer(cmd), sizeof(*cmd));
90ea5ca4
CH		 508 if (++nvmeq->sq_tail == nvmeq->q_depth)
509 nvmeq->sq_tail = 0;
04f3eafd
JA		 510}
511
512static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx)
513{
514 struct nvme_queue *nvmeq = hctx->driver_data;
515
516 spin_lock(&nvmeq->sq_lock);
38210800
KB		 517 if (nvmeq->sq_tail != nvmeq->last_sq_tail)
518 nvme_write_sq_db(nvmeq, true);
90ea5ca4 519 spin_unlock(&nvmeq->sq_lock);
b60503ba
MW		 520}
521
a7a7cbe3 522static void **nvme_pci_iod_list(struct request *req)
b60503ba 523{
f4800d6d 524 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3 525 return (void **)(iod->sg + blk_rq_nr_phys_segments(req));
b60503ba
MW		 526}
527
955b1b5a
MI		 528static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req)
529{
530 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
20469a37 531 int nseg = blk_rq_nr_phys_segments(req);
955b1b5a
MI		 532 unsigned int avg_seg_size;
533
20469a37 534 avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
955b1b5a 535
253a0b76 536 if (!nvme_ctrl_sgl_supported(&dev->ctrl))
955b1b5a
MI		 537 return false;
538 if (!iod->nvmeq->qid)
539 return false;
540 if (!sgl_threshold || avg_seg_size < sgl_threshold)
541 return false;
542 return true;
543}
544
9275c206 545static void nvme_free_prps(struct nvme_dev *dev, struct request *req)
b60503ba 546{
6c3c05b0 547 const int last_prp = NVME_CTRL_PAGE_SIZE / sizeof(__le64) - 1;
9275c206
CH		 548 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
549 dma_addr_t dma_addr = iod->first_dma;
eca18b23 550 int i;
eca18b23 551
9275c206
CH		 552 for (i = 0; i < iod->npages; i++) {
553 __le64 *prp_list = nvme_pci_iod_list(req)[i];
554 dma_addr_t next_dma_addr = le64_to_cpu(prp_list[last_prp]);
555
556 dma_pool_free(dev->prp_page_pool, prp_list, dma_addr);
557 dma_addr = next_dma_addr;
7fe07d14 558 }
9275c206 559}
dff824b2 560
9275c206
CH		 561static void nvme_free_sgls(struct nvme_dev *dev, struct request *req)
562{
563 const int last_sg = SGES_PER_PAGE - 1;
564 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
565 dma_addr_t dma_addr = iod->first_dma;
566 int i;
dff824b2 567
9275c206
CH		 568 for (i = 0; i < iod->npages; i++) {
569 struct nvme_sgl_desc *sg_list = nvme_pci_iod_list(req)[i];
570 dma_addr_t next_dma_addr = le64_to_cpu((sg_list[last_sg]).addr);
dff824b2 571
9275c206
CH		 572 dma_pool_free(dev->prp_page_pool, sg_list, dma_addr);
573 dma_addr = next_dma_addr;
574 }
9275c206 575}
a7a7cbe3 576
9275c206
CH		 577static void nvme_unmap_sg(struct nvme_dev *dev, struct request *req)
578{
579 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3 580
9275c206
CH		 581 if (is_pci_p2pdma_page(sg_page(iod->sg)))
582 pci_p2pdma_unmap_sg(dev->dev, iod->sg, iod->nents,
583 rq_dma_dir(req));
584 else
585 dma_unmap_sg(dev->dev, iod->sg, iod->nents, rq_dma_dir(req));
586}
a7a7cbe3 587
9275c206
CH		 588static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
589{
590 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3 591
9275c206
CH		 592 if (iod->dma_len) {
593 dma_unmap_page(dev->dev, iod->first_dma, iod->dma_len,
594 rq_dma_dir(req));
595 return;
eca18b23 596 }
ac3dd5bd 597
9275c206
CH		 598 WARN_ON_ONCE(!iod->nents);
599
600 nvme_unmap_sg(dev, req);
601 if (iod->npages == 0)
602 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0],
603 iod->first_dma);
604 else if (iod->use_sgl)
605 nvme_free_sgls(dev, req);
606 else
607 nvme_free_prps(dev, req);
d43f1ccf 608 mempool_free(iod->sg, dev->iod_mempool);
b4ff9c8d
KB		 609}
610
d0877473
KB		 611static void nvme_print_sgl(struct scatterlist *sgl, int nents)
612{
613 int i;
614 struct scatterlist *sg;
615
616 for_each_sg(sgl, sg, nents, i) {
617 dma_addr_t phys = sg_phys(sg);
618 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
619 "dma_address:%pad dma_length:%d\n",
620 i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
621 sg_dma_len(sg));
622 }
623}
624
a7a7cbe3
CK		 625static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
626 struct request *req, struct nvme_rw_command *cmnd)
ff22b54f 627{
f4800d6d 628 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
99802a7a 629 struct dma_pool *pool;
b131c61d 630 int length = blk_rq_payload_bytes(req);
eca18b23 631 struct scatterlist *sg = iod->sg;
ff22b54f
MW		 632 int dma_len = sg_dma_len(sg);
633 u64 dma_addr = sg_dma_address(sg);
6c3c05b0 634 int offset = dma_addr & (NVME_CTRL_PAGE_SIZE - 1);
e025344c 635 __le64 *prp_list;
a7a7cbe3 636 void **list = nvme_pci_iod_list(req);
e025344c 637 dma_addr_t prp_dma;
eca18b23 638 int nprps, i;
ff22b54f 639
6c3c05b0 640 length -= (NVME_CTRL_PAGE_SIZE - offset);
5228b328
JS		 641 if (length <= 0) {
642 iod->first_dma = 0;
a7a7cbe3 643 goto done;
5228b328 644 }
ff22b54f 645
6c3c05b0 646 dma_len -= (NVME_CTRL_PAGE_SIZE - offset);
ff22b54f 647 if (dma_len) {
6c3c05b0 648 dma_addr += (NVME_CTRL_PAGE_SIZE - offset);
ff22b54f
MW		 649 } else {
650 sg = sg_next(sg);
651 dma_addr = sg_dma_address(sg);
652 dma_len = sg_dma_len(sg);
653 }
654
6c3c05b0 655 if (length <= NVME_CTRL_PAGE_SIZE) {
edd10d33 656 iod->first_dma = dma_addr;
a7a7cbe3 657 goto done;
e025344c
SMM		 658 }
659
6c3c05b0 660 nprps = DIV_ROUND_UP(length, NVME_CTRL_PAGE_SIZE);
99802a7a
MW		 661 if (nprps <= (256 / 8)) {
662 pool = dev->prp_small_pool;
eca18b23 663 iod->npages = 0;
99802a7a
MW		 664 } else {
665 pool = dev->prp_page_pool;
eca18b23 666 iod->npages = 1;
99802a7a
MW		 667 }
668
69d2b571 669 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
b77954cb 670 if (!prp_list) {
edd10d33 671 iod->first_dma = dma_addr;
eca18b23 672 iod->npages = -1;
86eea289 673 return BLK_STS_RESOURCE;
b77954cb 674 }
eca18b23
MW		 675 list[0] = prp_list;
676 iod->first_dma = prp_dma;
e025344c
SMM		 677 i = 0;
678 for (;;) {
6c3c05b0 679 if (i == NVME_CTRL_PAGE_SIZE >> 3) {
e025344c 680 __le64 *old_prp_list = prp_list;
69d2b571 681 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
eca18b23 682 if (!prp_list)
fa073216 683 goto free_prps;
eca18b23 684 list[iod->npages++] = prp_list;
7523d834
MW		 685 prp_list[0] = old_prp_list[i - 1];
686 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
687 i = 1;
e025344c
SMM		 688 }
689 prp_list[i++] = cpu_to_le64(dma_addr);
6c3c05b0
CK		 690 dma_len -= NVME_CTRL_PAGE_SIZE;
691 dma_addr += NVME_CTRL_PAGE_SIZE;
692 length -= NVME_CTRL_PAGE_SIZE;
e025344c
SMM		 693 if (length <= 0)
694 break;
695 if (dma_len > 0)
696 continue;
86eea289
KB		 697 if (unlikely(dma_len < 0))
698 goto bad_sgl;
e025344c
SMM		 699 sg = sg_next(sg);
700 dma_addr = sg_dma_address(sg);
701 dma_len = sg_dma_len(sg);
ff22b54f 702 }
a7a7cbe3
CK		 703done:
704 cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
705 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
86eea289 706 return BLK_STS_OK;
fa073216
CH		 707free_prps:
708 nvme_free_prps(dev, req);
709 return BLK_STS_RESOURCE;
710bad_sgl:
d0877473
KB		 711 WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents),
712 "Invalid SGL for payload:%d nents:%d\n",
713 blk_rq_payload_bytes(req), iod->nents);
86eea289 714 return BLK_STS_IOERR;
ff22b54f
MW		 715}
716
a7a7cbe3
CK		 717static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
718 struct scatterlist *sg)
719{
720 sge->addr = cpu_to_le64(sg_dma_address(sg));
721 sge->length = cpu_to_le32(sg_dma_len(sg));
722 sge->type = NVME_SGL_FMT_DATA_DESC << 4;
723}
724
725static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
726 dma_addr_t dma_addr, int entries)
727{
728 sge->addr = cpu_to_le64(dma_addr);
729 if (entries < SGES_PER_PAGE) {
730 sge->length = cpu_to_le32(entries * sizeof(*sge));
731 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
732 } else {
733 sge->length = cpu_to_le32(PAGE_SIZE);
734 sge->type = NVME_SGL_FMT_SEG_DESC << 4;
735 }
736}
737
738static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
b0f2853b 739 struct request *req, struct nvme_rw_command *cmd, int entries)
a7a7cbe3
CK		 740{
741 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3
CK		 742 struct dma_pool *pool;
743 struct nvme_sgl_desc *sg_list;
744 struct scatterlist *sg = iod->sg;
a7a7cbe3 745 dma_addr_t sgl_dma;
b0f2853b 746 int i = 0;
a7a7cbe3 747
a7a7cbe3
CK		 748 /* setting the transfer type as SGL */
749 cmd->flags = NVME_CMD_SGL_METABUF;
750
b0f2853b 751 if (entries == 1) {
a7a7cbe3
CK		 752 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
753 return BLK_STS_OK;
754 }
755
756 if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
757 pool = dev->prp_small_pool;
758 iod->npages = 0;
759 } else {
760 pool = dev->prp_page_pool;
761 iod->npages = 1;
762 }
763
764 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
765 if (!sg_list) {
766 iod->npages = -1;
767 return BLK_STS_RESOURCE;
768 }
769
770 nvme_pci_iod_list(req)[0] = sg_list;
771 iod->first_dma = sgl_dma;
772
773 nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
774
775 do {
776 if (i == SGES_PER_PAGE) {
777 struct nvme_sgl_desc *old_sg_desc = sg_list;
778 struct nvme_sgl_desc *link = &old_sg_desc[i - 1];
779
780 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
781 if (!sg_list)
fa073216 782 goto free_sgls;
a7a7cbe3
CK		 783
784 i = 0;
785 nvme_pci_iod_list(req)[iod->npages++] = sg_list;
786 sg_list[i++] = *link;
787 nvme_pci_sgl_set_seg(link, sgl_dma, entries);
788 }
789
790 nvme_pci_sgl_set_data(&sg_list[i++], sg);
a7a7cbe3 791 sg = sg_next(sg);
b0f2853b 792 } while (--entries > 0);
a7a7cbe3 793
a7a7cbe3 794 return BLK_STS_OK;
fa073216
CH		 795free_sgls:
796 nvme_free_sgls(dev, req);
797 return BLK_STS_RESOURCE;
a7a7cbe3
CK		 798}
799
dff824b2
CH		 800static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev,
801 struct request *req, struct nvme_rw_command *cmnd,
802 struct bio_vec *bv)
803{
804 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
6c3c05b0
CK		 805 unsigned int offset = bv->bv_offset & (NVME_CTRL_PAGE_SIZE - 1);
806 unsigned int first_prp_len = NVME_CTRL_PAGE_SIZE - offset;
dff824b2
CH		 807
808 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
809 if (dma_mapping_error(dev->dev, iod->first_dma))
810 return BLK_STS_RESOURCE;
811 iod->dma_len = bv->bv_len;
812
813 cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma);
814 if (bv->bv_len > first_prp_len)
815 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len);
359c1f88 816 return BLK_STS_OK;
dff824b2
CH		 817}
818
29791057
CH		 819static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev,
820 struct request *req, struct nvme_rw_command *cmnd,
821 struct bio_vec *bv)
822{
823 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
824
825 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
826 if (dma_mapping_error(dev->dev, iod->first_dma))
827 return BLK_STS_RESOURCE;
828 iod->dma_len = bv->bv_len;
829
049bf372 830 cmnd->flags = NVME_CMD_SGL_METABUF;
29791057
CH		 831 cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma);
832 cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len);
833 cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4;
359c1f88 834 return BLK_STS_OK;
29791057
CH		 835}
836
fc17b653 837static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
b131c61d 838 struct nvme_command *cmnd)
d29ec824 839{
f4800d6d 840 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
70479b71 841 blk_status_t ret = BLK_STS_RESOURCE;
b0f2853b 842 int nr_mapped;
d29ec824 843
dff824b2
CH		 844 if (blk_rq_nr_phys_segments(req) == 1) {
845 struct bio_vec bv = req_bvec(req);
846
847 if (!is_pci_p2pdma_page(bv.bv_page)) {
6c3c05b0 848 if (bv.bv_offset + bv.bv_len <= NVME_CTRL_PAGE_SIZE * 2)
dff824b2
CH		 849 return nvme_setup_prp_simple(dev, req,
850 &cmnd->rw, &bv);
29791057 851
e51183be 852 if (iod->nvmeq->qid && sgl_threshold &&
253a0b76 853 nvme_ctrl_sgl_supported(&dev->ctrl))
29791057
CH		 854 return nvme_setup_sgl_simple(dev, req,
855 &cmnd->rw, &bv);
dff824b2
CH		 856 }
857 }
858
859 iod->dma_len = 0;
d43f1ccf
CH		 860 iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC);
861 if (!iod->sg)
862 return BLK_STS_RESOURCE;
f9d03f96 863 sg_init_table(iod->sg, blk_rq_nr_phys_segments(req));
70479b71 864 iod->nents = blk_rq_map_sg(req->q, req, iod->sg);
ba1ca37e 865 if (!iod->nents)
fa073216 866 goto out_free_sg;
d29ec824 867
e0596ab2 868 if (is_pci_p2pdma_page(sg_page(iod->sg)))
2b9f4bb2
LG		 869 nr_mapped = pci_p2pdma_map_sg_attrs(dev->dev, iod->sg,
870 iod->nents, rq_dma_dir(req), DMA_ATTR_NO_WARN);
e0596ab2
LG		 871 else
872 nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents,
70479b71 873 rq_dma_dir(req), DMA_ATTR_NO_WARN);
b0f2853b 874 if (!nr_mapped)
fa073216 875 goto out_free_sg;
d29ec824 876
70479b71 877 iod->use_sgl = nvme_pci_use_sgls(dev, req);
955b1b5a 878 if (iod->use_sgl)
b0f2853b 879 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped);
a7a7cbe3
CK		 880 else
881 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
86eea289 882 if (ret != BLK_STS_OK)
fa073216
CH		 883 goto out_unmap_sg;
884 return BLK_STS_OK;
885
886out_unmap_sg:
887 nvme_unmap_sg(dev, req);
888out_free_sg:
889 mempool_free(iod->sg, dev->iod_mempool);
4aedb705
CH		 890 return ret;
891}
3045c0d0 892
4aedb705
CH		 893static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req,
894 struct nvme_command *cmnd)
895{
896 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
00df5cb4 897
4aedb705
CH		 898 iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req),
899 rq_dma_dir(req), 0);
900 if (dma_mapping_error(dev->dev, iod->meta_dma))
901 return BLK_STS_IOERR;
902 cmnd->rw.metadata = cpu_to_le64(iod->meta_dma);
359c1f88 903 return BLK_STS_OK;
00df5cb4
MW		 904}
905
62451a2b 906static blk_status_t nvme_prep_rq(struct nvme_dev *dev, struct request *req)
edd10d33 907{
9b048119 908 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
ebe6d874 909 blk_status_t ret;
e1e5e564 910
9b048119
CH		 911 iod->aborted = 0;
912 iod->npages = -1;
913 iod->nents = 0;
914
62451a2b 915 ret = nvme_setup_cmd(req->q->queuedata, req);
fc17b653 916 if (ret)
f4800d6d 917 return ret;
a4aea562 918
fc17b653 919 if (blk_rq_nr_phys_segments(req)) {
62451a2b 920 ret = nvme_map_data(dev, req, &iod->cmd);
fc17b653 921 if (ret)
9b048119 922 goto out_free_cmd;
fc17b653 923 }
a4aea562 924
4aedb705 925 if (blk_integrity_rq(req)) {
62451a2b 926 ret = nvme_map_metadata(dev, req, &iod->cmd);
4aedb705
CH		 927 if (ret)
928 goto out_unmap_data;
929 }
930
aae239e1 931 blk_mq_start_request(req);
fc17b653 932 return BLK_STS_OK;
4aedb705
CH		 933out_unmap_data:
934 nvme_unmap_data(dev, req);
f9d03f96
CH		 935out_free_cmd:
936 nvme_cleanup_cmd(req);
ba1ca37e 937 return ret;
b60503ba 938}
e1e5e564 939
62451a2b
JA		 940/*
941 * NOTE: ns is NULL when called on the admin queue.
942 */
943static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
944 const struct blk_mq_queue_data *bd)
945{
946 struct nvme_queue *nvmeq = hctx->driver_data;
947 struct nvme_dev *dev = nvmeq->dev;
948 struct request *req = bd->rq;
949 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
950 blk_status_t ret;
951
952 /*
953 * We should not need to do this, but we're still using this to
954 * ensure we can drain requests on a dying queue.
955 */
956 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
957 return BLK_STS_IOERR;
958
959 if (unlikely(!nvme_check_ready(&dev->ctrl, req, true)))
960 return nvme_fail_nonready_command(&dev->ctrl, req);
961
962 ret = nvme_prep_rq(dev, req);
963 if (unlikely(ret))
964 return ret;
965 spin_lock(&nvmeq->sq_lock);
966 nvme_sq_copy_cmd(nvmeq, &iod->cmd);
967 nvme_write_sq_db(nvmeq, bd->last);
968 spin_unlock(&nvmeq->sq_lock);
969 return BLK_STS_OK;
970}
971
c234a653 972static __always_inline void nvme_pci_unmap_rq(struct request *req)
eee417b0 973{
f4800d6d 974 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
4aedb705 975 struct nvme_dev *dev = iod->nvmeq->dev;
a4aea562 976
4aedb705
CH		 977 if (blk_integrity_rq(req))
978 dma_unmap_page(dev->dev, iod->meta_dma,
979 rq_integrity_vec(req)->bv_len, rq_data_dir(req));
b15c592d 980 if (blk_rq_nr_phys_segments(req))
4aedb705 981 nvme_unmap_data(dev, req);
c234a653
JA		 982}
983
984static void nvme_pci_complete_rq(struct request *req)
985{
986 nvme_pci_unmap_rq(req);
77f02a7a 987 nvme_complete_rq(req);
b60503ba
MW		 988}
989
c234a653
JA		 990static void nvme_pci_complete_batch(struct io_comp_batch *iob)
991{
992 nvme_complete_batch(iob, nvme_pci_unmap_rq);
993}
994
d783e0bd 995/* We read the CQE phase first to check if the rest of the entry is valid */
750dde44 996static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq)
d783e0bd 997{
74943d45
KB		 998 struct nvme_completion *hcqe = &nvmeq->cqes[nvmeq->cq_head];
999
1000 return (le16_to_cpu(READ_ONCE(hcqe->status)) & 1) == nvmeq->cq_phase;
d783e0bd
MR		 1001}
1002
eb281c82 1003static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
b60503ba 1004{
eb281c82 1005 u16 head = nvmeq->cq_head;
adf68f21 1006
397c699f
KB		 1007 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
1008 nvmeq->dbbuf_cq_ei))
1009 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
eb281c82 1010}
aae239e1 1011
cfa27356
CH		 1012static inline struct blk_mq_tags *nvme_queue_tagset(struct nvme_queue *nvmeq)
1013{
1014 if (!nvmeq->qid)
1015 return nvmeq->dev->admin_tagset.tags[0];
1016 return nvmeq->dev->tagset.tags[nvmeq->qid - 1];
1017}
1018
c234a653
JA		 1019static inline void nvme_handle_cqe(struct nvme_queue *nvmeq,
1020 struct io_comp_batch *iob, u16 idx)
83a12fb7 1021{
74943d45 1022 struct nvme_completion *cqe = &nvmeq->cqes[idx];
62df8016 1023 __u16 command_id = READ_ONCE(cqe->command_id);
83a12fb7 1024 struct request *req;
adf68f21 1025
83a12fb7
SG		 1026 /*
1027 * AEN requests are special as they don't time out and can
1028 * survive any kind of queue freeze and often don't respond to
1029 * aborts. We don't even bother to allocate a struct request
1030 * for them but rather special case them here.
1031 */
62df8016 1032 if (unlikely(nvme_is_aen_req(nvmeq->qid, command_id))) {
83a12fb7
SG		 1033 nvme_complete_async_event(&nvmeq->dev->ctrl,
1034 cqe->status, &cqe->result);
a0fa9647 1035 return;
83a12fb7 1036 }
b60503ba 1037
e7006de6 1038 req = nvme_find_rq(nvme_queue_tagset(nvmeq), command_id);
50b7c243
XT		 1039 if (unlikely(!req)) {
1040 dev_warn(nvmeq->dev->ctrl.device,
1041 "invalid id %d completed on queue %d\n",
62df8016 1042 command_id, le16_to_cpu(cqe->sq_id));
50b7c243
XT		 1043 return;
1044 }
1045
604c01d5 1046 trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail);
c234a653
JA		 1047 if (!nvme_try_complete_req(req, cqe->status, cqe->result) &&
1048 !blk_mq_add_to_batch(req, iob, nvme_req(req)->status,
1049 nvme_pci_complete_batch))
ff029451 1050 nvme_pci_complete_rq(req);
83a12fb7 1051}
b60503ba 1052
5cb525c8
JA		 1053static inline void nvme_update_cq_head(struct nvme_queue *nvmeq)
1054{
a0aac973 1055 u32 tmp = nvmeq->cq_head + 1;
a8de6639
AD		 1056
1057 if (tmp == nvmeq->q_depth) {
5cb525c8 1058 nvmeq->cq_head = 0;
e2a366a4 1059 nvmeq->cq_phase ^= 1;
a8de6639
AD		 1060 } else {
1061 nvmeq->cq_head = tmp;
b60503ba 1062 }
a0fa9647
JA		 1063}
1064
c234a653
JA		 1065static inline int nvme_poll_cq(struct nvme_queue *nvmeq,
1066 struct io_comp_batch *iob)
a0fa9647 1067{
1052b8ac 1068 int found = 0;
b60503ba 1069
1052b8ac 1070 while (nvme_cqe_pending(nvmeq)) {
bf392a5d 1071 found++;
b69e2ef2
KB		 1072 /*
1073 * load-load control dependency between phase and the rest of
1074 * the cqe requires a full read memory barrier
1075 */
1076 dma_rmb();
c234a653 1077 nvme_handle_cqe(nvmeq, iob, nvmeq->cq_head);
5cb525c8 1078 nvme_update_cq_head(nvmeq);
920d13a8 1079 }
eb281c82 1080
324b494c 1081 if (found)
920d13a8 1082 nvme_ring_cq_doorbell(nvmeq);
5cb525c8 1083 return found;
b60503ba
MW		 1084}
1085
1086static irqreturn_t nvme_irq(int irq, void *data)
58ffacb5 1087{
58ffacb5 1088 struct nvme_queue *nvmeq = data;
4f502245 1089 DEFINE_IO_COMP_BATCH(iob);
5cb525c8 1090
4f502245
JA		 1091 if (nvme_poll_cq(nvmeq, &iob)) {
1092 if (!rq_list_empty(iob.req_list))
1093 nvme_pci_complete_batch(&iob);
05fae499 1094 return IRQ_HANDLED;
4f502245 1095 }
05fae499 1096 return IRQ_NONE;
58ffacb5
MW		 1097}
1098
1099static irqreturn_t nvme_irq_check(int irq, void *data)
1100{
1101 struct nvme_queue *nvmeq = data;
4e523547 1102
750dde44 1103 if (nvme_cqe_pending(nvmeq))
d783e0bd
MR		 1104 return IRQ_WAKE_THREAD;
1105 return IRQ_NONE;
58ffacb5
MW		 1106}
1107
0b2a8a9f 1108/*
fa059b85 1109 * Poll for completions for any interrupt driven queue
0b2a8a9f
CH		 1110 * Can be called from any context.
1111 */
fa059b85 1112static void nvme_poll_irqdisable(struct nvme_queue *nvmeq)
a0fa9647 1113{
3a7afd8e 1114 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
a0fa9647 1115
fa059b85 1116 WARN_ON_ONCE(test_bit(NVMEQ_POLLED, &nvmeq->flags));
442e19b7 1117
fa059b85 1118 disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
c234a653 1119 nvme_poll_cq(nvmeq, NULL);
fa059b85 1120 enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
a0fa9647
JA		 1121}
1122
5a72e899 1123static int nvme_poll(struct blk_mq_hw_ctx *hctx, struct io_comp_batch *iob)
dabcefab
JA		 1124{
1125 struct nvme_queue *nvmeq = hctx->driver_data;
dabcefab
JA		 1126 bool found;
1127
1128 if (!nvme_cqe_pending(nvmeq))
1129 return 0;
1130
3a7afd8e 1131 spin_lock(&nvmeq->cq_poll_lock);
c234a653 1132 found = nvme_poll_cq(nvmeq, iob);
3a7afd8e 1133 spin_unlock(&nvmeq->cq_poll_lock);
dabcefab 1134
dabcefab
JA		 1135 return found;
1136}
1137
ad22c355 1138static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
b60503ba 1139{
f866fc42 1140 struct nvme_dev *dev = to_nvme_dev(ctrl);
147b27e4 1141 struct nvme_queue *nvmeq = &dev->queues[0];
f66e2804 1142 struct nvme_command c = { };
b60503ba 1143
a4aea562 1144 c.common.opcode = nvme_admin_async_event;
ad22c355 1145 c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
3233b94c
JA		 1146
1147 spin_lock(&nvmeq->sq_lock);
1148 nvme_sq_copy_cmd(nvmeq, &c);
1149 nvme_write_sq_db(nvmeq, true);
1150 spin_unlock(&nvmeq->sq_lock);
f705f837
CH		 1151}
1152
b60503ba 1153static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
f705f837 1154{
f66e2804 1155 struct nvme_command c = { };
b60503ba 1156
b60503ba
MW		 1157 c.delete_queue.opcode = opcode;
1158 c.delete_queue.qid = cpu_to_le16(id);
1159
1c63dc66 1160 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1161}
1162
b60503ba 1163static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
a8e3e0bb 1164 struct nvme_queue *nvmeq, s16 vector)
b60503ba 1165{
f66e2804 1166 struct nvme_command c = { };
4b04cc6a
JA		 1167 int flags = NVME_QUEUE_PHYS_CONTIG;
1168
7c349dde 1169 if (!test_bit(NVMEQ_POLLED, &nvmeq->flags))
4b04cc6a 1170 flags |= NVME_CQ_IRQ_ENABLED;
b60503ba 1171
d29ec824 1172 /*
16772ae6 1173 * Note: we (ab)use the fact that the prp fields survive if no data
d29ec824
CH		 1174 * is attached to the request.
1175 */
b60503ba
MW		 1176 c.create_cq.opcode = nvme_admin_create_cq;
1177 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1178 c.create_cq.cqid = cpu_to_le16(qid);
1179 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1180 c.create_cq.cq_flags = cpu_to_le16(flags);
7c349dde 1181 c.create_cq.irq_vector = cpu_to_le16(vector);
b60503ba 1182
1c63dc66 1183 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1184}
1185
1186static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1187 struct nvme_queue *nvmeq)
1188{
9abd68ef 1189 struct nvme_ctrl *ctrl = &dev->ctrl;
f66e2804 1190 struct nvme_command c = { };
81c1cd98 1191 int flags = NVME_QUEUE_PHYS_CONTIG;
b60503ba 1192
9abd68ef
JA		 1193 /*
1194 * Some drives have a bug that auto-enables WRRU if MEDIUM isn't
1195 * set. Since URGENT priority is zeroes, it makes all queues
1196 * URGENT.
1197 */
1198 if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ)
1199 flags |= NVME_SQ_PRIO_MEDIUM;
1200
d29ec824 1201 /*
16772ae6 1202 * Note: we (ab)use the fact that the prp fields survive if no data
d29ec824
CH		 1203 * is attached to the request.
1204 */
b60503ba
MW		 1205 c.create_sq.opcode = nvme_admin_create_sq;
1206 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1207 c.create_sq.sqid = cpu_to_le16(qid);
1208 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1209 c.create_sq.sq_flags = cpu_to_le16(flags);
1210 c.create_sq.cqid = cpu_to_le16(qid);
1211
1c63dc66 1212 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1213}
1214
1215static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1216{
1217 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1218}
1219
1220static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1221{
1222 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1223}
1224
2a842aca 1225static void abort_endio(struct request *req, blk_status_t error)
bc5fc7e4 1226{
f4800d6d
CH		 1227 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1228 struct nvme_queue *nvmeq = iod->nvmeq;
e44ac588 1229
27fa9bc5
CH		 1230 dev_warn(nvmeq->dev->ctrl.device,
1231 "Abort status: 0x%x", nvme_req(req)->status);
e7a2a87d 1232 atomic_inc(&nvmeq->dev->ctrl.abort_limit);
e7a2a87d 1233 blk_mq_free_request(req);
bc5fc7e4
MW		 1234}
1235
b2a0eb1a
KB		 1236static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1237{
b2a0eb1a
KB		 1238 /* If true, indicates loss of adapter communication, possibly by a
1239 * NVMe Subsystem reset.
1240 */
1241 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1242
ad70062c
JW		 1243 /* If there is a reset/reinit ongoing, we shouldn't reset again. */
1244 switch (dev->ctrl.state) {
1245 case NVME_CTRL_RESETTING:
ad6a0a52 1246 case NVME_CTRL_CONNECTING:
b2a0eb1a 1247 return false;
ad70062c
JW		 1248 default:
1249 break;
1250 }
b2a0eb1a
KB		 1251
1252 /* We shouldn't reset unless the controller is on fatal error state
1253 * _or_ if we lost the communication with it.
1254 */
1255 if (!(csts & NVME_CSTS_CFS) && !nssro)
1256 return false;
1257
b2a0eb1a
KB		 1258 return true;
1259}
1260
1261static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1262{
1263 /* Read a config register to help see what died. */
1264 u16 pci_status;
1265 int result;
1266
1267 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1268 &pci_status);
1269 if (result == PCIBIOS_SUCCESSFUL)
1270 dev_warn(dev->ctrl.device,
1271 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1272 csts, pci_status);
1273 else
1274 dev_warn(dev->ctrl.device,
1275 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1276 csts, result);
1277}
1278
31c7c7d2 1279static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
c30341dc 1280{
f4800d6d
CH		 1281 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1282 struct nvme_queue *nvmeq = iod->nvmeq;
c30341dc 1283 struct nvme_dev *dev = nvmeq->dev;
a4aea562 1284 struct request *abort_req;
f66e2804 1285 struct nvme_command cmd = { };
b2a0eb1a
KB		 1286 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1287
651438bb
WX		 1288 /* If PCI error recovery process is happening, we cannot reset or
1289 * the recovery mechanism will surely fail.
1290 */
1291 mb();
1292 if (pci_channel_offline(to_pci_dev(dev->dev)))
1293 return BLK_EH_RESET_TIMER;
1294
b2a0eb1a
KB		 1295 /*
1296 * Reset immediately if the controller is failed
1297 */
1298 if (nvme_should_reset(dev, csts)) {
1299 nvme_warn_reset(dev, csts);
1300 nvme_dev_disable(dev, false);
d86c4d8e 1301 nvme_reset_ctrl(&dev->ctrl);
db8c48e4 1302 return BLK_EH_DONE;
b2a0eb1a 1303 }
c30341dc 1304
7776db1c
KB		 1305 /*
1306 * Did we miss an interrupt?
1307 */
fa059b85 1308 if (test_bit(NVMEQ_POLLED, &nvmeq->flags))
5a72e899 1309 nvme_poll(req->mq_hctx, NULL);
fa059b85
KB		 1310 else
1311 nvme_poll_irqdisable(nvmeq);
1312
bf392a5d 1313 if (blk_mq_request_completed(req)) {
7776db1c
KB		 1314 dev_warn(dev->ctrl.device,
1315 "I/O %d QID %d timeout, completion polled\n",
1316 req->tag, nvmeq->qid);
db8c48e4 1317 return BLK_EH_DONE;
7776db1c
KB		 1318 }
1319
31c7c7d2 1320 /*
fd634f41
CH		 1321 * Shutdown immediately if controller times out while starting. The
1322 * reset work will see the pci device disabled when it gets the forced
1323 * cancellation error. All outstanding requests are completed on
db8c48e4 1324 * shutdown, so we return BLK_EH_DONE.
fd634f41 1325 */
4244140d
KB		 1326 switch (dev->ctrl.state) {
1327 case NVME_CTRL_CONNECTING:
2036f726 1328 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
df561f66 1329 fallthrough;
2036f726 1330 case NVME_CTRL_DELETING:
b9cac43c 1331 dev_warn_ratelimited(dev->ctrl.device,
fd634f41
CH		 1332 "I/O %d QID %d timeout, disable controller\n",
1333 req->tag, nvmeq->qid);
27fa9bc5 1334 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
7ad92f65 1335 nvme_dev_disable(dev, true);
db8c48e4 1336 return BLK_EH_DONE;
39a9dd81
KB		 1337 case NVME_CTRL_RESETTING:
1338 return BLK_EH_RESET_TIMER;
4244140d
KB		 1339 default:
1340 break;
c30341dc
KB		 1341 }
1342
fd634f41 1343 /*
ee0d96d3
BW		 1344 * Shutdown the controller immediately and schedule a reset if the
1345 * command was already aborted once before and still hasn't been
1346 * returned to the driver, or if this is the admin queue.
31c7c7d2 1347 */
f4800d6d 1348 if (!nvmeq->qid || iod->aborted) {
1b3c47c1 1349 dev_warn(dev->ctrl.device,
e1569a16
KB		 1350 "I/O %d QID %d timeout, reset controller\n",
1351 req->tag, nvmeq->qid);
7ad92f65 1352 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
a5cdb68c 1353 nvme_dev_disable(dev, false);
d86c4d8e 1354 nvme_reset_ctrl(&dev->ctrl);
c30341dc 1355
db8c48e4 1356 return BLK_EH_DONE;
c30341dc 1357 }
c30341dc 1358
e7a2a87d 1359 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
6bf25d16 1360 atomic_inc(&dev->ctrl.abort_limit);
31c7c7d2 1361 return BLK_EH_RESET_TIMER;
6bf25d16 1362 }
7bf7d778 1363 iod->aborted = 1;
a4aea562 1364
c30341dc 1365 cmd.abort.opcode = nvme_admin_abort_cmd;
85f74acf 1366 cmd.abort.cid = nvme_cid(req);
c30341dc 1367 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
c30341dc 1368
1b3c47c1
SG		 1369 dev_warn(nvmeq->dev->ctrl.device,
1370 "I/O %d QID %d timeout, aborting\n",
1371 req->tag, nvmeq->qid);
e7a2a87d
CH		 1372
1373 abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
39dfe844 1374 BLK_MQ_REQ_NOWAIT);
e7a2a87d
CH		 1375 if (IS_ERR(abort_req)) {
1376 atomic_inc(&dev->ctrl.abort_limit);
1377 return BLK_EH_RESET_TIMER;
1378 }
1379
e7a2a87d 1380 abort_req->end_io_data = NULL;
b84ba30b 1381 blk_execute_rq_nowait(abort_req, false, abort_endio);
c30341dc 1382
31c7c7d2
CH		 1383 /*
1384 * The aborted req will be completed on receiving the abort req.
1385 * We enable the timer again. If hit twice, it'll cause a device reset,
1386 * as the device then is in a faulty state.
1387 */
1388 return BLK_EH_RESET_TIMER;
c30341dc
KB		 1389}
1390
a4aea562
MB		 1391static void nvme_free_queue(struct nvme_queue *nvmeq)
1392{
8a1d09a6 1393 dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq),
9e866774 1394 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
63223078
CH		 1395 if (!nvmeq->sq_cmds)
1396 return;
0f238ff5 1397
63223078 1398 if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) {
88a041f4 1399 pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev),
8a1d09a6 1400 nvmeq->sq_cmds, SQ_SIZE(nvmeq));
63223078 1401 } else {
8a1d09a6 1402 dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq),
63223078 1403 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
0f238ff5 1404 }
9e866774
MW		 1405}
1406
a1a5ef99 1407static void nvme_free_queues(struct nvme_dev *dev, int lowest)
22404274
KB		 1408{
1409 int i;
1410
d858e5f0 1411 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
d858e5f0 1412 dev->ctrl.queue_count--;
147b27e4 1413 nvme_free_queue(&dev->queues[i]);
121c7ad4 1414 }
22404274
KB		 1415}
1416
4d115420
KB		 1417/**
1418 * nvme_suspend_queue - put queue into suspended state
40581d1a 1419 * @nvmeq: queue to suspend
4d115420
KB		 1420 */
1421static int nvme_suspend_queue(struct nvme_queue *nvmeq)
b60503ba 1422{
4e224106 1423 if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags))
2b25d981 1424 return 1;
a09115b2 1425
4e224106 1426 /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */
d1f06f4a 1427 mb();
a09115b2 1428
4e224106 1429 nvmeq->dev->online_queues--;
1c63dc66 1430 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
6ca1d902 1431 nvme_stop_admin_queue(&nvmeq->dev->ctrl);
7c349dde
KB		 1432 if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags))
1433 pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq);
4d115420
KB		 1434 return 0;
1435}
b60503ba 1436
8fae268b
KB		 1437static void nvme_suspend_io_queues(struct nvme_dev *dev)
1438{
1439 int i;
1440
1441 for (i = dev->ctrl.queue_count - 1; i > 0; i--)
1442 nvme_suspend_queue(&dev->queues[i]);
1443}
1444
a5cdb68c 1445static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
4d115420 1446{
147b27e4 1447 struct nvme_queue *nvmeq = &dev->queues[0];
4d115420 1448
a5cdb68c
KB		 1449 if (shutdown)
1450 nvme_shutdown_ctrl(&dev->ctrl);
1451 else
b5b05048 1452 nvme_disable_ctrl(&dev->ctrl);
07836e65 1453
bf392a5d 1454 nvme_poll_irqdisable(nvmeq);
b60503ba
MW		 1455}
1456
fa46c6fb
KB		 1457/*
1458 * Called only on a device that has been disabled and after all other threads
9210c075
DZ		 1459 * that can check this device's completion queues have synced, except
1460 * nvme_poll(). This is the last chance for the driver to see a natural
1461 * completion before nvme_cancel_request() terminates all incomplete requests.
fa46c6fb
KB		 1462 */
1463static void nvme_reap_pending_cqes(struct nvme_dev *dev)
1464{
fa46c6fb
KB		 1465 int i;
1466
9210c075
DZ		 1467 for (i = dev->ctrl.queue_count - 1; i > 0; i--) {
1468 spin_lock(&dev->queues[i].cq_poll_lock);
c234a653 1469 nvme_poll_cq(&dev->queues[i], NULL);
9210c075
DZ		 1470 spin_unlock(&dev->queues[i].cq_poll_lock);
1471 }
fa46c6fb
KB		 1472}
1473
8ffaadf7
JD		 1474static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1475 int entry_size)
1476{
1477 int q_depth = dev->q_depth;
5fd4ce1b 1478 unsigned q_size_aligned = roundup(q_depth * entry_size,
6c3c05b0 1479 NVME_CTRL_PAGE_SIZE);
8ffaadf7
JD		 1480
1481 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
c45f5c99 1482 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
4e523547 1483
6c3c05b0 1484 mem_per_q = round_down(mem_per_q, NVME_CTRL_PAGE_SIZE);
c45f5c99 1485 q_depth = div_u64(mem_per_q, entry_size);
8ffaadf7
JD		 1486
1487 /*
1488 * Ensure the reduced q_depth is above some threshold where it
1489 * would be better to map queues in system memory with the
1490 * original depth
1491 */
1492 if (q_depth < 64)
1493 return -ENOMEM;
1494 }
1495
1496 return q_depth;
1497}
1498
1499static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
8a1d09a6 1500 int qid)
8ffaadf7 1501{
0f238ff5
LG		 1502 struct pci_dev *pdev = to_pci_dev(dev->dev);
1503
1504 if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
8a1d09a6 1505 nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq));
bfac8e9f
AM		 1506 if (nvmeq->sq_cmds) {
1507 nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev,
1508 nvmeq->sq_cmds);
1509 if (nvmeq->sq_dma_addr) {
1510 set_bit(NVMEQ_SQ_CMB, &nvmeq->flags);
1511 return 0;
1512 }
1513
8a1d09a6 1514 pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq));
63223078 1515 }
0f238ff5 1516 }
8ffaadf7 1517
8a1d09a6 1518 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq),
63223078 1519 &nvmeq->sq_dma_addr, GFP_KERNEL);
815c6704
KB		 1520 if (!nvmeq->sq_cmds)
1521 return -ENOMEM;
8ffaadf7
JD		 1522 return 0;
1523}
1524
a6ff7262 1525static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
b60503ba 1526{
147b27e4 1527 struct nvme_queue *nvmeq = &dev->queues[qid];
b60503ba 1528
62314e40
KB		 1529 if (dev->ctrl.queue_count > qid)
1530 return 0;
b60503ba 1531
c1e0cc7e 1532 nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES;
8a1d09a6
BH		 1533 nvmeq->q_depth = depth;
1534 nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq),
750afb08 1535 &nvmeq->cq_dma_addr, GFP_KERNEL);
b60503ba
MW		 1536 if (!nvmeq->cqes)
1537 goto free_nvmeq;
b60503ba 1538
8a1d09a6 1539 if (nvme_alloc_sq_cmds(dev, nvmeq, qid))
b60503ba
MW		 1540 goto free_cqdma;
1541
091b6092 1542 nvmeq->dev = dev;
1ab0cd69 1543 spin_lock_init(&nvmeq->sq_lock);
3a7afd8e 1544 spin_lock_init(&nvmeq->cq_poll_lock);
b60503ba 1545 nvmeq->cq_head = 0;
82123460 1546 nvmeq->cq_phase = 1;
b80d5ccc 1547 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
c30341dc 1548 nvmeq->qid = qid;
d858e5f0 1549 dev->ctrl.queue_count++;
36a7e993 1550
147b27e4 1551 return 0;
b60503ba
MW		 1552
1553 free_cqdma:
8a1d09a6
BH		 1554 dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes,
1555 nvmeq->cq_dma_addr);
b60503ba 1556 free_nvmeq:
147b27e4 1557 return -ENOMEM;
b60503ba
MW		 1558}
1559
dca51e78 1560static int queue_request_irq(struct nvme_queue *nvmeq)
3001082c 1561{
0ff199cb
CH		 1562 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1563 int nr = nvmeq->dev->ctrl.instance;
1564
1565 if (use_threaded_interrupts) {
1566 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1567 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1568 } else {
1569 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1570 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1571 }
3001082c
MW		 1572}
1573
22404274 1574static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
b60503ba 1575{
22404274 1576 struct nvme_dev *dev = nvmeq->dev;
b60503ba 1577
22404274 1578 nvmeq->sq_tail = 0;
38210800 1579 nvmeq->last_sq_tail = 0;
22404274
KB		 1580 nvmeq->cq_head = 0;
1581 nvmeq->cq_phase = 1;
b80d5ccc 1582 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
8a1d09a6 1583 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq));
f9f38e33 1584 nvme_dbbuf_init(dev, nvmeq, qid);
42f61420 1585 dev->online_queues++;
3a7afd8e 1586 wmb(); /* ensure the first interrupt sees the initialization */
22404274
KB		 1587}
1588
e4b9852a
CC		 1589/*
1590 * Try getting shutdown_lock while setting up IO queues.
1591 */
1592static int nvme_setup_io_queues_trylock(struct nvme_dev *dev)
1593{
1594 /*
1595 * Give up if the lock is being held by nvme_dev_disable.
1596 */
1597 if (!mutex_trylock(&dev->shutdown_lock))
1598 return -ENODEV;
1599
1600 /*
1601 * Controller is in wrong state, fail early.
1602 */
1603 if (dev->ctrl.state != NVME_CTRL_CONNECTING) {
1604 mutex_unlock(&dev->shutdown_lock);
1605 return -ENODEV;
1606 }
1607
1608 return 0;
1609}
1610
4b04cc6a 1611static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled)
22404274
KB		 1612{
1613 struct nvme_dev *dev = nvmeq->dev;
1614 int result;
7c349dde 1615 u16 vector = 0;
3f85d50b 1616
d1ed6aa1
CH		 1617 clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
1618
22b55601
KB		 1619 /*
1620 * A queue's vector matches the queue identifier unless the controller
1621 * has only one vector available.
1622 */
4b04cc6a
JA		 1623 if (!polled)
1624 vector = dev->num_vecs == 1 ? 0 : qid;
1625 else
7c349dde 1626 set_bit(NVMEQ_POLLED, &nvmeq->flags);
4b04cc6a 1627
a8e3e0bb 1628 result = adapter_alloc_cq(dev, qid, nvmeq, vector);
ded45505
KB		 1629 if (result)
1630 return result;
b60503ba
MW		 1631
1632 result = adapter_alloc_sq(dev, qid, nvmeq);
1633 if (result < 0)
ded45505 1634 return result;
c80b36cd 1635 if (result)
b60503ba
MW		 1636 goto release_cq;
1637
a8e3e0bb 1638 nvmeq->cq_vector = vector;
4b04cc6a 1639
e4b9852a
CC		 1640 result = nvme_setup_io_queues_trylock(dev);
1641 if (result)
1642 return result;
1643 nvme_init_queue(nvmeq, qid);
7c349dde 1644 if (!polled) {
4b04cc6a
JA		 1645 result = queue_request_irq(nvmeq);
1646 if (result < 0)
1647 goto release_sq;
1648 }
b60503ba 1649
4e224106 1650 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
e4b9852a 1651 mutex_unlock(&dev->shutdown_lock);
22404274 1652 return result;
b60503ba 1653
a8e3e0bb 1654release_sq:
f25a2dfc 1655 dev->online_queues--;
e4b9852a 1656 mutex_unlock(&dev->shutdown_lock);
b60503ba 1657 adapter_delete_sq(dev, qid);
a8e3e0bb 1658release_cq:
b60503ba 1659 adapter_delete_cq(dev, qid);
22404274 1660 return result;
b60503ba
MW		 1661}
1662
f363b089 1663static const struct blk_mq_ops nvme_mq_admin_ops = {
d29ec824 1664 .queue_rq = nvme_queue_rq,
77f02a7a 1665 .complete = nvme_pci_complete_rq,
a4aea562 1666 .init_hctx = nvme_admin_init_hctx,
0350815a 1667 .init_request = nvme_init_request,
a4aea562
MB		 1668 .timeout = nvme_timeout,
1669};
1670
f363b089 1671static const struct blk_mq_ops nvme_mq_ops = {
376f7ef8
CH		 1672 .queue_rq = nvme_queue_rq,
1673 .complete = nvme_pci_complete_rq,
1674 .commit_rqs = nvme_commit_rqs,
1675 .init_hctx = nvme_init_hctx,
1676 .init_request = nvme_init_request,
1677 .map_queues = nvme_pci_map_queues,
1678 .timeout = nvme_timeout,
1679 .poll = nvme_poll,
dabcefab
JA		 1680};
1681
ea191d2f
KB		 1682static void nvme_dev_remove_admin(struct nvme_dev *dev)
1683{
1c63dc66 1684 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
69d9a99c
KB		 1685 /*
1686 * If the controller was reset during removal, it's possible
1687 * user requests may be waiting on a stopped queue. Start the
1688 * queue to flush these to completion.
1689 */
6ca1d902 1690 nvme_start_admin_queue(&dev->ctrl);
1c63dc66 1691 blk_cleanup_queue(dev->ctrl.admin_q);
ea191d2f
KB		 1692 blk_mq_free_tag_set(&dev->admin_tagset);
1693 }
1694}
1695
a4aea562
MB		 1696static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1697{
1c63dc66 1698 if (!dev->ctrl.admin_q) {
a4aea562
MB		 1699 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1700 dev->admin_tagset.nr_hw_queues = 1;
e3e9d50c 1701
38dabe21 1702 dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH;
dc96f938 1703 dev->admin_tagset.timeout = NVME_ADMIN_TIMEOUT;
d4ec47f1 1704 dev->admin_tagset.numa_node = dev->ctrl.numa_node;
d43f1ccf 1705 dev->admin_tagset.cmd_size = sizeof(struct nvme_iod);
d3484991 1706 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED;
a4aea562
MB		 1707 dev->admin_tagset.driver_data = dev;
1708
1709 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1710 return -ENOMEM;
34b6c231 1711 dev->ctrl.admin_tagset = &dev->admin_tagset;
a4aea562 1712
1c63dc66
CH		 1713 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1714 if (IS_ERR(dev->ctrl.admin_q)) {
a4aea562
MB		 1715 blk_mq_free_tag_set(&dev->admin_tagset);
1716 return -ENOMEM;
1717 }
1c63dc66 1718 if (!blk_get_queue(dev->ctrl.admin_q)) {
ea191d2f 1719 nvme_dev_remove_admin(dev);
1c63dc66 1720 dev->ctrl.admin_q = NULL;
ea191d2f
KB		 1721 return -ENODEV;
1722 }
0fb59cbc 1723 } else
6ca1d902 1724 nvme_start_admin_queue(&dev->ctrl);
a4aea562
MB		 1725
1726 return 0;
1727}
1728
97f6ef64
XY		 1729static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1730{
1731 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1732}
1733
1734static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1735{
1736 struct pci_dev *pdev = to_pci_dev(dev->dev);
1737
1738 if (size <= dev->bar_mapped_size)
1739 return 0;
1740 if (size > pci_resource_len(pdev, 0))
1741 return -ENOMEM;
1742 if (dev->bar)
1743 iounmap(dev->bar);
1744 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1745 if (!dev->bar) {
1746 dev->bar_mapped_size = 0;
1747 return -ENOMEM;
1748 }
1749 dev->bar_mapped_size = size;
1750 dev->dbs = dev->bar + NVME_REG_DBS;
1751
1752 return 0;
1753}
1754
01ad0990 1755static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
b60503ba 1756{
ba47e386 1757 int result;
b60503ba
MW		 1758 u32 aqa;
1759 struct nvme_queue *nvmeq;
1760
97f6ef64
XY		 1761 result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1762 if (result < 0)
1763 return result;
1764
8ef2074d 1765 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
20d0dfe6 1766 NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
dfbac8c7 1767
7a67cbea
CH		 1768 if (dev->subsystem &&
1769 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1770 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
dfbac8c7 1771
b5b05048 1772 result = nvme_disable_ctrl(&dev->ctrl);
ba47e386
MW		 1773 if (result < 0)
1774 return result;
b60503ba 1775
a6ff7262 1776 result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
147b27e4
SG		 1777 if (result)
1778 return result;
b60503ba 1779
635333e4
MG		 1780 dev->ctrl.numa_node = dev_to_node(dev->dev);
1781
147b27e4 1782 nvmeq = &dev->queues[0];
b60503ba
MW		 1783 aqa = nvmeq->q_depth - 1;
1784 aqa |= aqa << 16;
1785
7a67cbea
CH		 1786 writel(aqa, dev->bar + NVME_REG_AQA);
1787 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1788 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
b60503ba 1789
c0f2f45b 1790 result = nvme_enable_ctrl(&dev->ctrl);
025c557a 1791 if (result)
d4875622 1792 return result;
a4aea562 1793
2b25d981 1794 nvmeq->cq_vector = 0;
161b8be2 1795 nvme_init_queue(nvmeq, 0);
dca51e78 1796 result = queue_request_irq(nvmeq);
758dd7fd 1797 if (result) {
7c349dde 1798 dev->online_queues--;
d4875622 1799 return result;
758dd7fd 1800 }
025c557a 1801
4e224106 1802 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
b60503ba
MW		 1803 return result;
1804}
1805
749941f2 1806static int nvme_create_io_queues(struct nvme_dev *dev)
42f61420 1807{
4b04cc6a 1808 unsigned i, max, rw_queues;
749941f2 1809 int ret = 0;
42f61420 1810
d858e5f0 1811 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
a6ff7262 1812 if (nvme_alloc_queue(dev, i, dev->q_depth)) {
749941f2 1813 ret = -ENOMEM;
42f61420 1814 break;
749941f2
CH		 1815 }
1816 }
42f61420 1817
d858e5f0 1818 max = min(dev->max_qid, dev->ctrl.queue_count - 1);
e20ba6e1
CH		 1819 if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) {
1820 rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] +
1821 dev->io_queues[HCTX_TYPE_READ];
4b04cc6a
JA		 1822 } else {
1823 rw_queues = max;
1824 }
1825
949928c1 1826 for (i = dev->online_queues; i <= max; i++) {
4b04cc6a
JA		 1827 bool polled = i > rw_queues;
1828
1829 ret = nvme_create_queue(&dev->queues[i], i, polled);
d4875622 1830 if (ret)
42f61420 1831 break;
27e8166c 1832 }
749941f2
CH		 1833
1834 /*
1835 * Ignore failing Create SQ/CQ commands, we can continue with less
8adb8c14
MI		 1836 * than the desired amount of queues, and even a controller without
1837 * I/O queues can still be used to issue admin commands. This might
749941f2
CH		 1838 * be useful to upgrade a buggy firmware for example.
1839 */
1840 return ret >= 0 ? 0 : ret;
b60503ba
MW		 1841}
1842
88de4598 1843static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
8ffaadf7 1844{
88de4598
CH		 1845 u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
1846
1847 return 1ULL << (12 + 4 * szu);
1848}
1849
1850static u32 nvme_cmb_size(struct nvme_dev *dev)
1851{
1852 return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
1853}
1854
f65efd6d 1855static void nvme_map_cmb(struct nvme_dev *dev)
8ffaadf7 1856{
88de4598 1857 u64 size, offset;
8ffaadf7
JD		 1858 resource_size_t bar_size;
1859 struct pci_dev *pdev = to_pci_dev(dev->dev);
8969f1f8 1860 int bar;
8ffaadf7 1861
9fe5c59f
KB		 1862 if (dev->cmb_size)
1863 return;
1864
20d3bb92
KJ		 1865 if (NVME_CAP_CMBS(dev->ctrl.cap))
1866 writel(NVME_CMBMSC_CRE, dev->bar + NVME_REG_CMBMSC);
1867
7a67cbea 1868 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
f65efd6d
CH		 1869 if (!dev->cmbsz)
1870 return;
202021c1 1871 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
8ffaadf7 1872
88de4598
CH		 1873 size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
1874 offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
8969f1f8
CH		 1875 bar = NVME_CMB_BIR(dev->cmbloc);
1876 bar_size = pci_resource_len(pdev, bar);
8ffaadf7
JD		 1877
1878 if (offset > bar_size)
f65efd6d 1879 return;
8ffaadf7 1880
20d3bb92
KJ		 1881 /*
1882 * Tell the controller about the host side address mapping the CMB,
1883 * and enable CMB decoding for the NVMe 1.4+ scheme:
1884 */
1885 if (NVME_CAP_CMBS(dev->ctrl.cap)) {
1886 hi_lo_writeq(NVME_CMBMSC_CRE | NVME_CMBMSC_CMSE |
1887 (pci_bus_address(pdev, bar) + offset),
1888 dev->bar + NVME_REG_CMBMSC);
1889 }
1890
8ffaadf7
JD		 1891 /*
1892 * Controllers may support a CMB size larger than their BAR,
1893 * for example, due to being behind a bridge. Reduce the CMB to
1894 * the reported size of the BAR
1895 */
1896 if (size > bar_size - offset)
1897 size = bar_size - offset;
1898
0f238ff5
LG		 1899 if (pci_p2pdma_add_resource(pdev, bar, size, offset)) {
1900 dev_warn(dev->ctrl.device,
1901 "failed to register the CMB\n");
f65efd6d 1902 return;
0f238ff5
LG		 1903 }
1904
8ffaadf7 1905 dev->cmb_size = size;
0f238ff5
LG		 1906 dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS);
1907
1908 if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) ==
1909 (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS))
1910 pci_p2pmem_publish(pdev, true);
8ffaadf7
JD		 1911}
1912
87ad72a5
CH		 1913static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1914{
6c3c05b0 1915 u32 host_mem_size = dev->host_mem_size >> NVME_CTRL_PAGE_SHIFT;
4033f35d 1916 u64 dma_addr = dev->host_mem_descs_dma;
f66e2804 1917 struct nvme_command c = { };
87ad72a5
CH		 1918 int ret;
1919
87ad72a5
CH		 1920 c.features.opcode = nvme_admin_set_features;
1921 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1922 c.features.dword11 = cpu_to_le32(bits);
6c3c05b0 1923 c.features.dword12 = cpu_to_le32(host_mem_size);
87ad72a5
CH		 1924 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr));
1925 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr));
1926 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs);
1927
1928 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1929 if (ret) {
1930 dev_warn(dev->ctrl.device,
1931 "failed to set host mem (err %d, flags %#x).\n",
1932 ret, bits);
a5df5e79
KB		 1933 } else
1934 dev->hmb = bits & NVME_HOST_MEM_ENABLE;
1935
87ad72a5
CH		 1936 return ret;
1937}
1938
1939static void nvme_free_host_mem(struct nvme_dev *dev)
1940{
1941 int i;
1942
1943 for (i = 0; i < dev->nr_host_mem_descs; i++) {
1944 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
6c3c05b0 1945 size_t size = le32_to_cpu(desc->size) * NVME_CTRL_PAGE_SIZE;
87ad72a5 1946
cc667f6d
LD		 1947 dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i],
1948 le64_to_cpu(desc->addr),
1949 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
87ad72a5
CH		 1950 }
1951
1952 kfree(dev->host_mem_desc_bufs);
1953 dev->host_mem_desc_bufs = NULL;
4033f35d
CH		 1954 dma_free_coherent(dev->dev,
1955 dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
1956 dev->host_mem_descs, dev->host_mem_descs_dma);
87ad72a5 1957 dev->host_mem_descs = NULL;
7e5dd57e 1958 dev->nr_host_mem_descs = 0;
87ad72a5
CH		 1959}
1960
92dc6895
CH		 1961static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
1962 u32 chunk_size)
9d713c2b 1963{
87ad72a5 1964 struct nvme_host_mem_buf_desc *descs;
92dc6895 1965 u32 max_entries, len;
4033f35d 1966 dma_addr_t descs_dma;
2ee0e4ed 1967 int i = 0;
87ad72a5 1968 void **bufs;
6fbcde66 1969 u64 size, tmp;
87ad72a5 1970
87ad72a5
CH		 1971 tmp = (preferred + chunk_size - 1);
1972 do_div(tmp, chunk_size);
1973 max_entries = tmp;
044a9df1
CH		 1974
1975 if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
1976 max_entries = dev->ctrl.hmmaxd;
1977
750afb08
LC		 1978 descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs),
1979 &descs_dma, GFP_KERNEL);
87ad72a5
CH		 1980 if (!descs)
1981 goto out;
1982
1983 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
1984 if (!bufs)
1985 goto out_free_descs;
1986
244a8fe4 1987 for (size = 0; size < preferred && i < max_entries; size += len) {
87ad72a5
CH		 1988 dma_addr_t dma_addr;
1989
50cdb7c6 1990 len = min_t(u64, chunk_size, preferred - size);
87ad72a5
CH		 1991 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
1992 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1993 if (!bufs[i])
1994 break;
1995
1996 descs[i].addr = cpu_to_le64(dma_addr);
6c3c05b0 1997 descs[i].size = cpu_to_le32(len / NVME_CTRL_PAGE_SIZE);
87ad72a5
CH		 1998 i++;
1999 }
2000
92dc6895 2001 if (!size)
87ad72a5 2002 goto out_free_bufs;
87ad72a5 2003
87ad72a5
CH		 2004 dev->nr_host_mem_descs = i;
2005 dev->host_mem_size = size;
2006 dev->host_mem_descs = descs;
4033f35d 2007 dev->host_mem_descs_dma = descs_dma;
87ad72a5
CH		 2008 dev->host_mem_desc_bufs = bufs;
2009 return 0;
2010
2011out_free_bufs:
2012 while (--i >= 0) {
6c3c05b0 2013 size_t size = le32_to_cpu(descs[i].size) * NVME_CTRL_PAGE_SIZE;
87ad72a5 2014
cc667f6d
LD		 2015 dma_free_attrs(dev->dev, size, bufs[i],
2016 le64_to_cpu(descs[i].addr),
2017 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
87ad72a5
CH		 2018 }
2019
2020 kfree(bufs);
2021out_free_descs:
4033f35d
CH		 2022 dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
2023 descs_dma);
87ad72a5 2024out:
87ad72a5
CH		 2025 dev->host_mem_descs = NULL;
2026 return -ENOMEM;
2027}
2028
92dc6895
CH		 2029static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
2030{
9dc54a0d
CK		 2031 u64 min_chunk = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
2032 u64 hmminds = max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
2033 u64 chunk_size;
92dc6895
CH		 2034
2035 /* start big and work our way down */
9dc54a0d 2036 for (chunk_size = min_chunk; chunk_size >= hmminds; chunk_size /= 2) {
92dc6895
CH		 2037 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
2038 if (!min || dev->host_mem_size >= min)
2039 return 0;
2040 nvme_free_host_mem(dev);
2041 }
2042 }
2043
2044 return -ENOMEM;
2045}
2046
9620cfba 2047static int nvme_setup_host_mem(struct nvme_dev *dev)
87ad72a5
CH		 2048{
2049 u64 max = (u64)max_host_mem_size_mb * SZ_1M;
2050 u64 preferred = (u64)dev->ctrl.hmpre * 4096;
2051 u64 min = (u64)dev->ctrl.hmmin * 4096;
2052 u32 enable_bits = NVME_HOST_MEM_ENABLE;
6fbcde66 2053 int ret;
87ad72a5
CH		 2054
2055 preferred = min(preferred, max);
2056 if (min > max) {
2057 dev_warn(dev->ctrl.device,
2058 "min host memory (%lld MiB) above limit (%d MiB).\n",
2059 min >> ilog2(SZ_1M), max_host_mem_size_mb);
2060 nvme_free_host_mem(dev);
9620cfba 2061 return 0;
87ad72a5
CH		 2062 }
2063
2064 /*
2065 * If we already have a buffer allocated check if we can reuse it.
2066 */
2067 if (dev->host_mem_descs) {
2068 if (dev->host_mem_size >= min)
2069 enable_bits |= NVME_HOST_MEM_RETURN;
2070 else
2071 nvme_free_host_mem(dev);
2072 }
2073
2074 if (!dev->host_mem_descs) {
92dc6895
CH		 2075 if (nvme_alloc_host_mem(dev, min, preferred)) {
2076 dev_warn(dev->ctrl.device,
2077 "failed to allocate host memory buffer.\n");
9620cfba 2078 return 0; /* controller must work without HMB */
92dc6895
CH		 2079 }
2080
2081 dev_info(dev->ctrl.device,
2082 "allocated %lld MiB host memory buffer.\n",
2083 dev->host_mem_size >> ilog2(SZ_1M));
87ad72a5
CH		 2084 }
2085
9620cfba
CH		 2086 ret = nvme_set_host_mem(dev, enable_bits);
2087 if (ret)
87ad72a5 2088 nvme_free_host_mem(dev);
9620cfba 2089 return ret;
9d713c2b
KB		 2090}
2091
0521905e
KB		 2092static ssize_t cmb_show(struct device *dev, struct device_attribute *attr,
2093 char *buf)
2094{
2095 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2096
2097 return sysfs_emit(buf, "cmbloc : x%08x\ncmbsz : x%08x\n",
2098 ndev->cmbloc, ndev->cmbsz);
2099}
2100static DEVICE_ATTR_RO(cmb);
2101
1751e97a
KB		 2102static ssize_t cmbloc_show(struct device *dev, struct device_attribute *attr,
2103 char *buf)
2104{
2105 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2106
2107 return sysfs_emit(buf, "%u\n", ndev->cmbloc);
2108}
2109static DEVICE_ATTR_RO(cmbloc);
2110
2111static ssize_t cmbsz_show(struct device *dev, struct device_attribute *attr,
2112 char *buf)
2113{
2114 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2115
2116 return sysfs_emit(buf, "%u\n", ndev->cmbsz);
2117}
2118static DEVICE_ATTR_RO(cmbsz);
2119
a5df5e79
KB		 2120static ssize_t hmb_show(struct device *dev, struct device_attribute *attr,
2121 char *buf)
2122{
2123 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2124
2125 return sysfs_emit(buf, "%d\n", ndev->hmb);
2126}
2127
2128static ssize_t hmb_store(struct device *dev, struct device_attribute *attr,
2129 const char *buf, size_t count)
2130{
2131 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2132 bool new;
2133 int ret;
2134
2135 if (strtobool(buf, &new) < 0)
2136 return -EINVAL;
2137
2138 if (new == ndev->hmb)
2139 return count;
2140
2141 if (new) {
2142 ret = nvme_setup_host_mem(ndev);
2143 } else {
2144 ret = nvme_set_host_mem(ndev, 0);
2145 if (!ret)
2146 nvme_free_host_mem(ndev);
2147 }
2148
2149 if (ret < 0)
2150 return ret;
2151
2152 return count;
2153}
2154static DEVICE_ATTR_RW(hmb);
2155
0521905e
KB		 2156static umode_t nvme_pci_attrs_are_visible(struct kobject *kobj,
2157 struct attribute *a, int n)
2158{
2159 struct nvme_ctrl *ctrl =
2160 dev_get_drvdata(container_of(kobj, struct device, kobj));
2161 struct nvme_dev *dev = to_nvme_dev(ctrl);
2162
1751e97a
KB		 2163 if (a == &dev_attr_cmb.attr ||
2164 a == &dev_attr_cmbloc.attr ||
2165 a == &dev_attr_cmbsz.attr) {
2166 if (!dev->cmbsz)
2167 return 0;
2168 }
a5df5e79
KB		 2169 if (a == &dev_attr_hmb.attr && !ctrl->hmpre)
2170 return 0;
2171
0521905e
KB		 2172 return a->mode;
2173}
2174
2175static struct attribute *nvme_pci_attrs[] = {
2176 &dev_attr_cmb.attr,
1751e97a
KB		 2177 &dev_attr_cmbloc.attr,
2178 &dev_attr_cmbsz.attr,
a5df5e79 2179 &dev_attr_hmb.attr,
0521905e
KB		 2180 NULL,
2181};
2182
2183static const struct attribute_group nvme_pci_attr_group = {
2184 .attrs = nvme_pci_attrs,
2185 .is_visible = nvme_pci_attrs_are_visible,
2186};
2187
612b7286
ML		 2188/*
2189 * nirqs is the number of interrupts available for write and read
2190 * queues. The core already reserved an interrupt for the admin queue.
2191 */
2192static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs)
3b6592f7 2193{
612b7286 2194 struct nvme_dev *dev = affd->priv;
2a5bcfdd 2195 unsigned int nr_read_queues, nr_write_queues = dev->nr_write_queues;
3b6592f7
JA		 2196
2197 /*
ee0d96d3 2198 * If there is no interrupt available for queues, ensure that
612b7286
ML		 2199 * the default queue is set to 1. The affinity set size is
2200 * also set to one, but the irq core ignores it for this case.
2201 *
2202 * If only one interrupt is available or 'write_queue' == 0, combine
2203 * write and read queues.
2204 *
2205 * If 'write_queues' > 0, ensure it leaves room for at least one read
2206 * queue.
3b6592f7 2207 */
612b7286
ML		 2208 if (!nrirqs) {
2209 nrirqs = 1;
2210 nr_read_queues = 0;
2a5bcfdd 2211 } else if (nrirqs == 1 || !nr_write_queues) {
612b7286 2212 nr_read_queues = 0;
2a5bcfdd 2213 } else if (nr_write_queues >= nrirqs) {
612b7286 2214 nr_read_queues = 1;
3b6592f7 2215 } else {
2a5bcfdd 2216 nr_read_queues = nrirqs - nr_write_queues;
3b6592f7 2217 }
612b7286
ML		 2218
2219 dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2220 affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2221 dev->io_queues[HCTX_TYPE_READ] = nr_read_queues;
2222 affd->set_size[HCTX_TYPE_READ] = nr_read_queues;
2223 affd->nr_sets = nr_read_queues ? 2 : 1;
3b6592f7
JA		 2224}
2225
6451fe73 2226static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues)
3b6592f7
JA		 2227{
2228 struct pci_dev *pdev = to_pci_dev(dev->dev);
3b6592f7 2229 struct irq_affinity affd = {
9cfef55b 2230 .pre_vectors = 1,
612b7286
ML		 2231 .calc_sets = nvme_calc_irq_sets,
2232 .priv = dev,
3b6592f7 2233 };
21cc2f3f 2234 unsigned int irq_queues, poll_queues;
6451fe73
JA		 2235
2236 /*
21cc2f3f
JX		 2237 * Poll queues don't need interrupts, but we need at least one I/O queue
2238 * left over for non-polled I/O.
6451fe73 2239 */
21cc2f3f
JX		 2240 poll_queues = min(dev->nr_poll_queues, nr_io_queues - 1);
2241 dev->io_queues[HCTX_TYPE_POLL] = poll_queues;
3b6592f7 2242
21cc2f3f
JX		 2243 /*
2244 * Initialize for the single interrupt case, will be updated in
2245 * nvme_calc_irq_sets().
2246 */
612b7286
ML		 2247 dev->io_queues[HCTX_TYPE_DEFAULT] = 1;
2248 dev->io_queues[HCTX_TYPE_READ] = 0;
3b6592f7 2249
66341331 2250 /*
21cc2f3f
JX		 2251 * We need interrupts for the admin queue and each non-polled I/O queue,
2252 * but some Apple controllers require all queues to use the first
2253 * vector.
66341331 2254 */
21cc2f3f
JX		 2255 irq_queues = 1;
2256 if (!(dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR))
2257 irq_queues += (nr_io_queues - poll_queues);
612b7286
ML		 2258 return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues,
2259 PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd);
3b6592f7
JA		 2260}
2261
8fae268b
KB		 2262static void nvme_disable_io_queues(struct nvme_dev *dev)
2263{
2264 if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq))
2265 __nvme_disable_io_queues(dev, nvme_admin_delete_cq);
2266}
2267
2a5bcfdd
WZ		 2268static unsigned int nvme_max_io_queues(struct nvme_dev *dev)
2269{
e3aef095
NS		 2270 /*
2271 * If tags are shared with admin queue (Apple bug), then
2272 * make sure we only use one IO queue.
2273 */
2274 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2275 return 1;
2a5bcfdd
WZ		 2276 return num_possible_cpus() + dev->nr_write_queues + dev->nr_poll_queues;
2277}
2278
8d85fce7 2279static int nvme_setup_io_queues(struct nvme_dev *dev)
b60503ba 2280{
147b27e4 2281 struct nvme_queue *adminq = &dev->queues[0];
e75ec752 2282 struct pci_dev *pdev = to_pci_dev(dev->dev);
2a5bcfdd 2283 unsigned int nr_io_queues;
97f6ef64 2284 unsigned long size;
2a5bcfdd 2285 int result;
b60503ba 2286
2a5bcfdd
WZ		 2287 /*
2288 * Sample the module parameters once at reset time so that we have
2289 * stable values to work with.
2290 */
2291 dev->nr_write_queues = write_queues;
2292 dev->nr_poll_queues = poll_queues;
d38e9f04 2293
e3aef095 2294 nr_io_queues = dev->nr_allocated_queues - 1;
9a0be7ab
CH		 2295 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
2296 if (result < 0)
1b23484b 2297 return result;
9a0be7ab 2298
f5fa90dc 2299 if (nr_io_queues == 0)
a5229050 2300 return 0;
53dc180e 2301
e4b9852a
CC		 2302 /*
2303 * Free IRQ resources as soon as NVMEQ_ENABLED bit transitions
2304 * from set to unset. If there is a window to it is truely freed,
2305 * pci_free_irq_vectors() jumping into this window will crash.
2306 * And take lock to avoid racing with pci_free_irq_vectors() in
2307 * nvme_dev_disable() path.
2308 */
2309 result = nvme_setup_io_queues_trylock(dev);
2310 if (result)
2311 return result;
2312 if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags))
2313 pci_free_irq(pdev, 0, adminq);
b60503ba 2314
0f238ff5 2315 if (dev->cmb_use_sqes) {
8ffaadf7
JD		 2316 result = nvme_cmb_qdepth(dev, nr_io_queues,
2317 sizeof(struct nvme_command));
2318 if (result > 0)
2319 dev->q_depth = result;
2320 else
0f238ff5 2321 dev->cmb_use_sqes = false;
8ffaadf7
JD		 2322 }
2323
97f6ef64
XY		 2324 do {
2325 size = db_bar_size(dev, nr_io_queues);
2326 result = nvme_remap_bar(dev, size);
2327 if (!result)
2328 break;
e4b9852a
CC		 2329 if (!--nr_io_queues) {
2330 result = -ENOMEM;
2331 goto out_unlock;
2332 }
97f6ef64
XY		 2333 } while (1);
2334 adminq->q_db = dev->dbs;
f1938f6e 2335
8fae268b 2336 retry:
9d713c2b 2337 /* Deregister the admin queue's interrupt */
e4b9852a
CC		 2338 if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags))
2339 pci_free_irq(pdev, 0, adminq);
9d713c2b 2340
e32efbfc
JA		 2341 /*
2342 * If we enable msix early due to not intx, disable it again before
2343 * setting up the full range we need.
2344 */
dca51e78 2345 pci_free_irq_vectors(pdev);
3b6592f7
JA		 2346
2347 result = nvme_setup_irqs(dev, nr_io_queues);
e4b9852a
CC		 2348 if (result <= 0) {
2349 result = -EIO;
2350 goto out_unlock;
2351 }
3b6592f7 2352
22b55601 2353 dev->num_vecs = result;
4b04cc6a 2354 result = max(result - 1, 1);
e20ba6e1 2355 dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL];
fa08a396 2356
063a8096
MW		 2357 /*
2358 * Should investigate if there's a performance win from allocating
2359 * more queues than interrupt vectors; it might allow the submission
2360 * path to scale better, even if the receive path is limited by the
2361 * number of interrupts.
2362 */
dca51e78 2363 result = queue_request_irq(adminq);
7c349dde 2364 if (result)
e4b9852a 2365 goto out_unlock;
4e224106 2366 set_bit(NVMEQ_ENABLED, &adminq->flags);
e4b9852a 2367 mutex_unlock(&dev->shutdown_lock);
8fae268b
KB		 2368
2369 result = nvme_create_io_queues(dev);
2370 if (result || dev->online_queues < 2)
2371 return result;
2372
2373 if (dev->online_queues - 1 < dev->max_qid) {
2374 nr_io_queues = dev->online_queues - 1;
2375 nvme_disable_io_queues(dev);
e4b9852a
CC		 2376 result = nvme_setup_io_queues_trylock(dev);
2377 if (result)
2378 return result;
8fae268b
KB		 2379 nvme_suspend_io_queues(dev);
2380 goto retry;
2381 }
2382 dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n",
2383 dev->io_queues[HCTX_TYPE_DEFAULT],
2384 dev->io_queues[HCTX_TYPE_READ],
2385 dev->io_queues[HCTX_TYPE_POLL]);
2386 return 0;
e4b9852a
CC		 2387out_unlock:
2388 mutex_unlock(&dev->shutdown_lock);
2389 return result;
b60503ba
MW		 2390}
2391
2a842aca 2392static void nvme_del_queue_end(struct request *req, blk_status_t error)
a5768aa8 2393{
db3cbfff 2394 struct nvme_queue *nvmeq = req->end_io_data;
b5875222 2395
db3cbfff 2396 blk_mq_free_request(req);
d1ed6aa1 2397 complete(&nvmeq->delete_done);
a5768aa8
KB		 2398}
2399
2a842aca 2400static void nvme_del_cq_end(struct request *req, blk_status_t error)
a5768aa8 2401{
db3cbfff 2402 struct nvme_queue *nvmeq = req->end_io_data;
a5768aa8 2403
d1ed6aa1
CH		 2404 if (error)
2405 set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
db3cbfff
KB		 2406
2407 nvme_del_queue_end(req, error);
a5768aa8
KB		 2408}
2409
db3cbfff 2410static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
bda4e0fb 2411{
db3cbfff
KB		 2412 struct request_queue *q = nvmeq->dev->ctrl.admin_q;
2413 struct request *req;
f66e2804 2414 struct nvme_command cmd = { };
bda4e0fb 2415
db3cbfff
KB		 2416 cmd.delete_queue.opcode = opcode;
2417 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
bda4e0fb 2418
39dfe844 2419 req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT);
db3cbfff
KB		 2420 if (IS_ERR(req))
2421 return PTR_ERR(req);
bda4e0fb 2422
db3cbfff
KB		 2423 req->end_io_data = nvmeq;
2424
d1ed6aa1 2425 init_completion(&nvmeq->delete_done);
b84ba30b
CH		 2426 blk_execute_rq_nowait(req, false, opcode == nvme_admin_delete_cq ?
2427 nvme_del_cq_end : nvme_del_queue_end);
db3cbfff 2428 return 0;
bda4e0fb
KB		 2429}
2430
8fae268b 2431static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode)
a5768aa8 2432{
5271edd4 2433 int nr_queues = dev->online_queues - 1, sent = 0;
db3cbfff 2434 unsigned long timeout;
a5768aa8 2435
db3cbfff 2436 retry:
dc96f938 2437 timeout = NVME_ADMIN_TIMEOUT;
5271edd4
CH		 2438 while (nr_queues > 0) {
2439 if (nvme_delete_queue(&dev->queues[nr_queues], opcode))
2440 break;
2441 nr_queues--;
2442 sent++;
db3cbfff 2443 }
d1ed6aa1
CH		 2444 while (sent) {
2445 struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent];
2446
2447 timeout = wait_for_completion_io_timeout(&nvmeq->delete_done,
5271edd4
CH		 2448 timeout);
2449 if (timeout == 0)
2450 return false;
d1ed6aa1 2451
d1ed6aa1 2452 sent--;
5271edd4
CH		 2453 if (nr_queues)
2454 goto retry;
2455 }
2456 return true;
a5768aa8
KB		 2457}
2458
5d02a5c1 2459static void nvme_dev_add(struct nvme_dev *dev)
b60503ba 2460{
2b1b7e78
JW		 2461 int ret;
2462
5bae7f73 2463 if (!dev->ctrl.tagset) {
376f7ef8 2464 dev->tagset.ops = &nvme_mq_ops;
ffe7704d 2465 dev->tagset.nr_hw_queues = dev->online_queues - 1;
8fe34be1 2466 dev->tagset.nr_maps = 2; /* default + read */
ed92ad37
CH		 2467 if (dev->io_queues[HCTX_TYPE_POLL])
2468 dev->tagset.nr_maps++;
ffe7704d 2469 dev->tagset.timeout = NVME_IO_TIMEOUT;
d4ec47f1 2470 dev->tagset.numa_node = dev->ctrl.numa_node;
61f3b896
CK		 2471 dev->tagset.queue_depth = min_t(unsigned int, dev->q_depth,
2472 BLK_MQ_MAX_DEPTH) - 1;
d43f1ccf 2473 dev->tagset.cmd_size = sizeof(struct nvme_iod);
ffe7704d
KB		 2474 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2475 dev->tagset.driver_data = dev;
b60503ba 2476
d38e9f04
BH		 2477 /*
2478 * Some Apple controllers requires tags to be unique
2479 * across admin and IO queue, so reserve the first 32
2480 * tags of the IO queue.
2481 */
2482 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2483 dev->tagset.reserved_tags = NVME_AQ_DEPTH;
2484
2b1b7e78
JW		 2485 ret = blk_mq_alloc_tag_set(&dev->tagset);
2486 if (ret) {
2487 dev_warn(dev->ctrl.device,
2488 "IO queues tagset allocation failed %d\n", ret);
5d02a5c1 2489 return;
2b1b7e78 2490 }
5bae7f73 2491 dev->ctrl.tagset = &dev->tagset;
949928c1
KB		 2492 } else {
2493 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2494
2495 /* Free previously allocated queues that are no longer usable */
2496 nvme_free_queues(dev, dev->online_queues);
ffe7704d 2497 }
949928c1 2498
e8fd41bb 2499 nvme_dbbuf_set(dev);
b60503ba
MW		 2500}
2501
b00a726a 2502static int nvme_pci_enable(struct nvme_dev *dev)
0877cb0d 2503{
b00a726a 2504 int result = -ENOMEM;
e75ec752 2505 struct pci_dev *pdev = to_pci_dev(dev->dev);
4bdf2603 2506 int dma_address_bits = 64;
0877cb0d
KB		 2507
2508 if (pci_enable_device_mem(pdev))
2509 return result;
2510
0877cb0d 2511 pci_set_master(pdev);
0877cb0d 2512
4bdf2603
FS		 2513 if (dev->ctrl.quirks & NVME_QUIRK_DMA_ADDRESS_BITS_48)
2514 dma_address_bits = 48;
2515 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(dma_address_bits)))
052d0efa 2516 goto disable;
0877cb0d 2517
7a67cbea 2518 if (readl(dev->bar + NVME_REG_CSTS) == -1) {
0e53d180 2519 result = -ENODEV;
b00a726a 2520 goto disable;
0e53d180 2521 }
e32efbfc
JA		 2522
2523 /*
a5229050
KB		 2524 * Some devices and/or platforms don't advertise or work with INTx
2525 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2526 * adjust this later.
e32efbfc 2527 */
dca51e78
CH		 2528 result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
2529 if (result < 0)
2530 return result;
e32efbfc 2531
20d0dfe6 2532 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
7a67cbea 2533
7442ddce 2534 dev->q_depth = min_t(u32, NVME_CAP_MQES(dev->ctrl.cap) + 1,
b27c1e68 2535 io_queue_depth);
aa22c8e6 2536 dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */
20d0dfe6 2537 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
7a67cbea 2538 dev->dbs = dev->bar + 4096;
1f390c1f 2539
66341331
BH		 2540 /*
2541 * Some Apple controllers require a non-standard SQE size.
2542 * Interestingly they also seem to ignore the CC:IOSQES register
2543 * so we don't bother updating it here.
2544 */
2545 if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES)
2546 dev->io_sqes = 7;
2547 else
2548 dev->io_sqes = NVME_NVM_IOSQES;
1f390c1f
SG		 2549
2550 /*
2551 * Temporary fix for the Apple controller found in the MacBook8,1 and
2552 * some MacBook7,1 to avoid controller resets and data loss.
2553 */
2554 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
2555 dev->q_depth = 2;
9bdcfb10
CH		 2556 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
2557 "set queue depth=%u to work around controller resets\n",
1f390c1f 2558 dev->q_depth);
d554b5e1
MP		 2559 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2560 (pdev->device == 0xa821 || pdev->device == 0xa822) &&
20d0dfe6 2561 NVME_CAP_MQES(dev->ctrl.cap) == 0) {
d554b5e1
MP		 2562 dev->q_depth = 64;
2563 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2564 "set queue depth=%u\n", dev->q_depth);
1f390c1f
SG		 2565 }
2566
d38e9f04
BH		 2567 /*
2568 * Controllers with the shared tags quirk need the IO queue to be
2569 * big enough so that we get 32 tags for the admin queue
2570 */
2571 if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) &&
2572 (dev->q_depth < (NVME_AQ_DEPTH + 2))) {
2573 dev->q_depth = NVME_AQ_DEPTH + 2;
2574 dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n",
2575 dev->q_depth);
2576 }
2577
2578
f65efd6d 2579 nvme_map_cmb(dev);
202021c1 2580
a0a3408e
KB		 2581 pci_enable_pcie_error_reporting(pdev);
2582 pci_save_state(pdev);
0877cb0d
KB		 2583 return 0;
2584
2585 disable:
0877cb0d
KB		 2586 pci_disable_device(pdev);
2587 return result;
2588}
2589
2590static void nvme_dev_unmap(struct nvme_dev *dev)
b00a726a
KB		 2591{
2592 if (dev->bar)
2593 iounmap(dev->bar);
a1f447b3 2594 pci_release_mem_regions(to_pci_dev(dev->dev));
b00a726a
KB		 2595}
2596
2597static void nvme_pci_disable(struct nvme_dev *dev)
0877cb0d 2598{
e75ec752
CH		 2599 struct pci_dev *pdev = to_pci_dev(dev->dev);
2600
dca51e78 2601 pci_free_irq_vectors(pdev);
0877cb0d 2602
a0a3408e
KB		 2603 if (pci_is_enabled(pdev)) {
2604 pci_disable_pcie_error_reporting(pdev);
e75ec752 2605 pci_disable_device(pdev);
4d115420 2606 }
4d115420
KB		 2607}
2608
a5cdb68c 2609static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
b60503ba 2610{
e43269e6 2611 bool dead = true, freeze = false;
302ad8cc 2612 struct pci_dev *pdev = to_pci_dev(dev->dev);
22404274 2613
77bf25ea 2614 mutex_lock(&dev->shutdown_lock);
302ad8cc
KB		 2615 if (pci_is_enabled(pdev)) {
2616 u32 csts = readl(dev->bar + NVME_REG_CSTS);
2617
ebef7368 2618 if (dev->ctrl.state == NVME_CTRL_LIVE ||
e43269e6
KB		 2619 dev->ctrl.state == NVME_CTRL_RESETTING) {
2620 freeze = true;
302ad8cc 2621 nvme_start_freeze(&dev->ctrl);
e43269e6 2622 }
302ad8cc
KB		 2623 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
2624 pdev->error_state != pci_channel_io_normal);
c9d3bf88 2625 }
c21377f8 2626
302ad8cc
KB		 2627 /*
2628 * Give the controller a chance to complete all entered requests if
2629 * doing a safe shutdown.
2630 */
e43269e6
KB		 2631 if (!dead && shutdown && freeze)
2632 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
9a915a5b
JW		 2633
2634 nvme_stop_queues(&dev->ctrl);
87ad72a5 2635
64ee0ac0 2636 if (!dead && dev->ctrl.queue_count > 0) {
8fae268b 2637 nvme_disable_io_queues(dev);
a5cdb68c 2638 nvme_disable_admin_queue(dev, shutdown);
4d115420 2639 }
8fae268b
KB		 2640 nvme_suspend_io_queues(dev);
2641 nvme_suspend_queue(&dev->queues[0]);
b00a726a 2642 nvme_pci_disable(dev);
fa46c6fb 2643 nvme_reap_pending_cqes(dev);
07836e65 2644
e1958e65
ML		 2645 blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
2646 blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
622b8b68
ML		 2647 blk_mq_tagset_wait_completed_request(&dev->tagset);
2648 blk_mq_tagset_wait_completed_request(&dev->admin_tagset);
302ad8cc
KB		 2649
2650 /*
2651 * The driver will not be starting up queues again if shutting down so
2652 * must flush all entered requests to their failed completion to avoid
2653 * deadlocking blk-mq hot-cpu notifier.
2654 */
c8e9e9b7 2655 if (shutdown) {
302ad8cc 2656 nvme_start_queues(&dev->ctrl);
c8e9e9b7 2657 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q))
6ca1d902 2658 nvme_start_admin_queue(&dev->ctrl);
c8e9e9b7 2659 }
77bf25ea 2660 mutex_unlock(&dev->shutdown_lock);
b60503ba
MW		 2661}
2662
c1ac9a4b
KB		 2663static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown)
2664{
2665 if (!nvme_wait_reset(&dev->ctrl))
2666 return -EBUSY;
2667 nvme_dev_disable(dev, shutdown);
2668 return 0;
2669}
2670
091b6092
MW		 2671static int nvme_setup_prp_pools(struct nvme_dev *dev)
2672{
e75ec752 2673 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
c61b82c7
CH		 2674 NVME_CTRL_PAGE_SIZE,
2675 NVME_CTRL_PAGE_SIZE, 0);
091b6092
MW		 2676 if (!dev->prp_page_pool)
2677 return -ENOMEM;
2678
99802a7a 2679 /* Optimisation for I/Os between 4k and 128k */
e75ec752 2680 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
99802a7a
MW		 2681 256, 256, 0);
2682 if (!dev->prp_small_pool) {
2683 dma_pool_destroy(dev->prp_page_pool);
2684 return -ENOMEM;
2685 }
091b6092
MW		 2686 return 0;
2687}
2688
2689static void nvme_release_prp_pools(struct nvme_dev *dev)
2690{
2691 dma_pool_destroy(dev->prp_page_pool);
99802a7a 2692 dma_pool_destroy(dev->prp_small_pool);
091b6092
MW		 2693}
2694
770597ec
KB		 2695static void nvme_free_tagset(struct nvme_dev *dev)
2696{
2697 if (dev->tagset.tags)
2698 blk_mq_free_tag_set(&dev->tagset);
2699 dev->ctrl.tagset = NULL;
2700}
2701
1673f1f0 2702static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
5e82e952 2703{
1673f1f0 2704 struct nvme_dev *dev = to_nvme_dev(ctrl);
9ac27090 2705
f9f38e33 2706 nvme_dbbuf_dma_free(dev);
770597ec 2707 nvme_free_tagset(dev);
1c63dc66
CH		 2708 if (dev->ctrl.admin_q)
2709 blk_put_queue(dev->ctrl.admin_q);
e286bcfc 2710 free_opal_dev(dev->ctrl.opal_dev);
943e942e 2711 mempool_destroy(dev->iod_mempool);
253fd4ac
IR		 2712 put_device(dev->dev);
2713 kfree(dev->queues);
5e82e952
KB		 2714 kfree(dev);
2715}
2716
7c1ce408 2717static void nvme_remove_dead_ctrl(struct nvme_dev *dev)
f58944e2 2718{
c1ac9a4b
KB		 2719 /*
2720 * Set state to deleting now to avoid blocking nvme_wait_reset(), which
2721 * may be holding this pci_dev's device lock.
2722 */
2723 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
d22524a4 2724 nvme_get_ctrl(&dev->ctrl);
69d9a99c 2725 nvme_dev_disable(dev, false);
9f9cafc1 2726 nvme_kill_queues(&dev->ctrl);
03e0f3a6 2727 if (!queue_work(nvme_wq, &dev->remove_work))
f58944e2
KB		 2728 nvme_put_ctrl(&dev->ctrl);
2729}
2730
fd634f41 2731static void nvme_reset_work(struct work_struct *work)
5e82e952 2732{
d86c4d8e
CH		 2733 struct nvme_dev *dev =
2734 container_of(work, struct nvme_dev, ctrl.reset_work);
a98e58e5 2735 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
e71afda4 2736 int result;
5e82e952 2737
7764656b
ZC		 2738 if (dev->ctrl.state != NVME_CTRL_RESETTING) {
2739 dev_warn(dev->ctrl.device, "ctrl state %d is not RESETTING\n",
2740 dev->ctrl.state);
e71afda4 2741 result = -ENODEV;
fd634f41 2742 goto out;
e71afda4 2743 }
5e82e952 2744
fd634f41
CH		 2745 /*
2746 * If we're called to reset a live controller first shut it down before
2747 * moving on.
2748 */
b00a726a 2749 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
a5cdb68c 2750 nvme_dev_disable(dev, false);
d6135c3a 2751 nvme_sync_queues(&dev->ctrl);
5e82e952 2752
5c959d73 2753 mutex_lock(&dev->shutdown_lock);
b00a726a 2754 result = nvme_pci_enable(dev);
f0b50732 2755 if (result)
4726bcf3 2756 goto out_unlock;
f0b50732 2757
01ad0990 2758 result = nvme_pci_configure_admin_queue(dev);
f0b50732 2759 if (result)
4726bcf3 2760 goto out_unlock;
f0b50732 2761
0fb59cbc
KB		 2762 result = nvme_alloc_admin_tags(dev);
2763 if (result)
4726bcf3 2764 goto out_unlock;
b9afca3e 2765
943e942e
JA		 2766 /*
2767 * Limit the max command size to prevent iod->sg allocations going
2768 * over a single page.
2769 */
7637de31
CH		 2770 dev->ctrl.max_hw_sectors = min_t(u32,
2771 NVME_MAX_KB_SZ << 1, dma_max_mapping_size(dev->dev) >> 9);
943e942e 2772 dev->ctrl.max_segments = NVME_MAX_SEGS;
a48bc520
CH		 2773
2774 /*
2775 * Don't limit the IOMMU merged segment size.
2776 */
2777 dma_set_max_seg_size(dev->dev, 0xffffffff);
3d2d861e 2778 dma_set_min_align_mask(dev->dev, NVME_CTRL_PAGE_SIZE - 1);
a48bc520 2779
5c959d73
KB		 2780 mutex_unlock(&dev->shutdown_lock);
2781
2782 /*
2783 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
2784 * initializing procedure here.
2785 */
2786 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
2787 dev_warn(dev->ctrl.device,
2788 "failed to mark controller CONNECTING\n");
cee6c269 2789 result = -EBUSY;
5c959d73
KB		 2790 goto out;
2791 }
943e942e 2792
95093350
MG		 2793 /*
2794 * We do not support an SGL for metadata (yet), so we are limited to a
2795 * single integrity segment for the separate metadata pointer.
2796 */
2797 dev->ctrl.max_integrity_segments = 1;
2798
f21c4769 2799 result = nvme_init_ctrl_finish(&dev->ctrl);
ce4541f4 2800 if (result)
f58944e2 2801 goto out;
ce4541f4 2802
e286bcfc
SB		 2803 if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
2804 if (!dev->ctrl.opal_dev)
2805 dev->ctrl.opal_dev =
2806 init_opal_dev(&dev->ctrl, &nvme_sec_submit);
2807 else if (was_suspend)
2808 opal_unlock_from_suspend(dev->ctrl.opal_dev);
2809 } else {
2810 free_opal_dev(dev->ctrl.opal_dev);
2811 dev->ctrl.opal_dev = NULL;
4f1244c8 2812 }
a98e58e5 2813
f9f38e33
HK		 2814 if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) {
2815 result = nvme_dbbuf_dma_alloc(dev);
2816 if (result)
2817 dev_warn(dev->dev,
2818 "unable to allocate dma for dbbuf\n");
2819 }
2820
9620cfba
CH		 2821 if (dev->ctrl.hmpre) {
2822 result = nvme_setup_host_mem(dev);
2823 if (result < 0)
2824 goto out;
2825 }
87ad72a5 2826
f0b50732 2827 result = nvme_setup_io_queues(dev);
badc34d4 2828 if (result)
f58944e2 2829 goto out;
f0b50732 2830
2659e57b
CH		 2831 /*
2832 * Keep the controller around but remove all namespaces if we don't have
2833 * any working I/O queue.
2834 */
3cf519b5 2835 if (dev->online_queues < 2) {
1b3c47c1 2836 dev_warn(dev->ctrl.device, "IO queues not created\n");
3b24774e 2837 nvme_kill_queues(&dev->ctrl);
5bae7f73 2838 nvme_remove_namespaces(&dev->ctrl);
770597ec 2839 nvme_free_tagset(dev);
3cf519b5 2840 } else {
25646264 2841 nvme_start_queues(&dev->ctrl);
302ad8cc 2842 nvme_wait_freeze(&dev->ctrl);
5d02a5c1 2843 nvme_dev_add(dev);
302ad8cc 2844 nvme_unfreeze(&dev->ctrl);
3cf519b5
CH		 2845 }
2846
2b1b7e78
JW		 2847 /*
2848 * If only admin queue live, keep it to do further investigation or
2849 * recovery.
2850 */
5d02a5c1 2851 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
2b1b7e78 2852 dev_warn(dev->ctrl.device,
5d02a5c1 2853 "failed to mark controller live state\n");
e71afda4 2854 result = -ENODEV;
bb8d261e
CH		 2855 goto out;
2856 }
92911a55 2857
0521905e
KB		 2858 if (!dev->attrs_added && !sysfs_create_group(&dev->ctrl.device->kobj,
2859 &nvme_pci_attr_group))
2860 dev->attrs_added = true;
2861
d09f2b45 2862 nvme_start_ctrl(&dev->ctrl);
3cf519b5 2863 return;
f0b50732 2864
4726bcf3
KB		 2865 out_unlock:
2866 mutex_unlock(&dev->shutdown_lock);
3cf519b5 2867 out:
7c1ce408
CK		 2868 if (result)
2869 dev_warn(dev->ctrl.device,
2870 "Removing after probe failure status: %d\n", result);
2871 nvme_remove_dead_ctrl(dev);
f0b50732
KB		 2872}
2873
5c8809e6 2874static void nvme_remove_dead_ctrl_work(struct work_struct *work)
9a6b9458 2875{
5c8809e6 2876 struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
e75ec752 2877 struct pci_dev *pdev = to_pci_dev(dev->dev);
9a6b9458
KB		 2878
2879 if (pci_get_drvdata(pdev))
921920ab 2880 device_release_driver(&pdev->dev);
1673f1f0 2881 nvme_put_ctrl(&dev->ctrl);
9a6b9458
KB		 2882}
2883
1c63dc66 2884static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
9ca97374 2885{
1c63dc66 2886 *val = readl(to_nvme_dev(ctrl)->bar + off);
90667892 2887 return 0;
9ca97374
TH		 2888}
2889
5fd4ce1b 2890static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
4cc06521 2891{
5fd4ce1b
CH		 2892 writel(val, to_nvme_dev(ctrl)->bar + off);
2893 return 0;
2894}
4cc06521 2895
7fd8930f
CH		 2896static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2897{
3a8ecc93 2898 *val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off);
7fd8930f 2899 return 0;
4cc06521
KB		 2900}
2901
97c12223
KB		 2902static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
2903{
2904 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2905
2db24e4a 2906 return snprintf(buf, size, "%s\n", dev_name(&pdev->dev));
97c12223
KB		 2907}
2908
1c63dc66 2909static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
1a353d85 2910 .name = "pcie",
e439bb12 2911 .module = THIS_MODULE,
e0596ab2
LG		 2912 .flags = NVME_F_METADATA_SUPPORTED |
2913 NVME_F_PCI_P2PDMA,
1c63dc66 2914 .reg_read32 = nvme_pci_reg_read32,
5fd4ce1b 2915 .reg_write32 = nvme_pci_reg_write32,
7fd8930f 2916 .reg_read64 = nvme_pci_reg_read64,
1673f1f0 2917 .free_ctrl = nvme_pci_free_ctrl,
f866fc42 2918 .submit_async_event = nvme_pci_submit_async_event,
97c12223 2919 .get_address = nvme_pci_get_address,
1c63dc66 2920};
4cc06521 2921
b00a726a
KB		 2922static int nvme_dev_map(struct nvme_dev *dev)
2923{
b00a726a
KB		 2924 struct pci_dev *pdev = to_pci_dev(dev->dev);
2925
a1f447b3 2926 if (pci_request_mem_regions(pdev, "nvme"))
b00a726a
KB		 2927 return -ENODEV;
2928
97f6ef64 2929 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
b00a726a
KB		 2930 goto release;
2931
9fa196e7 2932 return 0;
b00a726a 2933 release:
9fa196e7
MG		 2934 pci_release_mem_regions(pdev);
2935 return -ENODEV;
b00a726a
KB		 2936}
2937
8427bbc2 2938static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
ff5350a8
AL		 2939{
2940 if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
2941 /*
2942 * Several Samsung devices seem to drop off the PCIe bus
2943 * randomly when APST is on and uses the deepest sleep state.
2944 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2945 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2946 * 950 PRO 256GB", but it seems to be restricted to two Dell
2947 * laptops.
2948 */
2949 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
2950 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
2951 dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
2952 return NVME_QUIRK_NO_DEEPEST_PS;
8427bbc2
KHF		 2953 } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
2954 /*
2955 * Samsung SSD 960 EVO drops off the PCIe bus after system
467c77d4
JJ		 2956 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
2957 * within few minutes after bootup on a Coffee Lake board -
2958 * ASUS PRIME Z370-A
8427bbc2
KHF		 2959 */
2960 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
467c77d4
JJ		 2961 (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") ||
2962 dmi_match(DMI_BOARD_NAME, "PRIME Z370-A")))
8427bbc2 2963 return NVME_QUIRK_NO_APST;
1fae37ac
S		 2964 } else if ((pdev->vendor == 0x144d && (pdev->device == 0xa801 ||
2965 pdev->device == 0xa808 || pdev->device == 0xa809)) ||
2966 (pdev->vendor == 0x1e0f && pdev->device == 0x0001)) {
2967 /*
2968 * Forcing to use host managed nvme power settings for
2969 * lowest idle power with quick resume latency on
2970 * Samsung and Toshiba SSDs based on suspend behavior
2971 * on Coffee Lake board for LENOVO C640
2972 */
2973 if ((dmi_match(DMI_BOARD_VENDOR, "LENOVO")) &&
2974 dmi_match(DMI_BOARD_NAME, "LNVNB161216"))
2975 return NVME_QUIRK_SIMPLE_SUSPEND;
ff5350a8
AL		 2976 }
2977
2978 return 0;
2979}
2980
18119775
KB		 2981static void nvme_async_probe(void *data, async_cookie_t cookie)
2982{
2983 struct nvme_dev *dev = data;
80f513b5 2984
bd46a906 2985 flush_work(&dev->ctrl.reset_work);
18119775 2986 flush_work(&dev->ctrl.scan_work);
80f513b5 2987 nvme_put_ctrl(&dev->ctrl);
18119775
KB		 2988}
2989
8d85fce7 2990static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
b60503ba 2991{
a4aea562 2992 int node, result = -ENOMEM;
b60503ba 2993 struct nvme_dev *dev;
ff5350a8 2994 unsigned long quirks = id->driver_data;
943e942e 2995 size_t alloc_size;
b60503ba 2996
a4aea562
MB		 2997 node = dev_to_node(&pdev->dev);
2998 if (node == NUMA_NO_NODE)
2fa84351 2999 set_dev_node(&pdev->dev, first_memory_node);
a4aea562
MB		 3000
3001 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
b60503ba
MW		 3002 if (!dev)
3003 return -ENOMEM;
147b27e4 3004
2a5bcfdd
WZ		 3005 dev->nr_write_queues = write_queues;
3006 dev->nr_poll_queues = poll_queues;
3007 dev->nr_allocated_queues = nvme_max_io_queues(dev) + 1;
3008 dev->queues = kcalloc_node(dev->nr_allocated_queues,
3009 sizeof(struct nvme_queue), GFP_KERNEL, node);
b60503ba
MW		 3010 if (!dev->queues)
3011 goto free;
3012
e75ec752 3013 dev->dev = get_device(&pdev->dev);
9a6b9458 3014 pci_set_drvdata(pdev, dev);
1c63dc66 3015
b00a726a
KB		 3016 result = nvme_dev_map(dev);
3017 if (result)
b00c9b7a 3018 goto put_pci;
b00a726a 3019
d86c4d8e 3020 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
5c8809e6 3021 INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
77bf25ea 3022 mutex_init(&dev->shutdown_lock);
b60503ba 3023
091b6092
MW		 3024 result = nvme_setup_prp_pools(dev);
3025 if (result)
b00c9b7a 3026 goto unmap;
4cc06521 3027
8427bbc2 3028 quirks |= check_vendor_combination_bug(pdev);
ff5350a8 3029
2744d7a0 3030 if (!noacpi && acpi_storage_d3(&pdev->dev)) {
df4f9bc4
DB		 3031 /*
3032 * Some systems use a bios work around to ask for D3 on
3033 * platforms that support kernel managed suspend.
3034 */
3035 dev_info(&pdev->dev,
3036 "platform quirk: setting simple suspend\n");
3037 quirks |= NVME_QUIRK_SIMPLE_SUSPEND;
3038 }
3039
943e942e
JA		 3040 /*
3041 * Double check that our mempool alloc size will cover the biggest
3042 * command we support.
3043 */
b13c6393 3044 alloc_size = nvme_pci_iod_alloc_size();
943e942e
JA		 3045 WARN_ON_ONCE(alloc_size > PAGE_SIZE);
3046
3047 dev->iod_mempool = mempool_create_node(1, mempool_kmalloc,
3048 mempool_kfree,
3049 (void *) alloc_size,
3050 GFP_KERNEL, node);
3051 if (!dev->iod_mempool) {
3052 result = -ENOMEM;
3053 goto release_pools;
3054 }
3055
b6e44b4c
KB		 3056 result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
3057 quirks);
3058 if (result)
3059 goto release_mempool;
3060
1b3c47c1
SG		 3061 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
3062
bd46a906 3063 nvme_reset_ctrl(&dev->ctrl);
18119775 3064 async_schedule(nvme_async_probe, dev);
4caff8fc 3065
b60503ba
MW		 3066 return 0;
3067
b6e44b4c
KB		 3068 release_mempool:
3069 mempool_destroy(dev->iod_mempool);
0877cb0d 3070 release_pools:
091b6092 3071 nvme_release_prp_pools(dev);
b00c9b7a
CJ		 3072 unmap:
3073 nvme_dev_unmap(dev);
a96d4f5c 3074 put_pci:
e75ec752 3075 put_device(dev->dev);
b60503ba
MW		 3076 free:
3077 kfree(dev->queues);
b60503ba
MW		 3078 kfree(dev);
3079 return result;
3080}
3081
775755ed 3082static void nvme_reset_prepare(struct pci_dev *pdev)
f0d54a54 3083{
a6739479 3084 struct nvme_dev *dev = pci_get_drvdata(pdev);
c1ac9a4b
KB		 3085
3086 /*
3087 * We don't need to check the return value from waiting for the reset
3088 * state as pci_dev device lock is held, making it impossible to race
3089 * with ->remove().
3090 */
3091 nvme_disable_prepare_reset(dev, false);
3092 nvme_sync_queues(&dev->ctrl);
775755ed 3093}
f0d54a54 3094
775755ed
CH		 3095static void nvme_reset_done(struct pci_dev *pdev)
3096{
f263fbb8 3097 struct nvme_dev *dev = pci_get_drvdata(pdev);
c1ac9a4b
KB		 3098
3099 if (!nvme_try_sched_reset(&dev->ctrl))
3100 flush_work(&dev->ctrl.reset_work);
f0d54a54
KB		 3101}
3102
09ece142
KB		 3103static void nvme_shutdown(struct pci_dev *pdev)
3104{
3105 struct nvme_dev *dev = pci_get_drvdata(pdev);
4e523547 3106
c1ac9a4b 3107 nvme_disable_prepare_reset(dev, true);
09ece142
KB		 3108}
3109
0521905e
KB		 3110static void nvme_remove_attrs(struct nvme_dev *dev)
3111{
3112 if (dev->attrs_added)
3113 sysfs_remove_group(&dev->ctrl.device->kobj,
3114 &nvme_pci_attr_group);
3115}
3116
f58944e2
KB		 3117/*
3118 * The driver's remove may be called on a device in a partially initialized
3119 * state. This function must not have any dependencies on the device state in
3120 * order to proceed.
3121 */
8d85fce7 3122static void nvme_remove(struct pci_dev *pdev)
b60503ba
MW		 3123{
3124 struct nvme_dev *dev = pci_get_drvdata(pdev);
9a6b9458 3125
bb8d261e 3126 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
9a6b9458 3127 pci_set_drvdata(pdev, NULL);
0ff9d4e1 3128
6db28eda 3129 if (!pci_device_is_present(pdev)) {
0ff9d4e1 3130 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
1d39e692 3131 nvme_dev_disable(dev, true);
6db28eda 3132 }
0ff9d4e1 3133
d86c4d8e 3134 flush_work(&dev->ctrl.reset_work);
d09f2b45
SG		 3135 nvme_stop_ctrl(&dev->ctrl);
3136 nvme_remove_namespaces(&dev->ctrl);
a5cdb68c 3137 nvme_dev_disable(dev, true);
0521905e 3138 nvme_remove_attrs(dev);
87ad72a5 3139 nvme_free_host_mem(dev);
a4aea562 3140 nvme_dev_remove_admin(dev);
a1a5ef99 3141 nvme_free_queues(dev, 0);
9a6b9458 3142 nvme_release_prp_pools(dev);
b00a726a 3143 nvme_dev_unmap(dev);
726612b6 3144 nvme_uninit_ctrl(&dev->ctrl);
b60503ba
MW		 3145}
3146
671a6018 3147#ifdef CONFIG_PM_SLEEP
d916b1be
KB		 3148static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps)
3149{
3150 return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps);
3151}
3152
3153static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps)
3154{
3155 return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL);
3156}
3157
3158static int nvme_resume(struct device *dev)
3159{
3160 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
3161 struct nvme_ctrl *ctrl = &ndev->ctrl;
3162
4eaefe8c 3163 if (ndev->last_ps == U32_MAX ||
d916b1be 3164 nvme_set_power_state(ctrl, ndev->last_ps) != 0)
e5ad96f3
KB		 3165 goto reset;
3166 if (ctrl->hmpre && nvme_setup_host_mem(ndev))
3167 goto reset;
3168
d916b1be 3169 return 0;
e5ad96f3
KB		 3170reset:
3171 return nvme_try_sched_reset(ctrl);
d916b1be
KB		 3172}
3173
cd638946
KB		 3174static int nvme_suspend(struct device *dev)
3175{
3176 struct pci_dev *pdev = to_pci_dev(dev);
3177 struct nvme_dev *ndev = pci_get_drvdata(pdev);
d916b1be
KB		 3178 struct nvme_ctrl *ctrl = &ndev->ctrl;
3179 int ret = -EBUSY;
3180
4eaefe8c
RW		 3181 ndev->last_ps = U32_MAX;
3182
d916b1be
KB		 3183 /*
3184 * The platform does not remove power for a kernel managed suspend so
3185 * use host managed nvme power settings for lowest idle power if
3186 * possible. This should have quicker resume latency than a full device
3187 * shutdown. But if the firmware is involved after the suspend or the
3188 * device does not support any non-default power states, shut down the
3189 * device fully.
4eaefe8c
RW		 3190 *
3191 * If ASPM is not enabled for the device, shut down the device and allow
3192 * the PCI bus layer to put it into D3 in order to take the PCIe link
3193 * down, so as to allow the platform to achieve its minimum low-power
3194 * state (which may not be possible if the link is up).
d916b1be 3195 */
4eaefe8c 3196 if (pm_suspend_via_firmware() || !ctrl->npss ||
cb32de1b 3197 !pcie_aspm_enabled(pdev) ||
c1ac9a4b
KB		 3198 (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND))
3199 return nvme_disable_prepare_reset(ndev, true);
d916b1be
KB		 3200
3201 nvme_start_freeze(ctrl);
3202 nvme_wait_freeze(ctrl);
3203 nvme_sync_queues(ctrl);
3204
5d02a5c1 3205 if (ctrl->state != NVME_CTRL_LIVE)
d916b1be
KB		 3206 goto unfreeze;
3207
e5ad96f3
KB		 3208 /*
3209 * Host memory access may not be successful in a system suspend state,
3210 * but the specification allows the controller to access memory in a
3211 * non-operational power state.
3212 */
3213 if (ndev->hmb) {
3214 ret = nvme_set_host_mem(ndev, 0);
3215 if (ret < 0)
3216 goto unfreeze;
3217 }
3218
d916b1be
KB		 3219 ret = nvme_get_power_state(ctrl, &ndev->last_ps);
3220 if (ret < 0)
3221 goto unfreeze;
3222
7cbb5c6f
ML		 3223 /*
3224 * A saved state prevents pci pm from generically controlling the
3225 * device's power. If we're using protocol specific settings, we don't
3226 * want pci interfering.
3227 */
3228 pci_save_state(pdev);
3229
d916b1be
KB		 3230 ret = nvme_set_power_state(ctrl, ctrl->npss);
3231 if (ret < 0)
3232 goto unfreeze;
3233
3234 if (ret) {
7cbb5c6f
ML		 3235 /* discard the saved state */
3236 pci_load_saved_state(pdev, NULL);
3237
d916b1be
KB		 3238 /*
3239 * Clearing npss forces a controller reset on resume. The
05d3046f 3240 * correct value will be rediscovered then.
d916b1be 3241 */
c1ac9a4b 3242 ret = nvme_disable_prepare_reset(ndev, true);
d916b1be 3243 ctrl->npss = 0;
d916b1be 3244 }
d916b1be
KB		 3245unfreeze:
3246 nvme_unfreeze(ctrl);
3247 return ret;
3248}
3249
3250static int nvme_simple_suspend(struct device *dev)
3251{
3252 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
4e523547 3253
c1ac9a4b 3254 return nvme_disable_prepare_reset(ndev, true);
cd638946
KB		 3255}
3256
d916b1be 3257static int nvme_simple_resume(struct device *dev)
cd638946
KB		 3258{
3259 struct pci_dev *pdev = to_pci_dev(dev);
3260 struct nvme_dev *ndev = pci_get_drvdata(pdev);
cd638946 3261
c1ac9a4b 3262 return nvme_try_sched_reset(&ndev->ctrl);
cd638946
KB		 3263}
3264
21774222 3265static const struct dev_pm_ops nvme_dev_pm_ops = {
d916b1be
KB		 3266 .suspend = nvme_suspend,
3267 .resume = nvme_resume,
3268 .freeze = nvme_simple_suspend,
3269 .thaw = nvme_simple_resume,
3270 .poweroff = nvme_simple_suspend,
3271 .restore = nvme_simple_resume,
3272};
3273#endif /* CONFIG_PM_SLEEP */
b60503ba 3274
a0a3408e
KB		 3275static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
3276 pci_channel_state_t state)
3277{
3278 struct nvme_dev *dev = pci_get_drvdata(pdev);
3279
3280 /*
3281 * A frozen channel requires a reset. When detected, this method will
3282 * shutdown the controller to quiesce. The controller will be restarted
3283 * after the slot reset through driver's slot_reset callback.
3284 */
a0a3408e
KB		 3285 switch (state) {
3286 case pci_channel_io_normal:
3287 return PCI_ERS_RESULT_CAN_RECOVER;
3288 case pci_channel_io_frozen:
d011fb31
KB		 3289 dev_warn(dev->ctrl.device,
3290 "frozen state error detected, reset controller\n");
a5cdb68c 3291 nvme_dev_disable(dev, false);
a0a3408e
KB		 3292 return PCI_ERS_RESULT_NEED_RESET;
3293 case pci_channel_io_perm_failure:
d011fb31
KB		 3294 dev_warn(dev->ctrl.device,
3295 "failure state error detected, request disconnect\n");
a0a3408e
KB		 3296 return PCI_ERS_RESULT_DISCONNECT;
3297 }
3298 return PCI_ERS_RESULT_NEED_RESET;
3299}
3300
3301static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
3302{
3303 struct nvme_dev *dev = pci_get_drvdata(pdev);
3304
1b3c47c1 3305 dev_info(dev->ctrl.device, "restart after slot reset\n");
a0a3408e 3306 pci_restore_state(pdev);
d86c4d8e 3307 nvme_reset_ctrl(&dev->ctrl);
a0a3408e
KB		 3308 return PCI_ERS_RESULT_RECOVERED;
3309}
3310
3311static void nvme_error_resume(struct pci_dev *pdev)
3312{
72cd4cc2
KB		 3313 struct nvme_dev *dev = pci_get_drvdata(pdev);
3314
3315 flush_work(&dev->ctrl.reset_work);
a0a3408e
KB		 3316}
3317
1d352035 3318static const struct pci_error_handlers nvme_err_handler = {
b60503ba 3319 .error_detected = nvme_error_detected,
b60503ba
MW		 3320 .slot_reset = nvme_slot_reset,
3321 .resume = nvme_error_resume,
775755ed
CH		 3322 .reset_prepare = nvme_reset_prepare,
3323 .reset_done = nvme_reset_done,
b60503ba
MW		 3324};
3325
6eb0d698 3326static const struct pci_device_id nvme_id_table[] = {
972b13e2 3327 { PCI_VDEVICE(INTEL, 0x0953), /* Intel 750/P3500/P3600/P3700 */
08095e70 3328 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 3329 NVME_QUIRK_DEALLOCATE_ZEROES, },
972b13e2 3330 { PCI_VDEVICE(INTEL, 0x0a53), /* Intel P3520 */
99466e70 3331 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 3332 NVME_QUIRK_DEALLOCATE_ZEROES, },
972b13e2 3333 { PCI_VDEVICE(INTEL, 0x0a54), /* Intel P4500/P4600 */
99466e70 3334 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 3335 NVME_QUIRK_DEALLOCATE_ZEROES, },
972b13e2 3336 { PCI_VDEVICE(INTEL, 0x0a55), /* Dell Express Flash P4600 */
f99cb7af
DWF		 3337 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3338 NVME_QUIRK_DEALLOCATE_ZEROES, },
50af47d0 3339 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */
9abd68ef 3340 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
6c6aa2f2 3341 NVME_QUIRK_MEDIUM_PRIO_SQ |
ce4cc313
DM		 3342 NVME_QUIRK_NO_TEMP_THRESH_CHANGE |
3343 NVME_QUIRK_DISABLE_WRITE_ZEROES, },
6299358d
JD		 3344 { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */
3345 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
540c801c 3346 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */
7b210e4e
CH		 3347 .driver_data = NVME_QUIRK_IDENTIFY_CNS |
3348 NVME_QUIRK_DISABLE_WRITE_ZEROES, },
5bedd3af
CH		 3349 { PCI_DEVICE(0x126f, 0x2263), /* Silicon Motion unidentified */
3350 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST, },
0302ae60 3351 { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */
5e112d3f
JE		 3352 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
3353 NVME_QUIRK_NO_NS_DESC_LIST, },
54adc010
GP		 3354 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
3355 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
8c97eecc
JL		 3356 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */
3357 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
015282c9
WW		 3358 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
3359 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
d554b5e1
MP		 3360 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */
3361 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3362 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */
7ee5c78c 3363 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
abbb5f59 3364 NVME_QUIRK_DISABLE_WRITE_ZEROES|
7ee5c78c 3365 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
c9e95c39
CS		 3366 { PCI_DEVICE(0x1987, 0x5016), /* Phison E16 */
3367 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
6e6a6828
PT		 3368 { PCI_DEVICE(0x1b4b, 0x1092), /* Lexar 256 GB SSD */
3369 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST |
3370 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
08b903b5
MN		 3371 { PCI_DEVICE(0x10ec, 0x5762), /* ADATA SX6000LNP */
3372 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
f03e42c6
GC		 3373 { PCI_DEVICE(0x1cc1, 0x8201), /* ADATA SX8200PNP 512GB */
3374 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3375 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
5611ec2b
KHF		 3376 { PCI_DEVICE(0x1c5c, 0x1504), /* SK Hynix PC400 */
3377 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
02ca079c
KHF		 3378 { PCI_DEVICE(0x15b7, 0x2001), /* Sandisk Skyhawk */
3379 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
89919929
CK		 3380 { PCI_DEVICE(0x1d97, 0x2263), /* SPCC */
3381 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
dc22c1c0
ZB		 3382 { PCI_DEVICE(0x2646, 0x2262), /* KINGSTON SKC2000 NVMe SSD */
3383 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
538e4a8c
TL		 3384 { PCI_DEVICE(0x2646, 0x2263), /* KINGSTON A2000 NVMe SSD */
3385 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
4bdf2603
FS		 3386 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0061),
3387 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3388 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0065),
3389 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3390 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x8061),
3391 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3392 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd00),
3393 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3394 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd01),
3395 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3396 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd02),
3397 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
98f7b86a
AS		 3398 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001),
3399 .driver_data = NVME_QUIRK_SINGLE_VECTOR },
124298bd 3400 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
66341331
BH		 3401 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005),
3402 .driver_data = NVME_QUIRK_SINGLE_VECTOR |
d38e9f04 3403 NVME_QUIRK_128_BYTES_SQES |
a2941f6a
KB		 3404 NVME_QUIRK_SHARED_TAGS |
3405 NVME_QUIRK_SKIP_CID_GEN },
0b85f59d
AS		 3406
3407 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
b60503ba
MW		 3408 { 0, }
3409};
3410MODULE_DEVICE_TABLE(pci, nvme_id_table);
3411
3412static struct pci_driver nvme_driver = {
3413 .name = "nvme",
3414 .id_table = nvme_id_table,
3415 .probe = nvme_probe,
8d85fce7 3416 .remove = nvme_remove,
09ece142 3417 .shutdown = nvme_shutdown,
d916b1be 3418#ifdef CONFIG_PM_SLEEP
cd638946
KB		 3419 .driver = {
3420 .pm = &nvme_dev_pm_ops,
3421 },
d916b1be 3422#endif
74d986ab 3423 .sriov_configure = pci_sriov_configure_simple,
b60503ba
MW		 3424 .err_handler = &nvme_err_handler,
3425};
3426
3427static int __init nvme_init(void)
3428{
81101540
CH		 3429 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
3430 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
3431 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
612b7286 3432 BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2);
17c33167 3433
9a6327d2 3434 return pci_register_driver(&nvme_driver);
b60503ba
MW		 3435}
3436
3437static void __exit nvme_exit(void)
3438{
3439 pci_unregister_driver(&nvme_driver);
03e0f3a6 3440 flush_workqueue(nvme_wq);
b60503ba
MW		 3441}
3442
3443MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3444MODULE_LICENSE("GPL");
c78b4713 3445MODULE_VERSION("1.0");
b60503ba
MW		 3446module_init(nvme_init);
3447module_exit(nvme_exit);
Linux 6.x block layer and io_uring tree(s)