Commit | Line | Data |
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5f37396d | 1 | // SPDX-License-Identifier: GPL-2.0 |
b60503ba MW |
2 | /* |
3 | * NVM Express device driver | |
6eb0d698 | 4 | * Copyright (c) 2011-2014, Intel Corporation. |
b60503ba MW |
5 | */ |
6 | ||
df4f9bc4 | 7 | #include <linux/acpi.h> |
a0a3408e | 8 | #include <linux/aer.h> |
18119775 | 9 | #include <linux/async.h> |
b60503ba | 10 | #include <linux/blkdev.h> |
a4aea562 | 11 | #include <linux/blk-mq.h> |
dca51e78 | 12 | #include <linux/blk-mq-pci.h> |
fe45e630 | 13 | #include <linux/blk-integrity.h> |
ff5350a8 | 14 | #include <linux/dmi.h> |
b60503ba MW |
15 | #include <linux/init.h> |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/io.h> | |
b60503ba MW |
18 | #include <linux/mm.h> |
19 | #include <linux/module.h> | |
77bf25ea | 20 | #include <linux/mutex.h> |
d0877473 | 21 | #include <linux/once.h> |
b60503ba | 22 | #include <linux/pci.h> |
d916b1be | 23 | #include <linux/suspend.h> |
e1e5e564 | 24 | #include <linux/t10-pi.h> |
b60503ba | 25 | #include <linux/types.h> |
2f8e2c87 | 26 | #include <linux/io-64-nonatomic-lo-hi.h> |
20d3bb92 | 27 | #include <linux/io-64-nonatomic-hi-lo.h> |
a98e58e5 | 28 | #include <linux/sed-opal.h> |
0f238ff5 | 29 | #include <linux/pci-p2pdma.h> |
797a796a | 30 | |
604c01d5 | 31 | #include "trace.h" |
f11bb3e2 CH |
32 | #include "nvme.h" |
33 | ||
c1e0cc7e | 34 | #define SQ_SIZE(q) ((q)->q_depth << (q)->sqes) |
8a1d09a6 | 35 | #define CQ_SIZE(q) ((q)->q_depth * sizeof(struct nvme_completion)) |
c965809c | 36 | |
a7a7cbe3 | 37 | #define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc)) |
9d43cf64 | 38 | |
943e942e JA |
39 | /* |
40 | * These can be higher, but we need to ensure that any command doesn't | |
41 | * require an sg allocation that needs more than a page of data. | |
42 | */ | |
43 | #define NVME_MAX_KB_SZ 4096 | |
44 | #define NVME_MAX_SEGS 127 | |
45 | ||
58ffacb5 MW |
46 | static int use_threaded_interrupts; |
47 | module_param(use_threaded_interrupts, int, 0); | |
48 | ||
8ffaadf7 | 49 | static bool use_cmb_sqes = true; |
69f4eb9f | 50 | module_param(use_cmb_sqes, bool, 0444); |
8ffaadf7 JD |
51 | MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes"); |
52 | ||
87ad72a5 CH |
53 | static unsigned int max_host_mem_size_mb = 128; |
54 | module_param(max_host_mem_size_mb, uint, 0444); | |
55 | MODULE_PARM_DESC(max_host_mem_size_mb, | |
56 | "Maximum Host Memory Buffer (HMB) size per controller (in MiB)"); | |
1fa6aead | 57 | |
a7a7cbe3 CK |
58 | static unsigned int sgl_threshold = SZ_32K; |
59 | module_param(sgl_threshold, uint, 0644); | |
60 | MODULE_PARM_DESC(sgl_threshold, | |
61 | "Use SGLs when average request segment size is larger or equal to " | |
62 | "this size. Use 0 to disable SGLs."); | |
63 | ||
27453b45 SG |
64 | #define NVME_PCI_MIN_QUEUE_SIZE 2 |
65 | #define NVME_PCI_MAX_QUEUE_SIZE 4095 | |
b27c1e68 | 66 | static int io_queue_depth_set(const char *val, const struct kernel_param *kp); |
67 | static const struct kernel_param_ops io_queue_depth_ops = { | |
68 | .set = io_queue_depth_set, | |
61f3b896 | 69 | .get = param_get_uint, |
b27c1e68 | 70 | }; |
71 | ||
61f3b896 | 72 | static unsigned int io_queue_depth = 1024; |
b27c1e68 | 73 | module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644); |
27453b45 | 74 | MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2 and < 4096"); |
b27c1e68 | 75 | |
9c9e76d5 WZ |
76 | static int io_queue_count_set(const char *val, const struct kernel_param *kp) |
77 | { | |
78 | unsigned int n; | |
79 | int ret; | |
80 | ||
81 | ret = kstrtouint(val, 10, &n); | |
82 | if (ret != 0 || n > num_possible_cpus()) | |
83 | return -EINVAL; | |
84 | return param_set_uint(val, kp); | |
85 | } | |
86 | ||
87 | static const struct kernel_param_ops io_queue_count_ops = { | |
88 | .set = io_queue_count_set, | |
89 | .get = param_get_uint, | |
90 | }; | |
91 | ||
3f68baf7 | 92 | static unsigned int write_queues; |
9c9e76d5 | 93 | module_param_cb(write_queues, &io_queue_count_ops, &write_queues, 0644); |
3b6592f7 JA |
94 | MODULE_PARM_DESC(write_queues, |
95 | "Number of queues to use for writes. If not set, reads and writes " | |
96 | "will share a queue set."); | |
97 | ||
3f68baf7 | 98 | static unsigned int poll_queues; |
9c9e76d5 | 99 | module_param_cb(poll_queues, &io_queue_count_ops, &poll_queues, 0644); |
4b04cc6a JA |
100 | MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO."); |
101 | ||
df4f9bc4 DB |
102 | static bool noacpi; |
103 | module_param(noacpi, bool, 0444); | |
104 | MODULE_PARM_DESC(noacpi, "disable acpi bios quirks"); | |
105 | ||
1c63dc66 CH |
106 | struct nvme_dev; |
107 | struct nvme_queue; | |
b3fffdef | 108 | |
a5cdb68c | 109 | static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown); |
8fae268b | 110 | static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode); |
d4b4ff8e | 111 | |
1c63dc66 CH |
112 | /* |
113 | * Represents an NVM Express device. Each nvme_dev is a PCI function. | |
114 | */ | |
115 | struct nvme_dev { | |
147b27e4 | 116 | struct nvme_queue *queues; |
1c63dc66 CH |
117 | struct blk_mq_tag_set tagset; |
118 | struct blk_mq_tag_set admin_tagset; | |
119 | u32 __iomem *dbs; | |
120 | struct device *dev; | |
121 | struct dma_pool *prp_page_pool; | |
122 | struct dma_pool *prp_small_pool; | |
1c63dc66 CH |
123 | unsigned online_queues; |
124 | unsigned max_qid; | |
e20ba6e1 | 125 | unsigned io_queues[HCTX_MAX_TYPES]; |
22b55601 | 126 | unsigned int num_vecs; |
7442ddce | 127 | u32 q_depth; |
c1e0cc7e | 128 | int io_sqes; |
1c63dc66 | 129 | u32 db_stride; |
1c63dc66 | 130 | void __iomem *bar; |
97f6ef64 | 131 | unsigned long bar_mapped_size; |
5c8809e6 | 132 | struct work_struct remove_work; |
77bf25ea | 133 | struct mutex shutdown_lock; |
1c63dc66 | 134 | bool subsystem; |
1c63dc66 | 135 | u64 cmb_size; |
0f238ff5 | 136 | bool cmb_use_sqes; |
1c63dc66 | 137 | u32 cmbsz; |
202021c1 | 138 | u32 cmbloc; |
1c63dc66 | 139 | struct nvme_ctrl ctrl; |
d916b1be | 140 | u32 last_ps; |
a5df5e79 | 141 | bool hmb; |
87ad72a5 | 142 | |
943e942e JA |
143 | mempool_t *iod_mempool; |
144 | ||
87ad72a5 | 145 | /* shadow doorbell buffer support: */ |
f9f38e33 HK |
146 | u32 *dbbuf_dbs; |
147 | dma_addr_t dbbuf_dbs_dma_addr; | |
148 | u32 *dbbuf_eis; | |
149 | dma_addr_t dbbuf_eis_dma_addr; | |
87ad72a5 CH |
150 | |
151 | /* host memory buffer support: */ | |
152 | u64 host_mem_size; | |
153 | u32 nr_host_mem_descs; | |
4033f35d | 154 | dma_addr_t host_mem_descs_dma; |
87ad72a5 CH |
155 | struct nvme_host_mem_buf_desc *host_mem_descs; |
156 | void **host_mem_desc_bufs; | |
2a5bcfdd WZ |
157 | unsigned int nr_allocated_queues; |
158 | unsigned int nr_write_queues; | |
159 | unsigned int nr_poll_queues; | |
0521905e KB |
160 | |
161 | bool attrs_added; | |
4d115420 | 162 | }; |
1fa6aead | 163 | |
b27c1e68 | 164 | static int io_queue_depth_set(const char *val, const struct kernel_param *kp) |
165 | { | |
27453b45 SG |
166 | return param_set_uint_minmax(val, kp, NVME_PCI_MIN_QUEUE_SIZE, |
167 | NVME_PCI_MAX_QUEUE_SIZE); | |
b27c1e68 | 168 | } |
169 | ||
f9f38e33 HK |
170 | static inline unsigned int sq_idx(unsigned int qid, u32 stride) |
171 | { | |
172 | return qid * 2 * stride; | |
173 | } | |
174 | ||
175 | static inline unsigned int cq_idx(unsigned int qid, u32 stride) | |
176 | { | |
177 | return (qid * 2 + 1) * stride; | |
178 | } | |
179 | ||
1c63dc66 CH |
180 | static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl) |
181 | { | |
182 | return container_of(ctrl, struct nvme_dev, ctrl); | |
183 | } | |
184 | ||
b60503ba MW |
185 | /* |
186 | * An NVM Express queue. Each device has at least two (one for admin | |
187 | * commands and one for I/O commands). | |
188 | */ | |
189 | struct nvme_queue { | |
091b6092 | 190 | struct nvme_dev *dev; |
1ab0cd69 | 191 | spinlock_t sq_lock; |
c1e0cc7e | 192 | void *sq_cmds; |
3a7afd8e CH |
193 | /* only used for poll queues: */ |
194 | spinlock_t cq_poll_lock ____cacheline_aligned_in_smp; | |
74943d45 | 195 | struct nvme_completion *cqes; |
b60503ba MW |
196 | dma_addr_t sq_dma_addr; |
197 | dma_addr_t cq_dma_addr; | |
b60503ba | 198 | u32 __iomem *q_db; |
7442ddce | 199 | u32 q_depth; |
7c349dde | 200 | u16 cq_vector; |
b60503ba | 201 | u16 sq_tail; |
38210800 | 202 | u16 last_sq_tail; |
b60503ba | 203 | u16 cq_head; |
c30341dc | 204 | u16 qid; |
e9539f47 | 205 | u8 cq_phase; |
c1e0cc7e | 206 | u8 sqes; |
4e224106 CH |
207 | unsigned long flags; |
208 | #define NVMEQ_ENABLED 0 | |
63223078 | 209 | #define NVMEQ_SQ_CMB 1 |
d1ed6aa1 | 210 | #define NVMEQ_DELETE_ERROR 2 |
7c349dde | 211 | #define NVMEQ_POLLED 3 |
f9f38e33 HK |
212 | u32 *dbbuf_sq_db; |
213 | u32 *dbbuf_cq_db; | |
214 | u32 *dbbuf_sq_ei; | |
215 | u32 *dbbuf_cq_ei; | |
d1ed6aa1 | 216 | struct completion delete_done; |
b60503ba MW |
217 | }; |
218 | ||
71bd150c | 219 | /* |
9b048119 CH |
220 | * The nvme_iod describes the data in an I/O. |
221 | * | |
222 | * The sg pointer contains the list of PRP/SGL chunk allocations in addition | |
223 | * to the actual struct scatterlist. | |
71bd150c CH |
224 | */ |
225 | struct nvme_iod { | |
d49187e9 | 226 | struct nvme_request req; |
af7fae85 | 227 | struct nvme_command cmd; |
f4800d6d | 228 | struct nvme_queue *nvmeq; |
a7a7cbe3 | 229 | bool use_sgl; |
f4800d6d | 230 | int aborted; |
71bd150c | 231 | int npages; /* In the PRP list. 0 means small pool in use */ |
71bd150c | 232 | int nents; /* Used in scatterlist */ |
71bd150c | 233 | dma_addr_t first_dma; |
dff824b2 | 234 | unsigned int dma_len; /* length of single DMA segment mapping */ |
783b94bd | 235 | dma_addr_t meta_dma; |
f4800d6d | 236 | struct scatterlist *sg; |
b60503ba MW |
237 | }; |
238 | ||
2a5bcfdd | 239 | static inline unsigned int nvme_dbbuf_size(struct nvme_dev *dev) |
3b6592f7 | 240 | { |
2a5bcfdd | 241 | return dev->nr_allocated_queues * 8 * dev->db_stride; |
f9f38e33 HK |
242 | } |
243 | ||
244 | static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev) | |
245 | { | |
2a5bcfdd | 246 | unsigned int mem_size = nvme_dbbuf_size(dev); |
f9f38e33 HK |
247 | |
248 | if (dev->dbbuf_dbs) | |
249 | return 0; | |
250 | ||
251 | dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size, | |
252 | &dev->dbbuf_dbs_dma_addr, | |
253 | GFP_KERNEL); | |
254 | if (!dev->dbbuf_dbs) | |
255 | return -ENOMEM; | |
256 | dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size, | |
257 | &dev->dbbuf_eis_dma_addr, | |
258 | GFP_KERNEL); | |
259 | if (!dev->dbbuf_eis) { | |
260 | dma_free_coherent(dev->dev, mem_size, | |
261 | dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); | |
262 | dev->dbbuf_dbs = NULL; | |
263 | return -ENOMEM; | |
264 | } | |
265 | ||
266 | return 0; | |
267 | } | |
268 | ||
269 | static void nvme_dbbuf_dma_free(struct nvme_dev *dev) | |
270 | { | |
2a5bcfdd | 271 | unsigned int mem_size = nvme_dbbuf_size(dev); |
f9f38e33 HK |
272 | |
273 | if (dev->dbbuf_dbs) { | |
274 | dma_free_coherent(dev->dev, mem_size, | |
275 | dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); | |
276 | dev->dbbuf_dbs = NULL; | |
277 | } | |
278 | if (dev->dbbuf_eis) { | |
279 | dma_free_coherent(dev->dev, mem_size, | |
280 | dev->dbbuf_eis, dev->dbbuf_eis_dma_addr); | |
281 | dev->dbbuf_eis = NULL; | |
282 | } | |
283 | } | |
284 | ||
285 | static void nvme_dbbuf_init(struct nvme_dev *dev, | |
286 | struct nvme_queue *nvmeq, int qid) | |
287 | { | |
288 | if (!dev->dbbuf_dbs || !qid) | |
289 | return; | |
290 | ||
291 | nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)]; | |
292 | nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)]; | |
293 | nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)]; | |
294 | nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)]; | |
295 | } | |
296 | ||
0f0d2c87 MI |
297 | static void nvme_dbbuf_free(struct nvme_queue *nvmeq) |
298 | { | |
299 | if (!nvmeq->qid) | |
300 | return; | |
301 | ||
302 | nvmeq->dbbuf_sq_db = NULL; | |
303 | nvmeq->dbbuf_cq_db = NULL; | |
304 | nvmeq->dbbuf_sq_ei = NULL; | |
305 | nvmeq->dbbuf_cq_ei = NULL; | |
306 | } | |
307 | ||
f9f38e33 HK |
308 | static void nvme_dbbuf_set(struct nvme_dev *dev) |
309 | { | |
f66e2804 | 310 | struct nvme_command c = { }; |
0f0d2c87 | 311 | unsigned int i; |
f9f38e33 HK |
312 | |
313 | if (!dev->dbbuf_dbs) | |
314 | return; | |
315 | ||
f9f38e33 HK |
316 | c.dbbuf.opcode = nvme_admin_dbbuf; |
317 | c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr); | |
318 | c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr); | |
319 | ||
320 | if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) { | |
9bdcfb10 | 321 | dev_warn(dev->ctrl.device, "unable to set dbbuf\n"); |
f9f38e33 HK |
322 | /* Free memory and continue on */ |
323 | nvme_dbbuf_dma_free(dev); | |
0f0d2c87 MI |
324 | |
325 | for (i = 1; i <= dev->online_queues; i++) | |
326 | nvme_dbbuf_free(&dev->queues[i]); | |
f9f38e33 HK |
327 | } |
328 | } | |
329 | ||
330 | static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old) | |
331 | { | |
332 | return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old); | |
333 | } | |
334 | ||
335 | /* Update dbbuf and return true if an MMIO is required */ | |
336 | static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db, | |
337 | volatile u32 *dbbuf_ei) | |
338 | { | |
339 | if (dbbuf_db) { | |
340 | u16 old_value; | |
341 | ||
342 | /* | |
343 | * Ensure that the queue is written before updating | |
344 | * the doorbell in memory | |
345 | */ | |
346 | wmb(); | |
347 | ||
348 | old_value = *dbbuf_db; | |
349 | *dbbuf_db = value; | |
350 | ||
f1ed3df2 MW |
351 | /* |
352 | * Ensure that the doorbell is updated before reading the event | |
353 | * index from memory. The controller needs to provide similar | |
354 | * ordering to ensure the envent index is updated before reading | |
355 | * the doorbell. | |
356 | */ | |
357 | mb(); | |
358 | ||
f9f38e33 HK |
359 | if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value)) |
360 | return false; | |
361 | } | |
362 | ||
363 | return true; | |
b60503ba MW |
364 | } |
365 | ||
ac3dd5bd JA |
366 | /* |
367 | * Will slightly overestimate the number of pages needed. This is OK | |
368 | * as it only leads to a small amount of wasted memory for the lifetime of | |
369 | * the I/O. | |
370 | */ | |
b13c6393 | 371 | static int nvme_pci_npages_prp(void) |
ac3dd5bd | 372 | { |
b13c6393 | 373 | unsigned nprps = DIV_ROUND_UP(NVME_MAX_KB_SZ + NVME_CTRL_PAGE_SIZE, |
6c3c05b0 | 374 | NVME_CTRL_PAGE_SIZE); |
ac3dd5bd JA |
375 | return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); |
376 | } | |
377 | ||
a7a7cbe3 CK |
378 | /* |
379 | * Calculates the number of pages needed for the SGL segments. For example a 4k | |
380 | * page can accommodate 256 SGL descriptors. | |
381 | */ | |
b13c6393 | 382 | static int nvme_pci_npages_sgl(void) |
ac3dd5bd | 383 | { |
b13c6393 CK |
384 | return DIV_ROUND_UP(NVME_MAX_SEGS * sizeof(struct nvme_sgl_desc), |
385 | PAGE_SIZE); | |
f4800d6d | 386 | } |
ac3dd5bd | 387 | |
b13c6393 | 388 | static size_t nvme_pci_iod_alloc_size(void) |
f4800d6d | 389 | { |
b13c6393 | 390 | size_t npages = max(nvme_pci_npages_prp(), nvme_pci_npages_sgl()); |
a7a7cbe3 | 391 | |
b13c6393 CK |
392 | return sizeof(__le64 *) * npages + |
393 | sizeof(struct scatterlist) * NVME_MAX_SEGS; | |
f4800d6d | 394 | } |
ac3dd5bd | 395 | |
a4aea562 MB |
396 | static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, |
397 | unsigned int hctx_idx) | |
e85248e5 | 398 | { |
a4aea562 | 399 | struct nvme_dev *dev = data; |
147b27e4 | 400 | struct nvme_queue *nvmeq = &dev->queues[0]; |
a4aea562 | 401 | |
42483228 KB |
402 | WARN_ON(hctx_idx != 0); |
403 | WARN_ON(dev->admin_tagset.tags[0] != hctx->tags); | |
42483228 | 404 | |
a4aea562 MB |
405 | hctx->driver_data = nvmeq; |
406 | return 0; | |
e85248e5 MW |
407 | } |
408 | ||
a4aea562 MB |
409 | static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, |
410 | unsigned int hctx_idx) | |
b60503ba | 411 | { |
a4aea562 | 412 | struct nvme_dev *dev = data; |
147b27e4 | 413 | struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1]; |
a4aea562 | 414 | |
42483228 | 415 | WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags); |
a4aea562 MB |
416 | hctx->driver_data = nvmeq; |
417 | return 0; | |
b60503ba MW |
418 | } |
419 | ||
d6296d39 CH |
420 | static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req, |
421 | unsigned int hctx_idx, unsigned int numa_node) | |
b60503ba | 422 | { |
d6296d39 | 423 | struct nvme_dev *dev = set->driver_data; |
f4800d6d | 424 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
0350815a | 425 | int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0; |
147b27e4 | 426 | struct nvme_queue *nvmeq = &dev->queues[queue_idx]; |
a4aea562 MB |
427 | |
428 | BUG_ON(!nvmeq); | |
f4800d6d | 429 | iod->nvmeq = nvmeq; |
59e29ce6 SG |
430 | |
431 | nvme_req(req)->ctrl = &dev->ctrl; | |
f4b9e6c9 | 432 | nvme_req(req)->cmd = &iod->cmd; |
a4aea562 MB |
433 | return 0; |
434 | } | |
435 | ||
3b6592f7 JA |
436 | static int queue_irq_offset(struct nvme_dev *dev) |
437 | { | |
438 | /* if we have more than 1 vec, admin queue offsets us by 1 */ | |
439 | if (dev->num_vecs > 1) | |
440 | return 1; | |
441 | ||
442 | return 0; | |
443 | } | |
444 | ||
dca51e78 CH |
445 | static int nvme_pci_map_queues(struct blk_mq_tag_set *set) |
446 | { | |
447 | struct nvme_dev *dev = set->driver_data; | |
3b6592f7 JA |
448 | int i, qoff, offset; |
449 | ||
450 | offset = queue_irq_offset(dev); | |
451 | for (i = 0, qoff = 0; i < set->nr_maps; i++) { | |
452 | struct blk_mq_queue_map *map = &set->map[i]; | |
453 | ||
454 | map->nr_queues = dev->io_queues[i]; | |
455 | if (!map->nr_queues) { | |
e20ba6e1 | 456 | BUG_ON(i == HCTX_TYPE_DEFAULT); |
7e849dd9 | 457 | continue; |
3b6592f7 JA |
458 | } |
459 | ||
4b04cc6a JA |
460 | /* |
461 | * The poll queue(s) doesn't have an IRQ (and hence IRQ | |
462 | * affinity), so use the regular blk-mq cpu mapping | |
463 | */ | |
3b6592f7 | 464 | map->queue_offset = qoff; |
cb9e0e50 | 465 | if (i != HCTX_TYPE_POLL && offset) |
4b04cc6a JA |
466 | blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset); |
467 | else | |
468 | blk_mq_map_queues(map); | |
3b6592f7 JA |
469 | qoff += map->nr_queues; |
470 | offset += map->nr_queues; | |
471 | } | |
472 | ||
473 | return 0; | |
dca51e78 CH |
474 | } |
475 | ||
38210800 KB |
476 | /* |
477 | * Write sq tail if we are asked to, or if the next command would wrap. | |
478 | */ | |
479 | static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq) | |
04f3eafd | 480 | { |
38210800 KB |
481 | if (!write_sq) { |
482 | u16 next_tail = nvmeq->sq_tail + 1; | |
483 | ||
484 | if (next_tail == nvmeq->q_depth) | |
485 | next_tail = 0; | |
486 | if (next_tail != nvmeq->last_sq_tail) | |
487 | return; | |
488 | } | |
489 | ||
04f3eafd JA |
490 | if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail, |
491 | nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei)) | |
492 | writel(nvmeq->sq_tail, nvmeq->q_db); | |
38210800 | 493 | nvmeq->last_sq_tail = nvmeq->sq_tail; |
04f3eafd JA |
494 | } |
495 | ||
b60503ba | 496 | /** |
90ea5ca4 | 497 | * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell |
b60503ba MW |
498 | * @nvmeq: The queue to use |
499 | * @cmd: The command to send | |
04f3eafd | 500 | * @write_sq: whether to write to the SQ doorbell |
b60503ba | 501 | */ |
04f3eafd JA |
502 | static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd, |
503 | bool write_sq) | |
b60503ba | 504 | { |
90ea5ca4 | 505 | spin_lock(&nvmeq->sq_lock); |
c1e0cc7e BH |
506 | memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes), |
507 | cmd, sizeof(*cmd)); | |
90ea5ca4 CH |
508 | if (++nvmeq->sq_tail == nvmeq->q_depth) |
509 | nvmeq->sq_tail = 0; | |
38210800 | 510 | nvme_write_sq_db(nvmeq, write_sq); |
04f3eafd JA |
511 | spin_unlock(&nvmeq->sq_lock); |
512 | } | |
513 | ||
514 | static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx) | |
515 | { | |
516 | struct nvme_queue *nvmeq = hctx->driver_data; | |
517 | ||
518 | spin_lock(&nvmeq->sq_lock); | |
38210800 KB |
519 | if (nvmeq->sq_tail != nvmeq->last_sq_tail) |
520 | nvme_write_sq_db(nvmeq, true); | |
90ea5ca4 | 521 | spin_unlock(&nvmeq->sq_lock); |
b60503ba MW |
522 | } |
523 | ||
a7a7cbe3 | 524 | static void **nvme_pci_iod_list(struct request *req) |
b60503ba | 525 | { |
f4800d6d | 526 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
a7a7cbe3 | 527 | return (void **)(iod->sg + blk_rq_nr_phys_segments(req)); |
b60503ba MW |
528 | } |
529 | ||
955b1b5a MI |
530 | static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req) |
531 | { | |
532 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); | |
20469a37 | 533 | int nseg = blk_rq_nr_phys_segments(req); |
955b1b5a MI |
534 | unsigned int avg_seg_size; |
535 | ||
20469a37 | 536 | avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg); |
955b1b5a | 537 | |
253a0b76 | 538 | if (!nvme_ctrl_sgl_supported(&dev->ctrl)) |
955b1b5a MI |
539 | return false; |
540 | if (!iod->nvmeq->qid) | |
541 | return false; | |
542 | if (!sgl_threshold || avg_seg_size < sgl_threshold) | |
543 | return false; | |
544 | return true; | |
545 | } | |
546 | ||
9275c206 | 547 | static void nvme_free_prps(struct nvme_dev *dev, struct request *req) |
b60503ba | 548 | { |
6c3c05b0 | 549 | const int last_prp = NVME_CTRL_PAGE_SIZE / sizeof(__le64) - 1; |
9275c206 CH |
550 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
551 | dma_addr_t dma_addr = iod->first_dma; | |
eca18b23 | 552 | int i; |
eca18b23 | 553 | |
9275c206 CH |
554 | for (i = 0; i < iod->npages; i++) { |
555 | __le64 *prp_list = nvme_pci_iod_list(req)[i]; | |
556 | dma_addr_t next_dma_addr = le64_to_cpu(prp_list[last_prp]); | |
557 | ||
558 | dma_pool_free(dev->prp_page_pool, prp_list, dma_addr); | |
559 | dma_addr = next_dma_addr; | |
7fe07d14 | 560 | } |
9275c206 | 561 | } |
dff824b2 | 562 | |
9275c206 CH |
563 | static void nvme_free_sgls(struct nvme_dev *dev, struct request *req) |
564 | { | |
565 | const int last_sg = SGES_PER_PAGE - 1; | |
566 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); | |
567 | dma_addr_t dma_addr = iod->first_dma; | |
568 | int i; | |
dff824b2 | 569 | |
9275c206 CH |
570 | for (i = 0; i < iod->npages; i++) { |
571 | struct nvme_sgl_desc *sg_list = nvme_pci_iod_list(req)[i]; | |
572 | dma_addr_t next_dma_addr = le64_to_cpu((sg_list[last_sg]).addr); | |
dff824b2 | 573 | |
9275c206 CH |
574 | dma_pool_free(dev->prp_page_pool, sg_list, dma_addr); |
575 | dma_addr = next_dma_addr; | |
576 | } | |
9275c206 | 577 | } |
a7a7cbe3 | 578 | |
9275c206 CH |
579 | static void nvme_unmap_sg(struct nvme_dev *dev, struct request *req) |
580 | { | |
581 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); | |
a7a7cbe3 | 582 | |
9275c206 CH |
583 | if (is_pci_p2pdma_page(sg_page(iod->sg))) |
584 | pci_p2pdma_unmap_sg(dev->dev, iod->sg, iod->nents, | |
585 | rq_dma_dir(req)); | |
586 | else | |
587 | dma_unmap_sg(dev->dev, iod->sg, iod->nents, rq_dma_dir(req)); | |
588 | } | |
a7a7cbe3 | 589 | |
9275c206 CH |
590 | static void nvme_unmap_data(struct nvme_dev *dev, struct request *req) |
591 | { | |
592 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); | |
a7a7cbe3 | 593 | |
9275c206 CH |
594 | if (iod->dma_len) { |
595 | dma_unmap_page(dev->dev, iod->first_dma, iod->dma_len, | |
596 | rq_dma_dir(req)); | |
597 | return; | |
eca18b23 | 598 | } |
ac3dd5bd | 599 | |
9275c206 CH |
600 | WARN_ON_ONCE(!iod->nents); |
601 | ||
602 | nvme_unmap_sg(dev, req); | |
603 | if (iod->npages == 0) | |
604 | dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0], | |
605 | iod->first_dma); | |
606 | else if (iod->use_sgl) | |
607 | nvme_free_sgls(dev, req); | |
608 | else | |
609 | nvme_free_prps(dev, req); | |
d43f1ccf | 610 | mempool_free(iod->sg, dev->iod_mempool); |
b4ff9c8d KB |
611 | } |
612 | ||
d0877473 KB |
613 | static void nvme_print_sgl(struct scatterlist *sgl, int nents) |
614 | { | |
615 | int i; | |
616 | struct scatterlist *sg; | |
617 | ||
618 | for_each_sg(sgl, sg, nents, i) { | |
619 | dma_addr_t phys = sg_phys(sg); | |
620 | pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d " | |
621 | "dma_address:%pad dma_length:%d\n", | |
622 | i, &phys, sg->offset, sg->length, &sg_dma_address(sg), | |
623 | sg_dma_len(sg)); | |
624 | } | |
625 | } | |
626 | ||
a7a7cbe3 CK |
627 | static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev, |
628 | struct request *req, struct nvme_rw_command *cmnd) | |
ff22b54f | 629 | { |
f4800d6d | 630 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
99802a7a | 631 | struct dma_pool *pool; |
b131c61d | 632 | int length = blk_rq_payload_bytes(req); |
eca18b23 | 633 | struct scatterlist *sg = iod->sg; |
ff22b54f MW |
634 | int dma_len = sg_dma_len(sg); |
635 | u64 dma_addr = sg_dma_address(sg); | |
6c3c05b0 | 636 | int offset = dma_addr & (NVME_CTRL_PAGE_SIZE - 1); |
e025344c | 637 | __le64 *prp_list; |
a7a7cbe3 | 638 | void **list = nvme_pci_iod_list(req); |
e025344c | 639 | dma_addr_t prp_dma; |
eca18b23 | 640 | int nprps, i; |
ff22b54f | 641 | |
6c3c05b0 | 642 | length -= (NVME_CTRL_PAGE_SIZE - offset); |
5228b328 JS |
643 | if (length <= 0) { |
644 | iod->first_dma = 0; | |
a7a7cbe3 | 645 | goto done; |
5228b328 | 646 | } |
ff22b54f | 647 | |
6c3c05b0 | 648 | dma_len -= (NVME_CTRL_PAGE_SIZE - offset); |
ff22b54f | 649 | if (dma_len) { |
6c3c05b0 | 650 | dma_addr += (NVME_CTRL_PAGE_SIZE - offset); |
ff22b54f MW |
651 | } else { |
652 | sg = sg_next(sg); | |
653 | dma_addr = sg_dma_address(sg); | |
654 | dma_len = sg_dma_len(sg); | |
655 | } | |
656 | ||
6c3c05b0 | 657 | if (length <= NVME_CTRL_PAGE_SIZE) { |
edd10d33 | 658 | iod->first_dma = dma_addr; |
a7a7cbe3 | 659 | goto done; |
e025344c SMM |
660 | } |
661 | ||
6c3c05b0 | 662 | nprps = DIV_ROUND_UP(length, NVME_CTRL_PAGE_SIZE); |
99802a7a MW |
663 | if (nprps <= (256 / 8)) { |
664 | pool = dev->prp_small_pool; | |
eca18b23 | 665 | iod->npages = 0; |
99802a7a MW |
666 | } else { |
667 | pool = dev->prp_page_pool; | |
eca18b23 | 668 | iod->npages = 1; |
99802a7a MW |
669 | } |
670 | ||
69d2b571 | 671 | prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); |
b77954cb | 672 | if (!prp_list) { |
edd10d33 | 673 | iod->first_dma = dma_addr; |
eca18b23 | 674 | iod->npages = -1; |
86eea289 | 675 | return BLK_STS_RESOURCE; |
b77954cb | 676 | } |
eca18b23 MW |
677 | list[0] = prp_list; |
678 | iod->first_dma = prp_dma; | |
e025344c SMM |
679 | i = 0; |
680 | for (;;) { | |
6c3c05b0 | 681 | if (i == NVME_CTRL_PAGE_SIZE >> 3) { |
e025344c | 682 | __le64 *old_prp_list = prp_list; |
69d2b571 | 683 | prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); |
eca18b23 | 684 | if (!prp_list) |
fa073216 | 685 | goto free_prps; |
eca18b23 | 686 | list[iod->npages++] = prp_list; |
7523d834 MW |
687 | prp_list[0] = old_prp_list[i - 1]; |
688 | old_prp_list[i - 1] = cpu_to_le64(prp_dma); | |
689 | i = 1; | |
e025344c SMM |
690 | } |
691 | prp_list[i++] = cpu_to_le64(dma_addr); | |
6c3c05b0 CK |
692 | dma_len -= NVME_CTRL_PAGE_SIZE; |
693 | dma_addr += NVME_CTRL_PAGE_SIZE; | |
694 | length -= NVME_CTRL_PAGE_SIZE; | |
e025344c SMM |
695 | if (length <= 0) |
696 | break; | |
697 | if (dma_len > 0) | |
698 | continue; | |
86eea289 KB |
699 | if (unlikely(dma_len < 0)) |
700 | goto bad_sgl; | |
e025344c SMM |
701 | sg = sg_next(sg); |
702 | dma_addr = sg_dma_address(sg); | |
703 | dma_len = sg_dma_len(sg); | |
ff22b54f | 704 | } |
a7a7cbe3 CK |
705 | done: |
706 | cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg)); | |
707 | cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma); | |
86eea289 | 708 | return BLK_STS_OK; |
fa073216 CH |
709 | free_prps: |
710 | nvme_free_prps(dev, req); | |
711 | return BLK_STS_RESOURCE; | |
712 | bad_sgl: | |
d0877473 KB |
713 | WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents), |
714 | "Invalid SGL for payload:%d nents:%d\n", | |
715 | blk_rq_payload_bytes(req), iod->nents); | |
86eea289 | 716 | return BLK_STS_IOERR; |
ff22b54f MW |
717 | } |
718 | ||
a7a7cbe3 CK |
719 | static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge, |
720 | struct scatterlist *sg) | |
721 | { | |
722 | sge->addr = cpu_to_le64(sg_dma_address(sg)); | |
723 | sge->length = cpu_to_le32(sg_dma_len(sg)); | |
724 | sge->type = NVME_SGL_FMT_DATA_DESC << 4; | |
725 | } | |
726 | ||
727 | static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge, | |
728 | dma_addr_t dma_addr, int entries) | |
729 | { | |
730 | sge->addr = cpu_to_le64(dma_addr); | |
731 | if (entries < SGES_PER_PAGE) { | |
732 | sge->length = cpu_to_le32(entries * sizeof(*sge)); | |
733 | sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4; | |
734 | } else { | |
735 | sge->length = cpu_to_le32(PAGE_SIZE); | |
736 | sge->type = NVME_SGL_FMT_SEG_DESC << 4; | |
737 | } | |
738 | } | |
739 | ||
740 | static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev, | |
b0f2853b | 741 | struct request *req, struct nvme_rw_command *cmd, int entries) |
a7a7cbe3 CK |
742 | { |
743 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); | |
a7a7cbe3 CK |
744 | struct dma_pool *pool; |
745 | struct nvme_sgl_desc *sg_list; | |
746 | struct scatterlist *sg = iod->sg; | |
a7a7cbe3 | 747 | dma_addr_t sgl_dma; |
b0f2853b | 748 | int i = 0; |
a7a7cbe3 | 749 | |
a7a7cbe3 CK |
750 | /* setting the transfer type as SGL */ |
751 | cmd->flags = NVME_CMD_SGL_METABUF; | |
752 | ||
b0f2853b | 753 | if (entries == 1) { |
a7a7cbe3 CK |
754 | nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg); |
755 | return BLK_STS_OK; | |
756 | } | |
757 | ||
758 | if (entries <= (256 / sizeof(struct nvme_sgl_desc))) { | |
759 | pool = dev->prp_small_pool; | |
760 | iod->npages = 0; | |
761 | } else { | |
762 | pool = dev->prp_page_pool; | |
763 | iod->npages = 1; | |
764 | } | |
765 | ||
766 | sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); | |
767 | if (!sg_list) { | |
768 | iod->npages = -1; | |
769 | return BLK_STS_RESOURCE; | |
770 | } | |
771 | ||
772 | nvme_pci_iod_list(req)[0] = sg_list; | |
773 | iod->first_dma = sgl_dma; | |
774 | ||
775 | nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries); | |
776 | ||
777 | do { | |
778 | if (i == SGES_PER_PAGE) { | |
779 | struct nvme_sgl_desc *old_sg_desc = sg_list; | |
780 | struct nvme_sgl_desc *link = &old_sg_desc[i - 1]; | |
781 | ||
782 | sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); | |
783 | if (!sg_list) | |
fa073216 | 784 | goto free_sgls; |
a7a7cbe3 CK |
785 | |
786 | i = 0; | |
787 | nvme_pci_iod_list(req)[iod->npages++] = sg_list; | |
788 | sg_list[i++] = *link; | |
789 | nvme_pci_sgl_set_seg(link, sgl_dma, entries); | |
790 | } | |
791 | ||
792 | nvme_pci_sgl_set_data(&sg_list[i++], sg); | |
a7a7cbe3 | 793 | sg = sg_next(sg); |
b0f2853b | 794 | } while (--entries > 0); |
a7a7cbe3 | 795 | |
a7a7cbe3 | 796 | return BLK_STS_OK; |
fa073216 CH |
797 | free_sgls: |
798 | nvme_free_sgls(dev, req); | |
799 | return BLK_STS_RESOURCE; | |
a7a7cbe3 CK |
800 | } |
801 | ||
dff824b2 CH |
802 | static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev, |
803 | struct request *req, struct nvme_rw_command *cmnd, | |
804 | struct bio_vec *bv) | |
805 | { | |
806 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); | |
6c3c05b0 CK |
807 | unsigned int offset = bv->bv_offset & (NVME_CTRL_PAGE_SIZE - 1); |
808 | unsigned int first_prp_len = NVME_CTRL_PAGE_SIZE - offset; | |
dff824b2 CH |
809 | |
810 | iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0); | |
811 | if (dma_mapping_error(dev->dev, iod->first_dma)) | |
812 | return BLK_STS_RESOURCE; | |
813 | iod->dma_len = bv->bv_len; | |
814 | ||
815 | cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma); | |
816 | if (bv->bv_len > first_prp_len) | |
817 | cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len); | |
359c1f88 | 818 | return BLK_STS_OK; |
dff824b2 CH |
819 | } |
820 | ||
29791057 CH |
821 | static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev, |
822 | struct request *req, struct nvme_rw_command *cmnd, | |
823 | struct bio_vec *bv) | |
824 | { | |
825 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); | |
826 | ||
827 | iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0); | |
828 | if (dma_mapping_error(dev->dev, iod->first_dma)) | |
829 | return BLK_STS_RESOURCE; | |
830 | iod->dma_len = bv->bv_len; | |
831 | ||
049bf372 | 832 | cmnd->flags = NVME_CMD_SGL_METABUF; |
29791057 CH |
833 | cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma); |
834 | cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len); | |
835 | cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4; | |
359c1f88 | 836 | return BLK_STS_OK; |
29791057 CH |
837 | } |
838 | ||
fc17b653 | 839 | static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req, |
b131c61d | 840 | struct nvme_command *cmnd) |
d29ec824 | 841 | { |
f4800d6d | 842 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
70479b71 | 843 | blk_status_t ret = BLK_STS_RESOURCE; |
b0f2853b | 844 | int nr_mapped; |
d29ec824 | 845 | |
dff824b2 CH |
846 | if (blk_rq_nr_phys_segments(req) == 1) { |
847 | struct bio_vec bv = req_bvec(req); | |
848 | ||
849 | if (!is_pci_p2pdma_page(bv.bv_page)) { | |
6c3c05b0 | 850 | if (bv.bv_offset + bv.bv_len <= NVME_CTRL_PAGE_SIZE * 2) |
dff824b2 CH |
851 | return nvme_setup_prp_simple(dev, req, |
852 | &cmnd->rw, &bv); | |
29791057 | 853 | |
e51183be | 854 | if (iod->nvmeq->qid && sgl_threshold && |
253a0b76 | 855 | nvme_ctrl_sgl_supported(&dev->ctrl)) |
29791057 CH |
856 | return nvme_setup_sgl_simple(dev, req, |
857 | &cmnd->rw, &bv); | |
dff824b2 CH |
858 | } |
859 | } | |
860 | ||
861 | iod->dma_len = 0; | |
d43f1ccf CH |
862 | iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC); |
863 | if (!iod->sg) | |
864 | return BLK_STS_RESOURCE; | |
f9d03f96 | 865 | sg_init_table(iod->sg, blk_rq_nr_phys_segments(req)); |
70479b71 | 866 | iod->nents = blk_rq_map_sg(req->q, req, iod->sg); |
ba1ca37e | 867 | if (!iod->nents) |
fa073216 | 868 | goto out_free_sg; |
d29ec824 | 869 | |
e0596ab2 | 870 | if (is_pci_p2pdma_page(sg_page(iod->sg))) |
2b9f4bb2 LG |
871 | nr_mapped = pci_p2pdma_map_sg_attrs(dev->dev, iod->sg, |
872 | iod->nents, rq_dma_dir(req), DMA_ATTR_NO_WARN); | |
e0596ab2 LG |
873 | else |
874 | nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, | |
70479b71 | 875 | rq_dma_dir(req), DMA_ATTR_NO_WARN); |
b0f2853b | 876 | if (!nr_mapped) |
fa073216 | 877 | goto out_free_sg; |
d29ec824 | 878 | |
70479b71 | 879 | iod->use_sgl = nvme_pci_use_sgls(dev, req); |
955b1b5a | 880 | if (iod->use_sgl) |
b0f2853b | 881 | ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped); |
a7a7cbe3 CK |
882 | else |
883 | ret = nvme_pci_setup_prps(dev, req, &cmnd->rw); | |
86eea289 | 884 | if (ret != BLK_STS_OK) |
fa073216 CH |
885 | goto out_unmap_sg; |
886 | return BLK_STS_OK; | |
887 | ||
888 | out_unmap_sg: | |
889 | nvme_unmap_sg(dev, req); | |
890 | out_free_sg: | |
891 | mempool_free(iod->sg, dev->iod_mempool); | |
4aedb705 CH |
892 | return ret; |
893 | } | |
3045c0d0 | 894 | |
4aedb705 CH |
895 | static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req, |
896 | struct nvme_command *cmnd) | |
897 | { | |
898 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); | |
00df5cb4 | 899 | |
4aedb705 CH |
900 | iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req), |
901 | rq_dma_dir(req), 0); | |
902 | if (dma_mapping_error(dev->dev, iod->meta_dma)) | |
903 | return BLK_STS_IOERR; | |
904 | cmnd->rw.metadata = cpu_to_le64(iod->meta_dma); | |
359c1f88 | 905 | return BLK_STS_OK; |
00df5cb4 MW |
906 | } |
907 | ||
d29ec824 CH |
908 | /* |
909 | * NOTE: ns is NULL when called on the admin queue. | |
910 | */ | |
fc17b653 | 911 | static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx, |
a4aea562 | 912 | const struct blk_mq_queue_data *bd) |
edd10d33 | 913 | { |
a4aea562 MB |
914 | struct nvme_ns *ns = hctx->queue->queuedata; |
915 | struct nvme_queue *nvmeq = hctx->driver_data; | |
d29ec824 | 916 | struct nvme_dev *dev = nvmeq->dev; |
a4aea562 | 917 | struct request *req = bd->rq; |
9b048119 | 918 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
af7fae85 | 919 | struct nvme_command *cmnd = &iod->cmd; |
ebe6d874 | 920 | blk_status_t ret; |
e1e5e564 | 921 | |
9b048119 CH |
922 | iod->aborted = 0; |
923 | iod->npages = -1; | |
924 | iod->nents = 0; | |
925 | ||
d1f06f4a JA |
926 | /* |
927 | * We should not need to do this, but we're still using this to | |
928 | * ensure we can drain requests on a dying queue. | |
929 | */ | |
4e224106 | 930 | if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags))) |
d1f06f4a JA |
931 | return BLK_STS_IOERR; |
932 | ||
d4060d2b TC |
933 | if (!nvme_check_ready(&dev->ctrl, req, true)) |
934 | return nvme_fail_nonready_command(&dev->ctrl, req); | |
935 | ||
f4b9e6c9 | 936 | ret = nvme_setup_cmd(ns, req); |
fc17b653 | 937 | if (ret) |
f4800d6d | 938 | return ret; |
a4aea562 | 939 | |
fc17b653 | 940 | if (blk_rq_nr_phys_segments(req)) { |
af7fae85 | 941 | ret = nvme_map_data(dev, req, cmnd); |
fc17b653 | 942 | if (ret) |
9b048119 | 943 | goto out_free_cmd; |
fc17b653 | 944 | } |
a4aea562 | 945 | |
4aedb705 | 946 | if (blk_integrity_rq(req)) { |
af7fae85 | 947 | ret = nvme_map_metadata(dev, req, cmnd); |
4aedb705 CH |
948 | if (ret) |
949 | goto out_unmap_data; | |
950 | } | |
951 | ||
aae239e1 | 952 | blk_mq_start_request(req); |
af7fae85 | 953 | nvme_submit_cmd(nvmeq, cmnd, bd->last); |
fc17b653 | 954 | return BLK_STS_OK; |
4aedb705 CH |
955 | out_unmap_data: |
956 | nvme_unmap_data(dev, req); | |
f9d03f96 CH |
957 | out_free_cmd: |
958 | nvme_cleanup_cmd(req); | |
ba1ca37e | 959 | return ret; |
b60503ba | 960 | } |
e1e5e564 | 961 | |
77f02a7a | 962 | static void nvme_pci_complete_rq(struct request *req) |
eee417b0 | 963 | { |
f4800d6d | 964 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
4aedb705 | 965 | struct nvme_dev *dev = iod->nvmeq->dev; |
a4aea562 | 966 | |
4aedb705 CH |
967 | if (blk_integrity_rq(req)) |
968 | dma_unmap_page(dev->dev, iod->meta_dma, | |
969 | rq_integrity_vec(req)->bv_len, rq_data_dir(req)); | |
b15c592d | 970 | if (blk_rq_nr_phys_segments(req)) |
4aedb705 | 971 | nvme_unmap_data(dev, req); |
77f02a7a | 972 | nvme_complete_rq(req); |
b60503ba MW |
973 | } |
974 | ||
d783e0bd | 975 | /* We read the CQE phase first to check if the rest of the entry is valid */ |
750dde44 | 976 | static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq) |
d783e0bd | 977 | { |
74943d45 KB |
978 | struct nvme_completion *hcqe = &nvmeq->cqes[nvmeq->cq_head]; |
979 | ||
980 | return (le16_to_cpu(READ_ONCE(hcqe->status)) & 1) == nvmeq->cq_phase; | |
d783e0bd MR |
981 | } |
982 | ||
eb281c82 | 983 | static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq) |
b60503ba | 984 | { |
eb281c82 | 985 | u16 head = nvmeq->cq_head; |
adf68f21 | 986 | |
397c699f KB |
987 | if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db, |
988 | nvmeq->dbbuf_cq_ei)) | |
989 | writel(head, nvmeq->q_db + nvmeq->dev->db_stride); | |
eb281c82 | 990 | } |
aae239e1 | 991 | |
cfa27356 CH |
992 | static inline struct blk_mq_tags *nvme_queue_tagset(struct nvme_queue *nvmeq) |
993 | { | |
994 | if (!nvmeq->qid) | |
995 | return nvmeq->dev->admin_tagset.tags[0]; | |
996 | return nvmeq->dev->tagset.tags[nvmeq->qid - 1]; | |
997 | } | |
998 | ||
5cb525c8 | 999 | static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx) |
83a12fb7 | 1000 | { |
74943d45 | 1001 | struct nvme_completion *cqe = &nvmeq->cqes[idx]; |
62df8016 | 1002 | __u16 command_id = READ_ONCE(cqe->command_id); |
83a12fb7 | 1003 | struct request *req; |
adf68f21 | 1004 | |
83a12fb7 SG |
1005 | /* |
1006 | * AEN requests are special as they don't time out and can | |
1007 | * survive any kind of queue freeze and often don't respond to | |
1008 | * aborts. We don't even bother to allocate a struct request | |
1009 | * for them but rather special case them here. | |
1010 | */ | |
62df8016 | 1011 | if (unlikely(nvme_is_aen_req(nvmeq->qid, command_id))) { |
83a12fb7 SG |
1012 | nvme_complete_async_event(&nvmeq->dev->ctrl, |
1013 | cqe->status, &cqe->result); | |
a0fa9647 | 1014 | return; |
83a12fb7 | 1015 | } |
b60503ba | 1016 | |
e7006de6 | 1017 | req = nvme_find_rq(nvme_queue_tagset(nvmeq), command_id); |
50b7c243 XT |
1018 | if (unlikely(!req)) { |
1019 | dev_warn(nvmeq->dev->ctrl.device, | |
1020 | "invalid id %d completed on queue %d\n", | |
62df8016 | 1021 | command_id, le16_to_cpu(cqe->sq_id)); |
50b7c243 XT |
1022 | return; |
1023 | } | |
1024 | ||
604c01d5 | 1025 | trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail); |
2eb81a33 | 1026 | if (!nvme_try_complete_req(req, cqe->status, cqe->result)) |
ff029451 | 1027 | nvme_pci_complete_rq(req); |
83a12fb7 | 1028 | } |
b60503ba | 1029 | |
5cb525c8 JA |
1030 | static inline void nvme_update_cq_head(struct nvme_queue *nvmeq) |
1031 | { | |
a0aac973 | 1032 | u32 tmp = nvmeq->cq_head + 1; |
a8de6639 AD |
1033 | |
1034 | if (tmp == nvmeq->q_depth) { | |
5cb525c8 | 1035 | nvmeq->cq_head = 0; |
e2a366a4 | 1036 | nvmeq->cq_phase ^= 1; |
a8de6639 AD |
1037 | } else { |
1038 | nvmeq->cq_head = tmp; | |
b60503ba | 1039 | } |
a0fa9647 JA |
1040 | } |
1041 | ||
324b494c | 1042 | static inline int nvme_process_cq(struct nvme_queue *nvmeq) |
a0fa9647 | 1043 | { |
1052b8ac | 1044 | int found = 0; |
b60503ba | 1045 | |
1052b8ac | 1046 | while (nvme_cqe_pending(nvmeq)) { |
bf392a5d | 1047 | found++; |
b69e2ef2 KB |
1048 | /* |
1049 | * load-load control dependency between phase and the rest of | |
1050 | * the cqe requires a full read memory barrier | |
1051 | */ | |
1052 | dma_rmb(); | |
324b494c | 1053 | nvme_handle_cqe(nvmeq, nvmeq->cq_head); |
5cb525c8 | 1054 | nvme_update_cq_head(nvmeq); |
920d13a8 | 1055 | } |
eb281c82 | 1056 | |
324b494c | 1057 | if (found) |
920d13a8 | 1058 | nvme_ring_cq_doorbell(nvmeq); |
5cb525c8 | 1059 | return found; |
b60503ba MW |
1060 | } |
1061 | ||
1062 | static irqreturn_t nvme_irq(int irq, void *data) | |
58ffacb5 | 1063 | { |
58ffacb5 | 1064 | struct nvme_queue *nvmeq = data; |
5cb525c8 | 1065 | |
324b494c | 1066 | if (nvme_process_cq(nvmeq)) |
05fae499 CK |
1067 | return IRQ_HANDLED; |
1068 | return IRQ_NONE; | |
58ffacb5 MW |
1069 | } |
1070 | ||
1071 | static irqreturn_t nvme_irq_check(int irq, void *data) | |
1072 | { | |
1073 | struct nvme_queue *nvmeq = data; | |
4e523547 | 1074 | |
750dde44 | 1075 | if (nvme_cqe_pending(nvmeq)) |
d783e0bd MR |
1076 | return IRQ_WAKE_THREAD; |
1077 | return IRQ_NONE; | |
58ffacb5 MW |
1078 | } |
1079 | ||
0b2a8a9f | 1080 | /* |
fa059b85 | 1081 | * Poll for completions for any interrupt driven queue |
0b2a8a9f CH |
1082 | * Can be called from any context. |
1083 | */ | |
fa059b85 | 1084 | static void nvme_poll_irqdisable(struct nvme_queue *nvmeq) |
a0fa9647 | 1085 | { |
3a7afd8e | 1086 | struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); |
a0fa9647 | 1087 | |
fa059b85 | 1088 | WARN_ON_ONCE(test_bit(NVMEQ_POLLED, &nvmeq->flags)); |
442e19b7 | 1089 | |
fa059b85 KB |
1090 | disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); |
1091 | nvme_process_cq(nvmeq); | |
1092 | enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); | |
a0fa9647 JA |
1093 | } |
1094 | ||
5a72e899 | 1095 | static int nvme_poll(struct blk_mq_hw_ctx *hctx, struct io_comp_batch *iob) |
dabcefab JA |
1096 | { |
1097 | struct nvme_queue *nvmeq = hctx->driver_data; | |
dabcefab JA |
1098 | bool found; |
1099 | ||
1100 | if (!nvme_cqe_pending(nvmeq)) | |
1101 | return 0; | |
1102 | ||
3a7afd8e | 1103 | spin_lock(&nvmeq->cq_poll_lock); |
324b494c | 1104 | found = nvme_process_cq(nvmeq); |
3a7afd8e | 1105 | spin_unlock(&nvmeq->cq_poll_lock); |
dabcefab | 1106 | |
dabcefab JA |
1107 | return found; |
1108 | } | |
1109 | ||
ad22c355 | 1110 | static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl) |
b60503ba | 1111 | { |
f866fc42 | 1112 | struct nvme_dev *dev = to_nvme_dev(ctrl); |
147b27e4 | 1113 | struct nvme_queue *nvmeq = &dev->queues[0]; |
f66e2804 | 1114 | struct nvme_command c = { }; |
b60503ba | 1115 | |
a4aea562 | 1116 | c.common.opcode = nvme_admin_async_event; |
ad22c355 | 1117 | c.common.command_id = NVME_AQ_BLK_MQ_DEPTH; |
04f3eafd | 1118 | nvme_submit_cmd(nvmeq, &c, true); |
f705f837 CH |
1119 | } |
1120 | ||
b60503ba | 1121 | static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) |
f705f837 | 1122 | { |
f66e2804 | 1123 | struct nvme_command c = { }; |
b60503ba | 1124 | |
b60503ba MW |
1125 | c.delete_queue.opcode = opcode; |
1126 | c.delete_queue.qid = cpu_to_le16(id); | |
1127 | ||
1c63dc66 | 1128 | return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); |
b60503ba MW |
1129 | } |
1130 | ||
b60503ba | 1131 | static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, |
a8e3e0bb | 1132 | struct nvme_queue *nvmeq, s16 vector) |
b60503ba | 1133 | { |
f66e2804 | 1134 | struct nvme_command c = { }; |
4b04cc6a JA |
1135 | int flags = NVME_QUEUE_PHYS_CONTIG; |
1136 | ||
7c349dde | 1137 | if (!test_bit(NVMEQ_POLLED, &nvmeq->flags)) |
4b04cc6a | 1138 | flags |= NVME_CQ_IRQ_ENABLED; |
b60503ba | 1139 | |
d29ec824 | 1140 | /* |
16772ae6 | 1141 | * Note: we (ab)use the fact that the prp fields survive if no data |
d29ec824 CH |
1142 | * is attached to the request. |
1143 | */ | |
b60503ba MW |
1144 | c.create_cq.opcode = nvme_admin_create_cq; |
1145 | c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); | |
1146 | c.create_cq.cqid = cpu_to_le16(qid); | |
1147 | c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); | |
1148 | c.create_cq.cq_flags = cpu_to_le16(flags); | |
7c349dde | 1149 | c.create_cq.irq_vector = cpu_to_le16(vector); |
b60503ba | 1150 | |
1c63dc66 | 1151 | return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); |
b60503ba MW |
1152 | } |
1153 | ||
1154 | static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, | |
1155 | struct nvme_queue *nvmeq) | |
1156 | { | |
9abd68ef | 1157 | struct nvme_ctrl *ctrl = &dev->ctrl; |
f66e2804 | 1158 | struct nvme_command c = { }; |
81c1cd98 | 1159 | int flags = NVME_QUEUE_PHYS_CONTIG; |
b60503ba | 1160 | |
9abd68ef JA |
1161 | /* |
1162 | * Some drives have a bug that auto-enables WRRU if MEDIUM isn't | |
1163 | * set. Since URGENT priority is zeroes, it makes all queues | |
1164 | * URGENT. | |
1165 | */ | |
1166 | if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ) | |
1167 | flags |= NVME_SQ_PRIO_MEDIUM; | |
1168 | ||
d29ec824 | 1169 | /* |
16772ae6 | 1170 | * Note: we (ab)use the fact that the prp fields survive if no data |
d29ec824 CH |
1171 | * is attached to the request. |
1172 | */ | |
b60503ba MW |
1173 | c.create_sq.opcode = nvme_admin_create_sq; |
1174 | c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); | |
1175 | c.create_sq.sqid = cpu_to_le16(qid); | |
1176 | c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); | |
1177 | c.create_sq.sq_flags = cpu_to_le16(flags); | |
1178 | c.create_sq.cqid = cpu_to_le16(qid); | |
1179 | ||
1c63dc66 | 1180 | return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); |
b60503ba MW |
1181 | } |
1182 | ||
1183 | static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) | |
1184 | { | |
1185 | return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); | |
1186 | } | |
1187 | ||
1188 | static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) | |
1189 | { | |
1190 | return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); | |
1191 | } | |
1192 | ||
2a842aca | 1193 | static void abort_endio(struct request *req, blk_status_t error) |
bc5fc7e4 | 1194 | { |
f4800d6d CH |
1195 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
1196 | struct nvme_queue *nvmeq = iod->nvmeq; | |
e44ac588 | 1197 | |
27fa9bc5 CH |
1198 | dev_warn(nvmeq->dev->ctrl.device, |
1199 | "Abort status: 0x%x", nvme_req(req)->status); | |
e7a2a87d | 1200 | atomic_inc(&nvmeq->dev->ctrl.abort_limit); |
e7a2a87d | 1201 | blk_mq_free_request(req); |
bc5fc7e4 MW |
1202 | } |
1203 | ||
b2a0eb1a KB |
1204 | static bool nvme_should_reset(struct nvme_dev *dev, u32 csts) |
1205 | { | |
b2a0eb1a KB |
1206 | /* If true, indicates loss of adapter communication, possibly by a |
1207 | * NVMe Subsystem reset. | |
1208 | */ | |
1209 | bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO); | |
1210 | ||
ad70062c JW |
1211 | /* If there is a reset/reinit ongoing, we shouldn't reset again. */ |
1212 | switch (dev->ctrl.state) { | |
1213 | case NVME_CTRL_RESETTING: | |
ad6a0a52 | 1214 | case NVME_CTRL_CONNECTING: |
b2a0eb1a | 1215 | return false; |
ad70062c JW |
1216 | default: |
1217 | break; | |
1218 | } | |
b2a0eb1a KB |
1219 | |
1220 | /* We shouldn't reset unless the controller is on fatal error state | |
1221 | * _or_ if we lost the communication with it. | |
1222 | */ | |
1223 | if (!(csts & NVME_CSTS_CFS) && !nssro) | |
1224 | return false; | |
1225 | ||
b2a0eb1a KB |
1226 | return true; |
1227 | } | |
1228 | ||
1229 | static void nvme_warn_reset(struct nvme_dev *dev, u32 csts) | |
1230 | { | |
1231 | /* Read a config register to help see what died. */ | |
1232 | u16 pci_status; | |
1233 | int result; | |
1234 | ||
1235 | result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS, | |
1236 | &pci_status); | |
1237 | if (result == PCIBIOS_SUCCESSFUL) | |
1238 | dev_warn(dev->ctrl.device, | |
1239 | "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n", | |
1240 | csts, pci_status); | |
1241 | else | |
1242 | dev_warn(dev->ctrl.device, | |
1243 | "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n", | |
1244 | csts, result); | |
1245 | } | |
1246 | ||
31c7c7d2 | 1247 | static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved) |
c30341dc | 1248 | { |
f4800d6d CH |
1249 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
1250 | struct nvme_queue *nvmeq = iod->nvmeq; | |
c30341dc | 1251 | struct nvme_dev *dev = nvmeq->dev; |
a4aea562 | 1252 | struct request *abort_req; |
f66e2804 | 1253 | struct nvme_command cmd = { }; |
b2a0eb1a KB |
1254 | u32 csts = readl(dev->bar + NVME_REG_CSTS); |
1255 | ||
651438bb WX |
1256 | /* If PCI error recovery process is happening, we cannot reset or |
1257 | * the recovery mechanism will surely fail. | |
1258 | */ | |
1259 | mb(); | |
1260 | if (pci_channel_offline(to_pci_dev(dev->dev))) | |
1261 | return BLK_EH_RESET_TIMER; | |
1262 | ||
b2a0eb1a KB |
1263 | /* |
1264 | * Reset immediately if the controller is failed | |
1265 | */ | |
1266 | if (nvme_should_reset(dev, csts)) { | |
1267 | nvme_warn_reset(dev, csts); | |
1268 | nvme_dev_disable(dev, false); | |
d86c4d8e | 1269 | nvme_reset_ctrl(&dev->ctrl); |
db8c48e4 | 1270 | return BLK_EH_DONE; |
b2a0eb1a | 1271 | } |
c30341dc | 1272 | |
7776db1c KB |
1273 | /* |
1274 | * Did we miss an interrupt? | |
1275 | */ | |
fa059b85 | 1276 | if (test_bit(NVMEQ_POLLED, &nvmeq->flags)) |
5a72e899 | 1277 | nvme_poll(req->mq_hctx, NULL); |
fa059b85 KB |
1278 | else |
1279 | nvme_poll_irqdisable(nvmeq); | |
1280 | ||
bf392a5d | 1281 | if (blk_mq_request_completed(req)) { |
7776db1c KB |
1282 | dev_warn(dev->ctrl.device, |
1283 | "I/O %d QID %d timeout, completion polled\n", | |
1284 | req->tag, nvmeq->qid); | |
db8c48e4 | 1285 | return BLK_EH_DONE; |
7776db1c KB |
1286 | } |
1287 | ||
31c7c7d2 | 1288 | /* |
fd634f41 CH |
1289 | * Shutdown immediately if controller times out while starting. The |
1290 | * reset work will see the pci device disabled when it gets the forced | |
1291 | * cancellation error. All outstanding requests are completed on | |
db8c48e4 | 1292 | * shutdown, so we return BLK_EH_DONE. |
fd634f41 | 1293 | */ |
4244140d KB |
1294 | switch (dev->ctrl.state) { |
1295 | case NVME_CTRL_CONNECTING: | |
2036f726 | 1296 | nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); |
df561f66 | 1297 | fallthrough; |
2036f726 | 1298 | case NVME_CTRL_DELETING: |
b9cac43c | 1299 | dev_warn_ratelimited(dev->ctrl.device, |
fd634f41 CH |
1300 | "I/O %d QID %d timeout, disable controller\n", |
1301 | req->tag, nvmeq->qid); | |
27fa9bc5 | 1302 | nvme_req(req)->flags |= NVME_REQ_CANCELLED; |
7ad92f65 | 1303 | nvme_dev_disable(dev, true); |
db8c48e4 | 1304 | return BLK_EH_DONE; |
39a9dd81 KB |
1305 | case NVME_CTRL_RESETTING: |
1306 | return BLK_EH_RESET_TIMER; | |
4244140d KB |
1307 | default: |
1308 | break; | |
c30341dc KB |
1309 | } |
1310 | ||
fd634f41 | 1311 | /* |
ee0d96d3 BW |
1312 | * Shutdown the controller immediately and schedule a reset if the |
1313 | * command was already aborted once before and still hasn't been | |
1314 | * returned to the driver, or if this is the admin queue. | |
31c7c7d2 | 1315 | */ |
f4800d6d | 1316 | if (!nvmeq->qid || iod->aborted) { |
1b3c47c1 | 1317 | dev_warn(dev->ctrl.device, |
e1569a16 KB |
1318 | "I/O %d QID %d timeout, reset controller\n", |
1319 | req->tag, nvmeq->qid); | |
7ad92f65 | 1320 | nvme_req(req)->flags |= NVME_REQ_CANCELLED; |
a5cdb68c | 1321 | nvme_dev_disable(dev, false); |
d86c4d8e | 1322 | nvme_reset_ctrl(&dev->ctrl); |
c30341dc | 1323 | |
db8c48e4 | 1324 | return BLK_EH_DONE; |
c30341dc | 1325 | } |
c30341dc | 1326 | |
e7a2a87d | 1327 | if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) { |
6bf25d16 | 1328 | atomic_inc(&dev->ctrl.abort_limit); |
31c7c7d2 | 1329 | return BLK_EH_RESET_TIMER; |
6bf25d16 | 1330 | } |
7bf7d778 | 1331 | iod->aborted = 1; |
a4aea562 | 1332 | |
c30341dc | 1333 | cmd.abort.opcode = nvme_admin_abort_cmd; |
85f74acf | 1334 | cmd.abort.cid = nvme_cid(req); |
c30341dc | 1335 | cmd.abort.sqid = cpu_to_le16(nvmeq->qid); |
c30341dc | 1336 | |
1b3c47c1 SG |
1337 | dev_warn(nvmeq->dev->ctrl.device, |
1338 | "I/O %d QID %d timeout, aborting\n", | |
1339 | req->tag, nvmeq->qid); | |
e7a2a87d CH |
1340 | |
1341 | abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd, | |
39dfe844 | 1342 | BLK_MQ_REQ_NOWAIT); |
e7a2a87d CH |
1343 | if (IS_ERR(abort_req)) { |
1344 | atomic_inc(&dev->ctrl.abort_limit); | |
1345 | return BLK_EH_RESET_TIMER; | |
1346 | } | |
1347 | ||
e7a2a87d | 1348 | abort_req->end_io_data = NULL; |
8eeed0b5 | 1349 | blk_execute_rq_nowait(NULL, abort_req, 0, abort_endio); |
c30341dc | 1350 | |
31c7c7d2 CH |
1351 | /* |
1352 | * The aborted req will be completed on receiving the abort req. | |
1353 | * We enable the timer again. If hit twice, it'll cause a device reset, | |
1354 | * as the device then is in a faulty state. | |
1355 | */ | |
1356 | return BLK_EH_RESET_TIMER; | |
c30341dc KB |
1357 | } |
1358 | ||
a4aea562 MB |
1359 | static void nvme_free_queue(struct nvme_queue *nvmeq) |
1360 | { | |
8a1d09a6 | 1361 | dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq), |
9e866774 | 1362 | (void *)nvmeq->cqes, nvmeq->cq_dma_addr); |
63223078 CH |
1363 | if (!nvmeq->sq_cmds) |
1364 | return; | |
0f238ff5 | 1365 | |
63223078 | 1366 | if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) { |
88a041f4 | 1367 | pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev), |
8a1d09a6 | 1368 | nvmeq->sq_cmds, SQ_SIZE(nvmeq)); |
63223078 | 1369 | } else { |
8a1d09a6 | 1370 | dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq), |
63223078 | 1371 | nvmeq->sq_cmds, nvmeq->sq_dma_addr); |
0f238ff5 | 1372 | } |
9e866774 MW |
1373 | } |
1374 | ||
a1a5ef99 | 1375 | static void nvme_free_queues(struct nvme_dev *dev, int lowest) |
22404274 KB |
1376 | { |
1377 | int i; | |
1378 | ||
d858e5f0 | 1379 | for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) { |
d858e5f0 | 1380 | dev->ctrl.queue_count--; |
147b27e4 | 1381 | nvme_free_queue(&dev->queues[i]); |
121c7ad4 | 1382 | } |
22404274 KB |
1383 | } |
1384 | ||
4d115420 KB |
1385 | /** |
1386 | * nvme_suspend_queue - put queue into suspended state | |
40581d1a | 1387 | * @nvmeq: queue to suspend |
4d115420 KB |
1388 | */ |
1389 | static int nvme_suspend_queue(struct nvme_queue *nvmeq) | |
b60503ba | 1390 | { |
4e224106 | 1391 | if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags)) |
2b25d981 | 1392 | return 1; |
a09115b2 | 1393 | |
4e224106 | 1394 | /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */ |
d1f06f4a | 1395 | mb(); |
a09115b2 | 1396 | |
4e224106 | 1397 | nvmeq->dev->online_queues--; |
1c63dc66 | 1398 | if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q) |
c81545f9 | 1399 | blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q); |
7c349dde KB |
1400 | if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags)) |
1401 | pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq); | |
4d115420 KB |
1402 | return 0; |
1403 | } | |
b60503ba | 1404 | |
8fae268b KB |
1405 | static void nvme_suspend_io_queues(struct nvme_dev *dev) |
1406 | { | |
1407 | int i; | |
1408 | ||
1409 | for (i = dev->ctrl.queue_count - 1; i > 0; i--) | |
1410 | nvme_suspend_queue(&dev->queues[i]); | |
1411 | } | |
1412 | ||
a5cdb68c | 1413 | static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown) |
4d115420 | 1414 | { |
147b27e4 | 1415 | struct nvme_queue *nvmeq = &dev->queues[0]; |
4d115420 | 1416 | |
a5cdb68c KB |
1417 | if (shutdown) |
1418 | nvme_shutdown_ctrl(&dev->ctrl); | |
1419 | else | |
b5b05048 | 1420 | nvme_disable_ctrl(&dev->ctrl); |
07836e65 | 1421 | |
bf392a5d | 1422 | nvme_poll_irqdisable(nvmeq); |
b60503ba MW |
1423 | } |
1424 | ||
fa46c6fb KB |
1425 | /* |
1426 | * Called only on a device that has been disabled and after all other threads | |
9210c075 DZ |
1427 | * that can check this device's completion queues have synced, except |
1428 | * nvme_poll(). This is the last chance for the driver to see a natural | |
1429 | * completion before nvme_cancel_request() terminates all incomplete requests. | |
fa46c6fb KB |
1430 | */ |
1431 | static void nvme_reap_pending_cqes(struct nvme_dev *dev) | |
1432 | { | |
fa46c6fb KB |
1433 | int i; |
1434 | ||
9210c075 DZ |
1435 | for (i = dev->ctrl.queue_count - 1; i > 0; i--) { |
1436 | spin_lock(&dev->queues[i].cq_poll_lock); | |
324b494c | 1437 | nvme_process_cq(&dev->queues[i]); |
9210c075 DZ |
1438 | spin_unlock(&dev->queues[i].cq_poll_lock); |
1439 | } | |
fa46c6fb KB |
1440 | } |
1441 | ||
8ffaadf7 JD |
1442 | static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues, |
1443 | int entry_size) | |
1444 | { | |
1445 | int q_depth = dev->q_depth; | |
5fd4ce1b | 1446 | unsigned q_size_aligned = roundup(q_depth * entry_size, |
6c3c05b0 | 1447 | NVME_CTRL_PAGE_SIZE); |
8ffaadf7 JD |
1448 | |
1449 | if (q_size_aligned * nr_io_queues > dev->cmb_size) { | |
c45f5c99 | 1450 | u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues); |
4e523547 | 1451 | |
6c3c05b0 | 1452 | mem_per_q = round_down(mem_per_q, NVME_CTRL_PAGE_SIZE); |
c45f5c99 | 1453 | q_depth = div_u64(mem_per_q, entry_size); |
8ffaadf7 JD |
1454 | |
1455 | /* | |
1456 | * Ensure the reduced q_depth is above some threshold where it | |
1457 | * would be better to map queues in system memory with the | |
1458 | * original depth | |
1459 | */ | |
1460 | if (q_depth < 64) | |
1461 | return -ENOMEM; | |
1462 | } | |
1463 | ||
1464 | return q_depth; | |
1465 | } | |
1466 | ||
1467 | static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq, | |
8a1d09a6 | 1468 | int qid) |
8ffaadf7 | 1469 | { |
0f238ff5 LG |
1470 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
1471 | ||
1472 | if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) { | |
8a1d09a6 | 1473 | nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq)); |
bfac8e9f AM |
1474 | if (nvmeq->sq_cmds) { |
1475 | nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev, | |
1476 | nvmeq->sq_cmds); | |
1477 | if (nvmeq->sq_dma_addr) { | |
1478 | set_bit(NVMEQ_SQ_CMB, &nvmeq->flags); | |
1479 | return 0; | |
1480 | } | |
1481 | ||
8a1d09a6 | 1482 | pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq)); |
63223078 | 1483 | } |
0f238ff5 | 1484 | } |
8ffaadf7 | 1485 | |
8a1d09a6 | 1486 | nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq), |
63223078 | 1487 | &nvmeq->sq_dma_addr, GFP_KERNEL); |
815c6704 KB |
1488 | if (!nvmeq->sq_cmds) |
1489 | return -ENOMEM; | |
8ffaadf7 JD |
1490 | return 0; |
1491 | } | |
1492 | ||
a6ff7262 | 1493 | static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth) |
b60503ba | 1494 | { |
147b27e4 | 1495 | struct nvme_queue *nvmeq = &dev->queues[qid]; |
b60503ba | 1496 | |
62314e40 KB |
1497 | if (dev->ctrl.queue_count > qid) |
1498 | return 0; | |
b60503ba | 1499 | |
c1e0cc7e | 1500 | nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES; |
8a1d09a6 BH |
1501 | nvmeq->q_depth = depth; |
1502 | nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq), | |
750afb08 | 1503 | &nvmeq->cq_dma_addr, GFP_KERNEL); |
b60503ba MW |
1504 | if (!nvmeq->cqes) |
1505 | goto free_nvmeq; | |
b60503ba | 1506 | |
8a1d09a6 | 1507 | if (nvme_alloc_sq_cmds(dev, nvmeq, qid)) |
b60503ba MW |
1508 | goto free_cqdma; |
1509 | ||
091b6092 | 1510 | nvmeq->dev = dev; |
1ab0cd69 | 1511 | spin_lock_init(&nvmeq->sq_lock); |
3a7afd8e | 1512 | spin_lock_init(&nvmeq->cq_poll_lock); |
b60503ba | 1513 | nvmeq->cq_head = 0; |
82123460 | 1514 | nvmeq->cq_phase = 1; |
b80d5ccc | 1515 | nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; |
c30341dc | 1516 | nvmeq->qid = qid; |
d858e5f0 | 1517 | dev->ctrl.queue_count++; |
36a7e993 | 1518 | |
147b27e4 | 1519 | return 0; |
b60503ba MW |
1520 | |
1521 | free_cqdma: | |
8a1d09a6 BH |
1522 | dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes, |
1523 | nvmeq->cq_dma_addr); | |
b60503ba | 1524 | free_nvmeq: |
147b27e4 | 1525 | return -ENOMEM; |
b60503ba MW |
1526 | } |
1527 | ||
dca51e78 | 1528 | static int queue_request_irq(struct nvme_queue *nvmeq) |
3001082c | 1529 | { |
0ff199cb CH |
1530 | struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); |
1531 | int nr = nvmeq->dev->ctrl.instance; | |
1532 | ||
1533 | if (use_threaded_interrupts) { | |
1534 | return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check, | |
1535 | nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid); | |
1536 | } else { | |
1537 | return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq, | |
1538 | NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid); | |
1539 | } | |
3001082c MW |
1540 | } |
1541 | ||
22404274 | 1542 | static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) |
b60503ba | 1543 | { |
22404274 | 1544 | struct nvme_dev *dev = nvmeq->dev; |
b60503ba | 1545 | |
22404274 | 1546 | nvmeq->sq_tail = 0; |
38210800 | 1547 | nvmeq->last_sq_tail = 0; |
22404274 KB |
1548 | nvmeq->cq_head = 0; |
1549 | nvmeq->cq_phase = 1; | |
b80d5ccc | 1550 | nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; |
8a1d09a6 | 1551 | memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq)); |
f9f38e33 | 1552 | nvme_dbbuf_init(dev, nvmeq, qid); |
42f61420 | 1553 | dev->online_queues++; |
3a7afd8e | 1554 | wmb(); /* ensure the first interrupt sees the initialization */ |
22404274 KB |
1555 | } |
1556 | ||
e4b9852a CC |
1557 | /* |
1558 | * Try getting shutdown_lock while setting up IO queues. | |
1559 | */ | |
1560 | static int nvme_setup_io_queues_trylock(struct nvme_dev *dev) | |
1561 | { | |
1562 | /* | |
1563 | * Give up if the lock is being held by nvme_dev_disable. | |
1564 | */ | |
1565 | if (!mutex_trylock(&dev->shutdown_lock)) | |
1566 | return -ENODEV; | |
1567 | ||
1568 | /* | |
1569 | * Controller is in wrong state, fail early. | |
1570 | */ | |
1571 | if (dev->ctrl.state != NVME_CTRL_CONNECTING) { | |
1572 | mutex_unlock(&dev->shutdown_lock); | |
1573 | return -ENODEV; | |
1574 | } | |
1575 | ||
1576 | return 0; | |
1577 | } | |
1578 | ||
4b04cc6a | 1579 | static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled) |
22404274 KB |
1580 | { |
1581 | struct nvme_dev *dev = nvmeq->dev; | |
1582 | int result; | |
7c349dde | 1583 | u16 vector = 0; |
3f85d50b | 1584 | |
d1ed6aa1 CH |
1585 | clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); |
1586 | ||
22b55601 KB |
1587 | /* |
1588 | * A queue's vector matches the queue identifier unless the controller | |
1589 | * has only one vector available. | |
1590 | */ | |
4b04cc6a JA |
1591 | if (!polled) |
1592 | vector = dev->num_vecs == 1 ? 0 : qid; | |
1593 | else | |
7c349dde | 1594 | set_bit(NVMEQ_POLLED, &nvmeq->flags); |
4b04cc6a | 1595 | |
a8e3e0bb | 1596 | result = adapter_alloc_cq(dev, qid, nvmeq, vector); |
ded45505 KB |
1597 | if (result) |
1598 | return result; | |
b60503ba MW |
1599 | |
1600 | result = adapter_alloc_sq(dev, qid, nvmeq); | |
1601 | if (result < 0) | |
ded45505 | 1602 | return result; |
c80b36cd | 1603 | if (result) |
b60503ba MW |
1604 | goto release_cq; |
1605 | ||
a8e3e0bb | 1606 | nvmeq->cq_vector = vector; |
4b04cc6a | 1607 | |
e4b9852a CC |
1608 | result = nvme_setup_io_queues_trylock(dev); |
1609 | if (result) | |
1610 | return result; | |
1611 | nvme_init_queue(nvmeq, qid); | |
7c349dde | 1612 | if (!polled) { |
4b04cc6a JA |
1613 | result = queue_request_irq(nvmeq); |
1614 | if (result < 0) | |
1615 | goto release_sq; | |
1616 | } | |
b60503ba | 1617 | |
4e224106 | 1618 | set_bit(NVMEQ_ENABLED, &nvmeq->flags); |
e4b9852a | 1619 | mutex_unlock(&dev->shutdown_lock); |
22404274 | 1620 | return result; |
b60503ba | 1621 | |
a8e3e0bb | 1622 | release_sq: |
f25a2dfc | 1623 | dev->online_queues--; |
e4b9852a | 1624 | mutex_unlock(&dev->shutdown_lock); |
b60503ba | 1625 | adapter_delete_sq(dev, qid); |
a8e3e0bb | 1626 | release_cq: |
b60503ba | 1627 | adapter_delete_cq(dev, qid); |
22404274 | 1628 | return result; |
b60503ba MW |
1629 | } |
1630 | ||
f363b089 | 1631 | static const struct blk_mq_ops nvme_mq_admin_ops = { |
d29ec824 | 1632 | .queue_rq = nvme_queue_rq, |
77f02a7a | 1633 | .complete = nvme_pci_complete_rq, |
a4aea562 | 1634 | .init_hctx = nvme_admin_init_hctx, |
0350815a | 1635 | .init_request = nvme_init_request, |
a4aea562 MB |
1636 | .timeout = nvme_timeout, |
1637 | }; | |
1638 | ||
f363b089 | 1639 | static const struct blk_mq_ops nvme_mq_ops = { |
376f7ef8 CH |
1640 | .queue_rq = nvme_queue_rq, |
1641 | .complete = nvme_pci_complete_rq, | |
1642 | .commit_rqs = nvme_commit_rqs, | |
1643 | .init_hctx = nvme_init_hctx, | |
1644 | .init_request = nvme_init_request, | |
1645 | .map_queues = nvme_pci_map_queues, | |
1646 | .timeout = nvme_timeout, | |
1647 | .poll = nvme_poll, | |
dabcefab JA |
1648 | }; |
1649 | ||
ea191d2f KB |
1650 | static void nvme_dev_remove_admin(struct nvme_dev *dev) |
1651 | { | |
1c63dc66 | 1652 | if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) { |
69d9a99c KB |
1653 | /* |
1654 | * If the controller was reset during removal, it's possible | |
1655 | * user requests may be waiting on a stopped queue. Start the | |
1656 | * queue to flush these to completion. | |
1657 | */ | |
c81545f9 | 1658 | blk_mq_unquiesce_queue(dev->ctrl.admin_q); |
1c63dc66 | 1659 | blk_cleanup_queue(dev->ctrl.admin_q); |
ea191d2f KB |
1660 | blk_mq_free_tag_set(&dev->admin_tagset); |
1661 | } | |
1662 | } | |
1663 | ||
a4aea562 MB |
1664 | static int nvme_alloc_admin_tags(struct nvme_dev *dev) |
1665 | { | |
1c63dc66 | 1666 | if (!dev->ctrl.admin_q) { |
a4aea562 MB |
1667 | dev->admin_tagset.ops = &nvme_mq_admin_ops; |
1668 | dev->admin_tagset.nr_hw_queues = 1; | |
e3e9d50c | 1669 | |
38dabe21 | 1670 | dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH; |
dc96f938 | 1671 | dev->admin_tagset.timeout = NVME_ADMIN_TIMEOUT; |
d4ec47f1 | 1672 | dev->admin_tagset.numa_node = dev->ctrl.numa_node; |
d43f1ccf | 1673 | dev->admin_tagset.cmd_size = sizeof(struct nvme_iod); |
d3484991 | 1674 | dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED; |
a4aea562 MB |
1675 | dev->admin_tagset.driver_data = dev; |
1676 | ||
1677 | if (blk_mq_alloc_tag_set(&dev->admin_tagset)) | |
1678 | return -ENOMEM; | |
34b6c231 | 1679 | dev->ctrl.admin_tagset = &dev->admin_tagset; |
a4aea562 | 1680 | |
1c63dc66 CH |
1681 | dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset); |
1682 | if (IS_ERR(dev->ctrl.admin_q)) { | |
a4aea562 MB |
1683 | blk_mq_free_tag_set(&dev->admin_tagset); |
1684 | return -ENOMEM; | |
1685 | } | |
1c63dc66 | 1686 | if (!blk_get_queue(dev->ctrl.admin_q)) { |
ea191d2f | 1687 | nvme_dev_remove_admin(dev); |
1c63dc66 | 1688 | dev->ctrl.admin_q = NULL; |
ea191d2f KB |
1689 | return -ENODEV; |
1690 | } | |
0fb59cbc | 1691 | } else |
c81545f9 | 1692 | blk_mq_unquiesce_queue(dev->ctrl.admin_q); |
a4aea562 MB |
1693 | |
1694 | return 0; | |
1695 | } | |
1696 | ||
97f6ef64 XY |
1697 | static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) |
1698 | { | |
1699 | return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride); | |
1700 | } | |
1701 | ||
1702 | static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size) | |
1703 | { | |
1704 | struct pci_dev *pdev = to_pci_dev(dev->dev); | |
1705 | ||
1706 | if (size <= dev->bar_mapped_size) | |
1707 | return 0; | |
1708 | if (size > pci_resource_len(pdev, 0)) | |
1709 | return -ENOMEM; | |
1710 | if (dev->bar) | |
1711 | iounmap(dev->bar); | |
1712 | dev->bar = ioremap(pci_resource_start(pdev, 0), size); | |
1713 | if (!dev->bar) { | |
1714 | dev->bar_mapped_size = 0; | |
1715 | return -ENOMEM; | |
1716 | } | |
1717 | dev->bar_mapped_size = size; | |
1718 | dev->dbs = dev->bar + NVME_REG_DBS; | |
1719 | ||
1720 | return 0; | |
1721 | } | |
1722 | ||
01ad0990 | 1723 | static int nvme_pci_configure_admin_queue(struct nvme_dev *dev) |
b60503ba | 1724 | { |
ba47e386 | 1725 | int result; |
b60503ba MW |
1726 | u32 aqa; |
1727 | struct nvme_queue *nvmeq; | |
1728 | ||
97f6ef64 XY |
1729 | result = nvme_remap_bar(dev, db_bar_size(dev, 0)); |
1730 | if (result < 0) | |
1731 | return result; | |
1732 | ||
8ef2074d | 1733 | dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ? |
20d0dfe6 | 1734 | NVME_CAP_NSSRC(dev->ctrl.cap) : 0; |
dfbac8c7 | 1735 | |
7a67cbea CH |
1736 | if (dev->subsystem && |
1737 | (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO)) | |
1738 | writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS); | |
dfbac8c7 | 1739 | |
b5b05048 | 1740 | result = nvme_disable_ctrl(&dev->ctrl); |
ba47e386 MW |
1741 | if (result < 0) |
1742 | return result; | |
b60503ba | 1743 | |
a6ff7262 | 1744 | result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH); |
147b27e4 SG |
1745 | if (result) |
1746 | return result; | |
b60503ba | 1747 | |
635333e4 MG |
1748 | dev->ctrl.numa_node = dev_to_node(dev->dev); |
1749 | ||
147b27e4 | 1750 | nvmeq = &dev->queues[0]; |
b60503ba MW |
1751 | aqa = nvmeq->q_depth - 1; |
1752 | aqa |= aqa << 16; | |
1753 | ||
7a67cbea CH |
1754 | writel(aqa, dev->bar + NVME_REG_AQA); |
1755 | lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ); | |
1756 | lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ); | |
b60503ba | 1757 | |
c0f2f45b | 1758 | result = nvme_enable_ctrl(&dev->ctrl); |
025c557a | 1759 | if (result) |
d4875622 | 1760 | return result; |
a4aea562 | 1761 | |
2b25d981 | 1762 | nvmeq->cq_vector = 0; |
161b8be2 | 1763 | nvme_init_queue(nvmeq, 0); |
dca51e78 | 1764 | result = queue_request_irq(nvmeq); |
758dd7fd | 1765 | if (result) { |
7c349dde | 1766 | dev->online_queues--; |
d4875622 | 1767 | return result; |
758dd7fd | 1768 | } |
025c557a | 1769 | |
4e224106 | 1770 | set_bit(NVMEQ_ENABLED, &nvmeq->flags); |
b60503ba MW |
1771 | return result; |
1772 | } | |
1773 | ||
749941f2 | 1774 | static int nvme_create_io_queues(struct nvme_dev *dev) |
42f61420 | 1775 | { |
4b04cc6a | 1776 | unsigned i, max, rw_queues; |
749941f2 | 1777 | int ret = 0; |
42f61420 | 1778 | |
d858e5f0 | 1779 | for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) { |
a6ff7262 | 1780 | if (nvme_alloc_queue(dev, i, dev->q_depth)) { |
749941f2 | 1781 | ret = -ENOMEM; |
42f61420 | 1782 | break; |
749941f2 CH |
1783 | } |
1784 | } | |
42f61420 | 1785 | |
d858e5f0 | 1786 | max = min(dev->max_qid, dev->ctrl.queue_count - 1); |
e20ba6e1 CH |
1787 | if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) { |
1788 | rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] + | |
1789 | dev->io_queues[HCTX_TYPE_READ]; | |
4b04cc6a JA |
1790 | } else { |
1791 | rw_queues = max; | |
1792 | } | |
1793 | ||
949928c1 | 1794 | for (i = dev->online_queues; i <= max; i++) { |
4b04cc6a JA |
1795 | bool polled = i > rw_queues; |
1796 | ||
1797 | ret = nvme_create_queue(&dev->queues[i], i, polled); | |
d4875622 | 1798 | if (ret) |
42f61420 | 1799 | break; |
27e8166c | 1800 | } |
749941f2 CH |
1801 | |
1802 | /* | |
1803 | * Ignore failing Create SQ/CQ commands, we can continue with less | |
8adb8c14 MI |
1804 | * than the desired amount of queues, and even a controller without |
1805 | * I/O queues can still be used to issue admin commands. This might | |
749941f2 CH |
1806 | * be useful to upgrade a buggy firmware for example. |
1807 | */ | |
1808 | return ret >= 0 ? 0 : ret; | |
b60503ba MW |
1809 | } |
1810 | ||
88de4598 | 1811 | static u64 nvme_cmb_size_unit(struct nvme_dev *dev) |
8ffaadf7 | 1812 | { |
88de4598 CH |
1813 | u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK; |
1814 | ||
1815 | return 1ULL << (12 + 4 * szu); | |
1816 | } | |
1817 | ||
1818 | static u32 nvme_cmb_size(struct nvme_dev *dev) | |
1819 | { | |
1820 | return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK; | |
1821 | } | |
1822 | ||
f65efd6d | 1823 | static void nvme_map_cmb(struct nvme_dev *dev) |
8ffaadf7 | 1824 | { |
88de4598 | 1825 | u64 size, offset; |
8ffaadf7 JD |
1826 | resource_size_t bar_size; |
1827 | struct pci_dev *pdev = to_pci_dev(dev->dev); | |
8969f1f8 | 1828 | int bar; |
8ffaadf7 | 1829 | |
9fe5c59f KB |
1830 | if (dev->cmb_size) |
1831 | return; | |
1832 | ||
20d3bb92 KJ |
1833 | if (NVME_CAP_CMBS(dev->ctrl.cap)) |
1834 | writel(NVME_CMBMSC_CRE, dev->bar + NVME_REG_CMBMSC); | |
1835 | ||
7a67cbea | 1836 | dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ); |
f65efd6d CH |
1837 | if (!dev->cmbsz) |
1838 | return; | |
202021c1 | 1839 | dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC); |
8ffaadf7 | 1840 | |
88de4598 CH |
1841 | size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev); |
1842 | offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc); | |
8969f1f8 CH |
1843 | bar = NVME_CMB_BIR(dev->cmbloc); |
1844 | bar_size = pci_resource_len(pdev, bar); | |
8ffaadf7 JD |
1845 | |
1846 | if (offset > bar_size) | |
f65efd6d | 1847 | return; |
8ffaadf7 | 1848 | |
20d3bb92 KJ |
1849 | /* |
1850 | * Tell the controller about the host side address mapping the CMB, | |
1851 | * and enable CMB decoding for the NVMe 1.4+ scheme: | |
1852 | */ | |
1853 | if (NVME_CAP_CMBS(dev->ctrl.cap)) { | |
1854 | hi_lo_writeq(NVME_CMBMSC_CRE | NVME_CMBMSC_CMSE | | |
1855 | (pci_bus_address(pdev, bar) + offset), | |
1856 | dev->bar + NVME_REG_CMBMSC); | |
1857 | } | |
1858 | ||
8ffaadf7 JD |
1859 | /* |
1860 | * Controllers may support a CMB size larger than their BAR, | |
1861 | * for example, due to being behind a bridge. Reduce the CMB to | |
1862 | * the reported size of the BAR | |
1863 | */ | |
1864 | if (size > bar_size - offset) | |
1865 | size = bar_size - offset; | |
1866 | ||
0f238ff5 LG |
1867 | if (pci_p2pdma_add_resource(pdev, bar, size, offset)) { |
1868 | dev_warn(dev->ctrl.device, | |
1869 | "failed to register the CMB\n"); | |
f65efd6d | 1870 | return; |
0f238ff5 LG |
1871 | } |
1872 | ||
8ffaadf7 | 1873 | dev->cmb_size = size; |
0f238ff5 LG |
1874 | dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS); |
1875 | ||
1876 | if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) == | |
1877 | (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) | |
1878 | pci_p2pmem_publish(pdev, true); | |
8ffaadf7 JD |
1879 | } |
1880 | ||
87ad72a5 CH |
1881 | static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits) |
1882 | { | |
6c3c05b0 | 1883 | u32 host_mem_size = dev->host_mem_size >> NVME_CTRL_PAGE_SHIFT; |
4033f35d | 1884 | u64 dma_addr = dev->host_mem_descs_dma; |
f66e2804 | 1885 | struct nvme_command c = { }; |
87ad72a5 CH |
1886 | int ret; |
1887 | ||
87ad72a5 CH |
1888 | c.features.opcode = nvme_admin_set_features; |
1889 | c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF); | |
1890 | c.features.dword11 = cpu_to_le32(bits); | |
6c3c05b0 | 1891 | c.features.dword12 = cpu_to_le32(host_mem_size); |
87ad72a5 CH |
1892 | c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr)); |
1893 | c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr)); | |
1894 | c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs); | |
1895 | ||
1896 | ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); | |
1897 | if (ret) { | |
1898 | dev_warn(dev->ctrl.device, | |
1899 | "failed to set host mem (err %d, flags %#x).\n", | |
1900 | ret, bits); | |
a5df5e79 KB |
1901 | } else |
1902 | dev->hmb = bits & NVME_HOST_MEM_ENABLE; | |
1903 | ||
87ad72a5 CH |
1904 | return ret; |
1905 | } | |
1906 | ||
1907 | static void nvme_free_host_mem(struct nvme_dev *dev) | |
1908 | { | |
1909 | int i; | |
1910 | ||
1911 | for (i = 0; i < dev->nr_host_mem_descs; i++) { | |
1912 | struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i]; | |
6c3c05b0 | 1913 | size_t size = le32_to_cpu(desc->size) * NVME_CTRL_PAGE_SIZE; |
87ad72a5 | 1914 | |
cc667f6d LD |
1915 | dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i], |
1916 | le64_to_cpu(desc->addr), | |
1917 | DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); | |
87ad72a5 CH |
1918 | } |
1919 | ||
1920 | kfree(dev->host_mem_desc_bufs); | |
1921 | dev->host_mem_desc_bufs = NULL; | |
4033f35d CH |
1922 | dma_free_coherent(dev->dev, |
1923 | dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs), | |
1924 | dev->host_mem_descs, dev->host_mem_descs_dma); | |
87ad72a5 | 1925 | dev->host_mem_descs = NULL; |
7e5dd57e | 1926 | dev->nr_host_mem_descs = 0; |
87ad72a5 CH |
1927 | } |
1928 | ||
92dc6895 CH |
1929 | static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred, |
1930 | u32 chunk_size) | |
9d713c2b | 1931 | { |
87ad72a5 | 1932 | struct nvme_host_mem_buf_desc *descs; |
92dc6895 | 1933 | u32 max_entries, len; |
4033f35d | 1934 | dma_addr_t descs_dma; |
2ee0e4ed | 1935 | int i = 0; |
87ad72a5 | 1936 | void **bufs; |
6fbcde66 | 1937 | u64 size, tmp; |
87ad72a5 | 1938 | |
87ad72a5 CH |
1939 | tmp = (preferred + chunk_size - 1); |
1940 | do_div(tmp, chunk_size); | |
1941 | max_entries = tmp; | |
044a9df1 CH |
1942 | |
1943 | if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries) | |
1944 | max_entries = dev->ctrl.hmmaxd; | |
1945 | ||
750afb08 LC |
1946 | descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs), |
1947 | &descs_dma, GFP_KERNEL); | |
87ad72a5 CH |
1948 | if (!descs) |
1949 | goto out; | |
1950 | ||
1951 | bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL); | |
1952 | if (!bufs) | |
1953 | goto out_free_descs; | |
1954 | ||
244a8fe4 | 1955 | for (size = 0; size < preferred && i < max_entries; size += len) { |
87ad72a5 CH |
1956 | dma_addr_t dma_addr; |
1957 | ||
50cdb7c6 | 1958 | len = min_t(u64, chunk_size, preferred - size); |
87ad72a5 CH |
1959 | bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL, |
1960 | DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); | |
1961 | if (!bufs[i]) | |
1962 | break; | |
1963 | ||
1964 | descs[i].addr = cpu_to_le64(dma_addr); | |
6c3c05b0 | 1965 | descs[i].size = cpu_to_le32(len / NVME_CTRL_PAGE_SIZE); |
87ad72a5 CH |
1966 | i++; |
1967 | } | |
1968 | ||
92dc6895 | 1969 | if (!size) |
87ad72a5 | 1970 | goto out_free_bufs; |
87ad72a5 | 1971 | |
87ad72a5 CH |
1972 | dev->nr_host_mem_descs = i; |
1973 | dev->host_mem_size = size; | |
1974 | dev->host_mem_descs = descs; | |
4033f35d | 1975 | dev->host_mem_descs_dma = descs_dma; |
87ad72a5 CH |
1976 | dev->host_mem_desc_bufs = bufs; |
1977 | return 0; | |
1978 | ||
1979 | out_free_bufs: | |
1980 | while (--i >= 0) { | |
6c3c05b0 | 1981 | size_t size = le32_to_cpu(descs[i].size) * NVME_CTRL_PAGE_SIZE; |
87ad72a5 | 1982 | |
cc667f6d LD |
1983 | dma_free_attrs(dev->dev, size, bufs[i], |
1984 | le64_to_cpu(descs[i].addr), | |
1985 | DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); | |
87ad72a5 CH |
1986 | } |
1987 | ||
1988 | kfree(bufs); | |
1989 | out_free_descs: | |
4033f35d CH |
1990 | dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs, |
1991 | descs_dma); | |
87ad72a5 | 1992 | out: |
87ad72a5 CH |
1993 | dev->host_mem_descs = NULL; |
1994 | return -ENOMEM; | |
1995 | } | |
1996 | ||
92dc6895 CH |
1997 | static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred) |
1998 | { | |
9dc54a0d CK |
1999 | u64 min_chunk = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES); |
2000 | u64 hmminds = max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2); | |
2001 | u64 chunk_size; | |
92dc6895 CH |
2002 | |
2003 | /* start big and work our way down */ | |
9dc54a0d | 2004 | for (chunk_size = min_chunk; chunk_size >= hmminds; chunk_size /= 2) { |
92dc6895 CH |
2005 | if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) { |
2006 | if (!min || dev->host_mem_size >= min) | |
2007 | return 0; | |
2008 | nvme_free_host_mem(dev); | |
2009 | } | |
2010 | } | |
2011 | ||
2012 | return -ENOMEM; | |
2013 | } | |
2014 | ||
9620cfba | 2015 | static int nvme_setup_host_mem(struct nvme_dev *dev) |
87ad72a5 CH |
2016 | { |
2017 | u64 max = (u64)max_host_mem_size_mb * SZ_1M; | |
2018 | u64 preferred = (u64)dev->ctrl.hmpre * 4096; | |
2019 | u64 min = (u64)dev->ctrl.hmmin * 4096; | |
2020 | u32 enable_bits = NVME_HOST_MEM_ENABLE; | |
6fbcde66 | 2021 | int ret; |
87ad72a5 CH |
2022 | |
2023 | preferred = min(preferred, max); | |
2024 | if (min > max) { | |
2025 | dev_warn(dev->ctrl.device, | |
2026 | "min host memory (%lld MiB) above limit (%d MiB).\n", | |
2027 | min >> ilog2(SZ_1M), max_host_mem_size_mb); | |
2028 | nvme_free_host_mem(dev); | |
9620cfba | 2029 | return 0; |
87ad72a5 CH |
2030 | } |
2031 | ||
2032 | /* | |
2033 | * If we already have a buffer allocated check if we can reuse it. | |
2034 | */ | |
2035 | if (dev->host_mem_descs) { | |
2036 | if (dev->host_mem_size >= min) | |
2037 | enable_bits |= NVME_HOST_MEM_RETURN; | |
2038 | else | |
2039 | nvme_free_host_mem(dev); | |
2040 | } | |
2041 | ||
2042 | if (!dev->host_mem_descs) { | |
92dc6895 CH |
2043 | if (nvme_alloc_host_mem(dev, min, preferred)) { |
2044 | dev_warn(dev->ctrl.device, | |
2045 | "failed to allocate host memory buffer.\n"); | |
9620cfba | 2046 | return 0; /* controller must work without HMB */ |
92dc6895 CH |
2047 | } |
2048 | ||
2049 | dev_info(dev->ctrl.device, | |
2050 | "allocated %lld MiB host memory buffer.\n", | |
2051 | dev->host_mem_size >> ilog2(SZ_1M)); | |
87ad72a5 CH |
2052 | } |
2053 | ||
9620cfba CH |
2054 | ret = nvme_set_host_mem(dev, enable_bits); |
2055 | if (ret) | |
87ad72a5 | 2056 | nvme_free_host_mem(dev); |
9620cfba | 2057 | return ret; |
9d713c2b KB |
2058 | } |
2059 | ||
0521905e KB |
2060 | static ssize_t cmb_show(struct device *dev, struct device_attribute *attr, |
2061 | char *buf) | |
2062 | { | |
2063 | struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); | |
2064 | ||
2065 | return sysfs_emit(buf, "cmbloc : x%08x\ncmbsz : x%08x\n", | |
2066 | ndev->cmbloc, ndev->cmbsz); | |
2067 | } | |
2068 | static DEVICE_ATTR_RO(cmb); | |
2069 | ||
1751e97a KB |
2070 | static ssize_t cmbloc_show(struct device *dev, struct device_attribute *attr, |
2071 | char *buf) | |
2072 | { | |
2073 | struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); | |
2074 | ||
2075 | return sysfs_emit(buf, "%u\n", ndev->cmbloc); | |
2076 | } | |
2077 | static DEVICE_ATTR_RO(cmbloc); | |
2078 | ||
2079 | static ssize_t cmbsz_show(struct device *dev, struct device_attribute *attr, | |
2080 | char *buf) | |
2081 | { | |
2082 | struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); | |
2083 | ||
2084 | return sysfs_emit(buf, "%u\n", ndev->cmbsz); | |
2085 | } | |
2086 | static DEVICE_ATTR_RO(cmbsz); | |
2087 | ||
a5df5e79 KB |
2088 | static ssize_t hmb_show(struct device *dev, struct device_attribute *attr, |
2089 | char *buf) | |
2090 | { | |
2091 | struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); | |
2092 | ||
2093 | return sysfs_emit(buf, "%d\n", ndev->hmb); | |
2094 | } | |
2095 | ||
2096 | static ssize_t hmb_store(struct device *dev, struct device_attribute *attr, | |
2097 | const char *buf, size_t count) | |
2098 | { | |
2099 | struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); | |
2100 | bool new; | |
2101 | int ret; | |
2102 | ||
2103 | if (strtobool(buf, &new) < 0) | |
2104 | return -EINVAL; | |
2105 | ||
2106 | if (new == ndev->hmb) | |
2107 | return count; | |
2108 | ||
2109 | if (new) { | |
2110 | ret = nvme_setup_host_mem(ndev); | |
2111 | } else { | |
2112 | ret = nvme_set_host_mem(ndev, 0); | |
2113 | if (!ret) | |
2114 | nvme_free_host_mem(ndev); | |
2115 | } | |
2116 | ||
2117 | if (ret < 0) | |
2118 | return ret; | |
2119 | ||
2120 | return count; | |
2121 | } | |
2122 | static DEVICE_ATTR_RW(hmb); | |
2123 | ||
0521905e KB |
2124 | static umode_t nvme_pci_attrs_are_visible(struct kobject *kobj, |
2125 | struct attribute *a, int n) | |
2126 | { | |
2127 | struct nvme_ctrl *ctrl = | |
2128 | dev_get_drvdata(container_of(kobj, struct device, kobj)); | |
2129 | struct nvme_dev *dev = to_nvme_dev(ctrl); | |
2130 | ||
1751e97a KB |
2131 | if (a == &dev_attr_cmb.attr || |
2132 | a == &dev_attr_cmbloc.attr || | |
2133 | a == &dev_attr_cmbsz.attr) { | |
2134 | if (!dev->cmbsz) | |
2135 | return 0; | |
2136 | } | |
a5df5e79 KB |
2137 | if (a == &dev_attr_hmb.attr && !ctrl->hmpre) |
2138 | return 0; | |
2139 | ||
0521905e KB |
2140 | return a->mode; |
2141 | } | |
2142 | ||
2143 | static struct attribute *nvme_pci_attrs[] = { | |
2144 | &dev_attr_cmb.attr, | |
1751e97a KB |
2145 | &dev_attr_cmbloc.attr, |
2146 | &dev_attr_cmbsz.attr, | |
a5df5e79 | 2147 | &dev_attr_hmb.attr, |
0521905e KB |
2148 | NULL, |
2149 | }; | |
2150 | ||
2151 | static const struct attribute_group nvme_pci_attr_group = { | |
2152 | .attrs = nvme_pci_attrs, | |
2153 | .is_visible = nvme_pci_attrs_are_visible, | |
2154 | }; | |
2155 | ||
612b7286 ML |
2156 | /* |
2157 | * nirqs is the number of interrupts available for write and read | |
2158 | * queues. The core already reserved an interrupt for the admin queue. | |
2159 | */ | |
2160 | static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs) | |
3b6592f7 | 2161 | { |
612b7286 | 2162 | struct nvme_dev *dev = affd->priv; |
2a5bcfdd | 2163 | unsigned int nr_read_queues, nr_write_queues = dev->nr_write_queues; |
3b6592f7 JA |
2164 | |
2165 | /* | |
ee0d96d3 | 2166 | * If there is no interrupt available for queues, ensure that |
612b7286 ML |
2167 | * the default queue is set to 1. The affinity set size is |
2168 | * also set to one, but the irq core ignores it for this case. | |
2169 | * | |
2170 | * If only one interrupt is available or 'write_queue' == 0, combine | |
2171 | * write and read queues. | |
2172 | * | |
2173 | * If 'write_queues' > 0, ensure it leaves room for at least one read | |
2174 | * queue. | |
3b6592f7 | 2175 | */ |
612b7286 ML |
2176 | if (!nrirqs) { |
2177 | nrirqs = 1; | |
2178 | nr_read_queues = 0; | |
2a5bcfdd | 2179 | } else if (nrirqs == 1 || !nr_write_queues) { |
612b7286 | 2180 | nr_read_queues = 0; |
2a5bcfdd | 2181 | } else if (nr_write_queues >= nrirqs) { |
612b7286 | 2182 | nr_read_queues = 1; |
3b6592f7 | 2183 | } else { |
2a5bcfdd | 2184 | nr_read_queues = nrirqs - nr_write_queues; |
3b6592f7 | 2185 | } |
612b7286 ML |
2186 | |
2187 | dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues; | |
2188 | affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues; | |
2189 | dev->io_queues[HCTX_TYPE_READ] = nr_read_queues; | |
2190 | affd->set_size[HCTX_TYPE_READ] = nr_read_queues; | |
2191 | affd->nr_sets = nr_read_queues ? 2 : 1; | |
3b6592f7 JA |
2192 | } |
2193 | ||
6451fe73 | 2194 | static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues) |
3b6592f7 JA |
2195 | { |
2196 | struct pci_dev *pdev = to_pci_dev(dev->dev); | |
3b6592f7 | 2197 | struct irq_affinity affd = { |
9cfef55b | 2198 | .pre_vectors = 1, |
612b7286 ML |
2199 | .calc_sets = nvme_calc_irq_sets, |
2200 | .priv = dev, | |
3b6592f7 | 2201 | }; |
21cc2f3f | 2202 | unsigned int irq_queues, poll_queues; |
6451fe73 JA |
2203 | |
2204 | /* | |
21cc2f3f JX |
2205 | * Poll queues don't need interrupts, but we need at least one I/O queue |
2206 | * left over for non-polled I/O. | |
6451fe73 | 2207 | */ |
21cc2f3f JX |
2208 | poll_queues = min(dev->nr_poll_queues, nr_io_queues - 1); |
2209 | dev->io_queues[HCTX_TYPE_POLL] = poll_queues; | |
3b6592f7 | 2210 | |
21cc2f3f JX |
2211 | /* |
2212 | * Initialize for the single interrupt case, will be updated in | |
2213 | * nvme_calc_irq_sets(). | |
2214 | */ | |
612b7286 ML |
2215 | dev->io_queues[HCTX_TYPE_DEFAULT] = 1; |
2216 | dev->io_queues[HCTX_TYPE_READ] = 0; | |
3b6592f7 | 2217 | |
66341331 | 2218 | /* |
21cc2f3f JX |
2219 | * We need interrupts for the admin queue and each non-polled I/O queue, |
2220 | * but some Apple controllers require all queues to use the first | |
2221 | * vector. | |
66341331 | 2222 | */ |
21cc2f3f JX |
2223 | irq_queues = 1; |
2224 | if (!(dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR)) | |
2225 | irq_queues += (nr_io_queues - poll_queues); | |
612b7286 ML |
2226 | return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues, |
2227 | PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd); | |
3b6592f7 JA |
2228 | } |
2229 | ||
8fae268b KB |
2230 | static void nvme_disable_io_queues(struct nvme_dev *dev) |
2231 | { | |
2232 | if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq)) | |
2233 | __nvme_disable_io_queues(dev, nvme_admin_delete_cq); | |
2234 | } | |
2235 | ||
2a5bcfdd WZ |
2236 | static unsigned int nvme_max_io_queues(struct nvme_dev *dev) |
2237 | { | |
e3aef095 NS |
2238 | /* |
2239 | * If tags are shared with admin queue (Apple bug), then | |
2240 | * make sure we only use one IO queue. | |
2241 | */ | |
2242 | if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) | |
2243 | return 1; | |
2a5bcfdd WZ |
2244 | return num_possible_cpus() + dev->nr_write_queues + dev->nr_poll_queues; |
2245 | } | |
2246 | ||
8d85fce7 | 2247 | static int nvme_setup_io_queues(struct nvme_dev *dev) |
b60503ba | 2248 | { |
147b27e4 | 2249 | struct nvme_queue *adminq = &dev->queues[0]; |
e75ec752 | 2250 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
2a5bcfdd | 2251 | unsigned int nr_io_queues; |
97f6ef64 | 2252 | unsigned long size; |
2a5bcfdd | 2253 | int result; |
b60503ba | 2254 | |
2a5bcfdd WZ |
2255 | /* |
2256 | * Sample the module parameters once at reset time so that we have | |
2257 | * stable values to work with. | |
2258 | */ | |
2259 | dev->nr_write_queues = write_queues; | |
2260 | dev->nr_poll_queues = poll_queues; | |
d38e9f04 | 2261 | |
e3aef095 | 2262 | nr_io_queues = dev->nr_allocated_queues - 1; |
9a0be7ab CH |
2263 | result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues); |
2264 | if (result < 0) | |
1b23484b | 2265 | return result; |
9a0be7ab | 2266 | |
f5fa90dc | 2267 | if (nr_io_queues == 0) |
a5229050 | 2268 | return 0; |
53dc180e | 2269 | |
e4b9852a CC |
2270 | /* |
2271 | * Free IRQ resources as soon as NVMEQ_ENABLED bit transitions | |
2272 | * from set to unset. If there is a window to it is truely freed, | |
2273 | * pci_free_irq_vectors() jumping into this window will crash. | |
2274 | * And take lock to avoid racing with pci_free_irq_vectors() in | |
2275 | * nvme_dev_disable() path. | |
2276 | */ | |
2277 | result = nvme_setup_io_queues_trylock(dev); | |
2278 | if (result) | |
2279 | return result; | |
2280 | if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags)) | |
2281 | pci_free_irq(pdev, 0, adminq); | |
b60503ba | 2282 | |
0f238ff5 | 2283 | if (dev->cmb_use_sqes) { |
8ffaadf7 JD |
2284 | result = nvme_cmb_qdepth(dev, nr_io_queues, |
2285 | sizeof(struct nvme_command)); | |
2286 | if (result > 0) | |
2287 | dev->q_depth = result; | |
2288 | else | |
0f238ff5 | 2289 | dev->cmb_use_sqes = false; |
8ffaadf7 JD |
2290 | } |
2291 | ||
97f6ef64 XY |
2292 | do { |
2293 | size = db_bar_size(dev, nr_io_queues); | |
2294 | result = nvme_remap_bar(dev, size); | |
2295 | if (!result) | |
2296 | break; | |
e4b9852a CC |
2297 | if (!--nr_io_queues) { |
2298 | result = -ENOMEM; | |
2299 | goto out_unlock; | |
2300 | } | |
97f6ef64 XY |
2301 | } while (1); |
2302 | adminq->q_db = dev->dbs; | |
f1938f6e | 2303 | |
8fae268b | 2304 | retry: |
9d713c2b | 2305 | /* Deregister the admin queue's interrupt */ |
e4b9852a CC |
2306 | if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags)) |
2307 | pci_free_irq(pdev, 0, adminq); | |
9d713c2b | 2308 | |
e32efbfc JA |
2309 | /* |
2310 | * If we enable msix early due to not intx, disable it again before | |
2311 | * setting up the full range we need. | |
2312 | */ | |
dca51e78 | 2313 | pci_free_irq_vectors(pdev); |
3b6592f7 JA |
2314 | |
2315 | result = nvme_setup_irqs(dev, nr_io_queues); | |
e4b9852a CC |
2316 | if (result <= 0) { |
2317 | result = -EIO; | |
2318 | goto out_unlock; | |
2319 | } | |
3b6592f7 | 2320 | |
22b55601 | 2321 | dev->num_vecs = result; |
4b04cc6a | 2322 | result = max(result - 1, 1); |
e20ba6e1 | 2323 | dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL]; |
fa08a396 | 2324 | |
063a8096 MW |
2325 | /* |
2326 | * Should investigate if there's a performance win from allocating | |
2327 | * more queues than interrupt vectors; it might allow the submission | |
2328 | * path to scale better, even if the receive path is limited by the | |
2329 | * number of interrupts. | |
2330 | */ | |
dca51e78 | 2331 | result = queue_request_irq(adminq); |
7c349dde | 2332 | if (result) |
e4b9852a | 2333 | goto out_unlock; |
4e224106 | 2334 | set_bit(NVMEQ_ENABLED, &adminq->flags); |
e4b9852a | 2335 | mutex_unlock(&dev->shutdown_lock); |
8fae268b KB |
2336 | |
2337 | result = nvme_create_io_queues(dev); | |
2338 | if (result || dev->online_queues < 2) | |
2339 | return result; | |
2340 | ||
2341 | if (dev->online_queues - 1 < dev->max_qid) { | |
2342 | nr_io_queues = dev->online_queues - 1; | |
2343 | nvme_disable_io_queues(dev); | |
e4b9852a CC |
2344 | result = nvme_setup_io_queues_trylock(dev); |
2345 | if (result) | |
2346 | return result; | |
8fae268b KB |
2347 | nvme_suspend_io_queues(dev); |
2348 | goto retry; | |
2349 | } | |
2350 | dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n", | |
2351 | dev->io_queues[HCTX_TYPE_DEFAULT], | |
2352 | dev->io_queues[HCTX_TYPE_READ], | |
2353 | dev->io_queues[HCTX_TYPE_POLL]); | |
2354 | return 0; | |
e4b9852a CC |
2355 | out_unlock: |
2356 | mutex_unlock(&dev->shutdown_lock); | |
2357 | return result; | |
b60503ba MW |
2358 | } |
2359 | ||
2a842aca | 2360 | static void nvme_del_queue_end(struct request *req, blk_status_t error) |
a5768aa8 | 2361 | { |
db3cbfff | 2362 | struct nvme_queue *nvmeq = req->end_io_data; |
b5875222 | 2363 | |
db3cbfff | 2364 | blk_mq_free_request(req); |
d1ed6aa1 | 2365 | complete(&nvmeq->delete_done); |
a5768aa8 KB |
2366 | } |
2367 | ||
2a842aca | 2368 | static void nvme_del_cq_end(struct request *req, blk_status_t error) |
a5768aa8 | 2369 | { |
db3cbfff | 2370 | struct nvme_queue *nvmeq = req->end_io_data; |
a5768aa8 | 2371 | |
d1ed6aa1 CH |
2372 | if (error) |
2373 | set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); | |
db3cbfff KB |
2374 | |
2375 | nvme_del_queue_end(req, error); | |
a5768aa8 KB |
2376 | } |
2377 | ||
db3cbfff | 2378 | static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode) |
bda4e0fb | 2379 | { |
db3cbfff KB |
2380 | struct request_queue *q = nvmeq->dev->ctrl.admin_q; |
2381 | struct request *req; | |
f66e2804 | 2382 | struct nvme_command cmd = { }; |
bda4e0fb | 2383 | |
db3cbfff KB |
2384 | cmd.delete_queue.opcode = opcode; |
2385 | cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid); | |
bda4e0fb | 2386 | |
39dfe844 | 2387 | req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT); |
db3cbfff KB |
2388 | if (IS_ERR(req)) |
2389 | return PTR_ERR(req); | |
bda4e0fb | 2390 | |
db3cbfff KB |
2391 | req->end_io_data = nvmeq; |
2392 | ||
d1ed6aa1 | 2393 | init_completion(&nvmeq->delete_done); |
8eeed0b5 | 2394 | blk_execute_rq_nowait(NULL, req, false, |
db3cbfff KB |
2395 | opcode == nvme_admin_delete_cq ? |
2396 | nvme_del_cq_end : nvme_del_queue_end); | |
2397 | return 0; | |
bda4e0fb KB |
2398 | } |
2399 | ||
8fae268b | 2400 | static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode) |
a5768aa8 | 2401 | { |
5271edd4 | 2402 | int nr_queues = dev->online_queues - 1, sent = 0; |
db3cbfff | 2403 | unsigned long timeout; |
a5768aa8 | 2404 | |
db3cbfff | 2405 | retry: |
dc96f938 | 2406 | timeout = NVME_ADMIN_TIMEOUT; |
5271edd4 CH |
2407 | while (nr_queues > 0) { |
2408 | if (nvme_delete_queue(&dev->queues[nr_queues], opcode)) | |
2409 | break; | |
2410 | nr_queues--; | |
2411 | sent++; | |
db3cbfff | 2412 | } |
d1ed6aa1 CH |
2413 | while (sent) { |
2414 | struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent]; | |
2415 | ||
2416 | timeout = wait_for_completion_io_timeout(&nvmeq->delete_done, | |
5271edd4 CH |
2417 | timeout); |
2418 | if (timeout == 0) | |
2419 | return false; | |
d1ed6aa1 | 2420 | |
d1ed6aa1 | 2421 | sent--; |
5271edd4 CH |
2422 | if (nr_queues) |
2423 | goto retry; | |
2424 | } | |
2425 | return true; | |
a5768aa8 KB |
2426 | } |
2427 | ||
5d02a5c1 | 2428 | static void nvme_dev_add(struct nvme_dev *dev) |
b60503ba | 2429 | { |
2b1b7e78 JW |
2430 | int ret; |
2431 | ||
5bae7f73 | 2432 | if (!dev->ctrl.tagset) { |
376f7ef8 | 2433 | dev->tagset.ops = &nvme_mq_ops; |
ffe7704d | 2434 | dev->tagset.nr_hw_queues = dev->online_queues - 1; |
8fe34be1 | 2435 | dev->tagset.nr_maps = 2; /* default + read */ |
ed92ad37 CH |
2436 | if (dev->io_queues[HCTX_TYPE_POLL]) |
2437 | dev->tagset.nr_maps++; | |
ffe7704d | 2438 | dev->tagset.timeout = NVME_IO_TIMEOUT; |
d4ec47f1 | 2439 | dev->tagset.numa_node = dev->ctrl.numa_node; |
61f3b896 CK |
2440 | dev->tagset.queue_depth = min_t(unsigned int, dev->q_depth, |
2441 | BLK_MQ_MAX_DEPTH) - 1; | |
d43f1ccf | 2442 | dev->tagset.cmd_size = sizeof(struct nvme_iod); |
ffe7704d KB |
2443 | dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE; |
2444 | dev->tagset.driver_data = dev; | |
b60503ba | 2445 | |
d38e9f04 BH |
2446 | /* |
2447 | * Some Apple controllers requires tags to be unique | |
2448 | * across admin and IO queue, so reserve the first 32 | |
2449 | * tags of the IO queue. | |
2450 | */ | |
2451 | if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) | |
2452 | dev->tagset.reserved_tags = NVME_AQ_DEPTH; | |
2453 | ||
2b1b7e78 JW |
2454 | ret = blk_mq_alloc_tag_set(&dev->tagset); |
2455 | if (ret) { | |
2456 | dev_warn(dev->ctrl.device, | |
2457 | "IO queues tagset allocation failed %d\n", ret); | |
5d02a5c1 | 2458 | return; |
2b1b7e78 | 2459 | } |
5bae7f73 | 2460 | dev->ctrl.tagset = &dev->tagset; |
949928c1 KB |
2461 | } else { |
2462 | blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1); | |
2463 | ||
2464 | /* Free previously allocated queues that are no longer usable */ | |
2465 | nvme_free_queues(dev, dev->online_queues); | |
ffe7704d | 2466 | } |
949928c1 | 2467 | |
e8fd41bb | 2468 | nvme_dbbuf_set(dev); |
b60503ba MW |
2469 | } |
2470 | ||
b00a726a | 2471 | static int nvme_pci_enable(struct nvme_dev *dev) |
0877cb0d | 2472 | { |
b00a726a | 2473 | int result = -ENOMEM; |
e75ec752 | 2474 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
4bdf2603 | 2475 | int dma_address_bits = 64; |
0877cb0d KB |
2476 | |
2477 | if (pci_enable_device_mem(pdev)) | |
2478 | return result; | |
2479 | ||
0877cb0d | 2480 | pci_set_master(pdev); |
0877cb0d | 2481 | |
4bdf2603 FS |
2482 | if (dev->ctrl.quirks & NVME_QUIRK_DMA_ADDRESS_BITS_48) |
2483 | dma_address_bits = 48; | |
2484 | if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(dma_address_bits))) | |
052d0efa | 2485 | goto disable; |
0877cb0d | 2486 | |
7a67cbea | 2487 | if (readl(dev->bar + NVME_REG_CSTS) == -1) { |
0e53d180 | 2488 | result = -ENODEV; |
b00a726a | 2489 | goto disable; |
0e53d180 | 2490 | } |
e32efbfc JA |
2491 | |
2492 | /* | |
a5229050 KB |
2493 | * Some devices and/or platforms don't advertise or work with INTx |
2494 | * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll | |
2495 | * adjust this later. | |
e32efbfc | 2496 | */ |
dca51e78 CH |
2497 | result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); |
2498 | if (result < 0) | |
2499 | return result; | |
e32efbfc | 2500 | |
20d0dfe6 | 2501 | dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP); |
7a67cbea | 2502 | |
7442ddce | 2503 | dev->q_depth = min_t(u32, NVME_CAP_MQES(dev->ctrl.cap) + 1, |
b27c1e68 | 2504 | io_queue_depth); |
aa22c8e6 | 2505 | dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */ |
20d0dfe6 | 2506 | dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap); |
7a67cbea | 2507 | dev->dbs = dev->bar + 4096; |
1f390c1f | 2508 | |
66341331 BH |
2509 | /* |
2510 | * Some Apple controllers require a non-standard SQE size. | |
2511 | * Interestingly they also seem to ignore the CC:IOSQES register | |
2512 | * so we don't bother updating it here. | |
2513 | */ | |
2514 | if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES) | |
2515 | dev->io_sqes = 7; | |
2516 | else | |
2517 | dev->io_sqes = NVME_NVM_IOSQES; | |
1f390c1f SG |
2518 | |
2519 | /* | |
2520 | * Temporary fix for the Apple controller found in the MacBook8,1 and | |
2521 | * some MacBook7,1 to avoid controller resets and data loss. | |
2522 | */ | |
2523 | if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) { | |
2524 | dev->q_depth = 2; | |
9bdcfb10 CH |
2525 | dev_warn(dev->ctrl.device, "detected Apple NVMe controller, " |
2526 | "set queue depth=%u to work around controller resets\n", | |
1f390c1f | 2527 | dev->q_depth); |
d554b5e1 MP |
2528 | } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG && |
2529 | (pdev->device == 0xa821 || pdev->device == 0xa822) && | |
20d0dfe6 | 2530 | NVME_CAP_MQES(dev->ctrl.cap) == 0) { |
d554b5e1 MP |
2531 | dev->q_depth = 64; |
2532 | dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, " | |
2533 | "set queue depth=%u\n", dev->q_depth); | |
1f390c1f SG |
2534 | } |
2535 | ||
d38e9f04 BH |
2536 | /* |
2537 | * Controllers with the shared tags quirk need the IO queue to be | |
2538 | * big enough so that we get 32 tags for the admin queue | |
2539 | */ | |
2540 | if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) && | |
2541 | (dev->q_depth < (NVME_AQ_DEPTH + 2))) { | |
2542 | dev->q_depth = NVME_AQ_DEPTH + 2; | |
2543 | dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n", | |
2544 | dev->q_depth); | |
2545 | } | |
2546 | ||
2547 | ||
f65efd6d | 2548 | nvme_map_cmb(dev); |
202021c1 | 2549 | |
a0a3408e KB |
2550 | pci_enable_pcie_error_reporting(pdev); |
2551 | pci_save_state(pdev); | |
0877cb0d KB |
2552 | return 0; |
2553 | ||
2554 | disable: | |
0877cb0d KB |
2555 | pci_disable_device(pdev); |
2556 | return result; | |
2557 | } | |
2558 | ||
2559 | static void nvme_dev_unmap(struct nvme_dev *dev) | |
b00a726a KB |
2560 | { |
2561 | if (dev->bar) | |
2562 | iounmap(dev->bar); | |
a1f447b3 | 2563 | pci_release_mem_regions(to_pci_dev(dev->dev)); |
b00a726a KB |
2564 | } |
2565 | ||
2566 | static void nvme_pci_disable(struct nvme_dev *dev) | |
0877cb0d | 2567 | { |
e75ec752 CH |
2568 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
2569 | ||
dca51e78 | 2570 | pci_free_irq_vectors(pdev); |
0877cb0d | 2571 | |
a0a3408e KB |
2572 | if (pci_is_enabled(pdev)) { |
2573 | pci_disable_pcie_error_reporting(pdev); | |
e75ec752 | 2574 | pci_disable_device(pdev); |
4d115420 | 2575 | } |
4d115420 KB |
2576 | } |
2577 | ||
a5cdb68c | 2578 | static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown) |
b60503ba | 2579 | { |
e43269e6 | 2580 | bool dead = true, freeze = false; |
302ad8cc | 2581 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
22404274 | 2582 | |
77bf25ea | 2583 | mutex_lock(&dev->shutdown_lock); |
302ad8cc KB |
2584 | if (pci_is_enabled(pdev)) { |
2585 | u32 csts = readl(dev->bar + NVME_REG_CSTS); | |
2586 | ||
ebef7368 | 2587 | if (dev->ctrl.state == NVME_CTRL_LIVE || |
e43269e6 KB |
2588 | dev->ctrl.state == NVME_CTRL_RESETTING) { |
2589 | freeze = true; | |
302ad8cc | 2590 | nvme_start_freeze(&dev->ctrl); |
e43269e6 | 2591 | } |
302ad8cc KB |
2592 | dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) || |
2593 | pdev->error_state != pci_channel_io_normal); | |
c9d3bf88 | 2594 | } |
c21377f8 | 2595 | |
302ad8cc KB |
2596 | /* |
2597 | * Give the controller a chance to complete all entered requests if | |
2598 | * doing a safe shutdown. | |
2599 | */ | |
e43269e6 KB |
2600 | if (!dead && shutdown && freeze) |
2601 | nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT); | |
9a915a5b JW |
2602 | |
2603 | nvme_stop_queues(&dev->ctrl); | |
87ad72a5 | 2604 | |
64ee0ac0 | 2605 | if (!dead && dev->ctrl.queue_count > 0) { |
8fae268b | 2606 | nvme_disable_io_queues(dev); |
a5cdb68c | 2607 | nvme_disable_admin_queue(dev, shutdown); |
4d115420 | 2608 | } |
8fae268b KB |
2609 | nvme_suspend_io_queues(dev); |
2610 | nvme_suspend_queue(&dev->queues[0]); | |
b00a726a | 2611 | nvme_pci_disable(dev); |
fa46c6fb | 2612 | nvme_reap_pending_cqes(dev); |
07836e65 | 2613 | |
e1958e65 ML |
2614 | blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl); |
2615 | blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl); | |
622b8b68 ML |
2616 | blk_mq_tagset_wait_completed_request(&dev->tagset); |
2617 | blk_mq_tagset_wait_completed_request(&dev->admin_tagset); | |
302ad8cc KB |
2618 | |
2619 | /* | |
2620 | * The driver will not be starting up queues again if shutting down so | |
2621 | * must flush all entered requests to their failed completion to avoid | |
2622 | * deadlocking blk-mq hot-cpu notifier. | |
2623 | */ | |
c8e9e9b7 | 2624 | if (shutdown) { |
302ad8cc | 2625 | nvme_start_queues(&dev->ctrl); |
c8e9e9b7 KB |
2626 | if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) |
2627 | blk_mq_unquiesce_queue(dev->ctrl.admin_q); | |
2628 | } | |
77bf25ea | 2629 | mutex_unlock(&dev->shutdown_lock); |
b60503ba MW |
2630 | } |
2631 | ||
c1ac9a4b KB |
2632 | static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown) |
2633 | { | |
2634 | if (!nvme_wait_reset(&dev->ctrl)) | |
2635 | return -EBUSY; | |
2636 | nvme_dev_disable(dev, shutdown); | |
2637 | return 0; | |
2638 | } | |
2639 | ||
091b6092 MW |
2640 | static int nvme_setup_prp_pools(struct nvme_dev *dev) |
2641 | { | |
e75ec752 | 2642 | dev->prp_page_pool = dma_pool_create("prp list page", dev->dev, |
c61b82c7 CH |
2643 | NVME_CTRL_PAGE_SIZE, |
2644 | NVME_CTRL_PAGE_SIZE, 0); | |
091b6092 MW |
2645 | if (!dev->prp_page_pool) |
2646 | return -ENOMEM; | |
2647 | ||
99802a7a | 2648 | /* Optimisation for I/Os between 4k and 128k */ |
e75ec752 | 2649 | dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev, |
99802a7a MW |
2650 | 256, 256, 0); |
2651 | if (!dev->prp_small_pool) { | |
2652 | dma_pool_destroy(dev->prp_page_pool); | |
2653 | return -ENOMEM; | |
2654 | } | |
091b6092 MW |
2655 | return 0; |
2656 | } | |
2657 | ||
2658 | static void nvme_release_prp_pools(struct nvme_dev *dev) | |
2659 | { | |
2660 | dma_pool_destroy(dev->prp_page_pool); | |
99802a7a | 2661 | dma_pool_destroy(dev->prp_small_pool); |
091b6092 MW |
2662 | } |
2663 | ||
770597ec KB |
2664 | static void nvme_free_tagset(struct nvme_dev *dev) |
2665 | { | |
2666 | if (dev->tagset.tags) | |
2667 | blk_mq_free_tag_set(&dev->tagset); | |
2668 | dev->ctrl.tagset = NULL; | |
2669 | } | |
2670 | ||
1673f1f0 | 2671 | static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl) |
5e82e952 | 2672 | { |
1673f1f0 | 2673 | struct nvme_dev *dev = to_nvme_dev(ctrl); |
9ac27090 | 2674 | |
f9f38e33 | 2675 | nvme_dbbuf_dma_free(dev); |
770597ec | 2676 | nvme_free_tagset(dev); |
1c63dc66 CH |
2677 | if (dev->ctrl.admin_q) |
2678 | blk_put_queue(dev->ctrl.admin_q); | |
e286bcfc | 2679 | free_opal_dev(dev->ctrl.opal_dev); |
943e942e | 2680 | mempool_destroy(dev->iod_mempool); |
253fd4ac IR |
2681 | put_device(dev->dev); |
2682 | kfree(dev->queues); | |
5e82e952 KB |
2683 | kfree(dev); |
2684 | } | |
2685 | ||
7c1ce408 | 2686 | static void nvme_remove_dead_ctrl(struct nvme_dev *dev) |
f58944e2 | 2687 | { |
c1ac9a4b KB |
2688 | /* |
2689 | * Set state to deleting now to avoid blocking nvme_wait_reset(), which | |
2690 | * may be holding this pci_dev's device lock. | |
2691 | */ | |
2692 | nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); | |
d22524a4 | 2693 | nvme_get_ctrl(&dev->ctrl); |
69d9a99c | 2694 | nvme_dev_disable(dev, false); |
9f9cafc1 | 2695 | nvme_kill_queues(&dev->ctrl); |
03e0f3a6 | 2696 | if (!queue_work(nvme_wq, &dev->remove_work)) |
f58944e2 KB |
2697 | nvme_put_ctrl(&dev->ctrl); |
2698 | } | |
2699 | ||
fd634f41 | 2700 | static void nvme_reset_work(struct work_struct *work) |
5e82e952 | 2701 | { |
d86c4d8e CH |
2702 | struct nvme_dev *dev = |
2703 | container_of(work, struct nvme_dev, ctrl.reset_work); | |
a98e58e5 | 2704 | bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL); |
e71afda4 | 2705 | int result; |
5e82e952 | 2706 | |
7764656b ZC |
2707 | if (dev->ctrl.state != NVME_CTRL_RESETTING) { |
2708 | dev_warn(dev->ctrl.device, "ctrl state %d is not RESETTING\n", | |
2709 | dev->ctrl.state); | |
e71afda4 | 2710 | result = -ENODEV; |
fd634f41 | 2711 | goto out; |
e71afda4 | 2712 | } |
5e82e952 | 2713 | |
fd634f41 CH |
2714 | /* |
2715 | * If we're called to reset a live controller first shut it down before | |
2716 | * moving on. | |
2717 | */ | |
b00a726a | 2718 | if (dev->ctrl.ctrl_config & NVME_CC_ENABLE) |
a5cdb68c | 2719 | nvme_dev_disable(dev, false); |
d6135c3a | 2720 | nvme_sync_queues(&dev->ctrl); |
5e82e952 | 2721 | |
5c959d73 | 2722 | mutex_lock(&dev->shutdown_lock); |
b00a726a | 2723 | result = nvme_pci_enable(dev); |
f0b50732 | 2724 | if (result) |
4726bcf3 | 2725 | goto out_unlock; |
f0b50732 | 2726 | |
01ad0990 | 2727 | result = nvme_pci_configure_admin_queue(dev); |
f0b50732 | 2728 | if (result) |
4726bcf3 | 2729 | goto out_unlock; |
f0b50732 | 2730 | |
0fb59cbc KB |
2731 | result = nvme_alloc_admin_tags(dev); |
2732 | if (result) | |
4726bcf3 | 2733 | goto out_unlock; |
b9afca3e | 2734 | |
943e942e JA |
2735 | /* |
2736 | * Limit the max command size to prevent iod->sg allocations going | |
2737 | * over a single page. | |
2738 | */ | |
7637de31 CH |
2739 | dev->ctrl.max_hw_sectors = min_t(u32, |
2740 | NVME_MAX_KB_SZ << 1, dma_max_mapping_size(dev->dev) >> 9); | |
943e942e | 2741 | dev->ctrl.max_segments = NVME_MAX_SEGS; |
a48bc520 CH |
2742 | |
2743 | /* | |
2744 | * Don't limit the IOMMU merged segment size. | |
2745 | */ | |
2746 | dma_set_max_seg_size(dev->dev, 0xffffffff); | |
3d2d861e | 2747 | dma_set_min_align_mask(dev->dev, NVME_CTRL_PAGE_SIZE - 1); |
a48bc520 | 2748 | |
5c959d73 KB |
2749 | mutex_unlock(&dev->shutdown_lock); |
2750 | ||
2751 | /* | |
2752 | * Introduce CONNECTING state from nvme-fc/rdma transports to mark the | |
2753 | * initializing procedure here. | |
2754 | */ | |
2755 | if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) { | |
2756 | dev_warn(dev->ctrl.device, | |
2757 | "failed to mark controller CONNECTING\n"); | |
cee6c269 | 2758 | result = -EBUSY; |
5c959d73 KB |
2759 | goto out; |
2760 | } | |
943e942e | 2761 | |
95093350 MG |
2762 | /* |
2763 | * We do not support an SGL for metadata (yet), so we are limited to a | |
2764 | * single integrity segment for the separate metadata pointer. | |
2765 | */ | |
2766 | dev->ctrl.max_integrity_segments = 1; | |
2767 | ||
f21c4769 | 2768 | result = nvme_init_ctrl_finish(&dev->ctrl); |
ce4541f4 | 2769 | if (result) |
f58944e2 | 2770 | goto out; |
ce4541f4 | 2771 | |
e286bcfc SB |
2772 | if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) { |
2773 | if (!dev->ctrl.opal_dev) | |
2774 | dev->ctrl.opal_dev = | |
2775 | init_opal_dev(&dev->ctrl, &nvme_sec_submit); | |
2776 | else if (was_suspend) | |
2777 | opal_unlock_from_suspend(dev->ctrl.opal_dev); | |
2778 | } else { | |
2779 | free_opal_dev(dev->ctrl.opal_dev); | |
2780 | dev->ctrl.opal_dev = NULL; | |
4f1244c8 | 2781 | } |
a98e58e5 | 2782 | |
f9f38e33 HK |
2783 | if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) { |
2784 | result = nvme_dbbuf_dma_alloc(dev); | |
2785 | if (result) | |
2786 | dev_warn(dev->dev, | |
2787 | "unable to allocate dma for dbbuf\n"); | |
2788 | } | |
2789 | ||
9620cfba CH |
2790 | if (dev->ctrl.hmpre) { |
2791 | result = nvme_setup_host_mem(dev); | |
2792 | if (result < 0) | |
2793 | goto out; | |
2794 | } | |
87ad72a5 | 2795 | |
f0b50732 | 2796 | result = nvme_setup_io_queues(dev); |
badc34d4 | 2797 | if (result) |
f58944e2 | 2798 | goto out; |
f0b50732 | 2799 | |
2659e57b CH |
2800 | /* |
2801 | * Keep the controller around but remove all namespaces if we don't have | |
2802 | * any working I/O queue. | |
2803 | */ | |
3cf519b5 | 2804 | if (dev->online_queues < 2) { |
1b3c47c1 | 2805 | dev_warn(dev->ctrl.device, "IO queues not created\n"); |
3b24774e | 2806 | nvme_kill_queues(&dev->ctrl); |
5bae7f73 | 2807 | nvme_remove_namespaces(&dev->ctrl); |
770597ec | 2808 | nvme_free_tagset(dev); |
3cf519b5 | 2809 | } else { |
25646264 | 2810 | nvme_start_queues(&dev->ctrl); |
302ad8cc | 2811 | nvme_wait_freeze(&dev->ctrl); |
5d02a5c1 | 2812 | nvme_dev_add(dev); |
302ad8cc | 2813 | nvme_unfreeze(&dev->ctrl); |
3cf519b5 CH |
2814 | } |
2815 | ||
2b1b7e78 JW |
2816 | /* |
2817 | * If only admin queue live, keep it to do further investigation or | |
2818 | * recovery. | |
2819 | */ | |
5d02a5c1 | 2820 | if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) { |
2b1b7e78 | 2821 | dev_warn(dev->ctrl.device, |
5d02a5c1 | 2822 | "failed to mark controller live state\n"); |
e71afda4 | 2823 | result = -ENODEV; |
bb8d261e CH |
2824 | goto out; |
2825 | } | |
92911a55 | 2826 | |
0521905e KB |
2827 | if (!dev->attrs_added && !sysfs_create_group(&dev->ctrl.device->kobj, |
2828 | &nvme_pci_attr_group)) | |
2829 | dev->attrs_added = true; | |
2830 | ||
d09f2b45 | 2831 | nvme_start_ctrl(&dev->ctrl); |
3cf519b5 | 2832 | return; |
f0b50732 | 2833 | |
4726bcf3 KB |
2834 | out_unlock: |
2835 | mutex_unlock(&dev->shutdown_lock); | |
3cf519b5 | 2836 | out: |
7c1ce408 CK |
2837 | if (result) |
2838 | dev_warn(dev->ctrl.device, | |
2839 | "Removing after probe failure status: %d\n", result); | |
2840 | nvme_remove_dead_ctrl(dev); | |
f0b50732 KB |
2841 | } |
2842 | ||
5c8809e6 | 2843 | static void nvme_remove_dead_ctrl_work(struct work_struct *work) |
9a6b9458 | 2844 | { |
5c8809e6 | 2845 | struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work); |
e75ec752 | 2846 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
9a6b9458 KB |
2847 | |
2848 | if (pci_get_drvdata(pdev)) | |
921920ab | 2849 | device_release_driver(&pdev->dev); |
1673f1f0 | 2850 | nvme_put_ctrl(&dev->ctrl); |
9a6b9458 KB |
2851 | } |
2852 | ||
1c63dc66 | 2853 | static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val) |
9ca97374 | 2854 | { |
1c63dc66 | 2855 | *val = readl(to_nvme_dev(ctrl)->bar + off); |
90667892 | 2856 | return 0; |
9ca97374 TH |
2857 | } |
2858 | ||
5fd4ce1b | 2859 | static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val) |
4cc06521 | 2860 | { |
5fd4ce1b CH |
2861 | writel(val, to_nvme_dev(ctrl)->bar + off); |
2862 | return 0; | |
2863 | } | |
4cc06521 | 2864 | |
7fd8930f CH |
2865 | static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val) |
2866 | { | |
3a8ecc93 | 2867 | *val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off); |
7fd8930f | 2868 | return 0; |
4cc06521 KB |
2869 | } |
2870 | ||
97c12223 KB |
2871 | static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size) |
2872 | { | |
2873 | struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev); | |
2874 | ||
2db24e4a | 2875 | return snprintf(buf, size, "%s\n", dev_name(&pdev->dev)); |
97c12223 KB |
2876 | } |
2877 | ||
1c63dc66 | 2878 | static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = { |
1a353d85 | 2879 | .name = "pcie", |
e439bb12 | 2880 | .module = THIS_MODULE, |
e0596ab2 LG |
2881 | .flags = NVME_F_METADATA_SUPPORTED | |
2882 | NVME_F_PCI_P2PDMA, | |
1c63dc66 | 2883 | .reg_read32 = nvme_pci_reg_read32, |
5fd4ce1b | 2884 | .reg_write32 = nvme_pci_reg_write32, |
7fd8930f | 2885 | .reg_read64 = nvme_pci_reg_read64, |
1673f1f0 | 2886 | .free_ctrl = nvme_pci_free_ctrl, |
f866fc42 | 2887 | .submit_async_event = nvme_pci_submit_async_event, |
97c12223 | 2888 | .get_address = nvme_pci_get_address, |
1c63dc66 | 2889 | }; |
4cc06521 | 2890 | |
b00a726a KB |
2891 | static int nvme_dev_map(struct nvme_dev *dev) |
2892 | { | |
b00a726a KB |
2893 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
2894 | ||
a1f447b3 | 2895 | if (pci_request_mem_regions(pdev, "nvme")) |
b00a726a KB |
2896 | return -ENODEV; |
2897 | ||
97f6ef64 | 2898 | if (nvme_remap_bar(dev, NVME_REG_DBS + 4096)) |
b00a726a KB |
2899 | goto release; |
2900 | ||
9fa196e7 | 2901 | return 0; |
b00a726a | 2902 | release: |
9fa196e7 MG |
2903 | pci_release_mem_regions(pdev); |
2904 | return -ENODEV; | |
b00a726a KB |
2905 | } |
2906 | ||
8427bbc2 | 2907 | static unsigned long check_vendor_combination_bug(struct pci_dev *pdev) |
ff5350a8 AL |
2908 | { |
2909 | if (pdev->vendor == 0x144d && pdev->device == 0xa802) { | |
2910 | /* | |
2911 | * Several Samsung devices seem to drop off the PCIe bus | |
2912 | * randomly when APST is on and uses the deepest sleep state. | |
2913 | * This has been observed on a Samsung "SM951 NVMe SAMSUNG | |
2914 | * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD | |
2915 | * 950 PRO 256GB", but it seems to be restricted to two Dell | |
2916 | * laptops. | |
2917 | */ | |
2918 | if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") && | |
2919 | (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") || | |
2920 | dmi_match(DMI_PRODUCT_NAME, "Precision 5510"))) | |
2921 | return NVME_QUIRK_NO_DEEPEST_PS; | |
8427bbc2 KHF |
2922 | } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) { |
2923 | /* | |
2924 | * Samsung SSD 960 EVO drops off the PCIe bus after system | |
467c77d4 JJ |
2925 | * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as |
2926 | * within few minutes after bootup on a Coffee Lake board - | |
2927 | * ASUS PRIME Z370-A | |
8427bbc2 KHF |
2928 | */ |
2929 | if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") && | |
467c77d4 JJ |
2930 | (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") || |
2931 | dmi_match(DMI_BOARD_NAME, "PRIME Z370-A"))) | |
8427bbc2 | 2932 | return NVME_QUIRK_NO_APST; |
1fae37ac S |
2933 | } else if ((pdev->vendor == 0x144d && (pdev->device == 0xa801 || |
2934 | pdev->device == 0xa808 || pdev->device == 0xa809)) || | |
2935 | (pdev->vendor == 0x1e0f && pdev->device == 0x0001)) { | |
2936 | /* | |
2937 | * Forcing to use host managed nvme power settings for | |
2938 | * lowest idle power with quick resume latency on | |
2939 | * Samsung and Toshiba SSDs based on suspend behavior | |
2940 | * on Coffee Lake board for LENOVO C640 | |
2941 | */ | |
2942 | if ((dmi_match(DMI_BOARD_VENDOR, "LENOVO")) && | |
2943 | dmi_match(DMI_BOARD_NAME, "LNVNB161216")) | |
2944 | return NVME_QUIRK_SIMPLE_SUSPEND; | |
ff5350a8 AL |
2945 | } |
2946 | ||
2947 | return 0; | |
2948 | } | |
2949 | ||
18119775 KB |
2950 | static void nvme_async_probe(void *data, async_cookie_t cookie) |
2951 | { | |
2952 | struct nvme_dev *dev = data; | |
80f513b5 | 2953 | |
bd46a906 | 2954 | flush_work(&dev->ctrl.reset_work); |
18119775 | 2955 | flush_work(&dev->ctrl.scan_work); |
80f513b5 | 2956 | nvme_put_ctrl(&dev->ctrl); |
18119775 KB |
2957 | } |
2958 | ||
8d85fce7 | 2959 | static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) |
b60503ba | 2960 | { |
a4aea562 | 2961 | int node, result = -ENOMEM; |
b60503ba | 2962 | struct nvme_dev *dev; |
ff5350a8 | 2963 | unsigned long quirks = id->driver_data; |
943e942e | 2964 | size_t alloc_size; |
b60503ba | 2965 | |
a4aea562 MB |
2966 | node = dev_to_node(&pdev->dev); |
2967 | if (node == NUMA_NO_NODE) | |
2fa84351 | 2968 | set_dev_node(&pdev->dev, first_memory_node); |
a4aea562 MB |
2969 | |
2970 | dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); | |
b60503ba MW |
2971 | if (!dev) |
2972 | return -ENOMEM; | |
147b27e4 | 2973 | |
2a5bcfdd WZ |
2974 | dev->nr_write_queues = write_queues; |
2975 | dev->nr_poll_queues = poll_queues; | |
2976 | dev->nr_allocated_queues = nvme_max_io_queues(dev) + 1; | |
2977 | dev->queues = kcalloc_node(dev->nr_allocated_queues, | |
2978 | sizeof(struct nvme_queue), GFP_KERNEL, node); | |
b60503ba MW |
2979 | if (!dev->queues) |
2980 | goto free; | |
2981 | ||
e75ec752 | 2982 | dev->dev = get_device(&pdev->dev); |
9a6b9458 | 2983 | pci_set_drvdata(pdev, dev); |
1c63dc66 | 2984 | |
b00a726a KB |
2985 | result = nvme_dev_map(dev); |
2986 | if (result) | |
b00c9b7a | 2987 | goto put_pci; |
b00a726a | 2988 | |
d86c4d8e | 2989 | INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work); |
5c8809e6 | 2990 | INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work); |
77bf25ea | 2991 | mutex_init(&dev->shutdown_lock); |
b60503ba | 2992 | |
091b6092 MW |
2993 | result = nvme_setup_prp_pools(dev); |
2994 | if (result) | |
b00c9b7a | 2995 | goto unmap; |
4cc06521 | 2996 | |
8427bbc2 | 2997 | quirks |= check_vendor_combination_bug(pdev); |
ff5350a8 | 2998 | |
2744d7a0 | 2999 | if (!noacpi && acpi_storage_d3(&pdev->dev)) { |
df4f9bc4 DB |
3000 | /* |
3001 | * Some systems use a bios work around to ask for D3 on | |
3002 | * platforms that support kernel managed suspend. | |
3003 | */ | |
3004 | dev_info(&pdev->dev, | |
3005 | "platform quirk: setting simple suspend\n"); | |
3006 | quirks |= NVME_QUIRK_SIMPLE_SUSPEND; | |
3007 | } | |
3008 | ||
943e942e JA |
3009 | /* |
3010 | * Double check that our mempool alloc size will cover the biggest | |
3011 | * command we support. | |
3012 | */ | |
b13c6393 | 3013 | alloc_size = nvme_pci_iod_alloc_size(); |
943e942e JA |
3014 | WARN_ON_ONCE(alloc_size > PAGE_SIZE); |
3015 | ||
3016 | dev->iod_mempool = mempool_create_node(1, mempool_kmalloc, | |
3017 | mempool_kfree, | |
3018 | (void *) alloc_size, | |
3019 | GFP_KERNEL, node); | |
3020 | if (!dev->iod_mempool) { | |
3021 | result = -ENOMEM; | |
3022 | goto release_pools; | |
3023 | } | |
3024 | ||
b6e44b4c KB |
3025 | result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops, |
3026 | quirks); | |
3027 | if (result) | |
3028 | goto release_mempool; | |
3029 | ||
1b3c47c1 SG |
3030 | dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev)); |
3031 | ||
bd46a906 | 3032 | nvme_reset_ctrl(&dev->ctrl); |
18119775 | 3033 | async_schedule(nvme_async_probe, dev); |
4caff8fc | 3034 | |
b60503ba MW |
3035 | return 0; |
3036 | ||
b6e44b4c KB |
3037 | release_mempool: |
3038 | mempool_destroy(dev->iod_mempool); | |
0877cb0d | 3039 | release_pools: |
091b6092 | 3040 | nvme_release_prp_pools(dev); |
b00c9b7a CJ |
3041 | unmap: |
3042 | nvme_dev_unmap(dev); | |
a96d4f5c | 3043 | put_pci: |
e75ec752 | 3044 | put_device(dev->dev); |
b60503ba MW |
3045 | free: |
3046 | kfree(dev->queues); | |
b60503ba MW |
3047 | kfree(dev); |
3048 | return result; | |
3049 | } | |
3050 | ||
775755ed | 3051 | static void nvme_reset_prepare(struct pci_dev *pdev) |
f0d54a54 | 3052 | { |
a6739479 | 3053 | struct nvme_dev *dev = pci_get_drvdata(pdev); |
c1ac9a4b KB |
3054 | |
3055 | /* | |
3056 | * We don't need to check the return value from waiting for the reset | |
3057 | * state as pci_dev device lock is held, making it impossible to race | |
3058 | * with ->remove(). | |
3059 | */ | |
3060 | nvme_disable_prepare_reset(dev, false); | |
3061 | nvme_sync_queues(&dev->ctrl); | |
775755ed | 3062 | } |
f0d54a54 | 3063 | |
775755ed CH |
3064 | static void nvme_reset_done(struct pci_dev *pdev) |
3065 | { | |
f263fbb8 | 3066 | struct nvme_dev *dev = pci_get_drvdata(pdev); |
c1ac9a4b KB |
3067 | |
3068 | if (!nvme_try_sched_reset(&dev->ctrl)) | |
3069 | flush_work(&dev->ctrl.reset_work); | |
f0d54a54 KB |
3070 | } |
3071 | ||
09ece142 KB |
3072 | static void nvme_shutdown(struct pci_dev *pdev) |
3073 | { | |
3074 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
4e523547 | 3075 | |
c1ac9a4b | 3076 | nvme_disable_prepare_reset(dev, true); |
09ece142 KB |
3077 | } |
3078 | ||
0521905e KB |
3079 | static void nvme_remove_attrs(struct nvme_dev *dev) |
3080 | { | |
3081 | if (dev->attrs_added) | |
3082 | sysfs_remove_group(&dev->ctrl.device->kobj, | |
3083 | &nvme_pci_attr_group); | |
3084 | } | |
3085 | ||
f58944e2 KB |
3086 | /* |
3087 | * The driver's remove may be called on a device in a partially initialized | |
3088 | * state. This function must not have any dependencies on the device state in | |
3089 | * order to proceed. | |
3090 | */ | |
8d85fce7 | 3091 | static void nvme_remove(struct pci_dev *pdev) |
b60503ba MW |
3092 | { |
3093 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
9a6b9458 | 3094 | |
bb8d261e | 3095 | nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); |
9a6b9458 | 3096 | pci_set_drvdata(pdev, NULL); |
0ff9d4e1 | 3097 | |
6db28eda | 3098 | if (!pci_device_is_present(pdev)) { |
0ff9d4e1 | 3099 | nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD); |
1d39e692 | 3100 | nvme_dev_disable(dev, true); |
6db28eda | 3101 | } |
0ff9d4e1 | 3102 | |
d86c4d8e | 3103 | flush_work(&dev->ctrl.reset_work); |
d09f2b45 SG |
3104 | nvme_stop_ctrl(&dev->ctrl); |
3105 | nvme_remove_namespaces(&dev->ctrl); | |
a5cdb68c | 3106 | nvme_dev_disable(dev, true); |
0521905e | 3107 | nvme_remove_attrs(dev); |
87ad72a5 | 3108 | nvme_free_host_mem(dev); |
a4aea562 | 3109 | nvme_dev_remove_admin(dev); |
a1a5ef99 | 3110 | nvme_free_queues(dev, 0); |
9a6b9458 | 3111 | nvme_release_prp_pools(dev); |
b00a726a | 3112 | nvme_dev_unmap(dev); |
726612b6 | 3113 | nvme_uninit_ctrl(&dev->ctrl); |
b60503ba MW |
3114 | } |
3115 | ||
671a6018 | 3116 | #ifdef CONFIG_PM_SLEEP |
d916b1be KB |
3117 | static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps) |
3118 | { | |
3119 | return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps); | |
3120 | } | |
3121 | ||
3122 | static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps) | |
3123 | { | |
3124 | return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL); | |
3125 | } | |
3126 | ||
3127 | static int nvme_resume(struct device *dev) | |
3128 | { | |
3129 | struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev)); | |
3130 | struct nvme_ctrl *ctrl = &ndev->ctrl; | |
3131 | ||
4eaefe8c | 3132 | if (ndev->last_ps == U32_MAX || |
d916b1be | 3133 | nvme_set_power_state(ctrl, ndev->last_ps) != 0) |
e5ad96f3 KB |
3134 | goto reset; |
3135 | if (ctrl->hmpre && nvme_setup_host_mem(ndev)) | |
3136 | goto reset; | |
3137 | ||
d916b1be | 3138 | return 0; |
e5ad96f3 KB |
3139 | reset: |
3140 | return nvme_try_sched_reset(ctrl); | |
d916b1be KB |
3141 | } |
3142 | ||
cd638946 KB |
3143 | static int nvme_suspend(struct device *dev) |
3144 | { | |
3145 | struct pci_dev *pdev = to_pci_dev(dev); | |
3146 | struct nvme_dev *ndev = pci_get_drvdata(pdev); | |
d916b1be KB |
3147 | struct nvme_ctrl *ctrl = &ndev->ctrl; |
3148 | int ret = -EBUSY; | |
3149 | ||
4eaefe8c RW |
3150 | ndev->last_ps = U32_MAX; |
3151 | ||
d916b1be KB |
3152 | /* |
3153 | * The platform does not remove power for a kernel managed suspend so | |
3154 | * use host managed nvme power settings for lowest idle power if | |
3155 | * possible. This should have quicker resume latency than a full device | |
3156 | * shutdown. But if the firmware is involved after the suspend or the | |
3157 | * device does not support any non-default power states, shut down the | |
3158 | * device fully. | |
4eaefe8c RW |
3159 | * |
3160 | * If ASPM is not enabled for the device, shut down the device and allow | |
3161 | * the PCI bus layer to put it into D3 in order to take the PCIe link | |
3162 | * down, so as to allow the platform to achieve its minimum low-power | |
3163 | * state (which may not be possible if the link is up). | |
d916b1be | 3164 | */ |
4eaefe8c | 3165 | if (pm_suspend_via_firmware() || !ctrl->npss || |
cb32de1b | 3166 | !pcie_aspm_enabled(pdev) || |
c1ac9a4b KB |
3167 | (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND)) |
3168 | return nvme_disable_prepare_reset(ndev, true); | |
d916b1be KB |
3169 | |
3170 | nvme_start_freeze(ctrl); | |
3171 | nvme_wait_freeze(ctrl); | |
3172 | nvme_sync_queues(ctrl); | |
3173 | ||
5d02a5c1 | 3174 | if (ctrl->state != NVME_CTRL_LIVE) |
d916b1be KB |
3175 | goto unfreeze; |
3176 | ||
e5ad96f3 KB |
3177 | /* |
3178 | * Host memory access may not be successful in a system suspend state, | |
3179 | * but the specification allows the controller to access memory in a | |
3180 | * non-operational power state. | |
3181 | */ | |
3182 | if (ndev->hmb) { | |
3183 | ret = nvme_set_host_mem(ndev, 0); | |
3184 | if (ret < 0) | |
3185 | goto unfreeze; | |
3186 | } | |
3187 | ||
d916b1be KB |
3188 | ret = nvme_get_power_state(ctrl, &ndev->last_ps); |
3189 | if (ret < 0) | |
3190 | goto unfreeze; | |
3191 | ||
7cbb5c6f ML |
3192 | /* |
3193 | * A saved state prevents pci pm from generically controlling the | |
3194 | * device's power. If we're using protocol specific settings, we don't | |
3195 | * want pci interfering. | |
3196 | */ | |
3197 | pci_save_state(pdev); | |
3198 | ||
d916b1be KB |
3199 | ret = nvme_set_power_state(ctrl, ctrl->npss); |
3200 | if (ret < 0) | |
3201 | goto unfreeze; | |
3202 | ||
3203 | if (ret) { | |
7cbb5c6f ML |
3204 | /* discard the saved state */ |
3205 | pci_load_saved_state(pdev, NULL); | |
3206 | ||
d916b1be KB |
3207 | /* |
3208 | * Clearing npss forces a controller reset on resume. The | |
05d3046f | 3209 | * correct value will be rediscovered then. |
d916b1be | 3210 | */ |
c1ac9a4b | 3211 | ret = nvme_disable_prepare_reset(ndev, true); |
d916b1be | 3212 | ctrl->npss = 0; |
d916b1be | 3213 | } |
d916b1be KB |
3214 | unfreeze: |
3215 | nvme_unfreeze(ctrl); | |
3216 | return ret; | |
3217 | } | |
3218 | ||
3219 | static int nvme_simple_suspend(struct device *dev) | |
3220 | { | |
3221 | struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev)); | |
4e523547 | 3222 | |
c1ac9a4b | 3223 | return nvme_disable_prepare_reset(ndev, true); |
cd638946 KB |
3224 | } |
3225 | ||
d916b1be | 3226 | static int nvme_simple_resume(struct device *dev) |
cd638946 KB |
3227 | { |
3228 | struct pci_dev *pdev = to_pci_dev(dev); | |
3229 | struct nvme_dev *ndev = pci_get_drvdata(pdev); | |
cd638946 | 3230 | |
c1ac9a4b | 3231 | return nvme_try_sched_reset(&ndev->ctrl); |
cd638946 KB |
3232 | } |
3233 | ||
21774222 | 3234 | static const struct dev_pm_ops nvme_dev_pm_ops = { |
d916b1be KB |
3235 | .suspend = nvme_suspend, |
3236 | .resume = nvme_resume, | |
3237 | .freeze = nvme_simple_suspend, | |
3238 | .thaw = nvme_simple_resume, | |
3239 | .poweroff = nvme_simple_suspend, | |
3240 | .restore = nvme_simple_resume, | |
3241 | }; | |
3242 | #endif /* CONFIG_PM_SLEEP */ | |
b60503ba | 3243 | |
a0a3408e KB |
3244 | static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev, |
3245 | pci_channel_state_t state) | |
3246 | { | |
3247 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
3248 | ||
3249 | /* | |
3250 | * A frozen channel requires a reset. When detected, this method will | |
3251 | * shutdown the controller to quiesce. The controller will be restarted | |
3252 | * after the slot reset through driver's slot_reset callback. | |
3253 | */ | |
a0a3408e KB |
3254 | switch (state) { |
3255 | case pci_channel_io_normal: | |
3256 | return PCI_ERS_RESULT_CAN_RECOVER; | |
3257 | case pci_channel_io_frozen: | |
d011fb31 KB |
3258 | dev_warn(dev->ctrl.device, |
3259 | "frozen state error detected, reset controller\n"); | |
a5cdb68c | 3260 | nvme_dev_disable(dev, false); |
a0a3408e KB |
3261 | return PCI_ERS_RESULT_NEED_RESET; |
3262 | case pci_channel_io_perm_failure: | |
d011fb31 KB |
3263 | dev_warn(dev->ctrl.device, |
3264 | "failure state error detected, request disconnect\n"); | |
a0a3408e KB |
3265 | return PCI_ERS_RESULT_DISCONNECT; |
3266 | } | |
3267 | return PCI_ERS_RESULT_NEED_RESET; | |
3268 | } | |
3269 | ||
3270 | static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev) | |
3271 | { | |
3272 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
3273 | ||
1b3c47c1 | 3274 | dev_info(dev->ctrl.device, "restart after slot reset\n"); |
a0a3408e | 3275 | pci_restore_state(pdev); |
d86c4d8e | 3276 | nvme_reset_ctrl(&dev->ctrl); |
a0a3408e KB |
3277 | return PCI_ERS_RESULT_RECOVERED; |
3278 | } | |
3279 | ||
3280 | static void nvme_error_resume(struct pci_dev *pdev) | |
3281 | { | |
72cd4cc2 KB |
3282 | struct nvme_dev *dev = pci_get_drvdata(pdev); |
3283 | ||
3284 | flush_work(&dev->ctrl.reset_work); | |
a0a3408e KB |
3285 | } |
3286 | ||
1d352035 | 3287 | static const struct pci_error_handlers nvme_err_handler = { |
b60503ba | 3288 | .error_detected = nvme_error_detected, |
b60503ba MW |
3289 | .slot_reset = nvme_slot_reset, |
3290 | .resume = nvme_error_resume, | |
775755ed CH |
3291 | .reset_prepare = nvme_reset_prepare, |
3292 | .reset_done = nvme_reset_done, | |
b60503ba MW |
3293 | }; |
3294 | ||
6eb0d698 | 3295 | static const struct pci_device_id nvme_id_table[] = { |
972b13e2 | 3296 | { PCI_VDEVICE(INTEL, 0x0953), /* Intel 750/P3500/P3600/P3700 */ |
08095e70 | 3297 | .driver_data = NVME_QUIRK_STRIPE_SIZE | |
e850fd16 | 3298 | NVME_QUIRK_DEALLOCATE_ZEROES, }, |
972b13e2 | 3299 | { PCI_VDEVICE(INTEL, 0x0a53), /* Intel P3520 */ |
99466e70 | 3300 | .driver_data = NVME_QUIRK_STRIPE_SIZE | |
e850fd16 | 3301 | NVME_QUIRK_DEALLOCATE_ZEROES, }, |
972b13e2 | 3302 | { PCI_VDEVICE(INTEL, 0x0a54), /* Intel P4500/P4600 */ |
99466e70 | 3303 | .driver_data = NVME_QUIRK_STRIPE_SIZE | |
e850fd16 | 3304 | NVME_QUIRK_DEALLOCATE_ZEROES, }, |
972b13e2 | 3305 | { PCI_VDEVICE(INTEL, 0x0a55), /* Dell Express Flash P4600 */ |
f99cb7af DWF |
3306 | .driver_data = NVME_QUIRK_STRIPE_SIZE | |
3307 | NVME_QUIRK_DEALLOCATE_ZEROES, }, | |
50af47d0 | 3308 | { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */ |
9abd68ef | 3309 | .driver_data = NVME_QUIRK_NO_DEEPEST_PS | |
6c6aa2f2 | 3310 | NVME_QUIRK_MEDIUM_PRIO_SQ | |
ce4cc313 DM |
3311 | NVME_QUIRK_NO_TEMP_THRESH_CHANGE | |
3312 | NVME_QUIRK_DISABLE_WRITE_ZEROES, }, | |
6299358d JD |
3313 | { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */ |
3314 | .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, }, | |
540c801c | 3315 | { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */ |
7b210e4e CH |
3316 | .driver_data = NVME_QUIRK_IDENTIFY_CNS | |
3317 | NVME_QUIRK_DISABLE_WRITE_ZEROES, }, | |
5bedd3af CH |
3318 | { PCI_DEVICE(0x126f, 0x2263), /* Silicon Motion unidentified */ |
3319 | .driver_data = NVME_QUIRK_NO_NS_DESC_LIST, }, | |
0302ae60 | 3320 | { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */ |
5e112d3f JE |
3321 | .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY | |
3322 | NVME_QUIRK_NO_NS_DESC_LIST, }, | |
54adc010 GP |
3323 | { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */ |
3324 | .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, | |
8c97eecc JL |
3325 | { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */ |
3326 | .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, | |
015282c9 WW |
3327 | { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */ |
3328 | .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, | |
d554b5e1 MP |
3329 | { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */ |
3330 | .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, | |
3331 | { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */ | |
7ee5c78c | 3332 | .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY | |
abbb5f59 | 3333 | NVME_QUIRK_DISABLE_WRITE_ZEROES| |
7ee5c78c | 3334 | NVME_QUIRK_IGNORE_DEV_SUBNQN, }, |
c9e95c39 CS |
3335 | { PCI_DEVICE(0x1987, 0x5016), /* Phison E16 */ |
3336 | .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, }, | |
6e6a6828 PT |
3337 | { PCI_DEVICE(0x1b4b, 0x1092), /* Lexar 256 GB SSD */ |
3338 | .driver_data = NVME_QUIRK_NO_NS_DESC_LIST | | |
3339 | NVME_QUIRK_IGNORE_DEV_SUBNQN, }, | |
08b903b5 MN |
3340 | { PCI_DEVICE(0x10ec, 0x5762), /* ADATA SX6000LNP */ |
3341 | .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, }, | |
f03e42c6 GC |
3342 | { PCI_DEVICE(0x1cc1, 0x8201), /* ADATA SX8200PNP 512GB */ |
3343 | .driver_data = NVME_QUIRK_NO_DEEPEST_PS | | |
3344 | NVME_QUIRK_IGNORE_DEV_SUBNQN, }, | |
5611ec2b KHF |
3345 | { PCI_DEVICE(0x1c5c, 0x1504), /* SK Hynix PC400 */ |
3346 | .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, | |
02ca079c KHF |
3347 | { PCI_DEVICE(0x15b7, 0x2001), /* Sandisk Skyhawk */ |
3348 | .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, | |
89919929 CK |
3349 | { PCI_DEVICE(0x1d97, 0x2263), /* SPCC */ |
3350 | .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, | |
dc22c1c0 ZB |
3351 | { PCI_DEVICE(0x2646, 0x2262), /* KINGSTON SKC2000 NVMe SSD */ |
3352 | .driver_data = NVME_QUIRK_NO_DEEPEST_PS, }, | |
538e4a8c TL |
3353 | { PCI_DEVICE(0x2646, 0x2263), /* KINGSTON A2000 NVMe SSD */ |
3354 | .driver_data = NVME_QUIRK_NO_DEEPEST_PS, }, | |
4bdf2603 FS |
3355 | { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0061), |
3356 | .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, | |
3357 | { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0065), | |
3358 | .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, | |
3359 | { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x8061), | |
3360 | .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, | |
3361 | { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd00), | |
3362 | .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, | |
3363 | { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd01), | |
3364 | .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, | |
3365 | { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd02), | |
3366 | .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, | |
98f7b86a AS |
3367 | { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001), |
3368 | .driver_data = NVME_QUIRK_SINGLE_VECTOR }, | |
124298bd | 3369 | { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) }, |
66341331 BH |
3370 | { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005), |
3371 | .driver_data = NVME_QUIRK_SINGLE_VECTOR | | |
d38e9f04 | 3372 | NVME_QUIRK_128_BYTES_SQES | |
a2941f6a KB |
3373 | NVME_QUIRK_SHARED_TAGS | |
3374 | NVME_QUIRK_SKIP_CID_GEN }, | |
0b85f59d AS |
3375 | |
3376 | { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, | |
b60503ba MW |
3377 | { 0, } |
3378 | }; | |
3379 | MODULE_DEVICE_TABLE(pci, nvme_id_table); | |
3380 | ||
3381 | static struct pci_driver nvme_driver = { | |
3382 | .name = "nvme", | |
3383 | .id_table = nvme_id_table, | |
3384 | .probe = nvme_probe, | |
8d85fce7 | 3385 | .remove = nvme_remove, |
09ece142 | 3386 | .shutdown = nvme_shutdown, |
d916b1be | 3387 | #ifdef CONFIG_PM_SLEEP |
cd638946 KB |
3388 | .driver = { |
3389 | .pm = &nvme_dev_pm_ops, | |
3390 | }, | |
d916b1be | 3391 | #endif |
74d986ab | 3392 | .sriov_configure = pci_sriov_configure_simple, |
b60503ba MW |
3393 | .err_handler = &nvme_err_handler, |
3394 | }; | |
3395 | ||
3396 | static int __init nvme_init(void) | |
3397 | { | |
81101540 CH |
3398 | BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); |
3399 | BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); | |
3400 | BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); | |
612b7286 | 3401 | BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2); |
17c33167 | 3402 | |
9a6327d2 | 3403 | return pci_register_driver(&nvme_driver); |
b60503ba MW |
3404 | } |
3405 | ||
3406 | static void __exit nvme_exit(void) | |
3407 | { | |
3408 | pci_unregister_driver(&nvme_driver); | |
03e0f3a6 | 3409 | flush_workqueue(nvme_wq); |
b60503ba MW |
3410 | } |
3411 | ||
3412 | MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); | |
3413 | MODULE_LICENSE("GPL"); | |
c78b4713 | 3414 | MODULE_VERSION("1.0"); |
b60503ba MW |
3415 | module_init(nvme_init); |
3416 | module_exit(nvme_exit); |