Commit | Line | Data |
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b60503ba MW |
1 | /* |
2 | * NVM Express device driver | |
6eb0d698 | 3 | * Copyright (c) 2011-2014, Intel Corporation. |
b60503ba MW |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
b60503ba MW |
13 | */ |
14 | ||
a0a3408e | 15 | #include <linux/aer.h> |
8de05535 | 16 | #include <linux/bitops.h> |
b60503ba | 17 | #include <linux/blkdev.h> |
a4aea562 | 18 | #include <linux/blk-mq.h> |
dca51e78 | 19 | #include <linux/blk-mq-pci.h> |
ff5350a8 | 20 | #include <linux/dmi.h> |
b60503ba MW |
21 | #include <linux/init.h> |
22 | #include <linux/interrupt.h> | |
23 | #include <linux/io.h> | |
b60503ba MW |
24 | #include <linux/mm.h> |
25 | #include <linux/module.h> | |
77bf25ea | 26 | #include <linux/mutex.h> |
b60503ba | 27 | #include <linux/pci.h> |
be7b6275 | 28 | #include <linux/poison.h> |
e1e5e564 | 29 | #include <linux/t10-pi.h> |
2d55cd5f | 30 | #include <linux/timer.h> |
b60503ba | 31 | #include <linux/types.h> |
2f8e2c87 | 32 | #include <linux/io-64-nonatomic-lo-hi.h> |
1d277a63 | 33 | #include <asm/unaligned.h> |
a98e58e5 | 34 | #include <linux/sed-opal.h> |
797a796a | 35 | |
f11bb3e2 CH |
36 | #include "nvme.h" |
37 | ||
9d43cf64 | 38 | #define NVME_Q_DEPTH 1024 |
d31af0a3 | 39 | #define NVME_AQ_DEPTH 256 |
b60503ba MW |
40 | #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command)) |
41 | #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion)) | |
c965809c | 42 | |
adf68f21 CH |
43 | /* |
44 | * We handle AEN commands ourselves and don't even let the | |
45 | * block layer know about them. | |
46 | */ | |
f866fc42 | 47 | #define NVME_AQ_BLKMQ_DEPTH (NVME_AQ_DEPTH - NVME_NR_AERS) |
9d43cf64 | 48 | |
58ffacb5 MW |
49 | static int use_threaded_interrupts; |
50 | module_param(use_threaded_interrupts, int, 0); | |
51 | ||
8ffaadf7 JD |
52 | static bool use_cmb_sqes = true; |
53 | module_param(use_cmb_sqes, bool, 0644); | |
54 | MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes"); | |
55 | ||
87ad72a5 CH |
56 | static unsigned int max_host_mem_size_mb = 128; |
57 | module_param(max_host_mem_size_mb, uint, 0444); | |
58 | MODULE_PARM_DESC(max_host_mem_size_mb, | |
59 | "Maximum Host Memory Buffer (HMB) size per controller (in MiB)"); | |
60 | ||
1c63dc66 CH |
61 | struct nvme_dev; |
62 | struct nvme_queue; | |
b3fffdef | 63 | |
a0fa9647 | 64 | static void nvme_process_cq(struct nvme_queue *nvmeq); |
a5cdb68c | 65 | static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown); |
d4b4ff8e | 66 | |
1c63dc66 CH |
67 | /* |
68 | * Represents an NVM Express device. Each nvme_dev is a PCI function. | |
69 | */ | |
70 | struct nvme_dev { | |
1c63dc66 CH |
71 | struct nvme_queue **queues; |
72 | struct blk_mq_tag_set tagset; | |
73 | struct blk_mq_tag_set admin_tagset; | |
74 | u32 __iomem *dbs; | |
75 | struct device *dev; | |
76 | struct dma_pool *prp_page_pool; | |
77 | struct dma_pool *prp_small_pool; | |
78 | unsigned queue_count; | |
79 | unsigned online_queues; | |
80 | unsigned max_qid; | |
81 | int q_depth; | |
82 | u32 db_stride; | |
1c63dc66 | 83 | void __iomem *bar; |
97f6ef64 | 84 | unsigned long bar_mapped_size; |
5c8809e6 | 85 | struct work_struct remove_work; |
77bf25ea | 86 | struct mutex shutdown_lock; |
1c63dc66 | 87 | bool subsystem; |
1c63dc66 CH |
88 | void __iomem *cmb; |
89 | dma_addr_t cmb_dma_addr; | |
90 | u64 cmb_size; | |
91 | u32 cmbsz; | |
202021c1 | 92 | u32 cmbloc; |
1c63dc66 | 93 | struct nvme_ctrl ctrl; |
db3cbfff | 94 | struct completion ioq_wait; |
87ad72a5 CH |
95 | |
96 | /* shadow doorbell buffer support: */ | |
f9f38e33 HK |
97 | u32 *dbbuf_dbs; |
98 | dma_addr_t dbbuf_dbs_dma_addr; | |
99 | u32 *dbbuf_eis; | |
100 | dma_addr_t dbbuf_eis_dma_addr; | |
87ad72a5 CH |
101 | |
102 | /* host memory buffer support: */ | |
103 | u64 host_mem_size; | |
104 | u32 nr_host_mem_descs; | |
105 | struct nvme_host_mem_buf_desc *host_mem_descs; | |
106 | void **host_mem_desc_bufs; | |
4d115420 | 107 | }; |
1fa6aead | 108 | |
f9f38e33 HK |
109 | static inline unsigned int sq_idx(unsigned int qid, u32 stride) |
110 | { | |
111 | return qid * 2 * stride; | |
112 | } | |
113 | ||
114 | static inline unsigned int cq_idx(unsigned int qid, u32 stride) | |
115 | { | |
116 | return (qid * 2 + 1) * stride; | |
117 | } | |
118 | ||
1c63dc66 CH |
119 | static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl) |
120 | { | |
121 | return container_of(ctrl, struct nvme_dev, ctrl); | |
122 | } | |
123 | ||
b60503ba MW |
124 | /* |
125 | * An NVM Express queue. Each device has at least two (one for admin | |
126 | * commands and one for I/O commands). | |
127 | */ | |
128 | struct nvme_queue { | |
129 | struct device *q_dmadev; | |
091b6092 | 130 | struct nvme_dev *dev; |
b60503ba MW |
131 | spinlock_t q_lock; |
132 | struct nvme_command *sq_cmds; | |
8ffaadf7 | 133 | struct nvme_command __iomem *sq_cmds_io; |
b60503ba | 134 | volatile struct nvme_completion *cqes; |
42483228 | 135 | struct blk_mq_tags **tags; |
b60503ba MW |
136 | dma_addr_t sq_dma_addr; |
137 | dma_addr_t cq_dma_addr; | |
b60503ba MW |
138 | u32 __iomem *q_db; |
139 | u16 q_depth; | |
6222d172 | 140 | s16 cq_vector; |
b60503ba MW |
141 | u16 sq_tail; |
142 | u16 cq_head; | |
c30341dc | 143 | u16 qid; |
e9539f47 MW |
144 | u8 cq_phase; |
145 | u8 cqe_seen; | |
f9f38e33 HK |
146 | u32 *dbbuf_sq_db; |
147 | u32 *dbbuf_cq_db; | |
148 | u32 *dbbuf_sq_ei; | |
149 | u32 *dbbuf_cq_ei; | |
b60503ba MW |
150 | }; |
151 | ||
71bd150c CH |
152 | /* |
153 | * The nvme_iod describes the data in an I/O, including the list of PRP | |
154 | * entries. You can't see it in this data structure because C doesn't let | |
f4800d6d | 155 | * me express that. Use nvme_init_iod to ensure there's enough space |
71bd150c CH |
156 | * allocated to store the PRP list. |
157 | */ | |
158 | struct nvme_iod { | |
d49187e9 | 159 | struct nvme_request req; |
f4800d6d CH |
160 | struct nvme_queue *nvmeq; |
161 | int aborted; | |
71bd150c | 162 | int npages; /* In the PRP list. 0 means small pool in use */ |
71bd150c CH |
163 | int nents; /* Used in scatterlist */ |
164 | int length; /* Of data, in bytes */ | |
165 | dma_addr_t first_dma; | |
bf684057 | 166 | struct scatterlist meta_sg; /* metadata requires single contiguous buffer */ |
f4800d6d CH |
167 | struct scatterlist *sg; |
168 | struct scatterlist inline_sg[0]; | |
b60503ba MW |
169 | }; |
170 | ||
171 | /* | |
172 | * Check we didin't inadvertently grow the command struct | |
173 | */ | |
174 | static inline void _nvme_check_size(void) | |
175 | { | |
176 | BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64); | |
177 | BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); | |
178 | BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); | |
179 | BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); | |
180 | BUILD_BUG_ON(sizeof(struct nvme_features) != 64); | |
f8ebf840 | 181 | BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64); |
c30341dc | 182 | BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64); |
b60503ba | 183 | BUILD_BUG_ON(sizeof(struct nvme_command) != 64); |
0add5e8e JT |
184 | BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != NVME_IDENTIFY_DATA_SIZE); |
185 | BUILD_BUG_ON(sizeof(struct nvme_id_ns) != NVME_IDENTIFY_DATA_SIZE); | |
b60503ba | 186 | BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64); |
6ecec745 | 187 | BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512); |
f9f38e33 HK |
188 | BUILD_BUG_ON(sizeof(struct nvme_dbbuf) != 64); |
189 | } | |
190 | ||
191 | static inline unsigned int nvme_dbbuf_size(u32 stride) | |
192 | { | |
193 | return ((num_possible_cpus() + 1) * 8 * stride); | |
194 | } | |
195 | ||
196 | static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev) | |
197 | { | |
198 | unsigned int mem_size = nvme_dbbuf_size(dev->db_stride); | |
199 | ||
200 | if (dev->dbbuf_dbs) | |
201 | return 0; | |
202 | ||
203 | dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size, | |
204 | &dev->dbbuf_dbs_dma_addr, | |
205 | GFP_KERNEL); | |
206 | if (!dev->dbbuf_dbs) | |
207 | return -ENOMEM; | |
208 | dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size, | |
209 | &dev->dbbuf_eis_dma_addr, | |
210 | GFP_KERNEL); | |
211 | if (!dev->dbbuf_eis) { | |
212 | dma_free_coherent(dev->dev, mem_size, | |
213 | dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); | |
214 | dev->dbbuf_dbs = NULL; | |
215 | return -ENOMEM; | |
216 | } | |
217 | ||
218 | return 0; | |
219 | } | |
220 | ||
221 | static void nvme_dbbuf_dma_free(struct nvme_dev *dev) | |
222 | { | |
223 | unsigned int mem_size = nvme_dbbuf_size(dev->db_stride); | |
224 | ||
225 | if (dev->dbbuf_dbs) { | |
226 | dma_free_coherent(dev->dev, mem_size, | |
227 | dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); | |
228 | dev->dbbuf_dbs = NULL; | |
229 | } | |
230 | if (dev->dbbuf_eis) { | |
231 | dma_free_coherent(dev->dev, mem_size, | |
232 | dev->dbbuf_eis, dev->dbbuf_eis_dma_addr); | |
233 | dev->dbbuf_eis = NULL; | |
234 | } | |
235 | } | |
236 | ||
237 | static void nvme_dbbuf_init(struct nvme_dev *dev, | |
238 | struct nvme_queue *nvmeq, int qid) | |
239 | { | |
240 | if (!dev->dbbuf_dbs || !qid) | |
241 | return; | |
242 | ||
243 | nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)]; | |
244 | nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)]; | |
245 | nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)]; | |
246 | nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)]; | |
247 | } | |
248 | ||
249 | static void nvme_dbbuf_set(struct nvme_dev *dev) | |
250 | { | |
251 | struct nvme_command c; | |
252 | ||
253 | if (!dev->dbbuf_dbs) | |
254 | return; | |
255 | ||
256 | memset(&c, 0, sizeof(c)); | |
257 | c.dbbuf.opcode = nvme_admin_dbbuf; | |
258 | c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr); | |
259 | c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr); | |
260 | ||
261 | if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) { | |
9bdcfb10 | 262 | dev_warn(dev->ctrl.device, "unable to set dbbuf\n"); |
f9f38e33 HK |
263 | /* Free memory and continue on */ |
264 | nvme_dbbuf_dma_free(dev); | |
265 | } | |
266 | } | |
267 | ||
268 | static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old) | |
269 | { | |
270 | return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old); | |
271 | } | |
272 | ||
273 | /* Update dbbuf and return true if an MMIO is required */ | |
274 | static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db, | |
275 | volatile u32 *dbbuf_ei) | |
276 | { | |
277 | if (dbbuf_db) { | |
278 | u16 old_value; | |
279 | ||
280 | /* | |
281 | * Ensure that the queue is written before updating | |
282 | * the doorbell in memory | |
283 | */ | |
284 | wmb(); | |
285 | ||
286 | old_value = *dbbuf_db; | |
287 | *dbbuf_db = value; | |
288 | ||
289 | if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value)) | |
290 | return false; | |
291 | } | |
292 | ||
293 | return true; | |
b60503ba MW |
294 | } |
295 | ||
ac3dd5bd JA |
296 | /* |
297 | * Max size of iod being embedded in the request payload | |
298 | */ | |
299 | #define NVME_INT_PAGES 2 | |
5fd4ce1b | 300 | #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size) |
ac3dd5bd JA |
301 | |
302 | /* | |
303 | * Will slightly overestimate the number of pages needed. This is OK | |
304 | * as it only leads to a small amount of wasted memory for the lifetime of | |
305 | * the I/O. | |
306 | */ | |
307 | static int nvme_npages(unsigned size, struct nvme_dev *dev) | |
308 | { | |
5fd4ce1b CH |
309 | unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size, |
310 | dev->ctrl.page_size); | |
ac3dd5bd JA |
311 | return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); |
312 | } | |
313 | ||
f4800d6d CH |
314 | static unsigned int nvme_iod_alloc_size(struct nvme_dev *dev, |
315 | unsigned int size, unsigned int nseg) | |
ac3dd5bd | 316 | { |
f4800d6d CH |
317 | return sizeof(__le64 *) * nvme_npages(size, dev) + |
318 | sizeof(struct scatterlist) * nseg; | |
319 | } | |
ac3dd5bd | 320 | |
f4800d6d CH |
321 | static unsigned int nvme_cmd_size(struct nvme_dev *dev) |
322 | { | |
323 | return sizeof(struct nvme_iod) + | |
324 | nvme_iod_alloc_size(dev, NVME_INT_BYTES(dev), NVME_INT_PAGES); | |
ac3dd5bd JA |
325 | } |
326 | ||
a4aea562 MB |
327 | static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, |
328 | unsigned int hctx_idx) | |
e85248e5 | 329 | { |
a4aea562 MB |
330 | struct nvme_dev *dev = data; |
331 | struct nvme_queue *nvmeq = dev->queues[0]; | |
332 | ||
42483228 KB |
333 | WARN_ON(hctx_idx != 0); |
334 | WARN_ON(dev->admin_tagset.tags[0] != hctx->tags); | |
335 | WARN_ON(nvmeq->tags); | |
336 | ||
a4aea562 | 337 | hctx->driver_data = nvmeq; |
42483228 | 338 | nvmeq->tags = &dev->admin_tagset.tags[0]; |
a4aea562 | 339 | return 0; |
e85248e5 MW |
340 | } |
341 | ||
4af0e21c KB |
342 | static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx) |
343 | { | |
344 | struct nvme_queue *nvmeq = hctx->driver_data; | |
345 | ||
346 | nvmeq->tags = NULL; | |
347 | } | |
348 | ||
a4aea562 MB |
349 | static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, |
350 | unsigned int hctx_idx) | |
b60503ba | 351 | { |
a4aea562 | 352 | struct nvme_dev *dev = data; |
42483228 | 353 | struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1]; |
a4aea562 | 354 | |
42483228 KB |
355 | if (!nvmeq->tags) |
356 | nvmeq->tags = &dev->tagset.tags[hctx_idx]; | |
b60503ba | 357 | |
42483228 | 358 | WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags); |
a4aea562 MB |
359 | hctx->driver_data = nvmeq; |
360 | return 0; | |
b60503ba MW |
361 | } |
362 | ||
d6296d39 CH |
363 | static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req, |
364 | unsigned int hctx_idx, unsigned int numa_node) | |
b60503ba | 365 | { |
d6296d39 | 366 | struct nvme_dev *dev = set->driver_data; |
f4800d6d | 367 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
0350815a CH |
368 | int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0; |
369 | struct nvme_queue *nvmeq = dev->queues[queue_idx]; | |
a4aea562 MB |
370 | |
371 | BUG_ON(!nvmeq); | |
f4800d6d | 372 | iod->nvmeq = nvmeq; |
a4aea562 MB |
373 | return 0; |
374 | } | |
375 | ||
dca51e78 CH |
376 | static int nvme_pci_map_queues(struct blk_mq_tag_set *set) |
377 | { | |
378 | struct nvme_dev *dev = set->driver_data; | |
379 | ||
380 | return blk_mq_pci_map_queues(set, to_pci_dev(dev->dev)); | |
381 | } | |
382 | ||
b60503ba | 383 | /** |
adf68f21 | 384 | * __nvme_submit_cmd() - Copy a command into a queue and ring the doorbell |
b60503ba MW |
385 | * @nvmeq: The queue to use |
386 | * @cmd: The command to send | |
387 | * | |
388 | * Safe to use from interrupt context | |
389 | */ | |
e3f879bf SB |
390 | static void __nvme_submit_cmd(struct nvme_queue *nvmeq, |
391 | struct nvme_command *cmd) | |
b60503ba | 392 | { |
a4aea562 MB |
393 | u16 tail = nvmeq->sq_tail; |
394 | ||
8ffaadf7 JD |
395 | if (nvmeq->sq_cmds_io) |
396 | memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd)); | |
397 | else | |
398 | memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd)); | |
399 | ||
b60503ba MW |
400 | if (++tail == nvmeq->q_depth) |
401 | tail = 0; | |
f9f38e33 HK |
402 | if (nvme_dbbuf_update_and_check_event(tail, nvmeq->dbbuf_sq_db, |
403 | nvmeq->dbbuf_sq_ei)) | |
404 | writel(tail, nvmeq->q_db); | |
b60503ba | 405 | nvmeq->sq_tail = tail; |
b60503ba MW |
406 | } |
407 | ||
f4800d6d | 408 | static __le64 **iod_list(struct request *req) |
b60503ba | 409 | { |
f4800d6d | 410 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
f9d03f96 | 411 | return (__le64 **)(iod->sg + blk_rq_nr_phys_segments(req)); |
b60503ba MW |
412 | } |
413 | ||
fc17b653 | 414 | static blk_status_t nvme_init_iod(struct request *rq, struct nvme_dev *dev) |
ac3dd5bd | 415 | { |
f4800d6d | 416 | struct nvme_iod *iod = blk_mq_rq_to_pdu(rq); |
f9d03f96 | 417 | int nseg = blk_rq_nr_phys_segments(rq); |
b131c61d | 418 | unsigned int size = blk_rq_payload_bytes(rq); |
ac3dd5bd | 419 | |
f4800d6d CH |
420 | if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) { |
421 | iod->sg = kmalloc(nvme_iod_alloc_size(dev, size, nseg), GFP_ATOMIC); | |
422 | if (!iod->sg) | |
fc17b653 | 423 | return BLK_STS_RESOURCE; |
f4800d6d CH |
424 | } else { |
425 | iod->sg = iod->inline_sg; | |
ac3dd5bd JA |
426 | } |
427 | ||
f4800d6d CH |
428 | iod->aborted = 0; |
429 | iod->npages = -1; | |
430 | iod->nents = 0; | |
431 | iod->length = size; | |
f80ec966 | 432 | |
fc17b653 | 433 | return BLK_STS_OK; |
ac3dd5bd JA |
434 | } |
435 | ||
f4800d6d | 436 | static void nvme_free_iod(struct nvme_dev *dev, struct request *req) |
b60503ba | 437 | { |
f4800d6d | 438 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
5fd4ce1b | 439 | const int last_prp = dev->ctrl.page_size / 8 - 1; |
eca18b23 | 440 | int i; |
f4800d6d | 441 | __le64 **list = iod_list(req); |
eca18b23 MW |
442 | dma_addr_t prp_dma = iod->first_dma; |
443 | ||
444 | if (iod->npages == 0) | |
445 | dma_pool_free(dev->prp_small_pool, list[0], prp_dma); | |
446 | for (i = 0; i < iod->npages; i++) { | |
447 | __le64 *prp_list = list[i]; | |
448 | dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]); | |
449 | dma_pool_free(dev->prp_page_pool, prp_list, prp_dma); | |
450 | prp_dma = next_prp_dma; | |
451 | } | |
ac3dd5bd | 452 | |
f4800d6d CH |
453 | if (iod->sg != iod->inline_sg) |
454 | kfree(iod->sg); | |
b4ff9c8d KB |
455 | } |
456 | ||
52b68d7e | 457 | #ifdef CONFIG_BLK_DEV_INTEGRITY |
e1e5e564 KB |
458 | static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi) |
459 | { | |
460 | if (be32_to_cpu(pi->ref_tag) == v) | |
461 | pi->ref_tag = cpu_to_be32(p); | |
462 | } | |
463 | ||
464 | static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi) | |
465 | { | |
466 | if (be32_to_cpu(pi->ref_tag) == p) | |
467 | pi->ref_tag = cpu_to_be32(v); | |
468 | } | |
469 | ||
470 | /** | |
471 | * nvme_dif_remap - remaps ref tags to bip seed and physical lba | |
472 | * | |
473 | * The virtual start sector is the one that was originally submitted by the | |
474 | * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical | |
475 | * start sector may be different. Remap protection information to match the | |
476 | * physical LBA on writes, and back to the original seed on reads. | |
477 | * | |
478 | * Type 0 and 3 do not have a ref tag, so no remapping required. | |
479 | */ | |
480 | static void nvme_dif_remap(struct request *req, | |
481 | void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi)) | |
482 | { | |
483 | struct nvme_ns *ns = req->rq_disk->private_data; | |
484 | struct bio_integrity_payload *bip; | |
485 | struct t10_pi_tuple *pi; | |
486 | void *p, *pmap; | |
487 | u32 i, nlb, ts, phys, virt; | |
488 | ||
489 | if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3) | |
490 | return; | |
491 | ||
492 | bip = bio_integrity(req->bio); | |
493 | if (!bip) | |
494 | return; | |
495 | ||
496 | pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset; | |
e1e5e564 KB |
497 | |
498 | p = pmap; | |
499 | virt = bip_get_seed(bip); | |
500 | phys = nvme_block_nr(ns, blk_rq_pos(req)); | |
501 | nlb = (blk_rq_bytes(req) >> ns->lba_shift); | |
ac6fc48c | 502 | ts = ns->disk->queue->integrity.tuple_size; |
e1e5e564 KB |
503 | |
504 | for (i = 0; i < nlb; i++, virt++, phys++) { | |
505 | pi = (struct t10_pi_tuple *)p; | |
506 | dif_swap(phys, virt, pi); | |
507 | p += ts; | |
508 | } | |
509 | kunmap_atomic(pmap); | |
510 | } | |
52b68d7e KB |
511 | #else /* CONFIG_BLK_DEV_INTEGRITY */ |
512 | static void nvme_dif_remap(struct request *req, | |
513 | void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi)) | |
514 | { | |
515 | } | |
516 | static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi) | |
517 | { | |
518 | } | |
519 | static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi) | |
520 | { | |
521 | } | |
52b68d7e KB |
522 | #endif |
523 | ||
b131c61d | 524 | static bool nvme_setup_prps(struct nvme_dev *dev, struct request *req) |
ff22b54f | 525 | { |
f4800d6d | 526 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
99802a7a | 527 | struct dma_pool *pool; |
b131c61d | 528 | int length = blk_rq_payload_bytes(req); |
eca18b23 | 529 | struct scatterlist *sg = iod->sg; |
ff22b54f MW |
530 | int dma_len = sg_dma_len(sg); |
531 | u64 dma_addr = sg_dma_address(sg); | |
5fd4ce1b | 532 | u32 page_size = dev->ctrl.page_size; |
f137e0f1 | 533 | int offset = dma_addr & (page_size - 1); |
e025344c | 534 | __le64 *prp_list; |
f4800d6d | 535 | __le64 **list = iod_list(req); |
e025344c | 536 | dma_addr_t prp_dma; |
eca18b23 | 537 | int nprps, i; |
ff22b54f | 538 | |
1d090624 | 539 | length -= (page_size - offset); |
ff22b54f | 540 | if (length <= 0) |
69d2b571 | 541 | return true; |
ff22b54f | 542 | |
1d090624 | 543 | dma_len -= (page_size - offset); |
ff22b54f | 544 | if (dma_len) { |
1d090624 | 545 | dma_addr += (page_size - offset); |
ff22b54f MW |
546 | } else { |
547 | sg = sg_next(sg); | |
548 | dma_addr = sg_dma_address(sg); | |
549 | dma_len = sg_dma_len(sg); | |
550 | } | |
551 | ||
1d090624 | 552 | if (length <= page_size) { |
edd10d33 | 553 | iod->first_dma = dma_addr; |
69d2b571 | 554 | return true; |
e025344c SMM |
555 | } |
556 | ||
1d090624 | 557 | nprps = DIV_ROUND_UP(length, page_size); |
99802a7a MW |
558 | if (nprps <= (256 / 8)) { |
559 | pool = dev->prp_small_pool; | |
eca18b23 | 560 | iod->npages = 0; |
99802a7a MW |
561 | } else { |
562 | pool = dev->prp_page_pool; | |
eca18b23 | 563 | iod->npages = 1; |
99802a7a MW |
564 | } |
565 | ||
69d2b571 | 566 | prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); |
b77954cb | 567 | if (!prp_list) { |
edd10d33 | 568 | iod->first_dma = dma_addr; |
eca18b23 | 569 | iod->npages = -1; |
69d2b571 | 570 | return false; |
b77954cb | 571 | } |
eca18b23 MW |
572 | list[0] = prp_list; |
573 | iod->first_dma = prp_dma; | |
e025344c SMM |
574 | i = 0; |
575 | for (;;) { | |
1d090624 | 576 | if (i == page_size >> 3) { |
e025344c | 577 | __le64 *old_prp_list = prp_list; |
69d2b571 | 578 | prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); |
eca18b23 | 579 | if (!prp_list) |
69d2b571 | 580 | return false; |
eca18b23 | 581 | list[iod->npages++] = prp_list; |
7523d834 MW |
582 | prp_list[0] = old_prp_list[i - 1]; |
583 | old_prp_list[i - 1] = cpu_to_le64(prp_dma); | |
584 | i = 1; | |
e025344c SMM |
585 | } |
586 | prp_list[i++] = cpu_to_le64(dma_addr); | |
1d090624 KB |
587 | dma_len -= page_size; |
588 | dma_addr += page_size; | |
589 | length -= page_size; | |
e025344c SMM |
590 | if (length <= 0) |
591 | break; | |
592 | if (dma_len > 0) | |
593 | continue; | |
594 | BUG_ON(dma_len < 0); | |
595 | sg = sg_next(sg); | |
596 | dma_addr = sg_dma_address(sg); | |
597 | dma_len = sg_dma_len(sg); | |
ff22b54f MW |
598 | } |
599 | ||
69d2b571 | 600 | return true; |
ff22b54f MW |
601 | } |
602 | ||
fc17b653 | 603 | static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req, |
b131c61d | 604 | struct nvme_command *cmnd) |
d29ec824 | 605 | { |
f4800d6d | 606 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
ba1ca37e CH |
607 | struct request_queue *q = req->q; |
608 | enum dma_data_direction dma_dir = rq_data_dir(req) ? | |
609 | DMA_TO_DEVICE : DMA_FROM_DEVICE; | |
fc17b653 | 610 | blk_status_t ret = BLK_STS_IOERR; |
d29ec824 | 611 | |
f9d03f96 | 612 | sg_init_table(iod->sg, blk_rq_nr_phys_segments(req)); |
ba1ca37e CH |
613 | iod->nents = blk_rq_map_sg(q, req, iod->sg); |
614 | if (!iod->nents) | |
615 | goto out; | |
d29ec824 | 616 | |
fc17b653 | 617 | ret = BLK_STS_RESOURCE; |
2b6b535d MFO |
618 | if (!dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, dma_dir, |
619 | DMA_ATTR_NO_WARN)) | |
ba1ca37e | 620 | goto out; |
d29ec824 | 621 | |
b131c61d | 622 | if (!nvme_setup_prps(dev, req)) |
ba1ca37e | 623 | goto out_unmap; |
0e5e4f0e | 624 | |
fc17b653 | 625 | ret = BLK_STS_IOERR; |
ba1ca37e CH |
626 | if (blk_integrity_rq(req)) { |
627 | if (blk_rq_count_integrity_sg(q, req->bio) != 1) | |
628 | goto out_unmap; | |
0e5e4f0e | 629 | |
bf684057 CH |
630 | sg_init_table(&iod->meta_sg, 1); |
631 | if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1) | |
ba1ca37e | 632 | goto out_unmap; |
0e5e4f0e | 633 | |
ba1ca37e CH |
634 | if (rq_data_dir(req)) |
635 | nvme_dif_remap(req, nvme_dif_prep); | |
0e5e4f0e | 636 | |
bf684057 | 637 | if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir)) |
ba1ca37e | 638 | goto out_unmap; |
d29ec824 | 639 | } |
00df5cb4 | 640 | |
eb793e2c CH |
641 | cmnd->rw.dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg)); |
642 | cmnd->rw.dptr.prp2 = cpu_to_le64(iod->first_dma); | |
ba1ca37e | 643 | if (blk_integrity_rq(req)) |
bf684057 | 644 | cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg)); |
fc17b653 | 645 | return BLK_STS_OK; |
00df5cb4 | 646 | |
ba1ca37e CH |
647 | out_unmap: |
648 | dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); | |
649 | out: | |
650 | return ret; | |
00df5cb4 MW |
651 | } |
652 | ||
f4800d6d | 653 | static void nvme_unmap_data(struct nvme_dev *dev, struct request *req) |
b60503ba | 654 | { |
f4800d6d | 655 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
d4f6c3ab CH |
656 | enum dma_data_direction dma_dir = rq_data_dir(req) ? |
657 | DMA_TO_DEVICE : DMA_FROM_DEVICE; | |
658 | ||
659 | if (iod->nents) { | |
660 | dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); | |
661 | if (blk_integrity_rq(req)) { | |
662 | if (!rq_data_dir(req)) | |
663 | nvme_dif_remap(req, nvme_dif_complete); | |
bf684057 | 664 | dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir); |
e1e5e564 | 665 | } |
e19b127f | 666 | } |
e1e5e564 | 667 | |
f9d03f96 | 668 | nvme_cleanup_cmd(req); |
f4800d6d | 669 | nvme_free_iod(dev, req); |
d4f6c3ab | 670 | } |
b60503ba | 671 | |
d29ec824 CH |
672 | /* |
673 | * NOTE: ns is NULL when called on the admin queue. | |
674 | */ | |
fc17b653 | 675 | static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx, |
a4aea562 | 676 | const struct blk_mq_queue_data *bd) |
edd10d33 | 677 | { |
a4aea562 MB |
678 | struct nvme_ns *ns = hctx->queue->queuedata; |
679 | struct nvme_queue *nvmeq = hctx->driver_data; | |
d29ec824 | 680 | struct nvme_dev *dev = nvmeq->dev; |
a4aea562 | 681 | struct request *req = bd->rq; |
ba1ca37e | 682 | struct nvme_command cmnd; |
ebe6d874 | 683 | blk_status_t ret; |
e1e5e564 | 684 | |
f9d03f96 | 685 | ret = nvme_setup_cmd(ns, req, &cmnd); |
fc17b653 | 686 | if (ret) |
f4800d6d | 687 | return ret; |
a4aea562 | 688 | |
b131c61d | 689 | ret = nvme_init_iod(req, dev); |
fc17b653 | 690 | if (ret) |
f9d03f96 | 691 | goto out_free_cmd; |
a4aea562 | 692 | |
fc17b653 | 693 | if (blk_rq_nr_phys_segments(req)) { |
b131c61d | 694 | ret = nvme_map_data(dev, req, &cmnd); |
fc17b653 CH |
695 | if (ret) |
696 | goto out_cleanup_iod; | |
697 | } | |
a4aea562 | 698 | |
aae239e1 | 699 | blk_mq_start_request(req); |
a4aea562 | 700 | |
ba1ca37e | 701 | spin_lock_irq(&nvmeq->q_lock); |
ae1fba20 | 702 | if (unlikely(nvmeq->cq_vector < 0)) { |
fc17b653 | 703 | ret = BLK_STS_IOERR; |
ae1fba20 | 704 | spin_unlock_irq(&nvmeq->q_lock); |
f9d03f96 | 705 | goto out_cleanup_iod; |
ae1fba20 | 706 | } |
ba1ca37e | 707 | __nvme_submit_cmd(nvmeq, &cmnd); |
a4aea562 MB |
708 | nvme_process_cq(nvmeq); |
709 | spin_unlock_irq(&nvmeq->q_lock); | |
fc17b653 | 710 | return BLK_STS_OK; |
f9d03f96 | 711 | out_cleanup_iod: |
f4800d6d | 712 | nvme_free_iod(dev, req); |
f9d03f96 CH |
713 | out_free_cmd: |
714 | nvme_cleanup_cmd(req); | |
ba1ca37e | 715 | return ret; |
b60503ba | 716 | } |
e1e5e564 | 717 | |
77f02a7a | 718 | static void nvme_pci_complete_rq(struct request *req) |
eee417b0 | 719 | { |
f4800d6d | 720 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
a4aea562 | 721 | |
77f02a7a CH |
722 | nvme_unmap_data(iod->nvmeq->dev, req); |
723 | nvme_complete_rq(req); | |
b60503ba MW |
724 | } |
725 | ||
d783e0bd MR |
726 | /* We read the CQE phase first to check if the rest of the entry is valid */ |
727 | static inline bool nvme_cqe_valid(struct nvme_queue *nvmeq, u16 head, | |
728 | u16 phase) | |
729 | { | |
730 | return (le16_to_cpu(nvmeq->cqes[head].status) & 1) == phase; | |
731 | } | |
732 | ||
a0fa9647 | 733 | static void __nvme_process_cq(struct nvme_queue *nvmeq, unsigned int *tag) |
b60503ba | 734 | { |
82123460 | 735 | u16 head, phase; |
b60503ba | 736 | |
b60503ba | 737 | head = nvmeq->cq_head; |
82123460 | 738 | phase = nvmeq->cq_phase; |
b60503ba | 739 | |
d783e0bd | 740 | while (nvme_cqe_valid(nvmeq, head, phase)) { |
b60503ba | 741 | struct nvme_completion cqe = nvmeq->cqes[head]; |
eee417b0 | 742 | struct request *req; |
adf68f21 | 743 | |
b60503ba MW |
744 | if (++head == nvmeq->q_depth) { |
745 | head = 0; | |
82123460 | 746 | phase = !phase; |
b60503ba | 747 | } |
adf68f21 | 748 | |
a0fa9647 JA |
749 | if (tag && *tag == cqe.command_id) |
750 | *tag = -1; | |
adf68f21 | 751 | |
aae239e1 | 752 | if (unlikely(cqe.command_id >= nvmeq->q_depth)) { |
1b3c47c1 | 753 | dev_warn(nvmeq->dev->ctrl.device, |
aae239e1 CH |
754 | "invalid id %d completed on queue %d\n", |
755 | cqe.command_id, le16_to_cpu(cqe.sq_id)); | |
756 | continue; | |
757 | } | |
758 | ||
adf68f21 CH |
759 | /* |
760 | * AEN requests are special as they don't time out and can | |
761 | * survive any kind of queue freeze and often don't respond to | |
762 | * aborts. We don't even bother to allocate a struct request | |
763 | * for them but rather special case them here. | |
764 | */ | |
765 | if (unlikely(nvmeq->qid == 0 && | |
766 | cqe.command_id >= NVME_AQ_BLKMQ_DEPTH)) { | |
7bf58533 CH |
767 | nvme_complete_async_event(&nvmeq->dev->ctrl, |
768 | cqe.status, &cqe.result); | |
adf68f21 CH |
769 | continue; |
770 | } | |
771 | ||
eee417b0 | 772 | req = blk_mq_tag_to_rq(*nvmeq->tags, cqe.command_id); |
27fa9bc5 | 773 | nvme_end_request(req, cqe.status, cqe.result); |
b60503ba MW |
774 | } |
775 | ||
82123460 | 776 | if (head == nvmeq->cq_head && phase == nvmeq->cq_phase) |
a0fa9647 | 777 | return; |
b60503ba | 778 | |
604e8c8d | 779 | if (likely(nvmeq->cq_vector >= 0)) |
f9f38e33 HK |
780 | if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db, |
781 | nvmeq->dbbuf_cq_ei)) | |
782 | writel(head, nvmeq->q_db + nvmeq->dev->db_stride); | |
b60503ba | 783 | nvmeq->cq_head = head; |
82123460 | 784 | nvmeq->cq_phase = phase; |
b60503ba | 785 | |
e9539f47 | 786 | nvmeq->cqe_seen = 1; |
a0fa9647 JA |
787 | } |
788 | ||
789 | static void nvme_process_cq(struct nvme_queue *nvmeq) | |
790 | { | |
791 | __nvme_process_cq(nvmeq, NULL); | |
b60503ba MW |
792 | } |
793 | ||
794 | static irqreturn_t nvme_irq(int irq, void *data) | |
58ffacb5 MW |
795 | { |
796 | irqreturn_t result; | |
797 | struct nvme_queue *nvmeq = data; | |
798 | spin_lock(&nvmeq->q_lock); | |
e9539f47 MW |
799 | nvme_process_cq(nvmeq); |
800 | result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE; | |
801 | nvmeq->cqe_seen = 0; | |
58ffacb5 MW |
802 | spin_unlock(&nvmeq->q_lock); |
803 | return result; | |
804 | } | |
805 | ||
806 | static irqreturn_t nvme_irq_check(int irq, void *data) | |
807 | { | |
808 | struct nvme_queue *nvmeq = data; | |
d783e0bd MR |
809 | if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase)) |
810 | return IRQ_WAKE_THREAD; | |
811 | return IRQ_NONE; | |
58ffacb5 MW |
812 | } |
813 | ||
7776db1c | 814 | static int __nvme_poll(struct nvme_queue *nvmeq, unsigned int tag) |
a0fa9647 | 815 | { |
d783e0bd | 816 | if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase)) { |
a0fa9647 JA |
817 | spin_lock_irq(&nvmeq->q_lock); |
818 | __nvme_process_cq(nvmeq, &tag); | |
819 | spin_unlock_irq(&nvmeq->q_lock); | |
820 | ||
821 | if (tag == -1) | |
822 | return 1; | |
823 | } | |
824 | ||
825 | return 0; | |
826 | } | |
827 | ||
7776db1c KB |
828 | static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag) |
829 | { | |
830 | struct nvme_queue *nvmeq = hctx->driver_data; | |
831 | ||
832 | return __nvme_poll(nvmeq, tag); | |
833 | } | |
834 | ||
f866fc42 | 835 | static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl, int aer_idx) |
b60503ba | 836 | { |
f866fc42 | 837 | struct nvme_dev *dev = to_nvme_dev(ctrl); |
9396dec9 | 838 | struct nvme_queue *nvmeq = dev->queues[0]; |
a4aea562 | 839 | struct nvme_command c; |
b60503ba | 840 | |
a4aea562 MB |
841 | memset(&c, 0, sizeof(c)); |
842 | c.common.opcode = nvme_admin_async_event; | |
f866fc42 | 843 | c.common.command_id = NVME_AQ_BLKMQ_DEPTH + aer_idx; |
3c0cf138 | 844 | |
9396dec9 | 845 | spin_lock_irq(&nvmeq->q_lock); |
f866fc42 | 846 | __nvme_submit_cmd(nvmeq, &c); |
9396dec9 | 847 | spin_unlock_irq(&nvmeq->q_lock); |
f705f837 CH |
848 | } |
849 | ||
b60503ba | 850 | static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) |
f705f837 | 851 | { |
b60503ba MW |
852 | struct nvme_command c; |
853 | ||
854 | memset(&c, 0, sizeof(c)); | |
855 | c.delete_queue.opcode = opcode; | |
856 | c.delete_queue.qid = cpu_to_le16(id); | |
857 | ||
1c63dc66 | 858 | return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); |
b60503ba MW |
859 | } |
860 | ||
b60503ba MW |
861 | static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, |
862 | struct nvme_queue *nvmeq) | |
863 | { | |
b60503ba MW |
864 | struct nvme_command c; |
865 | int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED; | |
866 | ||
d29ec824 CH |
867 | /* |
868 | * Note: we (ab)use the fact the the prp fields survive if no data | |
869 | * is attached to the request. | |
870 | */ | |
b60503ba MW |
871 | memset(&c, 0, sizeof(c)); |
872 | c.create_cq.opcode = nvme_admin_create_cq; | |
873 | c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); | |
874 | c.create_cq.cqid = cpu_to_le16(qid); | |
875 | c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); | |
876 | c.create_cq.cq_flags = cpu_to_le16(flags); | |
877 | c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector); | |
878 | ||
1c63dc66 | 879 | return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); |
b60503ba MW |
880 | } |
881 | ||
882 | static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, | |
883 | struct nvme_queue *nvmeq) | |
884 | { | |
b60503ba | 885 | struct nvme_command c; |
81c1cd98 | 886 | int flags = NVME_QUEUE_PHYS_CONTIG; |
b60503ba | 887 | |
d29ec824 CH |
888 | /* |
889 | * Note: we (ab)use the fact the the prp fields survive if no data | |
890 | * is attached to the request. | |
891 | */ | |
b60503ba MW |
892 | memset(&c, 0, sizeof(c)); |
893 | c.create_sq.opcode = nvme_admin_create_sq; | |
894 | c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); | |
895 | c.create_sq.sqid = cpu_to_le16(qid); | |
896 | c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); | |
897 | c.create_sq.sq_flags = cpu_to_le16(flags); | |
898 | c.create_sq.cqid = cpu_to_le16(qid); | |
899 | ||
1c63dc66 | 900 | return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); |
b60503ba MW |
901 | } |
902 | ||
903 | static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) | |
904 | { | |
905 | return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); | |
906 | } | |
907 | ||
908 | static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) | |
909 | { | |
910 | return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); | |
911 | } | |
912 | ||
2a842aca | 913 | static void abort_endio(struct request *req, blk_status_t error) |
bc5fc7e4 | 914 | { |
f4800d6d CH |
915 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
916 | struct nvme_queue *nvmeq = iod->nvmeq; | |
e44ac588 | 917 | |
27fa9bc5 CH |
918 | dev_warn(nvmeq->dev->ctrl.device, |
919 | "Abort status: 0x%x", nvme_req(req)->status); | |
e7a2a87d | 920 | atomic_inc(&nvmeq->dev->ctrl.abort_limit); |
e7a2a87d | 921 | blk_mq_free_request(req); |
bc5fc7e4 MW |
922 | } |
923 | ||
b2a0eb1a KB |
924 | static bool nvme_should_reset(struct nvme_dev *dev, u32 csts) |
925 | { | |
926 | ||
927 | /* If true, indicates loss of adapter communication, possibly by a | |
928 | * NVMe Subsystem reset. | |
929 | */ | |
930 | bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO); | |
931 | ||
932 | /* If there is a reset ongoing, we shouldn't reset again. */ | |
933 | if (dev->ctrl.state == NVME_CTRL_RESETTING) | |
934 | return false; | |
935 | ||
936 | /* We shouldn't reset unless the controller is on fatal error state | |
937 | * _or_ if we lost the communication with it. | |
938 | */ | |
939 | if (!(csts & NVME_CSTS_CFS) && !nssro) | |
940 | return false; | |
941 | ||
942 | /* If PCI error recovery process is happening, we cannot reset or | |
943 | * the recovery mechanism will surely fail. | |
944 | */ | |
945 | if (pci_channel_offline(to_pci_dev(dev->dev))) | |
946 | return false; | |
947 | ||
948 | return true; | |
949 | } | |
950 | ||
951 | static void nvme_warn_reset(struct nvme_dev *dev, u32 csts) | |
952 | { | |
953 | /* Read a config register to help see what died. */ | |
954 | u16 pci_status; | |
955 | int result; | |
956 | ||
957 | result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS, | |
958 | &pci_status); | |
959 | if (result == PCIBIOS_SUCCESSFUL) | |
960 | dev_warn(dev->ctrl.device, | |
961 | "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n", | |
962 | csts, pci_status); | |
963 | else | |
964 | dev_warn(dev->ctrl.device, | |
965 | "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n", | |
966 | csts, result); | |
967 | } | |
968 | ||
31c7c7d2 | 969 | static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved) |
c30341dc | 970 | { |
f4800d6d CH |
971 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
972 | struct nvme_queue *nvmeq = iod->nvmeq; | |
c30341dc | 973 | struct nvme_dev *dev = nvmeq->dev; |
a4aea562 | 974 | struct request *abort_req; |
a4aea562 | 975 | struct nvme_command cmd; |
b2a0eb1a KB |
976 | u32 csts = readl(dev->bar + NVME_REG_CSTS); |
977 | ||
978 | /* | |
979 | * Reset immediately if the controller is failed | |
980 | */ | |
981 | if (nvme_should_reset(dev, csts)) { | |
982 | nvme_warn_reset(dev, csts); | |
983 | nvme_dev_disable(dev, false); | |
d86c4d8e | 984 | nvme_reset_ctrl(&dev->ctrl); |
b2a0eb1a KB |
985 | return BLK_EH_HANDLED; |
986 | } | |
c30341dc | 987 | |
7776db1c KB |
988 | /* |
989 | * Did we miss an interrupt? | |
990 | */ | |
991 | if (__nvme_poll(nvmeq, req->tag)) { | |
992 | dev_warn(dev->ctrl.device, | |
993 | "I/O %d QID %d timeout, completion polled\n", | |
994 | req->tag, nvmeq->qid); | |
995 | return BLK_EH_HANDLED; | |
996 | } | |
997 | ||
31c7c7d2 | 998 | /* |
fd634f41 CH |
999 | * Shutdown immediately if controller times out while starting. The |
1000 | * reset work will see the pci device disabled when it gets the forced | |
1001 | * cancellation error. All outstanding requests are completed on | |
1002 | * shutdown, so we return BLK_EH_HANDLED. | |
1003 | */ | |
bb8d261e | 1004 | if (dev->ctrl.state == NVME_CTRL_RESETTING) { |
1b3c47c1 | 1005 | dev_warn(dev->ctrl.device, |
fd634f41 CH |
1006 | "I/O %d QID %d timeout, disable controller\n", |
1007 | req->tag, nvmeq->qid); | |
a5cdb68c | 1008 | nvme_dev_disable(dev, false); |
27fa9bc5 | 1009 | nvme_req(req)->flags |= NVME_REQ_CANCELLED; |
fd634f41 | 1010 | return BLK_EH_HANDLED; |
c30341dc KB |
1011 | } |
1012 | ||
fd634f41 CH |
1013 | /* |
1014 | * Shutdown the controller immediately and schedule a reset if the | |
1015 | * command was already aborted once before and still hasn't been | |
1016 | * returned to the driver, or if this is the admin queue. | |
31c7c7d2 | 1017 | */ |
f4800d6d | 1018 | if (!nvmeq->qid || iod->aborted) { |
1b3c47c1 | 1019 | dev_warn(dev->ctrl.device, |
e1569a16 KB |
1020 | "I/O %d QID %d timeout, reset controller\n", |
1021 | req->tag, nvmeq->qid); | |
a5cdb68c | 1022 | nvme_dev_disable(dev, false); |
d86c4d8e | 1023 | nvme_reset_ctrl(&dev->ctrl); |
c30341dc | 1024 | |
e1569a16 KB |
1025 | /* |
1026 | * Mark the request as handled, since the inline shutdown | |
1027 | * forces all outstanding requests to complete. | |
1028 | */ | |
27fa9bc5 | 1029 | nvme_req(req)->flags |= NVME_REQ_CANCELLED; |
e1569a16 | 1030 | return BLK_EH_HANDLED; |
c30341dc | 1031 | } |
c30341dc | 1032 | |
e7a2a87d | 1033 | if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) { |
6bf25d16 | 1034 | atomic_inc(&dev->ctrl.abort_limit); |
31c7c7d2 | 1035 | return BLK_EH_RESET_TIMER; |
6bf25d16 | 1036 | } |
7bf7d778 | 1037 | iod->aborted = 1; |
a4aea562 | 1038 | |
c30341dc KB |
1039 | memset(&cmd, 0, sizeof(cmd)); |
1040 | cmd.abort.opcode = nvme_admin_abort_cmd; | |
a4aea562 | 1041 | cmd.abort.cid = req->tag; |
c30341dc | 1042 | cmd.abort.sqid = cpu_to_le16(nvmeq->qid); |
c30341dc | 1043 | |
1b3c47c1 SG |
1044 | dev_warn(nvmeq->dev->ctrl.device, |
1045 | "I/O %d QID %d timeout, aborting\n", | |
1046 | req->tag, nvmeq->qid); | |
e7a2a87d CH |
1047 | |
1048 | abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd, | |
eb71f435 | 1049 | BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); |
e7a2a87d CH |
1050 | if (IS_ERR(abort_req)) { |
1051 | atomic_inc(&dev->ctrl.abort_limit); | |
1052 | return BLK_EH_RESET_TIMER; | |
1053 | } | |
1054 | ||
1055 | abort_req->timeout = ADMIN_TIMEOUT; | |
1056 | abort_req->end_io_data = NULL; | |
1057 | blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio); | |
c30341dc | 1058 | |
31c7c7d2 CH |
1059 | /* |
1060 | * The aborted req will be completed on receiving the abort req. | |
1061 | * We enable the timer again. If hit twice, it'll cause a device reset, | |
1062 | * as the device then is in a faulty state. | |
1063 | */ | |
1064 | return BLK_EH_RESET_TIMER; | |
c30341dc KB |
1065 | } |
1066 | ||
a4aea562 MB |
1067 | static void nvme_free_queue(struct nvme_queue *nvmeq) |
1068 | { | |
9e866774 MW |
1069 | dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth), |
1070 | (void *)nvmeq->cqes, nvmeq->cq_dma_addr); | |
8ffaadf7 JD |
1071 | if (nvmeq->sq_cmds) |
1072 | dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth), | |
9e866774 MW |
1073 | nvmeq->sq_cmds, nvmeq->sq_dma_addr); |
1074 | kfree(nvmeq); | |
1075 | } | |
1076 | ||
a1a5ef99 | 1077 | static void nvme_free_queues(struct nvme_dev *dev, int lowest) |
22404274 KB |
1078 | { |
1079 | int i; | |
1080 | ||
a1a5ef99 | 1081 | for (i = dev->queue_count - 1; i >= lowest; i--) { |
a4aea562 | 1082 | struct nvme_queue *nvmeq = dev->queues[i]; |
22404274 | 1083 | dev->queue_count--; |
a4aea562 | 1084 | dev->queues[i] = NULL; |
f435c282 | 1085 | nvme_free_queue(nvmeq); |
121c7ad4 | 1086 | } |
22404274 KB |
1087 | } |
1088 | ||
4d115420 KB |
1089 | /** |
1090 | * nvme_suspend_queue - put queue into suspended state | |
1091 | * @nvmeq - queue to suspend | |
4d115420 KB |
1092 | */ |
1093 | static int nvme_suspend_queue(struct nvme_queue *nvmeq) | |
b60503ba | 1094 | { |
2b25d981 | 1095 | int vector; |
b60503ba | 1096 | |
a09115b2 | 1097 | spin_lock_irq(&nvmeq->q_lock); |
2b25d981 KB |
1098 | if (nvmeq->cq_vector == -1) { |
1099 | spin_unlock_irq(&nvmeq->q_lock); | |
1100 | return 1; | |
1101 | } | |
0ff199cb | 1102 | vector = nvmeq->cq_vector; |
42f61420 | 1103 | nvmeq->dev->online_queues--; |
2b25d981 | 1104 | nvmeq->cq_vector = -1; |
a09115b2 MW |
1105 | spin_unlock_irq(&nvmeq->q_lock); |
1106 | ||
1c63dc66 | 1107 | if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q) |
25646264 | 1108 | blk_mq_stop_hw_queues(nvmeq->dev->ctrl.admin_q); |
6df3dbc8 | 1109 | |
0ff199cb | 1110 | pci_free_irq(to_pci_dev(nvmeq->dev->dev), vector, nvmeq); |
b60503ba | 1111 | |
4d115420 KB |
1112 | return 0; |
1113 | } | |
b60503ba | 1114 | |
a5cdb68c | 1115 | static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown) |
4d115420 | 1116 | { |
a5cdb68c | 1117 | struct nvme_queue *nvmeq = dev->queues[0]; |
4d115420 KB |
1118 | |
1119 | if (!nvmeq) | |
1120 | return; | |
1121 | if (nvme_suspend_queue(nvmeq)) | |
1122 | return; | |
1123 | ||
a5cdb68c KB |
1124 | if (shutdown) |
1125 | nvme_shutdown_ctrl(&dev->ctrl); | |
1126 | else | |
1127 | nvme_disable_ctrl(&dev->ctrl, lo_hi_readq( | |
1128 | dev->bar + NVME_REG_CAP)); | |
07836e65 KB |
1129 | |
1130 | spin_lock_irq(&nvmeq->q_lock); | |
1131 | nvme_process_cq(nvmeq); | |
1132 | spin_unlock_irq(&nvmeq->q_lock); | |
b60503ba MW |
1133 | } |
1134 | ||
8ffaadf7 JD |
1135 | static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues, |
1136 | int entry_size) | |
1137 | { | |
1138 | int q_depth = dev->q_depth; | |
5fd4ce1b CH |
1139 | unsigned q_size_aligned = roundup(q_depth * entry_size, |
1140 | dev->ctrl.page_size); | |
8ffaadf7 JD |
1141 | |
1142 | if (q_size_aligned * nr_io_queues > dev->cmb_size) { | |
c45f5c99 | 1143 | u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues); |
5fd4ce1b | 1144 | mem_per_q = round_down(mem_per_q, dev->ctrl.page_size); |
c45f5c99 | 1145 | q_depth = div_u64(mem_per_q, entry_size); |
8ffaadf7 JD |
1146 | |
1147 | /* | |
1148 | * Ensure the reduced q_depth is above some threshold where it | |
1149 | * would be better to map queues in system memory with the | |
1150 | * original depth | |
1151 | */ | |
1152 | if (q_depth < 64) | |
1153 | return -ENOMEM; | |
1154 | } | |
1155 | ||
1156 | return q_depth; | |
1157 | } | |
1158 | ||
1159 | static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq, | |
1160 | int qid, int depth) | |
1161 | { | |
1162 | if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz)) { | |
5fd4ce1b CH |
1163 | unsigned offset = (qid - 1) * roundup(SQ_SIZE(depth), |
1164 | dev->ctrl.page_size); | |
8ffaadf7 JD |
1165 | nvmeq->sq_dma_addr = dev->cmb_dma_addr + offset; |
1166 | nvmeq->sq_cmds_io = dev->cmb + offset; | |
1167 | } else { | |
1168 | nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth), | |
1169 | &nvmeq->sq_dma_addr, GFP_KERNEL); | |
1170 | if (!nvmeq->sq_cmds) | |
1171 | return -ENOMEM; | |
1172 | } | |
1173 | ||
1174 | return 0; | |
1175 | } | |
1176 | ||
b60503ba | 1177 | static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid, |
d3af3ecd | 1178 | int depth, int node) |
b60503ba | 1179 | { |
d3af3ecd SL |
1180 | struct nvme_queue *nvmeq = kzalloc_node(sizeof(*nvmeq), GFP_KERNEL, |
1181 | node); | |
b60503ba MW |
1182 | if (!nvmeq) |
1183 | return NULL; | |
1184 | ||
e75ec752 | 1185 | nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth), |
4d51abf9 | 1186 | &nvmeq->cq_dma_addr, GFP_KERNEL); |
b60503ba MW |
1187 | if (!nvmeq->cqes) |
1188 | goto free_nvmeq; | |
b60503ba | 1189 | |
8ffaadf7 | 1190 | if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth)) |
b60503ba MW |
1191 | goto free_cqdma; |
1192 | ||
e75ec752 | 1193 | nvmeq->q_dmadev = dev->dev; |
091b6092 | 1194 | nvmeq->dev = dev; |
b60503ba MW |
1195 | spin_lock_init(&nvmeq->q_lock); |
1196 | nvmeq->cq_head = 0; | |
82123460 | 1197 | nvmeq->cq_phase = 1; |
b80d5ccc | 1198 | nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; |
b60503ba | 1199 | nvmeq->q_depth = depth; |
c30341dc | 1200 | nvmeq->qid = qid; |
758dd7fd | 1201 | nvmeq->cq_vector = -1; |
a4aea562 | 1202 | dev->queues[qid] = nvmeq; |
36a7e993 JD |
1203 | dev->queue_count++; |
1204 | ||
b60503ba MW |
1205 | return nvmeq; |
1206 | ||
1207 | free_cqdma: | |
e75ec752 | 1208 | dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes, |
b60503ba MW |
1209 | nvmeq->cq_dma_addr); |
1210 | free_nvmeq: | |
1211 | kfree(nvmeq); | |
1212 | return NULL; | |
1213 | } | |
1214 | ||
dca51e78 | 1215 | static int queue_request_irq(struct nvme_queue *nvmeq) |
3001082c | 1216 | { |
0ff199cb CH |
1217 | struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); |
1218 | int nr = nvmeq->dev->ctrl.instance; | |
1219 | ||
1220 | if (use_threaded_interrupts) { | |
1221 | return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check, | |
1222 | nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid); | |
1223 | } else { | |
1224 | return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq, | |
1225 | NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid); | |
1226 | } | |
3001082c MW |
1227 | } |
1228 | ||
22404274 | 1229 | static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) |
b60503ba | 1230 | { |
22404274 | 1231 | struct nvme_dev *dev = nvmeq->dev; |
b60503ba | 1232 | |
7be50e93 | 1233 | spin_lock_irq(&nvmeq->q_lock); |
22404274 KB |
1234 | nvmeq->sq_tail = 0; |
1235 | nvmeq->cq_head = 0; | |
1236 | nvmeq->cq_phase = 1; | |
b80d5ccc | 1237 | nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; |
22404274 | 1238 | memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth)); |
f9f38e33 | 1239 | nvme_dbbuf_init(dev, nvmeq, qid); |
42f61420 | 1240 | dev->online_queues++; |
7be50e93 | 1241 | spin_unlock_irq(&nvmeq->q_lock); |
22404274 KB |
1242 | } |
1243 | ||
1244 | static int nvme_create_queue(struct nvme_queue *nvmeq, int qid) | |
1245 | { | |
1246 | struct nvme_dev *dev = nvmeq->dev; | |
1247 | int result; | |
3f85d50b | 1248 | |
2b25d981 | 1249 | nvmeq->cq_vector = qid - 1; |
b60503ba MW |
1250 | result = adapter_alloc_cq(dev, qid, nvmeq); |
1251 | if (result < 0) | |
22404274 | 1252 | return result; |
b60503ba MW |
1253 | |
1254 | result = adapter_alloc_sq(dev, qid, nvmeq); | |
1255 | if (result < 0) | |
1256 | goto release_cq; | |
1257 | ||
dca51e78 | 1258 | result = queue_request_irq(nvmeq); |
b60503ba MW |
1259 | if (result < 0) |
1260 | goto release_sq; | |
1261 | ||
22404274 | 1262 | nvme_init_queue(nvmeq, qid); |
22404274 | 1263 | return result; |
b60503ba MW |
1264 | |
1265 | release_sq: | |
1266 | adapter_delete_sq(dev, qid); | |
1267 | release_cq: | |
1268 | adapter_delete_cq(dev, qid); | |
22404274 | 1269 | return result; |
b60503ba MW |
1270 | } |
1271 | ||
f363b089 | 1272 | static const struct blk_mq_ops nvme_mq_admin_ops = { |
d29ec824 | 1273 | .queue_rq = nvme_queue_rq, |
77f02a7a | 1274 | .complete = nvme_pci_complete_rq, |
a4aea562 | 1275 | .init_hctx = nvme_admin_init_hctx, |
4af0e21c | 1276 | .exit_hctx = nvme_admin_exit_hctx, |
0350815a | 1277 | .init_request = nvme_init_request, |
a4aea562 MB |
1278 | .timeout = nvme_timeout, |
1279 | }; | |
1280 | ||
f363b089 | 1281 | static const struct blk_mq_ops nvme_mq_ops = { |
a4aea562 | 1282 | .queue_rq = nvme_queue_rq, |
77f02a7a | 1283 | .complete = nvme_pci_complete_rq, |
a4aea562 MB |
1284 | .init_hctx = nvme_init_hctx, |
1285 | .init_request = nvme_init_request, | |
dca51e78 | 1286 | .map_queues = nvme_pci_map_queues, |
a4aea562 | 1287 | .timeout = nvme_timeout, |
a0fa9647 | 1288 | .poll = nvme_poll, |
a4aea562 MB |
1289 | }; |
1290 | ||
ea191d2f KB |
1291 | static void nvme_dev_remove_admin(struct nvme_dev *dev) |
1292 | { | |
1c63dc66 | 1293 | if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) { |
69d9a99c KB |
1294 | /* |
1295 | * If the controller was reset during removal, it's possible | |
1296 | * user requests may be waiting on a stopped queue. Start the | |
1297 | * queue to flush these to completion. | |
1298 | */ | |
1299 | blk_mq_start_stopped_hw_queues(dev->ctrl.admin_q, true); | |
1c63dc66 | 1300 | blk_cleanup_queue(dev->ctrl.admin_q); |
ea191d2f KB |
1301 | blk_mq_free_tag_set(&dev->admin_tagset); |
1302 | } | |
1303 | } | |
1304 | ||
a4aea562 MB |
1305 | static int nvme_alloc_admin_tags(struct nvme_dev *dev) |
1306 | { | |
1c63dc66 | 1307 | if (!dev->ctrl.admin_q) { |
a4aea562 MB |
1308 | dev->admin_tagset.ops = &nvme_mq_admin_ops; |
1309 | dev->admin_tagset.nr_hw_queues = 1; | |
e3e9d50c KB |
1310 | |
1311 | /* | |
1312 | * Subtract one to leave an empty queue entry for 'Full Queue' | |
1313 | * condition. See NVM-Express 1.2 specification, section 4.1.2. | |
1314 | */ | |
1315 | dev->admin_tagset.queue_depth = NVME_AQ_BLKMQ_DEPTH - 1; | |
a4aea562 | 1316 | dev->admin_tagset.timeout = ADMIN_TIMEOUT; |
e75ec752 | 1317 | dev->admin_tagset.numa_node = dev_to_node(dev->dev); |
ac3dd5bd | 1318 | dev->admin_tagset.cmd_size = nvme_cmd_size(dev); |
d3484991 | 1319 | dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED; |
a4aea562 MB |
1320 | dev->admin_tagset.driver_data = dev; |
1321 | ||
1322 | if (blk_mq_alloc_tag_set(&dev->admin_tagset)) | |
1323 | return -ENOMEM; | |
1324 | ||
1c63dc66 CH |
1325 | dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset); |
1326 | if (IS_ERR(dev->ctrl.admin_q)) { | |
a4aea562 MB |
1327 | blk_mq_free_tag_set(&dev->admin_tagset); |
1328 | return -ENOMEM; | |
1329 | } | |
1c63dc66 | 1330 | if (!blk_get_queue(dev->ctrl.admin_q)) { |
ea191d2f | 1331 | nvme_dev_remove_admin(dev); |
1c63dc66 | 1332 | dev->ctrl.admin_q = NULL; |
ea191d2f KB |
1333 | return -ENODEV; |
1334 | } | |
0fb59cbc | 1335 | } else |
25646264 | 1336 | blk_mq_start_stopped_hw_queues(dev->ctrl.admin_q, true); |
a4aea562 MB |
1337 | |
1338 | return 0; | |
1339 | } | |
1340 | ||
97f6ef64 XY |
1341 | static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) |
1342 | { | |
1343 | return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride); | |
1344 | } | |
1345 | ||
1346 | static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size) | |
1347 | { | |
1348 | struct pci_dev *pdev = to_pci_dev(dev->dev); | |
1349 | ||
1350 | if (size <= dev->bar_mapped_size) | |
1351 | return 0; | |
1352 | if (size > pci_resource_len(pdev, 0)) | |
1353 | return -ENOMEM; | |
1354 | if (dev->bar) | |
1355 | iounmap(dev->bar); | |
1356 | dev->bar = ioremap(pci_resource_start(pdev, 0), size); | |
1357 | if (!dev->bar) { | |
1358 | dev->bar_mapped_size = 0; | |
1359 | return -ENOMEM; | |
1360 | } | |
1361 | dev->bar_mapped_size = size; | |
1362 | dev->dbs = dev->bar + NVME_REG_DBS; | |
1363 | ||
1364 | return 0; | |
1365 | } | |
1366 | ||
8d85fce7 | 1367 | static int nvme_configure_admin_queue(struct nvme_dev *dev) |
b60503ba | 1368 | { |
ba47e386 | 1369 | int result; |
b60503ba | 1370 | u32 aqa; |
7a67cbea | 1371 | u64 cap = lo_hi_readq(dev->bar + NVME_REG_CAP); |
b60503ba MW |
1372 | struct nvme_queue *nvmeq; |
1373 | ||
97f6ef64 XY |
1374 | result = nvme_remap_bar(dev, db_bar_size(dev, 0)); |
1375 | if (result < 0) | |
1376 | return result; | |
1377 | ||
8ef2074d | 1378 | dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ? |
dfbac8c7 KB |
1379 | NVME_CAP_NSSRC(cap) : 0; |
1380 | ||
7a67cbea CH |
1381 | if (dev->subsystem && |
1382 | (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO)) | |
1383 | writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS); | |
dfbac8c7 | 1384 | |
5fd4ce1b | 1385 | result = nvme_disable_ctrl(&dev->ctrl, cap); |
ba47e386 MW |
1386 | if (result < 0) |
1387 | return result; | |
b60503ba | 1388 | |
a4aea562 | 1389 | nvmeq = dev->queues[0]; |
cd638946 | 1390 | if (!nvmeq) { |
d3af3ecd SL |
1391 | nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH, |
1392 | dev_to_node(dev->dev)); | |
cd638946 KB |
1393 | if (!nvmeq) |
1394 | return -ENOMEM; | |
cd638946 | 1395 | } |
b60503ba MW |
1396 | |
1397 | aqa = nvmeq->q_depth - 1; | |
1398 | aqa |= aqa << 16; | |
1399 | ||
7a67cbea CH |
1400 | writel(aqa, dev->bar + NVME_REG_AQA); |
1401 | lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ); | |
1402 | lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ); | |
b60503ba | 1403 | |
5fd4ce1b | 1404 | result = nvme_enable_ctrl(&dev->ctrl, cap); |
025c557a | 1405 | if (result) |
d4875622 | 1406 | return result; |
a4aea562 | 1407 | |
2b25d981 | 1408 | nvmeq->cq_vector = 0; |
dca51e78 | 1409 | result = queue_request_irq(nvmeq); |
758dd7fd JD |
1410 | if (result) { |
1411 | nvmeq->cq_vector = -1; | |
d4875622 | 1412 | return result; |
758dd7fd | 1413 | } |
025c557a | 1414 | |
b60503ba MW |
1415 | return result; |
1416 | } | |
1417 | ||
749941f2 | 1418 | static int nvme_create_io_queues(struct nvme_dev *dev) |
42f61420 | 1419 | { |
949928c1 | 1420 | unsigned i, max; |
749941f2 | 1421 | int ret = 0; |
42f61420 | 1422 | |
749941f2 | 1423 | for (i = dev->queue_count; i <= dev->max_qid; i++) { |
d3af3ecd SL |
1424 | /* vector == qid - 1, match nvme_create_queue */ |
1425 | if (!nvme_alloc_queue(dev, i, dev->q_depth, | |
1426 | pci_irq_get_node(to_pci_dev(dev->dev), i - 1))) { | |
749941f2 | 1427 | ret = -ENOMEM; |
42f61420 | 1428 | break; |
749941f2 CH |
1429 | } |
1430 | } | |
42f61420 | 1431 | |
949928c1 KB |
1432 | max = min(dev->max_qid, dev->queue_count - 1); |
1433 | for (i = dev->online_queues; i <= max; i++) { | |
749941f2 | 1434 | ret = nvme_create_queue(dev->queues[i], i); |
d4875622 | 1435 | if (ret) |
42f61420 | 1436 | break; |
27e8166c | 1437 | } |
749941f2 CH |
1438 | |
1439 | /* | |
1440 | * Ignore failing Create SQ/CQ commands, we can continue with less | |
1441 | * than the desired aount of queues, and even a controller without | |
1442 | * I/O queues an still be used to issue admin commands. This might | |
1443 | * be useful to upgrade a buggy firmware for example. | |
1444 | */ | |
1445 | return ret >= 0 ? 0 : ret; | |
b60503ba MW |
1446 | } |
1447 | ||
202021c1 SB |
1448 | static ssize_t nvme_cmb_show(struct device *dev, |
1449 | struct device_attribute *attr, | |
1450 | char *buf) | |
1451 | { | |
1452 | struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); | |
1453 | ||
c965809c | 1454 | return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n", |
202021c1 SB |
1455 | ndev->cmbloc, ndev->cmbsz); |
1456 | } | |
1457 | static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL); | |
1458 | ||
8ffaadf7 JD |
1459 | static void __iomem *nvme_map_cmb(struct nvme_dev *dev) |
1460 | { | |
1461 | u64 szu, size, offset; | |
8ffaadf7 JD |
1462 | resource_size_t bar_size; |
1463 | struct pci_dev *pdev = to_pci_dev(dev->dev); | |
1464 | void __iomem *cmb; | |
1465 | dma_addr_t dma_addr; | |
1466 | ||
7a67cbea | 1467 | dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ); |
8ffaadf7 JD |
1468 | if (!(NVME_CMB_SZ(dev->cmbsz))) |
1469 | return NULL; | |
202021c1 | 1470 | dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC); |
8ffaadf7 | 1471 | |
202021c1 SB |
1472 | if (!use_cmb_sqes) |
1473 | return NULL; | |
8ffaadf7 JD |
1474 | |
1475 | szu = (u64)1 << (12 + 4 * NVME_CMB_SZU(dev->cmbsz)); | |
1476 | size = szu * NVME_CMB_SZ(dev->cmbsz); | |
202021c1 SB |
1477 | offset = szu * NVME_CMB_OFST(dev->cmbloc); |
1478 | bar_size = pci_resource_len(pdev, NVME_CMB_BIR(dev->cmbloc)); | |
8ffaadf7 JD |
1479 | |
1480 | if (offset > bar_size) | |
1481 | return NULL; | |
1482 | ||
1483 | /* | |
1484 | * Controllers may support a CMB size larger than their BAR, | |
1485 | * for example, due to being behind a bridge. Reduce the CMB to | |
1486 | * the reported size of the BAR | |
1487 | */ | |
1488 | if (size > bar_size - offset) | |
1489 | size = bar_size - offset; | |
1490 | ||
202021c1 | 1491 | dma_addr = pci_resource_start(pdev, NVME_CMB_BIR(dev->cmbloc)) + offset; |
8ffaadf7 JD |
1492 | cmb = ioremap_wc(dma_addr, size); |
1493 | if (!cmb) | |
1494 | return NULL; | |
1495 | ||
1496 | dev->cmb_dma_addr = dma_addr; | |
1497 | dev->cmb_size = size; | |
1498 | return cmb; | |
1499 | } | |
1500 | ||
1501 | static inline void nvme_release_cmb(struct nvme_dev *dev) | |
1502 | { | |
1503 | if (dev->cmb) { | |
1504 | iounmap(dev->cmb); | |
1505 | dev->cmb = NULL; | |
f63572df JD |
1506 | if (dev->cmbsz) { |
1507 | sysfs_remove_file_from_group(&dev->ctrl.device->kobj, | |
1508 | &dev_attr_cmb.attr, NULL); | |
1509 | dev->cmbsz = 0; | |
1510 | } | |
8ffaadf7 JD |
1511 | } |
1512 | } | |
1513 | ||
87ad72a5 CH |
1514 | static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits) |
1515 | { | |
1516 | size_t len = dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs); | |
1517 | struct nvme_command c; | |
1518 | u64 dma_addr; | |
1519 | int ret; | |
1520 | ||
1521 | dma_addr = dma_map_single(dev->dev, dev->host_mem_descs, len, | |
1522 | DMA_TO_DEVICE); | |
1523 | if (dma_mapping_error(dev->dev, dma_addr)) | |
1524 | return -ENOMEM; | |
1525 | ||
1526 | memset(&c, 0, sizeof(c)); | |
1527 | c.features.opcode = nvme_admin_set_features; | |
1528 | c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF); | |
1529 | c.features.dword11 = cpu_to_le32(bits); | |
1530 | c.features.dword12 = cpu_to_le32(dev->host_mem_size >> | |
1531 | ilog2(dev->ctrl.page_size)); | |
1532 | c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr)); | |
1533 | c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr)); | |
1534 | c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs); | |
1535 | ||
1536 | ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); | |
1537 | if (ret) { | |
1538 | dev_warn(dev->ctrl.device, | |
1539 | "failed to set host mem (err %d, flags %#x).\n", | |
1540 | ret, bits); | |
1541 | } | |
1542 | dma_unmap_single(dev->dev, dma_addr, len, DMA_TO_DEVICE); | |
1543 | return ret; | |
1544 | } | |
1545 | ||
1546 | static void nvme_free_host_mem(struct nvme_dev *dev) | |
1547 | { | |
1548 | int i; | |
1549 | ||
1550 | for (i = 0; i < dev->nr_host_mem_descs; i++) { | |
1551 | struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i]; | |
1552 | size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size; | |
1553 | ||
1554 | dma_free_coherent(dev->dev, size, dev->host_mem_desc_bufs[i], | |
1555 | le64_to_cpu(desc->addr)); | |
1556 | } | |
1557 | ||
1558 | kfree(dev->host_mem_desc_bufs); | |
1559 | dev->host_mem_desc_bufs = NULL; | |
1560 | kfree(dev->host_mem_descs); | |
1561 | dev->host_mem_descs = NULL; | |
1562 | } | |
1563 | ||
1564 | static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred) | |
1565 | { | |
1566 | struct nvme_host_mem_buf_desc *descs; | |
1567 | u32 chunk_size, max_entries, i = 0; | |
1568 | void **bufs; | |
1569 | u64 size, tmp; | |
1570 | ||
1571 | /* start big and work our way down */ | |
1572 | chunk_size = min(preferred, (u64)PAGE_SIZE << MAX_ORDER); | |
1573 | retry: | |
1574 | tmp = (preferred + chunk_size - 1); | |
1575 | do_div(tmp, chunk_size); | |
1576 | max_entries = tmp; | |
1577 | descs = kcalloc(max_entries, sizeof(*descs), GFP_KERNEL); | |
1578 | if (!descs) | |
1579 | goto out; | |
1580 | ||
1581 | bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL); | |
1582 | if (!bufs) | |
1583 | goto out_free_descs; | |
1584 | ||
1585 | for (size = 0; size < preferred; size += chunk_size) { | |
1586 | u32 len = min_t(u64, chunk_size, preferred - size); | |
1587 | dma_addr_t dma_addr; | |
1588 | ||
1589 | bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL, | |
1590 | DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); | |
1591 | if (!bufs[i]) | |
1592 | break; | |
1593 | ||
1594 | descs[i].addr = cpu_to_le64(dma_addr); | |
1595 | descs[i].size = cpu_to_le32(len / dev->ctrl.page_size); | |
1596 | i++; | |
1597 | } | |
1598 | ||
1599 | if (!size || (min && size < min)) { | |
1600 | dev_warn(dev->ctrl.device, | |
1601 | "failed to allocate host memory buffer.\n"); | |
1602 | goto out_free_bufs; | |
1603 | } | |
1604 | ||
1605 | dev_info(dev->ctrl.device, | |
1606 | "allocated %lld MiB host memory buffer.\n", | |
1607 | size >> ilog2(SZ_1M)); | |
1608 | dev->nr_host_mem_descs = i; | |
1609 | dev->host_mem_size = size; | |
1610 | dev->host_mem_descs = descs; | |
1611 | dev->host_mem_desc_bufs = bufs; | |
1612 | return 0; | |
1613 | ||
1614 | out_free_bufs: | |
1615 | while (--i >= 0) { | |
1616 | size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size; | |
1617 | ||
1618 | dma_free_coherent(dev->dev, size, bufs[i], | |
1619 | le64_to_cpu(descs[i].addr)); | |
1620 | } | |
1621 | ||
1622 | kfree(bufs); | |
1623 | out_free_descs: | |
1624 | kfree(descs); | |
1625 | out: | |
1626 | /* try a smaller chunk size if we failed early */ | |
1627 | if (chunk_size >= PAGE_SIZE * 2 && (i == 0 || size < min)) { | |
1628 | chunk_size /= 2; | |
1629 | goto retry; | |
1630 | } | |
1631 | dev->host_mem_descs = NULL; | |
1632 | return -ENOMEM; | |
1633 | } | |
1634 | ||
1635 | static void nvme_setup_host_mem(struct nvme_dev *dev) | |
1636 | { | |
1637 | u64 max = (u64)max_host_mem_size_mb * SZ_1M; | |
1638 | u64 preferred = (u64)dev->ctrl.hmpre * 4096; | |
1639 | u64 min = (u64)dev->ctrl.hmmin * 4096; | |
1640 | u32 enable_bits = NVME_HOST_MEM_ENABLE; | |
1641 | ||
1642 | preferred = min(preferred, max); | |
1643 | if (min > max) { | |
1644 | dev_warn(dev->ctrl.device, | |
1645 | "min host memory (%lld MiB) above limit (%d MiB).\n", | |
1646 | min >> ilog2(SZ_1M), max_host_mem_size_mb); | |
1647 | nvme_free_host_mem(dev); | |
1648 | return; | |
1649 | } | |
1650 | ||
1651 | /* | |
1652 | * If we already have a buffer allocated check if we can reuse it. | |
1653 | */ | |
1654 | if (dev->host_mem_descs) { | |
1655 | if (dev->host_mem_size >= min) | |
1656 | enable_bits |= NVME_HOST_MEM_RETURN; | |
1657 | else | |
1658 | nvme_free_host_mem(dev); | |
1659 | } | |
1660 | ||
1661 | if (!dev->host_mem_descs) { | |
1662 | if (nvme_alloc_host_mem(dev, min, preferred)) | |
1663 | return; | |
1664 | } | |
1665 | ||
1666 | if (nvme_set_host_mem(dev, enable_bits)) | |
1667 | nvme_free_host_mem(dev); | |
1668 | } | |
1669 | ||
8d85fce7 | 1670 | static int nvme_setup_io_queues(struct nvme_dev *dev) |
b60503ba | 1671 | { |
a4aea562 | 1672 | struct nvme_queue *adminq = dev->queues[0]; |
e75ec752 | 1673 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
97f6ef64 XY |
1674 | int result, nr_io_queues; |
1675 | unsigned long size; | |
b60503ba | 1676 | |
2800b8e7 | 1677 | nr_io_queues = num_online_cpus(); |
9a0be7ab CH |
1678 | result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues); |
1679 | if (result < 0) | |
1b23484b | 1680 | return result; |
9a0be7ab | 1681 | |
f5fa90dc | 1682 | if (nr_io_queues == 0) |
a5229050 | 1683 | return 0; |
b60503ba | 1684 | |
8ffaadf7 JD |
1685 | if (dev->cmb && NVME_CMB_SQS(dev->cmbsz)) { |
1686 | result = nvme_cmb_qdepth(dev, nr_io_queues, | |
1687 | sizeof(struct nvme_command)); | |
1688 | if (result > 0) | |
1689 | dev->q_depth = result; | |
1690 | else | |
1691 | nvme_release_cmb(dev); | |
1692 | } | |
1693 | ||
97f6ef64 XY |
1694 | do { |
1695 | size = db_bar_size(dev, nr_io_queues); | |
1696 | result = nvme_remap_bar(dev, size); | |
1697 | if (!result) | |
1698 | break; | |
1699 | if (!--nr_io_queues) | |
1700 | return -ENOMEM; | |
1701 | } while (1); | |
1702 | adminq->q_db = dev->dbs; | |
f1938f6e | 1703 | |
9d713c2b | 1704 | /* Deregister the admin queue's interrupt */ |
0ff199cb | 1705 | pci_free_irq(pdev, 0, adminq); |
9d713c2b | 1706 | |
e32efbfc JA |
1707 | /* |
1708 | * If we enable msix early due to not intx, disable it again before | |
1709 | * setting up the full range we need. | |
1710 | */ | |
dca51e78 CH |
1711 | pci_free_irq_vectors(pdev); |
1712 | nr_io_queues = pci_alloc_irq_vectors(pdev, 1, nr_io_queues, | |
1713 | PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY); | |
1714 | if (nr_io_queues <= 0) | |
1715 | return -EIO; | |
1716 | dev->max_qid = nr_io_queues; | |
fa08a396 | 1717 | |
063a8096 MW |
1718 | /* |
1719 | * Should investigate if there's a performance win from allocating | |
1720 | * more queues than interrupt vectors; it might allow the submission | |
1721 | * path to scale better, even if the receive path is limited by the | |
1722 | * number of interrupts. | |
1723 | */ | |
063a8096 | 1724 | |
dca51e78 | 1725 | result = queue_request_irq(adminq); |
758dd7fd JD |
1726 | if (result) { |
1727 | adminq->cq_vector = -1; | |
d4875622 | 1728 | return result; |
758dd7fd | 1729 | } |
749941f2 | 1730 | return nvme_create_io_queues(dev); |
b60503ba MW |
1731 | } |
1732 | ||
2a842aca | 1733 | static void nvme_del_queue_end(struct request *req, blk_status_t error) |
a5768aa8 | 1734 | { |
db3cbfff | 1735 | struct nvme_queue *nvmeq = req->end_io_data; |
b5875222 | 1736 | |
db3cbfff KB |
1737 | blk_mq_free_request(req); |
1738 | complete(&nvmeq->dev->ioq_wait); | |
a5768aa8 KB |
1739 | } |
1740 | ||
2a842aca | 1741 | static void nvme_del_cq_end(struct request *req, blk_status_t error) |
a5768aa8 | 1742 | { |
db3cbfff | 1743 | struct nvme_queue *nvmeq = req->end_io_data; |
a5768aa8 | 1744 | |
db3cbfff KB |
1745 | if (!error) { |
1746 | unsigned long flags; | |
1747 | ||
2e39e0f6 ML |
1748 | /* |
1749 | * We might be called with the AQ q_lock held | |
1750 | * and the I/O queue q_lock should always | |
1751 | * nest inside the AQ one. | |
1752 | */ | |
1753 | spin_lock_irqsave_nested(&nvmeq->q_lock, flags, | |
1754 | SINGLE_DEPTH_NESTING); | |
db3cbfff KB |
1755 | nvme_process_cq(nvmeq); |
1756 | spin_unlock_irqrestore(&nvmeq->q_lock, flags); | |
a5768aa8 | 1757 | } |
db3cbfff KB |
1758 | |
1759 | nvme_del_queue_end(req, error); | |
a5768aa8 KB |
1760 | } |
1761 | ||
db3cbfff | 1762 | static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode) |
bda4e0fb | 1763 | { |
db3cbfff KB |
1764 | struct request_queue *q = nvmeq->dev->ctrl.admin_q; |
1765 | struct request *req; | |
1766 | struct nvme_command cmd; | |
bda4e0fb | 1767 | |
db3cbfff KB |
1768 | memset(&cmd, 0, sizeof(cmd)); |
1769 | cmd.delete_queue.opcode = opcode; | |
1770 | cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid); | |
bda4e0fb | 1771 | |
eb71f435 | 1772 | req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); |
db3cbfff KB |
1773 | if (IS_ERR(req)) |
1774 | return PTR_ERR(req); | |
bda4e0fb | 1775 | |
db3cbfff KB |
1776 | req->timeout = ADMIN_TIMEOUT; |
1777 | req->end_io_data = nvmeq; | |
1778 | ||
1779 | blk_execute_rq_nowait(q, NULL, req, false, | |
1780 | opcode == nvme_admin_delete_cq ? | |
1781 | nvme_del_cq_end : nvme_del_queue_end); | |
1782 | return 0; | |
bda4e0fb KB |
1783 | } |
1784 | ||
70659060 | 1785 | static void nvme_disable_io_queues(struct nvme_dev *dev, int queues) |
a5768aa8 | 1786 | { |
70659060 | 1787 | int pass; |
db3cbfff KB |
1788 | unsigned long timeout; |
1789 | u8 opcode = nvme_admin_delete_sq; | |
a5768aa8 | 1790 | |
db3cbfff | 1791 | for (pass = 0; pass < 2; pass++) { |
014a0d60 | 1792 | int sent = 0, i = queues; |
db3cbfff KB |
1793 | |
1794 | reinit_completion(&dev->ioq_wait); | |
1795 | retry: | |
1796 | timeout = ADMIN_TIMEOUT; | |
c21377f8 GKB |
1797 | for (; i > 0; i--, sent++) |
1798 | if (nvme_delete_queue(dev->queues[i], opcode)) | |
db3cbfff | 1799 | break; |
c21377f8 | 1800 | |
db3cbfff KB |
1801 | while (sent--) { |
1802 | timeout = wait_for_completion_io_timeout(&dev->ioq_wait, timeout); | |
1803 | if (timeout == 0) | |
1804 | return; | |
1805 | if (i) | |
1806 | goto retry; | |
1807 | } | |
1808 | opcode = nvme_admin_delete_cq; | |
1809 | } | |
a5768aa8 KB |
1810 | } |
1811 | ||
422ef0c7 MW |
1812 | /* |
1813 | * Return: error value if an error occurred setting up the queues or calling | |
1814 | * Identify Device. 0 if these succeeded, even if adding some of the | |
1815 | * namespaces failed. At the moment, these failures are silent. TBD which | |
1816 | * failures should be reported. | |
1817 | */ | |
8d85fce7 | 1818 | static int nvme_dev_add(struct nvme_dev *dev) |
b60503ba | 1819 | { |
5bae7f73 | 1820 | if (!dev->ctrl.tagset) { |
ffe7704d KB |
1821 | dev->tagset.ops = &nvme_mq_ops; |
1822 | dev->tagset.nr_hw_queues = dev->online_queues - 1; | |
1823 | dev->tagset.timeout = NVME_IO_TIMEOUT; | |
1824 | dev->tagset.numa_node = dev_to_node(dev->dev); | |
1825 | dev->tagset.queue_depth = | |
a4aea562 | 1826 | min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1; |
ffe7704d KB |
1827 | dev->tagset.cmd_size = nvme_cmd_size(dev); |
1828 | dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE; | |
1829 | dev->tagset.driver_data = dev; | |
b60503ba | 1830 | |
ffe7704d KB |
1831 | if (blk_mq_alloc_tag_set(&dev->tagset)) |
1832 | return 0; | |
5bae7f73 | 1833 | dev->ctrl.tagset = &dev->tagset; |
f9f38e33 HK |
1834 | |
1835 | nvme_dbbuf_set(dev); | |
949928c1 KB |
1836 | } else { |
1837 | blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1); | |
1838 | ||
1839 | /* Free previously allocated queues that are no longer usable */ | |
1840 | nvme_free_queues(dev, dev->online_queues); | |
ffe7704d | 1841 | } |
949928c1 | 1842 | |
e1e5e564 | 1843 | return 0; |
b60503ba MW |
1844 | } |
1845 | ||
b00a726a | 1846 | static int nvme_pci_enable(struct nvme_dev *dev) |
0877cb0d | 1847 | { |
42f61420 | 1848 | u64 cap; |
b00a726a | 1849 | int result = -ENOMEM; |
e75ec752 | 1850 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
0877cb0d KB |
1851 | |
1852 | if (pci_enable_device_mem(pdev)) | |
1853 | return result; | |
1854 | ||
0877cb0d | 1855 | pci_set_master(pdev); |
0877cb0d | 1856 | |
e75ec752 CH |
1857 | if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) && |
1858 | dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32))) | |
052d0efa | 1859 | goto disable; |
0877cb0d | 1860 | |
7a67cbea | 1861 | if (readl(dev->bar + NVME_REG_CSTS) == -1) { |
0e53d180 | 1862 | result = -ENODEV; |
b00a726a | 1863 | goto disable; |
0e53d180 | 1864 | } |
e32efbfc JA |
1865 | |
1866 | /* | |
a5229050 KB |
1867 | * Some devices and/or platforms don't advertise or work with INTx |
1868 | * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll | |
1869 | * adjust this later. | |
e32efbfc | 1870 | */ |
dca51e78 CH |
1871 | result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); |
1872 | if (result < 0) | |
1873 | return result; | |
e32efbfc | 1874 | |
7a67cbea CH |
1875 | cap = lo_hi_readq(dev->bar + NVME_REG_CAP); |
1876 | ||
42f61420 KB |
1877 | dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH); |
1878 | dev->db_stride = 1 << NVME_CAP_STRIDE(cap); | |
7a67cbea | 1879 | dev->dbs = dev->bar + 4096; |
1f390c1f SG |
1880 | |
1881 | /* | |
1882 | * Temporary fix for the Apple controller found in the MacBook8,1 and | |
1883 | * some MacBook7,1 to avoid controller resets and data loss. | |
1884 | */ | |
1885 | if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) { | |
1886 | dev->q_depth = 2; | |
9bdcfb10 CH |
1887 | dev_warn(dev->ctrl.device, "detected Apple NVMe controller, " |
1888 | "set queue depth=%u to work around controller resets\n", | |
1f390c1f SG |
1889 | dev->q_depth); |
1890 | } | |
1891 | ||
202021c1 SB |
1892 | /* |
1893 | * CMBs can currently only exist on >=1.2 PCIe devices. We only | |
1894 | * populate sysfs if a CMB is implemented. Note that we add the | |
1895 | * CMB attribute to the nvme_ctrl kobj which removes the need to remove | |
1896 | * it on exit. Since nvme_dev_attrs_group has no name we can pass | |
1897 | * NULL as final argument to sysfs_add_file_to_group. | |
1898 | */ | |
1899 | ||
8ef2074d | 1900 | if (readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 2, 0)) { |
8ffaadf7 | 1901 | dev->cmb = nvme_map_cmb(dev); |
0877cb0d | 1902 | |
202021c1 SB |
1903 | if (dev->cmbsz) { |
1904 | if (sysfs_add_file_to_group(&dev->ctrl.device->kobj, | |
1905 | &dev_attr_cmb.attr, NULL)) | |
9bdcfb10 | 1906 | dev_warn(dev->ctrl.device, |
202021c1 SB |
1907 | "failed to add sysfs attribute for CMB\n"); |
1908 | } | |
1909 | } | |
1910 | ||
a0a3408e KB |
1911 | pci_enable_pcie_error_reporting(pdev); |
1912 | pci_save_state(pdev); | |
0877cb0d KB |
1913 | return 0; |
1914 | ||
1915 | disable: | |
0877cb0d KB |
1916 | pci_disable_device(pdev); |
1917 | return result; | |
1918 | } | |
1919 | ||
1920 | static void nvme_dev_unmap(struct nvme_dev *dev) | |
b00a726a KB |
1921 | { |
1922 | if (dev->bar) | |
1923 | iounmap(dev->bar); | |
a1f447b3 | 1924 | pci_release_mem_regions(to_pci_dev(dev->dev)); |
b00a726a KB |
1925 | } |
1926 | ||
1927 | static void nvme_pci_disable(struct nvme_dev *dev) | |
0877cb0d | 1928 | { |
e75ec752 CH |
1929 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
1930 | ||
f63572df | 1931 | nvme_release_cmb(dev); |
dca51e78 | 1932 | pci_free_irq_vectors(pdev); |
0877cb0d | 1933 | |
a0a3408e KB |
1934 | if (pci_is_enabled(pdev)) { |
1935 | pci_disable_pcie_error_reporting(pdev); | |
e75ec752 | 1936 | pci_disable_device(pdev); |
4d115420 | 1937 | } |
4d115420 KB |
1938 | } |
1939 | ||
a5cdb68c | 1940 | static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown) |
b60503ba | 1941 | { |
70659060 | 1942 | int i, queues; |
302ad8cc KB |
1943 | bool dead = true; |
1944 | struct pci_dev *pdev = to_pci_dev(dev->dev); | |
22404274 | 1945 | |
77bf25ea | 1946 | mutex_lock(&dev->shutdown_lock); |
302ad8cc KB |
1947 | if (pci_is_enabled(pdev)) { |
1948 | u32 csts = readl(dev->bar + NVME_REG_CSTS); | |
1949 | ||
1950 | if (dev->ctrl.state == NVME_CTRL_LIVE) | |
1951 | nvme_start_freeze(&dev->ctrl); | |
1952 | dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) || | |
1953 | pdev->error_state != pci_channel_io_normal); | |
c9d3bf88 | 1954 | } |
c21377f8 | 1955 | |
302ad8cc KB |
1956 | /* |
1957 | * Give the controller a chance to complete all entered requests if | |
1958 | * doing a safe shutdown. | |
1959 | */ | |
87ad72a5 CH |
1960 | if (!dead) { |
1961 | if (shutdown) | |
1962 | nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT); | |
1963 | ||
1964 | /* | |
1965 | * If the controller is still alive tell it to stop using the | |
1966 | * host memory buffer. In theory the shutdown / reset should | |
1967 | * make sure that it doesn't access the host memoery anymore, | |
1968 | * but I'd rather be safe than sorry.. | |
1969 | */ | |
1970 | if (dev->host_mem_descs) | |
1971 | nvme_set_host_mem(dev, 0); | |
1972 | ||
1973 | } | |
302ad8cc KB |
1974 | nvme_stop_queues(&dev->ctrl); |
1975 | ||
70659060 | 1976 | queues = dev->online_queues - 1; |
c21377f8 GKB |
1977 | for (i = dev->queue_count - 1; i > 0; i--) |
1978 | nvme_suspend_queue(dev->queues[i]); | |
1979 | ||
302ad8cc | 1980 | if (dead) { |
82469c59 GKB |
1981 | /* A device might become IO incapable very soon during |
1982 | * probe, before the admin queue is configured. Thus, | |
1983 | * queue_count can be 0 here. | |
1984 | */ | |
1985 | if (dev->queue_count) | |
1986 | nvme_suspend_queue(dev->queues[0]); | |
4d115420 | 1987 | } else { |
70659060 | 1988 | nvme_disable_io_queues(dev, queues); |
a5cdb68c | 1989 | nvme_disable_admin_queue(dev, shutdown); |
4d115420 | 1990 | } |
b00a726a | 1991 | nvme_pci_disable(dev); |
07836e65 | 1992 | |
e1958e65 ML |
1993 | blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl); |
1994 | blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl); | |
302ad8cc KB |
1995 | |
1996 | /* | |
1997 | * The driver will not be starting up queues again if shutting down so | |
1998 | * must flush all entered requests to their failed completion to avoid | |
1999 | * deadlocking blk-mq hot-cpu notifier. | |
2000 | */ | |
2001 | if (shutdown) | |
2002 | nvme_start_queues(&dev->ctrl); | |
77bf25ea | 2003 | mutex_unlock(&dev->shutdown_lock); |
b60503ba MW |
2004 | } |
2005 | ||
091b6092 MW |
2006 | static int nvme_setup_prp_pools(struct nvme_dev *dev) |
2007 | { | |
e75ec752 | 2008 | dev->prp_page_pool = dma_pool_create("prp list page", dev->dev, |
091b6092 MW |
2009 | PAGE_SIZE, PAGE_SIZE, 0); |
2010 | if (!dev->prp_page_pool) | |
2011 | return -ENOMEM; | |
2012 | ||
99802a7a | 2013 | /* Optimisation for I/Os between 4k and 128k */ |
e75ec752 | 2014 | dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev, |
99802a7a MW |
2015 | 256, 256, 0); |
2016 | if (!dev->prp_small_pool) { | |
2017 | dma_pool_destroy(dev->prp_page_pool); | |
2018 | return -ENOMEM; | |
2019 | } | |
091b6092 MW |
2020 | return 0; |
2021 | } | |
2022 | ||
2023 | static void nvme_release_prp_pools(struct nvme_dev *dev) | |
2024 | { | |
2025 | dma_pool_destroy(dev->prp_page_pool); | |
99802a7a | 2026 | dma_pool_destroy(dev->prp_small_pool); |
091b6092 MW |
2027 | } |
2028 | ||
1673f1f0 | 2029 | static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl) |
5e82e952 | 2030 | { |
1673f1f0 | 2031 | struct nvme_dev *dev = to_nvme_dev(ctrl); |
9ac27090 | 2032 | |
f9f38e33 | 2033 | nvme_dbbuf_dma_free(dev); |
e75ec752 | 2034 | put_device(dev->dev); |
4af0e21c KB |
2035 | if (dev->tagset.tags) |
2036 | blk_mq_free_tag_set(&dev->tagset); | |
1c63dc66 CH |
2037 | if (dev->ctrl.admin_q) |
2038 | blk_put_queue(dev->ctrl.admin_q); | |
5e82e952 | 2039 | kfree(dev->queues); |
e286bcfc | 2040 | free_opal_dev(dev->ctrl.opal_dev); |
5e82e952 KB |
2041 | kfree(dev); |
2042 | } | |
2043 | ||
f58944e2 KB |
2044 | static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status) |
2045 | { | |
237045fc | 2046 | dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status); |
f58944e2 KB |
2047 | |
2048 | kref_get(&dev->ctrl.kref); | |
69d9a99c | 2049 | nvme_dev_disable(dev, false); |
f58944e2 KB |
2050 | if (!schedule_work(&dev->remove_work)) |
2051 | nvme_put_ctrl(&dev->ctrl); | |
2052 | } | |
2053 | ||
fd634f41 | 2054 | static void nvme_reset_work(struct work_struct *work) |
5e82e952 | 2055 | { |
d86c4d8e CH |
2056 | struct nvme_dev *dev = |
2057 | container_of(work, struct nvme_dev, ctrl.reset_work); | |
a98e58e5 | 2058 | bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL); |
f58944e2 | 2059 | int result = -ENODEV; |
5e82e952 | 2060 | |
82b057ca | 2061 | if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING)) |
fd634f41 | 2062 | goto out; |
5e82e952 | 2063 | |
fd634f41 CH |
2064 | /* |
2065 | * If we're called to reset a live controller first shut it down before | |
2066 | * moving on. | |
2067 | */ | |
b00a726a | 2068 | if (dev->ctrl.ctrl_config & NVME_CC_ENABLE) |
a5cdb68c | 2069 | nvme_dev_disable(dev, false); |
5e82e952 | 2070 | |
b00a726a | 2071 | result = nvme_pci_enable(dev); |
f0b50732 | 2072 | if (result) |
3cf519b5 | 2073 | goto out; |
f0b50732 KB |
2074 | |
2075 | result = nvme_configure_admin_queue(dev); | |
2076 | if (result) | |
f58944e2 | 2077 | goto out; |
f0b50732 | 2078 | |
a4aea562 | 2079 | nvme_init_queue(dev->queues[0], 0); |
0fb59cbc KB |
2080 | result = nvme_alloc_admin_tags(dev); |
2081 | if (result) | |
f58944e2 | 2082 | goto out; |
b9afca3e | 2083 | |
ce4541f4 CH |
2084 | result = nvme_init_identify(&dev->ctrl); |
2085 | if (result) | |
f58944e2 | 2086 | goto out; |
ce4541f4 | 2087 | |
e286bcfc SB |
2088 | if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) { |
2089 | if (!dev->ctrl.opal_dev) | |
2090 | dev->ctrl.opal_dev = | |
2091 | init_opal_dev(&dev->ctrl, &nvme_sec_submit); | |
2092 | else if (was_suspend) | |
2093 | opal_unlock_from_suspend(dev->ctrl.opal_dev); | |
2094 | } else { | |
2095 | free_opal_dev(dev->ctrl.opal_dev); | |
2096 | dev->ctrl.opal_dev = NULL; | |
4f1244c8 | 2097 | } |
a98e58e5 | 2098 | |
f9f38e33 HK |
2099 | if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) { |
2100 | result = nvme_dbbuf_dma_alloc(dev); | |
2101 | if (result) | |
2102 | dev_warn(dev->dev, | |
2103 | "unable to allocate dma for dbbuf\n"); | |
2104 | } | |
2105 | ||
87ad72a5 CH |
2106 | if (dev->ctrl.hmpre) |
2107 | nvme_setup_host_mem(dev); | |
2108 | ||
f0b50732 | 2109 | result = nvme_setup_io_queues(dev); |
badc34d4 | 2110 | if (result) |
f58944e2 | 2111 | goto out; |
f0b50732 | 2112 | |
21f033f7 KB |
2113 | /* |
2114 | * A controller that can not execute IO typically requires user | |
2115 | * intervention to correct. For such degraded controllers, the driver | |
2116 | * should not submit commands the user did not request, so skip | |
2117 | * registering for asynchronous event notification on this condition. | |
2118 | */ | |
f866fc42 CH |
2119 | if (dev->online_queues > 1) |
2120 | nvme_queue_async_events(&dev->ctrl); | |
3cf519b5 | 2121 | |
2659e57b CH |
2122 | /* |
2123 | * Keep the controller around but remove all namespaces if we don't have | |
2124 | * any working I/O queue. | |
2125 | */ | |
3cf519b5 | 2126 | if (dev->online_queues < 2) { |
1b3c47c1 | 2127 | dev_warn(dev->ctrl.device, "IO queues not created\n"); |
3b24774e | 2128 | nvme_kill_queues(&dev->ctrl); |
5bae7f73 | 2129 | nvme_remove_namespaces(&dev->ctrl); |
3cf519b5 | 2130 | } else { |
25646264 | 2131 | nvme_start_queues(&dev->ctrl); |
302ad8cc | 2132 | nvme_wait_freeze(&dev->ctrl); |
3cf519b5 | 2133 | nvme_dev_add(dev); |
302ad8cc | 2134 | nvme_unfreeze(&dev->ctrl); |
3cf519b5 CH |
2135 | } |
2136 | ||
bb8d261e CH |
2137 | if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) { |
2138 | dev_warn(dev->ctrl.device, "failed to mark controller live\n"); | |
2139 | goto out; | |
2140 | } | |
92911a55 CH |
2141 | |
2142 | if (dev->online_queues > 1) | |
5955be21 | 2143 | nvme_queue_scan(&dev->ctrl); |
3cf519b5 | 2144 | return; |
f0b50732 | 2145 | |
3cf519b5 | 2146 | out: |
f58944e2 | 2147 | nvme_remove_dead_ctrl(dev, result); |
f0b50732 KB |
2148 | } |
2149 | ||
5c8809e6 | 2150 | static void nvme_remove_dead_ctrl_work(struct work_struct *work) |
9a6b9458 | 2151 | { |
5c8809e6 | 2152 | struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work); |
e75ec752 | 2153 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
9a6b9458 | 2154 | |
69d9a99c | 2155 | nvme_kill_queues(&dev->ctrl); |
9a6b9458 | 2156 | if (pci_get_drvdata(pdev)) |
921920ab | 2157 | device_release_driver(&pdev->dev); |
1673f1f0 | 2158 | nvme_put_ctrl(&dev->ctrl); |
9a6b9458 KB |
2159 | } |
2160 | ||
1c63dc66 | 2161 | static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val) |
9ca97374 | 2162 | { |
1c63dc66 | 2163 | *val = readl(to_nvme_dev(ctrl)->bar + off); |
90667892 | 2164 | return 0; |
9ca97374 TH |
2165 | } |
2166 | ||
5fd4ce1b | 2167 | static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val) |
4cc06521 | 2168 | { |
5fd4ce1b CH |
2169 | writel(val, to_nvme_dev(ctrl)->bar + off); |
2170 | return 0; | |
2171 | } | |
4cc06521 | 2172 | |
7fd8930f CH |
2173 | static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val) |
2174 | { | |
2175 | *val = readq(to_nvme_dev(ctrl)->bar + off); | |
2176 | return 0; | |
4cc06521 KB |
2177 | } |
2178 | ||
1c63dc66 | 2179 | static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = { |
1a353d85 | 2180 | .name = "pcie", |
e439bb12 | 2181 | .module = THIS_MODULE, |
c81bfba9 | 2182 | .flags = NVME_F_METADATA_SUPPORTED, |
1c63dc66 | 2183 | .reg_read32 = nvme_pci_reg_read32, |
5fd4ce1b | 2184 | .reg_write32 = nvme_pci_reg_write32, |
7fd8930f | 2185 | .reg_read64 = nvme_pci_reg_read64, |
1673f1f0 | 2186 | .free_ctrl = nvme_pci_free_ctrl, |
f866fc42 | 2187 | .submit_async_event = nvme_pci_submit_async_event, |
1c63dc66 | 2188 | }; |
4cc06521 | 2189 | |
b00a726a KB |
2190 | static int nvme_dev_map(struct nvme_dev *dev) |
2191 | { | |
b00a726a KB |
2192 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
2193 | ||
a1f447b3 | 2194 | if (pci_request_mem_regions(pdev, "nvme")) |
b00a726a KB |
2195 | return -ENODEV; |
2196 | ||
97f6ef64 | 2197 | if (nvme_remap_bar(dev, NVME_REG_DBS + 4096)) |
b00a726a KB |
2198 | goto release; |
2199 | ||
9fa196e7 | 2200 | return 0; |
b00a726a | 2201 | release: |
9fa196e7 MG |
2202 | pci_release_mem_regions(pdev); |
2203 | return -ENODEV; | |
b00a726a KB |
2204 | } |
2205 | ||
ff5350a8 AL |
2206 | static unsigned long check_dell_samsung_bug(struct pci_dev *pdev) |
2207 | { | |
2208 | if (pdev->vendor == 0x144d && pdev->device == 0xa802) { | |
2209 | /* | |
2210 | * Several Samsung devices seem to drop off the PCIe bus | |
2211 | * randomly when APST is on and uses the deepest sleep state. | |
2212 | * This has been observed on a Samsung "SM951 NVMe SAMSUNG | |
2213 | * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD | |
2214 | * 950 PRO 256GB", but it seems to be restricted to two Dell | |
2215 | * laptops. | |
2216 | */ | |
2217 | if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") && | |
2218 | (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") || | |
2219 | dmi_match(DMI_PRODUCT_NAME, "Precision 5510"))) | |
2220 | return NVME_QUIRK_NO_DEEPEST_PS; | |
2221 | } | |
2222 | ||
2223 | return 0; | |
2224 | } | |
2225 | ||
8d85fce7 | 2226 | static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) |
b60503ba | 2227 | { |
a4aea562 | 2228 | int node, result = -ENOMEM; |
b60503ba | 2229 | struct nvme_dev *dev; |
ff5350a8 | 2230 | unsigned long quirks = id->driver_data; |
b60503ba | 2231 | |
a4aea562 MB |
2232 | node = dev_to_node(&pdev->dev); |
2233 | if (node == NUMA_NO_NODE) | |
2fa84351 | 2234 | set_dev_node(&pdev->dev, first_memory_node); |
a4aea562 MB |
2235 | |
2236 | dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); | |
b60503ba MW |
2237 | if (!dev) |
2238 | return -ENOMEM; | |
a4aea562 MB |
2239 | dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *), |
2240 | GFP_KERNEL, node); | |
b60503ba MW |
2241 | if (!dev->queues) |
2242 | goto free; | |
2243 | ||
e75ec752 | 2244 | dev->dev = get_device(&pdev->dev); |
9a6b9458 | 2245 | pci_set_drvdata(pdev, dev); |
1c63dc66 | 2246 | |
b00a726a KB |
2247 | result = nvme_dev_map(dev); |
2248 | if (result) | |
2249 | goto free; | |
2250 | ||
d86c4d8e | 2251 | INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work); |
5c8809e6 | 2252 | INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work); |
77bf25ea | 2253 | mutex_init(&dev->shutdown_lock); |
db3cbfff | 2254 | init_completion(&dev->ioq_wait); |
b60503ba | 2255 | |
091b6092 MW |
2256 | result = nvme_setup_prp_pools(dev); |
2257 | if (result) | |
a96d4f5c | 2258 | goto put_pci; |
4cc06521 | 2259 | |
ff5350a8 AL |
2260 | quirks |= check_dell_samsung_bug(pdev); |
2261 | ||
f3ca80fc | 2262 | result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops, |
ff5350a8 | 2263 | quirks); |
4cc06521 | 2264 | if (result) |
2e1d8448 | 2265 | goto release_pools; |
740216fc | 2266 | |
82b057ca | 2267 | nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_RESETTING); |
1b3c47c1 SG |
2268 | dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev)); |
2269 | ||
d86c4d8e | 2270 | queue_work(nvme_wq, &dev->ctrl.reset_work); |
b60503ba MW |
2271 | return 0; |
2272 | ||
0877cb0d | 2273 | release_pools: |
091b6092 | 2274 | nvme_release_prp_pools(dev); |
a96d4f5c | 2275 | put_pci: |
e75ec752 | 2276 | put_device(dev->dev); |
b00a726a | 2277 | nvme_dev_unmap(dev); |
b60503ba MW |
2278 | free: |
2279 | kfree(dev->queues); | |
b60503ba MW |
2280 | kfree(dev); |
2281 | return result; | |
2282 | } | |
2283 | ||
f0d54a54 KB |
2284 | static void nvme_reset_notify(struct pci_dev *pdev, bool prepare) |
2285 | { | |
a6739479 | 2286 | struct nvme_dev *dev = pci_get_drvdata(pdev); |
f0d54a54 | 2287 | |
a6739479 | 2288 | if (prepare) |
a5cdb68c | 2289 | nvme_dev_disable(dev, false); |
a6739479 | 2290 | else |
d86c4d8e | 2291 | nvme_reset_ctrl(&dev->ctrl); |
f0d54a54 KB |
2292 | } |
2293 | ||
09ece142 KB |
2294 | static void nvme_shutdown(struct pci_dev *pdev) |
2295 | { | |
2296 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
a5cdb68c | 2297 | nvme_dev_disable(dev, true); |
09ece142 KB |
2298 | } |
2299 | ||
f58944e2 KB |
2300 | /* |
2301 | * The driver's remove may be called on a device in a partially initialized | |
2302 | * state. This function must not have any dependencies on the device state in | |
2303 | * order to proceed. | |
2304 | */ | |
8d85fce7 | 2305 | static void nvme_remove(struct pci_dev *pdev) |
b60503ba MW |
2306 | { |
2307 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
9a6b9458 | 2308 | |
bb8d261e CH |
2309 | nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); |
2310 | ||
d86c4d8e | 2311 | cancel_work_sync(&dev->ctrl.reset_work); |
9a6b9458 | 2312 | pci_set_drvdata(pdev, NULL); |
0ff9d4e1 | 2313 | |
6db28eda | 2314 | if (!pci_device_is_present(pdev)) { |
0ff9d4e1 | 2315 | nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD); |
6db28eda KB |
2316 | nvme_dev_disable(dev, false); |
2317 | } | |
0ff9d4e1 | 2318 | |
d86c4d8e | 2319 | flush_work(&dev->ctrl.reset_work); |
53029b04 | 2320 | nvme_uninit_ctrl(&dev->ctrl); |
a5cdb68c | 2321 | nvme_dev_disable(dev, true); |
87ad72a5 | 2322 | nvme_free_host_mem(dev); |
a4aea562 | 2323 | nvme_dev_remove_admin(dev); |
a1a5ef99 | 2324 | nvme_free_queues(dev, 0); |
9a6b9458 | 2325 | nvme_release_prp_pools(dev); |
b00a726a | 2326 | nvme_dev_unmap(dev); |
1673f1f0 | 2327 | nvme_put_ctrl(&dev->ctrl); |
b60503ba MW |
2328 | } |
2329 | ||
13880f5b KB |
2330 | static int nvme_pci_sriov_configure(struct pci_dev *pdev, int numvfs) |
2331 | { | |
2332 | int ret = 0; | |
2333 | ||
2334 | if (numvfs == 0) { | |
2335 | if (pci_vfs_assigned(pdev)) { | |
2336 | dev_warn(&pdev->dev, | |
2337 | "Cannot disable SR-IOV VFs while assigned\n"); | |
2338 | return -EPERM; | |
2339 | } | |
2340 | pci_disable_sriov(pdev); | |
2341 | return 0; | |
2342 | } | |
2343 | ||
2344 | ret = pci_enable_sriov(pdev, numvfs); | |
2345 | return ret ? ret : numvfs; | |
2346 | } | |
2347 | ||
671a6018 | 2348 | #ifdef CONFIG_PM_SLEEP |
cd638946 KB |
2349 | static int nvme_suspend(struct device *dev) |
2350 | { | |
2351 | struct pci_dev *pdev = to_pci_dev(dev); | |
2352 | struct nvme_dev *ndev = pci_get_drvdata(pdev); | |
2353 | ||
a5cdb68c | 2354 | nvme_dev_disable(ndev, true); |
cd638946 KB |
2355 | return 0; |
2356 | } | |
2357 | ||
2358 | static int nvme_resume(struct device *dev) | |
2359 | { | |
2360 | struct pci_dev *pdev = to_pci_dev(dev); | |
2361 | struct nvme_dev *ndev = pci_get_drvdata(pdev); | |
cd638946 | 2362 | |
d86c4d8e | 2363 | nvme_reset_ctrl(&ndev->ctrl); |
9a6b9458 | 2364 | return 0; |
cd638946 | 2365 | } |
671a6018 | 2366 | #endif |
cd638946 KB |
2367 | |
2368 | static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume); | |
b60503ba | 2369 | |
a0a3408e KB |
2370 | static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev, |
2371 | pci_channel_state_t state) | |
2372 | { | |
2373 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
2374 | ||
2375 | /* | |
2376 | * A frozen channel requires a reset. When detected, this method will | |
2377 | * shutdown the controller to quiesce. The controller will be restarted | |
2378 | * after the slot reset through driver's slot_reset callback. | |
2379 | */ | |
a0a3408e KB |
2380 | switch (state) { |
2381 | case pci_channel_io_normal: | |
2382 | return PCI_ERS_RESULT_CAN_RECOVER; | |
2383 | case pci_channel_io_frozen: | |
d011fb31 KB |
2384 | dev_warn(dev->ctrl.device, |
2385 | "frozen state error detected, reset controller\n"); | |
a5cdb68c | 2386 | nvme_dev_disable(dev, false); |
a0a3408e KB |
2387 | return PCI_ERS_RESULT_NEED_RESET; |
2388 | case pci_channel_io_perm_failure: | |
d011fb31 KB |
2389 | dev_warn(dev->ctrl.device, |
2390 | "failure state error detected, request disconnect\n"); | |
a0a3408e KB |
2391 | return PCI_ERS_RESULT_DISCONNECT; |
2392 | } | |
2393 | return PCI_ERS_RESULT_NEED_RESET; | |
2394 | } | |
2395 | ||
2396 | static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev) | |
2397 | { | |
2398 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
2399 | ||
1b3c47c1 | 2400 | dev_info(dev->ctrl.device, "restart after slot reset\n"); |
a0a3408e | 2401 | pci_restore_state(pdev); |
d86c4d8e | 2402 | nvme_reset_ctrl(&dev->ctrl); |
a0a3408e KB |
2403 | return PCI_ERS_RESULT_RECOVERED; |
2404 | } | |
2405 | ||
2406 | static void nvme_error_resume(struct pci_dev *pdev) | |
2407 | { | |
2408 | pci_cleanup_aer_uncorrect_error_status(pdev); | |
2409 | } | |
2410 | ||
1d352035 | 2411 | static const struct pci_error_handlers nvme_err_handler = { |
b60503ba | 2412 | .error_detected = nvme_error_detected, |
b60503ba MW |
2413 | .slot_reset = nvme_slot_reset, |
2414 | .resume = nvme_error_resume, | |
f0d54a54 | 2415 | .reset_notify = nvme_reset_notify, |
b60503ba MW |
2416 | }; |
2417 | ||
6eb0d698 | 2418 | static const struct pci_device_id nvme_id_table[] = { |
106198ed | 2419 | { PCI_VDEVICE(INTEL, 0x0953), |
08095e70 | 2420 | .driver_data = NVME_QUIRK_STRIPE_SIZE | |
e850fd16 | 2421 | NVME_QUIRK_DEALLOCATE_ZEROES, }, |
99466e70 KB |
2422 | { PCI_VDEVICE(INTEL, 0x0a53), |
2423 | .driver_data = NVME_QUIRK_STRIPE_SIZE | | |
e850fd16 | 2424 | NVME_QUIRK_DEALLOCATE_ZEROES, }, |
99466e70 KB |
2425 | { PCI_VDEVICE(INTEL, 0x0a54), |
2426 | .driver_data = NVME_QUIRK_STRIPE_SIZE | | |
e850fd16 | 2427 | NVME_QUIRK_DEALLOCATE_ZEROES, }, |
50af47d0 AL |
2428 | { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */ |
2429 | .driver_data = NVME_QUIRK_NO_DEEPEST_PS }, | |
540c801c KB |
2430 | { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */ |
2431 | .driver_data = NVME_QUIRK_IDENTIFY_CNS, }, | |
54adc010 GP |
2432 | { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */ |
2433 | .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, | |
015282c9 WW |
2434 | { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */ |
2435 | .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, | |
b60503ba | 2436 | { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, |
c74dc780 | 2437 | { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) }, |
124298bd | 2438 | { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) }, |
b60503ba MW |
2439 | { 0, } |
2440 | }; | |
2441 | MODULE_DEVICE_TABLE(pci, nvme_id_table); | |
2442 | ||
2443 | static struct pci_driver nvme_driver = { | |
2444 | .name = "nvme", | |
2445 | .id_table = nvme_id_table, | |
2446 | .probe = nvme_probe, | |
8d85fce7 | 2447 | .remove = nvme_remove, |
09ece142 | 2448 | .shutdown = nvme_shutdown, |
cd638946 KB |
2449 | .driver = { |
2450 | .pm = &nvme_dev_pm_ops, | |
2451 | }, | |
13880f5b | 2452 | .sriov_configure = nvme_pci_sriov_configure, |
b60503ba MW |
2453 | .err_handler = &nvme_err_handler, |
2454 | }; | |
2455 | ||
2456 | static int __init nvme_init(void) | |
2457 | { | |
9a6327d2 | 2458 | return pci_register_driver(&nvme_driver); |
b60503ba MW |
2459 | } |
2460 | ||
2461 | static void __exit nvme_exit(void) | |
2462 | { | |
2463 | pci_unregister_driver(&nvme_driver); | |
21bd78bc | 2464 | _nvme_check_size(); |
b60503ba MW |
2465 | } |
2466 | ||
2467 | MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); | |
2468 | MODULE_LICENSE("GPL"); | |
c78b4713 | 2469 | MODULE_VERSION("1.0"); |
b60503ba MW |
2470 | module_init(nvme_init); |
2471 | module_exit(nvme_exit); |