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block: don't clear REQ_ALLOC_CACHE for non-polled requests
[linux-2.6-block.git] / drivers / nvme / host / pci.c
CommitLineData
5f37396d 1// SPDX-License-Identifier: GPL-2.0
b60503ba
MW		 2/*
3 * NVM Express device driver
6eb0d698 4 * Copyright (c) 2011-2014, Intel Corporation.
b60503ba
MW		 5 */
6
df4f9bc4 7#include <linux/acpi.h>
a0a3408e 8#include <linux/aer.h>
18119775 9#include <linux/async.h>
b60503ba 10#include <linux/blkdev.h>
a4aea562 11#include <linux/blk-mq.h>
dca51e78 12#include <linux/blk-mq-pci.h>
fe45e630 13#include <linux/blk-integrity.h>
ff5350a8 14#include <linux/dmi.h>
b60503ba
MW		 15#include <linux/init.h>
16#include <linux/interrupt.h>
17#include <linux/io.h>
99722c8a 18#include <linux/kstrtox.h>
dc90f084 19#include <linux/memremap.h>
b60503ba
MW		 20#include <linux/mm.h>
21#include <linux/module.h>
77bf25ea 22#include <linux/mutex.h>
d0877473 23#include <linux/once.h>
b60503ba 24#include <linux/pci.h>
d916b1be 25#include <linux/suspend.h>
e1e5e564 26#include <linux/t10-pi.h>
b60503ba 27#include <linux/types.h>
2f8e2c87 28#include <linux/io-64-nonatomic-lo-hi.h>
20d3bb92 29#include <linux/io-64-nonatomic-hi-lo.h>
a98e58e5 30#include <linux/sed-opal.h>
0f238ff5 31#include <linux/pci-p2pdma.h>
797a796a 32
604c01d5 33#include "trace.h"
f11bb3e2
CH		 34#include "nvme.h"
35
c1e0cc7e 36#define SQ_SIZE(q) ((q)->q_depth << (q)->sqes)
8a1d09a6 37#define CQ_SIZE(q) ((q)->q_depth * sizeof(struct nvme_completion))
c965809c 38
a7a7cbe3 39#define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc))
9d43cf64 40
943e942e
JA		 41/*
42 * These can be higher, but we need to ensure that any command doesn't
43 * require an sg allocation that needs more than a page of data.
44 */
45#define NVME_MAX_KB_SZ 4096
46#define NVME_MAX_SEGS 127
47
58ffacb5 48static int use_threaded_interrupts;
2e21e445 49module_param(use_threaded_interrupts, int, 0444);
58ffacb5 50
8ffaadf7 51static bool use_cmb_sqes = true;
69f4eb9f 52module_param(use_cmb_sqes, bool, 0444);
8ffaadf7
JD		 53MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
54
87ad72a5
CH		 55static unsigned int max_host_mem_size_mb = 128;
56module_param(max_host_mem_size_mb, uint, 0444);
57MODULE_PARM_DESC(max_host_mem_size_mb,
58 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
1fa6aead 59
a7a7cbe3
CK		 60static unsigned int sgl_threshold = SZ_32K;
61module_param(sgl_threshold, uint, 0644);
62MODULE_PARM_DESC(sgl_threshold,
63 "Use SGLs when average request segment size is larger or equal to "
64 "this size. Use 0 to disable SGLs.");
65
27453b45
SG		 66#define NVME_PCI_MIN_QUEUE_SIZE 2
67#define NVME_PCI_MAX_QUEUE_SIZE 4095
b27c1e68 68static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
69static const struct kernel_param_ops io_queue_depth_ops = {
70 .set = io_queue_depth_set,
61f3b896 71 .get = param_get_uint,
b27c1e68 72};
73
61f3b896 74static unsigned int io_queue_depth = 1024;
b27c1e68 75module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
27453b45 76MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2 and < 4096");
b27c1e68 77
9c9e76d5
WZ		 78static int io_queue_count_set(const char *val, const struct kernel_param *kp)
79{
80 unsigned int n;
81 int ret;
82
83 ret = kstrtouint(val, 10, &n);
84 if (ret != 0 || n > num_possible_cpus())
85 return -EINVAL;
86 return param_set_uint(val, kp);
87}
88
89static const struct kernel_param_ops io_queue_count_ops = {
90 .set = io_queue_count_set,
91 .get = param_get_uint,
92};
93
3f68baf7 94static unsigned int write_queues;
9c9e76d5 95module_param_cb(write_queues, &io_queue_count_ops, &write_queues, 0644);
3b6592f7
JA		 96MODULE_PARM_DESC(write_queues,
97 "Number of queues to use for writes. If not set, reads and writes "
98 "will share a queue set.");
99
3f68baf7 100static unsigned int poll_queues;
9c9e76d5 101module_param_cb(poll_queues, &io_queue_count_ops, &poll_queues, 0644);
4b04cc6a
JA		 102MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO.");
103
df4f9bc4
DB		 104static bool noacpi;
105module_param(noacpi, bool, 0444);
106MODULE_PARM_DESC(noacpi, "disable acpi bios quirks");
107
1c63dc66
CH		 108struct nvme_dev;
109struct nvme_queue;
b3fffdef 110
a5cdb68c 111static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
7d879c90 112static void nvme_delete_io_queues(struct nvme_dev *dev);
d4b4ff8e 113
1c63dc66
CH		 114/*
115 * Represents an NVM Express device. Each nvme_dev is a PCI function.
116 */
117struct nvme_dev {
147b27e4 118 struct nvme_queue *queues;
1c63dc66
CH		 119 struct blk_mq_tag_set tagset;
120 struct blk_mq_tag_set admin_tagset;
121 u32 __iomem *dbs;
122 struct device *dev;
123 struct dma_pool *prp_page_pool;
124 struct dma_pool *prp_small_pool;
1c63dc66
CH		 125 unsigned online_queues;
126 unsigned max_qid;
e20ba6e1 127 unsigned io_queues[HCTX_MAX_TYPES];
22b55601 128 unsigned int num_vecs;
7442ddce 129 u32 q_depth;
c1e0cc7e 130 int io_sqes;
1c63dc66 131 u32 db_stride;
1c63dc66 132 void __iomem *bar;
97f6ef64 133 unsigned long bar_mapped_size;
77bf25ea 134 struct mutex shutdown_lock;
1c63dc66 135 bool subsystem;
1c63dc66 136 u64 cmb_size;
0f238ff5 137 bool cmb_use_sqes;
1c63dc66 138 u32 cmbsz;
202021c1 139 u32 cmbloc;
1c63dc66 140 struct nvme_ctrl ctrl;
d916b1be 141 u32 last_ps;
a5df5e79 142 bool hmb;
87ad72a5 143
943e942e
JA		 144 mempool_t *iod_mempool;
145
87ad72a5 146 /* shadow doorbell buffer support: */
f9f38e33
HK		 147 u32 *dbbuf_dbs;
148 dma_addr_t dbbuf_dbs_dma_addr;
149 u32 *dbbuf_eis;
150 dma_addr_t dbbuf_eis_dma_addr;
87ad72a5
CH		 151
152 /* host memory buffer support: */
153 u64 host_mem_size;
154 u32 nr_host_mem_descs;
4033f35d 155 dma_addr_t host_mem_descs_dma;
87ad72a5
CH		 156 struct nvme_host_mem_buf_desc *host_mem_descs;
157 void **host_mem_desc_bufs;
2a5bcfdd
WZ		 158 unsigned int nr_allocated_queues;
159 unsigned int nr_write_queues;
160 unsigned int nr_poll_queues;
4d115420 161};
1fa6aead 162
b27c1e68 163static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
164{
27453b45
SG		 165 return param_set_uint_minmax(val, kp, NVME_PCI_MIN_QUEUE_SIZE,
166 NVME_PCI_MAX_QUEUE_SIZE);
b27c1e68 167}
168
f9f38e33
HK		 169static inline unsigned int sq_idx(unsigned int qid, u32 stride)
170{
171 return qid * 2 * stride;
172}
173
174static inline unsigned int cq_idx(unsigned int qid, u32 stride)
175{
176 return (qid * 2 + 1) * stride;
177}
178
1c63dc66
CH		 179static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
180{
181 return container_of(ctrl, struct nvme_dev, ctrl);
182}
183
b60503ba
MW		 184/*
185 * An NVM Express queue. Each device has at least two (one for admin
186 * commands and one for I/O commands).
187 */
188struct nvme_queue {
091b6092 189 struct nvme_dev *dev;
1ab0cd69 190 spinlock_t sq_lock;
c1e0cc7e 191 void *sq_cmds;
3a7afd8e
CH		 192 /* only used for poll queues: */
193 spinlock_t cq_poll_lock ____cacheline_aligned_in_smp;
74943d45 194 struct nvme_completion *cqes;
b60503ba
MW		 195 dma_addr_t sq_dma_addr;
196 dma_addr_t cq_dma_addr;
b60503ba 197 u32 __iomem *q_db;
7442ddce 198 u32 q_depth;
7c349dde 199 u16 cq_vector;
b60503ba 200 u16 sq_tail;
38210800 201 u16 last_sq_tail;
b60503ba 202 u16 cq_head;
c30341dc 203 u16 qid;
e9539f47 204 u8 cq_phase;
c1e0cc7e 205 u8 sqes;
4e224106
CH		 206 unsigned long flags;
207#define NVMEQ_ENABLED 0
63223078 208#define NVMEQ_SQ_CMB 1
d1ed6aa1 209#define NVMEQ_DELETE_ERROR 2
7c349dde 210#define NVMEQ_POLLED 3
f9f38e33
HK		 211 u32 *dbbuf_sq_db;
212 u32 *dbbuf_cq_db;
213 u32 *dbbuf_sq_ei;
214 u32 *dbbuf_cq_ei;
d1ed6aa1 215 struct completion delete_done;
b60503ba
MW		 216};
217
71bd150c 218/*
9b048119
CH		 219 * The nvme_iod describes the data in an I/O.
220 *
221 * The sg pointer contains the list of PRP/SGL chunk allocations in addition
222 * to the actual struct scatterlist.
71bd150c
CH		 223 */
224struct nvme_iod {
d49187e9 225 struct nvme_request req;
af7fae85 226 struct nvme_command cmd;
a7a7cbe3 227 bool use_sgl;
52da4f3f 228 bool aborted;
c372cdd1
KB		 229 s8 nr_allocations; /* PRP list pool allocations. 0 means small
230 pool in use */
dff824b2 231 unsigned int dma_len; /* length of single DMA segment mapping */
c4c22c52 232 dma_addr_t first_dma;
783b94bd 233 dma_addr_t meta_dma;
91fb2b60 234 struct sg_table sgt;
b60503ba
MW		 235};
236
2a5bcfdd 237static inline unsigned int nvme_dbbuf_size(struct nvme_dev *dev)
3b6592f7 238{
2a5bcfdd 239 return dev->nr_allocated_queues * 8 * dev->db_stride;
f9f38e33
HK		 240}
241
65a54646 242static void nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
f9f38e33 243{
2a5bcfdd 244 unsigned int mem_size = nvme_dbbuf_size(dev);
f9f38e33 245
65a54646
CH		 246 if (!(dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP))
247 return;
248
58847f12
KB		 249 if (dev->dbbuf_dbs) {
250 /*
251 * Clear the dbbuf memory so the driver doesn't observe stale
252 * values from the previous instantiation.
253 */
254 memset(dev->dbbuf_dbs, 0, mem_size);
255 memset(dev->dbbuf_eis, 0, mem_size);
65a54646 256 return;
58847f12 257 }
f9f38e33
HK		 258
259 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
260 &dev->dbbuf_dbs_dma_addr,
261 GFP_KERNEL);
262 if (!dev->dbbuf_dbs)
65a54646 263 goto fail;
f9f38e33
HK		 264 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
265 &dev->dbbuf_eis_dma_addr,
266 GFP_KERNEL);
65a54646
CH		 267 if (!dev->dbbuf_eis)
268 goto fail_free_dbbuf_dbs;
269 return;
f9f38e33 270
65a54646
CH		 271fail_free_dbbuf_dbs:
272 dma_free_coherent(dev->dev, mem_size, dev->dbbuf_dbs,
273 dev->dbbuf_dbs_dma_addr);
274 dev->dbbuf_dbs = NULL;
275fail:
276 dev_warn(dev->dev, "unable to allocate dma for dbbuf\n");
f9f38e33
HK		 277}
278
279static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
280{
2a5bcfdd 281 unsigned int mem_size = nvme_dbbuf_size(dev);
f9f38e33
HK		 282
283 if (dev->dbbuf_dbs) {
284 dma_free_coherent(dev->dev, mem_size,
285 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
286 dev->dbbuf_dbs = NULL;
287 }
288 if (dev->dbbuf_eis) {
289 dma_free_coherent(dev->dev, mem_size,
290 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
291 dev->dbbuf_eis = NULL;
292 }
293}
294
295static void nvme_dbbuf_init(struct nvme_dev *dev,
296 struct nvme_queue *nvmeq, int qid)
297{
298 if (!dev->dbbuf_dbs || !qid)
299 return;
300
301 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
302 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
303 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
304 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
305}
306
0f0d2c87
MI		 307static void nvme_dbbuf_free(struct nvme_queue *nvmeq)
308{
309 if (!nvmeq->qid)
310 return;
311
312 nvmeq->dbbuf_sq_db = NULL;
313 nvmeq->dbbuf_cq_db = NULL;
314 nvmeq->dbbuf_sq_ei = NULL;
315 nvmeq->dbbuf_cq_ei = NULL;
316}
317
f9f38e33
HK		 318static void nvme_dbbuf_set(struct nvme_dev *dev)
319{
f66e2804 320 struct nvme_command c = { };
0f0d2c87 321 unsigned int i;
f9f38e33
HK		 322
323 if (!dev->dbbuf_dbs)
324 return;
325
f9f38e33
HK		 326 c.dbbuf.opcode = nvme_admin_dbbuf;
327 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
328 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
329
330 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
9bdcfb10 331 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
f9f38e33
HK		 332 /* Free memory and continue on */
333 nvme_dbbuf_dma_free(dev);
0f0d2c87
MI		 334
335 for (i = 1; i <= dev->online_queues; i++)
336 nvme_dbbuf_free(&dev->queues[i]);
f9f38e33
HK		 337 }
338}
339
340static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
341{
342 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
343}
344
345/* Update dbbuf and return true if an MMIO is required */
346static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
347 volatile u32 *dbbuf_ei)
348{
349 if (dbbuf_db) {
350 u16 old_value;
351
352 /*
353 * Ensure that the queue is written before updating
354 * the doorbell in memory
355 */
356 wmb();
357
358 old_value = *dbbuf_db;
359 *dbbuf_db = value;
360
f1ed3df2
MW		 361 /*
362 * Ensure that the doorbell is updated before reading the event
363 * index from memory. The controller needs to provide similar
364 * ordering to ensure the envent index is updated before reading
365 * the doorbell.
366 */
367 mb();
368
f9f38e33
HK		 369 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value))
370 return false;
371 }
372
373 return true;
b60503ba
MW		 374}
375
ac3dd5bd
JA		 376/*
377 * Will slightly overestimate the number of pages needed. This is OK
378 * as it only leads to a small amount of wasted memory for the lifetime of
379 * the I/O.
380 */
b13c6393 381static int nvme_pci_npages_prp(void)
ac3dd5bd 382{
b13c6393 383 unsigned nprps = DIV_ROUND_UP(NVME_MAX_KB_SZ + NVME_CTRL_PAGE_SIZE,
6c3c05b0 384 NVME_CTRL_PAGE_SIZE);
ac3dd5bd
JA		 385 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
386}
387
a7a7cbe3
CK		 388/*
389 * Calculates the number of pages needed for the SGL segments. For example a 4k
390 * page can accommodate 256 SGL descriptors.
391 */
b13c6393 392static int nvme_pci_npages_sgl(void)
ac3dd5bd 393{
b13c6393
CK		 394 return DIV_ROUND_UP(NVME_MAX_SEGS * sizeof(struct nvme_sgl_desc),
395 PAGE_SIZE);
f4800d6d 396}
ac3dd5bd 397
a4aea562
MB		 398static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
399 unsigned int hctx_idx)
e85248e5 400{
0da7feaa 401 struct nvme_dev *dev = to_nvme_dev(data);
147b27e4 402 struct nvme_queue *nvmeq = &dev->queues[0];
a4aea562 403
42483228
KB		 404 WARN_ON(hctx_idx != 0);
405 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
42483228 406
a4aea562
MB		 407 hctx->driver_data = nvmeq;
408 return 0;
e85248e5
MW		 409}
410
a4aea562
MB		 411static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
412 unsigned int hctx_idx)
b60503ba 413{
0da7feaa 414 struct nvme_dev *dev = to_nvme_dev(data);
147b27e4 415 struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
a4aea562 416
42483228 417 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
a4aea562
MB		 418 hctx->driver_data = nvmeq;
419 return 0;
b60503ba
MW		 420}
421
e559398f
CH		 422static int nvme_pci_init_request(struct blk_mq_tag_set *set,
423 struct request *req, unsigned int hctx_idx,
424 unsigned int numa_node)
b60503ba 425{
0da7feaa 426 struct nvme_dev *dev = to_nvme_dev(set->driver_data);
f4800d6d 427 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
59e29ce6
SG		 428
429 nvme_req(req)->ctrl = &dev->ctrl;
f4b9e6c9 430 nvme_req(req)->cmd = &iod->cmd;
a4aea562
MB		 431 return 0;
432}
433
3b6592f7
JA		 434static int queue_irq_offset(struct nvme_dev *dev)
435{
436 /* if we have more than 1 vec, admin queue offsets us by 1 */
437 if (dev->num_vecs > 1)
438 return 1;
439
440 return 0;
441}
442
a4e1d0b7 443static void nvme_pci_map_queues(struct blk_mq_tag_set *set)
dca51e78 444{
0da7feaa 445 struct nvme_dev *dev = to_nvme_dev(set->driver_data);
3b6592f7
JA		 446 int i, qoff, offset;
447
448 offset = queue_irq_offset(dev);
449 for (i = 0, qoff = 0; i < set->nr_maps; i++) {
450 struct blk_mq_queue_map *map = &set->map[i];
451
452 map->nr_queues = dev->io_queues[i];
453 if (!map->nr_queues) {
e20ba6e1 454 BUG_ON(i == HCTX_TYPE_DEFAULT);
7e849dd9 455 continue;
3b6592f7
JA		 456 }
457
4b04cc6a
JA		 458 /*
459 * The poll queue(s) doesn't have an IRQ (and hence IRQ
460 * affinity), so use the regular blk-mq cpu mapping
461 */
3b6592f7 462 map->queue_offset = qoff;
cb9e0e50 463 if (i != HCTX_TYPE_POLL && offset)
4b04cc6a
JA		 464 blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset);
465 else
466 blk_mq_map_queues(map);
3b6592f7
JA		 467 qoff += map->nr_queues;
468 offset += map->nr_queues;
469 }
dca51e78
CH		 470}
471
38210800
KB		 472/*
473 * Write sq tail if we are asked to, or if the next command would wrap.
474 */
475static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq)
04f3eafd 476{
38210800
KB		 477 if (!write_sq) {
478 u16 next_tail = nvmeq->sq_tail + 1;
479
480 if (next_tail == nvmeq->q_depth)
481 next_tail = 0;
482 if (next_tail != nvmeq->last_sq_tail)
483 return;
484 }
485
04f3eafd
JA		 486 if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail,
487 nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei))
488 writel(nvmeq->sq_tail, nvmeq->q_db);
38210800 489 nvmeq->last_sq_tail = nvmeq->sq_tail;
04f3eafd
JA		 490}
491
3233b94c
JA		 492static inline void nvme_sq_copy_cmd(struct nvme_queue *nvmeq,
493 struct nvme_command *cmd)
b60503ba 494{
c1e0cc7e 495 memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes),
3233b94c 496 absolute_pointer(cmd), sizeof(*cmd));
90ea5ca4
CH		 497 if (++nvmeq->sq_tail == nvmeq->q_depth)
498 nvmeq->sq_tail = 0;
04f3eafd
JA		 499}
500
501static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx)
502{
503 struct nvme_queue *nvmeq = hctx->driver_data;
504
505 spin_lock(&nvmeq->sq_lock);
38210800
KB		 506 if (nvmeq->sq_tail != nvmeq->last_sq_tail)
507 nvme_write_sq_db(nvmeq, true);
90ea5ca4 508 spin_unlock(&nvmeq->sq_lock);
b60503ba
MW		 509}
510
a7a7cbe3 511static void **nvme_pci_iod_list(struct request *req)
b60503ba 512{
f4800d6d 513 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
91fb2b60 514 return (void **)(iod->sgt.sgl + blk_rq_nr_phys_segments(req));
b60503ba
MW		 515}
516
955b1b5a
MI		 517static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req)
518{
a53232cb 519 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
20469a37 520 int nseg = blk_rq_nr_phys_segments(req);
955b1b5a
MI		 521 unsigned int avg_seg_size;
522
20469a37 523 avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
955b1b5a 524
253a0b76 525 if (!nvme_ctrl_sgl_supported(&dev->ctrl))
955b1b5a 526 return false;
a53232cb 527 if (!nvmeq->qid)
955b1b5a
MI		 528 return false;
529 if (!sgl_threshold || avg_seg_size < sgl_threshold)
530 return false;
531 return true;
532}
533
9275c206 534static void nvme_free_prps(struct nvme_dev *dev, struct request *req)
b60503ba 535{
6c3c05b0 536 const int last_prp = NVME_CTRL_PAGE_SIZE / sizeof(__le64) - 1;
9275c206
CH		 537 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
538 dma_addr_t dma_addr = iod->first_dma;
eca18b23 539 int i;
eca18b23 540
c372cdd1 541 for (i = 0; i < iod->nr_allocations; i++) {
9275c206
CH		 542 __le64 *prp_list = nvme_pci_iod_list(req)[i];
543 dma_addr_t next_dma_addr = le64_to_cpu(prp_list[last_prp]);
544
545 dma_pool_free(dev->prp_page_pool, prp_list, dma_addr);
546 dma_addr = next_dma_addr;
7fe07d14 547 }
9275c206 548}
dff824b2 549
9275c206
CH		 550static void nvme_free_sgls(struct nvme_dev *dev, struct request *req)
551{
552 const int last_sg = SGES_PER_PAGE - 1;
553 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
554 dma_addr_t dma_addr = iod->first_dma;
555 int i;
dff824b2 556
c372cdd1 557 for (i = 0; i < iod->nr_allocations; i++) {
9275c206
CH		 558 struct nvme_sgl_desc *sg_list = nvme_pci_iod_list(req)[i];
559 dma_addr_t next_dma_addr = le64_to_cpu((sg_list[last_sg]).addr);
dff824b2 560
9275c206
CH		 561 dma_pool_free(dev->prp_page_pool, sg_list, dma_addr);
562 dma_addr = next_dma_addr;
563 }
9275c206 564}
a7a7cbe3 565
9275c206
CH		 566static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
567{
568 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3 569
9275c206
CH		 570 if (iod->dma_len) {
571 dma_unmap_page(dev->dev, iod->first_dma, iod->dma_len,
572 rq_dma_dir(req));
573 return;
eca18b23 574 }
ac3dd5bd 575
91fb2b60
LG		 576 WARN_ON_ONCE(!iod->sgt.nents);
577
578 dma_unmap_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req), 0);
9275c206 579
c372cdd1 580 if (iod->nr_allocations == 0)
9275c206
CH		 581 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0],
582 iod->first_dma);
583 else if (iod->use_sgl)
584 nvme_free_sgls(dev, req);
585 else
586 nvme_free_prps(dev, req);
91fb2b60 587 mempool_free(iod->sgt.sgl, dev->iod_mempool);
b4ff9c8d
KB		 588}
589
d0877473
KB		 590static void nvme_print_sgl(struct scatterlist *sgl, int nents)
591{
592 int i;
593 struct scatterlist *sg;
594
595 for_each_sg(sgl, sg, nents, i) {
596 dma_addr_t phys = sg_phys(sg);
597 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
598 "dma_address:%pad dma_length:%d\n",
599 i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
600 sg_dma_len(sg));
601 }
602}
603
a7a7cbe3
CK		 604static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
605 struct request *req, struct nvme_rw_command *cmnd)
ff22b54f 606{
f4800d6d 607 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
99802a7a 608 struct dma_pool *pool;
b131c61d 609 int length = blk_rq_payload_bytes(req);
91fb2b60 610 struct scatterlist *sg = iod->sgt.sgl;
ff22b54f
MW		 611 int dma_len = sg_dma_len(sg);
612 u64 dma_addr = sg_dma_address(sg);
6c3c05b0 613 int offset = dma_addr & (NVME_CTRL_PAGE_SIZE - 1);
e025344c 614 __le64 *prp_list;
a7a7cbe3 615 void **list = nvme_pci_iod_list(req);
e025344c 616 dma_addr_t prp_dma;
eca18b23 617 int nprps, i;
ff22b54f 618
6c3c05b0 619 length -= (NVME_CTRL_PAGE_SIZE - offset);
5228b328
JS		 620 if (length <= 0) {
621 iod->first_dma = 0;
a7a7cbe3 622 goto done;
5228b328 623 }
ff22b54f 624
6c3c05b0 625 dma_len -= (NVME_CTRL_PAGE_SIZE - offset);
ff22b54f 626 if (dma_len) {
6c3c05b0 627 dma_addr += (NVME_CTRL_PAGE_SIZE - offset);
ff22b54f
MW		 628 } else {
629 sg = sg_next(sg);
630 dma_addr = sg_dma_address(sg);
631 dma_len = sg_dma_len(sg);
632 }
633
6c3c05b0 634 if (length <= NVME_CTRL_PAGE_SIZE) {
edd10d33 635 iod->first_dma = dma_addr;
a7a7cbe3 636 goto done;
e025344c
SMM		 637 }
638
6c3c05b0 639 nprps = DIV_ROUND_UP(length, NVME_CTRL_PAGE_SIZE);
99802a7a
MW		 640 if (nprps <= (256 / 8)) {
641 pool = dev->prp_small_pool;
c372cdd1 642 iod->nr_allocations = 0;
99802a7a
MW		 643 } else {
644 pool = dev->prp_page_pool;
c372cdd1 645 iod->nr_allocations = 1;
99802a7a
MW		 646 }
647
69d2b571 648 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
b77954cb 649 if (!prp_list) {
c372cdd1 650 iod->nr_allocations = -1;
86eea289 651 return BLK_STS_RESOURCE;
b77954cb 652 }
eca18b23
MW		 653 list[0] = prp_list;
654 iod->first_dma = prp_dma;
e025344c
SMM		 655 i = 0;
656 for (;;) {
6c3c05b0 657 if (i == NVME_CTRL_PAGE_SIZE >> 3) {
e025344c 658 __le64 *old_prp_list = prp_list;
69d2b571 659 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
eca18b23 660 if (!prp_list)
fa073216 661 goto free_prps;
c372cdd1 662 list[iod->nr_allocations++] = prp_list;
7523d834
MW		 663 prp_list[0] = old_prp_list[i - 1];
664 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
665 i = 1;
e025344c
SMM		 666 }
667 prp_list[i++] = cpu_to_le64(dma_addr);
6c3c05b0
CK		 668 dma_len -= NVME_CTRL_PAGE_SIZE;
669 dma_addr += NVME_CTRL_PAGE_SIZE;
670 length -= NVME_CTRL_PAGE_SIZE;
e025344c
SMM		 671 if (length <= 0)
672 break;
673 if (dma_len > 0)
674 continue;
86eea289
KB		 675 if (unlikely(dma_len < 0))
676 goto bad_sgl;
e025344c
SMM		 677 sg = sg_next(sg);
678 dma_addr = sg_dma_address(sg);
679 dma_len = sg_dma_len(sg);
ff22b54f 680 }
a7a7cbe3 681done:
91fb2b60 682 cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sgt.sgl));
a7a7cbe3 683 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
86eea289 684 return BLK_STS_OK;
fa073216
CH		 685free_prps:
686 nvme_free_prps(dev, req);
687 return BLK_STS_RESOURCE;
688bad_sgl:
91fb2b60 689 WARN(DO_ONCE(nvme_print_sgl, iod->sgt.sgl, iod->sgt.nents),
d0877473 690 "Invalid SGL for payload:%d nents:%d\n",
91fb2b60 691 blk_rq_payload_bytes(req), iod->sgt.nents);
86eea289 692 return BLK_STS_IOERR;
ff22b54f
MW		 693}
694
a7a7cbe3
CK		 695static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
696 struct scatterlist *sg)
697{
698 sge->addr = cpu_to_le64(sg_dma_address(sg));
699 sge->length = cpu_to_le32(sg_dma_len(sg));
700 sge->type = NVME_SGL_FMT_DATA_DESC << 4;
701}
702
703static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
704 dma_addr_t dma_addr, int entries)
705{
706 sge->addr = cpu_to_le64(dma_addr);
707 if (entries < SGES_PER_PAGE) {
708 sge->length = cpu_to_le32(entries * sizeof(*sge));
709 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
710 } else {
711 sge->length = cpu_to_le32(PAGE_SIZE);
712 sge->type = NVME_SGL_FMT_SEG_DESC << 4;
713 }
714}
715
716static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
91fb2b60 717 struct request *req, struct nvme_rw_command *cmd)
a7a7cbe3
CK		 718{
719 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3
CK		 720 struct dma_pool *pool;
721 struct nvme_sgl_desc *sg_list;
91fb2b60
LG		 722 struct scatterlist *sg = iod->sgt.sgl;
723 unsigned int entries = iod->sgt.nents;
a7a7cbe3 724 dma_addr_t sgl_dma;
b0f2853b 725 int i = 0;
a7a7cbe3 726
a7a7cbe3
CK		 727 /* setting the transfer type as SGL */
728 cmd->flags = NVME_CMD_SGL_METABUF;
729
b0f2853b 730 if (entries == 1) {
a7a7cbe3
CK		 731 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
732 return BLK_STS_OK;
733 }
734
735 if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
736 pool = dev->prp_small_pool;
c372cdd1 737 iod->nr_allocations = 0;
a7a7cbe3
CK		 738 } else {
739 pool = dev->prp_page_pool;
c372cdd1 740 iod->nr_allocations = 1;
a7a7cbe3
CK		 741 }
742
743 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
744 if (!sg_list) {
c372cdd1 745 iod->nr_allocations = -1;
a7a7cbe3
CK		 746 return BLK_STS_RESOURCE;
747 }
748
749 nvme_pci_iod_list(req)[0] = sg_list;
750 iod->first_dma = sgl_dma;
751
752 nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
753
754 do {
755 if (i == SGES_PER_PAGE) {
756 struct nvme_sgl_desc *old_sg_desc = sg_list;
757 struct nvme_sgl_desc *link = &old_sg_desc[i - 1];
758
759 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
760 if (!sg_list)
fa073216 761 goto free_sgls;
a7a7cbe3
CK		 762
763 i = 0;
c372cdd1 764 nvme_pci_iod_list(req)[iod->nr_allocations++] = sg_list;
a7a7cbe3
CK		 765 sg_list[i++] = *link;
766 nvme_pci_sgl_set_seg(link, sgl_dma, entries);
767 }
768
769 nvme_pci_sgl_set_data(&sg_list[i++], sg);
a7a7cbe3 770 sg = sg_next(sg);
b0f2853b 771 } while (--entries > 0);
a7a7cbe3 772
a7a7cbe3 773 return BLK_STS_OK;
fa073216
CH		 774free_sgls:
775 nvme_free_sgls(dev, req);
776 return BLK_STS_RESOURCE;
a7a7cbe3
CK		 777}
778
dff824b2
CH		 779static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev,
780 struct request *req, struct nvme_rw_command *cmnd,
781 struct bio_vec *bv)
782{
783 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
6c3c05b0
CK		 784 unsigned int offset = bv->bv_offset & (NVME_CTRL_PAGE_SIZE - 1);
785 unsigned int first_prp_len = NVME_CTRL_PAGE_SIZE - offset;
dff824b2
CH		 786
787 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
788 if (dma_mapping_error(dev->dev, iod->first_dma))
789 return BLK_STS_RESOURCE;
790 iod->dma_len = bv->bv_len;
791
792 cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma);
793 if (bv->bv_len > first_prp_len)
794 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len);
a56ea614
LR		 795 else
796 cmnd->dptr.prp2 = 0;
359c1f88 797 return BLK_STS_OK;
dff824b2
CH		 798}
799
29791057
CH		 800static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev,
801 struct request *req, struct nvme_rw_command *cmnd,
802 struct bio_vec *bv)
803{
804 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
805
806 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
807 if (dma_mapping_error(dev->dev, iod->first_dma))
808 return BLK_STS_RESOURCE;
809 iod->dma_len = bv->bv_len;
810
049bf372 811 cmnd->flags = NVME_CMD_SGL_METABUF;
29791057
CH		 812 cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma);
813 cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len);
814 cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4;
359c1f88 815 return BLK_STS_OK;
29791057
CH		 816}
817
fc17b653 818static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
b131c61d 819 struct nvme_command *cmnd)
d29ec824 820{
f4800d6d 821 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
70479b71 822 blk_status_t ret = BLK_STS_RESOURCE;
91fb2b60 823 int rc;
d29ec824 824
dff824b2 825 if (blk_rq_nr_phys_segments(req) == 1) {
a53232cb 826 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
dff824b2
CH		 827 struct bio_vec bv = req_bvec(req);
828
829 if (!is_pci_p2pdma_page(bv.bv_page)) {
6c3c05b0 830 if (bv.bv_offset + bv.bv_len <= NVME_CTRL_PAGE_SIZE * 2)
dff824b2
CH		 831 return nvme_setup_prp_simple(dev, req,
832 &cmnd->rw, &bv);
29791057 833
a53232cb 834 if (nvmeq->qid && sgl_threshold &&
253a0b76 835 nvme_ctrl_sgl_supported(&dev->ctrl))
29791057
CH		 836 return nvme_setup_sgl_simple(dev, req,
837 &cmnd->rw, &bv);
dff824b2
CH		 838 }
839 }
840
841 iod->dma_len = 0;
91fb2b60
LG		 842 iod->sgt.sgl = mempool_alloc(dev->iod_mempool, GFP_ATOMIC);
843 if (!iod->sgt.sgl)
d43f1ccf 844 return BLK_STS_RESOURCE;
91fb2b60
LG		 845 sg_init_table(iod->sgt.sgl, blk_rq_nr_phys_segments(req));
846 iod->sgt.orig_nents = blk_rq_map_sg(req->q, req, iod->sgt.sgl);
847 if (!iod->sgt.orig_nents)
fa073216 848 goto out_free_sg;
d29ec824 849
91fb2b60
LG		 850 rc = dma_map_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req),
851 DMA_ATTR_NO_WARN);
852 if (rc) {
853 if (rc == -EREMOTEIO)
854 ret = BLK_STS_TARGET;
fa073216 855 goto out_free_sg;
91fb2b60 856 }
d29ec824 857
70479b71 858 iod->use_sgl = nvme_pci_use_sgls(dev, req);
955b1b5a 859 if (iod->use_sgl)
91fb2b60 860 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw);
a7a7cbe3
CK		 861 else
862 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
86eea289 863 if (ret != BLK_STS_OK)
fa073216
CH		 864 goto out_unmap_sg;
865 return BLK_STS_OK;
866
867out_unmap_sg:
91fb2b60 868 dma_unmap_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req), 0);
fa073216 869out_free_sg:
91fb2b60 870 mempool_free(iod->sgt.sgl, dev->iod_mempool);
4aedb705
CH		 871 return ret;
872}
3045c0d0 873
4aedb705
CH		 874static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req,
875 struct nvme_command *cmnd)
876{
877 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
00df5cb4 878
4aedb705
CH		 879 iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req),
880 rq_dma_dir(req), 0);
881 if (dma_mapping_error(dev->dev, iod->meta_dma))
882 return BLK_STS_IOERR;
883 cmnd->rw.metadata = cpu_to_le64(iod->meta_dma);
359c1f88 884 return BLK_STS_OK;
00df5cb4
MW		 885}
886
62451a2b 887static blk_status_t nvme_prep_rq(struct nvme_dev *dev, struct request *req)
edd10d33 888{
9b048119 889 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
ebe6d874 890 blk_status_t ret;
e1e5e564 891
52da4f3f 892 iod->aborted = false;
c372cdd1 893 iod->nr_allocations = -1;
91fb2b60 894 iod->sgt.nents = 0;
9b048119 895
62451a2b 896 ret = nvme_setup_cmd(req->q->queuedata, req);
fc17b653 897 if (ret)
f4800d6d 898 return ret;
a4aea562 899
fc17b653 900 if (blk_rq_nr_phys_segments(req)) {
62451a2b 901 ret = nvme_map_data(dev, req, &iod->cmd);
fc17b653 902 if (ret)
9b048119 903 goto out_free_cmd;
fc17b653 904 }
a4aea562 905
4aedb705 906 if (blk_integrity_rq(req)) {
62451a2b 907 ret = nvme_map_metadata(dev, req, &iod->cmd);
4aedb705
CH		 908 if (ret)
909 goto out_unmap_data;
910 }
911
6887fc64 912 nvme_start_request(req);
fc17b653 913 return BLK_STS_OK;
4aedb705
CH		 914out_unmap_data:
915 nvme_unmap_data(dev, req);
f9d03f96
CH		 916out_free_cmd:
917 nvme_cleanup_cmd(req);
ba1ca37e 918 return ret;
b60503ba 919}
e1e5e564 920
62451a2b
JA		 921/*
922 * NOTE: ns is NULL when called on the admin queue.
923 */
924static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
925 const struct blk_mq_queue_data *bd)
926{
927 struct nvme_queue *nvmeq = hctx->driver_data;
928 struct nvme_dev *dev = nvmeq->dev;
929 struct request *req = bd->rq;
930 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
931 blk_status_t ret;
932
933 /*
934 * We should not need to do this, but we're still using this to
935 * ensure we can drain requests on a dying queue.
936 */
937 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
938 return BLK_STS_IOERR;
939
940 if (unlikely(!nvme_check_ready(&dev->ctrl, req, true)))
941 return nvme_fail_nonready_command(&dev->ctrl, req);
942
943 ret = nvme_prep_rq(dev, req);
944 if (unlikely(ret))
945 return ret;
946 spin_lock(&nvmeq->sq_lock);
947 nvme_sq_copy_cmd(nvmeq, &iod->cmd);
948 nvme_write_sq_db(nvmeq, bd->last);
949 spin_unlock(&nvmeq->sq_lock);
950 return BLK_STS_OK;
951}
952
d62cbcf6
JA		 953static void nvme_submit_cmds(struct nvme_queue *nvmeq, struct request **rqlist)
954{
955 spin_lock(&nvmeq->sq_lock);
956 while (!rq_list_empty(*rqlist)) {
957 struct request *req = rq_list_pop(rqlist);
958 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
959
960 nvme_sq_copy_cmd(nvmeq, &iod->cmd);
961 }
962 nvme_write_sq_db(nvmeq, true);
963 spin_unlock(&nvmeq->sq_lock);
964}
965
966static bool nvme_prep_rq_batch(struct nvme_queue *nvmeq, struct request *req)
967{
968 /*
969 * We should not need to do this, but we're still using this to
970 * ensure we can drain requests on a dying queue.
971 */
972 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
973 return false;
974 if (unlikely(!nvme_check_ready(&nvmeq->dev->ctrl, req, true)))
975 return false;
976
977 req->mq_hctx->tags->rqs[req->tag] = req;
978 return nvme_prep_rq(nvmeq->dev, req) == BLK_STS_OK;
979}
980
981static void nvme_queue_rqs(struct request **rqlist)
982{
6bfec799 983 struct request *req, *next, *prev = NULL;
d62cbcf6
JA		 984 struct request *requeue_list = NULL;
985
6bfec799 986 rq_list_for_each_safe(rqlist, req, next) {
d62cbcf6
JA		 987 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
988
989 if (!nvme_prep_rq_batch(nvmeq, req)) {
990 /* detach 'req' and add to remainder list */
6bfec799
KB		 991 rq_list_move(rqlist, &requeue_list, req, prev);
992
993 req = prev;
994 if (!req)
995 continue;
d62cbcf6
JA		 996 }
997
6bfec799 998 if (!next || req->mq_hctx != next->mq_hctx) {
d62cbcf6 999 /* detach rest of list, and submit */
6bfec799 1000 req->rq_next = NULL;
d62cbcf6 1001 nvme_submit_cmds(nvmeq, rqlist);
6bfec799
KB		 1002 *rqlist = next;
1003 prev = NULL;
1004 } else
1005 prev = req;
1006 }
d62cbcf6
JA		 1007
1008 *rqlist = requeue_list;
1009}
1010
c234a653 1011static __always_inline void nvme_pci_unmap_rq(struct request *req)
eee417b0 1012{
a53232cb
KB		 1013 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
1014 struct nvme_dev *dev = nvmeq->dev;
1015
1016 if (blk_integrity_rq(req)) {
1017 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a4aea562 1018
4aedb705
CH		 1019 dma_unmap_page(dev->dev, iod->meta_dma,
1020 rq_integrity_vec(req)->bv_len, rq_data_dir(req));
a53232cb
KB		 1021 }
1022
b15c592d 1023 if (blk_rq_nr_phys_segments(req))
4aedb705 1024 nvme_unmap_data(dev, req);
c234a653
JA		 1025}
1026
1027static void nvme_pci_complete_rq(struct request *req)
1028{
1029 nvme_pci_unmap_rq(req);
77f02a7a 1030 nvme_complete_rq(req);
b60503ba
MW		 1031}
1032
c234a653
JA		 1033static void nvme_pci_complete_batch(struct io_comp_batch *iob)
1034{
1035 nvme_complete_batch(iob, nvme_pci_unmap_rq);
1036}
1037
d783e0bd 1038/* We read the CQE phase first to check if the rest of the entry is valid */
750dde44 1039static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq)
d783e0bd 1040{
74943d45
KB		 1041 struct nvme_completion *hcqe = &nvmeq->cqes[nvmeq->cq_head];
1042
1043 return (le16_to_cpu(READ_ONCE(hcqe->status)) & 1) == nvmeq->cq_phase;
d783e0bd
MR		 1044}
1045
eb281c82 1046static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
b60503ba 1047{
eb281c82 1048 u16 head = nvmeq->cq_head;
adf68f21 1049
397c699f
KB		 1050 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
1051 nvmeq->dbbuf_cq_ei))
1052 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
eb281c82 1053}
aae239e1 1054
cfa27356
CH		 1055static inline struct blk_mq_tags *nvme_queue_tagset(struct nvme_queue *nvmeq)
1056{
1057 if (!nvmeq->qid)
1058 return nvmeq->dev->admin_tagset.tags[0];
1059 return nvmeq->dev->tagset.tags[nvmeq->qid - 1];
1060}
1061
c234a653
JA		 1062static inline void nvme_handle_cqe(struct nvme_queue *nvmeq,
1063 struct io_comp_batch *iob, u16 idx)
83a12fb7 1064{
74943d45 1065 struct nvme_completion *cqe = &nvmeq->cqes[idx];
62df8016 1066 __u16 command_id = READ_ONCE(cqe->command_id);
83a12fb7 1067 struct request *req;
adf68f21 1068
83a12fb7
SG		 1069 /*
1070 * AEN requests are special as they don't time out and can
1071 * survive any kind of queue freeze and often don't respond to
1072 * aborts. We don't even bother to allocate a struct request
1073 * for them but rather special case them here.
1074 */
62df8016 1075 if (unlikely(nvme_is_aen_req(nvmeq->qid, command_id))) {
83a12fb7
SG		 1076 nvme_complete_async_event(&nvmeq->dev->ctrl,
1077 cqe->status, &cqe->result);
a0fa9647 1078 return;
83a12fb7 1079 }
b60503ba 1080
e7006de6 1081 req = nvme_find_rq(nvme_queue_tagset(nvmeq), command_id);
50b7c243
XT		 1082 if (unlikely(!req)) {
1083 dev_warn(nvmeq->dev->ctrl.device,
1084 "invalid id %d completed on queue %d\n",
62df8016 1085 command_id, le16_to_cpu(cqe->sq_id));
50b7c243
XT		 1086 return;
1087 }
1088
604c01d5 1089 trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail);
c234a653
JA		 1090 if (!nvme_try_complete_req(req, cqe->status, cqe->result) &&
1091 !blk_mq_add_to_batch(req, iob, nvme_req(req)->status,
1092 nvme_pci_complete_batch))
ff029451 1093 nvme_pci_complete_rq(req);
83a12fb7 1094}
b60503ba 1095
5cb525c8
JA		 1096static inline void nvme_update_cq_head(struct nvme_queue *nvmeq)
1097{
a0aac973 1098 u32 tmp = nvmeq->cq_head + 1;
a8de6639
AD		 1099
1100 if (tmp == nvmeq->q_depth) {
5cb525c8 1101 nvmeq->cq_head = 0;
e2a366a4 1102 nvmeq->cq_phase ^= 1;
a8de6639
AD		 1103 } else {
1104 nvmeq->cq_head = tmp;
b60503ba 1105 }
a0fa9647
JA		 1106}
1107
c234a653
JA		 1108static inline int nvme_poll_cq(struct nvme_queue *nvmeq,
1109 struct io_comp_batch *iob)
a0fa9647 1110{
1052b8ac 1111 int found = 0;
b60503ba 1112
1052b8ac 1113 while (nvme_cqe_pending(nvmeq)) {
bf392a5d 1114 found++;
b69e2ef2
KB		 1115 /*
1116 * load-load control dependency between phase and the rest of
1117 * the cqe requires a full read memory barrier
1118 */
1119 dma_rmb();
c234a653 1120 nvme_handle_cqe(nvmeq, iob, nvmeq->cq_head);
5cb525c8 1121 nvme_update_cq_head(nvmeq);
920d13a8 1122 }
eb281c82 1123
324b494c 1124 if (found)
920d13a8 1125 nvme_ring_cq_doorbell(nvmeq);
5cb525c8 1126 return found;
b60503ba
MW		 1127}
1128
1129static irqreturn_t nvme_irq(int irq, void *data)
58ffacb5 1130{
58ffacb5 1131 struct nvme_queue *nvmeq = data;
4f502245 1132 DEFINE_IO_COMP_BATCH(iob);
5cb525c8 1133
4f502245
JA		 1134 if (nvme_poll_cq(nvmeq, &iob)) {
1135 if (!rq_list_empty(iob.req_list))
1136 nvme_pci_complete_batch(&iob);
05fae499 1137 return IRQ_HANDLED;
4f502245 1138 }
05fae499 1139 return IRQ_NONE;
58ffacb5
MW		 1140}
1141
1142static irqreturn_t nvme_irq_check(int irq, void *data)
1143{
1144 struct nvme_queue *nvmeq = data;
4e523547 1145
750dde44 1146 if (nvme_cqe_pending(nvmeq))
d783e0bd
MR		 1147 return IRQ_WAKE_THREAD;
1148 return IRQ_NONE;
58ffacb5
MW		 1149}
1150
0b2a8a9f 1151/*
fa059b85 1152 * Poll for completions for any interrupt driven queue
0b2a8a9f
CH		 1153 * Can be called from any context.
1154 */
fa059b85 1155static void nvme_poll_irqdisable(struct nvme_queue *nvmeq)
a0fa9647 1156{
3a7afd8e 1157 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
a0fa9647 1158
fa059b85 1159 WARN_ON_ONCE(test_bit(NVMEQ_POLLED, &nvmeq->flags));
442e19b7 1160
fa059b85 1161 disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
c234a653 1162 nvme_poll_cq(nvmeq, NULL);
fa059b85 1163 enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
a0fa9647
JA		 1164}
1165
5a72e899 1166static int nvme_poll(struct blk_mq_hw_ctx *hctx, struct io_comp_batch *iob)
dabcefab
JA		 1167{
1168 struct nvme_queue *nvmeq = hctx->driver_data;
dabcefab
JA		 1169 bool found;
1170
1171 if (!nvme_cqe_pending(nvmeq))
1172 return 0;
1173
3a7afd8e 1174 spin_lock(&nvmeq->cq_poll_lock);
c234a653 1175 found = nvme_poll_cq(nvmeq, iob);
3a7afd8e 1176 spin_unlock(&nvmeq->cq_poll_lock);
dabcefab 1177
dabcefab
JA		 1178 return found;
1179}
1180
ad22c355 1181static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
b60503ba 1182{
f866fc42 1183 struct nvme_dev *dev = to_nvme_dev(ctrl);
147b27e4 1184 struct nvme_queue *nvmeq = &dev->queues[0];
f66e2804 1185 struct nvme_command c = { };
b60503ba 1186
a4aea562 1187 c.common.opcode = nvme_admin_async_event;
ad22c355 1188 c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
3233b94c
JA		 1189
1190 spin_lock(&nvmeq->sq_lock);
1191 nvme_sq_copy_cmd(nvmeq, &c);
1192 nvme_write_sq_db(nvmeq, true);
1193 spin_unlock(&nvmeq->sq_lock);
f705f837
CH		 1194}
1195
b60503ba 1196static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
f705f837 1197{
f66e2804 1198 struct nvme_command c = { };
b60503ba 1199
b60503ba
MW		 1200 c.delete_queue.opcode = opcode;
1201 c.delete_queue.qid = cpu_to_le16(id);
1202
1c63dc66 1203 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1204}
1205
b60503ba 1206static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
a8e3e0bb 1207 struct nvme_queue *nvmeq, s16 vector)
b60503ba 1208{
f66e2804 1209 struct nvme_command c = { };
4b04cc6a
JA		 1210 int flags = NVME_QUEUE_PHYS_CONTIG;
1211
7c349dde 1212 if (!test_bit(NVMEQ_POLLED, &nvmeq->flags))
4b04cc6a 1213 flags |= NVME_CQ_IRQ_ENABLED;
b60503ba 1214
d29ec824 1215 /*
16772ae6 1216 * Note: we (ab)use the fact that the prp fields survive if no data
d29ec824
CH		 1217 * is attached to the request.
1218 */
b60503ba
MW		 1219 c.create_cq.opcode = nvme_admin_create_cq;
1220 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1221 c.create_cq.cqid = cpu_to_le16(qid);
1222 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1223 c.create_cq.cq_flags = cpu_to_le16(flags);
7c349dde 1224 c.create_cq.irq_vector = cpu_to_le16(vector);
b60503ba 1225
1c63dc66 1226 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1227}
1228
1229static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1230 struct nvme_queue *nvmeq)
1231{
9abd68ef 1232 struct nvme_ctrl *ctrl = &dev->ctrl;
f66e2804 1233 struct nvme_command c = { };
81c1cd98 1234 int flags = NVME_QUEUE_PHYS_CONTIG;
b60503ba 1235
9abd68ef
JA		 1236 /*
1237 * Some drives have a bug that auto-enables WRRU if MEDIUM isn't
1238 * set. Since URGENT priority is zeroes, it makes all queues
1239 * URGENT.
1240 */
1241 if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ)
1242 flags |= NVME_SQ_PRIO_MEDIUM;
1243
d29ec824 1244 /*
16772ae6 1245 * Note: we (ab)use the fact that the prp fields survive if no data
d29ec824
CH		 1246 * is attached to the request.
1247 */
b60503ba
MW		 1248 c.create_sq.opcode = nvme_admin_create_sq;
1249 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1250 c.create_sq.sqid = cpu_to_le16(qid);
1251 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1252 c.create_sq.sq_flags = cpu_to_le16(flags);
1253 c.create_sq.cqid = cpu_to_le16(qid);
1254
1c63dc66 1255 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1256}
1257
1258static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1259{
1260 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1261}
1262
1263static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1264{
1265 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1266}
1267
de671d61 1268static enum rq_end_io_ret abort_endio(struct request *req, blk_status_t error)
bc5fc7e4 1269{
a53232cb 1270 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
e44ac588 1271
27fa9bc5
CH		 1272 dev_warn(nvmeq->dev->ctrl.device,
1273 "Abort status: 0x%x", nvme_req(req)->status);
e7a2a87d 1274 atomic_inc(&nvmeq->dev->ctrl.abort_limit);
e7a2a87d 1275 blk_mq_free_request(req);
de671d61 1276 return RQ_END_IO_NONE;
bc5fc7e4
MW		 1277}
1278
b2a0eb1a
KB		 1279static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1280{
b2a0eb1a
KB		 1281 /* If true, indicates loss of adapter communication, possibly by a
1282 * NVMe Subsystem reset.
1283 */
1284 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1285
ad70062c
JW		 1286 /* If there is a reset/reinit ongoing, we shouldn't reset again. */
1287 switch (dev->ctrl.state) {
1288 case NVME_CTRL_RESETTING:
ad6a0a52 1289 case NVME_CTRL_CONNECTING:
b2a0eb1a 1290 return false;
ad70062c
JW		 1291 default:
1292 break;
1293 }
b2a0eb1a
KB		 1294
1295 /* We shouldn't reset unless the controller is on fatal error state
1296 * _or_ if we lost the communication with it.
1297 */
1298 if (!(csts & NVME_CSTS_CFS) && !nssro)
1299 return false;
1300
b2a0eb1a
KB		 1301 return true;
1302}
1303
1304static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1305{
1306 /* Read a config register to help see what died. */
1307 u16 pci_status;
1308 int result;
1309
1310 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1311 &pci_status);
1312 if (result == PCIBIOS_SUCCESSFUL)
1313 dev_warn(dev->ctrl.device,
1314 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1315 csts, pci_status);
1316 else
1317 dev_warn(dev->ctrl.device,
1318 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1319 csts, result);
4641a8e6
KB		 1320
1321 if (csts != ~0)
1322 return;
1323
1324 dev_warn(dev->ctrl.device,
1325 "Does your device have a faulty power saving mode enabled?\n");
1326 dev_warn(dev->ctrl.device,
1327 "Try \"nvme_core.default_ps_max_latency_us=0 pcie_aspm=off\" and report a bug\n");
b2a0eb1a
KB		 1328}
1329
9bdb4833 1330static enum blk_eh_timer_return nvme_timeout(struct request *req)
c30341dc 1331{
f4800d6d 1332 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a53232cb 1333 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
c30341dc 1334 struct nvme_dev *dev = nvmeq->dev;
a4aea562 1335 struct request *abort_req;
f66e2804 1336 struct nvme_command cmd = { };
b2a0eb1a
KB		 1337 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1338
651438bb
WX		 1339 /* If PCI error recovery process is happening, we cannot reset or
1340 * the recovery mechanism will surely fail.
1341 */
1342 mb();
1343 if (pci_channel_offline(to_pci_dev(dev->dev)))
1344 return BLK_EH_RESET_TIMER;
1345
b2a0eb1a
KB		 1346 /*
1347 * Reset immediately if the controller is failed
1348 */
1349 if (nvme_should_reset(dev, csts)) {
1350 nvme_warn_reset(dev, csts);
1351 nvme_dev_disable(dev, false);
d86c4d8e 1352 nvme_reset_ctrl(&dev->ctrl);
db8c48e4 1353 return BLK_EH_DONE;
b2a0eb1a 1354 }
c30341dc 1355
7776db1c
KB		 1356 /*
1357 * Did we miss an interrupt?
1358 */
fa059b85 1359 if (test_bit(NVMEQ_POLLED, &nvmeq->flags))
5a72e899 1360 nvme_poll(req->mq_hctx, NULL);
fa059b85
KB		 1361 else
1362 nvme_poll_irqdisable(nvmeq);
1363
bf392a5d 1364 if (blk_mq_request_completed(req)) {
7776db1c
KB		 1365 dev_warn(dev->ctrl.device,
1366 "I/O %d QID %d timeout, completion polled\n",
1367 req->tag, nvmeq->qid);
db8c48e4 1368 return BLK_EH_DONE;
7776db1c
KB		 1369 }
1370
31c7c7d2 1371 /*
fd634f41
CH		 1372 * Shutdown immediately if controller times out while starting. The
1373 * reset work will see the pci device disabled when it gets the forced
1374 * cancellation error. All outstanding requests are completed on
db8c48e4 1375 * shutdown, so we return BLK_EH_DONE.
fd634f41 1376 */
4244140d
KB		 1377 switch (dev->ctrl.state) {
1378 case NVME_CTRL_CONNECTING:
2036f726 1379 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
df561f66 1380 fallthrough;
2036f726 1381 case NVME_CTRL_DELETING:
b9cac43c 1382 dev_warn_ratelimited(dev->ctrl.device,
fd634f41
CH		 1383 "I/O %d QID %d timeout, disable controller\n",
1384 req->tag, nvmeq->qid);
27fa9bc5 1385 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
7ad92f65 1386 nvme_dev_disable(dev, true);
db8c48e4 1387 return BLK_EH_DONE;
39a9dd81
KB		 1388 case NVME_CTRL_RESETTING:
1389 return BLK_EH_RESET_TIMER;
4244140d
KB		 1390 default:
1391 break;
c30341dc
KB		 1392 }
1393
fd634f41 1394 /*
ee0d96d3
BW		 1395 * Shutdown the controller immediately and schedule a reset if the
1396 * command was already aborted once before and still hasn't been
1397 * returned to the driver, or if this is the admin queue.
31c7c7d2 1398 */
f4800d6d 1399 if (!nvmeq->qid || iod->aborted) {
1b3c47c1 1400 dev_warn(dev->ctrl.device,
e1569a16
KB		 1401 "I/O %d QID %d timeout, reset controller\n",
1402 req->tag, nvmeq->qid);
7ad92f65 1403 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
a5cdb68c 1404 nvme_dev_disable(dev, false);
d86c4d8e 1405 nvme_reset_ctrl(&dev->ctrl);
c30341dc 1406
db8c48e4 1407 return BLK_EH_DONE;
c30341dc 1408 }
c30341dc 1409
e7a2a87d 1410 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
6bf25d16 1411 atomic_inc(&dev->ctrl.abort_limit);
31c7c7d2 1412 return BLK_EH_RESET_TIMER;
6bf25d16 1413 }
52da4f3f 1414 iod->aborted = true;
a4aea562 1415
c30341dc 1416 cmd.abort.opcode = nvme_admin_abort_cmd;
85f74acf 1417 cmd.abort.cid = nvme_cid(req);
c30341dc 1418 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
c30341dc 1419
1b3c47c1 1420 dev_warn(nvmeq->dev->ctrl.device,
86141440
CH		 1421 "I/O %d (%s) QID %d timeout, aborting\n",
1422 req->tag,
1423 nvme_get_opcode_str(nvme_req(req)->cmd->common.opcode),
1424 nvmeq->qid);
e7a2a87d 1425
e559398f
CH		 1426 abort_req = blk_mq_alloc_request(dev->ctrl.admin_q, nvme_req_op(&cmd),
1427 BLK_MQ_REQ_NOWAIT);
e7a2a87d
CH		 1428 if (IS_ERR(abort_req)) {
1429 atomic_inc(&dev->ctrl.abort_limit);
1430 return BLK_EH_RESET_TIMER;
1431 }
e559398f 1432 nvme_init_request(abort_req, &cmd);
e7a2a87d 1433
e2e53086 1434 abort_req->end_io = abort_endio;
e7a2a87d 1435 abort_req->end_io_data = NULL;
e2e53086 1436 blk_execute_rq_nowait(abort_req, false);
c30341dc 1437
31c7c7d2
CH		 1438 /*
1439 * The aborted req will be completed on receiving the abort req.
1440 * We enable the timer again. If hit twice, it'll cause a device reset,
1441 * as the device then is in a faulty state.
1442 */
1443 return BLK_EH_RESET_TIMER;
c30341dc
KB		 1444}
1445
a4aea562
MB		 1446static void nvme_free_queue(struct nvme_queue *nvmeq)
1447{
8a1d09a6 1448 dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq),
9e866774 1449 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
63223078
CH		 1450 if (!nvmeq->sq_cmds)
1451 return;
0f238ff5 1452
63223078 1453 if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) {
88a041f4 1454 pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev),
8a1d09a6 1455 nvmeq->sq_cmds, SQ_SIZE(nvmeq));
63223078 1456 } else {
8a1d09a6 1457 dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq),
63223078 1458 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
0f238ff5 1459 }
9e866774
MW		 1460}
1461
a1a5ef99 1462static void nvme_free_queues(struct nvme_dev *dev, int lowest)
22404274
KB		 1463{
1464 int i;
1465
d858e5f0 1466 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
d858e5f0 1467 dev->ctrl.queue_count--;
147b27e4 1468 nvme_free_queue(&dev->queues[i]);
121c7ad4 1469 }
22404274
KB		 1470}
1471
10981f23 1472static void nvme_suspend_queue(struct nvme_dev *dev, unsigned int qid)
b60503ba 1473{
10981f23
CH		 1474 struct nvme_queue *nvmeq = &dev->queues[qid];
1475
4e224106 1476 if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags))
10981f23 1477 return;
a09115b2 1478
4e224106 1479 /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */
d1f06f4a 1480 mb();
a09115b2 1481
4e224106 1482 nvmeq->dev->online_queues--;
1c63dc66 1483 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
9f27bd70 1484 nvme_quiesce_admin_queue(&nvmeq->dev->ctrl);
7c349dde 1485 if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags))
10981f23 1486 pci_free_irq(to_pci_dev(dev->dev), nvmeq->cq_vector, nvmeq);
4d115420 1487}
b60503ba 1488
8fae268b
KB		 1489static void nvme_suspend_io_queues(struct nvme_dev *dev)
1490{
1491 int i;
1492
1493 for (i = dev->ctrl.queue_count - 1; i > 0; i--)
10981f23 1494 nvme_suspend_queue(dev, i);
b60503ba
MW		 1495}
1496
fa46c6fb
KB		 1497/*
1498 * Called only on a device that has been disabled and after all other threads
9210c075
DZ		 1499 * that can check this device's completion queues have synced, except
1500 * nvme_poll(). This is the last chance for the driver to see a natural
1501 * completion before nvme_cancel_request() terminates all incomplete requests.
fa46c6fb
KB		 1502 */
1503static void nvme_reap_pending_cqes(struct nvme_dev *dev)
1504{
fa46c6fb
KB		 1505 int i;
1506
9210c075
DZ		 1507 for (i = dev->ctrl.queue_count - 1; i > 0; i--) {
1508 spin_lock(&dev->queues[i].cq_poll_lock);
c234a653 1509 nvme_poll_cq(&dev->queues[i], NULL);
9210c075
DZ		 1510 spin_unlock(&dev->queues[i].cq_poll_lock);
1511 }
fa46c6fb
KB		 1512}
1513
8ffaadf7
JD		 1514static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1515 int entry_size)
1516{
1517 int q_depth = dev->q_depth;
5fd4ce1b 1518 unsigned q_size_aligned = roundup(q_depth * entry_size,
6c3c05b0 1519 NVME_CTRL_PAGE_SIZE);
8ffaadf7
JD		 1520
1521 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
c45f5c99 1522 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
4e523547 1523
6c3c05b0 1524 mem_per_q = round_down(mem_per_q, NVME_CTRL_PAGE_SIZE);
c45f5c99 1525 q_depth = div_u64(mem_per_q, entry_size);
8ffaadf7
JD		 1526
1527 /*
1528 * Ensure the reduced q_depth is above some threshold where it
1529 * would be better to map queues in system memory with the
1530 * original depth
1531 */
1532 if (q_depth < 64)
1533 return -ENOMEM;
1534 }
1535
1536 return q_depth;
1537}
1538
1539static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
8a1d09a6 1540 int qid)
8ffaadf7 1541{
0f238ff5
LG		 1542 struct pci_dev *pdev = to_pci_dev(dev->dev);
1543
1544 if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
8a1d09a6 1545 nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq));
bfac8e9f
AM		 1546 if (nvmeq->sq_cmds) {
1547 nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev,
1548 nvmeq->sq_cmds);
1549 if (nvmeq->sq_dma_addr) {
1550 set_bit(NVMEQ_SQ_CMB, &nvmeq->flags);
1551 return 0;
1552 }
1553
8a1d09a6 1554 pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq));
63223078 1555 }
0f238ff5 1556 }
8ffaadf7 1557
8a1d09a6 1558 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq),
63223078 1559 &nvmeq->sq_dma_addr, GFP_KERNEL);
815c6704
KB		 1560 if (!nvmeq->sq_cmds)
1561 return -ENOMEM;
8ffaadf7
JD		 1562 return 0;
1563}
1564
a6ff7262 1565static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
b60503ba 1566{
147b27e4 1567 struct nvme_queue *nvmeq = &dev->queues[qid];
b60503ba 1568
62314e40
KB		 1569 if (dev->ctrl.queue_count > qid)
1570 return 0;
b60503ba 1571
c1e0cc7e 1572 nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES;
8a1d09a6
BH		 1573 nvmeq->q_depth = depth;
1574 nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq),
750afb08 1575 &nvmeq->cq_dma_addr, GFP_KERNEL);
b60503ba
MW		 1576 if (!nvmeq->cqes)
1577 goto free_nvmeq;
b60503ba 1578
8a1d09a6 1579 if (nvme_alloc_sq_cmds(dev, nvmeq, qid))
b60503ba
MW		 1580 goto free_cqdma;
1581
091b6092 1582 nvmeq->dev = dev;
1ab0cd69 1583 spin_lock_init(&nvmeq->sq_lock);
3a7afd8e 1584 spin_lock_init(&nvmeq->cq_poll_lock);
b60503ba 1585 nvmeq->cq_head = 0;
82123460 1586 nvmeq->cq_phase = 1;
b80d5ccc 1587 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
c30341dc 1588 nvmeq->qid = qid;
d858e5f0 1589 dev->ctrl.queue_count++;
36a7e993 1590
147b27e4 1591 return 0;
b60503ba
MW		 1592
1593 free_cqdma:
8a1d09a6
BH		 1594 dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes,
1595 nvmeq->cq_dma_addr);
b60503ba 1596 free_nvmeq:
147b27e4 1597 return -ENOMEM;
b60503ba
MW		 1598}
1599
dca51e78 1600static int queue_request_irq(struct nvme_queue *nvmeq)
3001082c 1601{
0ff199cb
CH		 1602 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1603 int nr = nvmeq->dev->ctrl.instance;
1604
1605 if (use_threaded_interrupts) {
1606 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1607 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1608 } else {
1609 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1610 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1611 }
3001082c
MW		 1612}
1613
22404274 1614static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
b60503ba 1615{
22404274 1616 struct nvme_dev *dev = nvmeq->dev;
b60503ba 1617
22404274 1618 nvmeq->sq_tail = 0;
38210800 1619 nvmeq->last_sq_tail = 0;
22404274
KB		 1620 nvmeq->cq_head = 0;
1621 nvmeq->cq_phase = 1;
b80d5ccc 1622 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
8a1d09a6 1623 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq));
f9f38e33 1624 nvme_dbbuf_init(dev, nvmeq, qid);
42f61420 1625 dev->online_queues++;
3a7afd8e 1626 wmb(); /* ensure the first interrupt sees the initialization */
22404274
KB		 1627}
1628
e4b9852a
CC		 1629/*
1630 * Try getting shutdown_lock while setting up IO queues.
1631 */
1632static int nvme_setup_io_queues_trylock(struct nvme_dev *dev)
1633{
1634 /*
1635 * Give up if the lock is being held by nvme_dev_disable.
1636 */
1637 if (!mutex_trylock(&dev->shutdown_lock))
1638 return -ENODEV;
1639
1640 /*
1641 * Controller is in wrong state, fail early.
1642 */
1643 if (dev->ctrl.state != NVME_CTRL_CONNECTING) {
1644 mutex_unlock(&dev->shutdown_lock);
1645 return -ENODEV;
1646 }
1647
1648 return 0;
1649}
1650
4b04cc6a 1651static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled)
22404274
KB		 1652{
1653 struct nvme_dev *dev = nvmeq->dev;
1654 int result;
7c349dde 1655 u16 vector = 0;
3f85d50b 1656
d1ed6aa1
CH		 1657 clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
1658
22b55601
KB		 1659 /*
1660 * A queue's vector matches the queue identifier unless the controller
1661 * has only one vector available.
1662 */
4b04cc6a
JA		 1663 if (!polled)
1664 vector = dev->num_vecs == 1 ? 0 : qid;
1665 else
7c349dde 1666 set_bit(NVMEQ_POLLED, &nvmeq->flags);
4b04cc6a 1667
a8e3e0bb 1668 result = adapter_alloc_cq(dev, qid, nvmeq, vector);
ded45505
KB		 1669 if (result)
1670 return result;
b60503ba
MW		 1671
1672 result = adapter_alloc_sq(dev, qid, nvmeq);
1673 if (result < 0)
ded45505 1674 return result;
c80b36cd 1675 if (result)
b60503ba
MW		 1676 goto release_cq;
1677
a8e3e0bb 1678 nvmeq->cq_vector = vector;
4b04cc6a 1679
e4b9852a
CC		 1680 result = nvme_setup_io_queues_trylock(dev);
1681 if (result)
1682 return result;
1683 nvme_init_queue(nvmeq, qid);
7c349dde 1684 if (!polled) {
4b04cc6a
JA		 1685 result = queue_request_irq(nvmeq);
1686 if (result < 0)
1687 goto release_sq;
1688 }
b60503ba 1689
4e224106 1690 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
e4b9852a 1691 mutex_unlock(&dev->shutdown_lock);
22404274 1692 return result;
b60503ba 1693
a8e3e0bb 1694release_sq:
f25a2dfc 1695 dev->online_queues--;
e4b9852a 1696 mutex_unlock(&dev->shutdown_lock);
b60503ba 1697 adapter_delete_sq(dev, qid);
a8e3e0bb 1698release_cq:
b60503ba 1699 adapter_delete_cq(dev, qid);
22404274 1700 return result;
b60503ba
MW		 1701}
1702
f363b089 1703static const struct blk_mq_ops nvme_mq_admin_ops = {
d29ec824 1704 .queue_rq = nvme_queue_rq,
77f02a7a 1705 .complete = nvme_pci_complete_rq,
a4aea562 1706 .init_hctx = nvme_admin_init_hctx,
e559398f 1707 .init_request = nvme_pci_init_request,
a4aea562
MB		 1708 .timeout = nvme_timeout,
1709};
1710
f363b089 1711static const struct blk_mq_ops nvme_mq_ops = {
376f7ef8 1712 .queue_rq = nvme_queue_rq,
d62cbcf6 1713 .queue_rqs = nvme_queue_rqs,
376f7ef8
CH		 1714 .complete = nvme_pci_complete_rq,
1715 .commit_rqs = nvme_commit_rqs,
1716 .init_hctx = nvme_init_hctx,
e559398f 1717 .init_request = nvme_pci_init_request,
376f7ef8
CH		 1718 .map_queues = nvme_pci_map_queues,
1719 .timeout = nvme_timeout,
1720 .poll = nvme_poll,
dabcefab
JA		 1721};
1722
ea191d2f
KB		 1723static void nvme_dev_remove_admin(struct nvme_dev *dev)
1724{
1c63dc66 1725 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
69d9a99c
KB		 1726 /*
1727 * If the controller was reset during removal, it's possible
1728 * user requests may be waiting on a stopped queue. Start the
1729 * queue to flush these to completion.
1730 */
9f27bd70 1731 nvme_unquiesce_admin_queue(&dev->ctrl);
0da7feaa 1732 nvme_remove_admin_tag_set(&dev->ctrl);
ea191d2f
KB		 1733 }
1734}
1735
97f6ef64
XY		 1736static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1737{
1738 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1739}
1740
1741static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1742{
1743 struct pci_dev *pdev = to_pci_dev(dev->dev);
1744
1745 if (size <= dev->bar_mapped_size)
1746 return 0;
1747 if (size > pci_resource_len(pdev, 0))
1748 return -ENOMEM;
1749 if (dev->bar)
1750 iounmap(dev->bar);
1751 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1752 if (!dev->bar) {
1753 dev->bar_mapped_size = 0;
1754 return -ENOMEM;
1755 }
1756 dev->bar_mapped_size = size;
1757 dev->dbs = dev->bar + NVME_REG_DBS;
1758
1759 return 0;
1760}
1761
01ad0990 1762static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
b60503ba 1763{
ba47e386 1764 int result;
b60503ba
MW		 1765 u32 aqa;
1766 struct nvme_queue *nvmeq;
1767
97f6ef64
XY		 1768 result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1769 if (result < 0)
1770 return result;
1771
8ef2074d 1772 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
20d0dfe6 1773 NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
dfbac8c7 1774
7a67cbea
CH		 1775 if (dev->subsystem &&
1776 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1777 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
dfbac8c7 1778
285b6e9b
CH		 1779 /*
1780 * If the device has been passed off to us in an enabled state, just
1781 * clear the enabled bit. The spec says we should set the 'shutdown
1782 * notification bits', but doing so may cause the device to complete
1783 * commands to the admin queue ... and we don't know what memory that
1784 * might be pointing at!
1785 */
1786 result = nvme_disable_ctrl(&dev->ctrl, false);
ba47e386
MW		 1787 if (result < 0)
1788 return result;
b60503ba 1789
a6ff7262 1790 result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
147b27e4
SG		 1791 if (result)
1792 return result;
b60503ba 1793
635333e4
MG		 1794 dev->ctrl.numa_node = dev_to_node(dev->dev);
1795
147b27e4 1796 nvmeq = &dev->queues[0];
b60503ba
MW		 1797 aqa = nvmeq->q_depth - 1;
1798 aqa |= aqa << 16;
1799
7a67cbea
CH		 1800 writel(aqa, dev->bar + NVME_REG_AQA);
1801 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1802 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
b60503ba 1803
c0f2f45b 1804 result = nvme_enable_ctrl(&dev->ctrl);
025c557a 1805 if (result)
d4875622 1806 return result;
a4aea562 1807
2b25d981 1808 nvmeq->cq_vector = 0;
161b8be2 1809 nvme_init_queue(nvmeq, 0);
dca51e78 1810 result = queue_request_irq(nvmeq);
758dd7fd 1811 if (result) {
7c349dde 1812 dev->online_queues--;
d4875622 1813 return result;
758dd7fd 1814 }
025c557a 1815
4e224106 1816 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
b60503ba
MW		 1817 return result;
1818}
1819
749941f2 1820static int nvme_create_io_queues(struct nvme_dev *dev)
42f61420 1821{
4b04cc6a 1822 unsigned i, max, rw_queues;
749941f2 1823 int ret = 0;
42f61420 1824
d858e5f0 1825 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
a6ff7262 1826 if (nvme_alloc_queue(dev, i, dev->q_depth)) {
749941f2 1827 ret = -ENOMEM;
42f61420 1828 break;
749941f2
CH		 1829 }
1830 }
42f61420 1831
d858e5f0 1832 max = min(dev->max_qid, dev->ctrl.queue_count - 1);
e20ba6e1
CH		 1833 if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) {
1834 rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] +
1835 dev->io_queues[HCTX_TYPE_READ];
4b04cc6a
JA		 1836 } else {
1837 rw_queues = max;
1838 }
1839
949928c1 1840 for (i = dev->online_queues; i <= max; i++) {
4b04cc6a
JA		 1841 bool polled = i > rw_queues;
1842
1843 ret = nvme_create_queue(&dev->queues[i], i, polled);
d4875622 1844 if (ret)
42f61420 1845 break;
27e8166c 1846 }
749941f2
CH		 1847
1848 /*
1849 * Ignore failing Create SQ/CQ commands, we can continue with less
8adb8c14
MI		 1850 * than the desired amount of queues, and even a controller without
1851 * I/O queues can still be used to issue admin commands. This might
749941f2
CH		 1852 * be useful to upgrade a buggy firmware for example.
1853 */
1854 return ret >= 0 ? 0 : ret;
b60503ba
MW		 1855}
1856
88de4598 1857static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
8ffaadf7 1858{
88de4598
CH		 1859 u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
1860
1861 return 1ULL << (12 + 4 * szu);
1862}
1863
1864static u32 nvme_cmb_size(struct nvme_dev *dev)
1865{
1866 return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
1867}
1868
f65efd6d 1869static void nvme_map_cmb(struct nvme_dev *dev)
8ffaadf7 1870{
88de4598 1871 u64 size, offset;
8ffaadf7
JD		 1872 resource_size_t bar_size;
1873 struct pci_dev *pdev = to_pci_dev(dev->dev);
8969f1f8 1874 int bar;
8ffaadf7 1875
9fe5c59f
KB		 1876 if (dev->cmb_size)
1877 return;
1878
20d3bb92
KJ		 1879 if (NVME_CAP_CMBS(dev->ctrl.cap))
1880 writel(NVME_CMBMSC_CRE, dev->bar + NVME_REG_CMBMSC);
1881
7a67cbea 1882 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
f65efd6d
CH		 1883 if (!dev->cmbsz)
1884 return;
202021c1 1885 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
8ffaadf7 1886
88de4598
CH		 1887 size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
1888 offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
8969f1f8
CH		 1889 bar = NVME_CMB_BIR(dev->cmbloc);
1890 bar_size = pci_resource_len(pdev, bar);
8ffaadf7
JD		 1891
1892 if (offset > bar_size)
f65efd6d 1893 return;
8ffaadf7 1894
20d3bb92
KJ		 1895 /*
1896 * Tell the controller about the host side address mapping the CMB,
1897 * and enable CMB decoding for the NVMe 1.4+ scheme:
1898 */
1899 if (NVME_CAP_CMBS(dev->ctrl.cap)) {
1900 hi_lo_writeq(NVME_CMBMSC_CRE | NVME_CMBMSC_CMSE |
1901 (pci_bus_address(pdev, bar) + offset),
1902 dev->bar + NVME_REG_CMBMSC);
1903 }
1904
8ffaadf7
JD		 1905 /*
1906 * Controllers may support a CMB size larger than their BAR,
1907 * for example, due to being behind a bridge. Reduce the CMB to
1908 * the reported size of the BAR
1909 */
1910 if (size > bar_size - offset)
1911 size = bar_size - offset;
1912
0f238ff5
LG		 1913 if (pci_p2pdma_add_resource(pdev, bar, size, offset)) {
1914 dev_warn(dev->ctrl.device,
1915 "failed to register the CMB\n");
f65efd6d 1916 return;
0f238ff5
LG		 1917 }
1918
8ffaadf7 1919 dev->cmb_size = size;
0f238ff5
LG		 1920 dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS);
1921
1922 if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) ==
1923 (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS))
1924 pci_p2pmem_publish(pdev, true);
8ffaadf7
JD		 1925}
1926
87ad72a5
CH		 1927static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1928{
6c3c05b0 1929 u32 host_mem_size = dev->host_mem_size >> NVME_CTRL_PAGE_SHIFT;
4033f35d 1930 u64 dma_addr = dev->host_mem_descs_dma;
f66e2804 1931 struct nvme_command c = { };
87ad72a5
CH		 1932 int ret;
1933
87ad72a5
CH		 1934 c.features.opcode = nvme_admin_set_features;
1935 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1936 c.features.dword11 = cpu_to_le32(bits);
6c3c05b0 1937 c.features.dword12 = cpu_to_le32(host_mem_size);
87ad72a5
CH		 1938 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr));
1939 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr));
1940 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs);
1941
1942 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1943 if (ret) {
1944 dev_warn(dev->ctrl.device,
1945 "failed to set host mem (err %d, flags %#x).\n",
1946 ret, bits);
a5df5e79
KB		 1947 } else
1948 dev->hmb = bits & NVME_HOST_MEM_ENABLE;
1949
87ad72a5
CH		 1950 return ret;
1951}
1952
1953static void nvme_free_host_mem(struct nvme_dev *dev)
1954{
1955 int i;
1956
1957 for (i = 0; i < dev->nr_host_mem_descs; i++) {
1958 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
6c3c05b0 1959 size_t size = le32_to_cpu(desc->size) * NVME_CTRL_PAGE_SIZE;
87ad72a5 1960
cc667f6d
LD		 1961 dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i],
1962 le64_to_cpu(desc->addr),
1963 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
87ad72a5
CH		 1964 }
1965
1966 kfree(dev->host_mem_desc_bufs);
1967 dev->host_mem_desc_bufs = NULL;
4033f35d
CH		 1968 dma_free_coherent(dev->dev,
1969 dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
1970 dev->host_mem_descs, dev->host_mem_descs_dma);
87ad72a5 1971 dev->host_mem_descs = NULL;
7e5dd57e 1972 dev->nr_host_mem_descs = 0;
87ad72a5
CH		 1973}
1974
92dc6895
CH		 1975static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
1976 u32 chunk_size)
9d713c2b 1977{
87ad72a5 1978 struct nvme_host_mem_buf_desc *descs;
92dc6895 1979 u32 max_entries, len;
4033f35d 1980 dma_addr_t descs_dma;
2ee0e4ed 1981 int i = 0;
87ad72a5 1982 void **bufs;
6fbcde66 1983 u64 size, tmp;
87ad72a5 1984
87ad72a5
CH		 1985 tmp = (preferred + chunk_size - 1);
1986 do_div(tmp, chunk_size);
1987 max_entries = tmp;
044a9df1
CH		 1988
1989 if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
1990 max_entries = dev->ctrl.hmmaxd;
1991
750afb08
LC		 1992 descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs),
1993 &descs_dma, GFP_KERNEL);
87ad72a5
CH		 1994 if (!descs)
1995 goto out;
1996
1997 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
1998 if (!bufs)
1999 goto out_free_descs;
2000
244a8fe4 2001 for (size = 0; size < preferred && i < max_entries; size += len) {
87ad72a5
CH		 2002 dma_addr_t dma_addr;
2003
50cdb7c6 2004 len = min_t(u64, chunk_size, preferred - size);
87ad72a5
CH		 2005 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
2006 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
2007 if (!bufs[i])
2008 break;
2009
2010 descs[i].addr = cpu_to_le64(dma_addr);
6c3c05b0 2011 descs[i].size = cpu_to_le32(len / NVME_CTRL_PAGE_SIZE);
87ad72a5
CH		 2012 i++;
2013 }
2014
92dc6895 2015 if (!size)
87ad72a5 2016 goto out_free_bufs;
87ad72a5 2017
87ad72a5
CH		 2018 dev->nr_host_mem_descs = i;
2019 dev->host_mem_size = size;
2020 dev->host_mem_descs = descs;
4033f35d 2021 dev->host_mem_descs_dma = descs_dma;
87ad72a5
CH		 2022 dev->host_mem_desc_bufs = bufs;
2023 return 0;
2024
2025out_free_bufs:
2026 while (--i >= 0) {
6c3c05b0 2027 size_t size = le32_to_cpu(descs[i].size) * NVME_CTRL_PAGE_SIZE;
87ad72a5 2028
cc667f6d
LD		 2029 dma_free_attrs(dev->dev, size, bufs[i],
2030 le64_to_cpu(descs[i].addr),
2031 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
87ad72a5
CH		 2032 }
2033
2034 kfree(bufs);
2035out_free_descs:
4033f35d
CH		 2036 dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
2037 descs_dma);
87ad72a5 2038out:
87ad72a5
CH		 2039 dev->host_mem_descs = NULL;
2040 return -ENOMEM;
2041}
2042
92dc6895
CH		 2043static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
2044{
9dc54a0d
CK		 2045 u64 min_chunk = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
2046 u64 hmminds = max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
2047 u64 chunk_size;
92dc6895
CH		 2048
2049 /* start big and work our way down */
9dc54a0d 2050 for (chunk_size = min_chunk; chunk_size >= hmminds; chunk_size /= 2) {
92dc6895
CH		 2051 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
2052 if (!min || dev->host_mem_size >= min)
2053 return 0;
2054 nvme_free_host_mem(dev);
2055 }
2056 }
2057
2058 return -ENOMEM;
2059}
2060
9620cfba 2061static int nvme_setup_host_mem(struct nvme_dev *dev)
87ad72a5
CH		 2062{
2063 u64 max = (u64)max_host_mem_size_mb * SZ_1M;
2064 u64 preferred = (u64)dev->ctrl.hmpre * 4096;
2065 u64 min = (u64)dev->ctrl.hmmin * 4096;
2066 u32 enable_bits = NVME_HOST_MEM_ENABLE;
6fbcde66 2067 int ret;
87ad72a5 2068
acb71e53
CH		 2069 if (!dev->ctrl.hmpre)
2070 return 0;
2071
87ad72a5
CH		 2072 preferred = min(preferred, max);
2073 if (min > max) {
2074 dev_warn(dev->ctrl.device,
2075 "min host memory (%lld MiB) above limit (%d MiB).\n",
2076 min >> ilog2(SZ_1M), max_host_mem_size_mb);
2077 nvme_free_host_mem(dev);
9620cfba 2078 return 0;
87ad72a5
CH		 2079 }
2080
2081 /*
2082 * If we already have a buffer allocated check if we can reuse it.
2083 */
2084 if (dev->host_mem_descs) {
2085 if (dev->host_mem_size >= min)
2086 enable_bits |= NVME_HOST_MEM_RETURN;
2087 else
2088 nvme_free_host_mem(dev);
2089 }
2090
2091 if (!dev->host_mem_descs) {
92dc6895
CH		 2092 if (nvme_alloc_host_mem(dev, min, preferred)) {
2093 dev_warn(dev->ctrl.device,
2094 "failed to allocate host memory buffer.\n");
9620cfba 2095 return 0; /* controller must work without HMB */
92dc6895
CH		 2096 }
2097
2098 dev_info(dev->ctrl.device,
2099 "allocated %lld MiB host memory buffer.\n",
2100 dev->host_mem_size >> ilog2(SZ_1M));
87ad72a5
CH		 2101 }
2102
9620cfba
CH		 2103 ret = nvme_set_host_mem(dev, enable_bits);
2104 if (ret)
87ad72a5 2105 nvme_free_host_mem(dev);
9620cfba 2106 return ret;
9d713c2b
KB		 2107}
2108
0521905e
KB		 2109static ssize_t cmb_show(struct device *dev, struct device_attribute *attr,
2110 char *buf)
2111{
2112 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2113
2114 return sysfs_emit(buf, "cmbloc : x%08x\ncmbsz : x%08x\n",
2115 ndev->cmbloc, ndev->cmbsz);
2116}
2117static DEVICE_ATTR_RO(cmb);
2118
1751e97a
KB		 2119static ssize_t cmbloc_show(struct device *dev, struct device_attribute *attr,
2120 char *buf)
2121{
2122 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2123
2124 return sysfs_emit(buf, "%u\n", ndev->cmbloc);
2125}
2126static DEVICE_ATTR_RO(cmbloc);
2127
2128static ssize_t cmbsz_show(struct device *dev, struct device_attribute *attr,
2129 char *buf)
2130{
2131 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2132
2133 return sysfs_emit(buf, "%u\n", ndev->cmbsz);
2134}
2135static DEVICE_ATTR_RO(cmbsz);
2136
a5df5e79
KB		 2137static ssize_t hmb_show(struct device *dev, struct device_attribute *attr,
2138 char *buf)
2139{
2140 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2141
2142 return sysfs_emit(buf, "%d\n", ndev->hmb);
2143}
2144
2145static ssize_t hmb_store(struct device *dev, struct device_attribute *attr,
2146 const char *buf, size_t count)
2147{
2148 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2149 bool new;
2150 int ret;
2151
99722c8a 2152 if (kstrtobool(buf, &new) < 0)
a5df5e79
KB		 2153 return -EINVAL;
2154
2155 if (new == ndev->hmb)
2156 return count;
2157
2158 if (new) {
2159 ret = nvme_setup_host_mem(ndev);
2160 } else {
2161 ret = nvme_set_host_mem(ndev, 0);
2162 if (!ret)
2163 nvme_free_host_mem(ndev);
2164 }
2165
2166 if (ret < 0)
2167 return ret;
2168
2169 return count;
2170}
2171static DEVICE_ATTR_RW(hmb);
2172
0521905e
KB		 2173static umode_t nvme_pci_attrs_are_visible(struct kobject *kobj,
2174 struct attribute *a, int n)
2175{
2176 struct nvme_ctrl *ctrl =
2177 dev_get_drvdata(container_of(kobj, struct device, kobj));
2178 struct nvme_dev *dev = to_nvme_dev(ctrl);
2179
1751e97a
KB		 2180 if (a == &dev_attr_cmb.attr ||
2181 a == &dev_attr_cmbloc.attr ||
2182 a == &dev_attr_cmbsz.attr) {
2183 if (!dev->cmbsz)
2184 return 0;
2185 }
a5df5e79
KB		 2186 if (a == &dev_attr_hmb.attr && !ctrl->hmpre)
2187 return 0;
2188
0521905e
KB		 2189 return a->mode;
2190}
2191
2192static struct attribute *nvme_pci_attrs[] = {
2193 &dev_attr_cmb.attr,
1751e97a
KB		 2194 &dev_attr_cmbloc.attr,
2195 &dev_attr_cmbsz.attr,
a5df5e79 2196 &dev_attr_hmb.attr,
0521905e
KB		 2197 NULL,
2198};
2199
86adbf0c 2200static const struct attribute_group nvme_pci_dev_attrs_group = {
0521905e
KB		 2201 .attrs = nvme_pci_attrs,
2202 .is_visible = nvme_pci_attrs_are_visible,
2203};
2204
86adbf0c
CH		 2205static const struct attribute_group *nvme_pci_dev_attr_groups[] = {
2206 &nvme_dev_attrs_group,
2207 &nvme_pci_dev_attrs_group,
2208 NULL,
2209};
2210
612b7286
ML		 2211/*
2212 * nirqs is the number of interrupts available for write and read
2213 * queues. The core already reserved an interrupt for the admin queue.
2214 */
2215static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs)
3b6592f7 2216{
612b7286 2217 struct nvme_dev *dev = affd->priv;
2a5bcfdd 2218 unsigned int nr_read_queues, nr_write_queues = dev->nr_write_queues;
3b6592f7
JA		 2219
2220 /*
ee0d96d3 2221 * If there is no interrupt available for queues, ensure that
612b7286
ML		 2222 * the default queue is set to 1. The affinity set size is
2223 * also set to one, but the irq core ignores it for this case.
2224 *
2225 * If only one interrupt is available or 'write_queue' == 0, combine
2226 * write and read queues.
2227 *
2228 * If 'write_queues' > 0, ensure it leaves room for at least one read
2229 * queue.
3b6592f7 2230 */
612b7286
ML		 2231 if (!nrirqs) {
2232 nrirqs = 1;
2233 nr_read_queues = 0;
2a5bcfdd 2234 } else if (nrirqs == 1 || !nr_write_queues) {
612b7286 2235 nr_read_queues = 0;
2a5bcfdd 2236 } else if (nr_write_queues >= nrirqs) {
612b7286 2237 nr_read_queues = 1;
3b6592f7 2238 } else {
2a5bcfdd 2239 nr_read_queues = nrirqs - nr_write_queues;
3b6592f7 2240 }
612b7286
ML		 2241
2242 dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2243 affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2244 dev->io_queues[HCTX_TYPE_READ] = nr_read_queues;
2245 affd->set_size[HCTX_TYPE_READ] = nr_read_queues;
2246 affd->nr_sets = nr_read_queues ? 2 : 1;
3b6592f7
JA		 2247}
2248
6451fe73 2249static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues)
3b6592f7
JA		 2250{
2251 struct pci_dev *pdev = to_pci_dev(dev->dev);
3b6592f7 2252 struct irq_affinity affd = {
9cfef55b 2253 .pre_vectors = 1,
612b7286
ML		 2254 .calc_sets = nvme_calc_irq_sets,
2255 .priv = dev,
3b6592f7 2256 };
21cc2f3f 2257 unsigned int irq_queues, poll_queues;
6451fe73
JA		 2258
2259 /*
21cc2f3f
JX		 2260 * Poll queues don't need interrupts, but we need at least one I/O queue
2261 * left over for non-polled I/O.
6451fe73 2262 */
21cc2f3f
JX		 2263 poll_queues = min(dev->nr_poll_queues, nr_io_queues - 1);
2264 dev->io_queues[HCTX_TYPE_POLL] = poll_queues;
3b6592f7 2265
21cc2f3f
JX		 2266 /*
2267 * Initialize for the single interrupt case, will be updated in
2268 * nvme_calc_irq_sets().
2269 */
612b7286
ML		 2270 dev->io_queues[HCTX_TYPE_DEFAULT] = 1;
2271 dev->io_queues[HCTX_TYPE_READ] = 0;
3b6592f7 2272
66341331 2273 /*
21cc2f3f
JX		 2274 * We need interrupts for the admin queue and each non-polled I/O queue,
2275 * but some Apple controllers require all queues to use the first
2276 * vector.
66341331 2277 */
21cc2f3f
JX		 2278 irq_queues = 1;
2279 if (!(dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR))
2280 irq_queues += (nr_io_queues - poll_queues);
612b7286
ML		 2281 return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues,
2282 PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd);
3b6592f7
JA		 2283}
2284
2a5bcfdd
WZ		 2285static unsigned int nvme_max_io_queues(struct nvme_dev *dev)
2286{
e3aef095
NS		 2287 /*
2288 * If tags are shared with admin queue (Apple bug), then
2289 * make sure we only use one IO queue.
2290 */
2291 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2292 return 1;
2a5bcfdd
WZ		 2293 return num_possible_cpus() + dev->nr_write_queues + dev->nr_poll_queues;
2294}
2295
8d85fce7 2296static int nvme_setup_io_queues(struct nvme_dev *dev)
b60503ba 2297{
147b27e4 2298 struct nvme_queue *adminq = &dev->queues[0];
e75ec752 2299 struct pci_dev *pdev = to_pci_dev(dev->dev);
2a5bcfdd 2300 unsigned int nr_io_queues;
97f6ef64 2301 unsigned long size;
2a5bcfdd 2302 int result;
b60503ba 2303
2a5bcfdd
WZ		 2304 /*
2305 * Sample the module parameters once at reset time so that we have
2306 * stable values to work with.
2307 */
2308 dev->nr_write_queues = write_queues;
2309 dev->nr_poll_queues = poll_queues;
d38e9f04 2310
e3aef095 2311 nr_io_queues = dev->nr_allocated_queues - 1;
9a0be7ab
CH		 2312 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
2313 if (result < 0)
1b23484b 2314 return result;
9a0be7ab 2315
f5fa90dc 2316 if (nr_io_queues == 0)
a5229050 2317 return 0;
53dc180e 2318
e4b9852a
CC		 2319 /*
2320 * Free IRQ resources as soon as NVMEQ_ENABLED bit transitions
2321 * from set to unset. If there is a window to it is truely freed,
2322 * pci_free_irq_vectors() jumping into this window will crash.
2323 * And take lock to avoid racing with pci_free_irq_vectors() in
2324 * nvme_dev_disable() path.
2325 */
2326 result = nvme_setup_io_queues_trylock(dev);
2327 if (result)
2328 return result;
2329 if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags))
2330 pci_free_irq(pdev, 0, adminq);
b60503ba 2331
0f238ff5 2332 if (dev->cmb_use_sqes) {
8ffaadf7
JD		 2333 result = nvme_cmb_qdepth(dev, nr_io_queues,
2334 sizeof(struct nvme_command));
2335 if (result > 0)
2336 dev->q_depth = result;
2337 else
0f238ff5 2338 dev->cmb_use_sqes = false;
8ffaadf7
JD		 2339 }
2340
97f6ef64
XY		 2341 do {
2342 size = db_bar_size(dev, nr_io_queues);
2343 result = nvme_remap_bar(dev, size);
2344 if (!result)
2345 break;
e4b9852a
CC		 2346 if (!--nr_io_queues) {
2347 result = -ENOMEM;
2348 goto out_unlock;
2349 }
97f6ef64
XY		 2350 } while (1);
2351 adminq->q_db = dev->dbs;
f1938f6e 2352
8fae268b 2353 retry:
9d713c2b 2354 /* Deregister the admin queue's interrupt */
e4b9852a
CC		 2355 if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags))
2356 pci_free_irq(pdev, 0, adminq);
9d713c2b 2357
e32efbfc
JA		 2358 /*
2359 * If we enable msix early due to not intx, disable it again before
2360 * setting up the full range we need.
2361 */
dca51e78 2362 pci_free_irq_vectors(pdev);
3b6592f7
JA		 2363
2364 result = nvme_setup_irqs(dev, nr_io_queues);
e4b9852a
CC		 2365 if (result <= 0) {
2366 result = -EIO;
2367 goto out_unlock;
2368 }
3b6592f7 2369
22b55601 2370 dev->num_vecs = result;
4b04cc6a 2371 result = max(result - 1, 1);
e20ba6e1 2372 dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL];
fa08a396 2373
063a8096
MW		 2374 /*
2375 * Should investigate if there's a performance win from allocating
2376 * more queues than interrupt vectors; it might allow the submission
2377 * path to scale better, even if the receive path is limited by the
2378 * number of interrupts.
2379 */
dca51e78 2380 result = queue_request_irq(adminq);
7c349dde 2381 if (result)
e4b9852a 2382 goto out_unlock;
4e224106 2383 set_bit(NVMEQ_ENABLED, &adminq->flags);
e4b9852a 2384 mutex_unlock(&dev->shutdown_lock);
8fae268b
KB		 2385
2386 result = nvme_create_io_queues(dev);
2387 if (result || dev->online_queues < 2)
2388 return result;
2389
2390 if (dev->online_queues - 1 < dev->max_qid) {
2391 nr_io_queues = dev->online_queues - 1;
7d879c90 2392 nvme_delete_io_queues(dev);
e4b9852a
CC		 2393 result = nvme_setup_io_queues_trylock(dev);
2394 if (result)
2395 return result;
8fae268b
KB		 2396 nvme_suspend_io_queues(dev);
2397 goto retry;
2398 }
2399 dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n",
2400 dev->io_queues[HCTX_TYPE_DEFAULT],
2401 dev->io_queues[HCTX_TYPE_READ],
2402 dev->io_queues[HCTX_TYPE_POLL]);
2403 return 0;
e4b9852a
CC		 2404out_unlock:
2405 mutex_unlock(&dev->shutdown_lock);
2406 return result;
b60503ba
MW		 2407}
2408
de671d61
JA		 2409static enum rq_end_io_ret nvme_del_queue_end(struct request *req,
2410 blk_status_t error)
a5768aa8 2411{
db3cbfff 2412 struct nvme_queue *nvmeq = req->end_io_data;
b5875222 2413
db3cbfff 2414 blk_mq_free_request(req);
d1ed6aa1 2415 complete(&nvmeq->delete_done);
de671d61 2416 return RQ_END_IO_NONE;
a5768aa8
KB		 2417}
2418
de671d61
JA		 2419static enum rq_end_io_ret nvme_del_cq_end(struct request *req,
2420 blk_status_t error)
a5768aa8 2421{
db3cbfff 2422 struct nvme_queue *nvmeq = req->end_io_data;
a5768aa8 2423
d1ed6aa1
CH		 2424 if (error)
2425 set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
db3cbfff 2426
de671d61 2427 return nvme_del_queue_end(req, error);
a5768aa8
KB		 2428}
2429
db3cbfff 2430static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
bda4e0fb 2431{
db3cbfff
KB		 2432 struct request_queue *q = nvmeq->dev->ctrl.admin_q;
2433 struct request *req;
f66e2804 2434 struct nvme_command cmd = { };
bda4e0fb 2435
db3cbfff
KB		 2436 cmd.delete_queue.opcode = opcode;
2437 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
bda4e0fb 2438
e559398f 2439 req = blk_mq_alloc_request(q, nvme_req_op(&cmd), BLK_MQ_REQ_NOWAIT);
db3cbfff
KB		 2440 if (IS_ERR(req))
2441 return PTR_ERR(req);
e559398f 2442 nvme_init_request(req, &cmd);
bda4e0fb 2443
e2e53086
CH		 2444 if (opcode == nvme_admin_delete_cq)
2445 req->end_io = nvme_del_cq_end;
2446 else
2447 req->end_io = nvme_del_queue_end;
db3cbfff
KB		 2448 req->end_io_data = nvmeq;
2449
d1ed6aa1 2450 init_completion(&nvmeq->delete_done);
e2e53086 2451 blk_execute_rq_nowait(req, false);
db3cbfff 2452 return 0;
bda4e0fb
KB		 2453}
2454
7d879c90 2455static bool __nvme_delete_io_queues(struct nvme_dev *dev, u8 opcode)
a5768aa8 2456{
5271edd4 2457 int nr_queues = dev->online_queues - 1, sent = 0;
db3cbfff 2458 unsigned long timeout;
a5768aa8 2459
db3cbfff 2460 retry:
dc96f938 2461 timeout = NVME_ADMIN_TIMEOUT;
5271edd4
CH		 2462 while (nr_queues > 0) {
2463 if (nvme_delete_queue(&dev->queues[nr_queues], opcode))
2464 break;
2465 nr_queues--;
2466 sent++;
db3cbfff 2467 }
d1ed6aa1
CH		 2468 while (sent) {
2469 struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent];
2470
2471 timeout = wait_for_completion_io_timeout(&nvmeq->delete_done,
5271edd4
CH		 2472 timeout);
2473 if (timeout == 0)
2474 return false;
d1ed6aa1 2475
d1ed6aa1 2476 sent--;
5271edd4
CH		 2477 if (nr_queues)
2478 goto retry;
2479 }
2480 return true;
a5768aa8
KB		 2481}
2482
7d879c90 2483static void nvme_delete_io_queues(struct nvme_dev *dev)
b60503ba 2484{
7d879c90
CH		 2485 if (__nvme_delete_io_queues(dev, nvme_admin_delete_sq))
2486 __nvme_delete_io_queues(dev, nvme_admin_delete_cq);
2487}
2b1b7e78 2488
0da7feaa 2489static unsigned int nvme_pci_nr_maps(struct nvme_dev *dev)
b60503ba 2490{
2455a4b7 2491 if (dev->io_queues[HCTX_TYPE_POLL])
0da7feaa
CH		 2492 return 3;
2493 if (dev->io_queues[HCTX_TYPE_READ])
2494 return 2;
2495 return 1;
2455a4b7 2496}
949928c1 2497
2455a4b7
CH		 2498static void nvme_pci_update_nr_queues(struct nvme_dev *dev)
2499{
2500 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2501 /* free previously allocated queues that are no longer usable */
2502 nvme_free_queues(dev, dev->online_queues);
b60503ba
MW		 2503}
2504
b00a726a 2505static int nvme_pci_enable(struct nvme_dev *dev)
0877cb0d 2506{
b00a726a 2507 int result = -ENOMEM;
e75ec752 2508 struct pci_dev *pdev = to_pci_dev(dev->dev);
4bdf2603 2509 int dma_address_bits = 64;
0877cb0d
KB		 2510
2511 if (pci_enable_device_mem(pdev))
2512 return result;
2513
0877cb0d 2514 pci_set_master(pdev);
0877cb0d 2515
4bdf2603
FS		 2516 if (dev->ctrl.quirks & NVME_QUIRK_DMA_ADDRESS_BITS_48)
2517 dma_address_bits = 48;
2518 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(dma_address_bits)))
052d0efa 2519 goto disable;
0877cb0d 2520
7a67cbea 2521 if (readl(dev->bar + NVME_REG_CSTS) == -1) {
0e53d180 2522 result = -ENODEV;
b00a726a 2523 goto disable;
0e53d180 2524 }
e32efbfc
JA		 2525
2526 /*
a5229050
KB		 2527 * Some devices and/or platforms don't advertise or work with INTx
2528 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2529 * adjust this later.
e32efbfc 2530 */
dca51e78
CH		 2531 result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
2532 if (result < 0)
2533 return result;
e32efbfc 2534
20d0dfe6 2535 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
7a67cbea 2536
7442ddce 2537 dev->q_depth = min_t(u32, NVME_CAP_MQES(dev->ctrl.cap) + 1,
b27c1e68 2538 io_queue_depth);
aa22c8e6 2539 dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */
20d0dfe6 2540 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
7a67cbea 2541 dev->dbs = dev->bar + 4096;
1f390c1f 2542
66341331
BH		 2543 /*
2544 * Some Apple controllers require a non-standard SQE size.
2545 * Interestingly they also seem to ignore the CC:IOSQES register
2546 * so we don't bother updating it here.
2547 */
2548 if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES)
2549 dev->io_sqes = 7;
2550 else
2551 dev->io_sqes = NVME_NVM_IOSQES;
1f390c1f
SG		 2552
2553 /*
2554 * Temporary fix for the Apple controller found in the MacBook8,1 and
2555 * some MacBook7,1 to avoid controller resets and data loss.
2556 */
2557 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
2558 dev->q_depth = 2;
9bdcfb10
CH		 2559 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
2560 "set queue depth=%u to work around controller resets\n",
1f390c1f 2561 dev->q_depth);
d554b5e1
MP		 2562 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2563 (pdev->device == 0xa821 || pdev->device == 0xa822) &&
20d0dfe6 2564 NVME_CAP_MQES(dev->ctrl.cap) == 0) {
d554b5e1
MP		 2565 dev->q_depth = 64;
2566 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2567 "set queue depth=%u\n", dev->q_depth);
1f390c1f
SG		 2568 }
2569
d38e9f04
BH		 2570 /*
2571 * Controllers with the shared tags quirk need the IO queue to be
2572 * big enough so that we get 32 tags for the admin queue
2573 */
2574 if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) &&
2575 (dev->q_depth < (NVME_AQ_DEPTH + 2))) {
2576 dev->q_depth = NVME_AQ_DEPTH + 2;
2577 dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n",
2578 dev->q_depth);
2579 }
2580
2581
f65efd6d 2582 nvme_map_cmb(dev);
202021c1 2583
a0a3408e
KB		 2584 pci_enable_pcie_error_reporting(pdev);
2585 pci_save_state(pdev);
a6ee7f19
CH		 2586
2587 return nvme_pci_configure_admin_queue(dev);
0877cb0d
KB		 2588
2589 disable:
0877cb0d
KB		 2590 pci_disable_device(pdev);
2591 return result;
2592}
2593
2594static void nvme_dev_unmap(struct nvme_dev *dev)
b00a726a
KB		 2595{
2596 if (dev->bar)
2597 iounmap(dev->bar);
a1f447b3 2598 pci_release_mem_regions(to_pci_dev(dev->dev));
b00a726a
KB		 2599}
2600
68e81eba 2601static bool nvme_pci_ctrl_is_dead(struct nvme_dev *dev)
0877cb0d 2602{
e75ec752 2603 struct pci_dev *pdev = to_pci_dev(dev->dev);
68e81eba 2604 u32 csts;
e75ec752 2605
68e81eba
CH		 2606 if (!pci_is_enabled(pdev) || !pci_device_is_present(pdev))
2607 return true;
2608 if (pdev->error_state != pci_channel_io_normal)
2609 return true;
0877cb0d 2610
68e81eba
CH		 2611 csts = readl(dev->bar + NVME_REG_CSTS);
2612 return (csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY);
4d115420
KB		 2613}
2614
a5cdb68c 2615static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
b60503ba 2616{
302ad8cc 2617 struct pci_dev *pdev = to_pci_dev(dev->dev);
68e81eba 2618 bool dead;
22404274 2619
77bf25ea 2620 mutex_lock(&dev->shutdown_lock);
68e81eba
CH		 2621 dead = nvme_pci_ctrl_is_dead(dev);
2622 if (dev->ctrl.state == NVME_CTRL_LIVE ||
2623 dev->ctrl.state == NVME_CTRL_RESETTING) {
2624 if (pci_is_enabled(pdev))
302ad8cc 2625 nvme_start_freeze(&dev->ctrl);
68e81eba
CH		 2626 /*
2627 * Give the controller a chance to complete all entered requests
2628 * if doing a safe shutdown.
2629 */
2630 if (!dead && shutdown)
2631 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
c9d3bf88 2632 }
c21377f8 2633
9f27bd70 2634 nvme_quiesce_io_queues(&dev->ctrl);
87ad72a5 2635
64ee0ac0 2636 if (!dead && dev->ctrl.queue_count > 0) {
7d879c90 2637 nvme_delete_io_queues(dev);
47d42d22
CH		 2638 nvme_disable_ctrl(&dev->ctrl, shutdown);
2639 nvme_poll_irqdisable(&dev->queues[0]);
4d115420 2640 }
8fae268b 2641 nvme_suspend_io_queues(dev);
10981f23 2642 nvme_suspend_queue(dev, 0);
c80767f7
CH		 2643 pci_free_irq_vectors(pdev);
2644 if (pci_is_enabled(pdev)) {
2645 pci_disable_pcie_error_reporting(pdev);
2646 pci_disable_device(pdev);
2647 }
fa46c6fb 2648 nvme_reap_pending_cqes(dev);
07836e65 2649
1fcfca78
GL		 2650 nvme_cancel_tagset(&dev->ctrl);
2651 nvme_cancel_admin_tagset(&dev->ctrl);
302ad8cc
KB		 2652
2653 /*
2654 * The driver will not be starting up queues again if shutting down so
2655 * must flush all entered requests to their failed completion to avoid
2656 * deadlocking blk-mq hot-cpu notifier.
2657 */
c8e9e9b7 2658 if (shutdown) {
9f27bd70 2659 nvme_unquiesce_io_queues(&dev->ctrl);
c8e9e9b7 2660 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q))
9f27bd70 2661 nvme_unquiesce_admin_queue(&dev->ctrl);
c8e9e9b7 2662 }
77bf25ea 2663 mutex_unlock(&dev->shutdown_lock);
b60503ba
MW		 2664}
2665
c1ac9a4b
KB		 2666static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown)
2667{
2668 if (!nvme_wait_reset(&dev->ctrl))
2669 return -EBUSY;
2670 nvme_dev_disable(dev, shutdown);
2671 return 0;
2672}
2673
091b6092
MW		 2674static int nvme_setup_prp_pools(struct nvme_dev *dev)
2675{
e75ec752 2676 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
c61b82c7
CH		 2677 NVME_CTRL_PAGE_SIZE,
2678 NVME_CTRL_PAGE_SIZE, 0);
091b6092
MW		 2679 if (!dev->prp_page_pool)
2680 return -ENOMEM;
2681
99802a7a 2682 /* Optimisation for I/Os between 4k and 128k */
e75ec752 2683 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
99802a7a
MW		 2684 256, 256, 0);
2685 if (!dev->prp_small_pool) {
2686 dma_pool_destroy(dev->prp_page_pool);
2687 return -ENOMEM;
2688 }
091b6092
MW		 2689 return 0;
2690}
2691
2692static void nvme_release_prp_pools(struct nvme_dev *dev)
2693{
2694 dma_pool_destroy(dev->prp_page_pool);
99802a7a 2695 dma_pool_destroy(dev->prp_small_pool);
091b6092
MW		 2696}
2697
081a7d95
CH		 2698static int nvme_pci_alloc_iod_mempool(struct nvme_dev *dev)
2699{
2700 size_t npages = max(nvme_pci_npages_prp(), nvme_pci_npages_sgl());
2701 size_t alloc_size = sizeof(__le64 *) * npages +
2702 sizeof(struct scatterlist) * NVME_MAX_SEGS;
2703
2704 WARN_ON_ONCE(alloc_size > PAGE_SIZE);
2705 dev->iod_mempool = mempool_create_node(1,
2706 mempool_kmalloc, mempool_kfree,
2707 (void *)alloc_size, GFP_KERNEL,
2708 dev_to_node(dev->dev));
2709 if (!dev->iod_mempool)
2710 return -ENOMEM;
2711 return 0;
2712}
2713
770597ec
KB		 2714static void nvme_free_tagset(struct nvme_dev *dev)
2715{
2716 if (dev->tagset.tags)
0da7feaa 2717 nvme_remove_io_tag_set(&dev->ctrl);
770597ec
KB		 2718 dev->ctrl.tagset = NULL;
2719}
2720
2e87570b 2721/* pairs with nvme_pci_alloc_dev */
1673f1f0 2722static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
5e82e952 2723{
1673f1f0 2724 struct nvme_dev *dev = to_nvme_dev(ctrl);
9ac27090 2725
770597ec 2726 nvme_free_tagset(dev);
253fd4ac
IR		 2727 put_device(dev->dev);
2728 kfree(dev->queues);
5e82e952
KB		 2729 kfree(dev);
2730}
2731
fd634f41 2732static void nvme_reset_work(struct work_struct *work)
5e82e952 2733{
d86c4d8e
CH		 2734 struct nvme_dev *dev =
2735 container_of(work, struct nvme_dev, ctrl.reset_work);
a98e58e5 2736 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
e71afda4 2737 int result;
5e82e952 2738
7764656b
ZC		 2739 if (dev->ctrl.state != NVME_CTRL_RESETTING) {
2740 dev_warn(dev->ctrl.device, "ctrl state %d is not RESETTING\n",
2741 dev->ctrl.state);
8cb9f10b 2742 return;
e71afda4 2743 }
5e82e952 2744
fd634f41
CH		 2745 /*
2746 * If we're called to reset a live controller first shut it down before
2747 * moving on.
2748 */
b00a726a 2749 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
a5cdb68c 2750 nvme_dev_disable(dev, false);
d6135c3a 2751 nvme_sync_queues(&dev->ctrl);
5e82e952 2752
5c959d73 2753 mutex_lock(&dev->shutdown_lock);
b00a726a 2754 result = nvme_pci_enable(dev);
f0b50732 2755 if (result)
4726bcf3 2756 goto out_unlock;
9f27bd70 2757 nvme_unquiesce_admin_queue(&dev->ctrl);
5c959d73
KB		 2758 mutex_unlock(&dev->shutdown_lock);
2759
2760 /*
2761 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
2762 * initializing procedure here.
2763 */
2764 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
2765 dev_warn(dev->ctrl.device,
2766 "failed to mark controller CONNECTING\n");
cee6c269 2767 result = -EBUSY;
5c959d73
KB		 2768 goto out;
2769 }
943e942e 2770
94cc781f 2771 result = nvme_init_ctrl_finish(&dev->ctrl, was_suspend);
ce4541f4 2772 if (result)
f58944e2 2773 goto out;
ce4541f4 2774
65a54646 2775 nvme_dbbuf_dma_alloc(dev);
f9f38e33 2776
acb71e53
CH		 2777 result = nvme_setup_host_mem(dev);
2778 if (result < 0)
2779 goto out;
87ad72a5 2780
f0b50732 2781 result = nvme_setup_io_queues(dev);
badc34d4 2782 if (result)
f58944e2 2783 goto out;
f0b50732 2784
2659e57b 2785 /*
eac3ef26
CH		 2786 * Freeze and update the number of I/O queues as thos might have
2787 * changed. If there are no I/O queues left after this reset, keep the
2788 * controller around but remove all namespaces.
2659e57b 2789 */
eac3ef26 2790 if (dev->online_queues > 1) {
9f27bd70 2791 nvme_unquiesce_io_queues(&dev->ctrl);
302ad8cc 2792 nvme_wait_freeze(&dev->ctrl);
eac3ef26 2793 nvme_pci_update_nr_queues(dev);
2455a4b7 2794 nvme_dbbuf_set(dev);
302ad8cc 2795 nvme_unfreeze(&dev->ctrl);
3cf519b5 2796 } else {
eac3ef26
CH		 2797 dev_warn(dev->ctrl.device, "IO queues lost\n");
2798 nvme_mark_namespaces_dead(&dev->ctrl);
9f27bd70 2799 nvme_unquiesce_io_queues(&dev->ctrl);
eac3ef26
CH		 2800 nvme_remove_namespaces(&dev->ctrl);
2801 nvme_free_tagset(dev);
3cf519b5
CH		 2802 }
2803
2b1b7e78
JW		 2804 /*
2805 * If only admin queue live, keep it to do further investigation or
2806 * recovery.
2807 */
5d02a5c1 2808 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
2b1b7e78 2809 dev_warn(dev->ctrl.device,
5d02a5c1 2810 "failed to mark controller live state\n");
e71afda4 2811 result = -ENODEV;
bb8d261e
CH		 2812 goto out;
2813 }
92911a55 2814
d09f2b45 2815 nvme_start_ctrl(&dev->ctrl);
3cf519b5 2816 return;
f0b50732 2817
4726bcf3
KB		 2818 out_unlock:
2819 mutex_unlock(&dev->shutdown_lock);
3cf519b5 2820 out:
c7c16c5b
CH		 2821 /*
2822 * Set state to deleting now to avoid blocking nvme_wait_reset(), which
2823 * may be holding this pci_dev's device lock.
2824 */
2825 dev_warn(dev->ctrl.device, "Disabling device after reset failure: %d\n",
2826 result);
2827 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
2828 nvme_dev_disable(dev, true);
2829 nvme_mark_namespaces_dead(&dev->ctrl);
2830 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
9a6b9458
KB		 2831}
2832
1c63dc66 2833static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
9ca97374 2834{
1c63dc66 2835 *val = readl(to_nvme_dev(ctrl)->bar + off);
90667892 2836 return 0;
9ca97374
TH		 2837}
2838
5fd4ce1b 2839static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
4cc06521 2840{
5fd4ce1b
CH		 2841 writel(val, to_nvme_dev(ctrl)->bar + off);
2842 return 0;
2843}
4cc06521 2844
7fd8930f
CH		 2845static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2846{
3a8ecc93 2847 *val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off);
7fd8930f 2848 return 0;
4cc06521
KB		 2849}
2850
97c12223
KB		 2851static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
2852{
2853 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2854
2db24e4a 2855 return snprintf(buf, size, "%s\n", dev_name(&pdev->dev));
97c12223
KB		 2856}
2857
2f0dad17
KB		 2858static void nvme_pci_print_device_info(struct nvme_ctrl *ctrl)
2859{
2860 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2861 struct nvme_subsystem *subsys = ctrl->subsys;
2862
2863 dev_err(ctrl->device,
2864 "VID:DID %04x:%04x model:%.*s firmware:%.*s\n",
2865 pdev->vendor, pdev->device,
2866 nvme_strlen(subsys->model, sizeof(subsys->model)),
2867 subsys->model, nvme_strlen(subsys->firmware_rev,
2868 sizeof(subsys->firmware_rev)),
2869 subsys->firmware_rev);
2870}
2871
2f859441
LG		 2872static bool nvme_pci_supports_pci_p2pdma(struct nvme_ctrl *ctrl)
2873{
2874 struct nvme_dev *dev = to_nvme_dev(ctrl);
2875
2876 return dma_pci_p2pdma_supported(dev->dev);
2877}
2878
1c63dc66 2879static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
1a353d85 2880 .name = "pcie",
e439bb12 2881 .module = THIS_MODULE,
2f859441 2882 .flags = NVME_F_METADATA_SUPPORTED,
86adbf0c 2883 .dev_attr_groups = nvme_pci_dev_attr_groups,
1c63dc66 2884 .reg_read32 = nvme_pci_reg_read32,
5fd4ce1b 2885 .reg_write32 = nvme_pci_reg_write32,
7fd8930f 2886 .reg_read64 = nvme_pci_reg_read64,
1673f1f0 2887 .free_ctrl = nvme_pci_free_ctrl,
f866fc42 2888 .submit_async_event = nvme_pci_submit_async_event,
97c12223 2889 .get_address = nvme_pci_get_address,
2f0dad17 2890 .print_device_info = nvme_pci_print_device_info,
2f859441 2891 .supports_pci_p2pdma = nvme_pci_supports_pci_p2pdma,
1c63dc66 2892};
4cc06521 2893
b00a726a
KB		 2894static int nvme_dev_map(struct nvme_dev *dev)
2895{
b00a726a
KB		 2896 struct pci_dev *pdev = to_pci_dev(dev->dev);
2897
a1f447b3 2898 if (pci_request_mem_regions(pdev, "nvme"))
b00a726a
KB		 2899 return -ENODEV;
2900
97f6ef64 2901 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
b00a726a
KB		 2902 goto release;
2903
9fa196e7 2904 return 0;
b00a726a 2905 release:
9fa196e7
MG		 2906 pci_release_mem_regions(pdev);
2907 return -ENODEV;
b00a726a
KB		 2908}
2909
8427bbc2 2910static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
ff5350a8
AL		 2911{
2912 if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
2913 /*
2914 * Several Samsung devices seem to drop off the PCIe bus
2915 * randomly when APST is on and uses the deepest sleep state.
2916 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2917 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2918 * 950 PRO 256GB", but it seems to be restricted to two Dell
2919 * laptops.
2920 */
2921 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
2922 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
2923 dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
2924 return NVME_QUIRK_NO_DEEPEST_PS;
8427bbc2
KHF		 2925 } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
2926 /*
2927 * Samsung SSD 960 EVO drops off the PCIe bus after system
467c77d4
JJ		 2928 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
2929 * within few minutes after bootup on a Coffee Lake board -
2930 * ASUS PRIME Z370-A
8427bbc2
KHF		 2931 */
2932 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
467c77d4
JJ		 2933 (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") ||
2934 dmi_match(DMI_BOARD_NAME, "PRIME Z370-A")))
8427bbc2 2935 return NVME_QUIRK_NO_APST;
1fae37ac
S		 2936 } else if ((pdev->vendor == 0x144d && (pdev->device == 0xa801 ||
2937 pdev->device == 0xa808 || pdev->device == 0xa809)) ||
2938 (pdev->vendor == 0x1e0f && pdev->device == 0x0001)) {
2939 /*
2940 * Forcing to use host managed nvme power settings for
2941 * lowest idle power with quick resume latency on
2942 * Samsung and Toshiba SSDs based on suspend behavior
2943 * on Coffee Lake board for LENOVO C640
2944 */
2945 if ((dmi_match(DMI_BOARD_VENDOR, "LENOVO")) &&
2946 dmi_match(DMI_BOARD_NAME, "LNVNB161216"))
2947 return NVME_QUIRK_SIMPLE_SUSPEND;
ff5350a8
AL		 2948 }
2949
2950 return 0;
2951}
2952
2e87570b
CH		 2953static struct nvme_dev *nvme_pci_alloc_dev(struct pci_dev *pdev,
2954 const struct pci_device_id *id)
18119775 2955{
ff5350a8 2956 unsigned long quirks = id->driver_data;
2e87570b
CH		 2957 int node = dev_to_node(&pdev->dev);
2958 struct nvme_dev *dev;
2959 int ret = -ENOMEM;
b60503ba 2960
a4aea562 2961 if (node == NUMA_NO_NODE)
2fa84351 2962 set_dev_node(&pdev->dev, first_memory_node);
a4aea562
MB		 2963
2964 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
b60503ba 2965 if (!dev)
2e87570b
CH		 2966 return NULL;
2967 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
2e87570b 2968 mutex_init(&dev->shutdown_lock);
147b27e4 2969
2a5bcfdd
WZ		 2970 dev->nr_write_queues = write_queues;
2971 dev->nr_poll_queues = poll_queues;
2972 dev->nr_allocated_queues = nvme_max_io_queues(dev) + 1;
2973 dev->queues = kcalloc_node(dev->nr_allocated_queues,
2974 sizeof(struct nvme_queue), GFP_KERNEL, node);
b60503ba 2975 if (!dev->queues)
2e87570b 2976 goto out_free_dev;
b60503ba 2977
e75ec752 2978 dev->dev = get_device(&pdev->dev);
4cc06521 2979
8427bbc2 2980 quirks |= check_vendor_combination_bug(pdev);
2744d7a0 2981 if (!noacpi && acpi_storage_d3(&pdev->dev)) {
df4f9bc4
DB		 2982 /*
2983 * Some systems use a bios work around to ask for D3 on
2984 * platforms that support kernel managed suspend.
2985 */
2986 dev_info(&pdev->dev,
2987 "platform quirk: setting simple suspend\n");
2988 quirks |= NVME_QUIRK_SIMPLE_SUSPEND;
2989 }
2e87570b
CH		 2990 ret = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
2991 quirks);
2992 if (ret)
2993 goto out_put_device;
3f30a79c
CH		 2994
2995 dma_set_min_align_mask(&pdev->dev, NVME_CTRL_PAGE_SIZE - 1);
2996 dma_set_max_seg_size(&pdev->dev, 0xffffffff);
df4f9bc4 2997
943e942e 2998 /*
3f30a79c
CH		 2999 * Limit the max command size to prevent iod->sg allocations going
3000 * over a single page.
943e942e 3001 */
3f30a79c
CH		 3002 dev->ctrl.max_hw_sectors = min_t(u32,
3003 NVME_MAX_KB_SZ << 1, dma_max_mapping_size(&pdev->dev) >> 9);
3004 dev->ctrl.max_segments = NVME_MAX_SEGS;
943e942e 3005
3f30a79c
CH		 3006 /*
3007 * There is no support for SGLs for metadata (yet), so we are limited to
3008 * a single integrity segment for the separate metadata pointer.
3009 */
3010 dev->ctrl.max_integrity_segments = 1;
2e87570b 3011 return dev;
df4f9bc4 3012
2e87570b
CH		 3013out_put_device:
3014 put_device(dev->dev);
3015 kfree(dev->queues);
3016out_free_dev:
3017 kfree(dev);
3018 return ERR_PTR(ret);
3019}
943e942e 3020
2e87570b
CH		 3021static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
3022{
3023 struct nvme_dev *dev;
3024 int result = -ENOMEM;
3025
3026 dev = nvme_pci_alloc_dev(pdev, id);
3027 if (!dev)
3028 return -ENOMEM;
3029
3030 result = nvme_dev_map(dev);
b6e44b4c 3031 if (result)
2e87570b
CH		 3032 goto out_uninit_ctrl;
3033
3034 result = nvme_setup_prp_pools(dev);
081a7d95 3035 if (result)
2e87570b 3036 goto out_dev_unmap;
943e942e 3037
2e87570b 3038 result = nvme_pci_alloc_iod_mempool(dev);
b6e44b4c 3039 if (result)
2e87570b 3040 goto out_release_prp_pools;
b6e44b4c 3041
1b3c47c1
SG		 3042 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
3043
eac3ef26
CH		 3044 result = nvme_pci_enable(dev);
3045 if (result)
3046 goto out_release_iod_mempool;
3047
0da7feaa
CH		 3048 result = nvme_alloc_admin_tag_set(&dev->ctrl, &dev->admin_tagset,
3049 &nvme_mq_admin_ops, sizeof(struct nvme_iod));
eac3ef26
CH		 3050 if (result)
3051 goto out_disable;
3052
3053 /*
3054 * Mark the controller as connecting before sending admin commands to
3055 * allow the timeout handler to do the right thing.
3056 */
3057 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
3058 dev_warn(dev->ctrl.device,
3059 "failed to mark controller CONNECTING\n");
3060 result = -EBUSY;
3061 goto out_disable;
3062 }
3063
3064 result = nvme_init_ctrl_finish(&dev->ctrl, false);
3065 if (result)
3066 goto out_disable;
3067
3068 nvme_dbbuf_dma_alloc(dev);
3069
3070 result = nvme_setup_host_mem(dev);
3071 if (result < 0)
3072 goto out_disable;
3073
3074 result = nvme_setup_io_queues(dev);
3075 if (result)
3076 goto out_disable;
4caff8fc 3077
eac3ef26 3078 if (dev->online_queues > 1) {
0da7feaa
CH		 3079 nvme_alloc_io_tag_set(&dev->ctrl, &dev->tagset, &nvme_mq_ops,
3080 nvme_pci_nr_maps(dev), sizeof(struct nvme_iod));
eac3ef26 3081 nvme_dbbuf_set(dev);
eac3ef26
CH		 3082 }
3083
0da7feaa
CH		 3084 if (!dev->ctrl.tagset)
3085 dev_warn(dev->ctrl.device, "IO queues not created\n");
3086
eac3ef26
CH		 3087 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
3088 dev_warn(dev->ctrl.device,
3089 "failed to mark controller live state\n");
3090 result = -ENODEV;
3091 goto out_disable;
3092 }
3093
2e87570b 3094 pci_set_drvdata(pdev, dev);
1b3c47c1 3095
eac3ef26
CH		 3096 nvme_start_ctrl(&dev->ctrl);
3097 nvme_put_ctrl(&dev->ctrl);
b60503ba
MW		 3098 return 0;
3099
eac3ef26
CH		 3100out_disable:
3101 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
3102 nvme_dev_disable(dev, true);
3103 nvme_free_host_mem(dev);
3104 nvme_dev_remove_admin(dev);
3105 nvme_dbbuf_dma_free(dev);
3106 nvme_free_queues(dev, 0);
3107out_release_iod_mempool:
b6e44b4c 3108 mempool_destroy(dev->iod_mempool);
2e87570b 3109out_release_prp_pools:
091b6092 3110 nvme_release_prp_pools(dev);
2e87570b 3111out_dev_unmap:
b00c9b7a 3112 nvme_dev_unmap(dev);
2e87570b
CH		 3113out_uninit_ctrl:
3114 nvme_uninit_ctrl(&dev->ctrl);
b60503ba
MW		 3115 return result;
3116}
3117
775755ed 3118static void nvme_reset_prepare(struct pci_dev *pdev)
f0d54a54 3119{
a6739479 3120 struct nvme_dev *dev = pci_get_drvdata(pdev);
c1ac9a4b
KB		 3121
3122 /*
3123 * We don't need to check the return value from waiting for the reset
3124 * state as pci_dev device lock is held, making it impossible to race
3125 * with ->remove().
3126 */
3127 nvme_disable_prepare_reset(dev, false);
3128 nvme_sync_queues(&dev->ctrl);
775755ed 3129}
f0d54a54 3130
775755ed
CH		 3131static void nvme_reset_done(struct pci_dev *pdev)
3132{
f263fbb8 3133 struct nvme_dev *dev = pci_get_drvdata(pdev);
c1ac9a4b
KB		 3134
3135 if (!nvme_try_sched_reset(&dev->ctrl))
3136 flush_work(&dev->ctrl.reset_work);
f0d54a54
KB		 3137}
3138
09ece142
KB		 3139static void nvme_shutdown(struct pci_dev *pdev)
3140{
3141 struct nvme_dev *dev = pci_get_drvdata(pdev);
4e523547 3142
c1ac9a4b 3143 nvme_disable_prepare_reset(dev, true);
09ece142
KB		 3144}
3145
f58944e2
KB		 3146/*
3147 * The driver's remove may be called on a device in a partially initialized
3148 * state. This function must not have any dependencies on the device state in
3149 * order to proceed.
3150 */
8d85fce7 3151static void nvme_remove(struct pci_dev *pdev)
b60503ba
MW		 3152{
3153 struct nvme_dev *dev = pci_get_drvdata(pdev);
9a6b9458 3154
bb8d261e 3155 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
9a6b9458 3156 pci_set_drvdata(pdev, NULL);
0ff9d4e1 3157
6db28eda 3158 if (!pci_device_is_present(pdev)) {
0ff9d4e1 3159 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
1d39e692 3160 nvme_dev_disable(dev, true);
6db28eda 3161 }
0ff9d4e1 3162
d86c4d8e 3163 flush_work(&dev->ctrl.reset_work);
d09f2b45
SG		 3164 nvme_stop_ctrl(&dev->ctrl);
3165 nvme_remove_namespaces(&dev->ctrl);
a5cdb68c 3166 nvme_dev_disable(dev, true);
87ad72a5 3167 nvme_free_host_mem(dev);
a4aea562 3168 nvme_dev_remove_admin(dev);
c11b7716 3169 nvme_dbbuf_dma_free(dev);
a1a5ef99 3170 nvme_free_queues(dev, 0);
c11b7716 3171 mempool_destroy(dev->iod_mempool);
9a6b9458 3172 nvme_release_prp_pools(dev);
b00a726a 3173 nvme_dev_unmap(dev);
726612b6 3174 nvme_uninit_ctrl(&dev->ctrl);
b60503ba
MW		 3175}
3176
671a6018 3177#ifdef CONFIG_PM_SLEEP
d916b1be
KB		 3178static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps)
3179{
3180 return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps);
3181}
3182
3183static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps)
3184{
3185 return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL);
3186}
3187
3188static int nvme_resume(struct device *dev)
3189{
3190 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
3191 struct nvme_ctrl *ctrl = &ndev->ctrl;
3192
4eaefe8c 3193 if (ndev->last_ps == U32_MAX ||
d916b1be 3194 nvme_set_power_state(ctrl, ndev->last_ps) != 0)
e5ad96f3
KB		 3195 goto reset;
3196 if (ctrl->hmpre && nvme_setup_host_mem(ndev))
3197 goto reset;
3198
d916b1be 3199 return 0;
e5ad96f3
KB		 3200reset:
3201 return nvme_try_sched_reset(ctrl);
d916b1be
KB		 3202}
3203
cd638946
KB		 3204static int nvme_suspend(struct device *dev)
3205{
3206 struct pci_dev *pdev = to_pci_dev(dev);
3207 struct nvme_dev *ndev = pci_get_drvdata(pdev);
d916b1be
KB		 3208 struct nvme_ctrl *ctrl = &ndev->ctrl;
3209 int ret = -EBUSY;
3210
4eaefe8c
RW		 3211 ndev->last_ps = U32_MAX;
3212
d916b1be
KB		 3213 /*
3214 * The platform does not remove power for a kernel managed suspend so
3215 * use host managed nvme power settings for lowest idle power if
3216 * possible. This should have quicker resume latency than a full device
3217 * shutdown. But if the firmware is involved after the suspend or the
3218 * device does not support any non-default power states, shut down the
3219 * device fully.
4eaefe8c
RW		 3220 *
3221 * If ASPM is not enabled for the device, shut down the device and allow
3222 * the PCI bus layer to put it into D3 in order to take the PCIe link
3223 * down, so as to allow the platform to achieve its minimum low-power
3224 * state (which may not be possible if the link is up).
d916b1be 3225 */
4eaefe8c 3226 if (pm_suspend_via_firmware() || !ctrl->npss ||
cb32de1b 3227 !pcie_aspm_enabled(pdev) ||
c1ac9a4b
KB		 3228 (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND))
3229 return nvme_disable_prepare_reset(ndev, true);
d916b1be
KB		 3230
3231 nvme_start_freeze(ctrl);
3232 nvme_wait_freeze(ctrl);
3233 nvme_sync_queues(ctrl);
3234
5d02a5c1 3235 if (ctrl->state != NVME_CTRL_LIVE)
d916b1be
KB		 3236 goto unfreeze;
3237
e5ad96f3
KB		 3238 /*
3239 * Host memory access may not be successful in a system suspend state,
3240 * but the specification allows the controller to access memory in a
3241 * non-operational power state.
3242 */
3243 if (ndev->hmb) {
3244 ret = nvme_set_host_mem(ndev, 0);
3245 if (ret < 0)
3246 goto unfreeze;
3247 }
3248
d916b1be
KB		 3249 ret = nvme_get_power_state(ctrl, &ndev->last_ps);
3250 if (ret < 0)
3251 goto unfreeze;
3252
7cbb5c6f
ML		 3253 /*
3254 * A saved state prevents pci pm from generically controlling the
3255 * device's power. If we're using protocol specific settings, we don't
3256 * want pci interfering.
3257 */
3258 pci_save_state(pdev);
3259
d916b1be
KB		 3260 ret = nvme_set_power_state(ctrl, ctrl->npss);
3261 if (ret < 0)
3262 goto unfreeze;
3263
3264 if (ret) {
7cbb5c6f
ML		 3265 /* discard the saved state */
3266 pci_load_saved_state(pdev, NULL);
3267
d916b1be
KB		 3268 /*
3269 * Clearing npss forces a controller reset on resume. The
05d3046f 3270 * correct value will be rediscovered then.
d916b1be 3271 */
c1ac9a4b 3272 ret = nvme_disable_prepare_reset(ndev, true);
d916b1be 3273 ctrl->npss = 0;
d916b1be 3274 }
d916b1be
KB		 3275unfreeze:
3276 nvme_unfreeze(ctrl);
3277 return ret;
3278}
3279
3280static int nvme_simple_suspend(struct device *dev)
3281{
3282 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
4e523547 3283
c1ac9a4b 3284 return nvme_disable_prepare_reset(ndev, true);
cd638946
KB		 3285}
3286
d916b1be 3287static int nvme_simple_resume(struct device *dev)
cd638946
KB		 3288{
3289 struct pci_dev *pdev = to_pci_dev(dev);
3290 struct nvme_dev *ndev = pci_get_drvdata(pdev);
cd638946 3291
c1ac9a4b 3292 return nvme_try_sched_reset(&ndev->ctrl);
cd638946
KB		 3293}
3294
21774222 3295static const struct dev_pm_ops nvme_dev_pm_ops = {
d916b1be
KB		 3296 .suspend = nvme_suspend,
3297 .resume = nvme_resume,
3298 .freeze = nvme_simple_suspend,
3299 .thaw = nvme_simple_resume,
3300 .poweroff = nvme_simple_suspend,
3301 .restore = nvme_simple_resume,
3302};
3303#endif /* CONFIG_PM_SLEEP */
b60503ba 3304
a0a3408e
KB		 3305static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
3306 pci_channel_state_t state)
3307{
3308 struct nvme_dev *dev = pci_get_drvdata(pdev);
3309
3310 /*
3311 * A frozen channel requires a reset. When detected, this method will
3312 * shutdown the controller to quiesce. The controller will be restarted
3313 * after the slot reset through driver's slot_reset callback.
3314 */
a0a3408e
KB		 3315 switch (state) {
3316 case pci_channel_io_normal:
3317 return PCI_ERS_RESULT_CAN_RECOVER;
3318 case pci_channel_io_frozen:
d011fb31
KB		 3319 dev_warn(dev->ctrl.device,
3320 "frozen state error detected, reset controller\n");
a5cdb68c 3321 nvme_dev_disable(dev, false);
a0a3408e
KB		 3322 return PCI_ERS_RESULT_NEED_RESET;
3323 case pci_channel_io_perm_failure:
d011fb31
KB		 3324 dev_warn(dev->ctrl.device,
3325 "failure state error detected, request disconnect\n");
a0a3408e
KB		 3326 return PCI_ERS_RESULT_DISCONNECT;
3327 }
3328 return PCI_ERS_RESULT_NEED_RESET;
3329}
3330
3331static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
3332{
3333 struct nvme_dev *dev = pci_get_drvdata(pdev);
3334
1b3c47c1 3335 dev_info(dev->ctrl.device, "restart after slot reset\n");
a0a3408e 3336 pci_restore_state(pdev);
d86c4d8e 3337 nvme_reset_ctrl(&dev->ctrl);
a0a3408e
KB		 3338 return PCI_ERS_RESULT_RECOVERED;
3339}
3340
3341static void nvme_error_resume(struct pci_dev *pdev)
3342{
72cd4cc2
KB		 3343 struct nvme_dev *dev = pci_get_drvdata(pdev);
3344
3345 flush_work(&dev->ctrl.reset_work);
a0a3408e
KB		 3346}
3347
1d352035 3348static const struct pci_error_handlers nvme_err_handler = {
b60503ba 3349 .error_detected = nvme_error_detected,
b60503ba
MW		 3350 .slot_reset = nvme_slot_reset,
3351 .resume = nvme_error_resume,
775755ed
CH		 3352 .reset_prepare = nvme_reset_prepare,
3353 .reset_done = nvme_reset_done,
b60503ba
MW		 3354};
3355
6eb0d698 3356static const struct pci_device_id nvme_id_table[] = {
972b13e2 3357 { PCI_VDEVICE(INTEL, 0x0953), /* Intel 750/P3500/P3600/P3700 */
08095e70 3358 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 3359 NVME_QUIRK_DEALLOCATE_ZEROES, },
972b13e2 3360 { PCI_VDEVICE(INTEL, 0x0a53), /* Intel P3520 */
99466e70 3361 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 3362 NVME_QUIRK_DEALLOCATE_ZEROES, },
972b13e2 3363 { PCI_VDEVICE(INTEL, 0x0a54), /* Intel P4500/P4600 */
99466e70 3364 .driver_data = NVME_QUIRK_STRIPE_SIZE |
25e58af4
WZ		 3365 NVME_QUIRK_DEALLOCATE_ZEROES |
3366 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
972b13e2 3367 { PCI_VDEVICE(INTEL, 0x0a55), /* Dell Express Flash P4600 */
f99cb7af
DWF		 3368 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3369 NVME_QUIRK_DEALLOCATE_ZEROES, },
50af47d0 3370 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */
9abd68ef 3371 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
6c6aa2f2 3372 NVME_QUIRK_MEDIUM_PRIO_SQ |
ce4cc313
DM		 3373 NVME_QUIRK_NO_TEMP_THRESH_CHANGE |
3374 NVME_QUIRK_DISABLE_WRITE_ZEROES, },
6299358d
JD		 3375 { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */
3376 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
540c801c 3377 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */
7b210e4e 3378 .driver_data = NVME_QUIRK_IDENTIFY_CNS |
66dd346b
CH		 3379 NVME_QUIRK_DISABLE_WRITE_ZEROES |
3380 NVME_QUIRK_BOGUS_NID, },
3381 { PCI_VDEVICE(REDHAT, 0x0010), /* Qemu emulated controller */
3382 .driver_data = NVME_QUIRK_BOGUS_NID, },
5bedd3af 3383 { PCI_DEVICE(0x126f, 0x2263), /* Silicon Motion unidentified */
c98a8793
KB		 3384 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST |
3385 NVME_QUIRK_BOGUS_NID, },
0302ae60 3386 { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */
5e112d3f
JE		 3387 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
3388 NVME_QUIRK_NO_NS_DESC_LIST, },
54adc010
GP		 3389 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
3390 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
8c97eecc
JL		 3391 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */
3392 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
015282c9
WW		 3393 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
3394 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
d554b5e1
MP		 3395 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */
3396 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3397 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */
7ee5c78c 3398 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
abbb5f59 3399 NVME_QUIRK_DISABLE_WRITE_ZEROES|
7ee5c78c 3400 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
2cf7a77e
KB		 3401 { PCI_DEVICE(0x1987, 0x5012), /* Phison E12 */
3402 .driver_data = NVME_QUIRK_BOGUS_NID, },
c9e95c39 3403 { PCI_DEVICE(0x1987, 0x5016), /* Phison E16 */
73029c9b
KB		 3404 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN |
3405 NVME_QUIRK_BOGUS_NID, },
d14c2731
TH		 3406 { PCI_DEVICE(0x1987, 0x5019), /* phison E19 */
3407 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3408 { PCI_DEVICE(0x1987, 0x5021), /* Phison E21 */
3409 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
6e6a6828
PT		 3410 { PCI_DEVICE(0x1b4b, 0x1092), /* Lexar 256 GB SSD */
3411 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST |
3412 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
e1c70d79
LVS		 3413 { PCI_DEVICE(0x1cc1, 0x33f8), /* ADATA IM2P33F8ABR1 1 TB */
3414 .driver_data = NVME_QUIRK_BOGUS_NID, },
08b903b5 3415 { PCI_DEVICE(0x10ec, 0x5762), /* ADATA SX6000LNP */
1629de0e
PG		 3416 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN |
3417 NVME_QUIRK_BOGUS_NID, },
f03e42c6
GC		 3418 { PCI_DEVICE(0x1cc1, 0x8201), /* ADATA SX8200PNP 512GB */
3419 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3420 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
41f38043
LS		 3421 { PCI_DEVICE(0x1344, 0x5407), /* Micron Technology Inc NVMe SSD */
3422 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN },
d5ceb4d1
BH		 3423 { PCI_DEVICE(0x1344, 0x6001), /* Micron Nitro NVMe */
3424 .driver_data = NVME_QUIRK_BOGUS_NID, },
5611ec2b
KHF		 3425 { PCI_DEVICE(0x1c5c, 0x1504), /* SK Hynix PC400 */
3426 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
c4f01a77
KB		 3427 { PCI_DEVICE(0x1c5c, 0x174a), /* SK Hynix P31 SSD */
3428 .driver_data = NVME_QUIRK_BOGUS_NID, },
02ca079c
KHF		 3429 { PCI_DEVICE(0x15b7, 0x2001), /* Sandisk Skyhawk */
3430 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
89919929
CK		 3431 { PCI_DEVICE(0x1d97, 0x2263), /* SPCC */
3432 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
43047e08 3433 { PCI_DEVICE(0x144d, 0xa80b), /* Samsung PM9B1 256G and 512G */
3434 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3435 { PCI_DEVICE(0x144d, 0xa809), /* Samsung MZALQ256HBJD 256G */
3436 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3437 { PCI_DEVICE(0x1cc4, 0x6303), /* UMIS RPJTJ512MGE1QDY 512G */
3438 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3439 { PCI_DEVICE(0x1cc4, 0x6302), /* UMIS RPJTJ256MGE1QDY 256G */
3440 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
dc22c1c0
ZB		 3441 { PCI_DEVICE(0x2646, 0x2262), /* KINGSTON SKC2000 NVMe SSD */
3442 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
538e4a8c
TL		 3443 { PCI_DEVICE(0x2646, 0x2263), /* KINGSTON A2000 NVMe SSD */
3444 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
ac9b57d4
XL		 3445 { PCI_DEVICE(0x2646, 0x5018), /* KINGSTON OM8SFP4xxxxP OS21012 NVMe SSD */
3446 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3447 { PCI_DEVICE(0x2646, 0x5016), /* KINGSTON OM3PGP4xxxxP OS21011 NVMe SSD */
3448 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3449 { PCI_DEVICE(0x2646, 0x501A), /* KINGSTON OM8PGP4xxxxP OS21005 NVMe SSD */
3450 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3451 { PCI_DEVICE(0x2646, 0x501B), /* KINGSTON OM8PGP4xxxxQ OS21005 NVMe SSD */
3452 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3453 { PCI_DEVICE(0x2646, 0x501E), /* KINGSTON OM3PGP4xxxxQ OS21011 NVMe SSD */
3454 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
8d6e38f6
TDF		 3455 { PCI_DEVICE(0x1f40, 0x5236), /* Netac Technologies Co. NV7000 NVMe SSD */
3456 .driver_data = NVME_QUIRK_BOGUS_NID, },
70ce3455
CH		 3457 { PCI_DEVICE(0x1e4B, 0x1001), /* MAXIO MAP1001 */
3458 .driver_data = NVME_QUIRK_BOGUS_NID, },
a98a945b
CH		 3459 { PCI_DEVICE(0x1e4B, 0x1002), /* MAXIO MAP1002 */
3460 .driver_data = NVME_QUIRK_BOGUS_NID, },
3461 { PCI_DEVICE(0x1e4B, 0x1202), /* MAXIO MAP1202 */
3462 .driver_data = NVME_QUIRK_BOGUS_NID, },
3765fad5
SR		 3463 { PCI_DEVICE(0x1cc1, 0x5350), /* ADATA XPG GAMMIX S50 */
3464 .driver_data = NVME_QUIRK_BOGUS_NID, },
f37527a0
DK		 3465 { PCI_DEVICE(0x1dbe, 0x5236), /* ADATA XPG GAMMIX S70 */
3466 .driver_data = NVME_QUIRK_BOGUS_NID, },
d5d3c100
XR		 3467 { PCI_DEVICE(0x1e49, 0x0021), /* ZHITAI TiPro5000 NVMe SSD */
3468 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
6b961bce
NW		 3469 { PCI_DEVICE(0x1e49, 0x0041), /* ZHITAI TiPro7000 NVMe SSD */
3470 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
d6c52fa3
TG		 3471 { PCI_DEVICE(0xc0a9, 0x540a), /* Crucial P2 */
3472 .driver_data = NVME_QUIRK_BOGUS_NID, },
200dccd0
SA		 3473 { PCI_DEVICE(0x1d97, 0x2263), /* Lexar NM610 */
3474 .driver_data = NVME_QUIRK_BOGUS_NID, },
80b26240
A		 3475 { PCI_DEVICE(0x1d97, 0x2269), /* Lexar NM760 */
3476 .driver_data = NVME_QUIRK_BOGUS_NID, },
4bdf2603
FS		 3477 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0061),
3478 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3479 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0065),
3480 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3481 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x8061),
3482 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3483 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd00),
3484 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3485 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd01),
3486 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3487 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd02),
3488 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
98f7b86a
AS		 3489 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001),
3490 .driver_data = NVME_QUIRK_SINGLE_VECTOR },
124298bd 3491 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
66341331
BH		 3492 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005),
3493 .driver_data = NVME_QUIRK_SINGLE_VECTOR |
d38e9f04 3494 NVME_QUIRK_128_BYTES_SQES |
a2941f6a
KB		 3495 NVME_QUIRK_SHARED_TAGS |
3496 NVME_QUIRK_SKIP_CID_GEN },
0b85f59d 3497 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
b60503ba
MW		 3498 { 0, }
3499};
3500MODULE_DEVICE_TABLE(pci, nvme_id_table);
3501
3502static struct pci_driver nvme_driver = {
3503 .name = "nvme",
3504 .id_table = nvme_id_table,
3505 .probe = nvme_probe,
8d85fce7 3506 .remove = nvme_remove,
09ece142 3507 .shutdown = nvme_shutdown,
cd638946 3508 .driver = {
eac3ef26
CH		 3509 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
3510#ifdef CONFIG_PM_SLEEP
3511 .pm = &nvme_dev_pm_ops,
d916b1be 3512#endif
eac3ef26 3513 },
74d986ab 3514 .sriov_configure = pci_sriov_configure_simple,
b60503ba
MW		 3515 .err_handler = &nvme_err_handler,
3516};
3517
3518static int __init nvme_init(void)
3519{
81101540
CH		 3520 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
3521 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
3522 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
612b7286 3523 BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2);
c372cdd1
KB		 3524 BUILD_BUG_ON(DIV_ROUND_UP(nvme_pci_npages_prp(), NVME_CTRL_PAGE_SIZE) >
3525 S8_MAX);
17c33167 3526
9a6327d2 3527 return pci_register_driver(&nvme_driver);
b60503ba
MW		 3528}
3529
3530static void __exit nvme_exit(void)
3531{
3532 pci_unregister_driver(&nvme_driver);
03e0f3a6 3533 flush_workqueue(nvme_wq);
b60503ba
MW		 3534}
3535
3536MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3537MODULE_LICENSE("GPL");
c78b4713 3538MODULE_VERSION("1.0");
b60503ba
MW		 3539module_init(nvme_init);
3540module_exit(nvme_exit);
Linux 6.x block layer and io_uring tree(s)