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nvme: hwmon: provide temperature min and max values for each sensor
[linux-2.6-block.git] / drivers / nvme / host / pci.c
CommitLineData
5f37396d 1// SPDX-License-Identifier: GPL-2.0
b60503ba
MW		 2/*
3 * NVM Express device driver
6eb0d698 4 * Copyright (c) 2011-2014, Intel Corporation.
b60503ba
MW		 5 */
6
a0a3408e 7#include <linux/aer.h>
18119775 8#include <linux/async.h>
b60503ba 9#include <linux/blkdev.h>
a4aea562 10#include <linux/blk-mq.h>
dca51e78 11#include <linux/blk-mq-pci.h>
ff5350a8 12#include <linux/dmi.h>
b60503ba
MW		 13#include <linux/init.h>
14#include <linux/interrupt.h>
15#include <linux/io.h>
b60503ba
MW		 16#include <linux/mm.h>
17#include <linux/module.h>
77bf25ea 18#include <linux/mutex.h>
d0877473 19#include <linux/once.h>
b60503ba 20#include <linux/pci.h>
d916b1be 21#include <linux/suspend.h>
e1e5e564 22#include <linux/t10-pi.h>
b60503ba 23#include <linux/types.h>
2f8e2c87 24#include <linux/io-64-nonatomic-lo-hi.h>
a98e58e5 25#include <linux/sed-opal.h>
0f238ff5 26#include <linux/pci-p2pdma.h>
797a796a 27
604c01d5 28#include "trace.h"
f11bb3e2
CH		 29#include "nvme.h"
30
c1e0cc7e 31#define SQ_SIZE(q) ((q)->q_depth << (q)->sqes)
8a1d09a6 32#define CQ_SIZE(q) ((q)->q_depth * sizeof(struct nvme_completion))
c965809c 33
a7a7cbe3 34#define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc))
9d43cf64 35
943e942e
JA		 36/*
37 * These can be higher, but we need to ensure that any command doesn't
38 * require an sg allocation that needs more than a page of data.
39 */
40#define NVME_MAX_KB_SZ 4096
41#define NVME_MAX_SEGS 127
42
58ffacb5
MW		 43static int use_threaded_interrupts;
44module_param(use_threaded_interrupts, int, 0);
45
8ffaadf7 46static bool use_cmb_sqes = true;
69f4eb9f 47module_param(use_cmb_sqes, bool, 0444);
8ffaadf7
JD		 48MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
49
87ad72a5
CH		 50static unsigned int max_host_mem_size_mb = 128;
51module_param(max_host_mem_size_mb, uint, 0444);
52MODULE_PARM_DESC(max_host_mem_size_mb,
53 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
1fa6aead 54
a7a7cbe3
CK		 55static unsigned int sgl_threshold = SZ_32K;
56module_param(sgl_threshold, uint, 0644);
57MODULE_PARM_DESC(sgl_threshold,
58 "Use SGLs when average request segment size is larger or equal to "
59 "this size. Use 0 to disable SGLs.");
60
b27c1e68 61static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
62static const struct kernel_param_ops io_queue_depth_ops = {
63 .set = io_queue_depth_set,
64 .get = param_get_int,
65};
66
67static int io_queue_depth = 1024;
68module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
69MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2");
70
3b6592f7 71static int write_queues;
483178f3 72module_param(write_queues, int, 0644);
3b6592f7
JA		 73MODULE_PARM_DESC(write_queues,
74 "Number of queues to use for writes. If not set, reads and writes "
75 "will share a queue set.");
76
a232ea0e 77static int poll_queues;
483178f3 78module_param(poll_queues, int, 0644);
4b04cc6a
JA		 79MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO.");
80
1c63dc66
CH		 81struct nvme_dev;
82struct nvme_queue;
b3fffdef 83
a5cdb68c 84static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
8fae268b 85static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode);
d4b4ff8e 86
1c63dc66
CH		 87/*
88 * Represents an NVM Express device. Each nvme_dev is a PCI function.
89 */
90struct nvme_dev {
147b27e4 91 struct nvme_queue *queues;
1c63dc66
CH		 92 struct blk_mq_tag_set tagset;
93 struct blk_mq_tag_set admin_tagset;
94 u32 __iomem *dbs;
95 struct device *dev;
96 struct dma_pool *prp_page_pool;
97 struct dma_pool *prp_small_pool;
1c63dc66
CH		 98 unsigned online_queues;
99 unsigned max_qid;
e20ba6e1 100 unsigned io_queues[HCTX_MAX_TYPES];
22b55601 101 unsigned int num_vecs;
1c63dc66 102 int q_depth;
c1e0cc7e 103 int io_sqes;
1c63dc66 104 u32 db_stride;
1c63dc66 105 void __iomem *bar;
97f6ef64 106 unsigned long bar_mapped_size;
5c8809e6 107 struct work_struct remove_work;
77bf25ea 108 struct mutex shutdown_lock;
1c63dc66 109 bool subsystem;
1c63dc66 110 u64 cmb_size;
0f238ff5 111 bool cmb_use_sqes;
1c63dc66 112 u32 cmbsz;
202021c1 113 u32 cmbloc;
1c63dc66 114 struct nvme_ctrl ctrl;
d916b1be 115 u32 last_ps;
87ad72a5 116
943e942e
JA		 117 mempool_t *iod_mempool;
118
87ad72a5 119 /* shadow doorbell buffer support: */
f9f38e33
HK		 120 u32 *dbbuf_dbs;
121 dma_addr_t dbbuf_dbs_dma_addr;
122 u32 *dbbuf_eis;
123 dma_addr_t dbbuf_eis_dma_addr;
87ad72a5
CH		 124
125 /* host memory buffer support: */
126 u64 host_mem_size;
127 u32 nr_host_mem_descs;
4033f35d 128 dma_addr_t host_mem_descs_dma;
87ad72a5
CH		 129 struct nvme_host_mem_buf_desc *host_mem_descs;
130 void **host_mem_desc_bufs;
4d115420 131};
1fa6aead 132
b27c1e68 133static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
134{
135 int n = 0, ret;
136
137 ret = kstrtoint(val, 10, &n);
138 if (ret != 0 || n < 2)
139 return -EINVAL;
140
141 return param_set_int(val, kp);
142}
143
f9f38e33
HK		 144static inline unsigned int sq_idx(unsigned int qid, u32 stride)
145{
146 return qid * 2 * stride;
147}
148
149static inline unsigned int cq_idx(unsigned int qid, u32 stride)
150{
151 return (qid * 2 + 1) * stride;
152}
153
1c63dc66
CH		 154static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
155{
156 return container_of(ctrl, struct nvme_dev, ctrl);
157}
158
b60503ba
MW		 159/*
160 * An NVM Express queue. Each device has at least two (one for admin
161 * commands and one for I/O commands).
162 */
163struct nvme_queue {
091b6092 164 struct nvme_dev *dev;
1ab0cd69 165 spinlock_t sq_lock;
c1e0cc7e 166 void *sq_cmds;
3a7afd8e
CH		 167 /* only used for poll queues: */
168 spinlock_t cq_poll_lock ____cacheline_aligned_in_smp;
b60503ba 169 volatile struct nvme_completion *cqes;
42483228 170 struct blk_mq_tags **tags;
b60503ba
MW		 171 dma_addr_t sq_dma_addr;
172 dma_addr_t cq_dma_addr;
b60503ba
MW		 173 u32 __iomem *q_db;
174 u16 q_depth;
7c349dde 175 u16 cq_vector;
b60503ba 176 u16 sq_tail;
04f3eafd 177 u16 last_sq_tail;
b60503ba 178 u16 cq_head;
68fa9dbe 179 u16 last_cq_head;
c30341dc 180 u16 qid;
e9539f47 181 u8 cq_phase;
c1e0cc7e 182 u8 sqes;
4e224106
CH		 183 unsigned long flags;
184#define NVMEQ_ENABLED 0
63223078 185#define NVMEQ_SQ_CMB 1
d1ed6aa1 186#define NVMEQ_DELETE_ERROR 2
7c349dde 187#define NVMEQ_POLLED 3
f9f38e33
HK		 188 u32 *dbbuf_sq_db;
189 u32 *dbbuf_cq_db;
190 u32 *dbbuf_sq_ei;
191 u32 *dbbuf_cq_ei;
d1ed6aa1 192 struct completion delete_done;
b60503ba
MW		 193};
194
71bd150c 195/*
9b048119
CH		 196 * The nvme_iod describes the data in an I/O.
197 *
198 * The sg pointer contains the list of PRP/SGL chunk allocations in addition
199 * to the actual struct scatterlist.
71bd150c
CH		 200 */
201struct nvme_iod {
d49187e9 202 struct nvme_request req;
f4800d6d 203 struct nvme_queue *nvmeq;
a7a7cbe3 204 bool use_sgl;
f4800d6d 205 int aborted;
71bd150c 206 int npages; /* In the PRP list. 0 means small pool in use */
71bd150c 207 int nents; /* Used in scatterlist */
71bd150c 208 dma_addr_t first_dma;
dff824b2 209 unsigned int dma_len; /* length of single DMA segment mapping */
783b94bd 210 dma_addr_t meta_dma;
f4800d6d 211 struct scatterlist *sg;
b60503ba
MW		 212};
213
3b6592f7
JA		 214static unsigned int max_io_queues(void)
215{
4b04cc6a 216 return num_possible_cpus() + write_queues + poll_queues;
3b6592f7
JA		 217}
218
219static unsigned int max_queue_count(void)
220{
221 /* IO queues + admin queue */
222 return 1 + max_io_queues();
223}
224
f9f38e33
HK		 225static inline unsigned int nvme_dbbuf_size(u32 stride)
226{
3b6592f7 227 return (max_queue_count() * 8 * stride);
f9f38e33
HK		 228}
229
230static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
231{
232 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
233
234 if (dev->dbbuf_dbs)
235 return 0;
236
237 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
238 &dev->dbbuf_dbs_dma_addr,
239 GFP_KERNEL);
240 if (!dev->dbbuf_dbs)
241 return -ENOMEM;
242 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
243 &dev->dbbuf_eis_dma_addr,
244 GFP_KERNEL);
245 if (!dev->dbbuf_eis) {
246 dma_free_coherent(dev->dev, mem_size,
247 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
248 dev->dbbuf_dbs = NULL;
249 return -ENOMEM;
250 }
251
252 return 0;
253}
254
255static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
256{
257 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
258
259 if (dev->dbbuf_dbs) {
260 dma_free_coherent(dev->dev, mem_size,
261 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
262 dev->dbbuf_dbs = NULL;
263 }
264 if (dev->dbbuf_eis) {
265 dma_free_coherent(dev->dev, mem_size,
266 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
267 dev->dbbuf_eis = NULL;
268 }
269}
270
271static void nvme_dbbuf_init(struct nvme_dev *dev,
272 struct nvme_queue *nvmeq, int qid)
273{
274 if (!dev->dbbuf_dbs || !qid)
275 return;
276
277 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
278 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
279 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
280 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
281}
282
283static void nvme_dbbuf_set(struct nvme_dev *dev)
284{
285 struct nvme_command c;
286
287 if (!dev->dbbuf_dbs)
288 return;
289
290 memset(&c, 0, sizeof(c));
291 c.dbbuf.opcode = nvme_admin_dbbuf;
292 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
293 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
294
295 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
9bdcfb10 296 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
f9f38e33
HK		 297 /* Free memory and continue on */
298 nvme_dbbuf_dma_free(dev);
299 }
300}
301
302static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
303{
304 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
305}
306
307/* Update dbbuf and return true if an MMIO is required */
308static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
309 volatile u32 *dbbuf_ei)
310{
311 if (dbbuf_db) {
312 u16 old_value;
313
314 /*
315 * Ensure that the queue is written before updating
316 * the doorbell in memory
317 */
318 wmb();
319
320 old_value = *dbbuf_db;
321 *dbbuf_db = value;
322
f1ed3df2
MW		 323 /*
324 * Ensure that the doorbell is updated before reading the event
325 * index from memory. The controller needs to provide similar
326 * ordering to ensure the envent index is updated before reading
327 * the doorbell.
328 */
329 mb();
330
f9f38e33
HK		 331 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value))
332 return false;
333 }
334
335 return true;
b60503ba
MW		 336}
337
ac3dd5bd
JA		 338/*
339 * Will slightly overestimate the number of pages needed. This is OK
340 * as it only leads to a small amount of wasted memory for the lifetime of
341 * the I/O.
342 */
343static int nvme_npages(unsigned size, struct nvme_dev *dev)
344{
5fd4ce1b
CH		 345 unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size,
346 dev->ctrl.page_size);
ac3dd5bd
JA		 347 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
348}
349
a7a7cbe3
CK		 350/*
351 * Calculates the number of pages needed for the SGL segments. For example a 4k
352 * page can accommodate 256 SGL descriptors.
353 */
354static int nvme_pci_npages_sgl(unsigned int num_seg)
ac3dd5bd 355{
a7a7cbe3 356 return DIV_ROUND_UP(num_seg * sizeof(struct nvme_sgl_desc), PAGE_SIZE);
f4800d6d 357}
ac3dd5bd 358
a7a7cbe3
CK		 359static unsigned int nvme_pci_iod_alloc_size(struct nvme_dev *dev,
360 unsigned int size, unsigned int nseg, bool use_sgl)
f4800d6d 361{
a7a7cbe3
CK		 362 size_t alloc_size;
363
364 if (use_sgl)
365 alloc_size = sizeof(__le64 *) * nvme_pci_npages_sgl(nseg);
366 else
367 alloc_size = sizeof(__le64 *) * nvme_npages(size, dev);
368
369 return alloc_size + sizeof(struct scatterlist) * nseg;
f4800d6d 370}
ac3dd5bd 371
a4aea562
MB		 372static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
373 unsigned int hctx_idx)
e85248e5 374{
a4aea562 375 struct nvme_dev *dev = data;
147b27e4 376 struct nvme_queue *nvmeq = &dev->queues[0];
a4aea562 377
42483228
KB		 378 WARN_ON(hctx_idx != 0);
379 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
380 WARN_ON(nvmeq->tags);
381
a4aea562 382 hctx->driver_data = nvmeq;
42483228 383 nvmeq->tags = &dev->admin_tagset.tags[0];
a4aea562 384 return 0;
e85248e5
MW		 385}
386
4af0e21c
KB		 387static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
388{
389 struct nvme_queue *nvmeq = hctx->driver_data;
390
391 nvmeq->tags = NULL;
392}
393
a4aea562
MB		 394static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
395 unsigned int hctx_idx)
b60503ba 396{
a4aea562 397 struct nvme_dev *dev = data;
147b27e4 398 struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
a4aea562 399
42483228
KB		 400 if (!nvmeq->tags)
401 nvmeq->tags = &dev->tagset.tags[hctx_idx];
b60503ba 402
42483228 403 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
a4aea562
MB		 404 hctx->driver_data = nvmeq;
405 return 0;
b60503ba
MW		 406}
407
d6296d39
CH		 408static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req,
409 unsigned int hctx_idx, unsigned int numa_node)
b60503ba 410{
d6296d39 411 struct nvme_dev *dev = set->driver_data;
f4800d6d 412 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
0350815a 413 int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0;
147b27e4 414 struct nvme_queue *nvmeq = &dev->queues[queue_idx];
a4aea562
MB		 415
416 BUG_ON(!nvmeq);
f4800d6d 417 iod->nvmeq = nvmeq;
59e29ce6
SG		 418
419 nvme_req(req)->ctrl = &dev->ctrl;
a4aea562
MB		 420 return 0;
421}
422
3b6592f7
JA		 423static int queue_irq_offset(struct nvme_dev *dev)
424{
425 /* if we have more than 1 vec, admin queue offsets us by 1 */
426 if (dev->num_vecs > 1)
427 return 1;
428
429 return 0;
430}
431
dca51e78
CH		 432static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
433{
434 struct nvme_dev *dev = set->driver_data;
3b6592f7
JA		 435 int i, qoff, offset;
436
437 offset = queue_irq_offset(dev);
438 for (i = 0, qoff = 0; i < set->nr_maps; i++) {
439 struct blk_mq_queue_map *map = &set->map[i];
440
441 map->nr_queues = dev->io_queues[i];
442 if (!map->nr_queues) {
e20ba6e1 443 BUG_ON(i == HCTX_TYPE_DEFAULT);
7e849dd9 444 continue;
3b6592f7
JA		 445 }
446
4b04cc6a
JA		 447 /*
448 * The poll queue(s) doesn't have an IRQ (and hence IRQ
449 * affinity), so use the regular blk-mq cpu mapping
450 */
3b6592f7 451 map->queue_offset = qoff;
cb9e0e50 452 if (i != HCTX_TYPE_POLL && offset)
4b04cc6a
JA		 453 blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset);
454 else
455 blk_mq_map_queues(map);
3b6592f7
JA		 456 qoff += map->nr_queues;
457 offset += map->nr_queues;
458 }
459
460 return 0;
dca51e78
CH		 461}
462
04f3eafd
JA		 463/*
464 * Write sq tail if we are asked to, or if the next command would wrap.
465 */
466static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq)
467{
468 if (!write_sq) {
469 u16 next_tail = nvmeq->sq_tail + 1;
470
471 if (next_tail == nvmeq->q_depth)
472 next_tail = 0;
473 if (next_tail != nvmeq->last_sq_tail)
474 return;
475 }
476
477 if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail,
478 nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei))
479 writel(nvmeq->sq_tail, nvmeq->q_db);
480 nvmeq->last_sq_tail = nvmeq->sq_tail;
481}
482
b60503ba 483/**
90ea5ca4 484 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
b60503ba
MW		 485 * @nvmeq: The queue to use
486 * @cmd: The command to send
04f3eafd 487 * @write_sq: whether to write to the SQ doorbell
b60503ba 488 */
04f3eafd
JA		 489static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd,
490 bool write_sq)
b60503ba 491{
90ea5ca4 492 spin_lock(&nvmeq->sq_lock);
c1e0cc7e
BH		 493 memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes),
494 cmd, sizeof(*cmd));
90ea5ca4
CH		 495 if (++nvmeq->sq_tail == nvmeq->q_depth)
496 nvmeq->sq_tail = 0;
04f3eafd
JA		 497 nvme_write_sq_db(nvmeq, write_sq);
498 spin_unlock(&nvmeq->sq_lock);
499}
500
501static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx)
502{
503 struct nvme_queue *nvmeq = hctx->driver_data;
504
505 spin_lock(&nvmeq->sq_lock);
506 if (nvmeq->sq_tail != nvmeq->last_sq_tail)
507 nvme_write_sq_db(nvmeq, true);
90ea5ca4 508 spin_unlock(&nvmeq->sq_lock);
b60503ba
MW		 509}
510
a7a7cbe3 511static void **nvme_pci_iod_list(struct request *req)
b60503ba 512{
f4800d6d 513 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3 514 return (void **)(iod->sg + blk_rq_nr_phys_segments(req));
b60503ba
MW		 515}
516
955b1b5a
MI		 517static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req)
518{
519 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
20469a37 520 int nseg = blk_rq_nr_phys_segments(req);
955b1b5a
MI		 521 unsigned int avg_seg_size;
522
20469a37
KB		 523 if (nseg == 0)
524 return false;
525
526 avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
955b1b5a
MI		 527
528 if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1))))
529 return false;
530 if (!iod->nvmeq->qid)
531 return false;
532 if (!sgl_threshold || avg_seg_size < sgl_threshold)
533 return false;
534 return true;
535}
536
7fe07d14 537static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
b60503ba 538{
f4800d6d 539 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3
CK		 540 const int last_prp = dev->ctrl.page_size / sizeof(__le64) - 1;
541 dma_addr_t dma_addr = iod->first_dma, next_dma_addr;
eca18b23 542 int i;
eca18b23 543
dff824b2 544 if (iod->dma_len) {
f2fa006f
IR		 545 dma_unmap_page(dev->dev, dma_addr, iod->dma_len,
546 rq_dma_dir(req));
dff824b2 547 return;
7fe07d14
CH		 548 }
549
dff824b2
CH		 550 WARN_ON_ONCE(!iod->nents);
551
7f73eac3
LG		 552 if (is_pci_p2pdma_page(sg_page(iod->sg)))
553 pci_p2pdma_unmap_sg(dev->dev, iod->sg, iod->nents,
554 rq_dma_dir(req));
555 else
dff824b2
CH		 556 dma_unmap_sg(dev->dev, iod->sg, iod->nents, rq_dma_dir(req));
557
558
eca18b23 559 if (iod->npages == 0)
a7a7cbe3
CK		 560 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0],
561 dma_addr);
562
eca18b23 563 for (i = 0; i < iod->npages; i++) {
a7a7cbe3
CK		 564 void *addr = nvme_pci_iod_list(req)[i];
565
566 if (iod->use_sgl) {
567 struct nvme_sgl_desc *sg_list = addr;
568
569 next_dma_addr =
570 le64_to_cpu((sg_list[SGES_PER_PAGE - 1]).addr);
571 } else {
572 __le64 *prp_list = addr;
573
574 next_dma_addr = le64_to_cpu(prp_list[last_prp]);
575 }
576
577 dma_pool_free(dev->prp_page_pool, addr, dma_addr);
578 dma_addr = next_dma_addr;
eca18b23 579 }
ac3dd5bd 580
d43f1ccf 581 mempool_free(iod->sg, dev->iod_mempool);
b4ff9c8d
KB		 582}
583
d0877473
KB		 584static void nvme_print_sgl(struct scatterlist *sgl, int nents)
585{
586 int i;
587 struct scatterlist *sg;
588
589 for_each_sg(sgl, sg, nents, i) {
590 dma_addr_t phys = sg_phys(sg);
591 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
592 "dma_address:%pad dma_length:%d\n",
593 i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
594 sg_dma_len(sg));
595 }
596}
597
a7a7cbe3
CK		 598static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
599 struct request *req, struct nvme_rw_command *cmnd)
ff22b54f 600{
f4800d6d 601 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
99802a7a 602 struct dma_pool *pool;
b131c61d 603 int length = blk_rq_payload_bytes(req);
eca18b23 604 struct scatterlist *sg = iod->sg;
ff22b54f
MW		 605 int dma_len = sg_dma_len(sg);
606 u64 dma_addr = sg_dma_address(sg);
5fd4ce1b 607 u32 page_size = dev->ctrl.page_size;
f137e0f1 608 int offset = dma_addr & (page_size - 1);
e025344c 609 __le64 *prp_list;
a7a7cbe3 610 void **list = nvme_pci_iod_list(req);
e025344c 611 dma_addr_t prp_dma;
eca18b23 612 int nprps, i;
ff22b54f 613
1d090624 614 length -= (page_size - offset);
5228b328
JS		 615 if (length <= 0) {
616 iod->first_dma = 0;
a7a7cbe3 617 goto done;
5228b328 618 }
ff22b54f 619
1d090624 620 dma_len -= (page_size - offset);
ff22b54f 621 if (dma_len) {
1d090624 622 dma_addr += (page_size - offset);
ff22b54f
MW		 623 } else {
624 sg = sg_next(sg);
625 dma_addr = sg_dma_address(sg);
626 dma_len = sg_dma_len(sg);
627 }
628
1d090624 629 if (length <= page_size) {
edd10d33 630 iod->first_dma = dma_addr;
a7a7cbe3 631 goto done;
e025344c
SMM		 632 }
633
1d090624 634 nprps = DIV_ROUND_UP(length, page_size);
99802a7a
MW		 635 if (nprps <= (256 / 8)) {
636 pool = dev->prp_small_pool;
eca18b23 637 iod->npages = 0;
99802a7a
MW		 638 } else {
639 pool = dev->prp_page_pool;
eca18b23 640 iod->npages = 1;
99802a7a
MW		 641 }
642
69d2b571 643 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
b77954cb 644 if (!prp_list) {
edd10d33 645 iod->first_dma = dma_addr;
eca18b23 646 iod->npages = -1;
86eea289 647 return BLK_STS_RESOURCE;
b77954cb 648 }
eca18b23
MW		 649 list[0] = prp_list;
650 iod->first_dma = prp_dma;
e025344c
SMM		 651 i = 0;
652 for (;;) {
1d090624 653 if (i == page_size >> 3) {
e025344c 654 __le64 *old_prp_list = prp_list;
69d2b571 655 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
eca18b23 656 if (!prp_list)
86eea289 657 return BLK_STS_RESOURCE;
eca18b23 658 list[iod->npages++] = prp_list;
7523d834
MW		 659 prp_list[0] = old_prp_list[i - 1];
660 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
661 i = 1;
e025344c
SMM		 662 }
663 prp_list[i++] = cpu_to_le64(dma_addr);
1d090624
KB		 664 dma_len -= page_size;
665 dma_addr += page_size;
666 length -= page_size;
e025344c
SMM		 667 if (length <= 0)
668 break;
669 if (dma_len > 0)
670 continue;
86eea289
KB		 671 if (unlikely(dma_len < 0))
672 goto bad_sgl;
e025344c
SMM		 673 sg = sg_next(sg);
674 dma_addr = sg_dma_address(sg);
675 dma_len = sg_dma_len(sg);
ff22b54f
MW		 676 }
677
a7a7cbe3
CK		 678done:
679 cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
680 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
681
86eea289
KB		 682 return BLK_STS_OK;
683
684 bad_sgl:
d0877473
KB		 685 WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents),
686 "Invalid SGL for payload:%d nents:%d\n",
687 blk_rq_payload_bytes(req), iod->nents);
86eea289 688 return BLK_STS_IOERR;
ff22b54f
MW		 689}
690
a7a7cbe3
CK		 691static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
692 struct scatterlist *sg)
693{
694 sge->addr = cpu_to_le64(sg_dma_address(sg));
695 sge->length = cpu_to_le32(sg_dma_len(sg));
696 sge->type = NVME_SGL_FMT_DATA_DESC << 4;
697}
698
699static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
700 dma_addr_t dma_addr, int entries)
701{
702 sge->addr = cpu_to_le64(dma_addr);
703 if (entries < SGES_PER_PAGE) {
704 sge->length = cpu_to_le32(entries * sizeof(*sge));
705 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
706 } else {
707 sge->length = cpu_to_le32(PAGE_SIZE);
708 sge->type = NVME_SGL_FMT_SEG_DESC << 4;
709 }
710}
711
712static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
b0f2853b 713 struct request *req, struct nvme_rw_command *cmd, int entries)
a7a7cbe3
CK		 714{
715 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3
CK		 716 struct dma_pool *pool;
717 struct nvme_sgl_desc *sg_list;
718 struct scatterlist *sg = iod->sg;
a7a7cbe3 719 dma_addr_t sgl_dma;
b0f2853b 720 int i = 0;
a7a7cbe3 721
a7a7cbe3
CK		 722 /* setting the transfer type as SGL */
723 cmd->flags = NVME_CMD_SGL_METABUF;
724
b0f2853b 725 if (entries == 1) {
a7a7cbe3
CK		 726 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
727 return BLK_STS_OK;
728 }
729
730 if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
731 pool = dev->prp_small_pool;
732 iod->npages = 0;
733 } else {
734 pool = dev->prp_page_pool;
735 iod->npages = 1;
736 }
737
738 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
739 if (!sg_list) {
740 iod->npages = -1;
741 return BLK_STS_RESOURCE;
742 }
743
744 nvme_pci_iod_list(req)[0] = sg_list;
745 iod->first_dma = sgl_dma;
746
747 nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
748
749 do {
750 if (i == SGES_PER_PAGE) {
751 struct nvme_sgl_desc *old_sg_desc = sg_list;
752 struct nvme_sgl_desc *link = &old_sg_desc[i - 1];
753
754 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
755 if (!sg_list)
756 return BLK_STS_RESOURCE;
757
758 i = 0;
759 nvme_pci_iod_list(req)[iod->npages++] = sg_list;
760 sg_list[i++] = *link;
761 nvme_pci_sgl_set_seg(link, sgl_dma, entries);
762 }
763
764 nvme_pci_sgl_set_data(&sg_list[i++], sg);
a7a7cbe3 765 sg = sg_next(sg);
b0f2853b 766 } while (--entries > 0);
a7a7cbe3 767
a7a7cbe3
CK		 768 return BLK_STS_OK;
769}
770
dff824b2
CH		 771static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev,
772 struct request *req, struct nvme_rw_command *cmnd,
773 struct bio_vec *bv)
774{
775 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
776 unsigned int first_prp_len = dev->ctrl.page_size - bv->bv_offset;
777
778 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
779 if (dma_mapping_error(dev->dev, iod->first_dma))
780 return BLK_STS_RESOURCE;
781 iod->dma_len = bv->bv_len;
782
783 cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma);
784 if (bv->bv_len > first_prp_len)
785 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len);
786 return 0;
787}
788
29791057
CH		 789static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev,
790 struct request *req, struct nvme_rw_command *cmnd,
791 struct bio_vec *bv)
792{
793 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
794
795 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
796 if (dma_mapping_error(dev->dev, iod->first_dma))
797 return BLK_STS_RESOURCE;
798 iod->dma_len = bv->bv_len;
799
049bf372 800 cmnd->flags = NVME_CMD_SGL_METABUF;
29791057
CH		 801 cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma);
802 cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len);
803 cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4;
804 return 0;
805}
806
fc17b653 807static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
b131c61d 808 struct nvme_command *cmnd)
d29ec824 809{
f4800d6d 810 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
70479b71 811 blk_status_t ret = BLK_STS_RESOURCE;
b0f2853b 812 int nr_mapped;
d29ec824 813
dff824b2
CH		 814 if (blk_rq_nr_phys_segments(req) == 1) {
815 struct bio_vec bv = req_bvec(req);
816
817 if (!is_pci_p2pdma_page(bv.bv_page)) {
818 if (bv.bv_offset + bv.bv_len <= dev->ctrl.page_size * 2)
819 return nvme_setup_prp_simple(dev, req,
820 &cmnd->rw, &bv);
29791057
CH		 821
822 if (iod->nvmeq->qid &&
823 dev->ctrl.sgls & ((1 << 0) | (1 << 1)))
824 return nvme_setup_sgl_simple(dev, req,
825 &cmnd->rw, &bv);
dff824b2
CH		 826 }
827 }
828
829 iod->dma_len = 0;
d43f1ccf
CH		 830 iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC);
831 if (!iod->sg)
832 return BLK_STS_RESOURCE;
f9d03f96 833 sg_init_table(iod->sg, blk_rq_nr_phys_segments(req));
70479b71 834 iod->nents = blk_rq_map_sg(req->q, req, iod->sg);
ba1ca37e
CH		 835 if (!iod->nents)
836 goto out;
d29ec824 837
e0596ab2 838 if (is_pci_p2pdma_page(sg_page(iod->sg)))
2b9f4bb2
LG		 839 nr_mapped = pci_p2pdma_map_sg_attrs(dev->dev, iod->sg,
840 iod->nents, rq_dma_dir(req), DMA_ATTR_NO_WARN);
e0596ab2
LG		 841 else
842 nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents,
70479b71 843 rq_dma_dir(req), DMA_ATTR_NO_WARN);
b0f2853b 844 if (!nr_mapped)
ba1ca37e 845 goto out;
d29ec824 846
70479b71 847 iod->use_sgl = nvme_pci_use_sgls(dev, req);
955b1b5a 848 if (iod->use_sgl)
b0f2853b 849 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped);
a7a7cbe3
CK		 850 else
851 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
4aedb705 852out:
86eea289 853 if (ret != BLK_STS_OK)
4aedb705
CH		 854 nvme_unmap_data(dev, req);
855 return ret;
856}
3045c0d0 857
4aedb705
CH		 858static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req,
859 struct nvme_command *cmnd)
860{
861 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
00df5cb4 862
4aedb705
CH		 863 iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req),
864 rq_dma_dir(req), 0);
865 if (dma_mapping_error(dev->dev, iod->meta_dma))
866 return BLK_STS_IOERR;
867 cmnd->rw.metadata = cpu_to_le64(iod->meta_dma);
868 return 0;
00df5cb4
MW		 869}
870
d29ec824
CH		 871/*
872 * NOTE: ns is NULL when called on the admin queue.
873 */
fc17b653 874static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
a4aea562 875 const struct blk_mq_queue_data *bd)
edd10d33 876{
a4aea562
MB		 877 struct nvme_ns *ns = hctx->queue->queuedata;
878 struct nvme_queue *nvmeq = hctx->driver_data;
d29ec824 879 struct nvme_dev *dev = nvmeq->dev;
a4aea562 880 struct request *req = bd->rq;
9b048119 881 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
ba1ca37e 882 struct nvme_command cmnd;
ebe6d874 883 blk_status_t ret;
e1e5e564 884
9b048119
CH		 885 iod->aborted = 0;
886 iod->npages = -1;
887 iod->nents = 0;
888
d1f06f4a
JA		 889 /*
890 * We should not need to do this, but we're still using this to
891 * ensure we can drain requests on a dying queue.
892 */
4e224106 893 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
d1f06f4a
JA		 894 return BLK_STS_IOERR;
895
f9d03f96 896 ret = nvme_setup_cmd(ns, req, &cmnd);
fc17b653 897 if (ret)
f4800d6d 898 return ret;
a4aea562 899
fc17b653 900 if (blk_rq_nr_phys_segments(req)) {
b131c61d 901 ret = nvme_map_data(dev, req, &cmnd);
fc17b653 902 if (ret)
9b048119 903 goto out_free_cmd;
fc17b653 904 }
a4aea562 905
4aedb705
CH		 906 if (blk_integrity_rq(req)) {
907 ret = nvme_map_metadata(dev, req, &cmnd);
908 if (ret)
909 goto out_unmap_data;
910 }
911
aae239e1 912 blk_mq_start_request(req);
04f3eafd 913 nvme_submit_cmd(nvmeq, &cmnd, bd->last);
fc17b653 914 return BLK_STS_OK;
4aedb705
CH		 915out_unmap_data:
916 nvme_unmap_data(dev, req);
f9d03f96
CH		 917out_free_cmd:
918 nvme_cleanup_cmd(req);
ba1ca37e 919 return ret;
b60503ba 920}
e1e5e564 921
77f02a7a 922static void nvme_pci_complete_rq(struct request *req)
eee417b0 923{
f4800d6d 924 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
4aedb705 925 struct nvme_dev *dev = iod->nvmeq->dev;
a4aea562 926
4aedb705
CH		 927 if (blk_integrity_rq(req))
928 dma_unmap_page(dev->dev, iod->meta_dma,
929 rq_integrity_vec(req)->bv_len, rq_data_dir(req));
b15c592d 930 if (blk_rq_nr_phys_segments(req))
4aedb705 931 nvme_unmap_data(dev, req);
77f02a7a 932 nvme_complete_rq(req);
b60503ba
MW		 933}
934
d783e0bd 935/* We read the CQE phase first to check if the rest of the entry is valid */
750dde44 936static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq)
d783e0bd 937{
750dde44
CH		 938 return (le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) ==
939 nvmeq->cq_phase;
d783e0bd
MR		 940}
941
eb281c82 942static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
b60503ba 943{
eb281c82 944 u16 head = nvmeq->cq_head;
adf68f21 945
397c699f
KB		 946 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
947 nvmeq->dbbuf_cq_ei))
948 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
eb281c82 949}
aae239e1 950
5cb525c8 951static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx)
83a12fb7 952{
5cb525c8 953 volatile struct nvme_completion *cqe = &nvmeq->cqes[idx];
83a12fb7 954 struct request *req;
adf68f21 955
83a12fb7
SG		 956 if (unlikely(cqe->command_id >= nvmeq->q_depth)) {
957 dev_warn(nvmeq->dev->ctrl.device,
958 "invalid id %d completed on queue %d\n",
959 cqe->command_id, le16_to_cpu(cqe->sq_id));
960 return;
b60503ba
MW		 961 }
962
83a12fb7
SG		 963 /*
964 * AEN requests are special as they don't time out and can
965 * survive any kind of queue freeze and often don't respond to
966 * aborts. We don't even bother to allocate a struct request
967 * for them but rather special case them here.
968 */
58a8df67 969 if (unlikely(nvme_is_aen_req(nvmeq->qid, cqe->command_id))) {
83a12fb7
SG		 970 nvme_complete_async_event(&nvmeq->dev->ctrl,
971 cqe->status, &cqe->result);
a0fa9647 972 return;
83a12fb7 973 }
b60503ba 974
83a12fb7 975 req = blk_mq_tag_to_rq(*nvmeq->tags, cqe->command_id);
604c01d5 976 trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail);
83a12fb7
SG		 977 nvme_end_request(req, cqe->status, cqe->result);
978}
b60503ba 979
5cb525c8 980static void nvme_complete_cqes(struct nvme_queue *nvmeq, u16 start, u16 end)
b60503ba 981{
5cb525c8
JA		 982 while (start != end) {
983 nvme_handle_cqe(nvmeq, start);
984 if (++start == nvmeq->q_depth)
985 start = 0;
986 }
987}
adf68f21 988
5cb525c8
JA		 989static inline void nvme_update_cq_head(struct nvme_queue *nvmeq)
990{
dcca1662 991 if (nvmeq->cq_head == nvmeq->q_depth - 1) {
5cb525c8
JA		 992 nvmeq->cq_head = 0;
993 nvmeq->cq_phase = !nvmeq->cq_phase;
dcca1662
HY		 994 } else {
995 nvmeq->cq_head++;
b60503ba 996 }
a0fa9647
JA		 997}
998
1052b8ac
JA		 999static inline int nvme_process_cq(struct nvme_queue *nvmeq, u16 *start,
1000 u16 *end, unsigned int tag)
a0fa9647 1001{
1052b8ac 1002 int found = 0;
b60503ba 1003
5cb525c8 1004 *start = nvmeq->cq_head;
1052b8ac
JA		 1005 while (nvme_cqe_pending(nvmeq)) {
1006 if (tag == -1U || nvmeq->cqes[nvmeq->cq_head].command_id == tag)
1007 found++;
5cb525c8 1008 nvme_update_cq_head(nvmeq);
920d13a8 1009 }
5cb525c8 1010 *end = nvmeq->cq_head;
eb281c82 1011
5cb525c8 1012 if (*start != *end)
920d13a8 1013 nvme_ring_cq_doorbell(nvmeq);
5cb525c8 1014 return found;
b60503ba
MW		 1015}
1016
1017static irqreturn_t nvme_irq(int irq, void *data)
58ffacb5 1018{
58ffacb5 1019 struct nvme_queue *nvmeq = data;
68fa9dbe 1020 irqreturn_t ret = IRQ_NONE;
5cb525c8
JA		 1021 u16 start, end;
1022
3a7afd8e
CH		 1023 /*
1024 * The rmb/wmb pair ensures we see all updates from a previous run of
1025 * the irq handler, even if that was on another CPU.
1026 */
1027 rmb();
68fa9dbe
JA		 1028 if (nvmeq->cq_head != nvmeq->last_cq_head)
1029 ret = IRQ_HANDLED;
5cb525c8 1030 nvme_process_cq(nvmeq, &start, &end, -1);
68fa9dbe 1031 nvmeq->last_cq_head = nvmeq->cq_head;
3a7afd8e 1032 wmb();
5cb525c8 1033
68fa9dbe
JA		 1034 if (start != end) {
1035 nvme_complete_cqes(nvmeq, start, end);
1036 return IRQ_HANDLED;
1037 }
1038
1039 return ret;
58ffacb5
MW		 1040}
1041
1042static irqreturn_t nvme_irq_check(int irq, void *data)
1043{
1044 struct nvme_queue *nvmeq = data;
750dde44 1045 if (nvme_cqe_pending(nvmeq))
d783e0bd
MR		 1046 return IRQ_WAKE_THREAD;
1047 return IRQ_NONE;
58ffacb5
MW		 1048}
1049
0b2a8a9f
CH		 1050/*
1051 * Poll for completions any queue, including those not dedicated to polling.
1052 * Can be called from any context.
1053 */
1054static int nvme_poll_irqdisable(struct nvme_queue *nvmeq, unsigned int tag)
a0fa9647 1055{
3a7afd8e 1056 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
5cb525c8 1057 u16 start, end;
1052b8ac 1058 int found;
a0fa9647 1059
3a7afd8e
CH		 1060 /*
1061 * For a poll queue we need to protect against the polling thread
1062 * using the CQ lock. For normal interrupt driven threads we have
1063 * to disable the interrupt to avoid racing with it.
1064 */
7c349dde 1065 if (test_bit(NVMEQ_POLLED, &nvmeq->flags)) {
3a7afd8e 1066 spin_lock(&nvmeq->cq_poll_lock);
91a509f8 1067 found = nvme_process_cq(nvmeq, &start, &end, tag);
3a7afd8e 1068 spin_unlock(&nvmeq->cq_poll_lock);
91a509f8
CH		 1069 } else {
1070 disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1071 found = nvme_process_cq(nvmeq, &start, &end, tag);
3a7afd8e 1072 enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
91a509f8 1073 }
442e19b7 1074
5cb525c8 1075 nvme_complete_cqes(nvmeq, start, end);
442e19b7 1076 return found;
a0fa9647
JA		 1077}
1078
9743139c 1079static int nvme_poll(struct blk_mq_hw_ctx *hctx)
dabcefab
JA		 1080{
1081 struct nvme_queue *nvmeq = hctx->driver_data;
1082 u16 start, end;
1083 bool found;
1084
1085 if (!nvme_cqe_pending(nvmeq))
1086 return 0;
1087
3a7afd8e 1088 spin_lock(&nvmeq->cq_poll_lock);
9743139c 1089 found = nvme_process_cq(nvmeq, &start, &end, -1);
3a7afd8e 1090 spin_unlock(&nvmeq->cq_poll_lock);
dabcefab
JA		 1091
1092 nvme_complete_cqes(nvmeq, start, end);
1093 return found;
1094}
1095
ad22c355 1096static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
b60503ba 1097{
f866fc42 1098 struct nvme_dev *dev = to_nvme_dev(ctrl);
147b27e4 1099 struct nvme_queue *nvmeq = &dev->queues[0];
a4aea562 1100 struct nvme_command c;
b60503ba 1101
a4aea562
MB		 1102 memset(&c, 0, sizeof(c));
1103 c.common.opcode = nvme_admin_async_event;
ad22c355 1104 c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
04f3eafd 1105 nvme_submit_cmd(nvmeq, &c, true);
f705f837
CH		 1106}
1107
b60503ba 1108static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
f705f837 1109{
b60503ba
MW		 1110 struct nvme_command c;
1111
1112 memset(&c, 0, sizeof(c));
1113 c.delete_queue.opcode = opcode;
1114 c.delete_queue.qid = cpu_to_le16(id);
1115
1c63dc66 1116 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1117}
1118
b60503ba 1119static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
a8e3e0bb 1120 struct nvme_queue *nvmeq, s16 vector)
b60503ba 1121{
b60503ba 1122 struct nvme_command c;
4b04cc6a
JA		 1123 int flags = NVME_QUEUE_PHYS_CONTIG;
1124
7c349dde 1125 if (!test_bit(NVMEQ_POLLED, &nvmeq->flags))
4b04cc6a 1126 flags |= NVME_CQ_IRQ_ENABLED;
b60503ba 1127
d29ec824 1128 /*
16772ae6 1129 * Note: we (ab)use the fact that the prp fields survive if no data
d29ec824
CH		 1130 * is attached to the request.
1131 */
b60503ba
MW		 1132 memset(&c, 0, sizeof(c));
1133 c.create_cq.opcode = nvme_admin_create_cq;
1134 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1135 c.create_cq.cqid = cpu_to_le16(qid);
1136 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1137 c.create_cq.cq_flags = cpu_to_le16(flags);
7c349dde 1138 c.create_cq.irq_vector = cpu_to_le16(vector);
b60503ba 1139
1c63dc66 1140 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1141}
1142
1143static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1144 struct nvme_queue *nvmeq)
1145{
9abd68ef 1146 struct nvme_ctrl *ctrl = &dev->ctrl;
b60503ba 1147 struct nvme_command c;
81c1cd98 1148 int flags = NVME_QUEUE_PHYS_CONTIG;
b60503ba 1149
9abd68ef
JA		 1150 /*
1151 * Some drives have a bug that auto-enables WRRU if MEDIUM isn't
1152 * set. Since URGENT priority is zeroes, it makes all queues
1153 * URGENT.
1154 */
1155 if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ)
1156 flags |= NVME_SQ_PRIO_MEDIUM;
1157
d29ec824 1158 /*
16772ae6 1159 * Note: we (ab)use the fact that the prp fields survive if no data
d29ec824
CH		 1160 * is attached to the request.
1161 */
b60503ba
MW		 1162 memset(&c, 0, sizeof(c));
1163 c.create_sq.opcode = nvme_admin_create_sq;
1164 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1165 c.create_sq.sqid = cpu_to_le16(qid);
1166 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1167 c.create_sq.sq_flags = cpu_to_le16(flags);
1168 c.create_sq.cqid = cpu_to_le16(qid);
1169
1c63dc66 1170 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1171}
1172
1173static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1174{
1175 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1176}
1177
1178static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1179{
1180 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1181}
1182
2a842aca 1183static void abort_endio(struct request *req, blk_status_t error)
bc5fc7e4 1184{
f4800d6d
CH		 1185 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1186 struct nvme_queue *nvmeq = iod->nvmeq;
e44ac588 1187
27fa9bc5
CH		 1188 dev_warn(nvmeq->dev->ctrl.device,
1189 "Abort status: 0x%x", nvme_req(req)->status);
e7a2a87d 1190 atomic_inc(&nvmeq->dev->ctrl.abort_limit);
e7a2a87d 1191 blk_mq_free_request(req);
bc5fc7e4
MW		 1192}
1193
b2a0eb1a
KB		 1194static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1195{
1196
1197 /* If true, indicates loss of adapter communication, possibly by a
1198 * NVMe Subsystem reset.
1199 */
1200 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1201
ad70062c
JW		 1202 /* If there is a reset/reinit ongoing, we shouldn't reset again. */
1203 switch (dev->ctrl.state) {
1204 case NVME_CTRL_RESETTING:
ad6a0a52 1205 case NVME_CTRL_CONNECTING:
b2a0eb1a 1206 return false;
ad70062c
JW		 1207 default:
1208 break;
1209 }
b2a0eb1a
KB		 1210
1211 /* We shouldn't reset unless the controller is on fatal error state
1212 * _or_ if we lost the communication with it.
1213 */
1214 if (!(csts & NVME_CSTS_CFS) && !nssro)
1215 return false;
1216
b2a0eb1a
KB		 1217 return true;
1218}
1219
1220static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1221{
1222 /* Read a config register to help see what died. */
1223 u16 pci_status;
1224 int result;
1225
1226 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1227 &pci_status);
1228 if (result == PCIBIOS_SUCCESSFUL)
1229 dev_warn(dev->ctrl.device,
1230 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1231 csts, pci_status);
1232 else
1233 dev_warn(dev->ctrl.device,
1234 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1235 csts, result);
1236}
1237
31c7c7d2 1238static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
c30341dc 1239{
f4800d6d
CH		 1240 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1241 struct nvme_queue *nvmeq = iod->nvmeq;
c30341dc 1242 struct nvme_dev *dev = nvmeq->dev;
a4aea562 1243 struct request *abort_req;
a4aea562 1244 struct nvme_command cmd;
b2a0eb1a
KB		 1245 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1246
651438bb
WX		 1247 /* If PCI error recovery process is happening, we cannot reset or
1248 * the recovery mechanism will surely fail.
1249 */
1250 mb();
1251 if (pci_channel_offline(to_pci_dev(dev->dev)))
1252 return BLK_EH_RESET_TIMER;
1253
b2a0eb1a
KB		 1254 /*
1255 * Reset immediately if the controller is failed
1256 */
1257 if (nvme_should_reset(dev, csts)) {
1258 nvme_warn_reset(dev, csts);
1259 nvme_dev_disable(dev, false);
d86c4d8e 1260 nvme_reset_ctrl(&dev->ctrl);
db8c48e4 1261 return BLK_EH_DONE;
b2a0eb1a 1262 }
c30341dc 1263
7776db1c
KB		 1264 /*
1265 * Did we miss an interrupt?
1266 */
0b2a8a9f 1267 if (nvme_poll_irqdisable(nvmeq, req->tag)) {
7776db1c
KB		 1268 dev_warn(dev->ctrl.device,
1269 "I/O %d QID %d timeout, completion polled\n",
1270 req->tag, nvmeq->qid);
db8c48e4 1271 return BLK_EH_DONE;
7776db1c
KB		 1272 }
1273
31c7c7d2 1274 /*
fd634f41
CH		 1275 * Shutdown immediately if controller times out while starting. The
1276 * reset work will see the pci device disabled when it gets the forced
1277 * cancellation error. All outstanding requests are completed on
db8c48e4 1278 * shutdown, so we return BLK_EH_DONE.
fd634f41 1279 */
4244140d
KB		 1280 switch (dev->ctrl.state) {
1281 case NVME_CTRL_CONNECTING:
2036f726
KB		 1282 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
1283 /* fall through */
1284 case NVME_CTRL_DELETING:
b9cac43c 1285 dev_warn_ratelimited(dev->ctrl.device,
fd634f41
CH		 1286 "I/O %d QID %d timeout, disable controller\n",
1287 req->tag, nvmeq->qid);
2036f726 1288 nvme_dev_disable(dev, true);
27fa9bc5 1289 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
db8c48e4 1290 return BLK_EH_DONE;
39a9dd81
KB		 1291 case NVME_CTRL_RESETTING:
1292 return BLK_EH_RESET_TIMER;
4244140d
KB		 1293 default:
1294 break;
c30341dc
KB		 1295 }
1296
fd634f41
CH		 1297 /*
1298 * Shutdown the controller immediately and schedule a reset if the
1299 * command was already aborted once before and still hasn't been
1300 * returned to the driver, or if this is the admin queue.
31c7c7d2 1301 */
f4800d6d 1302 if (!nvmeq->qid || iod->aborted) {
1b3c47c1 1303 dev_warn(dev->ctrl.device,
e1569a16
KB		 1304 "I/O %d QID %d timeout, reset controller\n",
1305 req->tag, nvmeq->qid);
a5cdb68c 1306 nvme_dev_disable(dev, false);
d86c4d8e 1307 nvme_reset_ctrl(&dev->ctrl);
c30341dc 1308
27fa9bc5 1309 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
db8c48e4 1310 return BLK_EH_DONE;
c30341dc 1311 }
c30341dc 1312
e7a2a87d 1313 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
6bf25d16 1314 atomic_inc(&dev->ctrl.abort_limit);
31c7c7d2 1315 return BLK_EH_RESET_TIMER;
6bf25d16 1316 }
7bf7d778 1317 iod->aborted = 1;
a4aea562 1318
c30341dc
KB		 1319 memset(&cmd, 0, sizeof(cmd));
1320 cmd.abort.opcode = nvme_admin_abort_cmd;
a4aea562 1321 cmd.abort.cid = req->tag;
c30341dc 1322 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
c30341dc 1323
1b3c47c1
SG		 1324 dev_warn(nvmeq->dev->ctrl.device,
1325 "I/O %d QID %d timeout, aborting\n",
1326 req->tag, nvmeq->qid);
e7a2a87d
CH		 1327
1328 abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
eb71f435 1329 BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
e7a2a87d
CH		 1330 if (IS_ERR(abort_req)) {
1331 atomic_inc(&dev->ctrl.abort_limit);
1332 return BLK_EH_RESET_TIMER;
1333 }
1334
1335 abort_req->timeout = ADMIN_TIMEOUT;
1336 abort_req->end_io_data = NULL;
1337 blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio);
c30341dc 1338
31c7c7d2
CH		 1339 /*
1340 * The aborted req will be completed on receiving the abort req.
1341 * We enable the timer again. If hit twice, it'll cause a device reset,
1342 * as the device then is in a faulty state.
1343 */
1344 return BLK_EH_RESET_TIMER;
c30341dc
KB		 1345}
1346
a4aea562
MB		 1347static void nvme_free_queue(struct nvme_queue *nvmeq)
1348{
8a1d09a6 1349 dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq),
9e866774 1350 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
63223078
CH		 1351 if (!nvmeq->sq_cmds)
1352 return;
0f238ff5 1353
63223078 1354 if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) {
88a041f4 1355 pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev),
8a1d09a6 1356 nvmeq->sq_cmds, SQ_SIZE(nvmeq));
63223078 1357 } else {
8a1d09a6 1358 dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq),
63223078 1359 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
0f238ff5 1360 }
9e866774
MW		 1361}
1362
a1a5ef99 1363static void nvme_free_queues(struct nvme_dev *dev, int lowest)
22404274
KB		 1364{
1365 int i;
1366
d858e5f0 1367 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
d858e5f0 1368 dev->ctrl.queue_count--;
147b27e4 1369 nvme_free_queue(&dev->queues[i]);
121c7ad4 1370 }
22404274
KB		 1371}
1372
4d115420
KB		 1373/**
1374 * nvme_suspend_queue - put queue into suspended state
40581d1a 1375 * @nvmeq: queue to suspend
4d115420
KB		 1376 */
1377static int nvme_suspend_queue(struct nvme_queue *nvmeq)
b60503ba 1378{
4e224106 1379 if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags))
2b25d981 1380 return 1;
a09115b2 1381
4e224106 1382 /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */
d1f06f4a 1383 mb();
a09115b2 1384
4e224106 1385 nvmeq->dev->online_queues--;
1c63dc66 1386 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
c81545f9 1387 blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q);
7c349dde
KB		 1388 if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags))
1389 pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq);
4d115420
KB		 1390 return 0;
1391}
b60503ba 1392
8fae268b
KB		 1393static void nvme_suspend_io_queues(struct nvme_dev *dev)
1394{
1395 int i;
1396
1397 for (i = dev->ctrl.queue_count - 1; i > 0; i--)
1398 nvme_suspend_queue(&dev->queues[i]);
1399}
1400
a5cdb68c 1401static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
4d115420 1402{
147b27e4 1403 struct nvme_queue *nvmeq = &dev->queues[0];
4d115420 1404
a5cdb68c
KB		 1405 if (shutdown)
1406 nvme_shutdown_ctrl(&dev->ctrl);
1407 else
b5b05048 1408 nvme_disable_ctrl(&dev->ctrl);
07836e65 1409
0b2a8a9f 1410 nvme_poll_irqdisable(nvmeq, -1);
b60503ba
MW		 1411}
1412
8ffaadf7
JD		 1413static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1414 int entry_size)
1415{
1416 int q_depth = dev->q_depth;
5fd4ce1b
CH		 1417 unsigned q_size_aligned = roundup(q_depth * entry_size,
1418 dev->ctrl.page_size);
8ffaadf7
JD		 1419
1420 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
c45f5c99 1421 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
5fd4ce1b 1422 mem_per_q = round_down(mem_per_q, dev->ctrl.page_size);
c45f5c99 1423 q_depth = div_u64(mem_per_q, entry_size);
8ffaadf7
JD		 1424
1425 /*
1426 * Ensure the reduced q_depth is above some threshold where it
1427 * would be better to map queues in system memory with the
1428 * original depth
1429 */
1430 if (q_depth < 64)
1431 return -ENOMEM;
1432 }
1433
1434 return q_depth;
1435}
1436
1437static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
8a1d09a6 1438 int qid)
8ffaadf7 1439{
0f238ff5
LG		 1440 struct pci_dev *pdev = to_pci_dev(dev->dev);
1441
1442 if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
8a1d09a6 1443 nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq));
bfac8e9f
AM		 1444 if (nvmeq->sq_cmds) {
1445 nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev,
1446 nvmeq->sq_cmds);
1447 if (nvmeq->sq_dma_addr) {
1448 set_bit(NVMEQ_SQ_CMB, &nvmeq->flags);
1449 return 0;
1450 }
1451
8a1d09a6 1452 pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq));
63223078 1453 }
0f238ff5 1454 }
8ffaadf7 1455
8a1d09a6 1456 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq),
63223078 1457 &nvmeq->sq_dma_addr, GFP_KERNEL);
815c6704
KB		 1458 if (!nvmeq->sq_cmds)
1459 return -ENOMEM;
8ffaadf7
JD		 1460 return 0;
1461}
1462
a6ff7262 1463static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
b60503ba 1464{
147b27e4 1465 struct nvme_queue *nvmeq = &dev->queues[qid];
b60503ba 1466
62314e40
KB		 1467 if (dev->ctrl.queue_count > qid)
1468 return 0;
b60503ba 1469
c1e0cc7e 1470 nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES;
8a1d09a6
BH		 1471 nvmeq->q_depth = depth;
1472 nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq),
750afb08 1473 &nvmeq->cq_dma_addr, GFP_KERNEL);
b60503ba
MW		 1474 if (!nvmeq->cqes)
1475 goto free_nvmeq;
b60503ba 1476
8a1d09a6 1477 if (nvme_alloc_sq_cmds(dev, nvmeq, qid))
b60503ba
MW		 1478 goto free_cqdma;
1479
091b6092 1480 nvmeq->dev = dev;
1ab0cd69 1481 spin_lock_init(&nvmeq->sq_lock);
3a7afd8e 1482 spin_lock_init(&nvmeq->cq_poll_lock);
b60503ba 1483 nvmeq->cq_head = 0;
82123460 1484 nvmeq->cq_phase = 1;
b80d5ccc 1485 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
c30341dc 1486 nvmeq->qid = qid;
d858e5f0 1487 dev->ctrl.queue_count++;
36a7e993 1488
147b27e4 1489 return 0;
b60503ba
MW		 1490
1491 free_cqdma:
8a1d09a6
BH		 1492 dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes,
1493 nvmeq->cq_dma_addr);
b60503ba 1494 free_nvmeq:
147b27e4 1495 return -ENOMEM;
b60503ba
MW		 1496}
1497
dca51e78 1498static int queue_request_irq(struct nvme_queue *nvmeq)
3001082c 1499{
0ff199cb
CH		 1500 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1501 int nr = nvmeq->dev->ctrl.instance;
1502
1503 if (use_threaded_interrupts) {
1504 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1505 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1506 } else {
1507 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1508 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1509 }
3001082c
MW		 1510}
1511
22404274 1512static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
b60503ba 1513{
22404274 1514 struct nvme_dev *dev = nvmeq->dev;
b60503ba 1515
22404274 1516 nvmeq->sq_tail = 0;
04f3eafd 1517 nvmeq->last_sq_tail = 0;
22404274
KB		 1518 nvmeq->cq_head = 0;
1519 nvmeq->cq_phase = 1;
b80d5ccc 1520 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
8a1d09a6 1521 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq));
f9f38e33 1522 nvme_dbbuf_init(dev, nvmeq, qid);
42f61420 1523 dev->online_queues++;
3a7afd8e 1524 wmb(); /* ensure the first interrupt sees the initialization */
22404274
KB		 1525}
1526
4b04cc6a 1527static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled)
22404274
KB		 1528{
1529 struct nvme_dev *dev = nvmeq->dev;
1530 int result;
7c349dde 1531 u16 vector = 0;
3f85d50b 1532
d1ed6aa1
CH		 1533 clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
1534
22b55601
KB		 1535 /*
1536 * A queue's vector matches the queue identifier unless the controller
1537 * has only one vector available.
1538 */
4b04cc6a
JA		 1539 if (!polled)
1540 vector = dev->num_vecs == 1 ? 0 : qid;
1541 else
7c349dde 1542 set_bit(NVMEQ_POLLED, &nvmeq->flags);
4b04cc6a 1543
a8e3e0bb 1544 result = adapter_alloc_cq(dev, qid, nvmeq, vector);
ded45505
KB		 1545 if (result)
1546 return result;
b60503ba
MW		 1547
1548 result = adapter_alloc_sq(dev, qid, nvmeq);
1549 if (result < 0)
ded45505
KB		 1550 return result;
1551 else if (result)
b60503ba
MW		 1552 goto release_cq;
1553
a8e3e0bb 1554 nvmeq->cq_vector = vector;
161b8be2 1555 nvme_init_queue(nvmeq, qid);
4b04cc6a 1556
7c349dde 1557 if (!polled) {
4b04cc6a
JA		 1558 result = queue_request_irq(nvmeq);
1559 if (result < 0)
1560 goto release_sq;
1561 }
b60503ba 1562
4e224106 1563 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
22404274 1564 return result;
b60503ba 1565
a8e3e0bb 1566release_sq:
f25a2dfc 1567 dev->online_queues--;
b60503ba 1568 adapter_delete_sq(dev, qid);
a8e3e0bb 1569release_cq:
b60503ba 1570 adapter_delete_cq(dev, qid);
22404274 1571 return result;
b60503ba
MW		 1572}
1573
f363b089 1574static const struct blk_mq_ops nvme_mq_admin_ops = {
d29ec824 1575 .queue_rq = nvme_queue_rq,
77f02a7a 1576 .complete = nvme_pci_complete_rq,
a4aea562 1577 .init_hctx = nvme_admin_init_hctx,
4af0e21c 1578 .exit_hctx = nvme_admin_exit_hctx,
0350815a 1579 .init_request = nvme_init_request,
a4aea562
MB		 1580 .timeout = nvme_timeout,
1581};
1582
f363b089 1583static const struct blk_mq_ops nvme_mq_ops = {
376f7ef8
CH		 1584 .queue_rq = nvme_queue_rq,
1585 .complete = nvme_pci_complete_rq,
1586 .commit_rqs = nvme_commit_rqs,
1587 .init_hctx = nvme_init_hctx,
1588 .init_request = nvme_init_request,
1589 .map_queues = nvme_pci_map_queues,
1590 .timeout = nvme_timeout,
1591 .poll = nvme_poll,
dabcefab
JA		 1592};
1593
ea191d2f
KB		 1594static void nvme_dev_remove_admin(struct nvme_dev *dev)
1595{
1c63dc66 1596 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
69d9a99c
KB		 1597 /*
1598 * If the controller was reset during removal, it's possible
1599 * user requests may be waiting on a stopped queue. Start the
1600 * queue to flush these to completion.
1601 */
c81545f9 1602 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1c63dc66 1603 blk_cleanup_queue(dev->ctrl.admin_q);
ea191d2f
KB		 1604 blk_mq_free_tag_set(&dev->admin_tagset);
1605 }
1606}
1607
a4aea562
MB		 1608static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1609{
1c63dc66 1610 if (!dev->ctrl.admin_q) {
a4aea562
MB		 1611 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1612 dev->admin_tagset.nr_hw_queues = 1;
e3e9d50c 1613
38dabe21 1614 dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH;
a4aea562 1615 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
e75ec752 1616 dev->admin_tagset.numa_node = dev_to_node(dev->dev);
d43f1ccf 1617 dev->admin_tagset.cmd_size = sizeof(struct nvme_iod);
d3484991 1618 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED;
a4aea562
MB		 1619 dev->admin_tagset.driver_data = dev;
1620
1621 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1622 return -ENOMEM;
34b6c231 1623 dev->ctrl.admin_tagset = &dev->admin_tagset;
a4aea562 1624
1c63dc66
CH		 1625 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1626 if (IS_ERR(dev->ctrl.admin_q)) {
a4aea562
MB		 1627 blk_mq_free_tag_set(&dev->admin_tagset);
1628 return -ENOMEM;
1629 }
1c63dc66 1630 if (!blk_get_queue(dev->ctrl.admin_q)) {
ea191d2f 1631 nvme_dev_remove_admin(dev);
1c63dc66 1632 dev->ctrl.admin_q = NULL;
ea191d2f
KB		 1633 return -ENODEV;
1634 }
0fb59cbc 1635 } else
c81545f9 1636 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
a4aea562
MB		 1637
1638 return 0;
1639}
1640
97f6ef64
XY		 1641static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1642{
1643 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1644}
1645
1646static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1647{
1648 struct pci_dev *pdev = to_pci_dev(dev->dev);
1649
1650 if (size <= dev->bar_mapped_size)
1651 return 0;
1652 if (size > pci_resource_len(pdev, 0))
1653 return -ENOMEM;
1654 if (dev->bar)
1655 iounmap(dev->bar);
1656 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1657 if (!dev->bar) {
1658 dev->bar_mapped_size = 0;
1659 return -ENOMEM;
1660 }
1661 dev->bar_mapped_size = size;
1662 dev->dbs = dev->bar + NVME_REG_DBS;
1663
1664 return 0;
1665}
1666
01ad0990 1667static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
b60503ba 1668{
ba47e386 1669 int result;
b60503ba
MW		 1670 u32 aqa;
1671 struct nvme_queue *nvmeq;
1672
97f6ef64
XY		 1673 result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1674 if (result < 0)
1675 return result;
1676
8ef2074d 1677 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
20d0dfe6 1678 NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
dfbac8c7 1679
7a67cbea
CH		 1680 if (dev->subsystem &&
1681 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1682 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
dfbac8c7 1683
b5b05048 1684 result = nvme_disable_ctrl(&dev->ctrl);
ba47e386
MW		 1685 if (result < 0)
1686 return result;
b60503ba 1687
a6ff7262 1688 result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
147b27e4
SG		 1689 if (result)
1690 return result;
b60503ba 1691
147b27e4 1692 nvmeq = &dev->queues[0];
b60503ba
MW		 1693 aqa = nvmeq->q_depth - 1;
1694 aqa |= aqa << 16;
1695
7a67cbea
CH		 1696 writel(aqa, dev->bar + NVME_REG_AQA);
1697 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1698 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
b60503ba 1699
c0f2f45b 1700 result = nvme_enable_ctrl(&dev->ctrl);
025c557a 1701 if (result)
d4875622 1702 return result;
a4aea562 1703
2b25d981 1704 nvmeq->cq_vector = 0;
161b8be2 1705 nvme_init_queue(nvmeq, 0);
dca51e78 1706 result = queue_request_irq(nvmeq);
758dd7fd 1707 if (result) {
7c349dde 1708 dev->online_queues--;
d4875622 1709 return result;
758dd7fd 1710 }
025c557a 1711
4e224106 1712 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
b60503ba
MW		 1713 return result;
1714}
1715
749941f2 1716static int nvme_create_io_queues(struct nvme_dev *dev)
42f61420 1717{
4b04cc6a 1718 unsigned i, max, rw_queues;
749941f2 1719 int ret = 0;
42f61420 1720
d858e5f0 1721 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
a6ff7262 1722 if (nvme_alloc_queue(dev, i, dev->q_depth)) {
749941f2 1723 ret = -ENOMEM;
42f61420 1724 break;
749941f2
CH		 1725 }
1726 }
42f61420 1727
d858e5f0 1728 max = min(dev->max_qid, dev->ctrl.queue_count - 1);
e20ba6e1
CH		 1729 if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) {
1730 rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] +
1731 dev->io_queues[HCTX_TYPE_READ];
4b04cc6a
JA		 1732 } else {
1733 rw_queues = max;
1734 }
1735
949928c1 1736 for (i = dev->online_queues; i <= max; i++) {
4b04cc6a
JA		 1737 bool polled = i > rw_queues;
1738
1739 ret = nvme_create_queue(&dev->queues[i], i, polled);
d4875622 1740 if (ret)
42f61420 1741 break;
27e8166c 1742 }
749941f2
CH		 1743
1744 /*
1745 * Ignore failing Create SQ/CQ commands, we can continue with less
8adb8c14
MI		 1746 * than the desired amount of queues, and even a controller without
1747 * I/O queues can still be used to issue admin commands. This might
749941f2
CH		 1748 * be useful to upgrade a buggy firmware for example.
1749 */
1750 return ret >= 0 ? 0 : ret;
b60503ba
MW		 1751}
1752
202021c1
SB		 1753static ssize_t nvme_cmb_show(struct device *dev,
1754 struct device_attribute *attr,
1755 char *buf)
1756{
1757 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
1758
c965809c 1759 return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n",
202021c1
SB		 1760 ndev->cmbloc, ndev->cmbsz);
1761}
1762static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL);
1763
88de4598 1764static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
8ffaadf7 1765{
88de4598
CH		 1766 u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
1767
1768 return 1ULL << (12 + 4 * szu);
1769}
1770
1771static u32 nvme_cmb_size(struct nvme_dev *dev)
1772{
1773 return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
1774}
1775
f65efd6d 1776static void nvme_map_cmb(struct nvme_dev *dev)
8ffaadf7 1777{
88de4598 1778 u64 size, offset;
8ffaadf7
JD		 1779 resource_size_t bar_size;
1780 struct pci_dev *pdev = to_pci_dev(dev->dev);
8969f1f8 1781 int bar;
8ffaadf7 1782
9fe5c59f
KB		 1783 if (dev->cmb_size)
1784 return;
1785
7a67cbea 1786 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
f65efd6d
CH		 1787 if (!dev->cmbsz)
1788 return;
202021c1 1789 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
8ffaadf7 1790
88de4598
CH		 1791 size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
1792 offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
8969f1f8
CH		 1793 bar = NVME_CMB_BIR(dev->cmbloc);
1794 bar_size = pci_resource_len(pdev, bar);
8ffaadf7
JD		 1795
1796 if (offset > bar_size)
f65efd6d 1797 return;
8ffaadf7
JD		 1798
1799 /*
1800 * Controllers may support a CMB size larger than their BAR,
1801 * for example, due to being behind a bridge. Reduce the CMB to
1802 * the reported size of the BAR
1803 */
1804 if (size > bar_size - offset)
1805 size = bar_size - offset;
1806
0f238ff5
LG		 1807 if (pci_p2pdma_add_resource(pdev, bar, size, offset)) {
1808 dev_warn(dev->ctrl.device,
1809 "failed to register the CMB\n");
f65efd6d 1810 return;
0f238ff5
LG		 1811 }
1812
8ffaadf7 1813 dev->cmb_size = size;
0f238ff5
LG		 1814 dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS);
1815
1816 if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) ==
1817 (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS))
1818 pci_p2pmem_publish(pdev, true);
f65efd6d
CH		 1819
1820 if (sysfs_add_file_to_group(&dev->ctrl.device->kobj,
1821 &dev_attr_cmb.attr, NULL))
1822 dev_warn(dev->ctrl.device,
1823 "failed to add sysfs attribute for CMB\n");
8ffaadf7
JD		 1824}
1825
1826static inline void nvme_release_cmb(struct nvme_dev *dev)
1827{
0f238ff5 1828 if (dev->cmb_size) {
1c78f773
MG		 1829 sysfs_remove_file_from_group(&dev->ctrl.device->kobj,
1830 &dev_attr_cmb.attr, NULL);
0f238ff5 1831 dev->cmb_size = 0;
8ffaadf7
JD		 1832 }
1833}
1834
87ad72a5
CH		 1835static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1836{
4033f35d 1837 u64 dma_addr = dev->host_mem_descs_dma;
87ad72a5 1838 struct nvme_command c;
87ad72a5
CH		 1839 int ret;
1840
87ad72a5
CH		 1841 memset(&c, 0, sizeof(c));
1842 c.features.opcode = nvme_admin_set_features;
1843 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1844 c.features.dword11 = cpu_to_le32(bits);
1845 c.features.dword12 = cpu_to_le32(dev->host_mem_size >>
1846 ilog2(dev->ctrl.page_size));
1847 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr));
1848 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr));
1849 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs);
1850
1851 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1852 if (ret) {
1853 dev_warn(dev->ctrl.device,
1854 "failed to set host mem (err %d, flags %#x).\n",
1855 ret, bits);
1856 }
87ad72a5
CH		 1857 return ret;
1858}
1859
1860static void nvme_free_host_mem(struct nvme_dev *dev)
1861{
1862 int i;
1863
1864 for (i = 0; i < dev->nr_host_mem_descs; i++) {
1865 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
1866 size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size;
1867
cc667f6d
LD		 1868 dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i],
1869 le64_to_cpu(desc->addr),
1870 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
87ad72a5
CH		 1871 }
1872
1873 kfree(dev->host_mem_desc_bufs);
1874 dev->host_mem_desc_bufs = NULL;
4033f35d
CH		 1875 dma_free_coherent(dev->dev,
1876 dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
1877 dev->host_mem_descs, dev->host_mem_descs_dma);
87ad72a5 1878 dev->host_mem_descs = NULL;
7e5dd57e 1879 dev->nr_host_mem_descs = 0;
87ad72a5
CH		 1880}
1881
92dc6895
CH		 1882static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
1883 u32 chunk_size)
9d713c2b 1884{
87ad72a5 1885 struct nvme_host_mem_buf_desc *descs;
92dc6895 1886 u32 max_entries, len;
4033f35d 1887 dma_addr_t descs_dma;
2ee0e4ed 1888 int i = 0;
87ad72a5 1889 void **bufs;
6fbcde66 1890 u64 size, tmp;
87ad72a5 1891
87ad72a5
CH		 1892 tmp = (preferred + chunk_size - 1);
1893 do_div(tmp, chunk_size);
1894 max_entries = tmp;
044a9df1
CH		 1895
1896 if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
1897 max_entries = dev->ctrl.hmmaxd;
1898
750afb08
LC		 1899 descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs),
1900 &descs_dma, GFP_KERNEL);
87ad72a5
CH		 1901 if (!descs)
1902 goto out;
1903
1904 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
1905 if (!bufs)
1906 goto out_free_descs;
1907
244a8fe4 1908 for (size = 0; size < preferred && i < max_entries; size += len) {
87ad72a5
CH		 1909 dma_addr_t dma_addr;
1910
50cdb7c6 1911 len = min_t(u64, chunk_size, preferred - size);
87ad72a5
CH		 1912 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
1913 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1914 if (!bufs[i])
1915 break;
1916
1917 descs[i].addr = cpu_to_le64(dma_addr);
1918 descs[i].size = cpu_to_le32(len / dev->ctrl.page_size);
1919 i++;
1920 }
1921
92dc6895 1922 if (!size)
87ad72a5 1923 goto out_free_bufs;
87ad72a5 1924
87ad72a5
CH		 1925 dev->nr_host_mem_descs = i;
1926 dev->host_mem_size = size;
1927 dev->host_mem_descs = descs;
4033f35d 1928 dev->host_mem_descs_dma = descs_dma;
87ad72a5
CH		 1929 dev->host_mem_desc_bufs = bufs;
1930 return 0;
1931
1932out_free_bufs:
1933 while (--i >= 0) {
1934 size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size;
1935
cc667f6d
LD		 1936 dma_free_attrs(dev->dev, size, bufs[i],
1937 le64_to_cpu(descs[i].addr),
1938 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
87ad72a5
CH		 1939 }
1940
1941 kfree(bufs);
1942out_free_descs:
4033f35d
CH		 1943 dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
1944 descs_dma);
87ad72a5 1945out:
87ad72a5
CH		 1946 dev->host_mem_descs = NULL;
1947 return -ENOMEM;
1948}
1949
92dc6895
CH		 1950static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
1951{
1952 u32 chunk_size;
1953
1954 /* start big and work our way down */
30f92d62 1955 for (chunk_size = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
044a9df1 1956 chunk_size >= max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
92dc6895
CH		 1957 chunk_size /= 2) {
1958 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
1959 if (!min || dev->host_mem_size >= min)
1960 return 0;
1961 nvme_free_host_mem(dev);
1962 }
1963 }
1964
1965 return -ENOMEM;
1966}
1967
9620cfba 1968static int nvme_setup_host_mem(struct nvme_dev *dev)
87ad72a5
CH		 1969{
1970 u64 max = (u64)max_host_mem_size_mb * SZ_1M;
1971 u64 preferred = (u64)dev->ctrl.hmpre * 4096;
1972 u64 min = (u64)dev->ctrl.hmmin * 4096;
1973 u32 enable_bits = NVME_HOST_MEM_ENABLE;
6fbcde66 1974 int ret;
87ad72a5
CH		 1975
1976 preferred = min(preferred, max);
1977 if (min > max) {
1978 dev_warn(dev->ctrl.device,
1979 "min host memory (%lld MiB) above limit (%d MiB).\n",
1980 min >> ilog2(SZ_1M), max_host_mem_size_mb);
1981 nvme_free_host_mem(dev);
9620cfba 1982 return 0;
87ad72a5
CH		 1983 }
1984
1985 /*
1986 * If we already have a buffer allocated check if we can reuse it.
1987 */
1988 if (dev->host_mem_descs) {
1989 if (dev->host_mem_size >= min)
1990 enable_bits |= NVME_HOST_MEM_RETURN;
1991 else
1992 nvme_free_host_mem(dev);
1993 }
1994
1995 if (!dev->host_mem_descs) {
92dc6895
CH		 1996 if (nvme_alloc_host_mem(dev, min, preferred)) {
1997 dev_warn(dev->ctrl.device,
1998 "failed to allocate host memory buffer.\n");
9620cfba 1999 return 0; /* controller must work without HMB */
92dc6895
CH		 2000 }
2001
2002 dev_info(dev->ctrl.device,
2003 "allocated %lld MiB host memory buffer.\n",
2004 dev->host_mem_size >> ilog2(SZ_1M));
87ad72a5
CH		 2005 }
2006
9620cfba
CH		 2007 ret = nvme_set_host_mem(dev, enable_bits);
2008 if (ret)
87ad72a5 2009 nvme_free_host_mem(dev);
9620cfba 2010 return ret;
9d713c2b
KB		 2011}
2012
612b7286
ML		 2013/*
2014 * nirqs is the number of interrupts available for write and read
2015 * queues. The core already reserved an interrupt for the admin queue.
2016 */
2017static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs)
3b6592f7 2018{
612b7286
ML		 2019 struct nvme_dev *dev = affd->priv;
2020 unsigned int nr_read_queues;
3b6592f7
JA		 2021
2022 /*
612b7286
ML		 2023 * If there is no interupt available for queues, ensure that
2024 * the default queue is set to 1. The affinity set size is
2025 * also set to one, but the irq core ignores it for this case.
2026 *
2027 * If only one interrupt is available or 'write_queue' == 0, combine
2028 * write and read queues.
2029 *
2030 * If 'write_queues' > 0, ensure it leaves room for at least one read
2031 * queue.
3b6592f7 2032 */
612b7286
ML		 2033 if (!nrirqs) {
2034 nrirqs = 1;
2035 nr_read_queues = 0;
2036 } else if (nrirqs == 1 || !write_queues) {
2037 nr_read_queues = 0;
2038 } else if (write_queues >= nrirqs) {
2039 nr_read_queues = 1;
3b6592f7 2040 } else {
612b7286 2041 nr_read_queues = nrirqs - write_queues;
3b6592f7 2042 }
612b7286
ML		 2043
2044 dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2045 affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2046 dev->io_queues[HCTX_TYPE_READ] = nr_read_queues;
2047 affd->set_size[HCTX_TYPE_READ] = nr_read_queues;
2048 affd->nr_sets = nr_read_queues ? 2 : 1;
3b6592f7
JA		 2049}
2050
6451fe73 2051static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues)
3b6592f7
JA		 2052{
2053 struct pci_dev *pdev = to_pci_dev(dev->dev);
3b6592f7 2054 struct irq_affinity affd = {
9cfef55b 2055 .pre_vectors = 1,
612b7286
ML		 2056 .calc_sets = nvme_calc_irq_sets,
2057 .priv = dev,
3b6592f7 2058 };
6451fe73 2059 unsigned int irq_queues, this_p_queues;
dad77d63 2060 unsigned int nr_cpus = num_possible_cpus();
6451fe73
JA		 2061
2062 /*
2063 * Poll queues don't need interrupts, but we need at least one IO
2064 * queue left over for non-polled IO.
2065 */
2066 this_p_queues = poll_queues;
2067 if (this_p_queues >= nr_io_queues) {
2068 this_p_queues = nr_io_queues - 1;
2069 irq_queues = 1;
2070 } else {
dad77d63
MI		 2071 if (nr_cpus < nr_io_queues - this_p_queues)
2072 irq_queues = nr_cpus + 1;
2073 else
2074 irq_queues = nr_io_queues - this_p_queues + 1;
6451fe73
JA		 2075 }
2076 dev->io_queues[HCTX_TYPE_POLL] = this_p_queues;
3b6592f7 2077
612b7286
ML		 2078 /* Initialize for the single interrupt case */
2079 dev->io_queues[HCTX_TYPE_DEFAULT] = 1;
2080 dev->io_queues[HCTX_TYPE_READ] = 0;
3b6592f7 2081
66341331
BH		 2082 /*
2083 * Some Apple controllers require all queues to use the
2084 * first vector.
2085 */
2086 if (dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR)
2087 irq_queues = 1;
2088
612b7286
ML		 2089 return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues,
2090 PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd);
3b6592f7
JA		 2091}
2092
8fae268b
KB		 2093static void nvme_disable_io_queues(struct nvme_dev *dev)
2094{
2095 if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq))
2096 __nvme_disable_io_queues(dev, nvme_admin_delete_cq);
2097}
2098
8d85fce7 2099static int nvme_setup_io_queues(struct nvme_dev *dev)
b60503ba 2100{
147b27e4 2101 struct nvme_queue *adminq = &dev->queues[0];
e75ec752 2102 struct pci_dev *pdev = to_pci_dev(dev->dev);
97f6ef64
XY		 2103 int result, nr_io_queues;
2104 unsigned long size;
b60503ba 2105
3b6592f7 2106 nr_io_queues = max_io_queues();
d38e9f04
BH		 2107
2108 /*
2109 * If tags are shared with admin queue (Apple bug), then
2110 * make sure we only use one IO queue.
2111 */
2112 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2113 nr_io_queues = 1;
2114
9a0be7ab
CH		 2115 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
2116 if (result < 0)
1b23484b 2117 return result;
9a0be7ab 2118
f5fa90dc 2119 if (nr_io_queues == 0)
a5229050 2120 return 0;
4e224106
CH		 2121
2122 clear_bit(NVMEQ_ENABLED, &adminq->flags);
b60503ba 2123
0f238ff5 2124 if (dev->cmb_use_sqes) {
8ffaadf7
JD		 2125 result = nvme_cmb_qdepth(dev, nr_io_queues,
2126 sizeof(struct nvme_command));
2127 if (result > 0)
2128 dev->q_depth = result;
2129 else
0f238ff5 2130 dev->cmb_use_sqes = false;
8ffaadf7
JD		 2131 }
2132
97f6ef64
XY		 2133 do {
2134 size = db_bar_size(dev, nr_io_queues);
2135 result = nvme_remap_bar(dev, size);
2136 if (!result)
2137 break;
2138 if (!--nr_io_queues)
2139 return -ENOMEM;
2140 } while (1);
2141 adminq->q_db = dev->dbs;
f1938f6e 2142
8fae268b 2143 retry:
9d713c2b 2144 /* Deregister the admin queue's interrupt */
0ff199cb 2145 pci_free_irq(pdev, 0, adminq);
9d713c2b 2146
e32efbfc
JA		 2147 /*
2148 * If we enable msix early due to not intx, disable it again before
2149 * setting up the full range we need.
2150 */
dca51e78 2151 pci_free_irq_vectors(pdev);
3b6592f7
JA		 2152
2153 result = nvme_setup_irqs(dev, nr_io_queues);
22b55601 2154 if (result <= 0)
dca51e78 2155 return -EIO;
3b6592f7 2156
22b55601 2157 dev->num_vecs = result;
4b04cc6a 2158 result = max(result - 1, 1);
e20ba6e1 2159 dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL];
fa08a396 2160
063a8096
MW		 2161 /*
2162 * Should investigate if there's a performance win from allocating
2163 * more queues than interrupt vectors; it might allow the submission
2164 * path to scale better, even if the receive path is limited by the
2165 * number of interrupts.
2166 */
dca51e78 2167 result = queue_request_irq(adminq);
7c349dde 2168 if (result)
d4875622 2169 return result;
4e224106 2170 set_bit(NVMEQ_ENABLED, &adminq->flags);
8fae268b
KB		 2171
2172 result = nvme_create_io_queues(dev);
2173 if (result || dev->online_queues < 2)
2174 return result;
2175
2176 if (dev->online_queues - 1 < dev->max_qid) {
2177 nr_io_queues = dev->online_queues - 1;
2178 nvme_disable_io_queues(dev);
2179 nvme_suspend_io_queues(dev);
2180 goto retry;
2181 }
2182 dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n",
2183 dev->io_queues[HCTX_TYPE_DEFAULT],
2184 dev->io_queues[HCTX_TYPE_READ],
2185 dev->io_queues[HCTX_TYPE_POLL]);
2186 return 0;
b60503ba
MW		 2187}
2188
2a842aca 2189static void nvme_del_queue_end(struct request *req, blk_status_t error)
a5768aa8 2190{
db3cbfff 2191 struct nvme_queue *nvmeq = req->end_io_data;
b5875222 2192
db3cbfff 2193 blk_mq_free_request(req);
d1ed6aa1 2194 complete(&nvmeq->delete_done);
a5768aa8
KB		 2195}
2196
2a842aca 2197static void nvme_del_cq_end(struct request *req, blk_status_t error)
a5768aa8 2198{
db3cbfff 2199 struct nvme_queue *nvmeq = req->end_io_data;
a5768aa8 2200
d1ed6aa1
CH		 2201 if (error)
2202 set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
db3cbfff
KB		 2203
2204 nvme_del_queue_end(req, error);
a5768aa8
KB		 2205}
2206
db3cbfff 2207static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
bda4e0fb 2208{
db3cbfff
KB		 2209 struct request_queue *q = nvmeq->dev->ctrl.admin_q;
2210 struct request *req;
2211 struct nvme_command cmd;
bda4e0fb 2212
db3cbfff
KB		 2213 memset(&cmd, 0, sizeof(cmd));
2214 cmd.delete_queue.opcode = opcode;
2215 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
bda4e0fb 2216
eb71f435 2217 req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
db3cbfff
KB		 2218 if (IS_ERR(req))
2219 return PTR_ERR(req);
bda4e0fb 2220
db3cbfff
KB		 2221 req->timeout = ADMIN_TIMEOUT;
2222 req->end_io_data = nvmeq;
2223
d1ed6aa1 2224 init_completion(&nvmeq->delete_done);
db3cbfff
KB		 2225 blk_execute_rq_nowait(q, NULL, req, false,
2226 opcode == nvme_admin_delete_cq ?
2227 nvme_del_cq_end : nvme_del_queue_end);
2228 return 0;
bda4e0fb
KB		 2229}
2230
8fae268b 2231static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode)
a5768aa8 2232{
5271edd4 2233 int nr_queues = dev->online_queues - 1, sent = 0;
db3cbfff 2234 unsigned long timeout;
a5768aa8 2235
db3cbfff 2236 retry:
5271edd4
CH		 2237 timeout = ADMIN_TIMEOUT;
2238 while (nr_queues > 0) {
2239 if (nvme_delete_queue(&dev->queues[nr_queues], opcode))
2240 break;
2241 nr_queues--;
2242 sent++;
db3cbfff 2243 }
d1ed6aa1
CH		 2244 while (sent) {
2245 struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent];
2246
2247 timeout = wait_for_completion_io_timeout(&nvmeq->delete_done,
5271edd4
CH		 2248 timeout);
2249 if (timeout == 0)
2250 return false;
d1ed6aa1
CH		 2251
2252 /* handle any remaining CQEs */
2253 if (opcode == nvme_admin_delete_cq &&
2254 !test_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags))
2255 nvme_poll_irqdisable(nvmeq, -1);
2256
2257 sent--;
5271edd4
CH		 2258 if (nr_queues)
2259 goto retry;
2260 }
2261 return true;
a5768aa8
KB		 2262}
2263
422ef0c7 2264/*
2b1b7e78 2265 * return error value only when tagset allocation failed
422ef0c7 2266 */
8d85fce7 2267static int nvme_dev_add(struct nvme_dev *dev)
b60503ba 2268{
2b1b7e78
JW		 2269 int ret;
2270
5bae7f73 2271 if (!dev->ctrl.tagset) {
376f7ef8 2272 dev->tagset.ops = &nvme_mq_ops;
ffe7704d 2273 dev->tagset.nr_hw_queues = dev->online_queues - 1;
8fe34be1 2274 dev->tagset.nr_maps = 2; /* default + read */
ed92ad37
CH		 2275 if (dev->io_queues[HCTX_TYPE_POLL])
2276 dev->tagset.nr_maps++;
ffe7704d
KB		 2277 dev->tagset.timeout = NVME_IO_TIMEOUT;
2278 dev->tagset.numa_node = dev_to_node(dev->dev);
2279 dev->tagset.queue_depth =
a4aea562 2280 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
d43f1ccf 2281 dev->tagset.cmd_size = sizeof(struct nvme_iod);
ffe7704d
KB		 2282 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2283 dev->tagset.driver_data = dev;
b60503ba 2284
d38e9f04
BH		 2285 /*
2286 * Some Apple controllers requires tags to be unique
2287 * across admin and IO queue, so reserve the first 32
2288 * tags of the IO queue.
2289 */
2290 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2291 dev->tagset.reserved_tags = NVME_AQ_DEPTH;
2292
2b1b7e78
JW		 2293 ret = blk_mq_alloc_tag_set(&dev->tagset);
2294 if (ret) {
2295 dev_warn(dev->ctrl.device,
2296 "IO queues tagset allocation failed %d\n", ret);
2297 return ret;
2298 }
5bae7f73 2299 dev->ctrl.tagset = &dev->tagset;
949928c1
KB		 2300 } else {
2301 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2302
2303 /* Free previously allocated queues that are no longer usable */
2304 nvme_free_queues(dev, dev->online_queues);
ffe7704d 2305 }
949928c1 2306
e8fd41bb 2307 nvme_dbbuf_set(dev);
e1e5e564 2308 return 0;
b60503ba
MW		 2309}
2310
b00a726a 2311static int nvme_pci_enable(struct nvme_dev *dev)
0877cb0d 2312{
b00a726a 2313 int result = -ENOMEM;
e75ec752 2314 struct pci_dev *pdev = to_pci_dev(dev->dev);
0877cb0d
KB		 2315
2316 if (pci_enable_device_mem(pdev))
2317 return result;
2318
0877cb0d 2319 pci_set_master(pdev);
0877cb0d 2320
4fe06923 2321 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)))
052d0efa 2322 goto disable;
0877cb0d 2323
7a67cbea 2324 if (readl(dev->bar + NVME_REG_CSTS) == -1) {
0e53d180 2325 result = -ENODEV;
b00a726a 2326 goto disable;
0e53d180 2327 }
e32efbfc
JA		 2328
2329 /*
a5229050
KB		 2330 * Some devices and/or platforms don't advertise or work with INTx
2331 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2332 * adjust this later.
e32efbfc 2333 */
dca51e78
CH		 2334 result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
2335 if (result < 0)
2336 return result;
e32efbfc 2337
20d0dfe6 2338 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
7a67cbea 2339
20d0dfe6 2340 dev->q_depth = min_t(int, NVME_CAP_MQES(dev->ctrl.cap) + 1,
b27c1e68 2341 io_queue_depth);
aa22c8e6 2342 dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */
20d0dfe6 2343 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
7a67cbea 2344 dev->dbs = dev->bar + 4096;
1f390c1f 2345
66341331
BH		 2346 /*
2347 * Some Apple controllers require a non-standard SQE size.
2348 * Interestingly they also seem to ignore the CC:IOSQES register
2349 * so we don't bother updating it here.
2350 */
2351 if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES)
2352 dev->io_sqes = 7;
2353 else
2354 dev->io_sqes = NVME_NVM_IOSQES;
1f390c1f
SG		 2355
2356 /*
2357 * Temporary fix for the Apple controller found in the MacBook8,1 and
2358 * some MacBook7,1 to avoid controller resets and data loss.
2359 */
2360 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
2361 dev->q_depth = 2;
9bdcfb10
CH		 2362 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
2363 "set queue depth=%u to work around controller resets\n",
1f390c1f 2364 dev->q_depth);
d554b5e1
MP		 2365 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2366 (pdev->device == 0xa821 || pdev->device == 0xa822) &&
20d0dfe6 2367 NVME_CAP_MQES(dev->ctrl.cap) == 0) {
d554b5e1
MP		 2368 dev->q_depth = 64;
2369 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2370 "set queue depth=%u\n", dev->q_depth);
1f390c1f
SG		 2371 }
2372
d38e9f04
BH		 2373 /*
2374 * Controllers with the shared tags quirk need the IO queue to be
2375 * big enough so that we get 32 tags for the admin queue
2376 */
2377 if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) &&
2378 (dev->q_depth < (NVME_AQ_DEPTH + 2))) {
2379 dev->q_depth = NVME_AQ_DEPTH + 2;
2380 dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n",
2381 dev->q_depth);
2382 }
2383
2384
f65efd6d 2385 nvme_map_cmb(dev);
202021c1 2386
a0a3408e
KB		 2387 pci_enable_pcie_error_reporting(pdev);
2388 pci_save_state(pdev);
0877cb0d
KB		 2389 return 0;
2390
2391 disable:
0877cb0d
KB		 2392 pci_disable_device(pdev);
2393 return result;
2394}
2395
2396static void nvme_dev_unmap(struct nvme_dev *dev)
b00a726a
KB		 2397{
2398 if (dev->bar)
2399 iounmap(dev->bar);
a1f447b3 2400 pci_release_mem_regions(to_pci_dev(dev->dev));
b00a726a
KB		 2401}
2402
2403static void nvme_pci_disable(struct nvme_dev *dev)
0877cb0d 2404{
e75ec752
CH		 2405 struct pci_dev *pdev = to_pci_dev(dev->dev);
2406
dca51e78 2407 pci_free_irq_vectors(pdev);
0877cb0d 2408
a0a3408e
KB		 2409 if (pci_is_enabled(pdev)) {
2410 pci_disable_pcie_error_reporting(pdev);
e75ec752 2411 pci_disable_device(pdev);
4d115420 2412 }
4d115420
KB		 2413}
2414
a5cdb68c 2415static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
b60503ba 2416{
e43269e6 2417 bool dead = true, freeze = false;
302ad8cc 2418 struct pci_dev *pdev = to_pci_dev(dev->dev);
22404274 2419
77bf25ea 2420 mutex_lock(&dev->shutdown_lock);
302ad8cc
KB		 2421 if (pci_is_enabled(pdev)) {
2422 u32 csts = readl(dev->bar + NVME_REG_CSTS);
2423
ebef7368 2424 if (dev->ctrl.state == NVME_CTRL_LIVE ||
e43269e6
KB		 2425 dev->ctrl.state == NVME_CTRL_RESETTING) {
2426 freeze = true;
302ad8cc 2427 nvme_start_freeze(&dev->ctrl);
e43269e6 2428 }
302ad8cc
KB		 2429 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
2430 pdev->error_state != pci_channel_io_normal);
c9d3bf88 2431 }
c21377f8 2432
302ad8cc
KB		 2433 /*
2434 * Give the controller a chance to complete all entered requests if
2435 * doing a safe shutdown.
2436 */
e43269e6
KB		 2437 if (!dead && shutdown && freeze)
2438 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
9a915a5b
JW		 2439
2440 nvme_stop_queues(&dev->ctrl);
87ad72a5 2441
64ee0ac0 2442 if (!dead && dev->ctrl.queue_count > 0) {
8fae268b 2443 nvme_disable_io_queues(dev);
a5cdb68c 2444 nvme_disable_admin_queue(dev, shutdown);
4d115420 2445 }
8fae268b
KB		 2446 nvme_suspend_io_queues(dev);
2447 nvme_suspend_queue(&dev->queues[0]);
b00a726a 2448 nvme_pci_disable(dev);
07836e65 2449
e1958e65
ML		 2450 blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
2451 blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
622b8b68
ML		 2452 blk_mq_tagset_wait_completed_request(&dev->tagset);
2453 blk_mq_tagset_wait_completed_request(&dev->admin_tagset);
302ad8cc
KB		 2454
2455 /*
2456 * The driver will not be starting up queues again if shutting down so
2457 * must flush all entered requests to their failed completion to avoid
2458 * deadlocking blk-mq hot-cpu notifier.
2459 */
c8e9e9b7 2460 if (shutdown) {
302ad8cc 2461 nvme_start_queues(&dev->ctrl);
c8e9e9b7
KB		 2462 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q))
2463 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
2464 }
77bf25ea 2465 mutex_unlock(&dev->shutdown_lock);
b60503ba
MW		 2466}
2467
091b6092
MW		 2468static int nvme_setup_prp_pools(struct nvme_dev *dev)
2469{
e75ec752 2470 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
091b6092
MW		 2471 PAGE_SIZE, PAGE_SIZE, 0);
2472 if (!dev->prp_page_pool)
2473 return -ENOMEM;
2474
99802a7a 2475 /* Optimisation for I/Os between 4k and 128k */
e75ec752 2476 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
99802a7a
MW		 2477 256, 256, 0);
2478 if (!dev->prp_small_pool) {
2479 dma_pool_destroy(dev->prp_page_pool);
2480 return -ENOMEM;
2481 }
091b6092
MW		 2482 return 0;
2483}
2484
2485static void nvme_release_prp_pools(struct nvme_dev *dev)
2486{
2487 dma_pool_destroy(dev->prp_page_pool);
99802a7a 2488 dma_pool_destroy(dev->prp_small_pool);
091b6092
MW		 2489}
2490
1673f1f0 2491static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
5e82e952 2492{
1673f1f0 2493 struct nvme_dev *dev = to_nvme_dev(ctrl);
9ac27090 2494
f9f38e33 2495 nvme_dbbuf_dma_free(dev);
e75ec752 2496 put_device(dev->dev);
4af0e21c
KB		 2497 if (dev->tagset.tags)
2498 blk_mq_free_tag_set(&dev->tagset);
1c63dc66
CH		 2499 if (dev->ctrl.admin_q)
2500 blk_put_queue(dev->ctrl.admin_q);
5e82e952 2501 kfree(dev->queues);
e286bcfc 2502 free_opal_dev(dev->ctrl.opal_dev);
943e942e 2503 mempool_destroy(dev->iod_mempool);
5e82e952
KB		 2504 kfree(dev);
2505}
2506
7c1ce408 2507static void nvme_remove_dead_ctrl(struct nvme_dev *dev)
f58944e2 2508{
d22524a4 2509 nvme_get_ctrl(&dev->ctrl);
69d9a99c 2510 nvme_dev_disable(dev, false);
9f9cafc1 2511 nvme_kill_queues(&dev->ctrl);
03e0f3a6 2512 if (!queue_work(nvme_wq, &dev->remove_work))
f58944e2
KB		 2513 nvme_put_ctrl(&dev->ctrl);
2514}
2515
fd634f41 2516static void nvme_reset_work(struct work_struct *work)
5e82e952 2517{
d86c4d8e
CH		 2518 struct nvme_dev *dev =
2519 container_of(work, struct nvme_dev, ctrl.reset_work);
a98e58e5 2520 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
e71afda4 2521 int result;
2b1b7e78 2522 enum nvme_ctrl_state new_state = NVME_CTRL_LIVE;
5e82e952 2523
e71afda4
CK		 2524 if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING)) {
2525 result = -ENODEV;
fd634f41 2526 goto out;
e71afda4 2527 }
5e82e952 2528
fd634f41
CH		 2529 /*
2530 * If we're called to reset a live controller first shut it down before
2531 * moving on.
2532 */
b00a726a 2533 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
a5cdb68c 2534 nvme_dev_disable(dev, false);
d6135c3a 2535 nvme_sync_queues(&dev->ctrl);
5e82e952 2536
5c959d73 2537 mutex_lock(&dev->shutdown_lock);
b00a726a 2538 result = nvme_pci_enable(dev);
f0b50732 2539 if (result)
4726bcf3 2540 goto out_unlock;
f0b50732 2541
01ad0990 2542 result = nvme_pci_configure_admin_queue(dev);
f0b50732 2543 if (result)
4726bcf3 2544 goto out_unlock;
f0b50732 2545
0fb59cbc
KB		 2546 result = nvme_alloc_admin_tags(dev);
2547 if (result)
4726bcf3 2548 goto out_unlock;
b9afca3e 2549
943e942e
JA		 2550 /*
2551 * Limit the max command size to prevent iod->sg allocations going
2552 * over a single page.
2553 */
7637de31
CH		 2554 dev->ctrl.max_hw_sectors = min_t(u32,
2555 NVME_MAX_KB_SZ << 1, dma_max_mapping_size(dev->dev) >> 9);
943e942e 2556 dev->ctrl.max_segments = NVME_MAX_SEGS;
a48bc520
CH		 2557
2558 /*
2559 * Don't limit the IOMMU merged segment size.
2560 */
2561 dma_set_max_seg_size(dev->dev, 0xffffffff);
2562
5c959d73
KB		 2563 mutex_unlock(&dev->shutdown_lock);
2564
2565 /*
2566 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
2567 * initializing procedure here.
2568 */
2569 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
2570 dev_warn(dev->ctrl.device,
2571 "failed to mark controller CONNECTING\n");
cee6c269 2572 result = -EBUSY;
5c959d73
KB		 2573 goto out;
2574 }
943e942e 2575
ce4541f4
CH		 2576 result = nvme_init_identify(&dev->ctrl);
2577 if (result)
f58944e2 2578 goto out;
ce4541f4 2579
e286bcfc
SB		 2580 if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
2581 if (!dev->ctrl.opal_dev)
2582 dev->ctrl.opal_dev =
2583 init_opal_dev(&dev->ctrl, &nvme_sec_submit);
2584 else if (was_suspend)
2585 opal_unlock_from_suspend(dev->ctrl.opal_dev);
2586 } else {
2587 free_opal_dev(dev->ctrl.opal_dev);
2588 dev->ctrl.opal_dev = NULL;
4f1244c8 2589 }
a98e58e5 2590
f9f38e33
HK		 2591 if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) {
2592 result = nvme_dbbuf_dma_alloc(dev);
2593 if (result)
2594 dev_warn(dev->dev,
2595 "unable to allocate dma for dbbuf\n");
2596 }
2597
9620cfba
CH		 2598 if (dev->ctrl.hmpre) {
2599 result = nvme_setup_host_mem(dev);
2600 if (result < 0)
2601 goto out;
2602 }
87ad72a5 2603
f0b50732 2604 result = nvme_setup_io_queues(dev);
badc34d4 2605 if (result)
f58944e2 2606 goto out;
f0b50732 2607
2659e57b
CH		 2608 /*
2609 * Keep the controller around but remove all namespaces if we don't have
2610 * any working I/O queue.
2611 */
3cf519b5 2612 if (dev->online_queues < 2) {
1b3c47c1 2613 dev_warn(dev->ctrl.device, "IO queues not created\n");
3b24774e 2614 nvme_kill_queues(&dev->ctrl);
5bae7f73 2615 nvme_remove_namespaces(&dev->ctrl);
2b1b7e78 2616 new_state = NVME_CTRL_ADMIN_ONLY;
3cf519b5 2617 } else {
25646264 2618 nvme_start_queues(&dev->ctrl);
302ad8cc 2619 nvme_wait_freeze(&dev->ctrl);
2b1b7e78
JW		 2620 /* hit this only when allocate tagset fails */
2621 if (nvme_dev_add(dev))
2622 new_state = NVME_CTRL_ADMIN_ONLY;
302ad8cc 2623 nvme_unfreeze(&dev->ctrl);
3cf519b5
CH		 2624 }
2625
2b1b7e78
JW		 2626 /*
2627 * If only admin queue live, keep it to do further investigation or
2628 * recovery.
2629 */
2630 if (!nvme_change_ctrl_state(&dev->ctrl, new_state)) {
2631 dev_warn(dev->ctrl.device,
2632 "failed to mark controller state %d\n", new_state);
e71afda4 2633 result = -ENODEV;
bb8d261e
CH		 2634 goto out;
2635 }
92911a55 2636
d09f2b45 2637 nvme_start_ctrl(&dev->ctrl);
3cf519b5 2638 return;
f0b50732 2639
4726bcf3
KB		 2640 out_unlock:
2641 mutex_unlock(&dev->shutdown_lock);
3cf519b5 2642 out:
7c1ce408
CK		 2643 if (result)
2644 dev_warn(dev->ctrl.device,
2645 "Removing after probe failure status: %d\n", result);
2646 nvme_remove_dead_ctrl(dev);
f0b50732
KB		 2647}
2648
5c8809e6 2649static void nvme_remove_dead_ctrl_work(struct work_struct *work)
9a6b9458 2650{
5c8809e6 2651 struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
e75ec752 2652 struct pci_dev *pdev = to_pci_dev(dev->dev);
9a6b9458
KB		 2653
2654 if (pci_get_drvdata(pdev))
921920ab 2655 device_release_driver(&pdev->dev);
1673f1f0 2656 nvme_put_ctrl(&dev->ctrl);
9a6b9458
KB		 2657}
2658
1c63dc66 2659static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
9ca97374 2660{
1c63dc66 2661 *val = readl(to_nvme_dev(ctrl)->bar + off);
90667892 2662 return 0;
9ca97374
TH		 2663}
2664
5fd4ce1b 2665static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
4cc06521 2666{
5fd4ce1b
CH		 2667 writel(val, to_nvme_dev(ctrl)->bar + off);
2668 return 0;
2669}
4cc06521 2670
7fd8930f
CH		 2671static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2672{
2673 *val = readq(to_nvme_dev(ctrl)->bar + off);
2674 return 0;
4cc06521
KB		 2675}
2676
97c12223
KB		 2677static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
2678{
2679 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2680
2681 return snprintf(buf, size, "%s", dev_name(&pdev->dev));
2682}
2683
1c63dc66 2684static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
1a353d85 2685 .name = "pcie",
e439bb12 2686 .module = THIS_MODULE,
e0596ab2
LG		 2687 .flags = NVME_F_METADATA_SUPPORTED |
2688 NVME_F_PCI_P2PDMA,
1c63dc66 2689 .reg_read32 = nvme_pci_reg_read32,
5fd4ce1b 2690 .reg_write32 = nvme_pci_reg_write32,
7fd8930f 2691 .reg_read64 = nvme_pci_reg_read64,
1673f1f0 2692 .free_ctrl = nvme_pci_free_ctrl,
f866fc42 2693 .submit_async_event = nvme_pci_submit_async_event,
97c12223 2694 .get_address = nvme_pci_get_address,
1c63dc66 2695};
4cc06521 2696
b00a726a
KB		 2697static int nvme_dev_map(struct nvme_dev *dev)
2698{
b00a726a
KB		 2699 struct pci_dev *pdev = to_pci_dev(dev->dev);
2700
a1f447b3 2701 if (pci_request_mem_regions(pdev, "nvme"))
b00a726a
KB		 2702 return -ENODEV;
2703
97f6ef64 2704 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
b00a726a
KB		 2705 goto release;
2706
9fa196e7 2707 return 0;
b00a726a 2708 release:
9fa196e7
MG		 2709 pci_release_mem_regions(pdev);
2710 return -ENODEV;
b00a726a
KB		 2711}
2712
8427bbc2 2713static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
ff5350a8
AL		 2714{
2715 if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
2716 /*
2717 * Several Samsung devices seem to drop off the PCIe bus
2718 * randomly when APST is on and uses the deepest sleep state.
2719 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2720 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2721 * 950 PRO 256GB", but it seems to be restricted to two Dell
2722 * laptops.
2723 */
2724 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
2725 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
2726 dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
2727 return NVME_QUIRK_NO_DEEPEST_PS;
8427bbc2
KHF		 2728 } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
2729 /*
2730 * Samsung SSD 960 EVO drops off the PCIe bus after system
467c77d4
JJ		 2731 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
2732 * within few minutes after bootup on a Coffee Lake board -
2733 * ASUS PRIME Z370-A
8427bbc2
KHF		 2734 */
2735 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
467c77d4
JJ		 2736 (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") ||
2737 dmi_match(DMI_BOARD_NAME, "PRIME Z370-A")))
8427bbc2 2738 return NVME_QUIRK_NO_APST;
ff5350a8
AL		 2739 }
2740
2741 return 0;
2742}
2743
18119775
KB		 2744static void nvme_async_probe(void *data, async_cookie_t cookie)
2745{
2746 struct nvme_dev *dev = data;
80f513b5 2747
bd46a906 2748 flush_work(&dev->ctrl.reset_work);
18119775 2749 flush_work(&dev->ctrl.scan_work);
80f513b5 2750 nvme_put_ctrl(&dev->ctrl);
18119775
KB		 2751}
2752
8d85fce7 2753static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
b60503ba 2754{
a4aea562 2755 int node, result = -ENOMEM;
b60503ba 2756 struct nvme_dev *dev;
ff5350a8 2757 unsigned long quirks = id->driver_data;
943e942e 2758 size_t alloc_size;
b60503ba 2759
a4aea562
MB		 2760 node = dev_to_node(&pdev->dev);
2761 if (node == NUMA_NO_NODE)
2fa84351 2762 set_dev_node(&pdev->dev, first_memory_node);
a4aea562
MB		 2763
2764 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
b60503ba
MW		 2765 if (!dev)
2766 return -ENOMEM;
147b27e4 2767
3b6592f7
JA		 2768 dev->queues = kcalloc_node(max_queue_count(), sizeof(struct nvme_queue),
2769 GFP_KERNEL, node);
b60503ba
MW		 2770 if (!dev->queues)
2771 goto free;
2772
e75ec752 2773 dev->dev = get_device(&pdev->dev);
9a6b9458 2774 pci_set_drvdata(pdev, dev);
1c63dc66 2775
b00a726a
KB		 2776 result = nvme_dev_map(dev);
2777 if (result)
b00c9b7a 2778 goto put_pci;
b00a726a 2779
d86c4d8e 2780 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
5c8809e6 2781 INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
77bf25ea 2782 mutex_init(&dev->shutdown_lock);
b60503ba 2783
091b6092
MW		 2784 result = nvme_setup_prp_pools(dev);
2785 if (result)
b00c9b7a 2786 goto unmap;
4cc06521 2787
8427bbc2 2788 quirks |= check_vendor_combination_bug(pdev);
ff5350a8 2789
943e942e
JA		 2790 /*
2791 * Double check that our mempool alloc size will cover the biggest
2792 * command we support.
2793 */
2794 alloc_size = nvme_pci_iod_alloc_size(dev, NVME_MAX_KB_SZ,
2795 NVME_MAX_SEGS, true);
2796 WARN_ON_ONCE(alloc_size > PAGE_SIZE);
2797
2798 dev->iod_mempool = mempool_create_node(1, mempool_kmalloc,
2799 mempool_kfree,
2800 (void *) alloc_size,
2801 GFP_KERNEL, node);
2802 if (!dev->iod_mempool) {
2803 result = -ENOMEM;
2804 goto release_pools;
2805 }
2806
b6e44b4c
KB		 2807 result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
2808 quirks);
2809 if (result)
2810 goto release_mempool;
2811
1b3c47c1
SG		 2812 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
2813
bd46a906 2814 nvme_reset_ctrl(&dev->ctrl);
80f513b5 2815 nvme_get_ctrl(&dev->ctrl);
18119775 2816 async_schedule(nvme_async_probe, dev);
4caff8fc 2817
b60503ba
MW		 2818 return 0;
2819
b6e44b4c
KB		 2820 release_mempool:
2821 mempool_destroy(dev->iod_mempool);
0877cb0d 2822 release_pools:
091b6092 2823 nvme_release_prp_pools(dev);
b00c9b7a
CJ		 2824 unmap:
2825 nvme_dev_unmap(dev);
a96d4f5c 2826 put_pci:
e75ec752 2827 put_device(dev->dev);
b60503ba
MW		 2828 free:
2829 kfree(dev->queues);
b60503ba
MW		 2830 kfree(dev);
2831 return result;
2832}
2833
775755ed 2834static void nvme_reset_prepare(struct pci_dev *pdev)
f0d54a54 2835{
a6739479 2836 struct nvme_dev *dev = pci_get_drvdata(pdev);
f263fbb8 2837 nvme_dev_disable(dev, false);
775755ed 2838}
f0d54a54 2839
775755ed
CH		 2840static void nvme_reset_done(struct pci_dev *pdev)
2841{
f263fbb8 2842 struct nvme_dev *dev = pci_get_drvdata(pdev);
79c48ccf 2843 nvme_reset_ctrl_sync(&dev->ctrl);
f0d54a54
KB		 2844}
2845
09ece142
KB		 2846static void nvme_shutdown(struct pci_dev *pdev)
2847{
2848 struct nvme_dev *dev = pci_get_drvdata(pdev);
a5cdb68c 2849 nvme_dev_disable(dev, true);
09ece142
KB		 2850}
2851
f58944e2
KB		 2852/*
2853 * The driver's remove may be called on a device in a partially initialized
2854 * state. This function must not have any dependencies on the device state in
2855 * order to proceed.
2856 */
8d85fce7 2857static void nvme_remove(struct pci_dev *pdev)
b60503ba
MW		 2858{
2859 struct nvme_dev *dev = pci_get_drvdata(pdev);
9a6b9458 2860
bb8d261e 2861 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
9a6b9458 2862 pci_set_drvdata(pdev, NULL);
0ff9d4e1 2863
6db28eda 2864 if (!pci_device_is_present(pdev)) {
0ff9d4e1 2865 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
1d39e692 2866 nvme_dev_disable(dev, true);
cb4bfda6 2867 nvme_dev_remove_admin(dev);
6db28eda 2868 }
0ff9d4e1 2869
d86c4d8e 2870 flush_work(&dev->ctrl.reset_work);
d09f2b45
SG		 2871 nvme_stop_ctrl(&dev->ctrl);
2872 nvme_remove_namespaces(&dev->ctrl);
a5cdb68c 2873 nvme_dev_disable(dev, true);
9fe5c59f 2874 nvme_release_cmb(dev);
87ad72a5 2875 nvme_free_host_mem(dev);
a4aea562 2876 nvme_dev_remove_admin(dev);
a1a5ef99 2877 nvme_free_queues(dev, 0);
d09f2b45 2878 nvme_uninit_ctrl(&dev->ctrl);
9a6b9458 2879 nvme_release_prp_pools(dev);
b00a726a 2880 nvme_dev_unmap(dev);
1673f1f0 2881 nvme_put_ctrl(&dev->ctrl);
b60503ba
MW		 2882}
2883
671a6018 2884#ifdef CONFIG_PM_SLEEP
d916b1be
KB		 2885static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps)
2886{
2887 return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps);
2888}
2889
2890static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps)
2891{
2892 return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL);
2893}
2894
2895static int nvme_resume(struct device *dev)
2896{
2897 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
2898 struct nvme_ctrl *ctrl = &ndev->ctrl;
2899
4eaefe8c 2900 if (ndev->last_ps == U32_MAX ||
d916b1be
KB		 2901 nvme_set_power_state(ctrl, ndev->last_ps) != 0)
2902 nvme_reset_ctrl(ctrl);
2903 return 0;
2904}
2905
cd638946
KB		 2906static int nvme_suspend(struct device *dev)
2907{
2908 struct pci_dev *pdev = to_pci_dev(dev);
2909 struct nvme_dev *ndev = pci_get_drvdata(pdev);
d916b1be
KB		 2910 struct nvme_ctrl *ctrl = &ndev->ctrl;
2911 int ret = -EBUSY;
2912
4eaefe8c
RW		 2913 ndev->last_ps = U32_MAX;
2914
d916b1be
KB		 2915 /*
2916 * The platform does not remove power for a kernel managed suspend so
2917 * use host managed nvme power settings for lowest idle power if
2918 * possible. This should have quicker resume latency than a full device
2919 * shutdown. But if the firmware is involved after the suspend or the
2920 * device does not support any non-default power states, shut down the
2921 * device fully.
4eaefe8c
RW		 2922 *
2923 * If ASPM is not enabled for the device, shut down the device and allow
2924 * the PCI bus layer to put it into D3 in order to take the PCIe link
2925 * down, so as to allow the platform to achieve its minimum low-power
2926 * state (which may not be possible if the link is up).
d916b1be 2927 */
4eaefe8c 2928 if (pm_suspend_via_firmware() || !ctrl->npss ||
cb32de1b
ML		 2929 !pcie_aspm_enabled(pdev) ||
2930 (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND)) {
d916b1be
KB		 2931 nvme_dev_disable(ndev, true);
2932 return 0;
2933 }
2934
2935 nvme_start_freeze(ctrl);
2936 nvme_wait_freeze(ctrl);
2937 nvme_sync_queues(ctrl);
2938
2939 if (ctrl->state != NVME_CTRL_LIVE &&
2940 ctrl->state != NVME_CTRL_ADMIN_ONLY)
2941 goto unfreeze;
2942
d916b1be
KB		 2943 ret = nvme_get_power_state(ctrl, &ndev->last_ps);
2944 if (ret < 0)
2945 goto unfreeze;
2946
7cbb5c6f
ML		 2947 /*
2948 * A saved state prevents pci pm from generically controlling the
2949 * device's power. If we're using protocol specific settings, we don't
2950 * want pci interfering.
2951 */
2952 pci_save_state(pdev);
2953
d916b1be
KB		 2954 ret = nvme_set_power_state(ctrl, ctrl->npss);
2955 if (ret < 0)
2956 goto unfreeze;
2957
2958 if (ret) {
7cbb5c6f
ML		 2959 /* discard the saved state */
2960 pci_load_saved_state(pdev, NULL);
2961
d916b1be
KB		 2962 /*
2963 * Clearing npss forces a controller reset on resume. The
05d3046f 2964 * correct value will be rediscovered then.
d916b1be
KB		 2965 */
2966 nvme_dev_disable(ndev, true);
2967 ctrl->npss = 0;
2968 ret = 0;
d916b1be 2969 }
d916b1be
KB		 2970unfreeze:
2971 nvme_unfreeze(ctrl);
2972 return ret;
2973}
2974
2975static int nvme_simple_suspend(struct device *dev)
2976{
2977 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
cd638946 2978
a5cdb68c 2979 nvme_dev_disable(ndev, true);
cd638946
KB		 2980 return 0;
2981}
2982
d916b1be 2983static int nvme_simple_resume(struct device *dev)
cd638946
KB		 2984{
2985 struct pci_dev *pdev = to_pci_dev(dev);
2986 struct nvme_dev *ndev = pci_get_drvdata(pdev);
cd638946 2987
d86c4d8e 2988 nvme_reset_ctrl(&ndev->ctrl);
9a6b9458 2989 return 0;
cd638946
KB		 2990}
2991
21774222 2992static const struct dev_pm_ops nvme_dev_pm_ops = {
d916b1be
KB		 2993 .suspend = nvme_suspend,
2994 .resume = nvme_resume,
2995 .freeze = nvme_simple_suspend,
2996 .thaw = nvme_simple_resume,
2997 .poweroff = nvme_simple_suspend,
2998 .restore = nvme_simple_resume,
2999};
3000#endif /* CONFIG_PM_SLEEP */
b60503ba 3001
a0a3408e
KB		 3002static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
3003 pci_channel_state_t state)
3004{
3005 struct nvme_dev *dev = pci_get_drvdata(pdev);
3006
3007 /*
3008 * A frozen channel requires a reset. When detected, this method will
3009 * shutdown the controller to quiesce. The controller will be restarted
3010 * after the slot reset through driver's slot_reset callback.
3011 */
a0a3408e
KB		 3012 switch (state) {
3013 case pci_channel_io_normal:
3014 return PCI_ERS_RESULT_CAN_RECOVER;
3015 case pci_channel_io_frozen:
d011fb31
KB		 3016 dev_warn(dev->ctrl.device,
3017 "frozen state error detected, reset controller\n");
a5cdb68c 3018 nvme_dev_disable(dev, false);
a0a3408e
KB		 3019 return PCI_ERS_RESULT_NEED_RESET;
3020 case pci_channel_io_perm_failure:
d011fb31
KB		 3021 dev_warn(dev->ctrl.device,
3022 "failure state error detected, request disconnect\n");
a0a3408e
KB		 3023 return PCI_ERS_RESULT_DISCONNECT;
3024 }
3025 return PCI_ERS_RESULT_NEED_RESET;
3026}
3027
3028static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
3029{
3030 struct nvme_dev *dev = pci_get_drvdata(pdev);
3031
1b3c47c1 3032 dev_info(dev->ctrl.device, "restart after slot reset\n");
a0a3408e 3033 pci_restore_state(pdev);
d86c4d8e 3034 nvme_reset_ctrl(&dev->ctrl);
a0a3408e
KB		 3035 return PCI_ERS_RESULT_RECOVERED;
3036}
3037
3038static void nvme_error_resume(struct pci_dev *pdev)
3039{
72cd4cc2
KB		 3040 struct nvme_dev *dev = pci_get_drvdata(pdev);
3041
3042 flush_work(&dev->ctrl.reset_work);
a0a3408e
KB		 3043}
3044
1d352035 3045static const struct pci_error_handlers nvme_err_handler = {
b60503ba 3046 .error_detected = nvme_error_detected,
b60503ba
MW		 3047 .slot_reset = nvme_slot_reset,
3048 .resume = nvme_error_resume,
775755ed
CH		 3049 .reset_prepare = nvme_reset_prepare,
3050 .reset_done = nvme_reset_done,
b60503ba
MW		 3051};
3052
6eb0d698 3053static const struct pci_device_id nvme_id_table[] = {
106198ed 3054 { PCI_VDEVICE(INTEL, 0x0953),
08095e70 3055 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 3056 NVME_QUIRK_DEALLOCATE_ZEROES, },
99466e70
KB		 3057 { PCI_VDEVICE(INTEL, 0x0a53),
3058 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 3059 NVME_QUIRK_DEALLOCATE_ZEROES, },
99466e70
KB		 3060 { PCI_VDEVICE(INTEL, 0x0a54),
3061 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 3062 NVME_QUIRK_DEALLOCATE_ZEROES, },
f99cb7af
DWF		 3063 { PCI_VDEVICE(INTEL, 0x0a55),
3064 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3065 NVME_QUIRK_DEALLOCATE_ZEROES, },
50af47d0 3066 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */
9abd68ef
JA		 3067 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3068 NVME_QUIRK_MEDIUM_PRIO_SQ },
6299358d
JD		 3069 { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */
3070 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
540c801c 3071 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */
7b210e4e
CH		 3072 .driver_data = NVME_QUIRK_IDENTIFY_CNS |
3073 NVME_QUIRK_DISABLE_WRITE_ZEROES, },
0302ae60
MP		 3074 { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */
3075 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
54adc010
GP		 3076 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
3077 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
8c97eecc
JL		 3078 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */
3079 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
015282c9
WW		 3080 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
3081 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
d554b5e1
MP		 3082 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */
3083 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3084 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */
3085 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
608cc4b1
CH		 3086 { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */
3087 .driver_data = NVME_QUIRK_LIGHTNVM, },
3088 { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */
3089 .driver_data = NVME_QUIRK_LIGHTNVM, },
ea48e877
WX		 3090 { PCI_DEVICE(0x1d1d, 0x2601), /* CNEX Granby */
3091 .driver_data = NVME_QUIRK_LIGHTNVM, },
08b903b5
MN		 3092 { PCI_DEVICE(0x10ec, 0x5762), /* ADATA SX6000LNP */
3093 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
f03e42c6
GC		 3094 { PCI_DEVICE(0x1cc1, 0x8201), /* ADATA SX8200PNP 512GB */
3095 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3096 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
b60503ba 3097 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
c74dc780 3098 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) },
124298bd 3099 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
66341331
BH		 3100 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005),
3101 .driver_data = NVME_QUIRK_SINGLE_VECTOR |
d38e9f04
BH		 3102 NVME_QUIRK_128_BYTES_SQES |
3103 NVME_QUIRK_SHARED_TAGS },
b60503ba
MW		 3104 { 0, }
3105};
3106MODULE_DEVICE_TABLE(pci, nvme_id_table);
3107
3108static struct pci_driver nvme_driver = {
3109 .name = "nvme",
3110 .id_table = nvme_id_table,
3111 .probe = nvme_probe,
8d85fce7 3112 .remove = nvme_remove,
09ece142 3113 .shutdown = nvme_shutdown,
d916b1be 3114#ifdef CONFIG_PM_SLEEP
cd638946
KB		 3115 .driver = {
3116 .pm = &nvme_dev_pm_ops,
3117 },
d916b1be 3118#endif
74d986ab 3119 .sriov_configure = pci_sriov_configure_simple,
b60503ba
MW		 3120 .err_handler = &nvme_err_handler,
3121};
3122
3123static int __init nvme_init(void)
3124{
81101540
CH		 3125 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
3126 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
3127 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
612b7286 3128 BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2);
9a6327d2 3129 return pci_register_driver(&nvme_driver);
b60503ba
MW		 3130}
3131
3132static void __exit nvme_exit(void)
3133{
3134 pci_unregister_driver(&nvme_driver);
03e0f3a6 3135 flush_workqueue(nvme_wq);
b60503ba
MW		 3136}
3137
3138MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3139MODULE_LICENSE("GPL");
c78b4713 3140MODULE_VERSION("1.0");
b60503ba
MW		 3141module_init(nvme_init);
3142module_exit(nvme_exit);
Linux 6.x block layer and io_uring tree(s)