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nvme-pci: iod's 'aborted' is a bool
[linux-2.6-block.git] / drivers / nvme / host / pci.c
CommitLineData
5f37396d 1// SPDX-License-Identifier: GPL-2.0
b60503ba
MW		 2/*
3 * NVM Express device driver
6eb0d698 4 * Copyright (c) 2011-2014, Intel Corporation.
b60503ba
MW		 5 */
6
df4f9bc4 7#include <linux/acpi.h>
a0a3408e 8#include <linux/aer.h>
18119775 9#include <linux/async.h>
b60503ba 10#include <linux/blkdev.h>
a4aea562 11#include <linux/blk-mq.h>
dca51e78 12#include <linux/blk-mq-pci.h>
fe45e630 13#include <linux/blk-integrity.h>
ff5350a8 14#include <linux/dmi.h>
b60503ba
MW		 15#include <linux/init.h>
16#include <linux/interrupt.h>
17#include <linux/io.h>
dc90f084 18#include <linux/memremap.h>
b60503ba
MW		 19#include <linux/mm.h>
20#include <linux/module.h>
77bf25ea 21#include <linux/mutex.h>
d0877473 22#include <linux/once.h>
b60503ba 23#include <linux/pci.h>
d916b1be 24#include <linux/suspend.h>
e1e5e564 25#include <linux/t10-pi.h>
b60503ba 26#include <linux/types.h>
2f8e2c87 27#include <linux/io-64-nonatomic-lo-hi.h>
20d3bb92 28#include <linux/io-64-nonatomic-hi-lo.h>
a98e58e5 29#include <linux/sed-opal.h>
0f238ff5 30#include <linux/pci-p2pdma.h>
797a796a 31
604c01d5 32#include "trace.h"
f11bb3e2
CH		 33#include "nvme.h"
34
c1e0cc7e 35#define SQ_SIZE(q) ((q)->q_depth << (q)->sqes)
8a1d09a6 36#define CQ_SIZE(q) ((q)->q_depth * sizeof(struct nvme_completion))
c965809c 37
a7a7cbe3 38#define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc))
9d43cf64 39
943e942e
JA		 40/*
41 * These can be higher, but we need to ensure that any command doesn't
42 * require an sg allocation that needs more than a page of data.
43 */
44#define NVME_MAX_KB_SZ 4096
45#define NVME_MAX_SEGS 127
46
58ffacb5 47static int use_threaded_interrupts;
2e21e445 48module_param(use_threaded_interrupts, int, 0444);
58ffacb5 49
8ffaadf7 50static bool use_cmb_sqes = true;
69f4eb9f 51module_param(use_cmb_sqes, bool, 0444);
8ffaadf7
JD		 52MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
53
87ad72a5
CH		 54static unsigned int max_host_mem_size_mb = 128;
55module_param(max_host_mem_size_mb, uint, 0444);
56MODULE_PARM_DESC(max_host_mem_size_mb,
57 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
1fa6aead 58
a7a7cbe3
CK		 59static unsigned int sgl_threshold = SZ_32K;
60module_param(sgl_threshold, uint, 0644);
61MODULE_PARM_DESC(sgl_threshold,
62 "Use SGLs when average request segment size is larger or equal to "
63 "this size. Use 0 to disable SGLs.");
64
27453b45
SG		 65#define NVME_PCI_MIN_QUEUE_SIZE 2
66#define NVME_PCI_MAX_QUEUE_SIZE 4095
b27c1e68 67static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
68static const struct kernel_param_ops io_queue_depth_ops = {
69 .set = io_queue_depth_set,
61f3b896 70 .get = param_get_uint,
b27c1e68 71};
72
61f3b896 73static unsigned int io_queue_depth = 1024;
b27c1e68 74module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
27453b45 75MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2 and < 4096");
b27c1e68 76
9c9e76d5
WZ		 77static int io_queue_count_set(const char *val, const struct kernel_param *kp)
78{
79 unsigned int n;
80 int ret;
81
82 ret = kstrtouint(val, 10, &n);
83 if (ret != 0 || n > num_possible_cpus())
84 return -EINVAL;
85 return param_set_uint(val, kp);
86}
87
88static const struct kernel_param_ops io_queue_count_ops = {
89 .set = io_queue_count_set,
90 .get = param_get_uint,
91};
92
3f68baf7 93static unsigned int write_queues;
9c9e76d5 94module_param_cb(write_queues, &io_queue_count_ops, &write_queues, 0644);
3b6592f7
JA		 95MODULE_PARM_DESC(write_queues,
96 "Number of queues to use for writes. If not set, reads and writes "
97 "will share a queue set.");
98
3f68baf7 99static unsigned int poll_queues;
9c9e76d5 100module_param_cb(poll_queues, &io_queue_count_ops, &poll_queues, 0644);
4b04cc6a
JA		 101MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO.");
102
df4f9bc4
DB		 103static bool noacpi;
104module_param(noacpi, bool, 0444);
105MODULE_PARM_DESC(noacpi, "disable acpi bios quirks");
106
1c63dc66
CH		 107struct nvme_dev;
108struct nvme_queue;
b3fffdef 109
a5cdb68c 110static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
8fae268b 111static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode);
d4b4ff8e 112
1c63dc66
CH		 113/*
114 * Represents an NVM Express device. Each nvme_dev is a PCI function.
115 */
116struct nvme_dev {
147b27e4 117 struct nvme_queue *queues;
1c63dc66
CH		 118 struct blk_mq_tag_set tagset;
119 struct blk_mq_tag_set admin_tagset;
120 u32 __iomem *dbs;
121 struct device *dev;
122 struct dma_pool *prp_page_pool;
123 struct dma_pool *prp_small_pool;
1c63dc66
CH		 124 unsigned online_queues;
125 unsigned max_qid;
e20ba6e1 126 unsigned io_queues[HCTX_MAX_TYPES];
22b55601 127 unsigned int num_vecs;
7442ddce 128 u32 q_depth;
c1e0cc7e 129 int io_sqes;
1c63dc66 130 u32 db_stride;
1c63dc66 131 void __iomem *bar;
97f6ef64 132 unsigned long bar_mapped_size;
5c8809e6 133 struct work_struct remove_work;
77bf25ea 134 struct mutex shutdown_lock;
1c63dc66 135 bool subsystem;
1c63dc66 136 u64 cmb_size;
0f238ff5 137 bool cmb_use_sqes;
1c63dc66 138 u32 cmbsz;
202021c1 139 u32 cmbloc;
1c63dc66 140 struct nvme_ctrl ctrl;
d916b1be 141 u32 last_ps;
a5df5e79 142 bool hmb;
87ad72a5 143
943e942e
JA		 144 mempool_t *iod_mempool;
145
87ad72a5 146 /* shadow doorbell buffer support: */
f9f38e33
HK		 147 u32 *dbbuf_dbs;
148 dma_addr_t dbbuf_dbs_dma_addr;
149 u32 *dbbuf_eis;
150 dma_addr_t dbbuf_eis_dma_addr;
87ad72a5
CH		 151
152 /* host memory buffer support: */
153 u64 host_mem_size;
154 u32 nr_host_mem_descs;
4033f35d 155 dma_addr_t host_mem_descs_dma;
87ad72a5
CH		 156 struct nvme_host_mem_buf_desc *host_mem_descs;
157 void **host_mem_desc_bufs;
2a5bcfdd
WZ		 158 unsigned int nr_allocated_queues;
159 unsigned int nr_write_queues;
160 unsigned int nr_poll_queues;
0521905e
KB		 161
162 bool attrs_added;
4d115420 163};
1fa6aead 164
b27c1e68 165static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
166{
27453b45
SG		 167 return param_set_uint_minmax(val, kp, NVME_PCI_MIN_QUEUE_SIZE,
168 NVME_PCI_MAX_QUEUE_SIZE);
b27c1e68 169}
170
f9f38e33
HK		 171static inline unsigned int sq_idx(unsigned int qid, u32 stride)
172{
173 return qid * 2 * stride;
174}
175
176static inline unsigned int cq_idx(unsigned int qid, u32 stride)
177{
178 return (qid * 2 + 1) * stride;
179}
180
1c63dc66
CH		 181static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
182{
183 return container_of(ctrl, struct nvme_dev, ctrl);
184}
185
b60503ba
MW		 186/*
187 * An NVM Express queue. Each device has at least two (one for admin
188 * commands and one for I/O commands).
189 */
190struct nvme_queue {
091b6092 191 struct nvme_dev *dev;
1ab0cd69 192 spinlock_t sq_lock;
c1e0cc7e 193 void *sq_cmds;
3a7afd8e
CH		 194 /* only used for poll queues: */
195 spinlock_t cq_poll_lock ____cacheline_aligned_in_smp;
74943d45 196 struct nvme_completion *cqes;
b60503ba
MW		 197 dma_addr_t sq_dma_addr;
198 dma_addr_t cq_dma_addr;
b60503ba 199 u32 __iomem *q_db;
7442ddce 200 u32 q_depth;
7c349dde 201 u16 cq_vector;
b60503ba 202 u16 sq_tail;
38210800 203 u16 last_sq_tail;
b60503ba 204 u16 cq_head;
c30341dc 205 u16 qid;
e9539f47 206 u8 cq_phase;
c1e0cc7e 207 u8 sqes;
4e224106
CH		 208 unsigned long flags;
209#define NVMEQ_ENABLED 0
63223078 210#define NVMEQ_SQ_CMB 1
d1ed6aa1 211#define NVMEQ_DELETE_ERROR 2
7c349dde 212#define NVMEQ_POLLED 3
f9f38e33
HK		 213 u32 *dbbuf_sq_db;
214 u32 *dbbuf_cq_db;
215 u32 *dbbuf_sq_ei;
216 u32 *dbbuf_cq_ei;
d1ed6aa1 217 struct completion delete_done;
b60503ba
MW		 218};
219
71bd150c 220/*
9b048119
CH		 221 * The nvme_iod describes the data in an I/O.
222 *
223 * The sg pointer contains the list of PRP/SGL chunk allocations in addition
224 * to the actual struct scatterlist.
71bd150c
CH		 225 */
226struct nvme_iod {
d49187e9 227 struct nvme_request req;
af7fae85 228 struct nvme_command cmd;
a7a7cbe3 229 bool use_sgl;
52da4f3f 230 bool aborted;
71bd150c 231 int npages; /* In the PRP list. 0 means small pool in use */
71bd150c 232 dma_addr_t first_dma;
dff824b2 233 unsigned int dma_len; /* length of single DMA segment mapping */
783b94bd 234 dma_addr_t meta_dma;
91fb2b60 235 struct sg_table sgt;
b60503ba
MW		 236};
237
2a5bcfdd 238static inline unsigned int nvme_dbbuf_size(struct nvme_dev *dev)
3b6592f7 239{
2a5bcfdd 240 return dev->nr_allocated_queues * 8 * dev->db_stride;
f9f38e33
HK		 241}
242
243static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
244{
2a5bcfdd 245 unsigned int mem_size = nvme_dbbuf_size(dev);
f9f38e33 246
58847f12
KB		 247 if (dev->dbbuf_dbs) {
248 /*
249 * Clear the dbbuf memory so the driver doesn't observe stale
250 * values from the previous instantiation.
251 */
252 memset(dev->dbbuf_dbs, 0, mem_size);
253 memset(dev->dbbuf_eis, 0, mem_size);
f9f38e33 254 return 0;
58847f12 255 }
f9f38e33
HK		 256
257 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
258 &dev->dbbuf_dbs_dma_addr,
259 GFP_KERNEL);
260 if (!dev->dbbuf_dbs)
261 return -ENOMEM;
262 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
263 &dev->dbbuf_eis_dma_addr,
264 GFP_KERNEL);
265 if (!dev->dbbuf_eis) {
266 dma_free_coherent(dev->dev, mem_size,
267 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
268 dev->dbbuf_dbs = NULL;
269 return -ENOMEM;
270 }
271
272 return 0;
273}
274
275static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
276{
2a5bcfdd 277 unsigned int mem_size = nvme_dbbuf_size(dev);
f9f38e33
HK		 278
279 if (dev->dbbuf_dbs) {
280 dma_free_coherent(dev->dev, mem_size,
281 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
282 dev->dbbuf_dbs = NULL;
283 }
284 if (dev->dbbuf_eis) {
285 dma_free_coherent(dev->dev, mem_size,
286 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
287 dev->dbbuf_eis = NULL;
288 }
289}
290
291static void nvme_dbbuf_init(struct nvme_dev *dev,
292 struct nvme_queue *nvmeq, int qid)
293{
294 if (!dev->dbbuf_dbs || !qid)
295 return;
296
297 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
298 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
299 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
300 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
301}
302
0f0d2c87
MI		 303static void nvme_dbbuf_free(struct nvme_queue *nvmeq)
304{
305 if (!nvmeq->qid)
306 return;
307
308 nvmeq->dbbuf_sq_db = NULL;
309 nvmeq->dbbuf_cq_db = NULL;
310 nvmeq->dbbuf_sq_ei = NULL;
311 nvmeq->dbbuf_cq_ei = NULL;
312}
313
f9f38e33
HK		 314static void nvme_dbbuf_set(struct nvme_dev *dev)
315{
f66e2804 316 struct nvme_command c = { };
0f0d2c87 317 unsigned int i;
f9f38e33
HK		 318
319 if (!dev->dbbuf_dbs)
320 return;
321
f9f38e33
HK		 322 c.dbbuf.opcode = nvme_admin_dbbuf;
323 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
324 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
325
326 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
9bdcfb10 327 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
f9f38e33
HK		 328 /* Free memory and continue on */
329 nvme_dbbuf_dma_free(dev);
0f0d2c87
MI		 330
331 for (i = 1; i <= dev->online_queues; i++)
332 nvme_dbbuf_free(&dev->queues[i]);
f9f38e33
HK		 333 }
334}
335
336static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
337{
338 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
339}
340
341/* Update dbbuf and return true if an MMIO is required */
342static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
343 volatile u32 *dbbuf_ei)
344{
345 if (dbbuf_db) {
346 u16 old_value;
347
348 /*
349 * Ensure that the queue is written before updating
350 * the doorbell in memory
351 */
352 wmb();
353
354 old_value = *dbbuf_db;
355 *dbbuf_db = value;
356
f1ed3df2
MW		 357 /*
358 * Ensure that the doorbell is updated before reading the event
359 * index from memory. The controller needs to provide similar
360 * ordering to ensure the envent index is updated before reading
361 * the doorbell.
362 */
363 mb();
364
f9f38e33
HK		 365 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value))
366 return false;
367 }
368
369 return true;
b60503ba
MW		 370}
371
ac3dd5bd
JA		 372/*
373 * Will slightly overestimate the number of pages needed. This is OK
374 * as it only leads to a small amount of wasted memory for the lifetime of
375 * the I/O.
376 */
b13c6393 377static int nvme_pci_npages_prp(void)
ac3dd5bd 378{
b13c6393 379 unsigned nprps = DIV_ROUND_UP(NVME_MAX_KB_SZ + NVME_CTRL_PAGE_SIZE,
6c3c05b0 380 NVME_CTRL_PAGE_SIZE);
ac3dd5bd
JA		 381 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
382}
383
a7a7cbe3
CK		 384/*
385 * Calculates the number of pages needed for the SGL segments. For example a 4k
386 * page can accommodate 256 SGL descriptors.
387 */
b13c6393 388static int nvme_pci_npages_sgl(void)
ac3dd5bd 389{
b13c6393
CK		 390 return DIV_ROUND_UP(NVME_MAX_SEGS * sizeof(struct nvme_sgl_desc),
391 PAGE_SIZE);
f4800d6d 392}
ac3dd5bd 393
b13c6393 394static size_t nvme_pci_iod_alloc_size(void)
f4800d6d 395{
b13c6393 396 size_t npages = max(nvme_pci_npages_prp(), nvme_pci_npages_sgl());
a7a7cbe3 397
b13c6393
CK		 398 return sizeof(__le64 *) * npages +
399 sizeof(struct scatterlist) * NVME_MAX_SEGS;
f4800d6d 400}
ac3dd5bd 401
a4aea562
MB		 402static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
403 unsigned int hctx_idx)
e85248e5 404{
a4aea562 405 struct nvme_dev *dev = data;
147b27e4 406 struct nvme_queue *nvmeq = &dev->queues[0];
a4aea562 407
42483228
KB		 408 WARN_ON(hctx_idx != 0);
409 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
42483228 410
a4aea562
MB		 411 hctx->driver_data = nvmeq;
412 return 0;
e85248e5
MW		 413}
414
a4aea562
MB		 415static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
416 unsigned int hctx_idx)
b60503ba 417{
a4aea562 418 struct nvme_dev *dev = data;
147b27e4 419 struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
a4aea562 420
42483228 421 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
a4aea562
MB		 422 hctx->driver_data = nvmeq;
423 return 0;
b60503ba
MW		 424}
425
e559398f
CH		 426static int nvme_pci_init_request(struct blk_mq_tag_set *set,
427 struct request *req, unsigned int hctx_idx,
428 unsigned int numa_node)
b60503ba 429{
d6296d39 430 struct nvme_dev *dev = set->driver_data;
f4800d6d 431 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
59e29ce6
SG		 432
433 nvme_req(req)->ctrl = &dev->ctrl;
f4b9e6c9 434 nvme_req(req)->cmd = &iod->cmd;
a4aea562
MB		 435 return 0;
436}
437
3b6592f7
JA		 438static int queue_irq_offset(struct nvme_dev *dev)
439{
440 /* if we have more than 1 vec, admin queue offsets us by 1 */
441 if (dev->num_vecs > 1)
442 return 1;
443
444 return 0;
445}
446
a4e1d0b7 447static void nvme_pci_map_queues(struct blk_mq_tag_set *set)
dca51e78
CH		 448{
449 struct nvme_dev *dev = set->driver_data;
3b6592f7
JA		 450 int i, qoff, offset;
451
452 offset = queue_irq_offset(dev);
453 for (i = 0, qoff = 0; i < set->nr_maps; i++) {
454 struct blk_mq_queue_map *map = &set->map[i];
455
456 map->nr_queues = dev->io_queues[i];
457 if (!map->nr_queues) {
e20ba6e1 458 BUG_ON(i == HCTX_TYPE_DEFAULT);
7e849dd9 459 continue;
3b6592f7
JA		 460 }
461
4b04cc6a
JA		 462 /*
463 * The poll queue(s) doesn't have an IRQ (and hence IRQ
464 * affinity), so use the regular blk-mq cpu mapping
465 */
3b6592f7 466 map->queue_offset = qoff;
cb9e0e50 467 if (i != HCTX_TYPE_POLL && offset)
4b04cc6a
JA		 468 blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset);
469 else
470 blk_mq_map_queues(map);
3b6592f7
JA		 471 qoff += map->nr_queues;
472 offset += map->nr_queues;
473 }
dca51e78
CH		 474}
475
38210800
KB		 476/*
477 * Write sq tail if we are asked to, or if the next command would wrap.
478 */
479static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq)
04f3eafd 480{
38210800
KB		 481 if (!write_sq) {
482 u16 next_tail = nvmeq->sq_tail + 1;
483
484 if (next_tail == nvmeq->q_depth)
485 next_tail = 0;
486 if (next_tail != nvmeq->last_sq_tail)
487 return;
488 }
489
04f3eafd
JA		 490 if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail,
491 nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei))
492 writel(nvmeq->sq_tail, nvmeq->q_db);
38210800 493 nvmeq->last_sq_tail = nvmeq->sq_tail;
04f3eafd
JA		 494}
495
3233b94c
JA		 496static inline void nvme_sq_copy_cmd(struct nvme_queue *nvmeq,
497 struct nvme_command *cmd)
b60503ba 498{
c1e0cc7e 499 memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes),
3233b94c 500 absolute_pointer(cmd), sizeof(*cmd));
90ea5ca4
CH		 501 if (++nvmeq->sq_tail == nvmeq->q_depth)
502 nvmeq->sq_tail = 0;
04f3eafd
JA		 503}
504
505static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx)
506{
507 struct nvme_queue *nvmeq = hctx->driver_data;
508
509 spin_lock(&nvmeq->sq_lock);
38210800
KB		 510 if (nvmeq->sq_tail != nvmeq->last_sq_tail)
511 nvme_write_sq_db(nvmeq, true);
90ea5ca4 512 spin_unlock(&nvmeq->sq_lock);
b60503ba
MW		 513}
514
a7a7cbe3 515static void **nvme_pci_iod_list(struct request *req)
b60503ba 516{
f4800d6d 517 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
91fb2b60 518 return (void **)(iod->sgt.sgl + blk_rq_nr_phys_segments(req));
b60503ba
MW		 519}
520
955b1b5a
MI		 521static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req)
522{
a53232cb 523 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
20469a37 524 int nseg = blk_rq_nr_phys_segments(req);
955b1b5a
MI		 525 unsigned int avg_seg_size;
526
20469a37 527 avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
955b1b5a 528
253a0b76 529 if (!nvme_ctrl_sgl_supported(&dev->ctrl))
955b1b5a 530 return false;
a53232cb 531 if (!nvmeq->qid)
955b1b5a
MI		 532 return false;
533 if (!sgl_threshold || avg_seg_size < sgl_threshold)
534 return false;
535 return true;
536}
537
9275c206 538static void nvme_free_prps(struct nvme_dev *dev, struct request *req)
b60503ba 539{
6c3c05b0 540 const int last_prp = NVME_CTRL_PAGE_SIZE / sizeof(__le64) - 1;
9275c206
CH		 541 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
542 dma_addr_t dma_addr = iod->first_dma;
eca18b23 543 int i;
eca18b23 544
9275c206
CH		 545 for (i = 0; i < iod->npages; i++) {
546 __le64 *prp_list = nvme_pci_iod_list(req)[i];
547 dma_addr_t next_dma_addr = le64_to_cpu(prp_list[last_prp]);
548
549 dma_pool_free(dev->prp_page_pool, prp_list, dma_addr);
550 dma_addr = next_dma_addr;
7fe07d14 551 }
9275c206 552}
dff824b2 553
9275c206
CH		 554static void nvme_free_sgls(struct nvme_dev *dev, struct request *req)
555{
556 const int last_sg = SGES_PER_PAGE - 1;
557 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
558 dma_addr_t dma_addr = iod->first_dma;
559 int i;
dff824b2 560
9275c206
CH		 561 for (i = 0; i < iod->npages; i++) {
562 struct nvme_sgl_desc *sg_list = nvme_pci_iod_list(req)[i];
563 dma_addr_t next_dma_addr = le64_to_cpu((sg_list[last_sg]).addr);
dff824b2 564
9275c206
CH		 565 dma_pool_free(dev->prp_page_pool, sg_list, dma_addr);
566 dma_addr = next_dma_addr;
567 }
9275c206 568}
a7a7cbe3 569
9275c206
CH		 570static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
571{
572 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3 573
9275c206
CH		 574 if (iod->dma_len) {
575 dma_unmap_page(dev->dev, iod->first_dma, iod->dma_len,
576 rq_dma_dir(req));
577 return;
eca18b23 578 }
ac3dd5bd 579
91fb2b60
LG		 580 WARN_ON_ONCE(!iod->sgt.nents);
581
582 dma_unmap_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req), 0);
9275c206 583
9275c206
CH		 584 if (iod->npages == 0)
585 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0],
586 iod->first_dma);
587 else if (iod->use_sgl)
588 nvme_free_sgls(dev, req);
589 else
590 nvme_free_prps(dev, req);
91fb2b60 591 mempool_free(iod->sgt.sgl, dev->iod_mempool);
b4ff9c8d
KB		 592}
593
d0877473
KB		 594static void nvme_print_sgl(struct scatterlist *sgl, int nents)
595{
596 int i;
597 struct scatterlist *sg;
598
599 for_each_sg(sgl, sg, nents, i) {
600 dma_addr_t phys = sg_phys(sg);
601 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
602 "dma_address:%pad dma_length:%d\n",
603 i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
604 sg_dma_len(sg));
605 }
606}
607
a7a7cbe3
CK		 608static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
609 struct request *req, struct nvme_rw_command *cmnd)
ff22b54f 610{
f4800d6d 611 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
99802a7a 612 struct dma_pool *pool;
b131c61d 613 int length = blk_rq_payload_bytes(req);
91fb2b60 614 struct scatterlist *sg = iod->sgt.sgl;
ff22b54f
MW		 615 int dma_len = sg_dma_len(sg);
616 u64 dma_addr = sg_dma_address(sg);
6c3c05b0 617 int offset = dma_addr & (NVME_CTRL_PAGE_SIZE - 1);
e025344c 618 __le64 *prp_list;
a7a7cbe3 619 void **list = nvme_pci_iod_list(req);
e025344c 620 dma_addr_t prp_dma;
eca18b23 621 int nprps, i;
ff22b54f 622
6c3c05b0 623 length -= (NVME_CTRL_PAGE_SIZE - offset);
5228b328
JS		 624 if (length <= 0) {
625 iod->first_dma = 0;
a7a7cbe3 626 goto done;
5228b328 627 }
ff22b54f 628
6c3c05b0 629 dma_len -= (NVME_CTRL_PAGE_SIZE - offset);
ff22b54f 630 if (dma_len) {
6c3c05b0 631 dma_addr += (NVME_CTRL_PAGE_SIZE - offset);
ff22b54f
MW		 632 } else {
633 sg = sg_next(sg);
634 dma_addr = sg_dma_address(sg);
635 dma_len = sg_dma_len(sg);
636 }
637
6c3c05b0 638 if (length <= NVME_CTRL_PAGE_SIZE) {
edd10d33 639 iod->first_dma = dma_addr;
a7a7cbe3 640 goto done;
e025344c
SMM		 641 }
642
6c3c05b0 643 nprps = DIV_ROUND_UP(length, NVME_CTRL_PAGE_SIZE);
99802a7a
MW		 644 if (nprps <= (256 / 8)) {
645 pool = dev->prp_small_pool;
eca18b23 646 iod->npages = 0;
99802a7a
MW		 647 } else {
648 pool = dev->prp_page_pool;
eca18b23 649 iod->npages = 1;
99802a7a
MW		 650 }
651
69d2b571 652 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
b77954cb 653 if (!prp_list) {
eca18b23 654 iod->npages = -1;
86eea289 655 return BLK_STS_RESOURCE;
b77954cb 656 }
eca18b23
MW		 657 list[0] = prp_list;
658 iod->first_dma = prp_dma;
e025344c
SMM		 659 i = 0;
660 for (;;) {
6c3c05b0 661 if (i == NVME_CTRL_PAGE_SIZE >> 3) {
e025344c 662 __le64 *old_prp_list = prp_list;
69d2b571 663 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
eca18b23 664 if (!prp_list)
fa073216 665 goto free_prps;
eca18b23 666 list[iod->npages++] = prp_list;
7523d834
MW		 667 prp_list[0] = old_prp_list[i - 1];
668 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
669 i = 1;
e025344c
SMM		 670 }
671 prp_list[i++] = cpu_to_le64(dma_addr);
6c3c05b0
CK		 672 dma_len -= NVME_CTRL_PAGE_SIZE;
673 dma_addr += NVME_CTRL_PAGE_SIZE;
674 length -= NVME_CTRL_PAGE_SIZE;
e025344c
SMM		 675 if (length <= 0)
676 break;
677 if (dma_len > 0)
678 continue;
86eea289
KB		 679 if (unlikely(dma_len < 0))
680 goto bad_sgl;
e025344c
SMM		 681 sg = sg_next(sg);
682 dma_addr = sg_dma_address(sg);
683 dma_len = sg_dma_len(sg);
ff22b54f 684 }
a7a7cbe3 685done:
91fb2b60 686 cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sgt.sgl));
a7a7cbe3 687 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
86eea289 688 return BLK_STS_OK;
fa073216
CH		 689free_prps:
690 nvme_free_prps(dev, req);
691 return BLK_STS_RESOURCE;
692bad_sgl:
91fb2b60 693 WARN(DO_ONCE(nvme_print_sgl, iod->sgt.sgl, iod->sgt.nents),
d0877473 694 "Invalid SGL for payload:%d nents:%d\n",
91fb2b60 695 blk_rq_payload_bytes(req), iod->sgt.nents);
86eea289 696 return BLK_STS_IOERR;
ff22b54f
MW		 697}
698
a7a7cbe3
CK		 699static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
700 struct scatterlist *sg)
701{
702 sge->addr = cpu_to_le64(sg_dma_address(sg));
703 sge->length = cpu_to_le32(sg_dma_len(sg));
704 sge->type = NVME_SGL_FMT_DATA_DESC << 4;
705}
706
707static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
708 dma_addr_t dma_addr, int entries)
709{
710 sge->addr = cpu_to_le64(dma_addr);
711 if (entries < SGES_PER_PAGE) {
712 sge->length = cpu_to_le32(entries * sizeof(*sge));
713 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
714 } else {
715 sge->length = cpu_to_le32(PAGE_SIZE);
716 sge->type = NVME_SGL_FMT_SEG_DESC << 4;
717 }
718}
719
720static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
91fb2b60 721 struct request *req, struct nvme_rw_command *cmd)
a7a7cbe3
CK		 722{
723 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3
CK		 724 struct dma_pool *pool;
725 struct nvme_sgl_desc *sg_list;
91fb2b60
LG		 726 struct scatterlist *sg = iod->sgt.sgl;
727 unsigned int entries = iod->sgt.nents;
a7a7cbe3 728 dma_addr_t sgl_dma;
b0f2853b 729 int i = 0;
a7a7cbe3 730
a7a7cbe3
CK		 731 /* setting the transfer type as SGL */
732 cmd->flags = NVME_CMD_SGL_METABUF;
733
b0f2853b 734 if (entries == 1) {
a7a7cbe3
CK		 735 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
736 return BLK_STS_OK;
737 }
738
739 if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
740 pool = dev->prp_small_pool;
741 iod->npages = 0;
742 } else {
743 pool = dev->prp_page_pool;
744 iod->npages = 1;
745 }
746
747 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
748 if (!sg_list) {
749 iod->npages = -1;
750 return BLK_STS_RESOURCE;
751 }
752
753 nvme_pci_iod_list(req)[0] = sg_list;
754 iod->first_dma = sgl_dma;
755
756 nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
757
758 do {
759 if (i == SGES_PER_PAGE) {
760 struct nvme_sgl_desc *old_sg_desc = sg_list;
761 struct nvme_sgl_desc *link = &old_sg_desc[i - 1];
762
763 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
764 if (!sg_list)
fa073216 765 goto free_sgls;
a7a7cbe3
CK		 766
767 i = 0;
768 nvme_pci_iod_list(req)[iod->npages++] = sg_list;
769 sg_list[i++] = *link;
770 nvme_pci_sgl_set_seg(link, sgl_dma, entries);
771 }
772
773 nvme_pci_sgl_set_data(&sg_list[i++], sg);
a7a7cbe3 774 sg = sg_next(sg);
b0f2853b 775 } while (--entries > 0);
a7a7cbe3 776
a7a7cbe3 777 return BLK_STS_OK;
fa073216
CH		 778free_sgls:
779 nvme_free_sgls(dev, req);
780 return BLK_STS_RESOURCE;
a7a7cbe3
CK		 781}
782
dff824b2
CH		 783static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev,
784 struct request *req, struct nvme_rw_command *cmnd,
785 struct bio_vec *bv)
786{
787 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
6c3c05b0
CK		 788 unsigned int offset = bv->bv_offset & (NVME_CTRL_PAGE_SIZE - 1);
789 unsigned int first_prp_len = NVME_CTRL_PAGE_SIZE - offset;
dff824b2
CH		 790
791 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
792 if (dma_mapping_error(dev->dev, iod->first_dma))
793 return BLK_STS_RESOURCE;
794 iod->dma_len = bv->bv_len;
795
796 cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma);
797 if (bv->bv_len > first_prp_len)
798 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len);
359c1f88 799 return BLK_STS_OK;
dff824b2
CH		 800}
801
29791057
CH		 802static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev,
803 struct request *req, struct nvme_rw_command *cmnd,
804 struct bio_vec *bv)
805{
806 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
807
808 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
809 if (dma_mapping_error(dev->dev, iod->first_dma))
810 return BLK_STS_RESOURCE;
811 iod->dma_len = bv->bv_len;
812
049bf372 813 cmnd->flags = NVME_CMD_SGL_METABUF;
29791057
CH		 814 cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma);
815 cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len);
816 cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4;
359c1f88 817 return BLK_STS_OK;
29791057
CH		 818}
819
fc17b653 820static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
b131c61d 821 struct nvme_command *cmnd)
d29ec824 822{
f4800d6d 823 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
70479b71 824 blk_status_t ret = BLK_STS_RESOURCE;
91fb2b60 825 int rc;
d29ec824 826
dff824b2 827 if (blk_rq_nr_phys_segments(req) == 1) {
a53232cb 828 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
dff824b2
CH		 829 struct bio_vec bv = req_bvec(req);
830
831 if (!is_pci_p2pdma_page(bv.bv_page)) {
6c3c05b0 832 if (bv.bv_offset + bv.bv_len <= NVME_CTRL_PAGE_SIZE * 2)
dff824b2
CH		 833 return nvme_setup_prp_simple(dev, req,
834 &cmnd->rw, &bv);
29791057 835
a53232cb 836 if (nvmeq->qid && sgl_threshold &&
253a0b76 837 nvme_ctrl_sgl_supported(&dev->ctrl))
29791057
CH		 838 return nvme_setup_sgl_simple(dev, req,
839 &cmnd->rw, &bv);
dff824b2
CH		 840 }
841 }
842
843 iod->dma_len = 0;
91fb2b60
LG		 844 iod->sgt.sgl = mempool_alloc(dev->iod_mempool, GFP_ATOMIC);
845 if (!iod->sgt.sgl)
d43f1ccf 846 return BLK_STS_RESOURCE;
91fb2b60
LG		 847 sg_init_table(iod->sgt.sgl, blk_rq_nr_phys_segments(req));
848 iod->sgt.orig_nents = blk_rq_map_sg(req->q, req, iod->sgt.sgl);
849 if (!iod->sgt.orig_nents)
fa073216 850 goto out_free_sg;
d29ec824 851
91fb2b60
LG		 852 rc = dma_map_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req),
853 DMA_ATTR_NO_WARN);
854 if (rc) {
855 if (rc == -EREMOTEIO)
856 ret = BLK_STS_TARGET;
fa073216 857 goto out_free_sg;
91fb2b60 858 }
d29ec824 859
70479b71 860 iod->use_sgl = nvme_pci_use_sgls(dev, req);
955b1b5a 861 if (iod->use_sgl)
91fb2b60 862 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw);
a7a7cbe3
CK		 863 else
864 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
86eea289 865 if (ret != BLK_STS_OK)
fa073216
CH		 866 goto out_unmap_sg;
867 return BLK_STS_OK;
868
869out_unmap_sg:
91fb2b60 870 dma_unmap_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req), 0);
fa073216 871out_free_sg:
91fb2b60 872 mempool_free(iod->sgt.sgl, dev->iod_mempool);
4aedb705
CH		 873 return ret;
874}
3045c0d0 875
4aedb705
CH		 876static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req,
877 struct nvme_command *cmnd)
878{
879 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
00df5cb4 880
4aedb705
CH		 881 iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req),
882 rq_dma_dir(req), 0);
883 if (dma_mapping_error(dev->dev, iod->meta_dma))
884 return BLK_STS_IOERR;
885 cmnd->rw.metadata = cpu_to_le64(iod->meta_dma);
359c1f88 886 return BLK_STS_OK;
00df5cb4
MW		 887}
888
62451a2b 889static blk_status_t nvme_prep_rq(struct nvme_dev *dev, struct request *req)
edd10d33 890{
9b048119 891 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
ebe6d874 892 blk_status_t ret;
e1e5e564 893
52da4f3f 894 iod->aborted = false;
9b048119 895 iod->npages = -1;
91fb2b60 896 iod->sgt.nents = 0;
9b048119 897
62451a2b 898 ret = nvme_setup_cmd(req->q->queuedata, req);
fc17b653 899 if (ret)
f4800d6d 900 return ret;
a4aea562 901
fc17b653 902 if (blk_rq_nr_phys_segments(req)) {
62451a2b 903 ret = nvme_map_data(dev, req, &iod->cmd);
fc17b653 904 if (ret)
9b048119 905 goto out_free_cmd;
fc17b653 906 }
a4aea562 907
4aedb705 908 if (blk_integrity_rq(req)) {
62451a2b 909 ret = nvme_map_metadata(dev, req, &iod->cmd);
4aedb705
CH		 910 if (ret)
911 goto out_unmap_data;
912 }
913
aae239e1 914 blk_mq_start_request(req);
fc17b653 915 return BLK_STS_OK;
4aedb705
CH		 916out_unmap_data:
917 nvme_unmap_data(dev, req);
f9d03f96
CH		 918out_free_cmd:
919 nvme_cleanup_cmd(req);
ba1ca37e 920 return ret;
b60503ba 921}
e1e5e564 922
62451a2b
JA		 923/*
924 * NOTE: ns is NULL when called on the admin queue.
925 */
926static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
927 const struct blk_mq_queue_data *bd)
928{
929 struct nvme_queue *nvmeq = hctx->driver_data;
930 struct nvme_dev *dev = nvmeq->dev;
931 struct request *req = bd->rq;
932 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
933 blk_status_t ret;
934
935 /*
936 * We should not need to do this, but we're still using this to
937 * ensure we can drain requests on a dying queue.
938 */
939 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
940 return BLK_STS_IOERR;
941
942 if (unlikely(!nvme_check_ready(&dev->ctrl, req, true)))
943 return nvme_fail_nonready_command(&dev->ctrl, req);
944
945 ret = nvme_prep_rq(dev, req);
946 if (unlikely(ret))
947 return ret;
948 spin_lock(&nvmeq->sq_lock);
949 nvme_sq_copy_cmd(nvmeq, &iod->cmd);
950 nvme_write_sq_db(nvmeq, bd->last);
951 spin_unlock(&nvmeq->sq_lock);
952 return BLK_STS_OK;
953}
954
d62cbcf6
JA		 955static void nvme_submit_cmds(struct nvme_queue *nvmeq, struct request **rqlist)
956{
957 spin_lock(&nvmeq->sq_lock);
958 while (!rq_list_empty(*rqlist)) {
959 struct request *req = rq_list_pop(rqlist);
960 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
961
962 nvme_sq_copy_cmd(nvmeq, &iod->cmd);
963 }
964 nvme_write_sq_db(nvmeq, true);
965 spin_unlock(&nvmeq->sq_lock);
966}
967
968static bool nvme_prep_rq_batch(struct nvme_queue *nvmeq, struct request *req)
969{
970 /*
971 * We should not need to do this, but we're still using this to
972 * ensure we can drain requests on a dying queue.
973 */
974 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
975 return false;
976 if (unlikely(!nvme_check_ready(&nvmeq->dev->ctrl, req, true)))
977 return false;
978
979 req->mq_hctx->tags->rqs[req->tag] = req;
980 return nvme_prep_rq(nvmeq->dev, req) == BLK_STS_OK;
981}
982
983static void nvme_queue_rqs(struct request **rqlist)
984{
6bfec799 985 struct request *req, *next, *prev = NULL;
d62cbcf6
JA		 986 struct request *requeue_list = NULL;
987
6bfec799 988 rq_list_for_each_safe(rqlist, req, next) {
d62cbcf6
JA		 989 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
990
991 if (!nvme_prep_rq_batch(nvmeq, req)) {
992 /* detach 'req' and add to remainder list */
6bfec799
KB		 993 rq_list_move(rqlist, &requeue_list, req, prev);
994
995 req = prev;
996 if (!req)
997 continue;
d62cbcf6
JA		 998 }
999
6bfec799 1000 if (!next || req->mq_hctx != next->mq_hctx) {
d62cbcf6 1001 /* detach rest of list, and submit */
6bfec799 1002 req->rq_next = NULL;
d62cbcf6 1003 nvme_submit_cmds(nvmeq, rqlist);
6bfec799
KB		 1004 *rqlist = next;
1005 prev = NULL;
1006 } else
1007 prev = req;
1008 }
d62cbcf6
JA		 1009
1010 *rqlist = requeue_list;
1011}
1012
c234a653 1013static __always_inline void nvme_pci_unmap_rq(struct request *req)
eee417b0 1014{
a53232cb
KB		 1015 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
1016 struct nvme_dev *dev = nvmeq->dev;
1017
1018 if (blk_integrity_rq(req)) {
1019 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a4aea562 1020
4aedb705
CH		 1021 dma_unmap_page(dev->dev, iod->meta_dma,
1022 rq_integrity_vec(req)->bv_len, rq_data_dir(req));
a53232cb
KB		 1023 }
1024
b15c592d 1025 if (blk_rq_nr_phys_segments(req))
4aedb705 1026 nvme_unmap_data(dev, req);
c234a653
JA		 1027}
1028
1029static void nvme_pci_complete_rq(struct request *req)
1030{
1031 nvme_pci_unmap_rq(req);
77f02a7a 1032 nvme_complete_rq(req);
b60503ba
MW		 1033}
1034
c234a653
JA		 1035static void nvme_pci_complete_batch(struct io_comp_batch *iob)
1036{
1037 nvme_complete_batch(iob, nvme_pci_unmap_rq);
1038}
1039
d783e0bd 1040/* We read the CQE phase first to check if the rest of the entry is valid */
750dde44 1041static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq)
d783e0bd 1042{
74943d45
KB		 1043 struct nvme_completion *hcqe = &nvmeq->cqes[nvmeq->cq_head];
1044
1045 return (le16_to_cpu(READ_ONCE(hcqe->status)) & 1) == nvmeq->cq_phase;
d783e0bd
MR		 1046}
1047
eb281c82 1048static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
b60503ba 1049{
eb281c82 1050 u16 head = nvmeq->cq_head;
adf68f21 1051
397c699f
KB		 1052 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
1053 nvmeq->dbbuf_cq_ei))
1054 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
eb281c82 1055}
aae239e1 1056
cfa27356
CH		 1057static inline struct blk_mq_tags *nvme_queue_tagset(struct nvme_queue *nvmeq)
1058{
1059 if (!nvmeq->qid)
1060 return nvmeq->dev->admin_tagset.tags[0];
1061 return nvmeq->dev->tagset.tags[nvmeq->qid - 1];
1062}
1063
c234a653
JA		 1064static inline void nvme_handle_cqe(struct nvme_queue *nvmeq,
1065 struct io_comp_batch *iob, u16 idx)
83a12fb7 1066{
74943d45 1067 struct nvme_completion *cqe = &nvmeq->cqes[idx];
62df8016 1068 __u16 command_id = READ_ONCE(cqe->command_id);
83a12fb7 1069 struct request *req;
adf68f21 1070
83a12fb7
SG		 1071 /*
1072 * AEN requests are special as they don't time out and can
1073 * survive any kind of queue freeze and often don't respond to
1074 * aborts. We don't even bother to allocate a struct request
1075 * for them but rather special case them here.
1076 */
62df8016 1077 if (unlikely(nvme_is_aen_req(nvmeq->qid, command_id))) {
83a12fb7
SG		 1078 nvme_complete_async_event(&nvmeq->dev->ctrl,
1079 cqe->status, &cqe->result);
a0fa9647 1080 return;
83a12fb7 1081 }
b60503ba 1082
e7006de6 1083 req = nvme_find_rq(nvme_queue_tagset(nvmeq), command_id);
50b7c243
XT		 1084 if (unlikely(!req)) {
1085 dev_warn(nvmeq->dev->ctrl.device,
1086 "invalid id %d completed on queue %d\n",
62df8016 1087 command_id, le16_to_cpu(cqe->sq_id));
50b7c243
XT		 1088 return;
1089 }
1090
604c01d5 1091 trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail);
c234a653
JA		 1092 if (!nvme_try_complete_req(req, cqe->status, cqe->result) &&
1093 !blk_mq_add_to_batch(req, iob, nvme_req(req)->status,
1094 nvme_pci_complete_batch))
ff029451 1095 nvme_pci_complete_rq(req);
83a12fb7 1096}
b60503ba 1097
5cb525c8
JA		 1098static inline void nvme_update_cq_head(struct nvme_queue *nvmeq)
1099{
a0aac973 1100 u32 tmp = nvmeq->cq_head + 1;
a8de6639
AD		 1101
1102 if (tmp == nvmeq->q_depth) {
5cb525c8 1103 nvmeq->cq_head = 0;
e2a366a4 1104 nvmeq->cq_phase ^= 1;
a8de6639
AD		 1105 } else {
1106 nvmeq->cq_head = tmp;
b60503ba 1107 }
a0fa9647
JA		 1108}
1109
c234a653
JA		 1110static inline int nvme_poll_cq(struct nvme_queue *nvmeq,
1111 struct io_comp_batch *iob)
a0fa9647 1112{
1052b8ac 1113 int found = 0;
b60503ba 1114
1052b8ac 1115 while (nvme_cqe_pending(nvmeq)) {
bf392a5d 1116 found++;
b69e2ef2
KB		 1117 /*
1118 * load-load control dependency between phase and the rest of
1119 * the cqe requires a full read memory barrier
1120 */
1121 dma_rmb();
c234a653 1122 nvme_handle_cqe(nvmeq, iob, nvmeq->cq_head);
5cb525c8 1123 nvme_update_cq_head(nvmeq);
920d13a8 1124 }
eb281c82 1125
324b494c 1126 if (found)
920d13a8 1127 nvme_ring_cq_doorbell(nvmeq);
5cb525c8 1128 return found;
b60503ba
MW		 1129}
1130
1131static irqreturn_t nvme_irq(int irq, void *data)
58ffacb5 1132{
58ffacb5 1133 struct nvme_queue *nvmeq = data;
4f502245 1134 DEFINE_IO_COMP_BATCH(iob);
5cb525c8 1135
4f502245
JA		 1136 if (nvme_poll_cq(nvmeq, &iob)) {
1137 if (!rq_list_empty(iob.req_list))
1138 nvme_pci_complete_batch(&iob);
05fae499 1139 return IRQ_HANDLED;
4f502245 1140 }
05fae499 1141 return IRQ_NONE;
58ffacb5
MW		 1142}
1143
1144static irqreturn_t nvme_irq_check(int irq, void *data)
1145{
1146 struct nvme_queue *nvmeq = data;
4e523547 1147
750dde44 1148 if (nvme_cqe_pending(nvmeq))
d783e0bd
MR		 1149 return IRQ_WAKE_THREAD;
1150 return IRQ_NONE;
58ffacb5
MW		 1151}
1152
0b2a8a9f 1153/*
fa059b85 1154 * Poll for completions for any interrupt driven queue
0b2a8a9f
CH		 1155 * Can be called from any context.
1156 */
fa059b85 1157static void nvme_poll_irqdisable(struct nvme_queue *nvmeq)
a0fa9647 1158{
3a7afd8e 1159 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
a0fa9647 1160
fa059b85 1161 WARN_ON_ONCE(test_bit(NVMEQ_POLLED, &nvmeq->flags));
442e19b7 1162
fa059b85 1163 disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
c234a653 1164 nvme_poll_cq(nvmeq, NULL);
fa059b85 1165 enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
a0fa9647
JA		 1166}
1167
5a72e899 1168static int nvme_poll(struct blk_mq_hw_ctx *hctx, struct io_comp_batch *iob)
dabcefab
JA		 1169{
1170 struct nvme_queue *nvmeq = hctx->driver_data;
dabcefab
JA		 1171 bool found;
1172
1173 if (!nvme_cqe_pending(nvmeq))
1174 return 0;
1175
3a7afd8e 1176 spin_lock(&nvmeq->cq_poll_lock);
c234a653 1177 found = nvme_poll_cq(nvmeq, iob);
3a7afd8e 1178 spin_unlock(&nvmeq->cq_poll_lock);
dabcefab 1179
dabcefab
JA		 1180 return found;
1181}
1182
ad22c355 1183static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
b60503ba 1184{
f866fc42 1185 struct nvme_dev *dev = to_nvme_dev(ctrl);
147b27e4 1186 struct nvme_queue *nvmeq = &dev->queues[0];
f66e2804 1187 struct nvme_command c = { };
b60503ba 1188
a4aea562 1189 c.common.opcode = nvme_admin_async_event;
ad22c355 1190 c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
3233b94c
JA		 1191
1192 spin_lock(&nvmeq->sq_lock);
1193 nvme_sq_copy_cmd(nvmeq, &c);
1194 nvme_write_sq_db(nvmeq, true);
1195 spin_unlock(&nvmeq->sq_lock);
f705f837
CH		 1196}
1197
b60503ba 1198static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
f705f837 1199{
f66e2804 1200 struct nvme_command c = { };
b60503ba 1201
b60503ba
MW		 1202 c.delete_queue.opcode = opcode;
1203 c.delete_queue.qid = cpu_to_le16(id);
1204
1c63dc66 1205 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1206}
1207
b60503ba 1208static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
a8e3e0bb 1209 struct nvme_queue *nvmeq, s16 vector)
b60503ba 1210{
f66e2804 1211 struct nvme_command c = { };
4b04cc6a
JA		 1212 int flags = NVME_QUEUE_PHYS_CONTIG;
1213
7c349dde 1214 if (!test_bit(NVMEQ_POLLED, &nvmeq->flags))
4b04cc6a 1215 flags |= NVME_CQ_IRQ_ENABLED;
b60503ba 1216
d29ec824 1217 /*
16772ae6 1218 * Note: we (ab)use the fact that the prp fields survive if no data
d29ec824
CH		 1219 * is attached to the request.
1220 */
b60503ba
MW		 1221 c.create_cq.opcode = nvme_admin_create_cq;
1222 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1223 c.create_cq.cqid = cpu_to_le16(qid);
1224 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1225 c.create_cq.cq_flags = cpu_to_le16(flags);
7c349dde 1226 c.create_cq.irq_vector = cpu_to_le16(vector);
b60503ba 1227
1c63dc66 1228 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1229}
1230
1231static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1232 struct nvme_queue *nvmeq)
1233{
9abd68ef 1234 struct nvme_ctrl *ctrl = &dev->ctrl;
f66e2804 1235 struct nvme_command c = { };
81c1cd98 1236 int flags = NVME_QUEUE_PHYS_CONTIG;
b60503ba 1237
9abd68ef
JA		 1238 /*
1239 * Some drives have a bug that auto-enables WRRU if MEDIUM isn't
1240 * set. Since URGENT priority is zeroes, it makes all queues
1241 * URGENT.
1242 */
1243 if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ)
1244 flags |= NVME_SQ_PRIO_MEDIUM;
1245
d29ec824 1246 /*
16772ae6 1247 * Note: we (ab)use the fact that the prp fields survive if no data
d29ec824
CH		 1248 * is attached to the request.
1249 */
b60503ba
MW		 1250 c.create_sq.opcode = nvme_admin_create_sq;
1251 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1252 c.create_sq.sqid = cpu_to_le16(qid);
1253 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1254 c.create_sq.sq_flags = cpu_to_le16(flags);
1255 c.create_sq.cqid = cpu_to_le16(qid);
1256
1c63dc66 1257 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1258}
1259
1260static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1261{
1262 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1263}
1264
1265static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1266{
1267 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1268}
1269
2a842aca 1270static void abort_endio(struct request *req, blk_status_t error)
bc5fc7e4 1271{
a53232cb 1272 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
e44ac588 1273
27fa9bc5
CH		 1274 dev_warn(nvmeq->dev->ctrl.device,
1275 "Abort status: 0x%x", nvme_req(req)->status);
e7a2a87d 1276 atomic_inc(&nvmeq->dev->ctrl.abort_limit);
e7a2a87d 1277 blk_mq_free_request(req);
bc5fc7e4
MW		 1278}
1279
b2a0eb1a
KB		 1280static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1281{
b2a0eb1a
KB		 1282 /* If true, indicates loss of adapter communication, possibly by a
1283 * NVMe Subsystem reset.
1284 */
1285 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1286
ad70062c
JW		 1287 /* If there is a reset/reinit ongoing, we shouldn't reset again. */
1288 switch (dev->ctrl.state) {
1289 case NVME_CTRL_RESETTING:
ad6a0a52 1290 case NVME_CTRL_CONNECTING:
b2a0eb1a 1291 return false;
ad70062c
JW		 1292 default:
1293 break;
1294 }
b2a0eb1a
KB		 1295
1296 /* We shouldn't reset unless the controller is on fatal error state
1297 * _or_ if we lost the communication with it.
1298 */
1299 if (!(csts & NVME_CSTS_CFS) && !nssro)
1300 return false;
1301
b2a0eb1a
KB		 1302 return true;
1303}
1304
1305static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1306{
1307 /* Read a config register to help see what died. */
1308 u16 pci_status;
1309 int result;
1310
1311 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1312 &pci_status);
1313 if (result == PCIBIOS_SUCCESSFUL)
1314 dev_warn(dev->ctrl.device,
1315 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1316 csts, pci_status);
1317 else
1318 dev_warn(dev->ctrl.device,
1319 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1320 csts, result);
4641a8e6
KB		 1321
1322 if (csts != ~0)
1323 return;
1324
1325 dev_warn(dev->ctrl.device,
1326 "Does your device have a faulty power saving mode enabled?\n");
1327 dev_warn(dev->ctrl.device,
1328 "Try \"nvme_core.default_ps_max_latency_us=0 pcie_aspm=off\" and report a bug\n");
b2a0eb1a
KB		 1329}
1330
9bdb4833 1331static enum blk_eh_timer_return nvme_timeout(struct request *req)
c30341dc 1332{
f4800d6d 1333 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a53232cb 1334 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
c30341dc 1335 struct nvme_dev *dev = nvmeq->dev;
a4aea562 1336 struct request *abort_req;
f66e2804 1337 struct nvme_command cmd = { };
b2a0eb1a
KB		 1338 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1339
651438bb
WX		 1340 /* If PCI error recovery process is happening, we cannot reset or
1341 * the recovery mechanism will surely fail.
1342 */
1343 mb();
1344 if (pci_channel_offline(to_pci_dev(dev->dev)))
1345 return BLK_EH_RESET_TIMER;
1346
b2a0eb1a
KB		 1347 /*
1348 * Reset immediately if the controller is failed
1349 */
1350 if (nvme_should_reset(dev, csts)) {
1351 nvme_warn_reset(dev, csts);
1352 nvme_dev_disable(dev, false);
d86c4d8e 1353 nvme_reset_ctrl(&dev->ctrl);
db8c48e4 1354 return BLK_EH_DONE;
b2a0eb1a 1355 }
c30341dc 1356
7776db1c
KB		 1357 /*
1358 * Did we miss an interrupt?
1359 */
fa059b85 1360 if (test_bit(NVMEQ_POLLED, &nvmeq->flags))
5a72e899 1361 nvme_poll(req->mq_hctx, NULL);
fa059b85
KB		 1362 else
1363 nvme_poll_irqdisable(nvmeq);
1364
bf392a5d 1365 if (blk_mq_request_completed(req)) {
7776db1c
KB		 1366 dev_warn(dev->ctrl.device,
1367 "I/O %d QID %d timeout, completion polled\n",
1368 req->tag, nvmeq->qid);
db8c48e4 1369 return BLK_EH_DONE;
7776db1c
KB		 1370 }
1371
31c7c7d2 1372 /*
fd634f41
CH		 1373 * Shutdown immediately if controller times out while starting. The
1374 * reset work will see the pci device disabled when it gets the forced
1375 * cancellation error. All outstanding requests are completed on
db8c48e4 1376 * shutdown, so we return BLK_EH_DONE.
fd634f41 1377 */
4244140d
KB		 1378 switch (dev->ctrl.state) {
1379 case NVME_CTRL_CONNECTING:
2036f726 1380 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
df561f66 1381 fallthrough;
2036f726 1382 case NVME_CTRL_DELETING:
b9cac43c 1383 dev_warn_ratelimited(dev->ctrl.device,
fd634f41
CH		 1384 "I/O %d QID %d timeout, disable controller\n",
1385 req->tag, nvmeq->qid);
27fa9bc5 1386 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
7ad92f65 1387 nvme_dev_disable(dev, true);
db8c48e4 1388 return BLK_EH_DONE;
39a9dd81
KB		 1389 case NVME_CTRL_RESETTING:
1390 return BLK_EH_RESET_TIMER;
4244140d
KB		 1391 default:
1392 break;
c30341dc
KB		 1393 }
1394
fd634f41 1395 /*
ee0d96d3
BW		 1396 * Shutdown the controller immediately and schedule a reset if the
1397 * command was already aborted once before and still hasn't been
1398 * returned to the driver, or if this is the admin queue.
31c7c7d2 1399 */
f4800d6d 1400 if (!nvmeq->qid || iod->aborted) {
1b3c47c1 1401 dev_warn(dev->ctrl.device,
e1569a16
KB		 1402 "I/O %d QID %d timeout, reset controller\n",
1403 req->tag, nvmeq->qid);
7ad92f65 1404 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
a5cdb68c 1405 nvme_dev_disable(dev, false);
d86c4d8e 1406 nvme_reset_ctrl(&dev->ctrl);
c30341dc 1407
db8c48e4 1408 return BLK_EH_DONE;
c30341dc 1409 }
c30341dc 1410
e7a2a87d 1411 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
6bf25d16 1412 atomic_inc(&dev->ctrl.abort_limit);
31c7c7d2 1413 return BLK_EH_RESET_TIMER;
6bf25d16 1414 }
52da4f3f 1415 iod->aborted = true;
a4aea562 1416
c30341dc 1417 cmd.abort.opcode = nvme_admin_abort_cmd;
85f74acf 1418 cmd.abort.cid = nvme_cid(req);
c30341dc 1419 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
c30341dc 1420
1b3c47c1 1421 dev_warn(nvmeq->dev->ctrl.device,
86141440
CH		 1422 "I/O %d (%s) QID %d timeout, aborting\n",
1423 req->tag,
1424 nvme_get_opcode_str(nvme_req(req)->cmd->common.opcode),
1425 nvmeq->qid);
e7a2a87d 1426
e559398f
CH		 1427 abort_req = blk_mq_alloc_request(dev->ctrl.admin_q, nvme_req_op(&cmd),
1428 BLK_MQ_REQ_NOWAIT);
e7a2a87d
CH		 1429 if (IS_ERR(abort_req)) {
1430 atomic_inc(&dev->ctrl.abort_limit);
1431 return BLK_EH_RESET_TIMER;
1432 }
e559398f 1433 nvme_init_request(abort_req, &cmd);
e7a2a87d 1434
e2e53086 1435 abort_req->end_io = abort_endio;
e7a2a87d 1436 abort_req->end_io_data = NULL;
128126a7 1437 abort_req->rq_flags |= RQF_QUIET;
e2e53086 1438 blk_execute_rq_nowait(abort_req, false);
c30341dc 1439
31c7c7d2
CH		 1440 /*
1441 * The aborted req will be completed on receiving the abort req.
1442 * We enable the timer again. If hit twice, it'll cause a device reset,
1443 * as the device then is in a faulty state.
1444 */
1445 return BLK_EH_RESET_TIMER;
c30341dc
KB		 1446}
1447
a4aea562
MB		 1448static void nvme_free_queue(struct nvme_queue *nvmeq)
1449{
8a1d09a6 1450 dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq),
9e866774 1451 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
63223078
CH		 1452 if (!nvmeq->sq_cmds)
1453 return;
0f238ff5 1454
63223078 1455 if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) {
88a041f4 1456 pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev),
8a1d09a6 1457 nvmeq->sq_cmds, SQ_SIZE(nvmeq));
63223078 1458 } else {
8a1d09a6 1459 dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq),
63223078 1460 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
0f238ff5 1461 }
9e866774
MW		 1462}
1463
a1a5ef99 1464static void nvme_free_queues(struct nvme_dev *dev, int lowest)
22404274
KB		 1465{
1466 int i;
1467
d858e5f0 1468 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
d858e5f0 1469 dev->ctrl.queue_count--;
147b27e4 1470 nvme_free_queue(&dev->queues[i]);
121c7ad4 1471 }
22404274
KB		 1472}
1473
4d115420
KB		 1474/**
1475 * nvme_suspend_queue - put queue into suspended state
40581d1a 1476 * @nvmeq: queue to suspend
4d115420
KB		 1477 */
1478static int nvme_suspend_queue(struct nvme_queue *nvmeq)
b60503ba 1479{
4e224106 1480 if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags))
2b25d981 1481 return 1;
a09115b2 1482
4e224106 1483 /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */
d1f06f4a 1484 mb();
a09115b2 1485
4e224106 1486 nvmeq->dev->online_queues--;
1c63dc66 1487 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
6ca1d902 1488 nvme_stop_admin_queue(&nvmeq->dev->ctrl);
7c349dde
KB		 1489 if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags))
1490 pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq);
4d115420
KB		 1491 return 0;
1492}
b60503ba 1493
8fae268b
KB		 1494static void nvme_suspend_io_queues(struct nvme_dev *dev)
1495{
1496 int i;
1497
1498 for (i = dev->ctrl.queue_count - 1; i > 0; i--)
1499 nvme_suspend_queue(&dev->queues[i]);
1500}
1501
a5cdb68c 1502static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
4d115420 1503{
147b27e4 1504 struct nvme_queue *nvmeq = &dev->queues[0];
4d115420 1505
a5cdb68c
KB		 1506 if (shutdown)
1507 nvme_shutdown_ctrl(&dev->ctrl);
1508 else
b5b05048 1509 nvme_disable_ctrl(&dev->ctrl);
07836e65 1510
bf392a5d 1511 nvme_poll_irqdisable(nvmeq);
b60503ba
MW		 1512}
1513
fa46c6fb
KB		 1514/*
1515 * Called only on a device that has been disabled and after all other threads
9210c075
DZ		 1516 * that can check this device's completion queues have synced, except
1517 * nvme_poll(). This is the last chance for the driver to see a natural
1518 * completion before nvme_cancel_request() terminates all incomplete requests.
fa46c6fb
KB		 1519 */
1520static void nvme_reap_pending_cqes(struct nvme_dev *dev)
1521{
fa46c6fb
KB		 1522 int i;
1523
9210c075
DZ		 1524 for (i = dev->ctrl.queue_count - 1; i > 0; i--) {
1525 spin_lock(&dev->queues[i].cq_poll_lock);
c234a653 1526 nvme_poll_cq(&dev->queues[i], NULL);
9210c075
DZ		 1527 spin_unlock(&dev->queues[i].cq_poll_lock);
1528 }
fa46c6fb
KB		 1529}
1530
8ffaadf7
JD		 1531static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1532 int entry_size)
1533{
1534 int q_depth = dev->q_depth;
5fd4ce1b 1535 unsigned q_size_aligned = roundup(q_depth * entry_size,
6c3c05b0 1536 NVME_CTRL_PAGE_SIZE);
8ffaadf7
JD		 1537
1538 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
c45f5c99 1539 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
4e523547 1540
6c3c05b0 1541 mem_per_q = round_down(mem_per_q, NVME_CTRL_PAGE_SIZE);
c45f5c99 1542 q_depth = div_u64(mem_per_q, entry_size);
8ffaadf7
JD		 1543
1544 /*
1545 * Ensure the reduced q_depth is above some threshold where it
1546 * would be better to map queues in system memory with the
1547 * original depth
1548 */
1549 if (q_depth < 64)
1550 return -ENOMEM;
1551 }
1552
1553 return q_depth;
1554}
1555
1556static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
8a1d09a6 1557 int qid)
8ffaadf7 1558{
0f238ff5
LG		 1559 struct pci_dev *pdev = to_pci_dev(dev->dev);
1560
1561 if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
8a1d09a6 1562 nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq));
bfac8e9f
AM		 1563 if (nvmeq->sq_cmds) {
1564 nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev,
1565 nvmeq->sq_cmds);
1566 if (nvmeq->sq_dma_addr) {
1567 set_bit(NVMEQ_SQ_CMB, &nvmeq->flags);
1568 return 0;
1569 }
1570
8a1d09a6 1571 pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq));
63223078 1572 }
0f238ff5 1573 }
8ffaadf7 1574
8a1d09a6 1575 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq),
63223078 1576 &nvmeq->sq_dma_addr, GFP_KERNEL);
815c6704
KB		 1577 if (!nvmeq->sq_cmds)
1578 return -ENOMEM;
8ffaadf7
JD		 1579 return 0;
1580}
1581
a6ff7262 1582static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
b60503ba 1583{
147b27e4 1584 struct nvme_queue *nvmeq = &dev->queues[qid];
b60503ba 1585
62314e40
KB		 1586 if (dev->ctrl.queue_count > qid)
1587 return 0;
b60503ba 1588
c1e0cc7e 1589 nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES;
8a1d09a6
BH		 1590 nvmeq->q_depth = depth;
1591 nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq),
750afb08 1592 &nvmeq->cq_dma_addr, GFP_KERNEL);
b60503ba
MW		 1593 if (!nvmeq->cqes)
1594 goto free_nvmeq;
b60503ba 1595
8a1d09a6 1596 if (nvme_alloc_sq_cmds(dev, nvmeq, qid))
b60503ba
MW		 1597 goto free_cqdma;
1598
091b6092 1599 nvmeq->dev = dev;
1ab0cd69 1600 spin_lock_init(&nvmeq->sq_lock);
3a7afd8e 1601 spin_lock_init(&nvmeq->cq_poll_lock);
b60503ba 1602 nvmeq->cq_head = 0;
82123460 1603 nvmeq->cq_phase = 1;
b80d5ccc 1604 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
c30341dc 1605 nvmeq->qid = qid;
d858e5f0 1606 dev->ctrl.queue_count++;
36a7e993 1607
147b27e4 1608 return 0;
b60503ba
MW		 1609
1610 free_cqdma:
8a1d09a6
BH		 1611 dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes,
1612 nvmeq->cq_dma_addr);
b60503ba 1613 free_nvmeq:
147b27e4 1614 return -ENOMEM;
b60503ba
MW		 1615}
1616
dca51e78 1617static int queue_request_irq(struct nvme_queue *nvmeq)
3001082c 1618{
0ff199cb
CH		 1619 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1620 int nr = nvmeq->dev->ctrl.instance;
1621
1622 if (use_threaded_interrupts) {
1623 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1624 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1625 } else {
1626 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1627 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1628 }
3001082c
MW		 1629}
1630
22404274 1631static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
b60503ba 1632{
22404274 1633 struct nvme_dev *dev = nvmeq->dev;
b60503ba 1634
22404274 1635 nvmeq->sq_tail = 0;
38210800 1636 nvmeq->last_sq_tail = 0;
22404274
KB		 1637 nvmeq->cq_head = 0;
1638 nvmeq->cq_phase = 1;
b80d5ccc 1639 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
8a1d09a6 1640 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq));
f9f38e33 1641 nvme_dbbuf_init(dev, nvmeq, qid);
42f61420 1642 dev->online_queues++;
3a7afd8e 1643 wmb(); /* ensure the first interrupt sees the initialization */
22404274
KB		 1644}
1645
e4b9852a
CC		 1646/*
1647 * Try getting shutdown_lock while setting up IO queues.
1648 */
1649static int nvme_setup_io_queues_trylock(struct nvme_dev *dev)
1650{
1651 /*
1652 * Give up if the lock is being held by nvme_dev_disable.
1653 */
1654 if (!mutex_trylock(&dev->shutdown_lock))
1655 return -ENODEV;
1656
1657 /*
1658 * Controller is in wrong state, fail early.
1659 */
1660 if (dev->ctrl.state != NVME_CTRL_CONNECTING) {
1661 mutex_unlock(&dev->shutdown_lock);
1662 return -ENODEV;
1663 }
1664
1665 return 0;
1666}
1667
4b04cc6a 1668static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled)
22404274
KB		 1669{
1670 struct nvme_dev *dev = nvmeq->dev;
1671 int result;
7c349dde 1672 u16 vector = 0;
3f85d50b 1673
d1ed6aa1
CH		 1674 clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
1675
22b55601
KB		 1676 /*
1677 * A queue's vector matches the queue identifier unless the controller
1678 * has only one vector available.
1679 */
4b04cc6a
JA		 1680 if (!polled)
1681 vector = dev->num_vecs == 1 ? 0 : qid;
1682 else
7c349dde 1683 set_bit(NVMEQ_POLLED, &nvmeq->flags);
4b04cc6a 1684
a8e3e0bb 1685 result = adapter_alloc_cq(dev, qid, nvmeq, vector);
ded45505
KB		 1686 if (result)
1687 return result;
b60503ba
MW		 1688
1689 result = adapter_alloc_sq(dev, qid, nvmeq);
1690 if (result < 0)
ded45505 1691 return result;
c80b36cd 1692 if (result)
b60503ba
MW		 1693 goto release_cq;
1694
a8e3e0bb 1695 nvmeq->cq_vector = vector;
4b04cc6a 1696
e4b9852a
CC		 1697 result = nvme_setup_io_queues_trylock(dev);
1698 if (result)
1699 return result;
1700 nvme_init_queue(nvmeq, qid);
7c349dde 1701 if (!polled) {
4b04cc6a
JA		 1702 result = queue_request_irq(nvmeq);
1703 if (result < 0)
1704 goto release_sq;
1705 }
b60503ba 1706
4e224106 1707 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
e4b9852a 1708 mutex_unlock(&dev->shutdown_lock);
22404274 1709 return result;
b60503ba 1710
a8e3e0bb 1711release_sq:
f25a2dfc 1712 dev->online_queues--;
e4b9852a 1713 mutex_unlock(&dev->shutdown_lock);
b60503ba 1714 adapter_delete_sq(dev, qid);
a8e3e0bb 1715release_cq:
b60503ba 1716 adapter_delete_cq(dev, qid);
22404274 1717 return result;
b60503ba
MW		 1718}
1719
f363b089 1720static const struct blk_mq_ops nvme_mq_admin_ops = {
d29ec824 1721 .queue_rq = nvme_queue_rq,
77f02a7a 1722 .complete = nvme_pci_complete_rq,
a4aea562 1723 .init_hctx = nvme_admin_init_hctx,
e559398f 1724 .init_request = nvme_pci_init_request,
a4aea562
MB		 1725 .timeout = nvme_timeout,
1726};
1727
f363b089 1728static const struct blk_mq_ops nvme_mq_ops = {
376f7ef8 1729 .queue_rq = nvme_queue_rq,
d62cbcf6 1730 .queue_rqs = nvme_queue_rqs,
376f7ef8
CH		 1731 .complete = nvme_pci_complete_rq,
1732 .commit_rqs = nvme_commit_rqs,
1733 .init_hctx = nvme_init_hctx,
e559398f 1734 .init_request = nvme_pci_init_request,
376f7ef8
CH		 1735 .map_queues = nvme_pci_map_queues,
1736 .timeout = nvme_timeout,
1737 .poll = nvme_poll,
dabcefab
JA		 1738};
1739
ea191d2f
KB		 1740static void nvme_dev_remove_admin(struct nvme_dev *dev)
1741{
1c63dc66 1742 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
69d9a99c
KB		 1743 /*
1744 * If the controller was reset during removal, it's possible
1745 * user requests may be waiting on a stopped queue. Start the
1746 * queue to flush these to completion.
1747 */
6ca1d902 1748 nvme_start_admin_queue(&dev->ctrl);
6f8191fd 1749 blk_mq_destroy_queue(dev->ctrl.admin_q);
ea191d2f
KB		 1750 blk_mq_free_tag_set(&dev->admin_tagset);
1751 }
1752}
1753
f91b727c 1754static int nvme_pci_alloc_admin_tag_set(struct nvme_dev *dev)
a4aea562 1755{
f91b727c 1756 struct blk_mq_tag_set *set = &dev->admin_tagset;
e3e9d50c 1757
f91b727c
CH		 1758 set->ops = &nvme_mq_admin_ops;
1759 set->nr_hw_queues = 1;
a4aea562 1760
f91b727c
CH		 1761 set->queue_depth = NVME_AQ_MQ_TAG_DEPTH;
1762 set->timeout = NVME_ADMIN_TIMEOUT;
1763 set->numa_node = dev->ctrl.numa_node;
1764 set->cmd_size = sizeof(struct nvme_iod);
1765 set->flags = BLK_MQ_F_NO_SCHED;
1766 set->driver_data = dev;
a4aea562 1767
f91b727c
CH		 1768 if (blk_mq_alloc_tag_set(set))
1769 return -ENOMEM;
1770 dev->ctrl.admin_tagset = set;
a4aea562 1771
f91b727c
CH		 1772 dev->ctrl.admin_q = blk_mq_init_queue(set);
1773 if (IS_ERR(dev->ctrl.admin_q)) {
1774 blk_mq_free_tag_set(set);
1775 dev->ctrl.admin_q = NULL;
1776 return -ENOMEM;
1777 }
1778 if (!blk_get_queue(dev->ctrl.admin_q)) {
1779 nvme_dev_remove_admin(dev);
1780 dev->ctrl.admin_q = NULL;
1781 return -ENODEV;
1782 }
a4aea562
MB		 1783 return 0;
1784}
1785
97f6ef64
XY		 1786static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1787{
1788 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1789}
1790
1791static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1792{
1793 struct pci_dev *pdev = to_pci_dev(dev->dev);
1794
1795 if (size <= dev->bar_mapped_size)
1796 return 0;
1797 if (size > pci_resource_len(pdev, 0))
1798 return -ENOMEM;
1799 if (dev->bar)
1800 iounmap(dev->bar);
1801 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1802 if (!dev->bar) {
1803 dev->bar_mapped_size = 0;
1804 return -ENOMEM;
1805 }
1806 dev->bar_mapped_size = size;
1807 dev->dbs = dev->bar + NVME_REG_DBS;
1808
1809 return 0;
1810}
1811
01ad0990 1812static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
b60503ba 1813{
ba47e386 1814 int result;
b60503ba
MW		 1815 u32 aqa;
1816 struct nvme_queue *nvmeq;
1817
97f6ef64
XY		 1818 result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1819 if (result < 0)
1820 return result;
1821
8ef2074d 1822 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
20d0dfe6 1823 NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
dfbac8c7 1824
7a67cbea
CH		 1825 if (dev->subsystem &&
1826 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1827 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
dfbac8c7 1828
b5b05048 1829 result = nvme_disable_ctrl(&dev->ctrl);
ba47e386
MW		 1830 if (result < 0)
1831 return result;
b60503ba 1832
a6ff7262 1833 result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
147b27e4
SG		 1834 if (result)
1835 return result;
b60503ba 1836
635333e4
MG		 1837 dev->ctrl.numa_node = dev_to_node(dev->dev);
1838
147b27e4 1839 nvmeq = &dev->queues[0];
b60503ba
MW		 1840 aqa = nvmeq->q_depth - 1;
1841 aqa |= aqa << 16;
1842
7a67cbea
CH		 1843 writel(aqa, dev->bar + NVME_REG_AQA);
1844 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1845 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
b60503ba 1846
c0f2f45b 1847 result = nvme_enable_ctrl(&dev->ctrl);
025c557a 1848 if (result)
d4875622 1849 return result;
a4aea562 1850
2b25d981 1851 nvmeq->cq_vector = 0;
161b8be2 1852 nvme_init_queue(nvmeq, 0);
dca51e78 1853 result = queue_request_irq(nvmeq);
758dd7fd 1854 if (result) {
7c349dde 1855 dev->online_queues--;
d4875622 1856 return result;
758dd7fd 1857 }
025c557a 1858
4e224106 1859 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
b60503ba
MW		 1860 return result;
1861}
1862
749941f2 1863static int nvme_create_io_queues(struct nvme_dev *dev)
42f61420 1864{
4b04cc6a 1865 unsigned i, max, rw_queues;
749941f2 1866 int ret = 0;
42f61420 1867
d858e5f0 1868 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
a6ff7262 1869 if (nvme_alloc_queue(dev, i, dev->q_depth)) {
749941f2 1870 ret = -ENOMEM;
42f61420 1871 break;
749941f2
CH		 1872 }
1873 }
42f61420 1874
d858e5f0 1875 max = min(dev->max_qid, dev->ctrl.queue_count - 1);
e20ba6e1
CH		 1876 if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) {
1877 rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] +
1878 dev->io_queues[HCTX_TYPE_READ];
4b04cc6a
JA		 1879 } else {
1880 rw_queues = max;
1881 }
1882
949928c1 1883 for (i = dev->online_queues; i <= max; i++) {
4b04cc6a
JA		 1884 bool polled = i > rw_queues;
1885
1886 ret = nvme_create_queue(&dev->queues[i], i, polled);
d4875622 1887 if (ret)
42f61420 1888 break;
27e8166c 1889 }
749941f2
CH		 1890
1891 /*
1892 * Ignore failing Create SQ/CQ commands, we can continue with less
8adb8c14
MI		 1893 * than the desired amount of queues, and even a controller without
1894 * I/O queues can still be used to issue admin commands. This might
749941f2
CH		 1895 * be useful to upgrade a buggy firmware for example.
1896 */
1897 return ret >= 0 ? 0 : ret;
b60503ba
MW		 1898}
1899
88de4598 1900static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
8ffaadf7 1901{
88de4598
CH		 1902 u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
1903
1904 return 1ULL << (12 + 4 * szu);
1905}
1906
1907static u32 nvme_cmb_size(struct nvme_dev *dev)
1908{
1909 return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
1910}
1911
f65efd6d 1912static void nvme_map_cmb(struct nvme_dev *dev)
8ffaadf7 1913{
88de4598 1914 u64 size, offset;
8ffaadf7
JD		 1915 resource_size_t bar_size;
1916 struct pci_dev *pdev = to_pci_dev(dev->dev);
8969f1f8 1917 int bar;
8ffaadf7 1918
9fe5c59f
KB		 1919 if (dev->cmb_size)
1920 return;
1921
20d3bb92
KJ		 1922 if (NVME_CAP_CMBS(dev->ctrl.cap))
1923 writel(NVME_CMBMSC_CRE, dev->bar + NVME_REG_CMBMSC);
1924
7a67cbea 1925 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
f65efd6d
CH		 1926 if (!dev->cmbsz)
1927 return;
202021c1 1928 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
8ffaadf7 1929
88de4598
CH		 1930 size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
1931 offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
8969f1f8
CH		 1932 bar = NVME_CMB_BIR(dev->cmbloc);
1933 bar_size = pci_resource_len(pdev, bar);
8ffaadf7
JD		 1934
1935 if (offset > bar_size)
f65efd6d 1936 return;
8ffaadf7 1937
20d3bb92
KJ		 1938 /*
1939 * Tell the controller about the host side address mapping the CMB,
1940 * and enable CMB decoding for the NVMe 1.4+ scheme:
1941 */
1942 if (NVME_CAP_CMBS(dev->ctrl.cap)) {
1943 hi_lo_writeq(NVME_CMBMSC_CRE | NVME_CMBMSC_CMSE |
1944 (pci_bus_address(pdev, bar) + offset),
1945 dev->bar + NVME_REG_CMBMSC);
1946 }
1947
8ffaadf7
JD		 1948 /*
1949 * Controllers may support a CMB size larger than their BAR,
1950 * for example, due to being behind a bridge. Reduce the CMB to
1951 * the reported size of the BAR
1952 */
1953 if (size > bar_size - offset)
1954 size = bar_size - offset;
1955
0f238ff5
LG		 1956 if (pci_p2pdma_add_resource(pdev, bar, size, offset)) {
1957 dev_warn(dev->ctrl.device,
1958 "failed to register the CMB\n");
f65efd6d 1959 return;
0f238ff5
LG		 1960 }
1961
8ffaadf7 1962 dev->cmb_size = size;
0f238ff5
LG		 1963 dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS);
1964
1965 if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) ==
1966 (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS))
1967 pci_p2pmem_publish(pdev, true);
8ffaadf7
JD		 1968}
1969
87ad72a5
CH		 1970static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1971{
6c3c05b0 1972 u32 host_mem_size = dev->host_mem_size >> NVME_CTRL_PAGE_SHIFT;
4033f35d 1973 u64 dma_addr = dev->host_mem_descs_dma;
f66e2804 1974 struct nvme_command c = { };
87ad72a5
CH		 1975 int ret;
1976
87ad72a5
CH		 1977 c.features.opcode = nvme_admin_set_features;
1978 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1979 c.features.dword11 = cpu_to_le32(bits);
6c3c05b0 1980 c.features.dword12 = cpu_to_le32(host_mem_size);
87ad72a5
CH		 1981 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr));
1982 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr));
1983 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs);
1984
1985 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1986 if (ret) {
1987 dev_warn(dev->ctrl.device,
1988 "failed to set host mem (err %d, flags %#x).\n",
1989 ret, bits);
a5df5e79
KB		 1990 } else
1991 dev->hmb = bits & NVME_HOST_MEM_ENABLE;
1992
87ad72a5
CH		 1993 return ret;
1994}
1995
1996static void nvme_free_host_mem(struct nvme_dev *dev)
1997{
1998 int i;
1999
2000 for (i = 0; i < dev->nr_host_mem_descs; i++) {
2001 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
6c3c05b0 2002 size_t size = le32_to_cpu(desc->size) * NVME_CTRL_PAGE_SIZE;
87ad72a5 2003
cc667f6d
LD		 2004 dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i],
2005 le64_to_cpu(desc->addr),
2006 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
87ad72a5
CH		 2007 }
2008
2009 kfree(dev->host_mem_desc_bufs);
2010 dev->host_mem_desc_bufs = NULL;
4033f35d
CH		 2011 dma_free_coherent(dev->dev,
2012 dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
2013 dev->host_mem_descs, dev->host_mem_descs_dma);
87ad72a5 2014 dev->host_mem_descs = NULL;
7e5dd57e 2015 dev->nr_host_mem_descs = 0;
87ad72a5
CH		 2016}
2017
92dc6895
CH		 2018static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
2019 u32 chunk_size)
9d713c2b 2020{
87ad72a5 2021 struct nvme_host_mem_buf_desc *descs;
92dc6895 2022 u32 max_entries, len;
4033f35d 2023 dma_addr_t descs_dma;
2ee0e4ed 2024 int i = 0;
87ad72a5 2025 void **bufs;
6fbcde66 2026 u64 size, tmp;
87ad72a5 2027
87ad72a5
CH		 2028 tmp = (preferred + chunk_size - 1);
2029 do_div(tmp, chunk_size);
2030 max_entries = tmp;
044a9df1
CH		 2031
2032 if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
2033 max_entries = dev->ctrl.hmmaxd;
2034
750afb08
LC		 2035 descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs),
2036 &descs_dma, GFP_KERNEL);
87ad72a5
CH		 2037 if (!descs)
2038 goto out;
2039
2040 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
2041 if (!bufs)
2042 goto out_free_descs;
2043
244a8fe4 2044 for (size = 0; size < preferred && i < max_entries; size += len) {
87ad72a5
CH		 2045 dma_addr_t dma_addr;
2046
50cdb7c6 2047 len = min_t(u64, chunk_size, preferred - size);
87ad72a5
CH		 2048 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
2049 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
2050 if (!bufs[i])
2051 break;
2052
2053 descs[i].addr = cpu_to_le64(dma_addr);
6c3c05b0 2054 descs[i].size = cpu_to_le32(len / NVME_CTRL_PAGE_SIZE);
87ad72a5
CH		 2055 i++;
2056 }
2057
92dc6895 2058 if (!size)
87ad72a5 2059 goto out_free_bufs;
87ad72a5 2060
87ad72a5
CH		 2061 dev->nr_host_mem_descs = i;
2062 dev->host_mem_size = size;
2063 dev->host_mem_descs = descs;
4033f35d 2064 dev->host_mem_descs_dma = descs_dma;
87ad72a5
CH		 2065 dev->host_mem_desc_bufs = bufs;
2066 return 0;
2067
2068out_free_bufs:
2069 while (--i >= 0) {
6c3c05b0 2070 size_t size = le32_to_cpu(descs[i].size) * NVME_CTRL_PAGE_SIZE;
87ad72a5 2071
cc667f6d
LD		 2072 dma_free_attrs(dev->dev, size, bufs[i],
2073 le64_to_cpu(descs[i].addr),
2074 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
87ad72a5
CH		 2075 }
2076
2077 kfree(bufs);
2078out_free_descs:
4033f35d
CH		 2079 dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
2080 descs_dma);
87ad72a5 2081out:
87ad72a5
CH		 2082 dev->host_mem_descs = NULL;
2083 return -ENOMEM;
2084}
2085
92dc6895
CH		 2086static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
2087{
9dc54a0d
CK		 2088 u64 min_chunk = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
2089 u64 hmminds = max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
2090 u64 chunk_size;
92dc6895
CH		 2091
2092 /* start big and work our way down */
9dc54a0d 2093 for (chunk_size = min_chunk; chunk_size >= hmminds; chunk_size /= 2) {
92dc6895
CH		 2094 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
2095 if (!min || dev->host_mem_size >= min)
2096 return 0;
2097 nvme_free_host_mem(dev);
2098 }
2099 }
2100
2101 return -ENOMEM;
2102}
2103
9620cfba 2104static int nvme_setup_host_mem(struct nvme_dev *dev)
87ad72a5
CH		 2105{
2106 u64 max = (u64)max_host_mem_size_mb * SZ_1M;
2107 u64 preferred = (u64)dev->ctrl.hmpre * 4096;
2108 u64 min = (u64)dev->ctrl.hmmin * 4096;
2109 u32 enable_bits = NVME_HOST_MEM_ENABLE;
6fbcde66 2110 int ret;
87ad72a5
CH		 2111
2112 preferred = min(preferred, max);
2113 if (min > max) {
2114 dev_warn(dev->ctrl.device,
2115 "min host memory (%lld MiB) above limit (%d MiB).\n",
2116 min >> ilog2(SZ_1M), max_host_mem_size_mb);
2117 nvme_free_host_mem(dev);
9620cfba 2118 return 0;
87ad72a5
CH		 2119 }
2120
2121 /*
2122 * If we already have a buffer allocated check if we can reuse it.
2123 */
2124 if (dev->host_mem_descs) {
2125 if (dev->host_mem_size >= min)
2126 enable_bits |= NVME_HOST_MEM_RETURN;
2127 else
2128 nvme_free_host_mem(dev);
2129 }
2130
2131 if (!dev->host_mem_descs) {
92dc6895
CH		 2132 if (nvme_alloc_host_mem(dev, min, preferred)) {
2133 dev_warn(dev->ctrl.device,
2134 "failed to allocate host memory buffer.\n");
9620cfba 2135 return 0; /* controller must work without HMB */
92dc6895
CH		 2136 }
2137
2138 dev_info(dev->ctrl.device,
2139 "allocated %lld MiB host memory buffer.\n",
2140 dev->host_mem_size >> ilog2(SZ_1M));
87ad72a5
CH		 2141 }
2142
9620cfba
CH		 2143 ret = nvme_set_host_mem(dev, enable_bits);
2144 if (ret)
87ad72a5 2145 nvme_free_host_mem(dev);
9620cfba 2146 return ret;
9d713c2b
KB		 2147}
2148
0521905e
KB		 2149static ssize_t cmb_show(struct device *dev, struct device_attribute *attr,
2150 char *buf)
2151{
2152 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2153
2154 return sysfs_emit(buf, "cmbloc : x%08x\ncmbsz : x%08x\n",
2155 ndev->cmbloc, ndev->cmbsz);
2156}
2157static DEVICE_ATTR_RO(cmb);
2158
1751e97a
KB		 2159static ssize_t cmbloc_show(struct device *dev, struct device_attribute *attr,
2160 char *buf)
2161{
2162 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2163
2164 return sysfs_emit(buf, "%u\n", ndev->cmbloc);
2165}
2166static DEVICE_ATTR_RO(cmbloc);
2167
2168static ssize_t cmbsz_show(struct device *dev, struct device_attribute *attr,
2169 char *buf)
2170{
2171 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2172
2173 return sysfs_emit(buf, "%u\n", ndev->cmbsz);
2174}
2175static DEVICE_ATTR_RO(cmbsz);
2176
a5df5e79
KB		 2177static ssize_t hmb_show(struct device *dev, struct device_attribute *attr,
2178 char *buf)
2179{
2180 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2181
2182 return sysfs_emit(buf, "%d\n", ndev->hmb);
2183}
2184
2185static ssize_t hmb_store(struct device *dev, struct device_attribute *attr,
2186 const char *buf, size_t count)
2187{
2188 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2189 bool new;
2190 int ret;
2191
2192 if (strtobool(buf, &new) < 0)
2193 return -EINVAL;
2194
2195 if (new == ndev->hmb)
2196 return count;
2197
2198 if (new) {
2199 ret = nvme_setup_host_mem(ndev);
2200 } else {
2201 ret = nvme_set_host_mem(ndev, 0);
2202 if (!ret)
2203 nvme_free_host_mem(ndev);
2204 }
2205
2206 if (ret < 0)
2207 return ret;
2208
2209 return count;
2210}
2211static DEVICE_ATTR_RW(hmb);
2212
0521905e
KB		 2213static umode_t nvme_pci_attrs_are_visible(struct kobject *kobj,
2214 struct attribute *a, int n)
2215{
2216 struct nvme_ctrl *ctrl =
2217 dev_get_drvdata(container_of(kobj, struct device, kobj));
2218 struct nvme_dev *dev = to_nvme_dev(ctrl);
2219
1751e97a
KB		 2220 if (a == &dev_attr_cmb.attr ||
2221 a == &dev_attr_cmbloc.attr ||
2222 a == &dev_attr_cmbsz.attr) {
2223 if (!dev->cmbsz)
2224 return 0;
2225 }
a5df5e79
KB		 2226 if (a == &dev_attr_hmb.attr && !ctrl->hmpre)
2227 return 0;
2228
0521905e
KB		 2229 return a->mode;
2230}
2231
2232static struct attribute *nvme_pci_attrs[] = {
2233 &dev_attr_cmb.attr,
1751e97a
KB		 2234 &dev_attr_cmbloc.attr,
2235 &dev_attr_cmbsz.attr,
a5df5e79 2236 &dev_attr_hmb.attr,
0521905e
KB		 2237 NULL,
2238};
2239
2240static const struct attribute_group nvme_pci_attr_group = {
2241 .attrs = nvme_pci_attrs,
2242 .is_visible = nvme_pci_attrs_are_visible,
2243};
2244
612b7286
ML		 2245/*
2246 * nirqs is the number of interrupts available for write and read
2247 * queues. The core already reserved an interrupt for the admin queue.
2248 */
2249static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs)
3b6592f7 2250{
612b7286 2251 struct nvme_dev *dev = affd->priv;
2a5bcfdd 2252 unsigned int nr_read_queues, nr_write_queues = dev->nr_write_queues;
3b6592f7
JA		 2253
2254 /*
ee0d96d3 2255 * If there is no interrupt available for queues, ensure that
612b7286
ML		 2256 * the default queue is set to 1. The affinity set size is
2257 * also set to one, but the irq core ignores it for this case.
2258 *
2259 * If only one interrupt is available or 'write_queue' == 0, combine
2260 * write and read queues.
2261 *
2262 * If 'write_queues' > 0, ensure it leaves room for at least one read
2263 * queue.
3b6592f7 2264 */
612b7286
ML		 2265 if (!nrirqs) {
2266 nrirqs = 1;
2267 nr_read_queues = 0;
2a5bcfdd 2268 } else if (nrirqs == 1 || !nr_write_queues) {
612b7286 2269 nr_read_queues = 0;
2a5bcfdd 2270 } else if (nr_write_queues >= nrirqs) {
612b7286 2271 nr_read_queues = 1;
3b6592f7 2272 } else {
2a5bcfdd 2273 nr_read_queues = nrirqs - nr_write_queues;
3b6592f7 2274 }
612b7286
ML		 2275
2276 dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2277 affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2278 dev->io_queues[HCTX_TYPE_READ] = nr_read_queues;
2279 affd->set_size[HCTX_TYPE_READ] = nr_read_queues;
2280 affd->nr_sets = nr_read_queues ? 2 : 1;
3b6592f7
JA		 2281}
2282
6451fe73 2283static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues)
3b6592f7
JA		 2284{
2285 struct pci_dev *pdev = to_pci_dev(dev->dev);
3b6592f7 2286 struct irq_affinity affd = {
9cfef55b 2287 .pre_vectors = 1,
612b7286
ML		 2288 .calc_sets = nvme_calc_irq_sets,
2289 .priv = dev,
3b6592f7 2290 };
21cc2f3f 2291 unsigned int irq_queues, poll_queues;
6451fe73
JA		 2292
2293 /*
21cc2f3f
JX		 2294 * Poll queues don't need interrupts, but we need at least one I/O queue
2295 * left over for non-polled I/O.
6451fe73 2296 */
21cc2f3f
JX		 2297 poll_queues = min(dev->nr_poll_queues, nr_io_queues - 1);
2298 dev->io_queues[HCTX_TYPE_POLL] = poll_queues;
3b6592f7 2299
21cc2f3f
JX		 2300 /*
2301 * Initialize for the single interrupt case, will be updated in
2302 * nvme_calc_irq_sets().
2303 */
612b7286
ML		 2304 dev->io_queues[HCTX_TYPE_DEFAULT] = 1;
2305 dev->io_queues[HCTX_TYPE_READ] = 0;
3b6592f7 2306
66341331 2307 /*
21cc2f3f
JX		 2308 * We need interrupts for the admin queue and each non-polled I/O queue,
2309 * but some Apple controllers require all queues to use the first
2310 * vector.
66341331 2311 */
21cc2f3f
JX		 2312 irq_queues = 1;
2313 if (!(dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR))
2314 irq_queues += (nr_io_queues - poll_queues);
612b7286
ML		 2315 return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues,
2316 PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd);
3b6592f7
JA		 2317}
2318
8fae268b
KB		 2319static void nvme_disable_io_queues(struct nvme_dev *dev)
2320{
2321 if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq))
2322 __nvme_disable_io_queues(dev, nvme_admin_delete_cq);
2323}
2324
2a5bcfdd
WZ		 2325static unsigned int nvme_max_io_queues(struct nvme_dev *dev)
2326{
e3aef095
NS		 2327 /*
2328 * If tags are shared with admin queue (Apple bug), then
2329 * make sure we only use one IO queue.
2330 */
2331 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2332 return 1;
2a5bcfdd
WZ		 2333 return num_possible_cpus() + dev->nr_write_queues + dev->nr_poll_queues;
2334}
2335
8d85fce7 2336static int nvme_setup_io_queues(struct nvme_dev *dev)
b60503ba 2337{
147b27e4 2338 struct nvme_queue *adminq = &dev->queues[0];
e75ec752 2339 struct pci_dev *pdev = to_pci_dev(dev->dev);
2a5bcfdd 2340 unsigned int nr_io_queues;
97f6ef64 2341 unsigned long size;
2a5bcfdd 2342 int result;
b60503ba 2343
2a5bcfdd
WZ		 2344 /*
2345 * Sample the module parameters once at reset time so that we have
2346 * stable values to work with.
2347 */
2348 dev->nr_write_queues = write_queues;
2349 dev->nr_poll_queues = poll_queues;
d38e9f04 2350
e3aef095 2351 nr_io_queues = dev->nr_allocated_queues - 1;
9a0be7ab
CH		 2352 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
2353 if (result < 0)
1b23484b 2354 return result;
9a0be7ab 2355
f5fa90dc 2356 if (nr_io_queues == 0)
a5229050 2357 return 0;
53dc180e 2358
e4b9852a
CC		 2359 /*
2360 * Free IRQ resources as soon as NVMEQ_ENABLED bit transitions
2361 * from set to unset. If there is a window to it is truely freed,
2362 * pci_free_irq_vectors() jumping into this window will crash.
2363 * And take lock to avoid racing with pci_free_irq_vectors() in
2364 * nvme_dev_disable() path.
2365 */
2366 result = nvme_setup_io_queues_trylock(dev);
2367 if (result)
2368 return result;
2369 if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags))
2370 pci_free_irq(pdev, 0, adminq);
b60503ba 2371
0f238ff5 2372 if (dev->cmb_use_sqes) {
8ffaadf7
JD		 2373 result = nvme_cmb_qdepth(dev, nr_io_queues,
2374 sizeof(struct nvme_command));
2375 if (result > 0)
2376 dev->q_depth = result;
2377 else
0f238ff5 2378 dev->cmb_use_sqes = false;
8ffaadf7
JD		 2379 }
2380
97f6ef64
XY		 2381 do {
2382 size = db_bar_size(dev, nr_io_queues);
2383 result = nvme_remap_bar(dev, size);
2384 if (!result)
2385 break;
e4b9852a
CC		 2386 if (!--nr_io_queues) {
2387 result = -ENOMEM;
2388 goto out_unlock;
2389 }
97f6ef64
XY		 2390 } while (1);
2391 adminq->q_db = dev->dbs;
f1938f6e 2392
8fae268b 2393 retry:
9d713c2b 2394 /* Deregister the admin queue's interrupt */
e4b9852a
CC		 2395 if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags))
2396 pci_free_irq(pdev, 0, adminq);
9d713c2b 2397
e32efbfc
JA		 2398 /*
2399 * If we enable msix early due to not intx, disable it again before
2400 * setting up the full range we need.
2401 */
dca51e78 2402 pci_free_irq_vectors(pdev);
3b6592f7
JA		 2403
2404 result = nvme_setup_irqs(dev, nr_io_queues);
e4b9852a
CC		 2405 if (result <= 0) {
2406 result = -EIO;
2407 goto out_unlock;
2408 }
3b6592f7 2409
22b55601 2410 dev->num_vecs = result;
4b04cc6a 2411 result = max(result - 1, 1);
e20ba6e1 2412 dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL];
fa08a396 2413
063a8096
MW		 2414 /*
2415 * Should investigate if there's a performance win from allocating
2416 * more queues than interrupt vectors; it might allow the submission
2417 * path to scale better, even if the receive path is limited by the
2418 * number of interrupts.
2419 */
dca51e78 2420 result = queue_request_irq(adminq);
7c349dde 2421 if (result)
e4b9852a 2422 goto out_unlock;
4e224106 2423 set_bit(NVMEQ_ENABLED, &adminq->flags);
e4b9852a 2424 mutex_unlock(&dev->shutdown_lock);
8fae268b
KB		 2425
2426 result = nvme_create_io_queues(dev);
2427 if (result || dev->online_queues < 2)
2428 return result;
2429
2430 if (dev->online_queues - 1 < dev->max_qid) {
2431 nr_io_queues = dev->online_queues - 1;
2432 nvme_disable_io_queues(dev);
e4b9852a
CC		 2433 result = nvme_setup_io_queues_trylock(dev);
2434 if (result)
2435 return result;
8fae268b
KB		 2436 nvme_suspend_io_queues(dev);
2437 goto retry;
2438 }
2439 dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n",
2440 dev->io_queues[HCTX_TYPE_DEFAULT],
2441 dev->io_queues[HCTX_TYPE_READ],
2442 dev->io_queues[HCTX_TYPE_POLL]);
2443 return 0;
e4b9852a
CC		 2444out_unlock:
2445 mutex_unlock(&dev->shutdown_lock);
2446 return result;
b60503ba
MW		 2447}
2448
2a842aca 2449static void nvme_del_queue_end(struct request *req, blk_status_t error)
a5768aa8 2450{
db3cbfff 2451 struct nvme_queue *nvmeq = req->end_io_data;
b5875222 2452
db3cbfff 2453 blk_mq_free_request(req);
d1ed6aa1 2454 complete(&nvmeq->delete_done);
a5768aa8
KB		 2455}
2456
2a842aca 2457static void nvme_del_cq_end(struct request *req, blk_status_t error)
a5768aa8 2458{
db3cbfff 2459 struct nvme_queue *nvmeq = req->end_io_data;
a5768aa8 2460
d1ed6aa1
CH		 2461 if (error)
2462 set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
db3cbfff
KB		 2463
2464 nvme_del_queue_end(req, error);
a5768aa8
KB		 2465}
2466
db3cbfff 2467static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
bda4e0fb 2468{
db3cbfff
KB		 2469 struct request_queue *q = nvmeq->dev->ctrl.admin_q;
2470 struct request *req;
f66e2804 2471 struct nvme_command cmd = { };
bda4e0fb 2472
db3cbfff
KB		 2473 cmd.delete_queue.opcode = opcode;
2474 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
bda4e0fb 2475
e559398f 2476 req = blk_mq_alloc_request(q, nvme_req_op(&cmd), BLK_MQ_REQ_NOWAIT);
db3cbfff
KB		 2477 if (IS_ERR(req))
2478 return PTR_ERR(req);
e559398f 2479 nvme_init_request(req, &cmd);
bda4e0fb 2480
e2e53086
CH		 2481 if (opcode == nvme_admin_delete_cq)
2482 req->end_io = nvme_del_cq_end;
2483 else
2484 req->end_io = nvme_del_queue_end;
db3cbfff
KB		 2485 req->end_io_data = nvmeq;
2486
d1ed6aa1 2487 init_completion(&nvmeq->delete_done);
128126a7 2488 req->rq_flags |= RQF_QUIET;
e2e53086 2489 blk_execute_rq_nowait(req, false);
db3cbfff 2490 return 0;
bda4e0fb
KB		 2491}
2492
8fae268b 2493static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode)
a5768aa8 2494{
5271edd4 2495 int nr_queues = dev->online_queues - 1, sent = 0;
db3cbfff 2496 unsigned long timeout;
a5768aa8 2497
db3cbfff 2498 retry:
dc96f938 2499 timeout = NVME_ADMIN_TIMEOUT;
5271edd4
CH		 2500 while (nr_queues > 0) {
2501 if (nvme_delete_queue(&dev->queues[nr_queues], opcode))
2502 break;
2503 nr_queues--;
2504 sent++;
db3cbfff 2505 }
d1ed6aa1
CH		 2506 while (sent) {
2507 struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent];
2508
2509 timeout = wait_for_completion_io_timeout(&nvmeq->delete_done,
5271edd4
CH		 2510 timeout);
2511 if (timeout == 0)
2512 return false;
d1ed6aa1 2513
d1ed6aa1 2514 sent--;
5271edd4
CH		 2515 if (nr_queues)
2516 goto retry;
2517 }
2518 return true;
a5768aa8
KB		 2519}
2520
2455a4b7 2521static void nvme_pci_alloc_tag_set(struct nvme_dev *dev)
b60503ba 2522{
2455a4b7 2523 struct blk_mq_tag_set * set = &dev->tagset;
2b1b7e78
JW		 2524 int ret;
2525
2455a4b7
CH		 2526 set->ops = &nvme_mq_ops;
2527 set->nr_hw_queues = dev->online_queues - 1;
2528 set->nr_maps = 2; /* default + read */
2529 if (dev->io_queues[HCTX_TYPE_POLL])
2530 set->nr_maps++;
2531 set->timeout = NVME_IO_TIMEOUT;
2532 set->numa_node = dev->ctrl.numa_node;
2533 set->queue_depth = min_t(unsigned, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
2534 set->cmd_size = sizeof(struct nvme_iod);
2535 set->flags = BLK_MQ_F_SHOULD_MERGE;
2536 set->driver_data = dev;
d38e9f04 2537
2455a4b7
CH		 2538 /*
2539 * Some Apple controllers requires tags to be unique
2540 * across admin and IO queue, so reserve the first 32
2541 * tags of the IO queue.
2542 */
2543 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2544 set->reserved_tags = NVME_AQ_DEPTH;
949928c1 2545
2455a4b7
CH		 2546 ret = blk_mq_alloc_tag_set(set);
2547 if (ret) {
2548 dev_warn(dev->ctrl.device,
2549 "IO queues tagset allocation failed %d\n", ret);
2550 return;
ffe7704d 2551 }
2455a4b7
CH		 2552 dev->ctrl.tagset = set;
2553}
949928c1 2554
2455a4b7
CH		 2555static void nvme_pci_update_nr_queues(struct nvme_dev *dev)
2556{
2557 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2558 /* free previously allocated queues that are no longer usable */
2559 nvme_free_queues(dev, dev->online_queues);
b60503ba
MW		 2560}
2561
b00a726a 2562static int nvme_pci_enable(struct nvme_dev *dev)
0877cb0d 2563{
b00a726a 2564 int result = -ENOMEM;
e75ec752 2565 struct pci_dev *pdev = to_pci_dev(dev->dev);
4bdf2603 2566 int dma_address_bits = 64;
0877cb0d
KB		 2567
2568 if (pci_enable_device_mem(pdev))
2569 return result;
2570
0877cb0d 2571 pci_set_master(pdev);
0877cb0d 2572
4bdf2603
FS		 2573 if (dev->ctrl.quirks & NVME_QUIRK_DMA_ADDRESS_BITS_48)
2574 dma_address_bits = 48;
2575 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(dma_address_bits)))
052d0efa 2576 goto disable;
0877cb0d 2577
7a67cbea 2578 if (readl(dev->bar + NVME_REG_CSTS) == -1) {
0e53d180 2579 result = -ENODEV;
b00a726a 2580 goto disable;
0e53d180 2581 }
e32efbfc
JA		 2582
2583 /*
a5229050
KB		 2584 * Some devices and/or platforms don't advertise or work with INTx
2585 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2586 * adjust this later.
e32efbfc 2587 */
dca51e78
CH		 2588 result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
2589 if (result < 0)
2590 return result;
e32efbfc 2591
20d0dfe6 2592 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
7a67cbea 2593
7442ddce 2594 dev->q_depth = min_t(u32, NVME_CAP_MQES(dev->ctrl.cap) + 1,
b27c1e68 2595 io_queue_depth);
aa22c8e6 2596 dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */
20d0dfe6 2597 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
7a67cbea 2598 dev->dbs = dev->bar + 4096;
1f390c1f 2599
66341331
BH		 2600 /*
2601 * Some Apple controllers require a non-standard SQE size.
2602 * Interestingly they also seem to ignore the CC:IOSQES register
2603 * so we don't bother updating it here.
2604 */
2605 if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES)
2606 dev->io_sqes = 7;
2607 else
2608 dev->io_sqes = NVME_NVM_IOSQES;
1f390c1f
SG		 2609
2610 /*
2611 * Temporary fix for the Apple controller found in the MacBook8,1 and
2612 * some MacBook7,1 to avoid controller resets and data loss.
2613 */
2614 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
2615 dev->q_depth = 2;
9bdcfb10
CH		 2616 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
2617 "set queue depth=%u to work around controller resets\n",
1f390c1f 2618 dev->q_depth);
d554b5e1
MP		 2619 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2620 (pdev->device == 0xa821 || pdev->device == 0xa822) &&
20d0dfe6 2621 NVME_CAP_MQES(dev->ctrl.cap) == 0) {
d554b5e1
MP		 2622 dev->q_depth = 64;
2623 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2624 "set queue depth=%u\n", dev->q_depth);
1f390c1f
SG		 2625 }
2626
d38e9f04
BH		 2627 /*
2628 * Controllers with the shared tags quirk need the IO queue to be
2629 * big enough so that we get 32 tags for the admin queue
2630 */
2631 if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) &&
2632 (dev->q_depth < (NVME_AQ_DEPTH + 2))) {
2633 dev->q_depth = NVME_AQ_DEPTH + 2;
2634 dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n",
2635 dev->q_depth);
2636 }
2637
2638
f65efd6d 2639 nvme_map_cmb(dev);
202021c1 2640
a0a3408e
KB		 2641 pci_enable_pcie_error_reporting(pdev);
2642 pci_save_state(pdev);
0877cb0d
KB		 2643 return 0;
2644
2645 disable:
0877cb0d
KB		 2646 pci_disable_device(pdev);
2647 return result;
2648}
2649
2650static void nvme_dev_unmap(struct nvme_dev *dev)
b00a726a
KB		 2651{
2652 if (dev->bar)
2653 iounmap(dev->bar);
a1f447b3 2654 pci_release_mem_regions(to_pci_dev(dev->dev));
b00a726a
KB		 2655}
2656
2657static void nvme_pci_disable(struct nvme_dev *dev)
0877cb0d 2658{
e75ec752
CH		 2659 struct pci_dev *pdev = to_pci_dev(dev->dev);
2660
dca51e78 2661 pci_free_irq_vectors(pdev);
0877cb0d 2662
a0a3408e
KB		 2663 if (pci_is_enabled(pdev)) {
2664 pci_disable_pcie_error_reporting(pdev);
e75ec752 2665 pci_disable_device(pdev);
4d115420 2666 }
4d115420
KB		 2667}
2668
a5cdb68c 2669static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
b60503ba 2670{
e43269e6 2671 bool dead = true, freeze = false;
302ad8cc 2672 struct pci_dev *pdev = to_pci_dev(dev->dev);
22404274 2673
77bf25ea 2674 mutex_lock(&dev->shutdown_lock);
081f5e75
KB		 2675 if (pci_is_enabled(pdev)) {
2676 u32 csts;
2677
2678 if (pci_device_is_present(pdev))
2679 csts = readl(dev->bar + NVME_REG_CSTS);
2680 else
2681 csts = ~0;
302ad8cc 2682
ebef7368 2683 if (dev->ctrl.state == NVME_CTRL_LIVE ||
e43269e6
KB		 2684 dev->ctrl.state == NVME_CTRL_RESETTING) {
2685 freeze = true;
302ad8cc 2686 nvme_start_freeze(&dev->ctrl);
e43269e6 2687 }
302ad8cc
KB		 2688 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
2689 pdev->error_state != pci_channel_io_normal);
c9d3bf88 2690 }
c21377f8 2691
302ad8cc
KB		 2692 /*
2693 * Give the controller a chance to complete all entered requests if
2694 * doing a safe shutdown.
2695 */
e43269e6
KB		 2696 if (!dead && shutdown && freeze)
2697 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
9a915a5b
JW		 2698
2699 nvme_stop_queues(&dev->ctrl);
87ad72a5 2700
64ee0ac0 2701 if (!dead && dev->ctrl.queue_count > 0) {
8fae268b 2702 nvme_disable_io_queues(dev);
a5cdb68c 2703 nvme_disable_admin_queue(dev, shutdown);
4d115420 2704 }
8fae268b
KB		 2705 nvme_suspend_io_queues(dev);
2706 nvme_suspend_queue(&dev->queues[0]);
b00a726a 2707 nvme_pci_disable(dev);
fa46c6fb 2708 nvme_reap_pending_cqes(dev);
07836e65 2709
1fcfca78
GL		 2710 nvme_cancel_tagset(&dev->ctrl);
2711 nvme_cancel_admin_tagset(&dev->ctrl);
302ad8cc
KB		 2712
2713 /*
2714 * The driver will not be starting up queues again if shutting down so
2715 * must flush all entered requests to their failed completion to avoid
2716 * deadlocking blk-mq hot-cpu notifier.
2717 */
c8e9e9b7 2718 if (shutdown) {
302ad8cc 2719 nvme_start_queues(&dev->ctrl);
c8e9e9b7 2720 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q))
6ca1d902 2721 nvme_start_admin_queue(&dev->ctrl);
c8e9e9b7 2722 }
77bf25ea 2723 mutex_unlock(&dev->shutdown_lock);
b60503ba
MW		 2724}
2725
c1ac9a4b
KB		 2726static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown)
2727{
2728 if (!nvme_wait_reset(&dev->ctrl))
2729 return -EBUSY;
2730 nvme_dev_disable(dev, shutdown);
2731 return 0;
2732}
2733
091b6092
MW		 2734static int nvme_setup_prp_pools(struct nvme_dev *dev)
2735{
e75ec752 2736 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
c61b82c7
CH		 2737 NVME_CTRL_PAGE_SIZE,
2738 NVME_CTRL_PAGE_SIZE, 0);
091b6092
MW		 2739 if (!dev->prp_page_pool)
2740 return -ENOMEM;
2741
99802a7a 2742 /* Optimisation for I/Os between 4k and 128k */
e75ec752 2743 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
99802a7a
MW		 2744 256, 256, 0);
2745 if (!dev->prp_small_pool) {
2746 dma_pool_destroy(dev->prp_page_pool);
2747 return -ENOMEM;
2748 }
091b6092
MW		 2749 return 0;
2750}
2751
2752static void nvme_release_prp_pools(struct nvme_dev *dev)
2753{
2754 dma_pool_destroy(dev->prp_page_pool);
99802a7a 2755 dma_pool_destroy(dev->prp_small_pool);
091b6092
MW		 2756}
2757
770597ec
KB		 2758static void nvme_free_tagset(struct nvme_dev *dev)
2759{
2760 if (dev->tagset.tags)
2761 blk_mq_free_tag_set(&dev->tagset);
2762 dev->ctrl.tagset = NULL;
2763}
2764
1673f1f0 2765static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
5e82e952 2766{
1673f1f0 2767 struct nvme_dev *dev = to_nvme_dev(ctrl);
9ac27090 2768
f9f38e33 2769 nvme_dbbuf_dma_free(dev);
770597ec 2770 nvme_free_tagset(dev);
1c63dc66
CH		 2771 if (dev->ctrl.admin_q)
2772 blk_put_queue(dev->ctrl.admin_q);
e286bcfc 2773 free_opal_dev(dev->ctrl.opal_dev);
943e942e 2774 mempool_destroy(dev->iod_mempool);
253fd4ac
IR		 2775 put_device(dev->dev);
2776 kfree(dev->queues);
5e82e952
KB		 2777 kfree(dev);
2778}
2779
7c1ce408 2780static void nvme_remove_dead_ctrl(struct nvme_dev *dev)
f58944e2 2781{
c1ac9a4b
KB		 2782 /*
2783 * Set state to deleting now to avoid blocking nvme_wait_reset(), which
2784 * may be holding this pci_dev's device lock.
2785 */
2786 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
d22524a4 2787 nvme_get_ctrl(&dev->ctrl);
69d9a99c 2788 nvme_dev_disable(dev, false);
9f9cafc1 2789 nvme_kill_queues(&dev->ctrl);
03e0f3a6 2790 if (!queue_work(nvme_wq, &dev->remove_work))
f58944e2
KB		 2791 nvme_put_ctrl(&dev->ctrl);
2792}
2793
fd634f41 2794static void nvme_reset_work(struct work_struct *work)
5e82e952 2795{
d86c4d8e
CH		 2796 struct nvme_dev *dev =
2797 container_of(work, struct nvme_dev, ctrl.reset_work);
a98e58e5 2798 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
e71afda4 2799 int result;
5e82e952 2800
7764656b
ZC		 2801 if (dev->ctrl.state != NVME_CTRL_RESETTING) {
2802 dev_warn(dev->ctrl.device, "ctrl state %d is not RESETTING\n",
2803 dev->ctrl.state);
e71afda4 2804 result = -ENODEV;
fd634f41 2805 goto out;
e71afda4 2806 }
5e82e952 2807
fd634f41
CH		 2808 /*
2809 * If we're called to reset a live controller first shut it down before
2810 * moving on.
2811 */
b00a726a 2812 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
a5cdb68c 2813 nvme_dev_disable(dev, false);
d6135c3a 2814 nvme_sync_queues(&dev->ctrl);
5e82e952 2815
5c959d73 2816 mutex_lock(&dev->shutdown_lock);
b00a726a 2817 result = nvme_pci_enable(dev);
f0b50732 2818 if (result)
4726bcf3 2819 goto out_unlock;
f0b50732 2820
01ad0990 2821 result = nvme_pci_configure_admin_queue(dev);
f0b50732 2822 if (result)
4726bcf3 2823 goto out_unlock;
f0b50732 2824
f91b727c
CH		 2825 if (!dev->ctrl.admin_q) {
2826 result = nvme_pci_alloc_admin_tag_set(dev);
2827 if (result)
2828 goto out_unlock;
2829 } else {
2830 nvme_start_admin_queue(&dev->ctrl);
2831 }
b9afca3e 2832
943e942e
JA		 2833 /*
2834 * Limit the max command size to prevent iod->sg allocations going
2835 * over a single page.
2836 */
7637de31
CH		 2837 dev->ctrl.max_hw_sectors = min_t(u32,
2838 NVME_MAX_KB_SZ << 1, dma_max_mapping_size(dev->dev) >> 9);
943e942e 2839 dev->ctrl.max_segments = NVME_MAX_SEGS;
a48bc520
CH		 2840
2841 /*
2842 * Don't limit the IOMMU merged segment size.
2843 */
2844 dma_set_max_seg_size(dev->dev, 0xffffffff);
3d2d861e 2845 dma_set_min_align_mask(dev->dev, NVME_CTRL_PAGE_SIZE - 1);
a48bc520 2846
5c959d73
KB		 2847 mutex_unlock(&dev->shutdown_lock);
2848
2849 /*
2850 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
2851 * initializing procedure here.
2852 */
2853 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
2854 dev_warn(dev->ctrl.device,
2855 "failed to mark controller CONNECTING\n");
cee6c269 2856 result = -EBUSY;
5c959d73
KB		 2857 goto out;
2858 }
943e942e 2859
95093350
MG		 2860 /*
2861 * We do not support an SGL for metadata (yet), so we are limited to a
2862 * single integrity segment for the separate metadata pointer.
2863 */
2864 dev->ctrl.max_integrity_segments = 1;
2865
f21c4769 2866 result = nvme_init_ctrl_finish(&dev->ctrl);
ce4541f4 2867 if (result)
f58944e2 2868 goto out;
ce4541f4 2869
e286bcfc
SB		 2870 if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
2871 if (!dev->ctrl.opal_dev)
2872 dev->ctrl.opal_dev =
2873 init_opal_dev(&dev->ctrl, &nvme_sec_submit);
2874 else if (was_suspend)
2875 opal_unlock_from_suspend(dev->ctrl.opal_dev);
2876 } else {
2877 free_opal_dev(dev->ctrl.opal_dev);
2878 dev->ctrl.opal_dev = NULL;
4f1244c8 2879 }
a98e58e5 2880
f9f38e33
HK		 2881 if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) {
2882 result = nvme_dbbuf_dma_alloc(dev);
2883 if (result)
2884 dev_warn(dev->dev,
2885 "unable to allocate dma for dbbuf\n");
2886 }
2887
9620cfba
CH		 2888 if (dev->ctrl.hmpre) {
2889 result = nvme_setup_host_mem(dev);
2890 if (result < 0)
2891 goto out;
2892 }
87ad72a5 2893
f0b50732 2894 result = nvme_setup_io_queues(dev);
badc34d4 2895 if (result)
f58944e2 2896 goto out;
f0b50732 2897
2659e57b
CH		 2898 /*
2899 * Keep the controller around but remove all namespaces if we don't have
2900 * any working I/O queue.
2901 */
3cf519b5 2902 if (dev->online_queues < 2) {
1b3c47c1 2903 dev_warn(dev->ctrl.device, "IO queues not created\n");
3b24774e 2904 nvme_kill_queues(&dev->ctrl);
5bae7f73 2905 nvme_remove_namespaces(&dev->ctrl);
770597ec 2906 nvme_free_tagset(dev);
3cf519b5 2907 } else {
25646264 2908 nvme_start_queues(&dev->ctrl);
302ad8cc 2909 nvme_wait_freeze(&dev->ctrl);
2455a4b7
CH		 2910 if (!dev->ctrl.tagset)
2911 nvme_pci_alloc_tag_set(dev);
2912 else
2913 nvme_pci_update_nr_queues(dev);
2914 nvme_dbbuf_set(dev);
302ad8cc 2915 nvme_unfreeze(&dev->ctrl);
3cf519b5
CH		 2916 }
2917
2b1b7e78
JW		 2918 /*
2919 * If only admin queue live, keep it to do further investigation or
2920 * recovery.
2921 */
5d02a5c1 2922 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
2b1b7e78 2923 dev_warn(dev->ctrl.device,
5d02a5c1 2924 "failed to mark controller live state\n");
e71afda4 2925 result = -ENODEV;
bb8d261e
CH		 2926 goto out;
2927 }
92911a55 2928
0521905e
KB		 2929 if (!dev->attrs_added && !sysfs_create_group(&dev->ctrl.device->kobj,
2930 &nvme_pci_attr_group))
2931 dev->attrs_added = true;
2932
d09f2b45 2933 nvme_start_ctrl(&dev->ctrl);
3cf519b5 2934 return;
f0b50732 2935
4726bcf3
KB		 2936 out_unlock:
2937 mutex_unlock(&dev->shutdown_lock);
3cf519b5 2938 out:
7c1ce408
CK		 2939 if (result)
2940 dev_warn(dev->ctrl.device,
2941 "Removing after probe failure status: %d\n", result);
2942 nvme_remove_dead_ctrl(dev);
f0b50732
KB		 2943}
2944
5c8809e6 2945static void nvme_remove_dead_ctrl_work(struct work_struct *work)
9a6b9458 2946{
5c8809e6 2947 struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
e75ec752 2948 struct pci_dev *pdev = to_pci_dev(dev->dev);
9a6b9458
KB		 2949
2950 if (pci_get_drvdata(pdev))
921920ab 2951 device_release_driver(&pdev->dev);
1673f1f0 2952 nvme_put_ctrl(&dev->ctrl);
9a6b9458
KB		 2953}
2954
1c63dc66 2955static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
9ca97374 2956{
1c63dc66 2957 *val = readl(to_nvme_dev(ctrl)->bar + off);
90667892 2958 return 0;
9ca97374
TH		 2959}
2960
5fd4ce1b 2961static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
4cc06521 2962{
5fd4ce1b
CH		 2963 writel(val, to_nvme_dev(ctrl)->bar + off);
2964 return 0;
2965}
4cc06521 2966
7fd8930f
CH		 2967static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2968{
3a8ecc93 2969 *val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off);
7fd8930f 2970 return 0;
4cc06521
KB		 2971}
2972
97c12223
KB		 2973static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
2974{
2975 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2976
2db24e4a 2977 return snprintf(buf, size, "%s\n", dev_name(&pdev->dev));
97c12223
KB		 2978}
2979
2f0dad17
KB		 2980static void nvme_pci_print_device_info(struct nvme_ctrl *ctrl)
2981{
2982 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2983 struct nvme_subsystem *subsys = ctrl->subsys;
2984
2985 dev_err(ctrl->device,
2986 "VID:DID %04x:%04x model:%.*s firmware:%.*s\n",
2987 pdev->vendor, pdev->device,
2988 nvme_strlen(subsys->model, sizeof(subsys->model)),
2989 subsys->model, nvme_strlen(subsys->firmware_rev,
2990 sizeof(subsys->firmware_rev)),
2991 subsys->firmware_rev);
2992}
2993
2f859441
LG		 2994static bool nvme_pci_supports_pci_p2pdma(struct nvme_ctrl *ctrl)
2995{
2996 struct nvme_dev *dev = to_nvme_dev(ctrl);
2997
2998 return dma_pci_p2pdma_supported(dev->dev);
2999}
3000
1c63dc66 3001static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
1a353d85 3002 .name = "pcie",
e439bb12 3003 .module = THIS_MODULE,
2f859441 3004 .flags = NVME_F_METADATA_SUPPORTED,
1c63dc66 3005 .reg_read32 = nvme_pci_reg_read32,
5fd4ce1b 3006 .reg_write32 = nvme_pci_reg_write32,
7fd8930f 3007 .reg_read64 = nvme_pci_reg_read64,
1673f1f0 3008 .free_ctrl = nvme_pci_free_ctrl,
f866fc42 3009 .submit_async_event = nvme_pci_submit_async_event,
97c12223 3010 .get_address = nvme_pci_get_address,
2f0dad17 3011 .print_device_info = nvme_pci_print_device_info,
2f859441 3012 .supports_pci_p2pdma = nvme_pci_supports_pci_p2pdma,
1c63dc66 3013};
4cc06521 3014
b00a726a
KB		 3015static int nvme_dev_map(struct nvme_dev *dev)
3016{
b00a726a
KB		 3017 struct pci_dev *pdev = to_pci_dev(dev->dev);
3018
a1f447b3 3019 if (pci_request_mem_regions(pdev, "nvme"))
b00a726a
KB		 3020 return -ENODEV;
3021
97f6ef64 3022 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
b00a726a
KB		 3023 goto release;
3024
9fa196e7 3025 return 0;
b00a726a 3026 release:
9fa196e7
MG		 3027 pci_release_mem_regions(pdev);
3028 return -ENODEV;
b00a726a
KB		 3029}
3030
8427bbc2 3031static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
ff5350a8
AL		 3032{
3033 if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
3034 /*
3035 * Several Samsung devices seem to drop off the PCIe bus
3036 * randomly when APST is on and uses the deepest sleep state.
3037 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
3038 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
3039 * 950 PRO 256GB", but it seems to be restricted to two Dell
3040 * laptops.
3041 */
3042 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
3043 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
3044 dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
3045 return NVME_QUIRK_NO_DEEPEST_PS;
8427bbc2
KHF		 3046 } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
3047 /*
3048 * Samsung SSD 960 EVO drops off the PCIe bus after system
467c77d4
JJ		 3049 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
3050 * within few minutes after bootup on a Coffee Lake board -
3051 * ASUS PRIME Z370-A
8427bbc2
KHF		 3052 */
3053 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
467c77d4
JJ		 3054 (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") ||
3055 dmi_match(DMI_BOARD_NAME, "PRIME Z370-A")))
8427bbc2 3056 return NVME_QUIRK_NO_APST;
1fae37ac
S		 3057 } else if ((pdev->vendor == 0x144d && (pdev->device == 0xa801 ||
3058 pdev->device == 0xa808 || pdev->device == 0xa809)) ||
3059 (pdev->vendor == 0x1e0f && pdev->device == 0x0001)) {
3060 /*
3061 * Forcing to use host managed nvme power settings for
3062 * lowest idle power with quick resume latency on
3063 * Samsung and Toshiba SSDs based on suspend behavior
3064 * on Coffee Lake board for LENOVO C640
3065 */
3066 if ((dmi_match(DMI_BOARD_VENDOR, "LENOVO")) &&
3067 dmi_match(DMI_BOARD_NAME, "LNVNB161216"))
3068 return NVME_QUIRK_SIMPLE_SUSPEND;
ff5350a8
AL		 3069 }
3070
3071 return 0;
3072}
3073
18119775
KB		 3074static void nvme_async_probe(void *data, async_cookie_t cookie)
3075{
3076 struct nvme_dev *dev = data;
80f513b5 3077
bd46a906 3078 flush_work(&dev->ctrl.reset_work);
18119775 3079 flush_work(&dev->ctrl.scan_work);
80f513b5 3080 nvme_put_ctrl(&dev->ctrl);
18119775
KB		 3081}
3082
8d85fce7 3083static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
b60503ba 3084{
a4aea562 3085 int node, result = -ENOMEM;
b60503ba 3086 struct nvme_dev *dev;
ff5350a8 3087 unsigned long quirks = id->driver_data;
943e942e 3088 size_t alloc_size;
b60503ba 3089
a4aea562
MB		 3090 node = dev_to_node(&pdev->dev);
3091 if (node == NUMA_NO_NODE)
2fa84351 3092 set_dev_node(&pdev->dev, first_memory_node);
a4aea562
MB		 3093
3094 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
b60503ba
MW		 3095 if (!dev)
3096 return -ENOMEM;
147b27e4 3097
2a5bcfdd
WZ		 3098 dev->nr_write_queues = write_queues;
3099 dev->nr_poll_queues = poll_queues;
3100 dev->nr_allocated_queues = nvme_max_io_queues(dev) + 1;
3101 dev->queues = kcalloc_node(dev->nr_allocated_queues,
3102 sizeof(struct nvme_queue), GFP_KERNEL, node);
b60503ba
MW		 3103 if (!dev->queues)
3104 goto free;
3105
e75ec752 3106 dev->dev = get_device(&pdev->dev);
9a6b9458 3107 pci_set_drvdata(pdev, dev);
1c63dc66 3108
b00a726a
KB		 3109 result = nvme_dev_map(dev);
3110 if (result)
b00c9b7a 3111 goto put_pci;
b00a726a 3112
d86c4d8e 3113 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
5c8809e6 3114 INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
77bf25ea 3115 mutex_init(&dev->shutdown_lock);
b60503ba 3116
091b6092
MW		 3117 result = nvme_setup_prp_pools(dev);
3118 if (result)
b00c9b7a 3119 goto unmap;
4cc06521 3120
8427bbc2 3121 quirks |= check_vendor_combination_bug(pdev);
ff5350a8 3122
2744d7a0 3123 if (!noacpi && acpi_storage_d3(&pdev->dev)) {
df4f9bc4
DB		 3124 /*
3125 * Some systems use a bios work around to ask for D3 on
3126 * platforms that support kernel managed suspend.
3127 */
3128 dev_info(&pdev->dev,
3129 "platform quirk: setting simple suspend\n");
3130 quirks |= NVME_QUIRK_SIMPLE_SUSPEND;
3131 }
3132
943e942e
JA		 3133 /*
3134 * Double check that our mempool alloc size will cover the biggest
3135 * command we support.
3136 */
b13c6393 3137 alloc_size = nvme_pci_iod_alloc_size();
943e942e
JA		 3138 WARN_ON_ONCE(alloc_size > PAGE_SIZE);
3139
3140 dev->iod_mempool = mempool_create_node(1, mempool_kmalloc,
3141 mempool_kfree,
3142 (void *) alloc_size,
3143 GFP_KERNEL, node);
3144 if (!dev->iod_mempool) {
3145 result = -ENOMEM;
3146 goto release_pools;
3147 }
3148
b6e44b4c
KB		 3149 result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
3150 quirks);
3151 if (result)
3152 goto release_mempool;
3153
1b3c47c1
SG		 3154 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
3155
bd46a906 3156 nvme_reset_ctrl(&dev->ctrl);
18119775 3157 async_schedule(nvme_async_probe, dev);
4caff8fc 3158
b60503ba
MW		 3159 return 0;
3160
b6e44b4c
KB		 3161 release_mempool:
3162 mempool_destroy(dev->iod_mempool);
0877cb0d 3163 release_pools:
091b6092 3164 nvme_release_prp_pools(dev);
b00c9b7a
CJ		 3165 unmap:
3166 nvme_dev_unmap(dev);
a96d4f5c 3167 put_pci:
e75ec752 3168 put_device(dev->dev);
b60503ba
MW		 3169 free:
3170 kfree(dev->queues);
b60503ba
MW		 3171 kfree(dev);
3172 return result;
3173}
3174
775755ed 3175static void nvme_reset_prepare(struct pci_dev *pdev)
f0d54a54 3176{
a6739479 3177 struct nvme_dev *dev = pci_get_drvdata(pdev);
c1ac9a4b
KB		 3178
3179 /*
3180 * We don't need to check the return value from waiting for the reset
3181 * state as pci_dev device lock is held, making it impossible to race
3182 * with ->remove().
3183 */
3184 nvme_disable_prepare_reset(dev, false);
3185 nvme_sync_queues(&dev->ctrl);
775755ed 3186}
f0d54a54 3187
775755ed
CH		 3188static void nvme_reset_done(struct pci_dev *pdev)
3189{
f263fbb8 3190 struct nvme_dev *dev = pci_get_drvdata(pdev);
c1ac9a4b
KB		 3191
3192 if (!nvme_try_sched_reset(&dev->ctrl))
3193 flush_work(&dev->ctrl.reset_work);
f0d54a54
KB		 3194}
3195
09ece142
KB		 3196static void nvme_shutdown(struct pci_dev *pdev)
3197{
3198 struct nvme_dev *dev = pci_get_drvdata(pdev);
4e523547 3199
c1ac9a4b 3200 nvme_disable_prepare_reset(dev, true);
09ece142
KB		 3201}
3202
0521905e
KB		 3203static void nvme_remove_attrs(struct nvme_dev *dev)
3204{
3205 if (dev->attrs_added)
3206 sysfs_remove_group(&dev->ctrl.device->kobj,
3207 &nvme_pci_attr_group);
3208}
3209
f58944e2
KB		 3210/*
3211 * The driver's remove may be called on a device in a partially initialized
3212 * state. This function must not have any dependencies on the device state in
3213 * order to proceed.
3214 */
8d85fce7 3215static void nvme_remove(struct pci_dev *pdev)
b60503ba
MW		 3216{
3217 struct nvme_dev *dev = pci_get_drvdata(pdev);
9a6b9458 3218
bb8d261e 3219 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
9a6b9458 3220 pci_set_drvdata(pdev, NULL);
0ff9d4e1 3221
6db28eda 3222 if (!pci_device_is_present(pdev)) {
0ff9d4e1 3223 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
1d39e692 3224 nvme_dev_disable(dev, true);
6db28eda 3225 }
0ff9d4e1 3226
d86c4d8e 3227 flush_work(&dev->ctrl.reset_work);
d09f2b45
SG		 3228 nvme_stop_ctrl(&dev->ctrl);
3229 nvme_remove_namespaces(&dev->ctrl);
a5cdb68c 3230 nvme_dev_disable(dev, true);
0521905e 3231 nvme_remove_attrs(dev);
87ad72a5 3232 nvme_free_host_mem(dev);
a4aea562 3233 nvme_dev_remove_admin(dev);
a1a5ef99 3234 nvme_free_queues(dev, 0);
9a6b9458 3235 nvme_release_prp_pools(dev);
b00a726a 3236 nvme_dev_unmap(dev);
726612b6 3237 nvme_uninit_ctrl(&dev->ctrl);
b60503ba
MW		 3238}
3239
671a6018 3240#ifdef CONFIG_PM_SLEEP
d916b1be
KB		 3241static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps)
3242{
3243 return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps);
3244}
3245
3246static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps)
3247{
3248 return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL);
3249}
3250
3251static int nvme_resume(struct device *dev)
3252{
3253 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
3254 struct nvme_ctrl *ctrl = &ndev->ctrl;
3255
4eaefe8c 3256 if (ndev->last_ps == U32_MAX ||
d916b1be 3257 nvme_set_power_state(ctrl, ndev->last_ps) != 0)
e5ad96f3
KB		 3258 goto reset;
3259 if (ctrl->hmpre && nvme_setup_host_mem(ndev))
3260 goto reset;
3261
d916b1be 3262 return 0;
e5ad96f3
KB		 3263reset:
3264 return nvme_try_sched_reset(ctrl);
d916b1be
KB		 3265}
3266
cd638946
KB		 3267static int nvme_suspend(struct device *dev)
3268{
3269 struct pci_dev *pdev = to_pci_dev(dev);
3270 struct nvme_dev *ndev = pci_get_drvdata(pdev);
d916b1be
KB		 3271 struct nvme_ctrl *ctrl = &ndev->ctrl;
3272 int ret = -EBUSY;
3273
4eaefe8c
RW		 3274 ndev->last_ps = U32_MAX;
3275
d916b1be
KB		 3276 /*
3277 * The platform does not remove power for a kernel managed suspend so
3278 * use host managed nvme power settings for lowest idle power if
3279 * possible. This should have quicker resume latency than a full device
3280 * shutdown. But if the firmware is involved after the suspend or the
3281 * device does not support any non-default power states, shut down the
3282 * device fully.
4eaefe8c
RW		 3283 *
3284 * If ASPM is not enabled for the device, shut down the device and allow
3285 * the PCI bus layer to put it into D3 in order to take the PCIe link
3286 * down, so as to allow the platform to achieve its minimum low-power
3287 * state (which may not be possible if the link is up).
d916b1be 3288 */
4eaefe8c 3289 if (pm_suspend_via_firmware() || !ctrl->npss ||
cb32de1b 3290 !pcie_aspm_enabled(pdev) ||
c1ac9a4b
KB		 3291 (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND))
3292 return nvme_disable_prepare_reset(ndev, true);
d916b1be
KB		 3293
3294 nvme_start_freeze(ctrl);
3295 nvme_wait_freeze(ctrl);
3296 nvme_sync_queues(ctrl);
3297
5d02a5c1 3298 if (ctrl->state != NVME_CTRL_LIVE)
d916b1be
KB		 3299 goto unfreeze;
3300
e5ad96f3
KB		 3301 /*
3302 * Host memory access may not be successful in a system suspend state,
3303 * but the specification allows the controller to access memory in a
3304 * non-operational power state.
3305 */
3306 if (ndev->hmb) {
3307 ret = nvme_set_host_mem(ndev, 0);
3308 if (ret < 0)
3309 goto unfreeze;
3310 }
3311
d916b1be
KB		 3312 ret = nvme_get_power_state(ctrl, &ndev->last_ps);
3313 if (ret < 0)
3314 goto unfreeze;
3315
7cbb5c6f
ML		 3316 /*
3317 * A saved state prevents pci pm from generically controlling the
3318 * device's power. If we're using protocol specific settings, we don't
3319 * want pci interfering.
3320 */
3321 pci_save_state(pdev);
3322
d916b1be
KB		 3323 ret = nvme_set_power_state(ctrl, ctrl->npss);
3324 if (ret < 0)
3325 goto unfreeze;
3326
3327 if (ret) {
7cbb5c6f
ML		 3328 /* discard the saved state */
3329 pci_load_saved_state(pdev, NULL);
3330
d916b1be
KB		 3331 /*
3332 * Clearing npss forces a controller reset on resume. The
05d3046f 3333 * correct value will be rediscovered then.
d916b1be 3334 */
c1ac9a4b 3335 ret = nvme_disable_prepare_reset(ndev, true);
d916b1be 3336 ctrl->npss = 0;
d916b1be 3337 }
d916b1be
KB		 3338unfreeze:
3339 nvme_unfreeze(ctrl);
3340 return ret;
3341}
3342
3343static int nvme_simple_suspend(struct device *dev)
3344{
3345 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
4e523547 3346
c1ac9a4b 3347 return nvme_disable_prepare_reset(ndev, true);
cd638946
KB		 3348}
3349
d916b1be 3350static int nvme_simple_resume(struct device *dev)
cd638946
KB		 3351{
3352 struct pci_dev *pdev = to_pci_dev(dev);
3353 struct nvme_dev *ndev = pci_get_drvdata(pdev);
cd638946 3354
c1ac9a4b 3355 return nvme_try_sched_reset(&ndev->ctrl);
cd638946
KB		 3356}
3357
21774222 3358static const struct dev_pm_ops nvme_dev_pm_ops = {
d916b1be
KB		 3359 .suspend = nvme_suspend,
3360 .resume = nvme_resume,
3361 .freeze = nvme_simple_suspend,
3362 .thaw = nvme_simple_resume,
3363 .poweroff = nvme_simple_suspend,
3364 .restore = nvme_simple_resume,
3365};
3366#endif /* CONFIG_PM_SLEEP */
b60503ba 3367
a0a3408e
KB		 3368static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
3369 pci_channel_state_t state)
3370{
3371 struct nvme_dev *dev = pci_get_drvdata(pdev);
3372
3373 /*
3374 * A frozen channel requires a reset. When detected, this method will
3375 * shutdown the controller to quiesce. The controller will be restarted
3376 * after the slot reset through driver's slot_reset callback.
3377 */
a0a3408e
KB		 3378 switch (state) {
3379 case pci_channel_io_normal:
3380 return PCI_ERS_RESULT_CAN_RECOVER;
3381 case pci_channel_io_frozen:
d011fb31
KB		 3382 dev_warn(dev->ctrl.device,
3383 "frozen state error detected, reset controller\n");
a5cdb68c 3384 nvme_dev_disable(dev, false);
a0a3408e
KB		 3385 return PCI_ERS_RESULT_NEED_RESET;
3386 case pci_channel_io_perm_failure:
d011fb31
KB		 3387 dev_warn(dev->ctrl.device,
3388 "failure state error detected, request disconnect\n");
a0a3408e
KB		 3389 return PCI_ERS_RESULT_DISCONNECT;
3390 }
3391 return PCI_ERS_RESULT_NEED_RESET;
3392}
3393
3394static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
3395{
3396 struct nvme_dev *dev = pci_get_drvdata(pdev);
3397
1b3c47c1 3398 dev_info(dev->ctrl.device, "restart after slot reset\n");
a0a3408e 3399 pci_restore_state(pdev);
d86c4d8e 3400 nvme_reset_ctrl(&dev->ctrl);
a0a3408e
KB		 3401 return PCI_ERS_RESULT_RECOVERED;
3402}
3403
3404static void nvme_error_resume(struct pci_dev *pdev)
3405{
72cd4cc2
KB		 3406 struct nvme_dev *dev = pci_get_drvdata(pdev);
3407
3408 flush_work(&dev->ctrl.reset_work);
a0a3408e
KB		 3409}
3410
1d352035 3411static const struct pci_error_handlers nvme_err_handler = {
b60503ba 3412 .error_detected = nvme_error_detected,
b60503ba
MW		 3413 .slot_reset = nvme_slot_reset,
3414 .resume = nvme_error_resume,
775755ed
CH		 3415 .reset_prepare = nvme_reset_prepare,
3416 .reset_done = nvme_reset_done,
b60503ba
MW		 3417};
3418
6eb0d698 3419static const struct pci_device_id nvme_id_table[] = {
972b13e2 3420 { PCI_VDEVICE(INTEL, 0x0953), /* Intel 750/P3500/P3600/P3700 */
08095e70 3421 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 3422 NVME_QUIRK_DEALLOCATE_ZEROES, },
972b13e2 3423 { PCI_VDEVICE(INTEL, 0x0a53), /* Intel P3520 */
99466e70 3424 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 3425 NVME_QUIRK_DEALLOCATE_ZEROES, },
972b13e2 3426 { PCI_VDEVICE(INTEL, 0x0a54), /* Intel P4500/P4600 */
99466e70 3427 .driver_data = NVME_QUIRK_STRIPE_SIZE |
25e58af4
WZ		 3428 NVME_QUIRK_DEALLOCATE_ZEROES |
3429 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
972b13e2 3430 { PCI_VDEVICE(INTEL, 0x0a55), /* Dell Express Flash P4600 */
f99cb7af
DWF		 3431 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3432 NVME_QUIRK_DEALLOCATE_ZEROES, },
50af47d0 3433 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */
9abd68ef 3434 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
6c6aa2f2 3435 NVME_QUIRK_MEDIUM_PRIO_SQ |
ce4cc313
DM		 3436 NVME_QUIRK_NO_TEMP_THRESH_CHANGE |
3437 NVME_QUIRK_DISABLE_WRITE_ZEROES, },
6299358d
JD		 3438 { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */
3439 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
540c801c 3440 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */
7b210e4e 3441 .driver_data = NVME_QUIRK_IDENTIFY_CNS |
66dd346b
CH		 3442 NVME_QUIRK_DISABLE_WRITE_ZEROES |
3443 NVME_QUIRK_BOGUS_NID, },
3444 { PCI_VDEVICE(REDHAT, 0x0010), /* Qemu emulated controller */
3445 .driver_data = NVME_QUIRK_BOGUS_NID, },
5bedd3af 3446 { PCI_DEVICE(0x126f, 0x2263), /* Silicon Motion unidentified */
c98a8793
KB		 3447 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST |
3448 NVME_QUIRK_BOGUS_NID, },
0302ae60 3449 { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */
5e112d3f
JE		 3450 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
3451 NVME_QUIRK_NO_NS_DESC_LIST, },
54adc010
GP		 3452 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
3453 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
8c97eecc
JL		 3454 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */
3455 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
015282c9
WW		 3456 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
3457 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
d554b5e1
MP		 3458 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */
3459 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3460 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */
7ee5c78c 3461 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
abbb5f59 3462 NVME_QUIRK_DISABLE_WRITE_ZEROES|
7ee5c78c 3463 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
2cf7a77e
KB		 3464 { PCI_DEVICE(0x1987, 0x5012), /* Phison E12 */
3465 .driver_data = NVME_QUIRK_BOGUS_NID, },
c9e95c39 3466 { PCI_DEVICE(0x1987, 0x5016), /* Phison E16 */
73029c9b
KB		 3467 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN |
3468 NVME_QUIRK_BOGUS_NID, },
6e6a6828
PT		 3469 { PCI_DEVICE(0x1b4b, 0x1092), /* Lexar 256 GB SSD */
3470 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST |
3471 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
e1c70d79
LVS		 3472 { PCI_DEVICE(0x1cc1, 0x33f8), /* ADATA IM2P33F8ABR1 1 TB */
3473 .driver_data = NVME_QUIRK_BOGUS_NID, },
08b903b5 3474 { PCI_DEVICE(0x10ec, 0x5762), /* ADATA SX6000LNP */
1629de0e
PG		 3475 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN |
3476 NVME_QUIRK_BOGUS_NID, },
f03e42c6
GC		 3477 { PCI_DEVICE(0x1cc1, 0x8201), /* ADATA SX8200PNP 512GB */
3478 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3479 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
41f38043
LS		 3480 { PCI_DEVICE(0x1344, 0x5407), /* Micron Technology Inc NVMe SSD */
3481 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN },
5611ec2b
KHF		 3482 { PCI_DEVICE(0x1c5c, 0x1504), /* SK Hynix PC400 */
3483 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
c4f01a77
KB		 3484 { PCI_DEVICE(0x1c5c, 0x174a), /* SK Hynix P31 SSD */
3485 .driver_data = NVME_QUIRK_BOGUS_NID, },
02ca079c
KHF		 3486 { PCI_DEVICE(0x15b7, 0x2001), /* Sandisk Skyhawk */
3487 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
89919929
CK		 3488 { PCI_DEVICE(0x1d97, 0x2263), /* SPCC */
3489 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
43047e08 3490 { PCI_DEVICE(0x144d, 0xa80b), /* Samsung PM9B1 256G and 512G */
3491 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3492 { PCI_DEVICE(0x144d, 0xa809), /* Samsung MZALQ256HBJD 256G */
3493 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3494 { PCI_DEVICE(0x1cc4, 0x6303), /* UMIS RPJTJ512MGE1QDY 512G */
3495 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3496 { PCI_DEVICE(0x1cc4, 0x6302), /* UMIS RPJTJ256MGE1QDY 256G */
3497 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
dc22c1c0
ZB		 3498 { PCI_DEVICE(0x2646, 0x2262), /* KINGSTON SKC2000 NVMe SSD */
3499 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
538e4a8c
TL		 3500 { PCI_DEVICE(0x2646, 0x2263), /* KINGSTON A2000 NVMe SSD */
3501 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
70ce3455
CH		 3502 { PCI_DEVICE(0x1e4B, 0x1001), /* MAXIO MAP1001 */
3503 .driver_data = NVME_QUIRK_BOGUS_NID, },
a98a945b
CH		 3504 { PCI_DEVICE(0x1e4B, 0x1002), /* MAXIO MAP1002 */
3505 .driver_data = NVME_QUIRK_BOGUS_NID, },
3506 { PCI_DEVICE(0x1e4B, 0x1202), /* MAXIO MAP1202 */
3507 .driver_data = NVME_QUIRK_BOGUS_NID, },
3765fad5
SR		 3508 { PCI_DEVICE(0x1cc1, 0x5350), /* ADATA XPG GAMMIX S50 */
3509 .driver_data = NVME_QUIRK_BOGUS_NID, },
f37527a0
DK		 3510 { PCI_DEVICE(0x1dbe, 0x5236), /* ADATA XPG GAMMIX S70 */
3511 .driver_data = NVME_QUIRK_BOGUS_NID, },
6b961bce
NW		 3512 { PCI_DEVICE(0x1e49, 0x0041), /* ZHITAI TiPro7000 NVMe SSD */
3513 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
d6c52fa3
TG		 3514 { PCI_DEVICE(0xc0a9, 0x540a), /* Crucial P2 */
3515 .driver_data = NVME_QUIRK_BOGUS_NID, },
4bdf2603
FS		 3516 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0061),
3517 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3518 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0065),
3519 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3520 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x8061),
3521 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3522 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd00),
3523 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3524 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd01),
3525 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3526 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd02),
3527 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
98f7b86a
AS		 3528 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001),
3529 .driver_data = NVME_QUIRK_SINGLE_VECTOR },
124298bd 3530 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
66341331
BH		 3531 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005),
3532 .driver_data = NVME_QUIRK_SINGLE_VECTOR |
d38e9f04 3533 NVME_QUIRK_128_BYTES_SQES |
a2941f6a
KB		 3534 NVME_QUIRK_SHARED_TAGS |
3535 NVME_QUIRK_SKIP_CID_GEN },
0b85f59d 3536 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
b60503ba
MW		 3537 { 0, }
3538};
3539MODULE_DEVICE_TABLE(pci, nvme_id_table);
3540
3541static struct pci_driver nvme_driver = {
3542 .name = "nvme",
3543 .id_table = nvme_id_table,
3544 .probe = nvme_probe,
8d85fce7 3545 .remove = nvme_remove,
09ece142 3546 .shutdown = nvme_shutdown,
d916b1be 3547#ifdef CONFIG_PM_SLEEP
cd638946
KB		 3548 .driver = {
3549 .pm = &nvme_dev_pm_ops,
3550 },
d916b1be 3551#endif
74d986ab 3552 .sriov_configure = pci_sriov_configure_simple,
b60503ba
MW		 3553 .err_handler = &nvme_err_handler,
3554};
3555
3556static int __init nvme_init(void)
3557{
81101540
CH		 3558 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
3559 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
3560 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
612b7286 3561 BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2);
17c33167 3562
9a6327d2 3563 return pci_register_driver(&nvme_driver);
b60503ba
MW		 3564}
3565
3566static void __exit nvme_exit(void)
3567{
3568 pci_unregister_driver(&nvme_driver);
03e0f3a6 3569 flush_workqueue(nvme_wq);
b60503ba
MW		 3570}
3571
3572MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3573MODULE_LICENSE("GPL");
c78b4713 3574MODULE_VERSION("1.0");
b60503ba
MW		 3575module_init(nvme_init);
3576module_exit(nvme_exit);
Linux 6.x block layer and io_uring tree(s)