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block: remove ->poll_fn
[linux-2.6-block.git] / drivers / nvme / host / pci.c
CommitLineData
b60503ba
MW		 1/*
2 * NVM Express device driver
6eb0d698 3 * Copyright (c) 2011-2014, Intel Corporation.
b60503ba
MW		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
b60503ba
MW		 13 */
14
a0a3408e 15#include <linux/aer.h>
18119775 16#include <linux/async.h>
b60503ba 17#include <linux/blkdev.h>
a4aea562 18#include <linux/blk-mq.h>
dca51e78 19#include <linux/blk-mq-pci.h>
ff5350a8 20#include <linux/dmi.h>
b60503ba
MW		 21#include <linux/init.h>
22#include <linux/interrupt.h>
23#include <linux/io.h>
b60503ba
MW		 24#include <linux/mm.h>
25#include <linux/module.h>
77bf25ea 26#include <linux/mutex.h>
d0877473 27#include <linux/once.h>
b60503ba 28#include <linux/pci.h>
e1e5e564 29#include <linux/t10-pi.h>
b60503ba 30#include <linux/types.h>
2f8e2c87 31#include <linux/io-64-nonatomic-lo-hi.h>
a98e58e5 32#include <linux/sed-opal.h>
0f238ff5 33#include <linux/pci-p2pdma.h>
797a796a 34
f11bb3e2
CH		 35#include "nvme.h"
36
b60503ba
MW		 37#define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
38#define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
c965809c 39
a7a7cbe3 40#define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc))
9d43cf64 41
943e942e
JA		 42/*
43 * These can be higher, but we need to ensure that any command doesn't
44 * require an sg allocation that needs more than a page of data.
45 */
46#define NVME_MAX_KB_SZ 4096
47#define NVME_MAX_SEGS 127
48
58ffacb5
MW		 49static int use_threaded_interrupts;
50module_param(use_threaded_interrupts, int, 0);
51
8ffaadf7 52static bool use_cmb_sqes = true;
69f4eb9f 53module_param(use_cmb_sqes, bool, 0444);
8ffaadf7
JD		 54MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
55
87ad72a5
CH		 56static unsigned int max_host_mem_size_mb = 128;
57module_param(max_host_mem_size_mb, uint, 0444);
58MODULE_PARM_DESC(max_host_mem_size_mb,
59 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
1fa6aead 60
a7a7cbe3
CK		 61static unsigned int sgl_threshold = SZ_32K;
62module_param(sgl_threshold, uint, 0644);
63MODULE_PARM_DESC(sgl_threshold,
64 "Use SGLs when average request segment size is larger or equal to "
65 "this size. Use 0 to disable SGLs.");
66
b27c1e68 67static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
68static const struct kernel_param_ops io_queue_depth_ops = {
69 .set = io_queue_depth_set,
70 .get = param_get_int,
71};
72
73static int io_queue_depth = 1024;
74module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
75MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2");
76
3b6592f7
JA		 77static int queue_count_set(const char *val, const struct kernel_param *kp);
78static const struct kernel_param_ops queue_count_ops = {
79 .set = queue_count_set,
80 .get = param_get_int,
81};
82
83static int write_queues;
84module_param_cb(write_queues, &queue_count_ops, &write_queues, 0644);
85MODULE_PARM_DESC(write_queues,
86 "Number of queues to use for writes. If not set, reads and writes "
87 "will share a queue set.");
88
a4668d9b 89static int poll_queues = 0;
4b04cc6a
JA		 90module_param_cb(poll_queues, &queue_count_ops, &poll_queues, 0644);
91MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO.");
92
1c63dc66
CH		 93struct nvme_dev;
94struct nvme_queue;
b3fffdef 95
a5cdb68c 96static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
d4b4ff8e 97
1c63dc66
CH		 98/*
99 * Represents an NVM Express device. Each nvme_dev is a PCI function.
100 */
101struct nvme_dev {
147b27e4 102 struct nvme_queue *queues;
1c63dc66
CH		 103 struct blk_mq_tag_set tagset;
104 struct blk_mq_tag_set admin_tagset;
105 u32 __iomem *dbs;
106 struct device *dev;
107 struct dma_pool *prp_page_pool;
108 struct dma_pool *prp_small_pool;
1c63dc66
CH		 109 unsigned online_queues;
110 unsigned max_qid;
e20ba6e1 111 unsigned io_queues[HCTX_MAX_TYPES];
22b55601 112 unsigned int num_vecs;
1c63dc66
CH		 113 int q_depth;
114 u32 db_stride;
1c63dc66 115 void __iomem *bar;
97f6ef64 116 unsigned long bar_mapped_size;
5c8809e6 117 struct work_struct remove_work;
77bf25ea 118 struct mutex shutdown_lock;
1c63dc66 119 bool subsystem;
1c63dc66 120 u64 cmb_size;
0f238ff5 121 bool cmb_use_sqes;
1c63dc66 122 u32 cmbsz;
202021c1 123 u32 cmbloc;
1c63dc66 124 struct nvme_ctrl ctrl;
87ad72a5 125
943e942e
JA		 126 mempool_t *iod_mempool;
127
87ad72a5 128 /* shadow doorbell buffer support: */
f9f38e33
HK		 129 u32 *dbbuf_dbs;
130 dma_addr_t dbbuf_dbs_dma_addr;
131 u32 *dbbuf_eis;
132 dma_addr_t dbbuf_eis_dma_addr;
87ad72a5
CH		 133
134 /* host memory buffer support: */
135 u64 host_mem_size;
136 u32 nr_host_mem_descs;
4033f35d 137 dma_addr_t host_mem_descs_dma;
87ad72a5
CH		 138 struct nvme_host_mem_buf_desc *host_mem_descs;
139 void **host_mem_desc_bufs;
4d115420 140};
1fa6aead 141
b27c1e68 142static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
143{
144 int n = 0, ret;
145
146 ret = kstrtoint(val, 10, &n);
147 if (ret != 0 || n < 2)
148 return -EINVAL;
149
150 return param_set_int(val, kp);
151}
152
3b6592f7
JA		 153static int queue_count_set(const char *val, const struct kernel_param *kp)
154{
155 int n = 0, ret;
156
157 ret = kstrtoint(val, 10, &n);
158 if (n > num_possible_cpus())
159 n = num_possible_cpus();
160
161 return param_set_int(val, kp);
162}
163
f9f38e33
HK		 164static inline unsigned int sq_idx(unsigned int qid, u32 stride)
165{
166 return qid * 2 * stride;
167}
168
169static inline unsigned int cq_idx(unsigned int qid, u32 stride)
170{
171 return (qid * 2 + 1) * stride;
172}
173
1c63dc66
CH		 174static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
175{
176 return container_of(ctrl, struct nvme_dev, ctrl);
177}
178
b60503ba
MW		 179/*
180 * An NVM Express queue. Each device has at least two (one for admin
181 * commands and one for I/O commands).
182 */
183struct nvme_queue {
184 struct device *q_dmadev;
091b6092 185 struct nvme_dev *dev;
1ab0cd69 186 spinlock_t sq_lock;
b60503ba 187 struct nvme_command *sq_cmds;
3a7afd8e
CH		 188 /* only used for poll queues: */
189 spinlock_t cq_poll_lock ____cacheline_aligned_in_smp;
b60503ba 190 volatile struct nvme_completion *cqes;
42483228 191 struct blk_mq_tags **tags;
b60503ba
MW		 192 dma_addr_t sq_dma_addr;
193 dma_addr_t cq_dma_addr;
b60503ba
MW		 194 u32 __iomem *q_db;
195 u16 q_depth;
6222d172 196 s16 cq_vector;
b60503ba 197 u16 sq_tail;
04f3eafd 198 u16 last_sq_tail;
b60503ba 199 u16 cq_head;
68fa9dbe 200 u16 last_cq_head;
c30341dc 201 u16 qid;
e9539f47 202 u8 cq_phase;
4e224106
CH		 203 unsigned long flags;
204#define NVMEQ_ENABLED 0
63223078 205#define NVMEQ_SQ_CMB 1
d1ed6aa1 206#define NVMEQ_DELETE_ERROR 2
f9f38e33
HK		 207 u32 *dbbuf_sq_db;
208 u32 *dbbuf_cq_db;
209 u32 *dbbuf_sq_ei;
210 u32 *dbbuf_cq_ei;
d1ed6aa1 211 struct completion delete_done;
b60503ba
MW		 212};
213
71bd150c
CH		 214/*
215 * The nvme_iod describes the data in an I/O, including the list of PRP
216 * entries. You can't see it in this data structure because C doesn't let
f4800d6d 217 * me express that. Use nvme_init_iod to ensure there's enough space
71bd150c
CH		 218 * allocated to store the PRP list.
219 */
220struct nvme_iod {
d49187e9 221 struct nvme_request req;
f4800d6d 222 struct nvme_queue *nvmeq;
a7a7cbe3 223 bool use_sgl;
f4800d6d 224 int aborted;
71bd150c 225 int npages; /* In the PRP list. 0 means small pool in use */
71bd150c
CH		 226 int nents; /* Used in scatterlist */
227 int length; /* Of data, in bytes */
228 dma_addr_t first_dma;
bf684057 229 struct scatterlist meta_sg; /* metadata requires single contiguous buffer */
f4800d6d
CH		 230 struct scatterlist *sg;
231 struct scatterlist inline_sg[0];
b60503ba
MW		 232};
233
234/*
235 * Check we didin't inadvertently grow the command struct
236 */
237static inline void _nvme_check_size(void)
238{
239 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
240 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
241 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
242 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
243 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
f8ebf840 244 BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
c30341dc 245 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
b60503ba 246 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
0add5e8e
JT		 247 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != NVME_IDENTIFY_DATA_SIZE);
248 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != NVME_IDENTIFY_DATA_SIZE);
b60503ba 249 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
6ecec745 250 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
f9f38e33
HK		 251 BUILD_BUG_ON(sizeof(struct nvme_dbbuf) != 64);
252}
253
3b6592f7
JA		 254static unsigned int max_io_queues(void)
255{
4b04cc6a 256 return num_possible_cpus() + write_queues + poll_queues;
3b6592f7
JA		 257}
258
259static unsigned int max_queue_count(void)
260{
261 /* IO queues + admin queue */
262 return 1 + max_io_queues();
263}
264
f9f38e33
HK		 265static inline unsigned int nvme_dbbuf_size(u32 stride)
266{
3b6592f7 267 return (max_queue_count() * 8 * stride);
f9f38e33
HK		 268}
269
270static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
271{
272 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
273
274 if (dev->dbbuf_dbs)
275 return 0;
276
277 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
278 &dev->dbbuf_dbs_dma_addr,
279 GFP_KERNEL);
280 if (!dev->dbbuf_dbs)
281 return -ENOMEM;
282 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
283 &dev->dbbuf_eis_dma_addr,
284 GFP_KERNEL);
285 if (!dev->dbbuf_eis) {
286 dma_free_coherent(dev->dev, mem_size,
287 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
288 dev->dbbuf_dbs = NULL;
289 return -ENOMEM;
290 }
291
292 return 0;
293}
294
295static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
296{
297 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
298
299 if (dev->dbbuf_dbs) {
300 dma_free_coherent(dev->dev, mem_size,
301 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
302 dev->dbbuf_dbs = NULL;
303 }
304 if (dev->dbbuf_eis) {
305 dma_free_coherent(dev->dev, mem_size,
306 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
307 dev->dbbuf_eis = NULL;
308 }
309}
310
311static void nvme_dbbuf_init(struct nvme_dev *dev,
312 struct nvme_queue *nvmeq, int qid)
313{
314 if (!dev->dbbuf_dbs || !qid)
315 return;
316
317 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
318 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
319 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
320 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
321}
322
323static void nvme_dbbuf_set(struct nvme_dev *dev)
324{
325 struct nvme_command c;
326
327 if (!dev->dbbuf_dbs)
328 return;
329
330 memset(&c, 0, sizeof(c));
331 c.dbbuf.opcode = nvme_admin_dbbuf;
332 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
333 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
334
335 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
9bdcfb10 336 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
f9f38e33
HK		 337 /* Free memory and continue on */
338 nvme_dbbuf_dma_free(dev);
339 }
340}
341
342static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
343{
344 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
345}
346
347/* Update dbbuf and return true if an MMIO is required */
348static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
349 volatile u32 *dbbuf_ei)
350{
351 if (dbbuf_db) {
352 u16 old_value;
353
354 /*
355 * Ensure that the queue is written before updating
356 * the doorbell in memory
357 */
358 wmb();
359
360 old_value = *dbbuf_db;
361 *dbbuf_db = value;
362
f1ed3df2
MW		 363 /*
364 * Ensure that the doorbell is updated before reading the event
365 * index from memory. The controller needs to provide similar
366 * ordering to ensure the envent index is updated before reading
367 * the doorbell.
368 */
369 mb();
370
f9f38e33
HK		 371 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value))
372 return false;
373 }
374
375 return true;
b60503ba
MW		 376}
377
ac3dd5bd
JA		 378/*
379 * Max size of iod being embedded in the request payload
380 */
381#define NVME_INT_PAGES 2
5fd4ce1b 382#define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size)
ac3dd5bd
JA		 383
384/*
385 * Will slightly overestimate the number of pages needed. This is OK
386 * as it only leads to a small amount of wasted memory for the lifetime of
387 * the I/O.
388 */
389static int nvme_npages(unsigned size, struct nvme_dev *dev)
390{
5fd4ce1b
CH		 391 unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size,
392 dev->ctrl.page_size);
ac3dd5bd
JA		 393 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
394}
395
a7a7cbe3
CK		 396/*
397 * Calculates the number of pages needed for the SGL segments. For example a 4k
398 * page can accommodate 256 SGL descriptors.
399 */
400static int nvme_pci_npages_sgl(unsigned int num_seg)
ac3dd5bd 401{
a7a7cbe3 402 return DIV_ROUND_UP(num_seg * sizeof(struct nvme_sgl_desc), PAGE_SIZE);
f4800d6d 403}
ac3dd5bd 404
a7a7cbe3
CK		 405static unsigned int nvme_pci_iod_alloc_size(struct nvme_dev *dev,
406 unsigned int size, unsigned int nseg, bool use_sgl)
f4800d6d 407{
a7a7cbe3
CK		 408 size_t alloc_size;
409
410 if (use_sgl)
411 alloc_size = sizeof(__le64 *) * nvme_pci_npages_sgl(nseg);
412 else
413 alloc_size = sizeof(__le64 *) * nvme_npages(size, dev);
414
415 return alloc_size + sizeof(struct scatterlist) * nseg;
f4800d6d 416}
ac3dd5bd 417
a7a7cbe3 418static unsigned int nvme_pci_cmd_size(struct nvme_dev *dev, bool use_sgl)
f4800d6d 419{
a7a7cbe3
CK		 420 unsigned int alloc_size = nvme_pci_iod_alloc_size(dev,
421 NVME_INT_BYTES(dev), NVME_INT_PAGES,
422 use_sgl);
423
424 return sizeof(struct nvme_iod) + alloc_size;
ac3dd5bd
JA		 425}
426
a4aea562
MB		 427static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
428 unsigned int hctx_idx)
e85248e5 429{
a4aea562 430 struct nvme_dev *dev = data;
147b27e4 431 struct nvme_queue *nvmeq = &dev->queues[0];
a4aea562 432
42483228
KB		 433 WARN_ON(hctx_idx != 0);
434 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
435 WARN_ON(nvmeq->tags);
436
a4aea562 437 hctx->driver_data = nvmeq;
42483228 438 nvmeq->tags = &dev->admin_tagset.tags[0];
a4aea562 439 return 0;
e85248e5
MW		 440}
441
4af0e21c
KB		 442static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
443{
444 struct nvme_queue *nvmeq = hctx->driver_data;
445
446 nvmeq->tags = NULL;
447}
448
a4aea562
MB		 449static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
450 unsigned int hctx_idx)
b60503ba 451{
a4aea562 452 struct nvme_dev *dev = data;
147b27e4 453 struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
a4aea562 454
42483228
KB		 455 if (!nvmeq->tags)
456 nvmeq->tags = &dev->tagset.tags[hctx_idx];
b60503ba 457
42483228 458 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
a4aea562
MB		 459 hctx->driver_data = nvmeq;
460 return 0;
b60503ba
MW		 461}
462
d6296d39
CH		 463static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req,
464 unsigned int hctx_idx, unsigned int numa_node)
b60503ba 465{
d6296d39 466 struct nvme_dev *dev = set->driver_data;
f4800d6d 467 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
0350815a 468 int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0;
147b27e4 469 struct nvme_queue *nvmeq = &dev->queues[queue_idx];
a4aea562
MB		 470
471 BUG_ON(!nvmeq);
f4800d6d 472 iod->nvmeq = nvmeq;
59e29ce6
SG		 473
474 nvme_req(req)->ctrl = &dev->ctrl;
a4aea562
MB		 475 return 0;
476}
477
3b6592f7
JA		 478static int queue_irq_offset(struct nvme_dev *dev)
479{
480 /* if we have more than 1 vec, admin queue offsets us by 1 */
481 if (dev->num_vecs > 1)
482 return 1;
483
484 return 0;
485}
486
dca51e78
CH		 487static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
488{
489 struct nvme_dev *dev = set->driver_data;
3b6592f7
JA		 490 int i, qoff, offset;
491
492 offset = queue_irq_offset(dev);
493 for (i = 0, qoff = 0; i < set->nr_maps; i++) {
494 struct blk_mq_queue_map *map = &set->map[i];
495
496 map->nr_queues = dev->io_queues[i];
497 if (!map->nr_queues) {
e20ba6e1 498 BUG_ON(i == HCTX_TYPE_DEFAULT);
dca51e78 499
3b6592f7 500 /* shared set, resuse read set parameters */
e20ba6e1 501 map->nr_queues = dev->io_queues[HCTX_TYPE_DEFAULT];
3b6592f7
JA		 502 qoff = 0;
503 offset = queue_irq_offset(dev);
504 }
505
4b04cc6a
JA		 506 /*
507 * The poll queue(s) doesn't have an IRQ (and hence IRQ
508 * affinity), so use the regular blk-mq cpu mapping
509 */
3b6592f7 510 map->queue_offset = qoff;
e20ba6e1 511 if (i != HCTX_TYPE_POLL)
4b04cc6a
JA		 512 blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset);
513 else
514 blk_mq_map_queues(map);
3b6592f7
JA		 515 qoff += map->nr_queues;
516 offset += map->nr_queues;
517 }
518
519 return 0;
dca51e78
CH		 520}
521
04f3eafd
JA		 522/*
523 * Write sq tail if we are asked to, or if the next command would wrap.
524 */
525static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq)
526{
527 if (!write_sq) {
528 u16 next_tail = nvmeq->sq_tail + 1;
529
530 if (next_tail == nvmeq->q_depth)
531 next_tail = 0;
532 if (next_tail != nvmeq->last_sq_tail)
533 return;
534 }
535
536 if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail,
537 nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei))
538 writel(nvmeq->sq_tail, nvmeq->q_db);
539 nvmeq->last_sq_tail = nvmeq->sq_tail;
540}
541
b60503ba 542/**
90ea5ca4 543 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
b60503ba
MW		 544 * @nvmeq: The queue to use
545 * @cmd: The command to send
04f3eafd 546 * @write_sq: whether to write to the SQ doorbell
b60503ba 547 */
04f3eafd
JA		 548static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd,
549 bool write_sq)
b60503ba 550{
90ea5ca4 551 spin_lock(&nvmeq->sq_lock);
0f238ff5 552 memcpy(&nvmeq->sq_cmds[nvmeq->sq_tail], cmd, sizeof(*cmd));
90ea5ca4
CH		 553 if (++nvmeq->sq_tail == nvmeq->q_depth)
554 nvmeq->sq_tail = 0;
04f3eafd
JA		 555 nvme_write_sq_db(nvmeq, write_sq);
556 spin_unlock(&nvmeq->sq_lock);
557}
558
559static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx)
560{
561 struct nvme_queue *nvmeq = hctx->driver_data;
562
563 spin_lock(&nvmeq->sq_lock);
564 if (nvmeq->sq_tail != nvmeq->last_sq_tail)
565 nvme_write_sq_db(nvmeq, true);
90ea5ca4 566 spin_unlock(&nvmeq->sq_lock);
b60503ba
MW		 567}
568
a7a7cbe3 569static void **nvme_pci_iod_list(struct request *req)
b60503ba 570{
f4800d6d 571 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3 572 return (void **)(iod->sg + blk_rq_nr_phys_segments(req));
b60503ba
MW		 573}
574
955b1b5a
MI		 575static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req)
576{
577 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
20469a37 578 int nseg = blk_rq_nr_phys_segments(req);
955b1b5a
MI		 579 unsigned int avg_seg_size;
580
20469a37
KB		 581 if (nseg == 0)
582 return false;
583
584 avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
955b1b5a
MI		 585
586 if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1))))
587 return false;
588 if (!iod->nvmeq->qid)
589 return false;
590 if (!sgl_threshold || avg_seg_size < sgl_threshold)
591 return false;
592 return true;
593}
594
fc17b653 595static blk_status_t nvme_init_iod(struct request *rq, struct nvme_dev *dev)
ac3dd5bd 596{
f4800d6d 597 struct nvme_iod *iod = blk_mq_rq_to_pdu(rq);
f9d03f96 598 int nseg = blk_rq_nr_phys_segments(rq);
b131c61d 599 unsigned int size = blk_rq_payload_bytes(rq);
ac3dd5bd 600
955b1b5a
MI		 601 iod->use_sgl = nvme_pci_use_sgls(dev, rq);
602
f4800d6d 603 if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) {
943e942e 604 iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC);
f4800d6d 605 if (!iod->sg)
fc17b653 606 return BLK_STS_RESOURCE;
f4800d6d
CH		 607 } else {
608 iod->sg = iod->inline_sg;
ac3dd5bd
JA		 609 }
610
f4800d6d
CH		 611 iod->aborted = 0;
612 iod->npages = -1;
613 iod->nents = 0;
614 iod->length = size;
f80ec966 615
fc17b653 616 return BLK_STS_OK;
ac3dd5bd
JA		 617}
618
f4800d6d 619static void nvme_free_iod(struct nvme_dev *dev, struct request *req)
b60503ba 620{
f4800d6d 621 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3
CK		 622 const int last_prp = dev->ctrl.page_size / sizeof(__le64) - 1;
623 dma_addr_t dma_addr = iod->first_dma, next_dma_addr;
624
eca18b23 625 int i;
eca18b23
MW		 626
627 if (iod->npages == 0)
a7a7cbe3
CK		 628 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0],
629 dma_addr);
630
eca18b23 631 for (i = 0; i < iod->npages; i++) {
a7a7cbe3
CK		 632 void *addr = nvme_pci_iod_list(req)[i];
633
634 if (iod->use_sgl) {
635 struct nvme_sgl_desc *sg_list = addr;
636
637 next_dma_addr =
638 le64_to_cpu((sg_list[SGES_PER_PAGE - 1]).addr);
639 } else {
640 __le64 *prp_list = addr;
641
642 next_dma_addr = le64_to_cpu(prp_list[last_prp]);
643 }
644
645 dma_pool_free(dev->prp_page_pool, addr, dma_addr);
646 dma_addr = next_dma_addr;
eca18b23 647 }
ac3dd5bd 648
f4800d6d 649 if (iod->sg != iod->inline_sg)
943e942e 650 mempool_free(iod->sg, dev->iod_mempool);
b4ff9c8d
KB		 651}
652
d0877473
KB		 653static void nvme_print_sgl(struct scatterlist *sgl, int nents)
654{
655 int i;
656 struct scatterlist *sg;
657
658 for_each_sg(sgl, sg, nents, i) {
659 dma_addr_t phys = sg_phys(sg);
660 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
661 "dma_address:%pad dma_length:%d\n",
662 i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
663 sg_dma_len(sg));
664 }
665}
666
a7a7cbe3
CK		 667static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
668 struct request *req, struct nvme_rw_command *cmnd)
ff22b54f 669{
f4800d6d 670 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
99802a7a 671 struct dma_pool *pool;
b131c61d 672 int length = blk_rq_payload_bytes(req);
eca18b23 673 struct scatterlist *sg = iod->sg;
ff22b54f
MW		 674 int dma_len = sg_dma_len(sg);
675 u64 dma_addr = sg_dma_address(sg);
5fd4ce1b 676 u32 page_size = dev->ctrl.page_size;
f137e0f1 677 int offset = dma_addr & (page_size - 1);
e025344c 678 __le64 *prp_list;
a7a7cbe3 679 void **list = nvme_pci_iod_list(req);
e025344c 680 dma_addr_t prp_dma;
eca18b23 681 int nprps, i;
ff22b54f 682
1d090624 683 length -= (page_size - offset);
5228b328
JS		 684 if (length <= 0) {
685 iod->first_dma = 0;
a7a7cbe3 686 goto done;
5228b328 687 }
ff22b54f 688
1d090624 689 dma_len -= (page_size - offset);
ff22b54f 690 if (dma_len) {
1d090624 691 dma_addr += (page_size - offset);
ff22b54f
MW		 692 } else {
693 sg = sg_next(sg);
694 dma_addr = sg_dma_address(sg);
695 dma_len = sg_dma_len(sg);
696 }
697
1d090624 698 if (length <= page_size) {
edd10d33 699 iod->first_dma = dma_addr;
a7a7cbe3 700 goto done;
e025344c
SMM		 701 }
702
1d090624 703 nprps = DIV_ROUND_UP(length, page_size);
99802a7a
MW		 704 if (nprps <= (256 / 8)) {
705 pool = dev->prp_small_pool;
eca18b23 706 iod->npages = 0;
99802a7a
MW		 707 } else {
708 pool = dev->prp_page_pool;
eca18b23 709 iod->npages = 1;
99802a7a
MW		 710 }
711
69d2b571 712 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
b77954cb 713 if (!prp_list) {
edd10d33 714 iod->first_dma = dma_addr;
eca18b23 715 iod->npages = -1;
86eea289 716 return BLK_STS_RESOURCE;
b77954cb 717 }
eca18b23
MW		 718 list[0] = prp_list;
719 iod->first_dma = prp_dma;
e025344c
SMM		 720 i = 0;
721 for (;;) {
1d090624 722 if (i == page_size >> 3) {
e025344c 723 __le64 *old_prp_list = prp_list;
69d2b571 724 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
eca18b23 725 if (!prp_list)
86eea289 726 return BLK_STS_RESOURCE;
eca18b23 727 list[iod->npages++] = prp_list;
7523d834
MW		 728 prp_list[0] = old_prp_list[i - 1];
729 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
730 i = 1;
e025344c
SMM		 731 }
732 prp_list[i++] = cpu_to_le64(dma_addr);
1d090624
KB		 733 dma_len -= page_size;
734 dma_addr += page_size;
735 length -= page_size;
e025344c
SMM		 736 if (length <= 0)
737 break;
738 if (dma_len > 0)
739 continue;
86eea289
KB		 740 if (unlikely(dma_len < 0))
741 goto bad_sgl;
e025344c
SMM		 742 sg = sg_next(sg);
743 dma_addr = sg_dma_address(sg);
744 dma_len = sg_dma_len(sg);
ff22b54f
MW		 745 }
746
a7a7cbe3
CK		 747done:
748 cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
749 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
750
86eea289
KB		 751 return BLK_STS_OK;
752
753 bad_sgl:
d0877473
KB		 754 WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents),
755 "Invalid SGL for payload:%d nents:%d\n",
756 blk_rq_payload_bytes(req), iod->nents);
86eea289 757 return BLK_STS_IOERR;
ff22b54f
MW		 758}
759
a7a7cbe3
CK		 760static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
761 struct scatterlist *sg)
762{
763 sge->addr = cpu_to_le64(sg_dma_address(sg));
764 sge->length = cpu_to_le32(sg_dma_len(sg));
765 sge->type = NVME_SGL_FMT_DATA_DESC << 4;
766}
767
768static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
769 dma_addr_t dma_addr, int entries)
770{
771 sge->addr = cpu_to_le64(dma_addr);
772 if (entries < SGES_PER_PAGE) {
773 sge->length = cpu_to_le32(entries * sizeof(*sge));
774 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
775 } else {
776 sge->length = cpu_to_le32(PAGE_SIZE);
777 sge->type = NVME_SGL_FMT_SEG_DESC << 4;
778 }
779}
780
781static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
b0f2853b 782 struct request *req, struct nvme_rw_command *cmd, int entries)
a7a7cbe3
CK		 783{
784 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3
CK		 785 struct dma_pool *pool;
786 struct nvme_sgl_desc *sg_list;
787 struct scatterlist *sg = iod->sg;
a7a7cbe3 788 dma_addr_t sgl_dma;
b0f2853b 789 int i = 0;
a7a7cbe3 790
a7a7cbe3
CK		 791 /* setting the transfer type as SGL */
792 cmd->flags = NVME_CMD_SGL_METABUF;
793
b0f2853b 794 if (entries == 1) {
a7a7cbe3
CK		 795 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
796 return BLK_STS_OK;
797 }
798
799 if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
800 pool = dev->prp_small_pool;
801 iod->npages = 0;
802 } else {
803 pool = dev->prp_page_pool;
804 iod->npages = 1;
805 }
806
807 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
808 if (!sg_list) {
809 iod->npages = -1;
810 return BLK_STS_RESOURCE;
811 }
812
813 nvme_pci_iod_list(req)[0] = sg_list;
814 iod->first_dma = sgl_dma;
815
816 nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
817
818 do {
819 if (i == SGES_PER_PAGE) {
820 struct nvme_sgl_desc *old_sg_desc = sg_list;
821 struct nvme_sgl_desc *link = &old_sg_desc[i - 1];
822
823 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
824 if (!sg_list)
825 return BLK_STS_RESOURCE;
826
827 i = 0;
828 nvme_pci_iod_list(req)[iod->npages++] = sg_list;
829 sg_list[i++] = *link;
830 nvme_pci_sgl_set_seg(link, sgl_dma, entries);
831 }
832
833 nvme_pci_sgl_set_data(&sg_list[i++], sg);
a7a7cbe3 834 sg = sg_next(sg);
b0f2853b 835 } while (--entries > 0);
a7a7cbe3 836
a7a7cbe3
CK		 837 return BLK_STS_OK;
838}
839
fc17b653 840static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
b131c61d 841 struct nvme_command *cmnd)
d29ec824 842{
f4800d6d 843 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
ba1ca37e
CH		 844 struct request_queue *q = req->q;
845 enum dma_data_direction dma_dir = rq_data_dir(req) ?
846 DMA_TO_DEVICE : DMA_FROM_DEVICE;
fc17b653 847 blk_status_t ret = BLK_STS_IOERR;
b0f2853b 848 int nr_mapped;
d29ec824 849
f9d03f96 850 sg_init_table(iod->sg, blk_rq_nr_phys_segments(req));
ba1ca37e
CH		 851 iod->nents = blk_rq_map_sg(q, req, iod->sg);
852 if (!iod->nents)
853 goto out;
d29ec824 854
fc17b653 855 ret = BLK_STS_RESOURCE;
e0596ab2
LG		 856
857 if (is_pci_p2pdma_page(sg_page(iod->sg)))
858 nr_mapped = pci_p2pdma_map_sg(dev->dev, iod->sg, iod->nents,
859 dma_dir);
860 else
861 nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents,
862 dma_dir, DMA_ATTR_NO_WARN);
b0f2853b 863 if (!nr_mapped)
ba1ca37e 864 goto out;
d29ec824 865
955b1b5a 866 if (iod->use_sgl)
b0f2853b 867 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped);
a7a7cbe3
CK		 868 else
869 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
870
86eea289 871 if (ret != BLK_STS_OK)
ba1ca37e 872 goto out_unmap;
0e5e4f0e 873
fc17b653 874 ret = BLK_STS_IOERR;
ba1ca37e
CH		 875 if (blk_integrity_rq(req)) {
876 if (blk_rq_count_integrity_sg(q, req->bio) != 1)
877 goto out_unmap;
0e5e4f0e 878
bf684057
CH		 879 sg_init_table(&iod->meta_sg, 1);
880 if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1)
ba1ca37e 881 goto out_unmap;
0e5e4f0e 882
bf684057 883 if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir))
ba1ca37e 884 goto out_unmap;
00df5cb4 885
bf684057 886 cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg));
3045c0d0
CK		 887 }
888
fc17b653 889 return BLK_STS_OK;
00df5cb4 890
ba1ca37e
CH		 891out_unmap:
892 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
893out:
894 return ret;
00df5cb4
MW		 895}
896
f4800d6d 897static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
b60503ba 898{
f4800d6d 899 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
d4f6c3ab
CH		 900 enum dma_data_direction dma_dir = rq_data_dir(req) ?
901 DMA_TO_DEVICE : DMA_FROM_DEVICE;
902
903 if (iod->nents) {
e0596ab2
LG		 904 /* P2PDMA requests do not need to be unmapped */
905 if (!is_pci_p2pdma_page(sg_page(iod->sg)))
906 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
907
f7f1fc36 908 if (blk_integrity_rq(req))
bf684057 909 dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir);
e19b127f 910 }
e1e5e564 911
f9d03f96 912 nvme_cleanup_cmd(req);
f4800d6d 913 nvme_free_iod(dev, req);
d4f6c3ab 914}
b60503ba 915
d29ec824
CH		 916/*
917 * NOTE: ns is NULL when called on the admin queue.
918 */
fc17b653 919static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
a4aea562 920 const struct blk_mq_queue_data *bd)
edd10d33 921{
a4aea562
MB		 922 struct nvme_ns *ns = hctx->queue->queuedata;
923 struct nvme_queue *nvmeq = hctx->driver_data;
d29ec824 924 struct nvme_dev *dev = nvmeq->dev;
a4aea562 925 struct request *req = bd->rq;
ba1ca37e 926 struct nvme_command cmnd;
ebe6d874 927 blk_status_t ret;
e1e5e564 928
d1f06f4a
JA		 929 /*
930 * We should not need to do this, but we're still using this to
931 * ensure we can drain requests on a dying queue.
932 */
4e224106 933 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
d1f06f4a
JA		 934 return BLK_STS_IOERR;
935
f9d03f96 936 ret = nvme_setup_cmd(ns, req, &cmnd);
fc17b653 937 if (ret)
f4800d6d 938 return ret;
a4aea562 939
b131c61d 940 ret = nvme_init_iod(req, dev);
fc17b653 941 if (ret)
f9d03f96 942 goto out_free_cmd;
a4aea562 943
fc17b653 944 if (blk_rq_nr_phys_segments(req)) {
b131c61d 945 ret = nvme_map_data(dev, req, &cmnd);
fc17b653
CH		 946 if (ret)
947 goto out_cleanup_iod;
948 }
a4aea562 949
aae239e1 950 blk_mq_start_request(req);
04f3eafd 951 nvme_submit_cmd(nvmeq, &cmnd, bd->last);
fc17b653 952 return BLK_STS_OK;
f9d03f96 953out_cleanup_iod:
f4800d6d 954 nvme_free_iod(dev, req);
f9d03f96
CH		 955out_free_cmd:
956 nvme_cleanup_cmd(req);
ba1ca37e 957 return ret;
b60503ba 958}
e1e5e564 959
77f02a7a 960static void nvme_pci_complete_rq(struct request *req)
eee417b0 961{
f4800d6d 962 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a4aea562 963
77f02a7a
CH		 964 nvme_unmap_data(iod->nvmeq->dev, req);
965 nvme_complete_rq(req);
b60503ba
MW		 966}
967
d783e0bd 968/* We read the CQE phase first to check if the rest of the entry is valid */
750dde44 969static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq)
d783e0bd 970{
750dde44
CH		 971 return (le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) ==
972 nvmeq->cq_phase;
d783e0bd
MR		 973}
974
eb281c82 975static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
b60503ba 976{
eb281c82 977 u16 head = nvmeq->cq_head;
adf68f21 978
397c699f
KB		 979 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
980 nvmeq->dbbuf_cq_ei))
981 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
eb281c82 982}
aae239e1 983
5cb525c8 984static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx)
83a12fb7 985{
5cb525c8 986 volatile struct nvme_completion *cqe = &nvmeq->cqes[idx];
83a12fb7 987 struct request *req;
adf68f21 988
83a12fb7
SG		 989 if (unlikely(cqe->command_id >= nvmeq->q_depth)) {
990 dev_warn(nvmeq->dev->ctrl.device,
991 "invalid id %d completed on queue %d\n",
992 cqe->command_id, le16_to_cpu(cqe->sq_id));
993 return;
b60503ba
MW		 994 }
995
83a12fb7
SG		 996 /*
997 * AEN requests are special as they don't time out and can
998 * survive any kind of queue freeze and often don't respond to
999 * aborts. We don't even bother to allocate a struct request
1000 * for them but rather special case them here.
1001 */
1002 if (unlikely(nvmeq->qid == 0 &&
38dabe21 1003 cqe->command_id >= NVME_AQ_BLK_MQ_DEPTH)) {
83a12fb7
SG		 1004 nvme_complete_async_event(&nvmeq->dev->ctrl,
1005 cqe->status, &cqe->result);
a0fa9647 1006 return;
83a12fb7 1007 }
b60503ba 1008
83a12fb7
SG		 1009 req = blk_mq_tag_to_rq(*nvmeq->tags, cqe->command_id);
1010 nvme_end_request(req, cqe->status, cqe->result);
1011}
b60503ba 1012
5cb525c8 1013static void nvme_complete_cqes(struct nvme_queue *nvmeq, u16 start, u16 end)
b60503ba 1014{
5cb525c8
JA		 1015 while (start != end) {
1016 nvme_handle_cqe(nvmeq, start);
1017 if (++start == nvmeq->q_depth)
1018 start = 0;
1019 }
1020}
adf68f21 1021
5cb525c8
JA		 1022static inline void nvme_update_cq_head(struct nvme_queue *nvmeq)
1023{
1024 if (++nvmeq->cq_head == nvmeq->q_depth) {
1025 nvmeq->cq_head = 0;
1026 nvmeq->cq_phase = !nvmeq->cq_phase;
b60503ba 1027 }
a0fa9647
JA		 1028}
1029
1052b8ac
JA		 1030static inline int nvme_process_cq(struct nvme_queue *nvmeq, u16 *start,
1031 u16 *end, unsigned int tag)
a0fa9647 1032{
1052b8ac 1033 int found = 0;
b60503ba 1034
5cb525c8 1035 *start = nvmeq->cq_head;
1052b8ac
JA		 1036 while (nvme_cqe_pending(nvmeq)) {
1037 if (tag == -1U || nvmeq->cqes[nvmeq->cq_head].command_id == tag)
1038 found++;
5cb525c8 1039 nvme_update_cq_head(nvmeq);
920d13a8 1040 }
5cb525c8 1041 *end = nvmeq->cq_head;
eb281c82 1042
5cb525c8 1043 if (*start != *end)
920d13a8 1044 nvme_ring_cq_doorbell(nvmeq);
5cb525c8 1045 return found;
b60503ba
MW		 1046}
1047
1048static irqreturn_t nvme_irq(int irq, void *data)
58ffacb5 1049{
58ffacb5 1050 struct nvme_queue *nvmeq = data;
68fa9dbe 1051 irqreturn_t ret = IRQ_NONE;
5cb525c8
JA		 1052 u16 start, end;
1053
3a7afd8e
CH		 1054 /*
1055 * The rmb/wmb pair ensures we see all updates from a previous run of
1056 * the irq handler, even if that was on another CPU.
1057 */
1058 rmb();
68fa9dbe
JA		 1059 if (nvmeq->cq_head != nvmeq->last_cq_head)
1060 ret = IRQ_HANDLED;
5cb525c8 1061 nvme_process_cq(nvmeq, &start, &end, -1);
68fa9dbe 1062 nvmeq->last_cq_head = nvmeq->cq_head;
3a7afd8e 1063 wmb();
5cb525c8 1064
68fa9dbe
JA		 1065 if (start != end) {
1066 nvme_complete_cqes(nvmeq, start, end);
1067 return IRQ_HANDLED;
1068 }
1069
1070 return ret;
58ffacb5
MW		 1071}
1072
1073static irqreturn_t nvme_irq_check(int irq, void *data)
1074{
1075 struct nvme_queue *nvmeq = data;
750dde44 1076 if (nvme_cqe_pending(nvmeq))
d783e0bd
MR		 1077 return IRQ_WAKE_THREAD;
1078 return IRQ_NONE;
58ffacb5
MW		 1079}
1080
0b2a8a9f
CH		 1081/*
1082 * Poll for completions any queue, including those not dedicated to polling.
1083 * Can be called from any context.
1084 */
1085static int nvme_poll_irqdisable(struct nvme_queue *nvmeq, unsigned int tag)
a0fa9647 1086{
3a7afd8e 1087 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
5cb525c8 1088 u16 start, end;
1052b8ac 1089 int found;
a0fa9647 1090
3a7afd8e
CH		 1091 /*
1092 * For a poll queue we need to protect against the polling thread
1093 * using the CQ lock. For normal interrupt driven threads we have
1094 * to disable the interrupt to avoid racing with it.
1095 */
1096 if (nvmeq->cq_vector == -1)
1097 spin_lock(&nvmeq->cq_poll_lock);
1098 else
1099 disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
5cb525c8 1100 found = nvme_process_cq(nvmeq, &start, &end, tag);
3a7afd8e
CH		 1101 if (nvmeq->cq_vector == -1)
1102 spin_unlock(&nvmeq->cq_poll_lock);
1103 else
1104 enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
442e19b7 1105
5cb525c8 1106 nvme_complete_cqes(nvmeq, start, end);
442e19b7 1107 return found;
a0fa9647
JA		 1108}
1109
9743139c 1110static int nvme_poll(struct blk_mq_hw_ctx *hctx)
dabcefab
JA		 1111{
1112 struct nvme_queue *nvmeq = hctx->driver_data;
1113 u16 start, end;
1114 bool found;
1115
1116 if (!nvme_cqe_pending(nvmeq))
1117 return 0;
1118
3a7afd8e 1119 spin_lock(&nvmeq->cq_poll_lock);
9743139c 1120 found = nvme_process_cq(nvmeq, &start, &end, -1);
3a7afd8e 1121 spin_unlock(&nvmeq->cq_poll_lock);
dabcefab
JA		 1122
1123 nvme_complete_cqes(nvmeq, start, end);
1124 return found;
1125}
1126
ad22c355 1127static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
b60503ba 1128{
f866fc42 1129 struct nvme_dev *dev = to_nvme_dev(ctrl);
147b27e4 1130 struct nvme_queue *nvmeq = &dev->queues[0];
a4aea562 1131 struct nvme_command c;
b60503ba 1132
a4aea562
MB		 1133 memset(&c, 0, sizeof(c));
1134 c.common.opcode = nvme_admin_async_event;
ad22c355 1135 c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
04f3eafd 1136 nvme_submit_cmd(nvmeq, &c, true);
f705f837
CH		 1137}
1138
b60503ba 1139static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
f705f837 1140{
b60503ba
MW		 1141 struct nvme_command c;
1142
1143 memset(&c, 0, sizeof(c));
1144 c.delete_queue.opcode = opcode;
1145 c.delete_queue.qid = cpu_to_le16(id);
1146
1c63dc66 1147 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1148}
1149
b60503ba 1150static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
a8e3e0bb 1151 struct nvme_queue *nvmeq, s16 vector)
b60503ba 1152{
b60503ba 1153 struct nvme_command c;
4b04cc6a
JA		 1154 int flags = NVME_QUEUE_PHYS_CONTIG;
1155
1156 if (vector != -1)
1157 flags |= NVME_CQ_IRQ_ENABLED;
b60503ba 1158
d29ec824 1159 /*
16772ae6 1160 * Note: we (ab)use the fact that the prp fields survive if no data
d29ec824
CH		 1161 * is attached to the request.
1162 */
b60503ba
MW		 1163 memset(&c, 0, sizeof(c));
1164 c.create_cq.opcode = nvme_admin_create_cq;
1165 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1166 c.create_cq.cqid = cpu_to_le16(qid);
1167 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1168 c.create_cq.cq_flags = cpu_to_le16(flags);
4b04cc6a
JA		 1169 if (vector != -1)
1170 c.create_cq.irq_vector = cpu_to_le16(vector);
1171 else
1172 c.create_cq.irq_vector = 0;
b60503ba 1173
1c63dc66 1174 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1175}
1176
1177static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1178 struct nvme_queue *nvmeq)
1179{
9abd68ef 1180 struct nvme_ctrl *ctrl = &dev->ctrl;
b60503ba 1181 struct nvme_command c;
81c1cd98 1182 int flags = NVME_QUEUE_PHYS_CONTIG;
b60503ba 1183
9abd68ef
JA		 1184 /*
1185 * Some drives have a bug that auto-enables WRRU if MEDIUM isn't
1186 * set. Since URGENT priority is zeroes, it makes all queues
1187 * URGENT.
1188 */
1189 if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ)
1190 flags |= NVME_SQ_PRIO_MEDIUM;
1191
d29ec824 1192 /*
16772ae6 1193 * Note: we (ab)use the fact that the prp fields survive if no data
d29ec824
CH		 1194 * is attached to the request.
1195 */
b60503ba
MW		 1196 memset(&c, 0, sizeof(c));
1197 c.create_sq.opcode = nvme_admin_create_sq;
1198 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1199 c.create_sq.sqid = cpu_to_le16(qid);
1200 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1201 c.create_sq.sq_flags = cpu_to_le16(flags);
1202 c.create_sq.cqid = cpu_to_le16(qid);
1203
1c63dc66 1204 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1205}
1206
1207static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1208{
1209 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1210}
1211
1212static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1213{
1214 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1215}
1216
2a842aca 1217static void abort_endio(struct request *req, blk_status_t error)
bc5fc7e4 1218{
f4800d6d
CH		 1219 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1220 struct nvme_queue *nvmeq = iod->nvmeq;
e44ac588 1221
27fa9bc5
CH		 1222 dev_warn(nvmeq->dev->ctrl.device,
1223 "Abort status: 0x%x", nvme_req(req)->status);
e7a2a87d 1224 atomic_inc(&nvmeq->dev->ctrl.abort_limit);
e7a2a87d 1225 blk_mq_free_request(req);
bc5fc7e4
MW		 1226}
1227
b2a0eb1a
KB		 1228static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1229{
1230
1231 /* If true, indicates loss of adapter communication, possibly by a
1232 * NVMe Subsystem reset.
1233 */
1234 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1235
ad70062c
JW		 1236 /* If there is a reset/reinit ongoing, we shouldn't reset again. */
1237 switch (dev->ctrl.state) {
1238 case NVME_CTRL_RESETTING:
ad6a0a52 1239 case NVME_CTRL_CONNECTING:
b2a0eb1a 1240 return false;
ad70062c
JW		 1241 default:
1242 break;
1243 }
b2a0eb1a
KB		 1244
1245 /* We shouldn't reset unless the controller is on fatal error state
1246 * _or_ if we lost the communication with it.
1247 */
1248 if (!(csts & NVME_CSTS_CFS) && !nssro)
1249 return false;
1250
b2a0eb1a
KB		 1251 return true;
1252}
1253
1254static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1255{
1256 /* Read a config register to help see what died. */
1257 u16 pci_status;
1258 int result;
1259
1260 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1261 &pci_status);
1262 if (result == PCIBIOS_SUCCESSFUL)
1263 dev_warn(dev->ctrl.device,
1264 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1265 csts, pci_status);
1266 else
1267 dev_warn(dev->ctrl.device,
1268 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1269 csts, result);
1270}
1271
31c7c7d2 1272static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
c30341dc 1273{
f4800d6d
CH		 1274 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1275 struct nvme_queue *nvmeq = iod->nvmeq;
c30341dc 1276 struct nvme_dev *dev = nvmeq->dev;
a4aea562 1277 struct request *abort_req;
a4aea562 1278 struct nvme_command cmd;
b2a0eb1a
KB		 1279 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1280
651438bb
WX		 1281 /* If PCI error recovery process is happening, we cannot reset or
1282 * the recovery mechanism will surely fail.
1283 */
1284 mb();
1285 if (pci_channel_offline(to_pci_dev(dev->dev)))
1286 return BLK_EH_RESET_TIMER;
1287
b2a0eb1a
KB		 1288 /*
1289 * Reset immediately if the controller is failed
1290 */
1291 if (nvme_should_reset(dev, csts)) {
1292 nvme_warn_reset(dev, csts);
1293 nvme_dev_disable(dev, false);
d86c4d8e 1294 nvme_reset_ctrl(&dev->ctrl);
db8c48e4 1295 return BLK_EH_DONE;
b2a0eb1a 1296 }
c30341dc 1297
7776db1c
KB		 1298 /*
1299 * Did we miss an interrupt?
1300 */
0b2a8a9f 1301 if (nvme_poll_irqdisable(nvmeq, req->tag)) {
7776db1c
KB		 1302 dev_warn(dev->ctrl.device,
1303 "I/O %d QID %d timeout, completion polled\n",
1304 req->tag, nvmeq->qid);
db8c48e4 1305 return BLK_EH_DONE;
7776db1c
KB		 1306 }
1307
31c7c7d2 1308 /*
fd634f41
CH		 1309 * Shutdown immediately if controller times out while starting. The
1310 * reset work will see the pci device disabled when it gets the forced
1311 * cancellation error. All outstanding requests are completed on
db8c48e4 1312 * shutdown, so we return BLK_EH_DONE.
fd634f41 1313 */
4244140d
KB		 1314 switch (dev->ctrl.state) {
1315 case NVME_CTRL_CONNECTING:
1316 case NVME_CTRL_RESETTING:
b9cac43c 1317 dev_warn_ratelimited(dev->ctrl.device,
fd634f41
CH		 1318 "I/O %d QID %d timeout, disable controller\n",
1319 req->tag, nvmeq->qid);
a5cdb68c 1320 nvme_dev_disable(dev, false);
27fa9bc5 1321 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
db8c48e4 1322 return BLK_EH_DONE;
4244140d
KB		 1323 default:
1324 break;
c30341dc
KB		 1325 }
1326
fd634f41
CH		 1327 /*
1328 * Shutdown the controller immediately and schedule a reset if the
1329 * command was already aborted once before and still hasn't been
1330 * returned to the driver, or if this is the admin queue.
31c7c7d2 1331 */
f4800d6d 1332 if (!nvmeq->qid || iod->aborted) {
1b3c47c1 1333 dev_warn(dev->ctrl.device,
e1569a16
KB		 1334 "I/O %d QID %d timeout, reset controller\n",
1335 req->tag, nvmeq->qid);
a5cdb68c 1336 nvme_dev_disable(dev, false);
d86c4d8e 1337 nvme_reset_ctrl(&dev->ctrl);
c30341dc 1338
27fa9bc5 1339 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
db8c48e4 1340 return BLK_EH_DONE;
c30341dc 1341 }
c30341dc 1342
e7a2a87d 1343 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
6bf25d16 1344 atomic_inc(&dev->ctrl.abort_limit);
31c7c7d2 1345 return BLK_EH_RESET_TIMER;
6bf25d16 1346 }
7bf7d778 1347 iod->aborted = 1;
a4aea562 1348
c30341dc
KB		 1349 memset(&cmd, 0, sizeof(cmd));
1350 cmd.abort.opcode = nvme_admin_abort_cmd;
a4aea562 1351 cmd.abort.cid = req->tag;
c30341dc 1352 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
c30341dc 1353
1b3c47c1
SG		 1354 dev_warn(nvmeq->dev->ctrl.device,
1355 "I/O %d QID %d timeout, aborting\n",
1356 req->tag, nvmeq->qid);
e7a2a87d
CH		 1357
1358 abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
eb71f435 1359 BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
e7a2a87d
CH		 1360 if (IS_ERR(abort_req)) {
1361 atomic_inc(&dev->ctrl.abort_limit);
1362 return BLK_EH_RESET_TIMER;
1363 }
1364
1365 abort_req->timeout = ADMIN_TIMEOUT;
1366 abort_req->end_io_data = NULL;
1367 blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio);
c30341dc 1368
31c7c7d2
CH		 1369 /*
1370 * The aborted req will be completed on receiving the abort req.
1371 * We enable the timer again. If hit twice, it'll cause a device reset,
1372 * as the device then is in a faulty state.
1373 */
1374 return BLK_EH_RESET_TIMER;
c30341dc
KB		 1375}
1376
a4aea562
MB		 1377static void nvme_free_queue(struct nvme_queue *nvmeq)
1378{
9e866774
MW		 1379 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1380 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
63223078
CH		 1381 if (!nvmeq->sq_cmds)
1382 return;
0f238ff5 1383
63223078
CH		 1384 if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) {
1385 pci_free_p2pmem(to_pci_dev(nvmeq->q_dmadev),
1386 nvmeq->sq_cmds, SQ_SIZE(nvmeq->q_depth));
1387 } else {
1388 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
1389 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
0f238ff5 1390 }
9e866774
MW		 1391}
1392
a1a5ef99 1393static void nvme_free_queues(struct nvme_dev *dev, int lowest)
22404274
KB		 1394{
1395 int i;
1396
d858e5f0 1397 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
d858e5f0 1398 dev->ctrl.queue_count--;
147b27e4 1399 nvme_free_queue(&dev->queues[i]);
121c7ad4 1400 }
22404274
KB		 1401}
1402
4d115420
KB		 1403/**
1404 * nvme_suspend_queue - put queue into suspended state
40581d1a 1405 * @nvmeq: queue to suspend
4d115420
KB		 1406 */
1407static int nvme_suspend_queue(struct nvme_queue *nvmeq)
b60503ba 1408{
4e224106 1409 if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags))
2b25d981 1410 return 1;
a09115b2 1411
4e224106 1412 /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */
d1f06f4a 1413 mb();
a09115b2 1414
4e224106 1415 nvmeq->dev->online_queues--;
1c63dc66 1416 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
c81545f9 1417 blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q);
4e224106
CH		 1418 if (nvmeq->cq_vector == -1)
1419 return 0;
1420 pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq);
1421 nvmeq->cq_vector = -1;
4d115420
KB		 1422 return 0;
1423}
b60503ba 1424
a5cdb68c 1425static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
4d115420 1426{
147b27e4 1427 struct nvme_queue *nvmeq = &dev->queues[0];
4d115420 1428
a5cdb68c
KB		 1429 if (shutdown)
1430 nvme_shutdown_ctrl(&dev->ctrl);
1431 else
20d0dfe6 1432 nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap);
07836e65 1433
0b2a8a9f 1434 nvme_poll_irqdisable(nvmeq, -1);
b60503ba
MW		 1435}
1436
8ffaadf7
JD		 1437static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1438 int entry_size)
1439{
1440 int q_depth = dev->q_depth;
5fd4ce1b
CH		 1441 unsigned q_size_aligned = roundup(q_depth * entry_size,
1442 dev->ctrl.page_size);
8ffaadf7
JD		 1443
1444 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
c45f5c99 1445 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
5fd4ce1b 1446 mem_per_q = round_down(mem_per_q, dev->ctrl.page_size);
c45f5c99 1447 q_depth = div_u64(mem_per_q, entry_size);
8ffaadf7
JD		 1448
1449 /*
1450 * Ensure the reduced q_depth is above some threshold where it
1451 * would be better to map queues in system memory with the
1452 * original depth
1453 */
1454 if (q_depth < 64)
1455 return -ENOMEM;
1456 }
1457
1458 return q_depth;
1459}
1460
1461static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1462 int qid, int depth)
1463{
0f238ff5
LG		 1464 struct pci_dev *pdev = to_pci_dev(dev->dev);
1465
1466 if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
1467 nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(depth));
1468 nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev,
1469 nvmeq->sq_cmds);
63223078
CH		 1470 if (nvmeq->sq_dma_addr) {
1471 set_bit(NVMEQ_SQ_CMB, &nvmeq->flags);
1472 return 0;
1473 }
0f238ff5 1474 }
8ffaadf7 1475
63223078
CH		 1476 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
1477 &nvmeq->sq_dma_addr, GFP_KERNEL);
815c6704
KB		 1478 if (!nvmeq->sq_cmds)
1479 return -ENOMEM;
8ffaadf7
JD		 1480 return 0;
1481}
1482
a6ff7262 1483static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
b60503ba 1484{
147b27e4 1485 struct nvme_queue *nvmeq = &dev->queues[qid];
b60503ba 1486
62314e40
KB		 1487 if (dev->ctrl.queue_count > qid)
1488 return 0;
b60503ba 1489
e75ec752 1490 nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth),
4d51abf9 1491 &nvmeq->cq_dma_addr, GFP_KERNEL);
b60503ba
MW		 1492 if (!nvmeq->cqes)
1493 goto free_nvmeq;
b60503ba 1494
8ffaadf7 1495 if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth))
b60503ba
MW		 1496 goto free_cqdma;
1497
e75ec752 1498 nvmeq->q_dmadev = dev->dev;
091b6092 1499 nvmeq->dev = dev;
1ab0cd69 1500 spin_lock_init(&nvmeq->sq_lock);
3a7afd8e 1501 spin_lock_init(&nvmeq->cq_poll_lock);
b60503ba 1502 nvmeq->cq_head = 0;
82123460 1503 nvmeq->cq_phase = 1;
b80d5ccc 1504 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
b60503ba 1505 nvmeq->q_depth = depth;
c30341dc 1506 nvmeq->qid = qid;
758dd7fd 1507 nvmeq->cq_vector = -1;
d858e5f0 1508 dev->ctrl.queue_count++;
36a7e993 1509
147b27e4 1510 return 0;
b60503ba
MW		 1511
1512 free_cqdma:
e75ec752 1513 dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes,
b60503ba
MW		 1514 nvmeq->cq_dma_addr);
1515 free_nvmeq:
147b27e4 1516 return -ENOMEM;
b60503ba
MW		 1517}
1518
dca51e78 1519static int queue_request_irq(struct nvme_queue *nvmeq)
3001082c 1520{
0ff199cb
CH		 1521 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1522 int nr = nvmeq->dev->ctrl.instance;
1523
1524 if (use_threaded_interrupts) {
1525 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1526 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1527 } else {
1528 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1529 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1530 }
3001082c
MW		 1531}
1532
22404274 1533static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
b60503ba 1534{
22404274 1535 struct nvme_dev *dev = nvmeq->dev;
b60503ba 1536
22404274 1537 nvmeq->sq_tail = 0;
04f3eafd 1538 nvmeq->last_sq_tail = 0;
22404274
KB		 1539 nvmeq->cq_head = 0;
1540 nvmeq->cq_phase = 1;
b80d5ccc 1541 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
22404274 1542 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
f9f38e33 1543 nvme_dbbuf_init(dev, nvmeq, qid);
42f61420 1544 dev->online_queues++;
3a7afd8e 1545 wmb(); /* ensure the first interrupt sees the initialization */
22404274
KB		 1546}
1547
4b04cc6a 1548static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled)
22404274
KB		 1549{
1550 struct nvme_dev *dev = nvmeq->dev;
1551 int result;
a8e3e0bb 1552 s16 vector;
3f85d50b 1553
d1ed6aa1
CH		 1554 clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
1555
22b55601
KB		 1556 /*
1557 * A queue's vector matches the queue identifier unless the controller
1558 * has only one vector available.
1559 */
4b04cc6a
JA		 1560 if (!polled)
1561 vector = dev->num_vecs == 1 ? 0 : qid;
1562 else
1563 vector = -1;
1564
a8e3e0bb 1565 result = adapter_alloc_cq(dev, qid, nvmeq, vector);
ded45505
KB		 1566 if (result)
1567 return result;
b60503ba
MW		 1568
1569 result = adapter_alloc_sq(dev, qid, nvmeq);
1570 if (result < 0)
ded45505
KB		 1571 return result;
1572 else if (result)
b60503ba
MW		 1573 goto release_cq;
1574
a8e3e0bb 1575 nvmeq->cq_vector = vector;
161b8be2 1576 nvme_init_queue(nvmeq, qid);
4b04cc6a
JA		 1577
1578 if (vector != -1) {
1579 result = queue_request_irq(nvmeq);
1580 if (result < 0)
1581 goto release_sq;
1582 }
b60503ba 1583
4e224106 1584 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
22404274 1585 return result;
b60503ba 1586
a8e3e0bb
JW		 1587release_sq:
1588 nvmeq->cq_vector = -1;
f25a2dfc 1589 dev->online_queues--;
b60503ba 1590 adapter_delete_sq(dev, qid);
a8e3e0bb 1591release_cq:
b60503ba 1592 adapter_delete_cq(dev, qid);
22404274 1593 return result;
b60503ba
MW		 1594}
1595
f363b089 1596static const struct blk_mq_ops nvme_mq_admin_ops = {
d29ec824 1597 .queue_rq = nvme_queue_rq,
77f02a7a 1598 .complete = nvme_pci_complete_rq,
a4aea562 1599 .init_hctx = nvme_admin_init_hctx,
4af0e21c 1600 .exit_hctx = nvme_admin_exit_hctx,
0350815a 1601 .init_request = nvme_init_request,
a4aea562
MB		 1602 .timeout = nvme_timeout,
1603};
1604
dabcefab
JA		 1605#define NVME_SHARED_MQ_OPS \
1606 .queue_rq = nvme_queue_rq, \
04f3eafd 1607 .commit_rqs = nvme_commit_rqs, \
dabcefab
JA		 1608 .complete = nvme_pci_complete_rq, \
1609 .init_hctx = nvme_init_hctx, \
1610 .init_request = nvme_init_request, \
1611 .map_queues = nvme_pci_map_queues, \
1612 .timeout = nvme_timeout \
1613
f363b089 1614static const struct blk_mq_ops nvme_mq_ops = {
dabcefab 1615 NVME_SHARED_MQ_OPS,
a4aea562
MB		 1616};
1617
c6d962ae 1618static const struct blk_mq_ops nvme_mq_poll_ops = {
dabcefab 1619 NVME_SHARED_MQ_OPS,
c6d962ae 1620 .poll = nvme_poll,
dabcefab
JA		 1621};
1622
ea191d2f
KB		 1623static void nvme_dev_remove_admin(struct nvme_dev *dev)
1624{
1c63dc66 1625 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
69d9a99c
KB		 1626 /*
1627 * If the controller was reset during removal, it's possible
1628 * user requests may be waiting on a stopped queue. Start the
1629 * queue to flush these to completion.
1630 */
c81545f9 1631 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1c63dc66 1632 blk_cleanup_queue(dev->ctrl.admin_q);
ea191d2f
KB		 1633 blk_mq_free_tag_set(&dev->admin_tagset);
1634 }
1635}
1636
a4aea562
MB		 1637static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1638{
1c63dc66 1639 if (!dev->ctrl.admin_q) {
a4aea562
MB		 1640 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1641 dev->admin_tagset.nr_hw_queues = 1;
e3e9d50c 1642
38dabe21 1643 dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH;
a4aea562 1644 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
e75ec752 1645 dev->admin_tagset.numa_node = dev_to_node(dev->dev);
a7a7cbe3 1646 dev->admin_tagset.cmd_size = nvme_pci_cmd_size(dev, false);
d3484991 1647 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED;
a4aea562
MB		 1648 dev->admin_tagset.driver_data = dev;
1649
1650 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1651 return -ENOMEM;
34b6c231 1652 dev->ctrl.admin_tagset = &dev->admin_tagset;
a4aea562 1653
1c63dc66
CH		 1654 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1655 if (IS_ERR(dev->ctrl.admin_q)) {
a4aea562
MB		 1656 blk_mq_free_tag_set(&dev->admin_tagset);
1657 return -ENOMEM;
1658 }
1c63dc66 1659 if (!blk_get_queue(dev->ctrl.admin_q)) {
ea191d2f 1660 nvme_dev_remove_admin(dev);
1c63dc66 1661 dev->ctrl.admin_q = NULL;
ea191d2f
KB		 1662 return -ENODEV;
1663 }
0fb59cbc 1664 } else
c81545f9 1665 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
a4aea562
MB		 1666
1667 return 0;
1668}
1669
97f6ef64
XY		 1670static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1671{
1672 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1673}
1674
1675static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1676{
1677 struct pci_dev *pdev = to_pci_dev(dev->dev);
1678
1679 if (size <= dev->bar_mapped_size)
1680 return 0;
1681 if (size > pci_resource_len(pdev, 0))
1682 return -ENOMEM;
1683 if (dev->bar)
1684 iounmap(dev->bar);
1685 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1686 if (!dev->bar) {
1687 dev->bar_mapped_size = 0;
1688 return -ENOMEM;
1689 }
1690 dev->bar_mapped_size = size;
1691 dev->dbs = dev->bar + NVME_REG_DBS;
1692
1693 return 0;
1694}
1695
01ad0990 1696static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
b60503ba 1697{
ba47e386 1698 int result;
b60503ba
MW		 1699 u32 aqa;
1700 struct nvme_queue *nvmeq;
1701
97f6ef64
XY		 1702 result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1703 if (result < 0)
1704 return result;
1705
8ef2074d 1706 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
20d0dfe6 1707 NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
dfbac8c7 1708
7a67cbea
CH		 1709 if (dev->subsystem &&
1710 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1711 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
dfbac8c7 1712
20d0dfe6 1713 result = nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap);
ba47e386
MW		 1714 if (result < 0)
1715 return result;
b60503ba 1716
a6ff7262 1717 result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
147b27e4
SG		 1718 if (result)
1719 return result;
b60503ba 1720
147b27e4 1721 nvmeq = &dev->queues[0];
b60503ba
MW		 1722 aqa = nvmeq->q_depth - 1;
1723 aqa |= aqa << 16;
1724
7a67cbea
CH		 1725 writel(aqa, dev->bar + NVME_REG_AQA);
1726 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1727 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
b60503ba 1728
20d0dfe6 1729 result = nvme_enable_ctrl(&dev->ctrl, dev->ctrl.cap);
025c557a 1730 if (result)
d4875622 1731 return result;
a4aea562 1732
2b25d981 1733 nvmeq->cq_vector = 0;
161b8be2 1734 nvme_init_queue(nvmeq, 0);
dca51e78 1735 result = queue_request_irq(nvmeq);
758dd7fd
JD		 1736 if (result) {
1737 nvmeq->cq_vector = -1;
d4875622 1738 return result;
758dd7fd 1739 }
025c557a 1740
4e224106 1741 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
b60503ba
MW		 1742 return result;
1743}
1744
749941f2 1745static int nvme_create_io_queues(struct nvme_dev *dev)
42f61420 1746{
4b04cc6a 1747 unsigned i, max, rw_queues;
749941f2 1748 int ret = 0;
42f61420 1749
d858e5f0 1750 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
a6ff7262 1751 if (nvme_alloc_queue(dev, i, dev->q_depth)) {
749941f2 1752 ret = -ENOMEM;
42f61420 1753 break;
749941f2
CH		 1754 }
1755 }
42f61420 1756
d858e5f0 1757 max = min(dev->max_qid, dev->ctrl.queue_count - 1);
e20ba6e1
CH		 1758 if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) {
1759 rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] +
1760 dev->io_queues[HCTX_TYPE_READ];
4b04cc6a
JA		 1761 } else {
1762 rw_queues = max;
1763 }
1764
949928c1 1765 for (i = dev->online_queues; i <= max; i++) {
4b04cc6a
JA		 1766 bool polled = i > rw_queues;
1767
1768 ret = nvme_create_queue(&dev->queues[i], i, polled);
d4875622 1769 if (ret)
42f61420 1770 break;
27e8166c 1771 }
749941f2
CH		 1772
1773 /*
1774 * Ignore failing Create SQ/CQ commands, we can continue with less
8adb8c14
MI		 1775 * than the desired amount of queues, and even a controller without
1776 * I/O queues can still be used to issue admin commands. This might
749941f2
CH		 1777 * be useful to upgrade a buggy firmware for example.
1778 */
1779 return ret >= 0 ? 0 : ret;
b60503ba
MW		 1780}
1781
202021c1
SB		 1782static ssize_t nvme_cmb_show(struct device *dev,
1783 struct device_attribute *attr,
1784 char *buf)
1785{
1786 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
1787
c965809c 1788 return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n",
202021c1
SB		 1789 ndev->cmbloc, ndev->cmbsz);
1790}
1791static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL);
1792
88de4598 1793static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
8ffaadf7 1794{
88de4598
CH		 1795 u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
1796
1797 return 1ULL << (12 + 4 * szu);
1798}
1799
1800static u32 nvme_cmb_size(struct nvme_dev *dev)
1801{
1802 return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
1803}
1804
f65efd6d 1805static void nvme_map_cmb(struct nvme_dev *dev)
8ffaadf7 1806{
88de4598 1807 u64 size, offset;
8ffaadf7
JD		 1808 resource_size_t bar_size;
1809 struct pci_dev *pdev = to_pci_dev(dev->dev);
8969f1f8 1810 int bar;
8ffaadf7 1811
9fe5c59f
KB		 1812 if (dev->cmb_size)
1813 return;
1814
7a67cbea 1815 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
f65efd6d
CH		 1816 if (!dev->cmbsz)
1817 return;
202021c1 1818 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
8ffaadf7 1819
88de4598
CH		 1820 size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
1821 offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
8969f1f8
CH		 1822 bar = NVME_CMB_BIR(dev->cmbloc);
1823 bar_size = pci_resource_len(pdev, bar);
8ffaadf7
JD		 1824
1825 if (offset > bar_size)
f65efd6d 1826 return;
8ffaadf7
JD		 1827
1828 /*
1829 * Controllers may support a CMB size larger than their BAR,
1830 * for example, due to being behind a bridge. Reduce the CMB to
1831 * the reported size of the BAR
1832 */
1833 if (size > bar_size - offset)
1834 size = bar_size - offset;
1835
0f238ff5
LG		 1836 if (pci_p2pdma_add_resource(pdev, bar, size, offset)) {
1837 dev_warn(dev->ctrl.device,
1838 "failed to register the CMB\n");
f65efd6d 1839 return;
0f238ff5
LG		 1840 }
1841
8ffaadf7 1842 dev->cmb_size = size;
0f238ff5
LG		 1843 dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS);
1844
1845 if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) ==
1846 (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS))
1847 pci_p2pmem_publish(pdev, true);
f65efd6d
CH		 1848
1849 if (sysfs_add_file_to_group(&dev->ctrl.device->kobj,
1850 &dev_attr_cmb.attr, NULL))
1851 dev_warn(dev->ctrl.device,
1852 "failed to add sysfs attribute for CMB\n");
8ffaadf7
JD		 1853}
1854
1855static inline void nvme_release_cmb(struct nvme_dev *dev)
1856{
0f238ff5 1857 if (dev->cmb_size) {
1c78f773
MG		 1858 sysfs_remove_file_from_group(&dev->ctrl.device->kobj,
1859 &dev_attr_cmb.attr, NULL);
0f238ff5 1860 dev->cmb_size = 0;
8ffaadf7
JD		 1861 }
1862}
1863
87ad72a5
CH		 1864static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1865{
4033f35d 1866 u64 dma_addr = dev->host_mem_descs_dma;
87ad72a5 1867 struct nvme_command c;
87ad72a5
CH		 1868 int ret;
1869
87ad72a5
CH		 1870 memset(&c, 0, sizeof(c));
1871 c.features.opcode = nvme_admin_set_features;
1872 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1873 c.features.dword11 = cpu_to_le32(bits);
1874 c.features.dword12 = cpu_to_le32(dev->host_mem_size >>
1875 ilog2(dev->ctrl.page_size));
1876 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr));
1877 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr));
1878 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs);
1879
1880 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1881 if (ret) {
1882 dev_warn(dev->ctrl.device,
1883 "failed to set host mem (err %d, flags %#x).\n",
1884 ret, bits);
1885 }
87ad72a5
CH		 1886 return ret;
1887}
1888
1889static void nvme_free_host_mem(struct nvme_dev *dev)
1890{
1891 int i;
1892
1893 for (i = 0; i < dev->nr_host_mem_descs; i++) {
1894 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
1895 size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size;
1896
1897 dma_free_coherent(dev->dev, size, dev->host_mem_desc_bufs[i],
1898 le64_to_cpu(desc->addr));
1899 }
1900
1901 kfree(dev->host_mem_desc_bufs);
1902 dev->host_mem_desc_bufs = NULL;
4033f35d
CH		 1903 dma_free_coherent(dev->dev,
1904 dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
1905 dev->host_mem_descs, dev->host_mem_descs_dma);
87ad72a5 1906 dev->host_mem_descs = NULL;
7e5dd57e 1907 dev->nr_host_mem_descs = 0;
87ad72a5
CH		 1908}
1909
92dc6895
CH		 1910static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
1911 u32 chunk_size)
9d713c2b 1912{
87ad72a5 1913 struct nvme_host_mem_buf_desc *descs;
92dc6895 1914 u32 max_entries, len;
4033f35d 1915 dma_addr_t descs_dma;
2ee0e4ed 1916 int i = 0;
87ad72a5 1917 void **bufs;
6fbcde66 1918 u64 size, tmp;
87ad72a5 1919
87ad72a5
CH		 1920 tmp = (preferred + chunk_size - 1);
1921 do_div(tmp, chunk_size);
1922 max_entries = tmp;
044a9df1
CH		 1923
1924 if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
1925 max_entries = dev->ctrl.hmmaxd;
1926
4033f35d
CH		 1927 descs = dma_zalloc_coherent(dev->dev, max_entries * sizeof(*descs),
1928 &descs_dma, GFP_KERNEL);
87ad72a5
CH		 1929 if (!descs)
1930 goto out;
1931
1932 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
1933 if (!bufs)
1934 goto out_free_descs;
1935
244a8fe4 1936 for (size = 0; size < preferred && i < max_entries; size += len) {
87ad72a5
CH		 1937 dma_addr_t dma_addr;
1938
50cdb7c6 1939 len = min_t(u64, chunk_size, preferred - size);
87ad72a5
CH		 1940 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
1941 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1942 if (!bufs[i])
1943 break;
1944
1945 descs[i].addr = cpu_to_le64(dma_addr);
1946 descs[i].size = cpu_to_le32(len / dev->ctrl.page_size);
1947 i++;
1948 }
1949
92dc6895 1950 if (!size)
87ad72a5 1951 goto out_free_bufs;
87ad72a5 1952
87ad72a5
CH		 1953 dev->nr_host_mem_descs = i;
1954 dev->host_mem_size = size;
1955 dev->host_mem_descs = descs;
4033f35d 1956 dev->host_mem_descs_dma = descs_dma;
87ad72a5
CH		 1957 dev->host_mem_desc_bufs = bufs;
1958 return 0;
1959
1960out_free_bufs:
1961 while (--i >= 0) {
1962 size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size;
1963
1964 dma_free_coherent(dev->dev, size, bufs[i],
1965 le64_to_cpu(descs[i].addr));
1966 }
1967
1968 kfree(bufs);
1969out_free_descs:
4033f35d
CH		 1970 dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
1971 descs_dma);
87ad72a5 1972out:
87ad72a5
CH		 1973 dev->host_mem_descs = NULL;
1974 return -ENOMEM;
1975}
1976
92dc6895
CH		 1977static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
1978{
1979 u32 chunk_size;
1980
1981 /* start big and work our way down */
30f92d62 1982 for (chunk_size = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
044a9df1 1983 chunk_size >= max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
92dc6895
CH		 1984 chunk_size /= 2) {
1985 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
1986 if (!min || dev->host_mem_size >= min)
1987 return 0;
1988 nvme_free_host_mem(dev);
1989 }
1990 }
1991
1992 return -ENOMEM;
1993}
1994
9620cfba 1995static int nvme_setup_host_mem(struct nvme_dev *dev)
87ad72a5
CH		 1996{
1997 u64 max = (u64)max_host_mem_size_mb * SZ_1M;
1998 u64 preferred = (u64)dev->ctrl.hmpre * 4096;
1999 u64 min = (u64)dev->ctrl.hmmin * 4096;
2000 u32 enable_bits = NVME_HOST_MEM_ENABLE;
6fbcde66 2001 int ret;
87ad72a5
CH		 2002
2003 preferred = min(preferred, max);
2004 if (min > max) {
2005 dev_warn(dev->ctrl.device,
2006 "min host memory (%lld MiB) above limit (%d MiB).\n",
2007 min >> ilog2(SZ_1M), max_host_mem_size_mb);
2008 nvme_free_host_mem(dev);
9620cfba 2009 return 0;
87ad72a5
CH		 2010 }
2011
2012 /*
2013 * If we already have a buffer allocated check if we can reuse it.
2014 */
2015 if (dev->host_mem_descs) {
2016 if (dev->host_mem_size >= min)
2017 enable_bits |= NVME_HOST_MEM_RETURN;
2018 else
2019 nvme_free_host_mem(dev);
2020 }
2021
2022 if (!dev->host_mem_descs) {
92dc6895
CH		 2023 if (nvme_alloc_host_mem(dev, min, preferred)) {
2024 dev_warn(dev->ctrl.device,
2025 "failed to allocate host memory buffer.\n");
9620cfba 2026 return 0; /* controller must work without HMB */
92dc6895
CH		 2027 }
2028
2029 dev_info(dev->ctrl.device,
2030 "allocated %lld MiB host memory buffer.\n",
2031 dev->host_mem_size >> ilog2(SZ_1M));
87ad72a5
CH		 2032 }
2033
9620cfba
CH		 2034 ret = nvme_set_host_mem(dev, enable_bits);
2035 if (ret)
87ad72a5 2036 nvme_free_host_mem(dev);
9620cfba 2037 return ret;
9d713c2b
KB		 2038}
2039
3b6592f7
JA		 2040static void nvme_calc_io_queues(struct nvme_dev *dev, unsigned int nr_io_queues)
2041{
2042 unsigned int this_w_queues = write_queues;
4b04cc6a 2043 unsigned int this_p_queues = poll_queues;
3b6592f7
JA		 2044
2045 /*
2046 * Setup read/write queue split
2047 */
2048 if (nr_io_queues == 1) {
e20ba6e1
CH		 2049 dev->io_queues[HCTX_TYPE_DEFAULT] = 1;
2050 dev->io_queues[HCTX_TYPE_READ] = 0;
2051 dev->io_queues[HCTX_TYPE_POLL] = 0;
3b6592f7
JA		 2052 return;
2053 }
2054
4b04cc6a
JA		 2055 /*
2056 * Configure number of poll queues, if set
2057 */
2058 if (this_p_queues) {
2059 /*
2060 * We need at least one queue left. With just one queue, we'll
2061 * have a single shared read/write set.
2062 */
2063 if (this_p_queues >= nr_io_queues) {
2064 this_w_queues = 0;
2065 this_p_queues = nr_io_queues - 1;
2066 }
2067
e20ba6e1 2068 dev->io_queues[HCTX_TYPE_POLL] = this_p_queues;
4b04cc6a
JA		 2069 nr_io_queues -= this_p_queues;
2070 } else
e20ba6e1 2071 dev->io_queues[HCTX_TYPE_POLL] = 0;
4b04cc6a 2072
3b6592f7
JA		 2073 /*
2074 * If 'write_queues' is set, ensure it leaves room for at least
2075 * one read queue
2076 */
2077 if (this_w_queues >= nr_io_queues)
2078 this_w_queues = nr_io_queues - 1;
2079
2080 /*
2081 * If 'write_queues' is set to zero, reads and writes will share
2082 * a queue set.
2083 */
2084 if (!this_w_queues) {
e20ba6e1
CH		 2085 dev->io_queues[HCTX_TYPE_DEFAULT] = nr_io_queues;
2086 dev->io_queues[HCTX_TYPE_READ] = 0;
3b6592f7 2087 } else {
e20ba6e1
CH		 2088 dev->io_queues[HCTX_TYPE_DEFAULT] = this_w_queues;
2089 dev->io_queues[HCTX_TYPE_READ] = nr_io_queues - this_w_queues;
3b6592f7
JA		 2090 }
2091}
2092
2093static int nvme_setup_irqs(struct nvme_dev *dev, int nr_io_queues)
2094{
2095 struct pci_dev *pdev = to_pci_dev(dev->dev);
2096 int irq_sets[2];
2097 struct irq_affinity affd = {
2098 .pre_vectors = 1,
2099 .nr_sets = ARRAY_SIZE(irq_sets),
2100 .sets = irq_sets,
2101 };
30e06628 2102 int result = 0;
3b6592f7
JA		 2103
2104 /*
2105 * For irq sets, we have to ask for minvec == maxvec. This passes
2106 * any reduction back to us, so we can adjust our queue counts and
2107 * IRQ vector needs.
2108 */
2109 do {
2110 nvme_calc_io_queues(dev, nr_io_queues);
e20ba6e1
CH		 2111 irq_sets[0] = dev->io_queues[HCTX_TYPE_DEFAULT];
2112 irq_sets[1] = dev->io_queues[HCTX_TYPE_READ];
3b6592f7
JA		 2113 if (!irq_sets[1])
2114 affd.nr_sets = 1;
2115
2116 /*
db29eb05
JA		 2117 * If we got a failure and we're down to asking for just
2118 * 1 + 1 queues, just ask for a single vector. We'll share
2119 * that between the single IO queue and the admin queue.
3b6592f7 2120 */
db29eb05 2121 if (!(result < 0 && nr_io_queues == 1))
30e06628 2122 nr_io_queues = irq_sets[0] + irq_sets[1] + 1;
3b6592f7
JA		 2123
2124 result = pci_alloc_irq_vectors_affinity(pdev, nr_io_queues,
2125 nr_io_queues,
2126 PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd);
2127
2128 /*
db29eb05
JA		 2129 * Need to reduce our vec counts. If we get ENOSPC, the
2130 * platform should support mulitple vecs, we just need
2131 * to decrease our ask. If we get EINVAL, the platform
2132 * likely does not. Back down to ask for just one vector.
3b6592f7
JA		 2133 */
2134 if (result == -ENOSPC) {
2135 nr_io_queues--;
2136 if (!nr_io_queues)
2137 return result;
2138 continue;
db29eb05
JA		 2139 } else if (result == -EINVAL) {
2140 nr_io_queues = 1;
2141 continue;
3b6592f7
JA		 2142 } else if (result <= 0)
2143 return -EIO;
2144 break;
2145 } while (1);
2146
2147 return result;
2148}
2149
8d85fce7 2150static int nvme_setup_io_queues(struct nvme_dev *dev)
b60503ba 2151{
147b27e4 2152 struct nvme_queue *adminq = &dev->queues[0];
e75ec752 2153 struct pci_dev *pdev = to_pci_dev(dev->dev);
97f6ef64
XY		 2154 int result, nr_io_queues;
2155 unsigned long size;
b60503ba 2156
3b6592f7 2157 nr_io_queues = max_io_queues();
9a0be7ab
CH		 2158 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
2159 if (result < 0)
1b23484b 2160 return result;
9a0be7ab 2161
f5fa90dc 2162 if (nr_io_queues == 0)
a5229050 2163 return 0;
4e224106
CH		 2164
2165 clear_bit(NVMEQ_ENABLED, &adminq->flags);
b60503ba 2166
0f238ff5 2167 if (dev->cmb_use_sqes) {
8ffaadf7
JD		 2168 result = nvme_cmb_qdepth(dev, nr_io_queues,
2169 sizeof(struct nvme_command));
2170 if (result > 0)
2171 dev->q_depth = result;
2172 else
0f238ff5 2173 dev->cmb_use_sqes = false;
8ffaadf7
JD		 2174 }
2175
97f6ef64
XY		 2176 do {
2177 size = db_bar_size(dev, nr_io_queues);
2178 result = nvme_remap_bar(dev, size);
2179 if (!result)
2180 break;
2181 if (!--nr_io_queues)
2182 return -ENOMEM;
2183 } while (1);
2184 adminq->q_db = dev->dbs;
f1938f6e 2185
9d713c2b 2186 /* Deregister the admin queue's interrupt */
0ff199cb 2187 pci_free_irq(pdev, 0, adminq);
9d713c2b 2188
e32efbfc
JA		 2189 /*
2190 * If we enable msix early due to not intx, disable it again before
2191 * setting up the full range we need.
2192 */
dca51e78 2193 pci_free_irq_vectors(pdev);
3b6592f7
JA		 2194
2195 result = nvme_setup_irqs(dev, nr_io_queues);
22b55601 2196 if (result <= 0)
dca51e78 2197 return -EIO;
3b6592f7 2198
22b55601 2199 dev->num_vecs = result;
4b04cc6a 2200 result = max(result - 1, 1);
e20ba6e1 2201 dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL];
fa08a396 2202
e20ba6e1
CH		 2203 dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n",
2204 dev->io_queues[HCTX_TYPE_DEFAULT],
2205 dev->io_queues[HCTX_TYPE_READ],
2206 dev->io_queues[HCTX_TYPE_POLL]);
3b6592f7 2207
063a8096
MW		 2208 /*
2209 * Should investigate if there's a performance win from allocating
2210 * more queues than interrupt vectors; it might allow the submission
2211 * path to scale better, even if the receive path is limited by the
2212 * number of interrupts.
2213 */
063a8096 2214
dca51e78 2215 result = queue_request_irq(adminq);
758dd7fd
JD		 2216 if (result) {
2217 adminq->cq_vector = -1;
d4875622 2218 return result;
758dd7fd 2219 }
4e224106 2220 set_bit(NVMEQ_ENABLED, &adminq->flags);
749941f2 2221 return nvme_create_io_queues(dev);
b60503ba
MW		 2222}
2223
2a842aca 2224static void nvme_del_queue_end(struct request *req, blk_status_t error)
a5768aa8 2225{
db3cbfff 2226 struct nvme_queue *nvmeq = req->end_io_data;
b5875222 2227
db3cbfff 2228 blk_mq_free_request(req);
d1ed6aa1 2229 complete(&nvmeq->delete_done);
a5768aa8
KB		 2230}
2231
2a842aca 2232static void nvme_del_cq_end(struct request *req, blk_status_t error)
a5768aa8 2233{
db3cbfff 2234 struct nvme_queue *nvmeq = req->end_io_data;
a5768aa8 2235
d1ed6aa1
CH		 2236 if (error)
2237 set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
db3cbfff
KB		 2238
2239 nvme_del_queue_end(req, error);
a5768aa8
KB		 2240}
2241
db3cbfff 2242static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
bda4e0fb 2243{
db3cbfff
KB		 2244 struct request_queue *q = nvmeq->dev->ctrl.admin_q;
2245 struct request *req;
2246 struct nvme_command cmd;
bda4e0fb 2247
db3cbfff
KB		 2248 memset(&cmd, 0, sizeof(cmd));
2249 cmd.delete_queue.opcode = opcode;
2250 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
bda4e0fb 2251
eb71f435 2252 req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
db3cbfff
KB		 2253 if (IS_ERR(req))
2254 return PTR_ERR(req);
bda4e0fb 2255
db3cbfff
KB		 2256 req->timeout = ADMIN_TIMEOUT;
2257 req->end_io_data = nvmeq;
2258
d1ed6aa1 2259 init_completion(&nvmeq->delete_done);
db3cbfff
KB		 2260 blk_execute_rq_nowait(q, NULL, req, false,
2261 opcode == nvme_admin_delete_cq ?
2262 nvme_del_cq_end : nvme_del_queue_end);
2263 return 0;
bda4e0fb
KB		 2264}
2265
5271edd4 2266static bool nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode)
a5768aa8 2267{
5271edd4 2268 int nr_queues = dev->online_queues - 1, sent = 0;
db3cbfff 2269 unsigned long timeout;
a5768aa8 2270
db3cbfff 2271 retry:
5271edd4
CH		 2272 timeout = ADMIN_TIMEOUT;
2273 while (nr_queues > 0) {
2274 if (nvme_delete_queue(&dev->queues[nr_queues], opcode))
2275 break;
2276 nr_queues--;
2277 sent++;
db3cbfff 2278 }
d1ed6aa1
CH		 2279 while (sent) {
2280 struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent];
2281
2282 timeout = wait_for_completion_io_timeout(&nvmeq->delete_done,
5271edd4
CH		 2283 timeout);
2284 if (timeout == 0)
2285 return false;
d1ed6aa1
CH		 2286
2287 /* handle any remaining CQEs */
2288 if (opcode == nvme_admin_delete_cq &&
2289 !test_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags))
2290 nvme_poll_irqdisable(nvmeq, -1);
2291
2292 sent--;
5271edd4
CH		 2293 if (nr_queues)
2294 goto retry;
2295 }
2296 return true;
a5768aa8
KB		 2297}
2298
422ef0c7 2299/*
2b1b7e78 2300 * return error value only when tagset allocation failed
422ef0c7 2301 */
8d85fce7 2302static int nvme_dev_add(struct nvme_dev *dev)
b60503ba 2303{
2b1b7e78
JW		 2304 int ret;
2305
5bae7f73 2306 if (!dev->ctrl.tagset) {
c6d962ae
CH		 2307 if (dev->io_queues[HCTX_TYPE_POLL])
2308 dev->tagset.ops = &nvme_mq_poll_ops;
dabcefab 2309 else
c6d962ae 2310 dev->tagset.ops = &nvme_mq_ops;
dabcefab 2311
ffe7704d 2312 dev->tagset.nr_hw_queues = dev->online_queues - 1;
e20ba6e1 2313 dev->tagset.nr_maps = HCTX_MAX_TYPES;
ffe7704d
KB		 2314 dev->tagset.timeout = NVME_IO_TIMEOUT;
2315 dev->tagset.numa_node = dev_to_node(dev->dev);
2316 dev->tagset.queue_depth =
a4aea562 2317 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
a7a7cbe3
CK		 2318 dev->tagset.cmd_size = nvme_pci_cmd_size(dev, false);
2319 if ((dev->ctrl.sgls & ((1 << 0) | (1 << 1))) && sgl_threshold) {
2320 dev->tagset.cmd_size = max(dev->tagset.cmd_size,
2321 nvme_pci_cmd_size(dev, true));
2322 }
ffe7704d
KB		 2323 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2324 dev->tagset.driver_data = dev;
b60503ba 2325
2b1b7e78
JW		 2326 ret = blk_mq_alloc_tag_set(&dev->tagset);
2327 if (ret) {
2328 dev_warn(dev->ctrl.device,
2329 "IO queues tagset allocation failed %d\n", ret);
2330 return ret;
2331 }
5bae7f73 2332 dev->ctrl.tagset = &dev->tagset;
f9f38e33
HK		 2333
2334 nvme_dbbuf_set(dev);
949928c1
KB		 2335 } else {
2336 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2337
2338 /* Free previously allocated queues that are no longer usable */
2339 nvme_free_queues(dev, dev->online_queues);
ffe7704d 2340 }
949928c1 2341
e1e5e564 2342 return 0;
b60503ba
MW		 2343}
2344
b00a726a 2345static int nvme_pci_enable(struct nvme_dev *dev)
0877cb0d 2346{
b00a726a 2347 int result = -ENOMEM;
e75ec752 2348 struct pci_dev *pdev = to_pci_dev(dev->dev);
0877cb0d
KB		 2349
2350 if (pci_enable_device_mem(pdev))
2351 return result;
2352
0877cb0d 2353 pci_set_master(pdev);
0877cb0d 2354
e75ec752
CH		 2355 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) &&
2356 dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32)))
052d0efa 2357 goto disable;
0877cb0d 2358
7a67cbea 2359 if (readl(dev->bar + NVME_REG_CSTS) == -1) {
0e53d180 2360 result = -ENODEV;
b00a726a 2361 goto disable;
0e53d180 2362 }
e32efbfc
JA		 2363
2364 /*
a5229050
KB		 2365 * Some devices and/or platforms don't advertise or work with INTx
2366 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2367 * adjust this later.
e32efbfc 2368 */
dca51e78
CH		 2369 result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
2370 if (result < 0)
2371 return result;
e32efbfc 2372
20d0dfe6 2373 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
7a67cbea 2374
20d0dfe6 2375 dev->q_depth = min_t(int, NVME_CAP_MQES(dev->ctrl.cap) + 1,
b27c1e68 2376 io_queue_depth);
20d0dfe6 2377 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
7a67cbea 2378 dev->dbs = dev->bar + 4096;
1f390c1f
SG		 2379
2380 /*
2381 * Temporary fix for the Apple controller found in the MacBook8,1 and
2382 * some MacBook7,1 to avoid controller resets and data loss.
2383 */
2384 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
2385 dev->q_depth = 2;
9bdcfb10
CH		 2386 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
2387 "set queue depth=%u to work around controller resets\n",
1f390c1f 2388 dev->q_depth);
d554b5e1
MP		 2389 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2390 (pdev->device == 0xa821 || pdev->device == 0xa822) &&
20d0dfe6 2391 NVME_CAP_MQES(dev->ctrl.cap) == 0) {
d554b5e1
MP		 2392 dev->q_depth = 64;
2393 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2394 "set queue depth=%u\n", dev->q_depth);
1f390c1f
SG		 2395 }
2396
f65efd6d 2397 nvme_map_cmb(dev);
202021c1 2398
a0a3408e
KB		 2399 pci_enable_pcie_error_reporting(pdev);
2400 pci_save_state(pdev);
0877cb0d
KB		 2401 return 0;
2402
2403 disable:
0877cb0d
KB		 2404 pci_disable_device(pdev);
2405 return result;
2406}
2407
2408static void nvme_dev_unmap(struct nvme_dev *dev)
b00a726a
KB		 2409{
2410 if (dev->bar)
2411 iounmap(dev->bar);
a1f447b3 2412 pci_release_mem_regions(to_pci_dev(dev->dev));
b00a726a
KB		 2413}
2414
2415static void nvme_pci_disable(struct nvme_dev *dev)
0877cb0d 2416{
e75ec752
CH		 2417 struct pci_dev *pdev = to_pci_dev(dev->dev);
2418
dca51e78 2419 pci_free_irq_vectors(pdev);
0877cb0d 2420
a0a3408e
KB		 2421 if (pci_is_enabled(pdev)) {
2422 pci_disable_pcie_error_reporting(pdev);
e75ec752 2423 pci_disable_device(pdev);
4d115420 2424 }
4d115420
KB		 2425}
2426
a5cdb68c 2427static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
b60503ba 2428{
ee9aebb2 2429 int i;
302ad8cc
KB		 2430 bool dead = true;
2431 struct pci_dev *pdev = to_pci_dev(dev->dev);
22404274 2432
77bf25ea 2433 mutex_lock(&dev->shutdown_lock);
302ad8cc
KB		 2434 if (pci_is_enabled(pdev)) {
2435 u32 csts = readl(dev->bar + NVME_REG_CSTS);
2436
ebef7368
KB		 2437 if (dev->ctrl.state == NVME_CTRL_LIVE ||
2438 dev->ctrl.state == NVME_CTRL_RESETTING)
302ad8cc
KB		 2439 nvme_start_freeze(&dev->ctrl);
2440 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
2441 pdev->error_state != pci_channel_io_normal);
c9d3bf88 2442 }
c21377f8 2443
302ad8cc
KB		 2444 /*
2445 * Give the controller a chance to complete all entered requests if
2446 * doing a safe shutdown.
2447 */
87ad72a5
CH		 2448 if (!dead) {
2449 if (shutdown)
2450 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
9a915a5b
JW		 2451 }
2452
2453 nvme_stop_queues(&dev->ctrl);
87ad72a5 2454
64ee0ac0 2455 if (!dead && dev->ctrl.queue_count > 0) {
5271edd4
CH		 2456 if (nvme_disable_io_queues(dev, nvme_admin_delete_sq))
2457 nvme_disable_io_queues(dev, nvme_admin_delete_cq);
a5cdb68c 2458 nvme_disable_admin_queue(dev, shutdown);
4d115420 2459 }
ee9aebb2
KB		 2460 for (i = dev->ctrl.queue_count - 1; i >= 0; i--)
2461 nvme_suspend_queue(&dev->queues[i]);
2462
b00a726a 2463 nvme_pci_disable(dev);
07836e65 2464
e1958e65
ML		 2465 blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
2466 blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
302ad8cc
KB		 2467
2468 /*
2469 * The driver will not be starting up queues again if shutting down so
2470 * must flush all entered requests to their failed completion to avoid
2471 * deadlocking blk-mq hot-cpu notifier.
2472 */
2473 if (shutdown)
2474 nvme_start_queues(&dev->ctrl);
77bf25ea 2475 mutex_unlock(&dev->shutdown_lock);
b60503ba
MW		 2476}
2477
091b6092
MW		 2478static int nvme_setup_prp_pools(struct nvme_dev *dev)
2479{
e75ec752 2480 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
091b6092
MW		 2481 PAGE_SIZE, PAGE_SIZE, 0);
2482 if (!dev->prp_page_pool)
2483 return -ENOMEM;
2484
99802a7a 2485 /* Optimisation for I/Os between 4k and 128k */
e75ec752 2486 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
99802a7a
MW		 2487 256, 256, 0);
2488 if (!dev->prp_small_pool) {
2489 dma_pool_destroy(dev->prp_page_pool);
2490 return -ENOMEM;
2491 }
091b6092
MW		 2492 return 0;
2493}
2494
2495static void nvme_release_prp_pools(struct nvme_dev *dev)
2496{
2497 dma_pool_destroy(dev->prp_page_pool);
99802a7a 2498 dma_pool_destroy(dev->prp_small_pool);
091b6092
MW		 2499}
2500
1673f1f0 2501static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
5e82e952 2502{
1673f1f0 2503 struct nvme_dev *dev = to_nvme_dev(ctrl);
9ac27090 2504
f9f38e33 2505 nvme_dbbuf_dma_free(dev);
e75ec752 2506 put_device(dev->dev);
4af0e21c
KB		 2507 if (dev->tagset.tags)
2508 blk_mq_free_tag_set(&dev->tagset);
1c63dc66
CH		 2509 if (dev->ctrl.admin_q)
2510 blk_put_queue(dev->ctrl.admin_q);
5e82e952 2511 kfree(dev->queues);
e286bcfc 2512 free_opal_dev(dev->ctrl.opal_dev);
943e942e 2513 mempool_destroy(dev->iod_mempool);
5e82e952
KB		 2514 kfree(dev);
2515}
2516
f58944e2
KB		 2517static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status)
2518{
237045fc 2519 dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status);
f58944e2 2520
d22524a4 2521 nvme_get_ctrl(&dev->ctrl);
69d9a99c 2522 nvme_dev_disable(dev, false);
9f9cafc1 2523 nvme_kill_queues(&dev->ctrl);
03e0f3a6 2524 if (!queue_work(nvme_wq, &dev->remove_work))
f58944e2
KB		 2525 nvme_put_ctrl(&dev->ctrl);
2526}
2527
fd634f41 2528static void nvme_reset_work(struct work_struct *work)
5e82e952 2529{
d86c4d8e
CH		 2530 struct nvme_dev *dev =
2531 container_of(work, struct nvme_dev, ctrl.reset_work);
a98e58e5 2532 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
f58944e2 2533 int result = -ENODEV;
2b1b7e78 2534 enum nvme_ctrl_state new_state = NVME_CTRL_LIVE;
5e82e952 2535
82b057ca 2536 if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING))
fd634f41 2537 goto out;
5e82e952 2538
fd634f41
CH		 2539 /*
2540 * If we're called to reset a live controller first shut it down before
2541 * moving on.
2542 */
b00a726a 2543 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
a5cdb68c 2544 nvme_dev_disable(dev, false);
5e82e952 2545
ad70062c 2546 /*
ad6a0a52 2547 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
ad70062c
JW		 2548 * initializing procedure here.
2549 */
ad6a0a52 2550 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
ad70062c 2551 dev_warn(dev->ctrl.device,
ad6a0a52 2552 "failed to mark controller CONNECTING\n");
ad70062c
JW		 2553 goto out;
2554 }
2555
b00a726a 2556 result = nvme_pci_enable(dev);
f0b50732 2557 if (result)
3cf519b5 2558 goto out;
f0b50732 2559
01ad0990 2560 result = nvme_pci_configure_admin_queue(dev);
f0b50732 2561 if (result)
f58944e2 2562 goto out;
f0b50732 2563
0fb59cbc
KB		 2564 result = nvme_alloc_admin_tags(dev);
2565 if (result)
f58944e2 2566 goto out;
b9afca3e 2567
943e942e
JA		 2568 /*
2569 * Limit the max command size to prevent iod->sg allocations going
2570 * over a single page.
2571 */
2572 dev->ctrl.max_hw_sectors = NVME_MAX_KB_SZ << 1;
2573 dev->ctrl.max_segments = NVME_MAX_SEGS;
2574
ce4541f4
CH		 2575 result = nvme_init_identify(&dev->ctrl);
2576 if (result)
f58944e2 2577 goto out;
ce4541f4 2578
e286bcfc
SB		 2579 if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
2580 if (!dev->ctrl.opal_dev)
2581 dev->ctrl.opal_dev =
2582 init_opal_dev(&dev->ctrl, &nvme_sec_submit);
2583 else if (was_suspend)
2584 opal_unlock_from_suspend(dev->ctrl.opal_dev);
2585 } else {
2586 free_opal_dev(dev->ctrl.opal_dev);
2587 dev->ctrl.opal_dev = NULL;
4f1244c8 2588 }
a98e58e5 2589
f9f38e33
HK		 2590 if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) {
2591 result = nvme_dbbuf_dma_alloc(dev);
2592 if (result)
2593 dev_warn(dev->dev,
2594 "unable to allocate dma for dbbuf\n");
2595 }
2596
9620cfba
CH		 2597 if (dev->ctrl.hmpre) {
2598 result = nvme_setup_host_mem(dev);
2599 if (result < 0)
2600 goto out;
2601 }
87ad72a5 2602
f0b50732 2603 result = nvme_setup_io_queues(dev);
badc34d4 2604 if (result)
f58944e2 2605 goto out;
f0b50732 2606
2659e57b
CH		 2607 /*
2608 * Keep the controller around but remove all namespaces if we don't have
2609 * any working I/O queue.
2610 */
3cf519b5 2611 if (dev->online_queues < 2) {
1b3c47c1 2612 dev_warn(dev->ctrl.device, "IO queues not created\n");
3b24774e 2613 nvme_kill_queues(&dev->ctrl);
5bae7f73 2614 nvme_remove_namespaces(&dev->ctrl);
2b1b7e78 2615 new_state = NVME_CTRL_ADMIN_ONLY;
3cf519b5 2616 } else {
25646264 2617 nvme_start_queues(&dev->ctrl);
302ad8cc 2618 nvme_wait_freeze(&dev->ctrl);
2b1b7e78
JW		 2619 /* hit this only when allocate tagset fails */
2620 if (nvme_dev_add(dev))
2621 new_state = NVME_CTRL_ADMIN_ONLY;
302ad8cc 2622 nvme_unfreeze(&dev->ctrl);
3cf519b5
CH		 2623 }
2624
2b1b7e78
JW		 2625 /*
2626 * If only admin queue live, keep it to do further investigation or
2627 * recovery.
2628 */
2629 if (!nvme_change_ctrl_state(&dev->ctrl, new_state)) {
2630 dev_warn(dev->ctrl.device,
2631 "failed to mark controller state %d\n", new_state);
bb8d261e
CH		 2632 goto out;
2633 }
92911a55 2634
d09f2b45 2635 nvme_start_ctrl(&dev->ctrl);
3cf519b5 2636 return;
f0b50732 2637
3cf519b5 2638 out:
f58944e2 2639 nvme_remove_dead_ctrl(dev, result);
f0b50732
KB		 2640}
2641
5c8809e6 2642static void nvme_remove_dead_ctrl_work(struct work_struct *work)
9a6b9458 2643{
5c8809e6 2644 struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
e75ec752 2645 struct pci_dev *pdev = to_pci_dev(dev->dev);
9a6b9458
KB		 2646
2647 if (pci_get_drvdata(pdev))
921920ab 2648 device_release_driver(&pdev->dev);
1673f1f0 2649 nvme_put_ctrl(&dev->ctrl);
9a6b9458
KB		 2650}
2651
1c63dc66 2652static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
9ca97374 2653{
1c63dc66 2654 *val = readl(to_nvme_dev(ctrl)->bar + off);
90667892 2655 return 0;
9ca97374
TH		 2656}
2657
5fd4ce1b 2658static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
4cc06521 2659{
5fd4ce1b
CH		 2660 writel(val, to_nvme_dev(ctrl)->bar + off);
2661 return 0;
2662}
4cc06521 2663
7fd8930f
CH		 2664static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2665{
2666 *val = readq(to_nvme_dev(ctrl)->bar + off);
2667 return 0;
4cc06521
KB		 2668}
2669
97c12223
KB		 2670static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
2671{
2672 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2673
2674 return snprintf(buf, size, "%s", dev_name(&pdev->dev));
2675}
2676
1c63dc66 2677static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
1a353d85 2678 .name = "pcie",
e439bb12 2679 .module = THIS_MODULE,
e0596ab2
LG		 2680 .flags = NVME_F_METADATA_SUPPORTED |
2681 NVME_F_PCI_P2PDMA,
1c63dc66 2682 .reg_read32 = nvme_pci_reg_read32,
5fd4ce1b 2683 .reg_write32 = nvme_pci_reg_write32,
7fd8930f 2684 .reg_read64 = nvme_pci_reg_read64,
1673f1f0 2685 .free_ctrl = nvme_pci_free_ctrl,
f866fc42 2686 .submit_async_event = nvme_pci_submit_async_event,
97c12223 2687 .get_address = nvme_pci_get_address,
1c63dc66 2688};
4cc06521 2689
b00a726a
KB		 2690static int nvme_dev_map(struct nvme_dev *dev)
2691{
b00a726a
KB		 2692 struct pci_dev *pdev = to_pci_dev(dev->dev);
2693
a1f447b3 2694 if (pci_request_mem_regions(pdev, "nvme"))
b00a726a
KB		 2695 return -ENODEV;
2696
97f6ef64 2697 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
b00a726a
KB		 2698 goto release;
2699
9fa196e7 2700 return 0;
b00a726a 2701 release:
9fa196e7
MG		 2702 pci_release_mem_regions(pdev);
2703 return -ENODEV;
b00a726a
KB		 2704}
2705
8427bbc2 2706static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
ff5350a8
AL		 2707{
2708 if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
2709 /*
2710 * Several Samsung devices seem to drop off the PCIe bus
2711 * randomly when APST is on and uses the deepest sleep state.
2712 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2713 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2714 * 950 PRO 256GB", but it seems to be restricted to two Dell
2715 * laptops.
2716 */
2717 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
2718 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
2719 dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
2720 return NVME_QUIRK_NO_DEEPEST_PS;
8427bbc2
KHF		 2721 } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
2722 /*
2723 * Samsung SSD 960 EVO drops off the PCIe bus after system
467c77d4
JJ		 2724 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
2725 * within few minutes after bootup on a Coffee Lake board -
2726 * ASUS PRIME Z370-A
8427bbc2
KHF		 2727 */
2728 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
467c77d4
JJ		 2729 (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") ||
2730 dmi_match(DMI_BOARD_NAME, "PRIME Z370-A")))
8427bbc2 2731 return NVME_QUIRK_NO_APST;
ff5350a8
AL		 2732 }
2733
2734 return 0;
2735}
2736
18119775
KB		 2737static void nvme_async_probe(void *data, async_cookie_t cookie)
2738{
2739 struct nvme_dev *dev = data;
80f513b5 2740
18119775
KB		 2741 nvme_reset_ctrl_sync(&dev->ctrl);
2742 flush_work(&dev->ctrl.scan_work);
80f513b5 2743 nvme_put_ctrl(&dev->ctrl);
18119775
KB		 2744}
2745
8d85fce7 2746static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
b60503ba 2747{
a4aea562 2748 int node, result = -ENOMEM;
b60503ba 2749 struct nvme_dev *dev;
ff5350a8 2750 unsigned long quirks = id->driver_data;
943e942e 2751 size_t alloc_size;
b60503ba 2752
a4aea562
MB		 2753 node = dev_to_node(&pdev->dev);
2754 if (node == NUMA_NO_NODE)
2fa84351 2755 set_dev_node(&pdev->dev, first_memory_node);
a4aea562
MB		 2756
2757 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
b60503ba
MW		 2758 if (!dev)
2759 return -ENOMEM;
147b27e4 2760
3b6592f7
JA		 2761 dev->queues = kcalloc_node(max_queue_count(), sizeof(struct nvme_queue),
2762 GFP_KERNEL, node);
b60503ba
MW		 2763 if (!dev->queues)
2764 goto free;
2765
e75ec752 2766 dev->dev = get_device(&pdev->dev);
9a6b9458 2767 pci_set_drvdata(pdev, dev);
1c63dc66 2768
b00a726a
KB		 2769 result = nvme_dev_map(dev);
2770 if (result)
b00c9b7a 2771 goto put_pci;
b00a726a 2772
d86c4d8e 2773 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
5c8809e6 2774 INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
77bf25ea 2775 mutex_init(&dev->shutdown_lock);
b60503ba 2776
091b6092
MW		 2777 result = nvme_setup_prp_pools(dev);
2778 if (result)
b00c9b7a 2779 goto unmap;
4cc06521 2780
8427bbc2 2781 quirks |= check_vendor_combination_bug(pdev);
ff5350a8 2782
943e942e
JA		 2783 /*
2784 * Double check that our mempool alloc size will cover the biggest
2785 * command we support.
2786 */
2787 alloc_size = nvme_pci_iod_alloc_size(dev, NVME_MAX_KB_SZ,
2788 NVME_MAX_SEGS, true);
2789 WARN_ON_ONCE(alloc_size > PAGE_SIZE);
2790
2791 dev->iod_mempool = mempool_create_node(1, mempool_kmalloc,
2792 mempool_kfree,
2793 (void *) alloc_size,
2794 GFP_KERNEL, node);
2795 if (!dev->iod_mempool) {
2796 result = -ENOMEM;
2797 goto release_pools;
2798 }
2799
b6e44b4c
KB		 2800 result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
2801 quirks);
2802 if (result)
2803 goto release_mempool;
2804
1b3c47c1
SG		 2805 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
2806
80f513b5 2807 nvme_get_ctrl(&dev->ctrl);
18119775 2808 async_schedule(nvme_async_probe, dev);
4caff8fc 2809
b60503ba
MW		 2810 return 0;
2811
b6e44b4c
KB		 2812 release_mempool:
2813 mempool_destroy(dev->iod_mempool);
0877cb0d 2814 release_pools:
091b6092 2815 nvme_release_prp_pools(dev);
b00c9b7a
CJ		 2816 unmap:
2817 nvme_dev_unmap(dev);
a96d4f5c 2818 put_pci:
e75ec752 2819 put_device(dev->dev);
b60503ba
MW		 2820 free:
2821 kfree(dev->queues);
b60503ba
MW		 2822 kfree(dev);
2823 return result;
2824}
2825
775755ed 2826static void nvme_reset_prepare(struct pci_dev *pdev)
f0d54a54 2827{
a6739479 2828 struct nvme_dev *dev = pci_get_drvdata(pdev);
f263fbb8 2829 nvme_dev_disable(dev, false);
775755ed 2830}
f0d54a54 2831
775755ed
CH		 2832static void nvme_reset_done(struct pci_dev *pdev)
2833{
f263fbb8 2834 struct nvme_dev *dev = pci_get_drvdata(pdev);
79c48ccf 2835 nvme_reset_ctrl_sync(&dev->ctrl);
f0d54a54
KB		 2836}
2837
09ece142
KB		 2838static void nvme_shutdown(struct pci_dev *pdev)
2839{
2840 struct nvme_dev *dev = pci_get_drvdata(pdev);
a5cdb68c 2841 nvme_dev_disable(dev, true);
09ece142
KB		 2842}
2843
f58944e2
KB		 2844/*
2845 * The driver's remove may be called on a device in a partially initialized
2846 * state. This function must not have any dependencies on the device state in
2847 * order to proceed.
2848 */
8d85fce7 2849static void nvme_remove(struct pci_dev *pdev)
b60503ba
MW		 2850{
2851 struct nvme_dev *dev = pci_get_drvdata(pdev);
9a6b9458 2852
bb8d261e 2853 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
9a6b9458 2854 pci_set_drvdata(pdev, NULL);
0ff9d4e1 2855
6db28eda 2856 if (!pci_device_is_present(pdev)) {
0ff9d4e1 2857 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
1d39e692 2858 nvme_dev_disable(dev, true);
cb4bfda6 2859 nvme_dev_remove_admin(dev);
6db28eda 2860 }
0ff9d4e1 2861
d86c4d8e 2862 flush_work(&dev->ctrl.reset_work);
d09f2b45
SG		 2863 nvme_stop_ctrl(&dev->ctrl);
2864 nvme_remove_namespaces(&dev->ctrl);
a5cdb68c 2865 nvme_dev_disable(dev, true);
9fe5c59f 2866 nvme_release_cmb(dev);
87ad72a5 2867 nvme_free_host_mem(dev);
a4aea562 2868 nvme_dev_remove_admin(dev);
a1a5ef99 2869 nvme_free_queues(dev, 0);
d09f2b45 2870 nvme_uninit_ctrl(&dev->ctrl);
9a6b9458 2871 nvme_release_prp_pools(dev);
b00a726a 2872 nvme_dev_unmap(dev);
1673f1f0 2873 nvme_put_ctrl(&dev->ctrl);
b60503ba
MW		 2874}
2875
671a6018 2876#ifdef CONFIG_PM_SLEEP
cd638946
KB		 2877static int nvme_suspend(struct device *dev)
2878{
2879 struct pci_dev *pdev = to_pci_dev(dev);
2880 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2881
a5cdb68c 2882 nvme_dev_disable(ndev, true);
cd638946
KB		 2883 return 0;
2884}
2885
2886static int nvme_resume(struct device *dev)
2887{
2888 struct pci_dev *pdev = to_pci_dev(dev);
2889 struct nvme_dev *ndev = pci_get_drvdata(pdev);
cd638946 2890
d86c4d8e 2891 nvme_reset_ctrl(&ndev->ctrl);
9a6b9458 2892 return 0;
cd638946 2893}
671a6018 2894#endif
cd638946
KB		 2895
2896static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
b60503ba 2897
a0a3408e
KB		 2898static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
2899 pci_channel_state_t state)
2900{
2901 struct nvme_dev *dev = pci_get_drvdata(pdev);
2902
2903 /*
2904 * A frozen channel requires a reset. When detected, this method will
2905 * shutdown the controller to quiesce. The controller will be restarted
2906 * after the slot reset through driver's slot_reset callback.
2907 */
a0a3408e
KB		 2908 switch (state) {
2909 case pci_channel_io_normal:
2910 return PCI_ERS_RESULT_CAN_RECOVER;
2911 case pci_channel_io_frozen:
d011fb31
KB		 2912 dev_warn(dev->ctrl.device,
2913 "frozen state error detected, reset controller\n");
a5cdb68c 2914 nvme_dev_disable(dev, false);
a0a3408e
KB		 2915 return PCI_ERS_RESULT_NEED_RESET;
2916 case pci_channel_io_perm_failure:
d011fb31
KB		 2917 dev_warn(dev->ctrl.device,
2918 "failure state error detected, request disconnect\n");
a0a3408e
KB		 2919 return PCI_ERS_RESULT_DISCONNECT;
2920 }
2921 return PCI_ERS_RESULT_NEED_RESET;
2922}
2923
2924static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
2925{
2926 struct nvme_dev *dev = pci_get_drvdata(pdev);
2927
1b3c47c1 2928 dev_info(dev->ctrl.device, "restart after slot reset\n");
a0a3408e 2929 pci_restore_state(pdev);
d86c4d8e 2930 nvme_reset_ctrl(&dev->ctrl);
a0a3408e
KB		 2931 return PCI_ERS_RESULT_RECOVERED;
2932}
2933
2934static void nvme_error_resume(struct pci_dev *pdev)
2935{
72cd4cc2
KB		 2936 struct nvme_dev *dev = pci_get_drvdata(pdev);
2937
2938 flush_work(&dev->ctrl.reset_work);
a0a3408e
KB		 2939}
2940
1d352035 2941static const struct pci_error_handlers nvme_err_handler = {
b60503ba 2942 .error_detected = nvme_error_detected,
b60503ba
MW		 2943 .slot_reset = nvme_slot_reset,
2944 .resume = nvme_error_resume,
775755ed
CH		 2945 .reset_prepare = nvme_reset_prepare,
2946 .reset_done = nvme_reset_done,
b60503ba
MW		 2947};
2948
6eb0d698 2949static const struct pci_device_id nvme_id_table[] = {
106198ed 2950 { PCI_VDEVICE(INTEL, 0x0953),
08095e70 2951 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 2952 NVME_QUIRK_DEALLOCATE_ZEROES, },
99466e70
KB		 2953 { PCI_VDEVICE(INTEL, 0x0a53),
2954 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 2955 NVME_QUIRK_DEALLOCATE_ZEROES, },
99466e70
KB		 2956 { PCI_VDEVICE(INTEL, 0x0a54),
2957 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 2958 NVME_QUIRK_DEALLOCATE_ZEROES, },
f99cb7af
DWF		 2959 { PCI_VDEVICE(INTEL, 0x0a55),
2960 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2961 NVME_QUIRK_DEALLOCATE_ZEROES, },
50af47d0 2962 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */
9abd68ef
JA		 2963 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
2964 NVME_QUIRK_MEDIUM_PRIO_SQ },
540c801c
KB		 2965 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */
2966 .driver_data = NVME_QUIRK_IDENTIFY_CNS, },
0302ae60
MP		 2967 { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */
2968 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
54adc010
GP		 2969 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
2970 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
8c97eecc
JL		 2971 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */
2972 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
015282c9
WW		 2973 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
2974 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
d554b5e1
MP		 2975 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */
2976 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2977 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */
2978 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
608cc4b1
CH		 2979 { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */
2980 .driver_data = NVME_QUIRK_LIGHTNVM, },
2981 { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */
2982 .driver_data = NVME_QUIRK_LIGHTNVM, },
ea48e877
WX		 2983 { PCI_DEVICE(0x1d1d, 0x2601), /* CNEX Granby */
2984 .driver_data = NVME_QUIRK_LIGHTNVM, },
b60503ba 2985 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
c74dc780 2986 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) },
124298bd 2987 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
b60503ba
MW		 2988 { 0, }
2989};
2990MODULE_DEVICE_TABLE(pci, nvme_id_table);
2991
2992static struct pci_driver nvme_driver = {
2993 .name = "nvme",
2994 .id_table = nvme_id_table,
2995 .probe = nvme_probe,
8d85fce7 2996 .remove = nvme_remove,
09ece142 2997 .shutdown = nvme_shutdown,
cd638946
KB		 2998 .driver = {
2999 .pm = &nvme_dev_pm_ops,
3000 },
74d986ab 3001 .sriov_configure = pci_sriov_configure_simple,
b60503ba
MW		 3002 .err_handler = &nvme_err_handler,
3003};
3004
3005static int __init nvme_init(void)
3006{
9a6327d2 3007 return pci_register_driver(&nvme_driver);
b60503ba
MW		 3008}
3009
3010static void __exit nvme_exit(void)
3011{
3012 pci_unregister_driver(&nvme_driver);
03e0f3a6 3013 flush_workqueue(nvme_wq);
21bd78bc 3014 _nvme_check_size();
b60503ba
MW		 3015}
3016
3017MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3018MODULE_LICENSE("GPL");
c78b4713 3019MODULE_VERSION("1.0");
b60503ba
MW		 3020module_init(nvme_init);
3021module_exit(nvme_exit);
Linux 6.x block layer and io_uring tree(s)