Commit | Line | Data |
---|---|---|
b60503ba MW |
1 | /* |
2 | * NVM Express device driver | |
6eb0d698 | 3 | * Copyright (c) 2011-2014, Intel Corporation. |
b60503ba MW |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
b60503ba MW |
13 | */ |
14 | ||
8de05535 | 15 | #include <linux/bitops.h> |
b60503ba | 16 | #include <linux/blkdev.h> |
a4aea562 | 17 | #include <linux/blk-mq.h> |
42f61420 | 18 | #include <linux/cpu.h> |
fd63e9ce | 19 | #include <linux/delay.h> |
b60503ba MW |
20 | #include <linux/errno.h> |
21 | #include <linux/fs.h> | |
22 | #include <linux/genhd.h> | |
4cc09e2d | 23 | #include <linux/hdreg.h> |
5aff9382 | 24 | #include <linux/idr.h> |
b60503ba MW |
25 | #include <linux/init.h> |
26 | #include <linux/interrupt.h> | |
27 | #include <linux/io.h> | |
28 | #include <linux/kdev_t.h> | |
1fa6aead | 29 | #include <linux/kthread.h> |
b60503ba MW |
30 | #include <linux/kernel.h> |
31 | #include <linux/mm.h> | |
32 | #include <linux/module.h> | |
33 | #include <linux/moduleparam.h> | |
77bf25ea | 34 | #include <linux/mutex.h> |
b60503ba | 35 | #include <linux/pci.h> |
be7b6275 | 36 | #include <linux/poison.h> |
c3bfe717 | 37 | #include <linux/ptrace.h> |
b60503ba MW |
38 | #include <linux/sched.h> |
39 | #include <linux/slab.h> | |
e1e5e564 | 40 | #include <linux/t10-pi.h> |
b60503ba | 41 | #include <linux/types.h> |
2f8e2c87 | 42 | #include <linux/io-64-nonatomic-lo-hi.h> |
1d277a63 | 43 | #include <asm/unaligned.h> |
797a796a | 44 | |
f11bb3e2 CH |
45 | #include "nvme.h" |
46 | ||
9d43cf64 | 47 | #define NVME_Q_DEPTH 1024 |
d31af0a3 | 48 | #define NVME_AQ_DEPTH 256 |
b60503ba MW |
49 | #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command)) |
50 | #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion)) | |
9d43cf64 | 51 | |
21d34711 | 52 | unsigned char admin_timeout = 60; |
9d43cf64 KB |
53 | module_param(admin_timeout, byte, 0644); |
54 | MODULE_PARM_DESC(admin_timeout, "timeout in seconds for admin commands"); | |
b60503ba | 55 | |
bd67608a MW |
56 | unsigned char nvme_io_timeout = 30; |
57 | module_param_named(io_timeout, nvme_io_timeout, byte, 0644); | |
b355084a | 58 | MODULE_PARM_DESC(io_timeout, "timeout in seconds for I/O"); |
b60503ba | 59 | |
5fd4ce1b | 60 | unsigned char shutdown_timeout = 5; |
2484f407 DM |
61 | module_param(shutdown_timeout, byte, 0644); |
62 | MODULE_PARM_DESC(shutdown_timeout, "timeout in seconds for controller shutdown"); | |
63 | ||
58ffacb5 MW |
64 | static int use_threaded_interrupts; |
65 | module_param(use_threaded_interrupts, int, 0); | |
66 | ||
8ffaadf7 JD |
67 | static bool use_cmb_sqes = true; |
68 | module_param(use_cmb_sqes, bool, 0644); | |
69 | MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes"); | |
70 | ||
1fa6aead MW |
71 | static LIST_HEAD(dev_list); |
72 | static struct task_struct *nvme_thread; | |
9a6b9458 | 73 | static struct workqueue_struct *nvme_workq; |
b9afca3e | 74 | static wait_queue_head_t nvme_kthread_wait; |
1fa6aead | 75 | |
1c63dc66 CH |
76 | struct nvme_dev; |
77 | struct nvme_queue; | |
d4f6c3ab | 78 | struct nvme_iod; |
1c63dc66 | 79 | |
90667892 | 80 | static int __nvme_reset(struct nvme_dev *dev); |
4cc06521 | 81 | static int nvme_reset(struct nvme_dev *dev); |
a0fa9647 | 82 | static void nvme_process_cq(struct nvme_queue *nvmeq); |
d4f6c3ab | 83 | static void nvme_unmap_data(struct nvme_dev *dev, struct nvme_iod *iod); |
3cf519b5 | 84 | static void nvme_dead_ctrl(struct nvme_dev *dev); |
d4b4ff8e | 85 | |
4d115420 KB |
86 | struct async_cmd_info { |
87 | struct kthread_work work; | |
88 | struct kthread_worker *worker; | |
a4aea562 | 89 | struct request *req; |
4d115420 KB |
90 | u32 result; |
91 | int status; | |
92 | void *ctx; | |
93 | }; | |
1fa6aead | 94 | |
1c63dc66 CH |
95 | /* |
96 | * Represents an NVM Express device. Each nvme_dev is a PCI function. | |
97 | */ | |
98 | struct nvme_dev { | |
99 | struct list_head node; | |
100 | struct nvme_queue **queues; | |
101 | struct blk_mq_tag_set tagset; | |
102 | struct blk_mq_tag_set admin_tagset; | |
103 | u32 __iomem *dbs; | |
104 | struct device *dev; | |
105 | struct dma_pool *prp_page_pool; | |
106 | struct dma_pool *prp_small_pool; | |
107 | unsigned queue_count; | |
108 | unsigned online_queues; | |
109 | unsigned max_qid; | |
110 | int q_depth; | |
111 | u32 db_stride; | |
1c63dc66 CH |
112 | struct msix_entry *entry; |
113 | void __iomem *bar; | |
1c63dc66 CH |
114 | struct work_struct reset_work; |
115 | struct work_struct probe_work; | |
116 | struct work_struct scan_work; | |
77bf25ea | 117 | struct mutex shutdown_lock; |
1c63dc66 | 118 | bool subsystem; |
1c63dc66 CH |
119 | void __iomem *cmb; |
120 | dma_addr_t cmb_dma_addr; | |
121 | u64 cmb_size; | |
122 | u32 cmbsz; | |
123 | ||
124 | struct nvme_ctrl ctrl; | |
125 | }; | |
126 | ||
127 | static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl) | |
128 | { | |
129 | return container_of(ctrl, struct nvme_dev, ctrl); | |
130 | } | |
131 | ||
b60503ba MW |
132 | /* |
133 | * An NVM Express queue. Each device has at least two (one for admin | |
134 | * commands and one for I/O commands). | |
135 | */ | |
136 | struct nvme_queue { | |
137 | struct device *q_dmadev; | |
091b6092 | 138 | struct nvme_dev *dev; |
3193f07b | 139 | char irqname[24]; /* nvme4294967295-65535\0 */ |
b60503ba MW |
140 | spinlock_t q_lock; |
141 | struct nvme_command *sq_cmds; | |
8ffaadf7 | 142 | struct nvme_command __iomem *sq_cmds_io; |
b60503ba | 143 | volatile struct nvme_completion *cqes; |
42483228 | 144 | struct blk_mq_tags **tags; |
b60503ba MW |
145 | dma_addr_t sq_dma_addr; |
146 | dma_addr_t cq_dma_addr; | |
b60503ba MW |
147 | u32 __iomem *q_db; |
148 | u16 q_depth; | |
6222d172 | 149 | s16 cq_vector; |
b60503ba MW |
150 | u16 sq_head; |
151 | u16 sq_tail; | |
152 | u16 cq_head; | |
c30341dc | 153 | u16 qid; |
e9539f47 MW |
154 | u8 cq_phase; |
155 | u8 cqe_seen; | |
4d115420 | 156 | struct async_cmd_info cmdinfo; |
b60503ba MW |
157 | }; |
158 | ||
71bd150c CH |
159 | /* |
160 | * The nvme_iod describes the data in an I/O, including the list of PRP | |
161 | * entries. You can't see it in this data structure because C doesn't let | |
162 | * me express that. Use nvme_alloc_iod to ensure there's enough space | |
163 | * allocated to store the PRP list. | |
164 | */ | |
165 | struct nvme_iod { | |
166 | unsigned long private; /* For the use of the submitter of the I/O */ | |
167 | int npages; /* In the PRP list. 0 means small pool in use */ | |
168 | int offset; /* Of PRP list */ | |
169 | int nents; /* Used in scatterlist */ | |
170 | int length; /* Of data, in bytes */ | |
171 | dma_addr_t first_dma; | |
172 | struct scatterlist meta_sg[1]; /* metadata requires single contiguous buffer */ | |
173 | struct scatterlist sg[0]; | |
174 | }; | |
175 | ||
b60503ba MW |
176 | /* |
177 | * Check we didin't inadvertently grow the command struct | |
178 | */ | |
179 | static inline void _nvme_check_size(void) | |
180 | { | |
181 | BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64); | |
182 | BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); | |
183 | BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); | |
184 | BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); | |
185 | BUILD_BUG_ON(sizeof(struct nvme_features) != 64); | |
f8ebf840 | 186 | BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64); |
c30341dc | 187 | BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64); |
b60503ba MW |
188 | BUILD_BUG_ON(sizeof(struct nvme_command) != 64); |
189 | BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096); | |
190 | BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096); | |
191 | BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64); | |
6ecec745 | 192 | BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512); |
b60503ba MW |
193 | } |
194 | ||
edd10d33 | 195 | typedef void (*nvme_completion_fn)(struct nvme_queue *, void *, |
c2f5b650 MW |
196 | struct nvme_completion *); |
197 | ||
e85248e5 | 198 | struct nvme_cmd_info { |
c2f5b650 MW |
199 | nvme_completion_fn fn; |
200 | void *ctx; | |
c30341dc | 201 | int aborted; |
a4aea562 | 202 | struct nvme_queue *nvmeq; |
ac3dd5bd | 203 | struct nvme_iod iod[0]; |
e85248e5 MW |
204 | }; |
205 | ||
ac3dd5bd JA |
206 | /* |
207 | * Max size of iod being embedded in the request payload | |
208 | */ | |
209 | #define NVME_INT_PAGES 2 | |
5fd4ce1b | 210 | #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size) |
fda631ff | 211 | #define NVME_INT_MASK 0x01 |
ac3dd5bd JA |
212 | |
213 | /* | |
214 | * Will slightly overestimate the number of pages needed. This is OK | |
215 | * as it only leads to a small amount of wasted memory for the lifetime of | |
216 | * the I/O. | |
217 | */ | |
218 | static int nvme_npages(unsigned size, struct nvme_dev *dev) | |
219 | { | |
5fd4ce1b CH |
220 | unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size, |
221 | dev->ctrl.page_size); | |
ac3dd5bd JA |
222 | return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); |
223 | } | |
224 | ||
225 | static unsigned int nvme_cmd_size(struct nvme_dev *dev) | |
226 | { | |
227 | unsigned int ret = sizeof(struct nvme_cmd_info); | |
228 | ||
229 | ret += sizeof(struct nvme_iod); | |
230 | ret += sizeof(__le64 *) * nvme_npages(NVME_INT_BYTES(dev), dev); | |
231 | ret += sizeof(struct scatterlist) * NVME_INT_PAGES; | |
232 | ||
233 | return ret; | |
234 | } | |
235 | ||
a4aea562 MB |
236 | static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, |
237 | unsigned int hctx_idx) | |
e85248e5 | 238 | { |
a4aea562 MB |
239 | struct nvme_dev *dev = data; |
240 | struct nvme_queue *nvmeq = dev->queues[0]; | |
241 | ||
42483228 KB |
242 | WARN_ON(hctx_idx != 0); |
243 | WARN_ON(dev->admin_tagset.tags[0] != hctx->tags); | |
244 | WARN_ON(nvmeq->tags); | |
245 | ||
a4aea562 | 246 | hctx->driver_data = nvmeq; |
42483228 | 247 | nvmeq->tags = &dev->admin_tagset.tags[0]; |
a4aea562 | 248 | return 0; |
e85248e5 MW |
249 | } |
250 | ||
4af0e21c KB |
251 | static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx) |
252 | { | |
253 | struct nvme_queue *nvmeq = hctx->driver_data; | |
254 | ||
255 | nvmeq->tags = NULL; | |
256 | } | |
257 | ||
a4aea562 MB |
258 | static int nvme_admin_init_request(void *data, struct request *req, |
259 | unsigned int hctx_idx, unsigned int rq_idx, | |
260 | unsigned int numa_node) | |
22404274 | 261 | { |
a4aea562 MB |
262 | struct nvme_dev *dev = data; |
263 | struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req); | |
264 | struct nvme_queue *nvmeq = dev->queues[0]; | |
265 | ||
266 | BUG_ON(!nvmeq); | |
267 | cmd->nvmeq = nvmeq; | |
268 | return 0; | |
22404274 KB |
269 | } |
270 | ||
a4aea562 MB |
271 | static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, |
272 | unsigned int hctx_idx) | |
b60503ba | 273 | { |
a4aea562 | 274 | struct nvme_dev *dev = data; |
42483228 | 275 | struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1]; |
a4aea562 | 276 | |
42483228 KB |
277 | if (!nvmeq->tags) |
278 | nvmeq->tags = &dev->tagset.tags[hctx_idx]; | |
b60503ba | 279 | |
42483228 | 280 | WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags); |
a4aea562 MB |
281 | hctx->driver_data = nvmeq; |
282 | return 0; | |
b60503ba MW |
283 | } |
284 | ||
a4aea562 MB |
285 | static int nvme_init_request(void *data, struct request *req, |
286 | unsigned int hctx_idx, unsigned int rq_idx, | |
287 | unsigned int numa_node) | |
b60503ba | 288 | { |
a4aea562 MB |
289 | struct nvme_dev *dev = data; |
290 | struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req); | |
291 | struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1]; | |
292 | ||
293 | BUG_ON(!nvmeq); | |
294 | cmd->nvmeq = nvmeq; | |
295 | return 0; | |
296 | } | |
297 | ||
298 | static void nvme_set_info(struct nvme_cmd_info *cmd, void *ctx, | |
299 | nvme_completion_fn handler) | |
300 | { | |
301 | cmd->fn = handler; | |
302 | cmd->ctx = ctx; | |
303 | cmd->aborted = 0; | |
c917dfe5 | 304 | blk_mq_start_request(blk_mq_rq_from_pdu(cmd)); |
b60503ba MW |
305 | } |
306 | ||
ac3dd5bd JA |
307 | static void *iod_get_private(struct nvme_iod *iod) |
308 | { | |
309 | return (void *) (iod->private & ~0x1UL); | |
310 | } | |
311 | ||
312 | /* | |
313 | * If bit 0 is set, the iod is embedded in the request payload. | |
314 | */ | |
315 | static bool iod_should_kfree(struct nvme_iod *iod) | |
316 | { | |
fda631ff | 317 | return (iod->private & NVME_INT_MASK) == 0; |
ac3dd5bd JA |
318 | } |
319 | ||
c2f5b650 MW |
320 | /* Special values must be less than 0x1000 */ |
321 | #define CMD_CTX_BASE ((void *)POISON_POINTER_DELTA) | |
d2d87034 MW |
322 | #define CMD_CTX_CANCELLED (0x30C + CMD_CTX_BASE) |
323 | #define CMD_CTX_COMPLETED (0x310 + CMD_CTX_BASE) | |
324 | #define CMD_CTX_INVALID (0x314 + CMD_CTX_BASE) | |
be7b6275 | 325 | |
edd10d33 | 326 | static void special_completion(struct nvme_queue *nvmeq, void *ctx, |
c2f5b650 MW |
327 | struct nvme_completion *cqe) |
328 | { | |
329 | if (ctx == CMD_CTX_CANCELLED) | |
330 | return; | |
c2f5b650 | 331 | if (ctx == CMD_CTX_COMPLETED) { |
edd10d33 | 332 | dev_warn(nvmeq->q_dmadev, |
c2f5b650 MW |
333 | "completed id %d twice on queue %d\n", |
334 | cqe->command_id, le16_to_cpup(&cqe->sq_id)); | |
335 | return; | |
336 | } | |
337 | if (ctx == CMD_CTX_INVALID) { | |
edd10d33 | 338 | dev_warn(nvmeq->q_dmadev, |
c2f5b650 MW |
339 | "invalid id %d completed on queue %d\n", |
340 | cqe->command_id, le16_to_cpup(&cqe->sq_id)); | |
341 | return; | |
342 | } | |
edd10d33 | 343 | dev_warn(nvmeq->q_dmadev, "Unknown special completion %p\n", ctx); |
c2f5b650 MW |
344 | } |
345 | ||
a4aea562 | 346 | static void *cancel_cmd_info(struct nvme_cmd_info *cmd, nvme_completion_fn *fn) |
b60503ba | 347 | { |
c2f5b650 | 348 | void *ctx; |
b60503ba | 349 | |
859361a2 | 350 | if (fn) |
a4aea562 MB |
351 | *fn = cmd->fn; |
352 | ctx = cmd->ctx; | |
353 | cmd->fn = special_completion; | |
354 | cmd->ctx = CMD_CTX_CANCELLED; | |
c2f5b650 | 355 | return ctx; |
b60503ba MW |
356 | } |
357 | ||
a4aea562 MB |
358 | static void async_req_completion(struct nvme_queue *nvmeq, void *ctx, |
359 | struct nvme_completion *cqe) | |
3c0cf138 | 360 | { |
a4aea562 MB |
361 | u32 result = le32_to_cpup(&cqe->result); |
362 | u16 status = le16_to_cpup(&cqe->status) >> 1; | |
363 | ||
364 | if (status == NVME_SC_SUCCESS || status == NVME_SC_ABORT_REQ) | |
1c63dc66 | 365 | ++nvmeq->dev->ctrl.event_limit; |
a5768aa8 KB |
366 | if (status != NVME_SC_SUCCESS) |
367 | return; | |
368 | ||
369 | switch (result & 0xff07) { | |
370 | case NVME_AER_NOTICE_NS_CHANGED: | |
371 | dev_info(nvmeq->q_dmadev, "rescanning\n"); | |
372 | schedule_work(&nvmeq->dev->scan_work); | |
373 | default: | |
374 | dev_warn(nvmeq->q_dmadev, "async event result %08x\n", result); | |
375 | } | |
b60503ba MW |
376 | } |
377 | ||
a4aea562 MB |
378 | static void abort_completion(struct nvme_queue *nvmeq, void *ctx, |
379 | struct nvme_completion *cqe) | |
5a92e700 | 380 | { |
a4aea562 MB |
381 | struct request *req = ctx; |
382 | ||
383 | u16 status = le16_to_cpup(&cqe->status) >> 1; | |
384 | u32 result = le32_to_cpup(&cqe->result); | |
a51afb54 | 385 | |
42483228 | 386 | blk_mq_free_request(req); |
a51afb54 | 387 | |
a4aea562 | 388 | dev_warn(nvmeq->q_dmadev, "Abort status:%x result:%x", status, result); |
1c63dc66 | 389 | ++nvmeq->dev->ctrl.abort_limit; |
5a92e700 KB |
390 | } |
391 | ||
a4aea562 MB |
392 | static void async_completion(struct nvme_queue *nvmeq, void *ctx, |
393 | struct nvme_completion *cqe) | |
b60503ba | 394 | { |
a4aea562 MB |
395 | struct async_cmd_info *cmdinfo = ctx; |
396 | cmdinfo->result = le32_to_cpup(&cqe->result); | |
397 | cmdinfo->status = le16_to_cpup(&cqe->status) >> 1; | |
398 | queue_kthread_work(cmdinfo->worker, &cmdinfo->work); | |
42483228 | 399 | blk_mq_free_request(cmdinfo->req); |
b60503ba MW |
400 | } |
401 | ||
a4aea562 MB |
402 | static inline struct nvme_cmd_info *get_cmd_from_tag(struct nvme_queue *nvmeq, |
403 | unsigned int tag) | |
b60503ba | 404 | { |
42483228 | 405 | struct request *req = blk_mq_tag_to_rq(*nvmeq->tags, tag); |
a51afb54 | 406 | |
a4aea562 | 407 | return blk_mq_rq_to_pdu(req); |
4f5099af KB |
408 | } |
409 | ||
a4aea562 MB |
410 | /* |
411 | * Called with local interrupts disabled and the q_lock held. May not sleep. | |
412 | */ | |
413 | static void *nvme_finish_cmd(struct nvme_queue *nvmeq, int tag, | |
414 | nvme_completion_fn *fn) | |
4f5099af | 415 | { |
a4aea562 MB |
416 | struct nvme_cmd_info *cmd = get_cmd_from_tag(nvmeq, tag); |
417 | void *ctx; | |
418 | if (tag >= nvmeq->q_depth) { | |
419 | *fn = special_completion; | |
420 | return CMD_CTX_INVALID; | |
421 | } | |
422 | if (fn) | |
423 | *fn = cmd->fn; | |
424 | ctx = cmd->ctx; | |
425 | cmd->fn = special_completion; | |
426 | cmd->ctx = CMD_CTX_COMPLETED; | |
427 | return ctx; | |
b60503ba MW |
428 | } |
429 | ||
430 | /** | |
714a7a22 | 431 | * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell |
b60503ba MW |
432 | * @nvmeq: The queue to use |
433 | * @cmd: The command to send | |
434 | * | |
435 | * Safe to use from interrupt context | |
436 | */ | |
e3f879bf SB |
437 | static void __nvme_submit_cmd(struct nvme_queue *nvmeq, |
438 | struct nvme_command *cmd) | |
b60503ba | 439 | { |
a4aea562 MB |
440 | u16 tail = nvmeq->sq_tail; |
441 | ||
8ffaadf7 JD |
442 | if (nvmeq->sq_cmds_io) |
443 | memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd)); | |
444 | else | |
445 | memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd)); | |
446 | ||
b60503ba MW |
447 | if (++tail == nvmeq->q_depth) |
448 | tail = 0; | |
7547881d | 449 | writel(tail, nvmeq->q_db); |
b60503ba | 450 | nvmeq->sq_tail = tail; |
b60503ba MW |
451 | } |
452 | ||
e3f879bf | 453 | static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd) |
a4aea562 MB |
454 | { |
455 | unsigned long flags; | |
a4aea562 | 456 | spin_lock_irqsave(&nvmeq->q_lock, flags); |
e3f879bf | 457 | __nvme_submit_cmd(nvmeq, cmd); |
a4aea562 | 458 | spin_unlock_irqrestore(&nvmeq->q_lock, flags); |
a4aea562 MB |
459 | } |
460 | ||
eca18b23 | 461 | static __le64 **iod_list(struct nvme_iod *iod) |
e025344c | 462 | { |
eca18b23 | 463 | return ((void *)iod) + iod->offset; |
e025344c SMM |
464 | } |
465 | ||
ac3dd5bd JA |
466 | static inline void iod_init(struct nvme_iod *iod, unsigned nbytes, |
467 | unsigned nseg, unsigned long private) | |
eca18b23 | 468 | { |
ac3dd5bd JA |
469 | iod->private = private; |
470 | iod->offset = offsetof(struct nvme_iod, sg[nseg]); | |
471 | iod->npages = -1; | |
472 | iod->length = nbytes; | |
473 | iod->nents = 0; | |
eca18b23 | 474 | } |
b60503ba | 475 | |
eca18b23 | 476 | static struct nvme_iod * |
ac3dd5bd JA |
477 | __nvme_alloc_iod(unsigned nseg, unsigned bytes, struct nvme_dev *dev, |
478 | unsigned long priv, gfp_t gfp) | |
b60503ba | 479 | { |
eca18b23 | 480 | struct nvme_iod *iod = kmalloc(sizeof(struct nvme_iod) + |
ac3dd5bd | 481 | sizeof(__le64 *) * nvme_npages(bytes, dev) + |
eca18b23 MW |
482 | sizeof(struct scatterlist) * nseg, gfp); |
483 | ||
ac3dd5bd JA |
484 | if (iod) |
485 | iod_init(iod, bytes, nseg, priv); | |
eca18b23 MW |
486 | |
487 | return iod; | |
b60503ba MW |
488 | } |
489 | ||
ac3dd5bd JA |
490 | static struct nvme_iod *nvme_alloc_iod(struct request *rq, struct nvme_dev *dev, |
491 | gfp_t gfp) | |
492 | { | |
493 | unsigned size = !(rq->cmd_flags & REQ_DISCARD) ? blk_rq_bytes(rq) : | |
494 | sizeof(struct nvme_dsm_range); | |
ac3dd5bd JA |
495 | struct nvme_iod *iod; |
496 | ||
497 | if (rq->nr_phys_segments <= NVME_INT_PAGES && | |
498 | size <= NVME_INT_BYTES(dev)) { | |
499 | struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(rq); | |
500 | ||
501 | iod = cmd->iod; | |
ac3dd5bd | 502 | iod_init(iod, size, rq->nr_phys_segments, |
fda631ff | 503 | (unsigned long) rq | NVME_INT_MASK); |
ac3dd5bd JA |
504 | return iod; |
505 | } | |
506 | ||
507 | return __nvme_alloc_iod(rq->nr_phys_segments, size, dev, | |
508 | (unsigned long) rq, gfp); | |
509 | } | |
510 | ||
d29ec824 | 511 | static void nvme_free_iod(struct nvme_dev *dev, struct nvme_iod *iod) |
b60503ba | 512 | { |
5fd4ce1b | 513 | const int last_prp = dev->ctrl.page_size / 8 - 1; |
eca18b23 MW |
514 | int i; |
515 | __le64 **list = iod_list(iod); | |
516 | dma_addr_t prp_dma = iod->first_dma; | |
517 | ||
518 | if (iod->npages == 0) | |
519 | dma_pool_free(dev->prp_small_pool, list[0], prp_dma); | |
520 | for (i = 0; i < iod->npages; i++) { | |
521 | __le64 *prp_list = list[i]; | |
522 | dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]); | |
523 | dma_pool_free(dev->prp_page_pool, prp_list, prp_dma); | |
524 | prp_dma = next_prp_dma; | |
525 | } | |
ac3dd5bd JA |
526 | |
527 | if (iod_should_kfree(iod)) | |
528 | kfree(iod); | |
b60503ba MW |
529 | } |
530 | ||
52b68d7e | 531 | #ifdef CONFIG_BLK_DEV_INTEGRITY |
e1e5e564 KB |
532 | static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi) |
533 | { | |
534 | if (be32_to_cpu(pi->ref_tag) == v) | |
535 | pi->ref_tag = cpu_to_be32(p); | |
536 | } | |
537 | ||
538 | static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi) | |
539 | { | |
540 | if (be32_to_cpu(pi->ref_tag) == p) | |
541 | pi->ref_tag = cpu_to_be32(v); | |
542 | } | |
543 | ||
544 | /** | |
545 | * nvme_dif_remap - remaps ref tags to bip seed and physical lba | |
546 | * | |
547 | * The virtual start sector is the one that was originally submitted by the | |
548 | * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical | |
549 | * start sector may be different. Remap protection information to match the | |
550 | * physical LBA on writes, and back to the original seed on reads. | |
551 | * | |
552 | * Type 0 and 3 do not have a ref tag, so no remapping required. | |
553 | */ | |
554 | static void nvme_dif_remap(struct request *req, | |
555 | void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi)) | |
556 | { | |
557 | struct nvme_ns *ns = req->rq_disk->private_data; | |
558 | struct bio_integrity_payload *bip; | |
559 | struct t10_pi_tuple *pi; | |
560 | void *p, *pmap; | |
561 | u32 i, nlb, ts, phys, virt; | |
562 | ||
563 | if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3) | |
564 | return; | |
565 | ||
566 | bip = bio_integrity(req->bio); | |
567 | if (!bip) | |
568 | return; | |
569 | ||
570 | pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset; | |
e1e5e564 KB |
571 | |
572 | p = pmap; | |
573 | virt = bip_get_seed(bip); | |
574 | phys = nvme_block_nr(ns, blk_rq_pos(req)); | |
575 | nlb = (blk_rq_bytes(req) >> ns->lba_shift); | |
ac6fc48c | 576 | ts = ns->disk->queue->integrity.tuple_size; |
e1e5e564 KB |
577 | |
578 | for (i = 0; i < nlb; i++, virt++, phys++) { | |
579 | pi = (struct t10_pi_tuple *)p; | |
580 | dif_swap(phys, virt, pi); | |
581 | p += ts; | |
582 | } | |
583 | kunmap_atomic(pmap); | |
584 | } | |
52b68d7e KB |
585 | #else /* CONFIG_BLK_DEV_INTEGRITY */ |
586 | static void nvme_dif_remap(struct request *req, | |
587 | void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi)) | |
588 | { | |
589 | } | |
590 | static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi) | |
591 | { | |
592 | } | |
593 | static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi) | |
594 | { | |
595 | } | |
52b68d7e KB |
596 | #endif |
597 | ||
a4aea562 | 598 | static void req_completion(struct nvme_queue *nvmeq, void *ctx, |
b60503ba MW |
599 | struct nvme_completion *cqe) |
600 | { | |
eca18b23 | 601 | struct nvme_iod *iod = ctx; |
ac3dd5bd | 602 | struct request *req = iod_get_private(iod); |
a4aea562 | 603 | struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req); |
b60503ba | 604 | u16 status = le16_to_cpup(&cqe->status) >> 1; |
81c04b94 | 605 | int error = 0; |
b60503ba | 606 | |
edd10d33 | 607 | if (unlikely(status)) { |
a4aea562 MB |
608 | if (!(status & NVME_SC_DNR || blk_noretry_request(req)) |
609 | && (jiffies - req->start_time) < req->timeout) { | |
c9d3bf88 KB |
610 | unsigned long flags; |
611 | ||
d4f6c3ab CH |
612 | nvme_unmap_data(nvmeq->dev, iod); |
613 | ||
a4aea562 | 614 | blk_mq_requeue_request(req); |
c9d3bf88 KB |
615 | spin_lock_irqsave(req->q->queue_lock, flags); |
616 | if (!blk_queue_stopped(req->q)) | |
617 | blk_mq_kick_requeue_list(req->q); | |
618 | spin_unlock_irqrestore(req->q->queue_lock, flags); | |
d4f6c3ab | 619 | return; |
edd10d33 | 620 | } |
f4829a9b | 621 | |
d29ec824 | 622 | if (req->cmd_type == REQ_TYPE_DRV_PRIV) { |
17188bb4 | 623 | if (cmd_rq->ctx == CMD_CTX_CANCELLED) |
81c04b94 CH |
624 | error = -EINTR; |
625 | else | |
626 | error = status; | |
d29ec824 | 627 | } else { |
81c04b94 | 628 | error = nvme_error_status(status); |
d29ec824 | 629 | } |
f4829a9b CH |
630 | } |
631 | ||
a0a931d6 KB |
632 | if (req->cmd_type == REQ_TYPE_DRV_PRIV) { |
633 | u32 result = le32_to_cpup(&cqe->result); | |
634 | req->special = (void *)(uintptr_t)result; | |
635 | } | |
a4aea562 MB |
636 | |
637 | if (cmd_rq->aborted) | |
e75ec752 | 638 | dev_warn(nvmeq->dev->dev, |
a4aea562 | 639 | "completing aborted command with status:%04x\n", |
81c04b94 | 640 | error); |
a4aea562 | 641 | |
d4f6c3ab CH |
642 | nvme_unmap_data(nvmeq->dev, iod); |
643 | blk_mq_complete_request(req, error); | |
b60503ba MW |
644 | } |
645 | ||
69d2b571 CH |
646 | static bool nvme_setup_prps(struct nvme_dev *dev, struct nvme_iod *iod, |
647 | int total_len) | |
ff22b54f | 648 | { |
99802a7a | 649 | struct dma_pool *pool; |
eca18b23 MW |
650 | int length = total_len; |
651 | struct scatterlist *sg = iod->sg; | |
ff22b54f MW |
652 | int dma_len = sg_dma_len(sg); |
653 | u64 dma_addr = sg_dma_address(sg); | |
5fd4ce1b | 654 | u32 page_size = dev->ctrl.page_size; |
f137e0f1 | 655 | int offset = dma_addr & (page_size - 1); |
e025344c | 656 | __le64 *prp_list; |
eca18b23 | 657 | __le64 **list = iod_list(iod); |
e025344c | 658 | dma_addr_t prp_dma; |
eca18b23 | 659 | int nprps, i; |
ff22b54f | 660 | |
1d090624 | 661 | length -= (page_size - offset); |
ff22b54f | 662 | if (length <= 0) |
69d2b571 | 663 | return true; |
ff22b54f | 664 | |
1d090624 | 665 | dma_len -= (page_size - offset); |
ff22b54f | 666 | if (dma_len) { |
1d090624 | 667 | dma_addr += (page_size - offset); |
ff22b54f MW |
668 | } else { |
669 | sg = sg_next(sg); | |
670 | dma_addr = sg_dma_address(sg); | |
671 | dma_len = sg_dma_len(sg); | |
672 | } | |
673 | ||
1d090624 | 674 | if (length <= page_size) { |
edd10d33 | 675 | iod->first_dma = dma_addr; |
69d2b571 | 676 | return true; |
e025344c SMM |
677 | } |
678 | ||
1d090624 | 679 | nprps = DIV_ROUND_UP(length, page_size); |
99802a7a MW |
680 | if (nprps <= (256 / 8)) { |
681 | pool = dev->prp_small_pool; | |
eca18b23 | 682 | iod->npages = 0; |
99802a7a MW |
683 | } else { |
684 | pool = dev->prp_page_pool; | |
eca18b23 | 685 | iod->npages = 1; |
99802a7a MW |
686 | } |
687 | ||
69d2b571 | 688 | prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); |
b77954cb | 689 | if (!prp_list) { |
edd10d33 | 690 | iod->first_dma = dma_addr; |
eca18b23 | 691 | iod->npages = -1; |
69d2b571 | 692 | return false; |
b77954cb | 693 | } |
eca18b23 MW |
694 | list[0] = prp_list; |
695 | iod->first_dma = prp_dma; | |
e025344c SMM |
696 | i = 0; |
697 | for (;;) { | |
1d090624 | 698 | if (i == page_size >> 3) { |
e025344c | 699 | __le64 *old_prp_list = prp_list; |
69d2b571 | 700 | prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); |
eca18b23 | 701 | if (!prp_list) |
69d2b571 | 702 | return false; |
eca18b23 | 703 | list[iod->npages++] = prp_list; |
7523d834 MW |
704 | prp_list[0] = old_prp_list[i - 1]; |
705 | old_prp_list[i - 1] = cpu_to_le64(prp_dma); | |
706 | i = 1; | |
e025344c SMM |
707 | } |
708 | prp_list[i++] = cpu_to_le64(dma_addr); | |
1d090624 KB |
709 | dma_len -= page_size; |
710 | dma_addr += page_size; | |
711 | length -= page_size; | |
e025344c SMM |
712 | if (length <= 0) |
713 | break; | |
714 | if (dma_len > 0) | |
715 | continue; | |
716 | BUG_ON(dma_len < 0); | |
717 | sg = sg_next(sg); | |
718 | dma_addr = sg_dma_address(sg); | |
719 | dma_len = sg_dma_len(sg); | |
ff22b54f MW |
720 | } |
721 | ||
69d2b571 | 722 | return true; |
ff22b54f MW |
723 | } |
724 | ||
ba1ca37e CH |
725 | static int nvme_map_data(struct nvme_dev *dev, struct nvme_iod *iod, |
726 | struct nvme_command *cmnd) | |
d29ec824 | 727 | { |
ba1ca37e CH |
728 | struct request *req = iod_get_private(iod); |
729 | struct request_queue *q = req->q; | |
730 | enum dma_data_direction dma_dir = rq_data_dir(req) ? | |
731 | DMA_TO_DEVICE : DMA_FROM_DEVICE; | |
732 | int ret = BLK_MQ_RQ_QUEUE_ERROR; | |
733 | ||
734 | sg_init_table(iod->sg, req->nr_phys_segments); | |
735 | iod->nents = blk_rq_map_sg(q, req, iod->sg); | |
736 | if (!iod->nents) | |
737 | goto out; | |
738 | ||
739 | ret = BLK_MQ_RQ_QUEUE_BUSY; | |
740 | if (!dma_map_sg(dev->dev, iod->sg, iod->nents, dma_dir)) | |
741 | goto out; | |
742 | ||
743 | if (!nvme_setup_prps(dev, iod, blk_rq_bytes(req))) | |
744 | goto out_unmap; | |
745 | ||
746 | ret = BLK_MQ_RQ_QUEUE_ERROR; | |
747 | if (blk_integrity_rq(req)) { | |
748 | if (blk_rq_count_integrity_sg(q, req->bio) != 1) | |
749 | goto out_unmap; | |
750 | ||
751 | sg_init_table(iod->meta_sg, 1); | |
752 | if (blk_rq_map_integrity_sg(q, req->bio, iod->meta_sg) != 1) | |
753 | goto out_unmap; | |
d29ec824 | 754 | |
ba1ca37e CH |
755 | if (rq_data_dir(req)) |
756 | nvme_dif_remap(req, nvme_dif_prep); | |
757 | ||
758 | if (!dma_map_sg(dev->dev, iod->meta_sg, 1, dma_dir)) | |
759 | goto out_unmap; | |
d29ec824 CH |
760 | } |
761 | ||
ba1ca37e CH |
762 | cmnd->rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg)); |
763 | cmnd->rw.prp2 = cpu_to_le64(iod->first_dma); | |
764 | if (blk_integrity_rq(req)) | |
765 | cmnd->rw.metadata = cpu_to_le64(sg_dma_address(iod->meta_sg)); | |
766 | return BLK_MQ_RQ_QUEUE_OK; | |
767 | ||
768 | out_unmap: | |
769 | dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); | |
770 | out: | |
771 | return ret; | |
d29ec824 CH |
772 | } |
773 | ||
d4f6c3ab CH |
774 | static void nvme_unmap_data(struct nvme_dev *dev, struct nvme_iod *iod) |
775 | { | |
776 | struct request *req = iod_get_private(iod); | |
777 | enum dma_data_direction dma_dir = rq_data_dir(req) ? | |
778 | DMA_TO_DEVICE : DMA_FROM_DEVICE; | |
779 | ||
780 | if (iod->nents) { | |
781 | dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); | |
782 | if (blk_integrity_rq(req)) { | |
783 | if (!rq_data_dir(req)) | |
784 | nvme_dif_remap(req, nvme_dif_complete); | |
785 | dma_unmap_sg(dev->dev, iod->meta_sg, 1, dma_dir); | |
786 | } | |
787 | } | |
788 | ||
789 | nvme_free_iod(dev, iod); | |
790 | } | |
791 | ||
a4aea562 MB |
792 | /* |
793 | * We reuse the small pool to allocate the 16-byte range here as it is not | |
794 | * worth having a special pool for these or additional cases to handle freeing | |
795 | * the iod. | |
796 | */ | |
ba1ca37e CH |
797 | static int nvme_setup_discard(struct nvme_queue *nvmeq, struct nvme_ns *ns, |
798 | struct nvme_iod *iod, struct nvme_command *cmnd) | |
0e5e4f0e | 799 | { |
ba1ca37e CH |
800 | struct request *req = iod_get_private(iod); |
801 | struct nvme_dsm_range *range; | |
802 | ||
803 | range = dma_pool_alloc(nvmeq->dev->prp_small_pool, GFP_ATOMIC, | |
804 | &iod->first_dma); | |
805 | if (!range) | |
806 | return BLK_MQ_RQ_QUEUE_BUSY; | |
807 | iod_list(iod)[0] = (__le64 *)range; | |
808 | iod->npages = 0; | |
0e5e4f0e | 809 | |
0e5e4f0e | 810 | range->cattr = cpu_to_le32(0); |
a4aea562 MB |
811 | range->nlb = cpu_to_le32(blk_rq_bytes(req) >> ns->lba_shift); |
812 | range->slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req))); | |
0e5e4f0e | 813 | |
ba1ca37e CH |
814 | memset(cmnd, 0, sizeof(*cmnd)); |
815 | cmnd->dsm.opcode = nvme_cmd_dsm; | |
816 | cmnd->dsm.nsid = cpu_to_le32(ns->ns_id); | |
817 | cmnd->dsm.prp1 = cpu_to_le64(iod->first_dma); | |
818 | cmnd->dsm.nr = 0; | |
819 | cmnd->dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD); | |
820 | return BLK_MQ_RQ_QUEUE_OK; | |
0e5e4f0e KB |
821 | } |
822 | ||
d29ec824 CH |
823 | /* |
824 | * NOTE: ns is NULL when called on the admin queue. | |
825 | */ | |
a4aea562 MB |
826 | static int nvme_queue_rq(struct blk_mq_hw_ctx *hctx, |
827 | const struct blk_mq_queue_data *bd) | |
edd10d33 | 828 | { |
a4aea562 MB |
829 | struct nvme_ns *ns = hctx->queue->queuedata; |
830 | struct nvme_queue *nvmeq = hctx->driver_data; | |
d29ec824 | 831 | struct nvme_dev *dev = nvmeq->dev; |
a4aea562 MB |
832 | struct request *req = bd->rq; |
833 | struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req); | |
edd10d33 | 834 | struct nvme_iod *iod; |
ba1ca37e CH |
835 | struct nvme_command cmnd; |
836 | int ret = BLK_MQ_RQ_QUEUE_OK; | |
edd10d33 | 837 | |
e1e5e564 KB |
838 | /* |
839 | * If formated with metadata, require the block layer provide a buffer | |
840 | * unless this namespace is formated such that the metadata can be | |
841 | * stripped/generated by the controller with PRACT=1. | |
842 | */ | |
d29ec824 | 843 | if (ns && ns->ms && !blk_integrity_rq(req)) { |
71feb364 KB |
844 | if (!(ns->pi_type && ns->ms == 8) && |
845 | req->cmd_type != REQ_TYPE_DRV_PRIV) { | |
f4829a9b | 846 | blk_mq_complete_request(req, -EFAULT); |
e1e5e564 KB |
847 | return BLK_MQ_RQ_QUEUE_OK; |
848 | } | |
849 | } | |
850 | ||
d29ec824 | 851 | iod = nvme_alloc_iod(req, dev, GFP_ATOMIC); |
edd10d33 | 852 | if (!iod) |
fe54303e | 853 | return BLK_MQ_RQ_QUEUE_BUSY; |
a4aea562 | 854 | |
a4aea562 | 855 | if (req->cmd_flags & REQ_DISCARD) { |
ba1ca37e CH |
856 | ret = nvme_setup_discard(nvmeq, ns, iod, &cmnd); |
857 | } else { | |
858 | if (req->cmd_type == REQ_TYPE_DRV_PRIV) | |
859 | memcpy(&cmnd, req->cmd, sizeof(cmnd)); | |
860 | else if (req->cmd_flags & REQ_FLUSH) | |
861 | nvme_setup_flush(ns, &cmnd); | |
862 | else | |
863 | nvme_setup_rw(ns, req, &cmnd); | |
a4aea562 | 864 | |
ba1ca37e CH |
865 | if (req->nr_phys_segments) |
866 | ret = nvme_map_data(dev, iod, &cmnd); | |
edd10d33 | 867 | } |
1974b1ae | 868 | |
ba1ca37e CH |
869 | if (ret) |
870 | goto out; | |
871 | ||
872 | cmnd.common.command_id = req->tag; | |
9af8785a | 873 | nvme_set_info(cmd, iod, req_completion); |
a4aea562 | 874 | |
ba1ca37e CH |
875 | spin_lock_irq(&nvmeq->q_lock); |
876 | __nvme_submit_cmd(nvmeq, &cmnd); | |
a4aea562 MB |
877 | nvme_process_cq(nvmeq); |
878 | spin_unlock_irq(&nvmeq->q_lock); | |
879 | return BLK_MQ_RQ_QUEUE_OK; | |
ba1ca37e | 880 | out: |
d29ec824 | 881 | nvme_free_iod(dev, iod); |
ba1ca37e | 882 | return ret; |
b60503ba MW |
883 | } |
884 | ||
a0fa9647 | 885 | static void __nvme_process_cq(struct nvme_queue *nvmeq, unsigned int *tag) |
b60503ba | 886 | { |
82123460 | 887 | u16 head, phase; |
b60503ba | 888 | |
b60503ba | 889 | head = nvmeq->cq_head; |
82123460 | 890 | phase = nvmeq->cq_phase; |
b60503ba MW |
891 | |
892 | for (;;) { | |
c2f5b650 MW |
893 | void *ctx; |
894 | nvme_completion_fn fn; | |
b60503ba | 895 | struct nvme_completion cqe = nvmeq->cqes[head]; |
82123460 | 896 | if ((le16_to_cpu(cqe.status) & 1) != phase) |
b60503ba MW |
897 | break; |
898 | nvmeq->sq_head = le16_to_cpu(cqe.sq_head); | |
899 | if (++head == nvmeq->q_depth) { | |
900 | head = 0; | |
82123460 | 901 | phase = !phase; |
b60503ba | 902 | } |
a0fa9647 JA |
903 | if (tag && *tag == cqe.command_id) |
904 | *tag = -1; | |
a4aea562 | 905 | ctx = nvme_finish_cmd(nvmeq, cqe.command_id, &fn); |
edd10d33 | 906 | fn(nvmeq, ctx, &cqe); |
b60503ba MW |
907 | } |
908 | ||
909 | /* If the controller ignores the cq head doorbell and continuously | |
910 | * writes to the queue, it is theoretically possible to wrap around | |
911 | * the queue twice and mistakenly return IRQ_NONE. Linux only | |
912 | * requires that 0.1% of your interrupts are handled, so this isn't | |
913 | * a big problem. | |
914 | */ | |
82123460 | 915 | if (head == nvmeq->cq_head && phase == nvmeq->cq_phase) |
a0fa9647 | 916 | return; |
b60503ba | 917 | |
604e8c8d KB |
918 | if (likely(nvmeq->cq_vector >= 0)) |
919 | writel(head, nvmeq->q_db + nvmeq->dev->db_stride); | |
b60503ba | 920 | nvmeq->cq_head = head; |
82123460 | 921 | nvmeq->cq_phase = phase; |
b60503ba | 922 | |
e9539f47 | 923 | nvmeq->cqe_seen = 1; |
a0fa9647 JA |
924 | } |
925 | ||
926 | static void nvme_process_cq(struct nvme_queue *nvmeq) | |
927 | { | |
928 | __nvme_process_cq(nvmeq, NULL); | |
b60503ba MW |
929 | } |
930 | ||
931 | static irqreturn_t nvme_irq(int irq, void *data) | |
58ffacb5 MW |
932 | { |
933 | irqreturn_t result; | |
934 | struct nvme_queue *nvmeq = data; | |
935 | spin_lock(&nvmeq->q_lock); | |
e9539f47 MW |
936 | nvme_process_cq(nvmeq); |
937 | result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE; | |
938 | nvmeq->cqe_seen = 0; | |
58ffacb5 MW |
939 | spin_unlock(&nvmeq->q_lock); |
940 | return result; | |
941 | } | |
942 | ||
943 | static irqreturn_t nvme_irq_check(int irq, void *data) | |
944 | { | |
945 | struct nvme_queue *nvmeq = data; | |
946 | struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head]; | |
947 | if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase) | |
948 | return IRQ_NONE; | |
949 | return IRQ_WAKE_THREAD; | |
950 | } | |
951 | ||
a0fa9647 JA |
952 | static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag) |
953 | { | |
954 | struct nvme_queue *nvmeq = hctx->driver_data; | |
955 | ||
956 | if ((le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) == | |
957 | nvmeq->cq_phase) { | |
958 | spin_lock_irq(&nvmeq->q_lock); | |
959 | __nvme_process_cq(nvmeq, &tag); | |
960 | spin_unlock_irq(&nvmeq->q_lock); | |
961 | ||
962 | if (tag == -1) | |
963 | return 1; | |
964 | } | |
965 | ||
966 | return 0; | |
967 | } | |
968 | ||
a4aea562 MB |
969 | static int nvme_submit_async_admin_req(struct nvme_dev *dev) |
970 | { | |
971 | struct nvme_queue *nvmeq = dev->queues[0]; | |
972 | struct nvme_command c; | |
973 | struct nvme_cmd_info *cmd_info; | |
974 | struct request *req; | |
975 | ||
1c63dc66 | 976 | req = blk_mq_alloc_request(dev->ctrl.admin_q, WRITE, |
6f3b0e8b | 977 | BLK_MQ_REQ_NOWAIT | BLK_MQ_REQ_RESERVED); |
9f173b33 DC |
978 | if (IS_ERR(req)) |
979 | return PTR_ERR(req); | |
a4aea562 | 980 | |
c917dfe5 | 981 | req->cmd_flags |= REQ_NO_TIMEOUT; |
a4aea562 | 982 | cmd_info = blk_mq_rq_to_pdu(req); |
1efccc9d | 983 | nvme_set_info(cmd_info, NULL, async_req_completion); |
a4aea562 MB |
984 | |
985 | memset(&c, 0, sizeof(c)); | |
986 | c.common.opcode = nvme_admin_async_event; | |
987 | c.common.command_id = req->tag; | |
988 | ||
42483228 | 989 | blk_mq_free_request(req); |
e3f879bf SB |
990 | __nvme_submit_cmd(nvmeq, &c); |
991 | return 0; | |
a4aea562 MB |
992 | } |
993 | ||
994 | static int nvme_submit_admin_async_cmd(struct nvme_dev *dev, | |
4d115420 KB |
995 | struct nvme_command *cmd, |
996 | struct async_cmd_info *cmdinfo, unsigned timeout) | |
997 | { | |
a4aea562 MB |
998 | struct nvme_queue *nvmeq = dev->queues[0]; |
999 | struct request *req; | |
1000 | struct nvme_cmd_info *cmd_rq; | |
4d115420 | 1001 | |
1c63dc66 | 1002 | req = blk_mq_alloc_request(dev->ctrl.admin_q, WRITE, 0); |
9f173b33 DC |
1003 | if (IS_ERR(req)) |
1004 | return PTR_ERR(req); | |
a4aea562 MB |
1005 | |
1006 | req->timeout = timeout; | |
1007 | cmd_rq = blk_mq_rq_to_pdu(req); | |
1008 | cmdinfo->req = req; | |
1009 | nvme_set_info(cmd_rq, cmdinfo, async_completion); | |
4d115420 | 1010 | cmdinfo->status = -EINTR; |
a4aea562 MB |
1011 | |
1012 | cmd->common.command_id = req->tag; | |
1013 | ||
e3f879bf SB |
1014 | nvme_submit_cmd(nvmeq, cmd); |
1015 | return 0; | |
4d115420 KB |
1016 | } |
1017 | ||
b60503ba MW |
1018 | static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) |
1019 | { | |
b60503ba MW |
1020 | struct nvme_command c; |
1021 | ||
1022 | memset(&c, 0, sizeof(c)); | |
1023 | c.delete_queue.opcode = opcode; | |
1024 | c.delete_queue.qid = cpu_to_le16(id); | |
1025 | ||
1c63dc66 | 1026 | return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); |
b60503ba MW |
1027 | } |
1028 | ||
1029 | static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, | |
1030 | struct nvme_queue *nvmeq) | |
1031 | { | |
b60503ba MW |
1032 | struct nvme_command c; |
1033 | int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED; | |
1034 | ||
d29ec824 CH |
1035 | /* |
1036 | * Note: we (ab)use the fact the the prp fields survive if no data | |
1037 | * is attached to the request. | |
1038 | */ | |
b60503ba MW |
1039 | memset(&c, 0, sizeof(c)); |
1040 | c.create_cq.opcode = nvme_admin_create_cq; | |
1041 | c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); | |
1042 | c.create_cq.cqid = cpu_to_le16(qid); | |
1043 | c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); | |
1044 | c.create_cq.cq_flags = cpu_to_le16(flags); | |
1045 | c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector); | |
1046 | ||
1c63dc66 | 1047 | return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); |
b60503ba MW |
1048 | } |
1049 | ||
1050 | static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, | |
1051 | struct nvme_queue *nvmeq) | |
1052 | { | |
b60503ba MW |
1053 | struct nvme_command c; |
1054 | int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM; | |
1055 | ||
d29ec824 CH |
1056 | /* |
1057 | * Note: we (ab)use the fact the the prp fields survive if no data | |
1058 | * is attached to the request. | |
1059 | */ | |
b60503ba MW |
1060 | memset(&c, 0, sizeof(c)); |
1061 | c.create_sq.opcode = nvme_admin_create_sq; | |
1062 | c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); | |
1063 | c.create_sq.sqid = cpu_to_le16(qid); | |
1064 | c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); | |
1065 | c.create_sq.sq_flags = cpu_to_le16(flags); | |
1066 | c.create_sq.cqid = cpu_to_le16(qid); | |
1067 | ||
1c63dc66 | 1068 | return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); |
b60503ba MW |
1069 | } |
1070 | ||
1071 | static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) | |
1072 | { | |
1073 | return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); | |
1074 | } | |
1075 | ||
1076 | static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) | |
1077 | { | |
1078 | return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); | |
1079 | } | |
1080 | ||
c30341dc | 1081 | /** |
a4aea562 | 1082 | * nvme_abort_req - Attempt aborting a request |
c30341dc KB |
1083 | * |
1084 | * Schedule controller reset if the command was already aborted once before and | |
1085 | * still hasn't been returned to the driver, or if this is the admin queue. | |
1086 | */ | |
a4aea562 | 1087 | static void nvme_abort_req(struct request *req) |
c30341dc | 1088 | { |
a4aea562 MB |
1089 | struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req); |
1090 | struct nvme_queue *nvmeq = cmd_rq->nvmeq; | |
c30341dc | 1091 | struct nvme_dev *dev = nvmeq->dev; |
a4aea562 MB |
1092 | struct request *abort_req; |
1093 | struct nvme_cmd_info *abort_cmd; | |
1094 | struct nvme_command cmd; | |
c30341dc | 1095 | |
a4aea562 | 1096 | if (!nvmeq->qid || cmd_rq->aborted) { |
4c9f748f | 1097 | spin_lock_irq(&dev_list_lock); |
90667892 CH |
1098 | if (!__nvme_reset(dev)) { |
1099 | dev_warn(dev->dev, | |
1100 | "I/O %d QID %d timeout, reset controller\n", | |
1101 | req->tag, nvmeq->qid); | |
1102 | } | |
4c9f748f | 1103 | spin_unlock_irq(&dev_list_lock); |
c30341dc KB |
1104 | return; |
1105 | } | |
1106 | ||
1c63dc66 | 1107 | if (!dev->ctrl.abort_limit) |
c30341dc KB |
1108 | return; |
1109 | ||
1c63dc66 | 1110 | abort_req = blk_mq_alloc_request(dev->ctrl.admin_q, WRITE, |
6f3b0e8b | 1111 | BLK_MQ_REQ_NOWAIT); |
9f173b33 | 1112 | if (IS_ERR(abort_req)) |
c30341dc KB |
1113 | return; |
1114 | ||
a4aea562 MB |
1115 | abort_cmd = blk_mq_rq_to_pdu(abort_req); |
1116 | nvme_set_info(abort_cmd, abort_req, abort_completion); | |
1117 | ||
c30341dc KB |
1118 | memset(&cmd, 0, sizeof(cmd)); |
1119 | cmd.abort.opcode = nvme_admin_abort_cmd; | |
a4aea562 | 1120 | cmd.abort.cid = req->tag; |
c30341dc | 1121 | cmd.abort.sqid = cpu_to_le16(nvmeq->qid); |
a4aea562 | 1122 | cmd.abort.command_id = abort_req->tag; |
c30341dc | 1123 | |
1c63dc66 | 1124 | --dev->ctrl.abort_limit; |
a4aea562 | 1125 | cmd_rq->aborted = 1; |
c30341dc | 1126 | |
a4aea562 | 1127 | dev_warn(nvmeq->q_dmadev, "Aborting I/O %d QID %d\n", req->tag, |
c30341dc | 1128 | nvmeq->qid); |
e3f879bf | 1129 | nvme_submit_cmd(dev->queues[0], &cmd); |
c30341dc KB |
1130 | } |
1131 | ||
42483228 | 1132 | static void nvme_cancel_queue_ios(struct request *req, void *data, bool reserved) |
a09115b2 | 1133 | { |
a4aea562 MB |
1134 | struct nvme_queue *nvmeq = data; |
1135 | void *ctx; | |
1136 | nvme_completion_fn fn; | |
1137 | struct nvme_cmd_info *cmd; | |
cef6a948 KB |
1138 | struct nvme_completion cqe; |
1139 | ||
1140 | if (!blk_mq_request_started(req)) | |
1141 | return; | |
a09115b2 | 1142 | |
a4aea562 | 1143 | cmd = blk_mq_rq_to_pdu(req); |
a09115b2 | 1144 | |
a4aea562 MB |
1145 | if (cmd->ctx == CMD_CTX_CANCELLED) |
1146 | return; | |
1147 | ||
cef6a948 KB |
1148 | if (blk_queue_dying(req->q)) |
1149 | cqe.status = cpu_to_le16((NVME_SC_ABORT_REQ | NVME_SC_DNR) << 1); | |
1150 | else | |
1151 | cqe.status = cpu_to_le16(NVME_SC_ABORT_REQ << 1); | |
1152 | ||
1153 | ||
a4aea562 MB |
1154 | dev_warn(nvmeq->q_dmadev, "Cancelling I/O %d QID %d\n", |
1155 | req->tag, nvmeq->qid); | |
1156 | ctx = cancel_cmd_info(cmd, &fn); | |
1157 | fn(nvmeq, ctx, &cqe); | |
a09115b2 MW |
1158 | } |
1159 | ||
a4aea562 | 1160 | static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved) |
9e866774 | 1161 | { |
a4aea562 MB |
1162 | struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req); |
1163 | struct nvme_queue *nvmeq = cmd->nvmeq; | |
1164 | ||
1165 | dev_warn(nvmeq->q_dmadev, "Timeout I/O %d QID %d\n", req->tag, | |
1166 | nvmeq->qid); | |
07836e65 | 1167 | nvme_abort_req(req); |
a4aea562 | 1168 | |
07836e65 KB |
1169 | /* |
1170 | * The aborted req will be completed on receiving the abort req. | |
1171 | * We enable the timer again. If hit twice, it'll cause a device reset, | |
1172 | * as the device then is in a faulty state. | |
1173 | */ | |
1174 | return BLK_EH_RESET_TIMER; | |
a4aea562 | 1175 | } |
22404274 | 1176 | |
a4aea562 MB |
1177 | static void nvme_free_queue(struct nvme_queue *nvmeq) |
1178 | { | |
9e866774 MW |
1179 | dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth), |
1180 | (void *)nvmeq->cqes, nvmeq->cq_dma_addr); | |
8ffaadf7 JD |
1181 | if (nvmeq->sq_cmds) |
1182 | dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth), | |
9e866774 MW |
1183 | nvmeq->sq_cmds, nvmeq->sq_dma_addr); |
1184 | kfree(nvmeq); | |
1185 | } | |
1186 | ||
a1a5ef99 | 1187 | static void nvme_free_queues(struct nvme_dev *dev, int lowest) |
22404274 KB |
1188 | { |
1189 | int i; | |
1190 | ||
a1a5ef99 | 1191 | for (i = dev->queue_count - 1; i >= lowest; i--) { |
a4aea562 | 1192 | struct nvme_queue *nvmeq = dev->queues[i]; |
22404274 | 1193 | dev->queue_count--; |
a4aea562 | 1194 | dev->queues[i] = NULL; |
f435c282 | 1195 | nvme_free_queue(nvmeq); |
121c7ad4 | 1196 | } |
22404274 KB |
1197 | } |
1198 | ||
4d115420 KB |
1199 | /** |
1200 | * nvme_suspend_queue - put queue into suspended state | |
1201 | * @nvmeq - queue to suspend | |
4d115420 KB |
1202 | */ |
1203 | static int nvme_suspend_queue(struct nvme_queue *nvmeq) | |
b60503ba | 1204 | { |
2b25d981 | 1205 | int vector; |
b60503ba | 1206 | |
a09115b2 | 1207 | spin_lock_irq(&nvmeq->q_lock); |
2b25d981 KB |
1208 | if (nvmeq->cq_vector == -1) { |
1209 | spin_unlock_irq(&nvmeq->q_lock); | |
1210 | return 1; | |
1211 | } | |
1212 | vector = nvmeq->dev->entry[nvmeq->cq_vector].vector; | |
42f61420 | 1213 | nvmeq->dev->online_queues--; |
2b25d981 | 1214 | nvmeq->cq_vector = -1; |
a09115b2 MW |
1215 | spin_unlock_irq(&nvmeq->q_lock); |
1216 | ||
1c63dc66 CH |
1217 | if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q) |
1218 | blk_mq_freeze_queue_start(nvmeq->dev->ctrl.admin_q); | |
6df3dbc8 | 1219 | |
aba2080f MW |
1220 | irq_set_affinity_hint(vector, NULL); |
1221 | free_irq(vector, nvmeq); | |
b60503ba | 1222 | |
4d115420 KB |
1223 | return 0; |
1224 | } | |
b60503ba | 1225 | |
4d115420 KB |
1226 | static void nvme_clear_queue(struct nvme_queue *nvmeq) |
1227 | { | |
22404274 | 1228 | spin_lock_irq(&nvmeq->q_lock); |
42483228 KB |
1229 | if (nvmeq->tags && *nvmeq->tags) |
1230 | blk_mq_all_tag_busy_iter(*nvmeq->tags, nvme_cancel_queue_ios, nvmeq); | |
22404274 | 1231 | spin_unlock_irq(&nvmeq->q_lock); |
b60503ba MW |
1232 | } |
1233 | ||
4d115420 KB |
1234 | static void nvme_disable_queue(struct nvme_dev *dev, int qid) |
1235 | { | |
a4aea562 | 1236 | struct nvme_queue *nvmeq = dev->queues[qid]; |
4d115420 KB |
1237 | |
1238 | if (!nvmeq) | |
1239 | return; | |
1240 | if (nvme_suspend_queue(nvmeq)) | |
1241 | return; | |
1242 | ||
0e53d180 KB |
1243 | /* Don't tell the adapter to delete the admin queue. |
1244 | * Don't tell a removed adapter to delete IO queues. */ | |
7a67cbea | 1245 | if (qid && readl(dev->bar + NVME_REG_CSTS) != -1) { |
b60503ba MW |
1246 | adapter_delete_sq(dev, qid); |
1247 | adapter_delete_cq(dev, qid); | |
1248 | } | |
07836e65 KB |
1249 | |
1250 | spin_lock_irq(&nvmeq->q_lock); | |
1251 | nvme_process_cq(nvmeq); | |
1252 | spin_unlock_irq(&nvmeq->q_lock); | |
b60503ba MW |
1253 | } |
1254 | ||
8ffaadf7 JD |
1255 | static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues, |
1256 | int entry_size) | |
1257 | { | |
1258 | int q_depth = dev->q_depth; | |
5fd4ce1b CH |
1259 | unsigned q_size_aligned = roundup(q_depth * entry_size, |
1260 | dev->ctrl.page_size); | |
8ffaadf7 JD |
1261 | |
1262 | if (q_size_aligned * nr_io_queues > dev->cmb_size) { | |
c45f5c99 | 1263 | u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues); |
5fd4ce1b | 1264 | mem_per_q = round_down(mem_per_q, dev->ctrl.page_size); |
c45f5c99 | 1265 | q_depth = div_u64(mem_per_q, entry_size); |
8ffaadf7 JD |
1266 | |
1267 | /* | |
1268 | * Ensure the reduced q_depth is above some threshold where it | |
1269 | * would be better to map queues in system memory with the | |
1270 | * original depth | |
1271 | */ | |
1272 | if (q_depth < 64) | |
1273 | return -ENOMEM; | |
1274 | } | |
1275 | ||
1276 | return q_depth; | |
1277 | } | |
1278 | ||
1279 | static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq, | |
1280 | int qid, int depth) | |
1281 | { | |
1282 | if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz)) { | |
5fd4ce1b CH |
1283 | unsigned offset = (qid - 1) * roundup(SQ_SIZE(depth), |
1284 | dev->ctrl.page_size); | |
8ffaadf7 JD |
1285 | nvmeq->sq_dma_addr = dev->cmb_dma_addr + offset; |
1286 | nvmeq->sq_cmds_io = dev->cmb + offset; | |
1287 | } else { | |
1288 | nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth), | |
1289 | &nvmeq->sq_dma_addr, GFP_KERNEL); | |
1290 | if (!nvmeq->sq_cmds) | |
1291 | return -ENOMEM; | |
1292 | } | |
1293 | ||
1294 | return 0; | |
1295 | } | |
1296 | ||
b60503ba | 1297 | static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid, |
2b25d981 | 1298 | int depth) |
b60503ba | 1299 | { |
a4aea562 | 1300 | struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq), GFP_KERNEL); |
b60503ba MW |
1301 | if (!nvmeq) |
1302 | return NULL; | |
1303 | ||
e75ec752 | 1304 | nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth), |
4d51abf9 | 1305 | &nvmeq->cq_dma_addr, GFP_KERNEL); |
b60503ba MW |
1306 | if (!nvmeq->cqes) |
1307 | goto free_nvmeq; | |
b60503ba | 1308 | |
8ffaadf7 | 1309 | if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth)) |
b60503ba MW |
1310 | goto free_cqdma; |
1311 | ||
e75ec752 | 1312 | nvmeq->q_dmadev = dev->dev; |
091b6092 | 1313 | nvmeq->dev = dev; |
3193f07b | 1314 | snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d", |
1c63dc66 | 1315 | dev->ctrl.instance, qid); |
b60503ba MW |
1316 | spin_lock_init(&nvmeq->q_lock); |
1317 | nvmeq->cq_head = 0; | |
82123460 | 1318 | nvmeq->cq_phase = 1; |
b80d5ccc | 1319 | nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; |
b60503ba | 1320 | nvmeq->q_depth = depth; |
c30341dc | 1321 | nvmeq->qid = qid; |
758dd7fd | 1322 | nvmeq->cq_vector = -1; |
a4aea562 | 1323 | dev->queues[qid] = nvmeq; |
b60503ba | 1324 | |
36a7e993 JD |
1325 | /* make sure queue descriptor is set before queue count, for kthread */ |
1326 | mb(); | |
1327 | dev->queue_count++; | |
1328 | ||
b60503ba MW |
1329 | return nvmeq; |
1330 | ||
1331 | free_cqdma: | |
e75ec752 | 1332 | dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes, |
b60503ba MW |
1333 | nvmeq->cq_dma_addr); |
1334 | free_nvmeq: | |
1335 | kfree(nvmeq); | |
1336 | return NULL; | |
1337 | } | |
1338 | ||
3001082c MW |
1339 | static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq, |
1340 | const char *name) | |
1341 | { | |
58ffacb5 MW |
1342 | if (use_threaded_interrupts) |
1343 | return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector, | |
481e5bad | 1344 | nvme_irq_check, nvme_irq, IRQF_SHARED, |
58ffacb5 | 1345 | name, nvmeq); |
3001082c | 1346 | return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq, |
481e5bad | 1347 | IRQF_SHARED, name, nvmeq); |
3001082c MW |
1348 | } |
1349 | ||
22404274 | 1350 | static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) |
b60503ba | 1351 | { |
22404274 | 1352 | struct nvme_dev *dev = nvmeq->dev; |
b60503ba | 1353 | |
7be50e93 | 1354 | spin_lock_irq(&nvmeq->q_lock); |
22404274 KB |
1355 | nvmeq->sq_tail = 0; |
1356 | nvmeq->cq_head = 0; | |
1357 | nvmeq->cq_phase = 1; | |
b80d5ccc | 1358 | nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; |
22404274 | 1359 | memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth)); |
42f61420 | 1360 | dev->online_queues++; |
7be50e93 | 1361 | spin_unlock_irq(&nvmeq->q_lock); |
22404274 KB |
1362 | } |
1363 | ||
1364 | static int nvme_create_queue(struct nvme_queue *nvmeq, int qid) | |
1365 | { | |
1366 | struct nvme_dev *dev = nvmeq->dev; | |
1367 | int result; | |
3f85d50b | 1368 | |
2b25d981 | 1369 | nvmeq->cq_vector = qid - 1; |
b60503ba MW |
1370 | result = adapter_alloc_cq(dev, qid, nvmeq); |
1371 | if (result < 0) | |
22404274 | 1372 | return result; |
b60503ba MW |
1373 | |
1374 | result = adapter_alloc_sq(dev, qid, nvmeq); | |
1375 | if (result < 0) | |
1376 | goto release_cq; | |
1377 | ||
3193f07b | 1378 | result = queue_request_irq(dev, nvmeq, nvmeq->irqname); |
b60503ba MW |
1379 | if (result < 0) |
1380 | goto release_sq; | |
1381 | ||
22404274 | 1382 | nvme_init_queue(nvmeq, qid); |
22404274 | 1383 | return result; |
b60503ba MW |
1384 | |
1385 | release_sq: | |
1386 | adapter_delete_sq(dev, qid); | |
1387 | release_cq: | |
1388 | adapter_delete_cq(dev, qid); | |
22404274 | 1389 | return result; |
b60503ba MW |
1390 | } |
1391 | ||
a4aea562 | 1392 | static struct blk_mq_ops nvme_mq_admin_ops = { |
d29ec824 | 1393 | .queue_rq = nvme_queue_rq, |
a4aea562 MB |
1394 | .map_queue = blk_mq_map_queue, |
1395 | .init_hctx = nvme_admin_init_hctx, | |
4af0e21c | 1396 | .exit_hctx = nvme_admin_exit_hctx, |
a4aea562 MB |
1397 | .init_request = nvme_admin_init_request, |
1398 | .timeout = nvme_timeout, | |
1399 | }; | |
1400 | ||
1401 | static struct blk_mq_ops nvme_mq_ops = { | |
1402 | .queue_rq = nvme_queue_rq, | |
1403 | .map_queue = blk_mq_map_queue, | |
1404 | .init_hctx = nvme_init_hctx, | |
1405 | .init_request = nvme_init_request, | |
1406 | .timeout = nvme_timeout, | |
a0fa9647 | 1407 | .poll = nvme_poll, |
a4aea562 MB |
1408 | }; |
1409 | ||
ea191d2f KB |
1410 | static void nvme_dev_remove_admin(struct nvme_dev *dev) |
1411 | { | |
1c63dc66 CH |
1412 | if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) { |
1413 | blk_cleanup_queue(dev->ctrl.admin_q); | |
ea191d2f KB |
1414 | blk_mq_free_tag_set(&dev->admin_tagset); |
1415 | } | |
1416 | } | |
1417 | ||
a4aea562 MB |
1418 | static int nvme_alloc_admin_tags(struct nvme_dev *dev) |
1419 | { | |
1c63dc66 | 1420 | if (!dev->ctrl.admin_q) { |
a4aea562 MB |
1421 | dev->admin_tagset.ops = &nvme_mq_admin_ops; |
1422 | dev->admin_tagset.nr_hw_queues = 1; | |
1423 | dev->admin_tagset.queue_depth = NVME_AQ_DEPTH - 1; | |
1efccc9d | 1424 | dev->admin_tagset.reserved_tags = 1; |
a4aea562 | 1425 | dev->admin_tagset.timeout = ADMIN_TIMEOUT; |
e75ec752 | 1426 | dev->admin_tagset.numa_node = dev_to_node(dev->dev); |
ac3dd5bd | 1427 | dev->admin_tagset.cmd_size = nvme_cmd_size(dev); |
a4aea562 MB |
1428 | dev->admin_tagset.driver_data = dev; |
1429 | ||
1430 | if (blk_mq_alloc_tag_set(&dev->admin_tagset)) | |
1431 | return -ENOMEM; | |
1432 | ||
1c63dc66 CH |
1433 | dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset); |
1434 | if (IS_ERR(dev->ctrl.admin_q)) { | |
a4aea562 MB |
1435 | blk_mq_free_tag_set(&dev->admin_tagset); |
1436 | return -ENOMEM; | |
1437 | } | |
1c63dc66 | 1438 | if (!blk_get_queue(dev->ctrl.admin_q)) { |
ea191d2f | 1439 | nvme_dev_remove_admin(dev); |
1c63dc66 | 1440 | dev->ctrl.admin_q = NULL; |
ea191d2f KB |
1441 | return -ENODEV; |
1442 | } | |
0fb59cbc | 1443 | } else |
1c63dc66 | 1444 | blk_mq_unfreeze_queue(dev->ctrl.admin_q); |
a4aea562 MB |
1445 | |
1446 | return 0; | |
1447 | } | |
1448 | ||
8d85fce7 | 1449 | static int nvme_configure_admin_queue(struct nvme_dev *dev) |
b60503ba | 1450 | { |
ba47e386 | 1451 | int result; |
b60503ba | 1452 | u32 aqa; |
7a67cbea | 1453 | u64 cap = lo_hi_readq(dev->bar + NVME_REG_CAP); |
b60503ba MW |
1454 | struct nvme_queue *nvmeq; |
1455 | ||
7a67cbea | 1456 | dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1) ? |
dfbac8c7 KB |
1457 | NVME_CAP_NSSRC(cap) : 0; |
1458 | ||
7a67cbea CH |
1459 | if (dev->subsystem && |
1460 | (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO)) | |
1461 | writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS); | |
dfbac8c7 | 1462 | |
5fd4ce1b | 1463 | result = nvme_disable_ctrl(&dev->ctrl, cap); |
ba47e386 MW |
1464 | if (result < 0) |
1465 | return result; | |
b60503ba | 1466 | |
a4aea562 | 1467 | nvmeq = dev->queues[0]; |
cd638946 | 1468 | if (!nvmeq) { |
2b25d981 | 1469 | nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH); |
cd638946 KB |
1470 | if (!nvmeq) |
1471 | return -ENOMEM; | |
cd638946 | 1472 | } |
b60503ba MW |
1473 | |
1474 | aqa = nvmeq->q_depth - 1; | |
1475 | aqa |= aqa << 16; | |
1476 | ||
7a67cbea CH |
1477 | writel(aqa, dev->bar + NVME_REG_AQA); |
1478 | lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ); | |
1479 | lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ); | |
b60503ba | 1480 | |
5fd4ce1b | 1481 | result = nvme_enable_ctrl(&dev->ctrl, cap); |
025c557a | 1482 | if (result) |
a4aea562 MB |
1483 | goto free_nvmeq; |
1484 | ||
2b25d981 | 1485 | nvmeq->cq_vector = 0; |
3193f07b | 1486 | result = queue_request_irq(dev, nvmeq, nvmeq->irqname); |
758dd7fd JD |
1487 | if (result) { |
1488 | nvmeq->cq_vector = -1; | |
0fb59cbc | 1489 | goto free_nvmeq; |
758dd7fd | 1490 | } |
025c557a | 1491 | |
b60503ba | 1492 | return result; |
a4aea562 | 1493 | |
a4aea562 MB |
1494 | free_nvmeq: |
1495 | nvme_free_queues(dev, 0); | |
1496 | return result; | |
b60503ba MW |
1497 | } |
1498 | ||
1fa6aead MW |
1499 | static int nvme_kthread(void *data) |
1500 | { | |
d4b4ff8e | 1501 | struct nvme_dev *dev, *next; |
1fa6aead MW |
1502 | |
1503 | while (!kthread_should_stop()) { | |
564a232c | 1504 | set_current_state(TASK_INTERRUPTIBLE); |
1fa6aead | 1505 | spin_lock(&dev_list_lock); |
d4b4ff8e | 1506 | list_for_each_entry_safe(dev, next, &dev_list, node) { |
1fa6aead | 1507 | int i; |
7a67cbea | 1508 | u32 csts = readl(dev->bar + NVME_REG_CSTS); |
dfbac8c7 KB |
1509 | |
1510 | if ((dev->subsystem && (csts & NVME_CSTS_NSSRO)) || | |
1511 | csts & NVME_CSTS_CFS) { | |
90667892 CH |
1512 | if (!__nvme_reset(dev)) { |
1513 | dev_warn(dev->dev, | |
1514 | "Failed status: %x, reset controller\n", | |
7a67cbea | 1515 | readl(dev->bar + NVME_REG_CSTS)); |
90667892 | 1516 | } |
d4b4ff8e KB |
1517 | continue; |
1518 | } | |
1fa6aead | 1519 | for (i = 0; i < dev->queue_count; i++) { |
a4aea562 | 1520 | struct nvme_queue *nvmeq = dev->queues[i]; |
740216fc MW |
1521 | if (!nvmeq) |
1522 | continue; | |
1fa6aead | 1523 | spin_lock_irq(&nvmeq->q_lock); |
bc57a0f7 | 1524 | nvme_process_cq(nvmeq); |
6fccf938 | 1525 | |
1c63dc66 | 1526 | while (i == 0 && dev->ctrl.event_limit > 0) { |
a4aea562 | 1527 | if (nvme_submit_async_admin_req(dev)) |
6fccf938 | 1528 | break; |
1c63dc66 | 1529 | dev->ctrl.event_limit--; |
6fccf938 | 1530 | } |
1fa6aead MW |
1531 | spin_unlock_irq(&nvmeq->q_lock); |
1532 | } | |
1533 | } | |
1534 | spin_unlock(&dev_list_lock); | |
acb7aa0d | 1535 | schedule_timeout(round_jiffies_relative(HZ)); |
1fa6aead MW |
1536 | } |
1537 | return 0; | |
1538 | } | |
1539 | ||
749941f2 | 1540 | static int nvme_create_io_queues(struct nvme_dev *dev) |
42f61420 | 1541 | { |
a4aea562 | 1542 | unsigned i; |
749941f2 | 1543 | int ret = 0; |
42f61420 | 1544 | |
749941f2 CH |
1545 | for (i = dev->queue_count; i <= dev->max_qid; i++) { |
1546 | if (!nvme_alloc_queue(dev, i, dev->q_depth)) { | |
1547 | ret = -ENOMEM; | |
42f61420 | 1548 | break; |
749941f2 CH |
1549 | } |
1550 | } | |
42f61420 | 1551 | |
749941f2 CH |
1552 | for (i = dev->online_queues; i <= dev->queue_count - 1; i++) { |
1553 | ret = nvme_create_queue(dev->queues[i], i); | |
1554 | if (ret) { | |
2659e57b | 1555 | nvme_free_queues(dev, i); |
42f61420 | 1556 | break; |
2659e57b | 1557 | } |
749941f2 CH |
1558 | } |
1559 | ||
1560 | /* | |
1561 | * Ignore failing Create SQ/CQ commands, we can continue with less | |
1562 | * than the desired aount of queues, and even a controller without | |
1563 | * I/O queues an still be used to issue admin commands. This might | |
1564 | * be useful to upgrade a buggy firmware for example. | |
1565 | */ | |
1566 | return ret >= 0 ? 0 : ret; | |
42f61420 KB |
1567 | } |
1568 | ||
8ffaadf7 JD |
1569 | static void __iomem *nvme_map_cmb(struct nvme_dev *dev) |
1570 | { | |
1571 | u64 szu, size, offset; | |
1572 | u32 cmbloc; | |
1573 | resource_size_t bar_size; | |
1574 | struct pci_dev *pdev = to_pci_dev(dev->dev); | |
1575 | void __iomem *cmb; | |
1576 | dma_addr_t dma_addr; | |
1577 | ||
1578 | if (!use_cmb_sqes) | |
1579 | return NULL; | |
1580 | ||
7a67cbea | 1581 | dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ); |
8ffaadf7 JD |
1582 | if (!(NVME_CMB_SZ(dev->cmbsz))) |
1583 | return NULL; | |
1584 | ||
7a67cbea | 1585 | cmbloc = readl(dev->bar + NVME_REG_CMBLOC); |
8ffaadf7 JD |
1586 | |
1587 | szu = (u64)1 << (12 + 4 * NVME_CMB_SZU(dev->cmbsz)); | |
1588 | size = szu * NVME_CMB_SZ(dev->cmbsz); | |
1589 | offset = szu * NVME_CMB_OFST(cmbloc); | |
1590 | bar_size = pci_resource_len(pdev, NVME_CMB_BIR(cmbloc)); | |
1591 | ||
1592 | if (offset > bar_size) | |
1593 | return NULL; | |
1594 | ||
1595 | /* | |
1596 | * Controllers may support a CMB size larger than their BAR, | |
1597 | * for example, due to being behind a bridge. Reduce the CMB to | |
1598 | * the reported size of the BAR | |
1599 | */ | |
1600 | if (size > bar_size - offset) | |
1601 | size = bar_size - offset; | |
1602 | ||
1603 | dma_addr = pci_resource_start(pdev, NVME_CMB_BIR(cmbloc)) + offset; | |
1604 | cmb = ioremap_wc(dma_addr, size); | |
1605 | if (!cmb) | |
1606 | return NULL; | |
1607 | ||
1608 | dev->cmb_dma_addr = dma_addr; | |
1609 | dev->cmb_size = size; | |
1610 | return cmb; | |
1611 | } | |
1612 | ||
1613 | static inline void nvme_release_cmb(struct nvme_dev *dev) | |
1614 | { | |
1615 | if (dev->cmb) { | |
1616 | iounmap(dev->cmb); | |
1617 | dev->cmb = NULL; | |
1618 | } | |
1619 | } | |
1620 | ||
9d713c2b KB |
1621 | static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) |
1622 | { | |
b80d5ccc | 1623 | return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride); |
9d713c2b KB |
1624 | } |
1625 | ||
8d85fce7 | 1626 | static int nvme_setup_io_queues(struct nvme_dev *dev) |
b60503ba | 1627 | { |
a4aea562 | 1628 | struct nvme_queue *adminq = dev->queues[0]; |
e75ec752 | 1629 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
42f61420 | 1630 | int result, i, vecs, nr_io_queues, size; |
b60503ba | 1631 | |
42f61420 | 1632 | nr_io_queues = num_possible_cpus(); |
9a0be7ab CH |
1633 | result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues); |
1634 | if (result < 0) | |
1b23484b | 1635 | return result; |
9a0be7ab CH |
1636 | |
1637 | /* | |
1638 | * Degraded controllers might return an error when setting the queue | |
1639 | * count. We still want to be able to bring them online and offer | |
1640 | * access to the admin queue, as that might be only way to fix them up. | |
1641 | */ | |
1642 | if (result > 0) { | |
1643 | dev_err(dev->dev, "Could not set queue count (%d)\n", result); | |
1644 | nr_io_queues = 0; | |
1645 | result = 0; | |
1646 | } | |
b60503ba | 1647 | |
8ffaadf7 JD |
1648 | if (dev->cmb && NVME_CMB_SQS(dev->cmbsz)) { |
1649 | result = nvme_cmb_qdepth(dev, nr_io_queues, | |
1650 | sizeof(struct nvme_command)); | |
1651 | if (result > 0) | |
1652 | dev->q_depth = result; | |
1653 | else | |
1654 | nvme_release_cmb(dev); | |
1655 | } | |
1656 | ||
9d713c2b KB |
1657 | size = db_bar_size(dev, nr_io_queues); |
1658 | if (size > 8192) { | |
f1938f6e | 1659 | iounmap(dev->bar); |
9d713c2b KB |
1660 | do { |
1661 | dev->bar = ioremap(pci_resource_start(pdev, 0), size); | |
1662 | if (dev->bar) | |
1663 | break; | |
1664 | if (!--nr_io_queues) | |
1665 | return -ENOMEM; | |
1666 | size = db_bar_size(dev, nr_io_queues); | |
1667 | } while (1); | |
7a67cbea | 1668 | dev->dbs = dev->bar + 4096; |
5a92e700 | 1669 | adminq->q_db = dev->dbs; |
f1938f6e MW |
1670 | } |
1671 | ||
9d713c2b | 1672 | /* Deregister the admin queue's interrupt */ |
3193f07b | 1673 | free_irq(dev->entry[0].vector, adminq); |
9d713c2b | 1674 | |
e32efbfc JA |
1675 | /* |
1676 | * If we enable msix early due to not intx, disable it again before | |
1677 | * setting up the full range we need. | |
1678 | */ | |
1679 | if (!pdev->irq) | |
1680 | pci_disable_msix(pdev); | |
1681 | ||
be577fab | 1682 | for (i = 0; i < nr_io_queues; i++) |
1b23484b | 1683 | dev->entry[i].entry = i; |
be577fab AG |
1684 | vecs = pci_enable_msix_range(pdev, dev->entry, 1, nr_io_queues); |
1685 | if (vecs < 0) { | |
1686 | vecs = pci_enable_msi_range(pdev, 1, min(nr_io_queues, 32)); | |
1687 | if (vecs < 0) { | |
1688 | vecs = 1; | |
1689 | } else { | |
1690 | for (i = 0; i < vecs; i++) | |
1691 | dev->entry[i].vector = i + pdev->irq; | |
fa08a396 RRG |
1692 | } |
1693 | } | |
1694 | ||
063a8096 MW |
1695 | /* |
1696 | * Should investigate if there's a performance win from allocating | |
1697 | * more queues than interrupt vectors; it might allow the submission | |
1698 | * path to scale better, even if the receive path is limited by the | |
1699 | * number of interrupts. | |
1700 | */ | |
1701 | nr_io_queues = vecs; | |
42f61420 | 1702 | dev->max_qid = nr_io_queues; |
063a8096 | 1703 | |
3193f07b | 1704 | result = queue_request_irq(dev, adminq, adminq->irqname); |
758dd7fd JD |
1705 | if (result) { |
1706 | adminq->cq_vector = -1; | |
22404274 | 1707 | goto free_queues; |
758dd7fd | 1708 | } |
1b23484b | 1709 | |
cd638946 | 1710 | /* Free previously allocated queues that are no longer usable */ |
42f61420 | 1711 | nvme_free_queues(dev, nr_io_queues + 1); |
749941f2 | 1712 | return nvme_create_io_queues(dev); |
b60503ba | 1713 | |
22404274 | 1714 | free_queues: |
a1a5ef99 | 1715 | nvme_free_queues(dev, 1); |
22404274 | 1716 | return result; |
b60503ba MW |
1717 | } |
1718 | ||
bda4e0fb KB |
1719 | static void nvme_set_irq_hints(struct nvme_dev *dev) |
1720 | { | |
1721 | struct nvme_queue *nvmeq; | |
1722 | int i; | |
1723 | ||
1724 | for (i = 0; i < dev->online_queues; i++) { | |
1725 | nvmeq = dev->queues[i]; | |
1726 | ||
1727 | if (!nvmeq->tags || !(*nvmeq->tags)) | |
1728 | continue; | |
1729 | ||
1730 | irq_set_affinity_hint(dev->entry[nvmeq->cq_vector].vector, | |
1731 | blk_mq_tags_cpumask(*nvmeq->tags)); | |
1732 | } | |
1733 | } | |
1734 | ||
a5768aa8 KB |
1735 | static void nvme_dev_scan(struct work_struct *work) |
1736 | { | |
1737 | struct nvme_dev *dev = container_of(work, struct nvme_dev, scan_work); | |
a5768aa8 KB |
1738 | |
1739 | if (!dev->tagset.tags) | |
1740 | return; | |
5bae7f73 | 1741 | nvme_scan_namespaces(&dev->ctrl); |
bda4e0fb | 1742 | nvme_set_irq_hints(dev); |
a5768aa8 KB |
1743 | } |
1744 | ||
422ef0c7 MW |
1745 | /* |
1746 | * Return: error value if an error occurred setting up the queues or calling | |
1747 | * Identify Device. 0 if these succeeded, even if adding some of the | |
1748 | * namespaces failed. At the moment, these failures are silent. TBD which | |
1749 | * failures should be reported. | |
1750 | */ | |
8d85fce7 | 1751 | static int nvme_dev_add(struct nvme_dev *dev) |
b60503ba | 1752 | { |
5bae7f73 | 1753 | if (!dev->ctrl.tagset) { |
ffe7704d KB |
1754 | dev->tagset.ops = &nvme_mq_ops; |
1755 | dev->tagset.nr_hw_queues = dev->online_queues - 1; | |
1756 | dev->tagset.timeout = NVME_IO_TIMEOUT; | |
1757 | dev->tagset.numa_node = dev_to_node(dev->dev); | |
1758 | dev->tagset.queue_depth = | |
a4aea562 | 1759 | min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1; |
ffe7704d KB |
1760 | dev->tagset.cmd_size = nvme_cmd_size(dev); |
1761 | dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE; | |
1762 | dev->tagset.driver_data = dev; | |
b60503ba | 1763 | |
ffe7704d KB |
1764 | if (blk_mq_alloc_tag_set(&dev->tagset)) |
1765 | return 0; | |
5bae7f73 | 1766 | dev->ctrl.tagset = &dev->tagset; |
ffe7704d | 1767 | } |
a5768aa8 | 1768 | schedule_work(&dev->scan_work); |
e1e5e564 | 1769 | return 0; |
b60503ba MW |
1770 | } |
1771 | ||
0877cb0d KB |
1772 | static int nvme_dev_map(struct nvme_dev *dev) |
1773 | { | |
42f61420 | 1774 | u64 cap; |
0877cb0d | 1775 | int bars, result = -ENOMEM; |
e75ec752 | 1776 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
0877cb0d KB |
1777 | |
1778 | if (pci_enable_device_mem(pdev)) | |
1779 | return result; | |
1780 | ||
1781 | dev->entry[0].vector = pdev->irq; | |
1782 | pci_set_master(pdev); | |
1783 | bars = pci_select_bars(pdev, IORESOURCE_MEM); | |
be7837e8 JA |
1784 | if (!bars) |
1785 | goto disable_pci; | |
1786 | ||
0877cb0d KB |
1787 | if (pci_request_selected_regions(pdev, bars, "nvme")) |
1788 | goto disable_pci; | |
1789 | ||
e75ec752 CH |
1790 | if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) && |
1791 | dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32))) | |
052d0efa | 1792 | goto disable; |
0877cb0d | 1793 | |
0877cb0d KB |
1794 | dev->bar = ioremap(pci_resource_start(pdev, 0), 8192); |
1795 | if (!dev->bar) | |
1796 | goto disable; | |
e32efbfc | 1797 | |
7a67cbea | 1798 | if (readl(dev->bar + NVME_REG_CSTS) == -1) { |
0e53d180 KB |
1799 | result = -ENODEV; |
1800 | goto unmap; | |
1801 | } | |
e32efbfc JA |
1802 | |
1803 | /* | |
1804 | * Some devices don't advertse INTx interrupts, pre-enable a single | |
1805 | * MSIX vec for setup. We'll adjust this later. | |
1806 | */ | |
1807 | if (!pdev->irq) { | |
1808 | result = pci_enable_msix(pdev, dev->entry, 1); | |
1809 | if (result < 0) | |
1810 | goto unmap; | |
1811 | } | |
1812 | ||
7a67cbea CH |
1813 | cap = lo_hi_readq(dev->bar + NVME_REG_CAP); |
1814 | ||
42f61420 KB |
1815 | dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH); |
1816 | dev->db_stride = 1 << NVME_CAP_STRIDE(cap); | |
7a67cbea CH |
1817 | dev->dbs = dev->bar + 4096; |
1818 | if (readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 2)) | |
8ffaadf7 | 1819 | dev->cmb = nvme_map_cmb(dev); |
0877cb0d KB |
1820 | |
1821 | return 0; | |
1822 | ||
0e53d180 KB |
1823 | unmap: |
1824 | iounmap(dev->bar); | |
1825 | dev->bar = NULL; | |
0877cb0d KB |
1826 | disable: |
1827 | pci_release_regions(pdev); | |
1828 | disable_pci: | |
1829 | pci_disable_device(pdev); | |
1830 | return result; | |
1831 | } | |
1832 | ||
1833 | static void nvme_dev_unmap(struct nvme_dev *dev) | |
1834 | { | |
e75ec752 CH |
1835 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
1836 | ||
1837 | if (pdev->msi_enabled) | |
1838 | pci_disable_msi(pdev); | |
1839 | else if (pdev->msix_enabled) | |
1840 | pci_disable_msix(pdev); | |
0877cb0d KB |
1841 | |
1842 | if (dev->bar) { | |
1843 | iounmap(dev->bar); | |
1844 | dev->bar = NULL; | |
e75ec752 | 1845 | pci_release_regions(pdev); |
0877cb0d KB |
1846 | } |
1847 | ||
e75ec752 CH |
1848 | if (pci_is_enabled(pdev)) |
1849 | pci_disable_device(pdev); | |
0877cb0d KB |
1850 | } |
1851 | ||
4d115420 KB |
1852 | struct nvme_delq_ctx { |
1853 | struct task_struct *waiter; | |
1854 | struct kthread_worker *worker; | |
1855 | atomic_t refcount; | |
1856 | }; | |
1857 | ||
1858 | static void nvme_wait_dq(struct nvme_delq_ctx *dq, struct nvme_dev *dev) | |
1859 | { | |
1860 | dq->waiter = current; | |
1861 | mb(); | |
1862 | ||
1863 | for (;;) { | |
1864 | set_current_state(TASK_KILLABLE); | |
1865 | if (!atomic_read(&dq->refcount)) | |
1866 | break; | |
1867 | if (!schedule_timeout(ADMIN_TIMEOUT) || | |
1868 | fatal_signal_pending(current)) { | |
0fb59cbc KB |
1869 | /* |
1870 | * Disable the controller first since we can't trust it | |
1871 | * at this point, but leave the admin queue enabled | |
1872 | * until all queue deletion requests are flushed. | |
1873 | * FIXME: This may take a while if there are more h/w | |
1874 | * queues than admin tags. | |
1875 | */ | |
4d115420 | 1876 | set_current_state(TASK_RUNNING); |
5fd4ce1b | 1877 | nvme_disable_ctrl(&dev->ctrl, |
7a67cbea | 1878 | lo_hi_readq(dev->bar + NVME_REG_CAP)); |
0fb59cbc | 1879 | nvme_clear_queue(dev->queues[0]); |
4d115420 | 1880 | flush_kthread_worker(dq->worker); |
0fb59cbc | 1881 | nvme_disable_queue(dev, 0); |
4d115420 KB |
1882 | return; |
1883 | } | |
1884 | } | |
1885 | set_current_state(TASK_RUNNING); | |
1886 | } | |
1887 | ||
1888 | static void nvme_put_dq(struct nvme_delq_ctx *dq) | |
1889 | { | |
1890 | atomic_dec(&dq->refcount); | |
1891 | if (dq->waiter) | |
1892 | wake_up_process(dq->waiter); | |
1893 | } | |
1894 | ||
1895 | static struct nvme_delq_ctx *nvme_get_dq(struct nvme_delq_ctx *dq) | |
1896 | { | |
1897 | atomic_inc(&dq->refcount); | |
1898 | return dq; | |
1899 | } | |
1900 | ||
1901 | static void nvme_del_queue_end(struct nvme_queue *nvmeq) | |
1902 | { | |
1903 | struct nvme_delq_ctx *dq = nvmeq->cmdinfo.ctx; | |
4d115420 | 1904 | nvme_put_dq(dq); |
604e8c8d KB |
1905 | |
1906 | spin_lock_irq(&nvmeq->q_lock); | |
1907 | nvme_process_cq(nvmeq); | |
1908 | spin_unlock_irq(&nvmeq->q_lock); | |
4d115420 KB |
1909 | } |
1910 | ||
1911 | static int adapter_async_del_queue(struct nvme_queue *nvmeq, u8 opcode, | |
1912 | kthread_work_func_t fn) | |
1913 | { | |
1914 | struct nvme_command c; | |
1915 | ||
1916 | memset(&c, 0, sizeof(c)); | |
1917 | c.delete_queue.opcode = opcode; | |
1918 | c.delete_queue.qid = cpu_to_le16(nvmeq->qid); | |
1919 | ||
1920 | init_kthread_work(&nvmeq->cmdinfo.work, fn); | |
a4aea562 MB |
1921 | return nvme_submit_admin_async_cmd(nvmeq->dev, &c, &nvmeq->cmdinfo, |
1922 | ADMIN_TIMEOUT); | |
4d115420 KB |
1923 | } |
1924 | ||
1925 | static void nvme_del_cq_work_handler(struct kthread_work *work) | |
1926 | { | |
1927 | struct nvme_queue *nvmeq = container_of(work, struct nvme_queue, | |
1928 | cmdinfo.work); | |
1929 | nvme_del_queue_end(nvmeq); | |
1930 | } | |
1931 | ||
1932 | static int nvme_delete_cq(struct nvme_queue *nvmeq) | |
1933 | { | |
1934 | return adapter_async_del_queue(nvmeq, nvme_admin_delete_cq, | |
1935 | nvme_del_cq_work_handler); | |
1936 | } | |
1937 | ||
1938 | static void nvme_del_sq_work_handler(struct kthread_work *work) | |
1939 | { | |
1940 | struct nvme_queue *nvmeq = container_of(work, struct nvme_queue, | |
1941 | cmdinfo.work); | |
1942 | int status = nvmeq->cmdinfo.status; | |
1943 | ||
1944 | if (!status) | |
1945 | status = nvme_delete_cq(nvmeq); | |
1946 | if (status) | |
1947 | nvme_del_queue_end(nvmeq); | |
1948 | } | |
1949 | ||
1950 | static int nvme_delete_sq(struct nvme_queue *nvmeq) | |
1951 | { | |
1952 | return adapter_async_del_queue(nvmeq, nvme_admin_delete_sq, | |
1953 | nvme_del_sq_work_handler); | |
1954 | } | |
1955 | ||
1956 | static void nvme_del_queue_start(struct kthread_work *work) | |
1957 | { | |
1958 | struct nvme_queue *nvmeq = container_of(work, struct nvme_queue, | |
1959 | cmdinfo.work); | |
4d115420 KB |
1960 | if (nvme_delete_sq(nvmeq)) |
1961 | nvme_del_queue_end(nvmeq); | |
1962 | } | |
1963 | ||
1964 | static void nvme_disable_io_queues(struct nvme_dev *dev) | |
1965 | { | |
1966 | int i; | |
1967 | DEFINE_KTHREAD_WORKER_ONSTACK(worker); | |
1968 | struct nvme_delq_ctx dq; | |
1969 | struct task_struct *kworker_task = kthread_run(kthread_worker_fn, | |
1c63dc66 | 1970 | &worker, "nvme%d", dev->ctrl.instance); |
4d115420 KB |
1971 | |
1972 | if (IS_ERR(kworker_task)) { | |
e75ec752 | 1973 | dev_err(dev->dev, |
4d115420 KB |
1974 | "Failed to create queue del task\n"); |
1975 | for (i = dev->queue_count - 1; i > 0; i--) | |
1976 | nvme_disable_queue(dev, i); | |
1977 | return; | |
1978 | } | |
1979 | ||
1980 | dq.waiter = NULL; | |
1981 | atomic_set(&dq.refcount, 0); | |
1982 | dq.worker = &worker; | |
1983 | for (i = dev->queue_count - 1; i > 0; i--) { | |
a4aea562 | 1984 | struct nvme_queue *nvmeq = dev->queues[i]; |
4d115420 KB |
1985 | |
1986 | if (nvme_suspend_queue(nvmeq)) | |
1987 | continue; | |
1988 | nvmeq->cmdinfo.ctx = nvme_get_dq(&dq); | |
1989 | nvmeq->cmdinfo.worker = dq.worker; | |
1990 | init_kthread_work(&nvmeq->cmdinfo.work, nvme_del_queue_start); | |
1991 | queue_kthread_work(dq.worker, &nvmeq->cmdinfo.work); | |
1992 | } | |
1993 | nvme_wait_dq(&dq, dev); | |
1994 | kthread_stop(kworker_task); | |
1995 | } | |
1996 | ||
7385014c CH |
1997 | static int nvme_dev_list_add(struct nvme_dev *dev) |
1998 | { | |
1999 | bool start_thread = false; | |
2000 | ||
2001 | spin_lock(&dev_list_lock); | |
2002 | if (list_empty(&dev_list) && IS_ERR_OR_NULL(nvme_thread)) { | |
2003 | start_thread = true; | |
2004 | nvme_thread = NULL; | |
2005 | } | |
2006 | list_add(&dev->node, &dev_list); | |
2007 | spin_unlock(&dev_list_lock); | |
2008 | ||
2009 | if (start_thread) { | |
2010 | nvme_thread = kthread_run(nvme_kthread, NULL, "nvme"); | |
2011 | wake_up_all(&nvme_kthread_wait); | |
2012 | } else | |
2013 | wait_event_killable(nvme_kthread_wait, nvme_thread); | |
2014 | ||
2015 | if (IS_ERR_OR_NULL(nvme_thread)) | |
2016 | return nvme_thread ? PTR_ERR(nvme_thread) : -EINTR; | |
2017 | ||
2018 | return 0; | |
2019 | } | |
2020 | ||
b9afca3e DM |
2021 | /* |
2022 | * Remove the node from the device list and check | |
2023 | * for whether or not we need to stop the nvme_thread. | |
2024 | */ | |
2025 | static void nvme_dev_list_remove(struct nvme_dev *dev) | |
2026 | { | |
2027 | struct task_struct *tmp = NULL; | |
2028 | ||
2029 | spin_lock(&dev_list_lock); | |
2030 | list_del_init(&dev->node); | |
2031 | if (list_empty(&dev_list) && !IS_ERR_OR_NULL(nvme_thread)) { | |
2032 | tmp = nvme_thread; | |
2033 | nvme_thread = NULL; | |
2034 | } | |
2035 | spin_unlock(&dev_list_lock); | |
2036 | ||
2037 | if (tmp) | |
2038 | kthread_stop(tmp); | |
2039 | } | |
2040 | ||
c9d3bf88 KB |
2041 | static void nvme_freeze_queues(struct nvme_dev *dev) |
2042 | { | |
2043 | struct nvme_ns *ns; | |
2044 | ||
5bae7f73 | 2045 | list_for_each_entry(ns, &dev->ctrl.namespaces, list) { |
c9d3bf88 KB |
2046 | blk_mq_freeze_queue_start(ns->queue); |
2047 | ||
cddcd72b | 2048 | spin_lock_irq(ns->queue->queue_lock); |
c9d3bf88 | 2049 | queue_flag_set(QUEUE_FLAG_STOPPED, ns->queue); |
cddcd72b | 2050 | spin_unlock_irq(ns->queue->queue_lock); |
c9d3bf88 KB |
2051 | |
2052 | blk_mq_cancel_requeue_work(ns->queue); | |
2053 | blk_mq_stop_hw_queues(ns->queue); | |
2054 | } | |
2055 | } | |
2056 | ||
2057 | static void nvme_unfreeze_queues(struct nvme_dev *dev) | |
2058 | { | |
2059 | struct nvme_ns *ns; | |
2060 | ||
5bae7f73 | 2061 | list_for_each_entry(ns, &dev->ctrl.namespaces, list) { |
c9d3bf88 KB |
2062 | queue_flag_clear_unlocked(QUEUE_FLAG_STOPPED, ns->queue); |
2063 | blk_mq_unfreeze_queue(ns->queue); | |
2064 | blk_mq_start_stopped_hw_queues(ns->queue, true); | |
2065 | blk_mq_kick_requeue_list(ns->queue); | |
2066 | } | |
2067 | } | |
2068 | ||
f0b50732 | 2069 | static void nvme_dev_shutdown(struct nvme_dev *dev) |
b60503ba | 2070 | { |
22404274 | 2071 | int i; |
7c1b2450 | 2072 | u32 csts = -1; |
22404274 | 2073 | |
b9afca3e | 2074 | nvme_dev_list_remove(dev); |
1fa6aead | 2075 | |
77bf25ea | 2076 | mutex_lock(&dev->shutdown_lock); |
c9d3bf88 KB |
2077 | if (dev->bar) { |
2078 | nvme_freeze_queues(dev); | |
7a67cbea | 2079 | csts = readl(dev->bar + NVME_REG_CSTS); |
c9d3bf88 | 2080 | } |
7c1b2450 | 2081 | if (csts & NVME_CSTS_CFS || !(csts & NVME_CSTS_RDY)) { |
4d115420 | 2082 | for (i = dev->queue_count - 1; i >= 0; i--) { |
a4aea562 | 2083 | struct nvme_queue *nvmeq = dev->queues[i]; |
4d115420 | 2084 | nvme_suspend_queue(nvmeq); |
4d115420 KB |
2085 | } |
2086 | } else { | |
2087 | nvme_disable_io_queues(dev); | |
5fd4ce1b | 2088 | nvme_shutdown_ctrl(&dev->ctrl); |
4d115420 KB |
2089 | nvme_disable_queue(dev, 0); |
2090 | } | |
f0b50732 | 2091 | nvme_dev_unmap(dev); |
07836e65 KB |
2092 | |
2093 | for (i = dev->queue_count - 1; i >= 0; i--) | |
2094 | nvme_clear_queue(dev->queues[i]); | |
77bf25ea | 2095 | mutex_unlock(&dev->shutdown_lock); |
f0b50732 KB |
2096 | } |
2097 | ||
091b6092 MW |
2098 | static int nvme_setup_prp_pools(struct nvme_dev *dev) |
2099 | { | |
e75ec752 | 2100 | dev->prp_page_pool = dma_pool_create("prp list page", dev->dev, |
091b6092 MW |
2101 | PAGE_SIZE, PAGE_SIZE, 0); |
2102 | if (!dev->prp_page_pool) | |
2103 | return -ENOMEM; | |
2104 | ||
99802a7a | 2105 | /* Optimisation for I/Os between 4k and 128k */ |
e75ec752 | 2106 | dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev, |
99802a7a MW |
2107 | 256, 256, 0); |
2108 | if (!dev->prp_small_pool) { | |
2109 | dma_pool_destroy(dev->prp_page_pool); | |
2110 | return -ENOMEM; | |
2111 | } | |
091b6092 MW |
2112 | return 0; |
2113 | } | |
2114 | ||
2115 | static void nvme_release_prp_pools(struct nvme_dev *dev) | |
2116 | { | |
2117 | dma_pool_destroy(dev->prp_page_pool); | |
99802a7a | 2118 | dma_pool_destroy(dev->prp_small_pool); |
091b6092 MW |
2119 | } |
2120 | ||
1673f1f0 | 2121 | static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl) |
5e82e952 | 2122 | { |
1673f1f0 | 2123 | struct nvme_dev *dev = to_nvme_dev(ctrl); |
9ac27090 | 2124 | |
e75ec752 | 2125 | put_device(dev->dev); |
4af0e21c KB |
2126 | if (dev->tagset.tags) |
2127 | blk_mq_free_tag_set(&dev->tagset); | |
1c63dc66 CH |
2128 | if (dev->ctrl.admin_q) |
2129 | blk_put_queue(dev->ctrl.admin_q); | |
5e82e952 KB |
2130 | kfree(dev->queues); |
2131 | kfree(dev->entry); | |
2132 | kfree(dev); | |
2133 | } | |
2134 | ||
3cf519b5 | 2135 | static void nvme_probe_work(struct work_struct *work) |
f0b50732 | 2136 | { |
3cf519b5 | 2137 | struct nvme_dev *dev = container_of(work, struct nvme_dev, probe_work); |
3cf519b5 | 2138 | int result; |
f0b50732 KB |
2139 | |
2140 | result = nvme_dev_map(dev); | |
2141 | if (result) | |
3cf519b5 | 2142 | goto out; |
f0b50732 KB |
2143 | |
2144 | result = nvme_configure_admin_queue(dev); | |
2145 | if (result) | |
2146 | goto unmap; | |
2147 | ||
a4aea562 | 2148 | nvme_init_queue(dev->queues[0], 0); |
0fb59cbc KB |
2149 | result = nvme_alloc_admin_tags(dev); |
2150 | if (result) | |
2151 | goto disable; | |
b9afca3e | 2152 | |
ce4541f4 CH |
2153 | result = nvme_init_identify(&dev->ctrl); |
2154 | if (result) | |
2155 | goto free_tags; | |
2156 | ||
f0b50732 | 2157 | result = nvme_setup_io_queues(dev); |
badc34d4 | 2158 | if (result) |
0fb59cbc | 2159 | goto free_tags; |
f0b50732 | 2160 | |
1c63dc66 | 2161 | dev->ctrl.event_limit = 1; |
3cf519b5 | 2162 | |
7385014c CH |
2163 | result = nvme_dev_list_add(dev); |
2164 | if (result) | |
2165 | goto remove; | |
2166 | ||
2659e57b CH |
2167 | /* |
2168 | * Keep the controller around but remove all namespaces if we don't have | |
2169 | * any working I/O queue. | |
2170 | */ | |
3cf519b5 CH |
2171 | if (dev->online_queues < 2) { |
2172 | dev_warn(dev->dev, "IO queues not created\n"); | |
5bae7f73 | 2173 | nvme_remove_namespaces(&dev->ctrl); |
3cf519b5 CH |
2174 | } else { |
2175 | nvme_unfreeze_queues(dev); | |
2176 | nvme_dev_add(dev); | |
2177 | } | |
2178 | ||
2179 | return; | |
f0b50732 | 2180 | |
7385014c CH |
2181 | remove: |
2182 | nvme_dev_list_remove(dev); | |
0fb59cbc KB |
2183 | free_tags: |
2184 | nvme_dev_remove_admin(dev); | |
1c63dc66 CH |
2185 | blk_put_queue(dev->ctrl.admin_q); |
2186 | dev->ctrl.admin_q = NULL; | |
4af0e21c | 2187 | dev->queues[0]->tags = NULL; |
f0b50732 | 2188 | disable: |
a1a5ef99 | 2189 | nvme_disable_queue(dev, 0); |
f0b50732 KB |
2190 | unmap: |
2191 | nvme_dev_unmap(dev); | |
3cf519b5 CH |
2192 | out: |
2193 | if (!work_busy(&dev->reset_work)) | |
2194 | nvme_dead_ctrl(dev); | |
f0b50732 KB |
2195 | } |
2196 | ||
9a6b9458 KB |
2197 | static int nvme_remove_dead_ctrl(void *arg) |
2198 | { | |
2199 | struct nvme_dev *dev = (struct nvme_dev *)arg; | |
e75ec752 | 2200 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
9a6b9458 KB |
2201 | |
2202 | if (pci_get_drvdata(pdev)) | |
c81f4975 | 2203 | pci_stop_and_remove_bus_device_locked(pdev); |
1673f1f0 | 2204 | nvme_put_ctrl(&dev->ctrl); |
9a6b9458 KB |
2205 | return 0; |
2206 | } | |
2207 | ||
de3eff2b KB |
2208 | static void nvme_dead_ctrl(struct nvme_dev *dev) |
2209 | { | |
2210 | dev_warn(dev->dev, "Device failed to resume\n"); | |
1673f1f0 | 2211 | kref_get(&dev->ctrl.kref); |
de3eff2b | 2212 | if (IS_ERR(kthread_run(nvme_remove_dead_ctrl, dev, "nvme%d", |
1c63dc66 | 2213 | dev->ctrl.instance))) { |
de3eff2b KB |
2214 | dev_err(dev->dev, |
2215 | "Failed to start controller remove task\n"); | |
1673f1f0 | 2216 | nvme_put_ctrl(&dev->ctrl); |
de3eff2b KB |
2217 | } |
2218 | } | |
2219 | ||
77b50d9e | 2220 | static void nvme_reset_work(struct work_struct *ws) |
9a6b9458 | 2221 | { |
77b50d9e | 2222 | struct nvme_dev *dev = container_of(ws, struct nvme_dev, reset_work); |
ffe7704d KB |
2223 | bool in_probe = work_busy(&dev->probe_work); |
2224 | ||
9a6b9458 | 2225 | nvme_dev_shutdown(dev); |
ffe7704d KB |
2226 | |
2227 | /* Synchronize with device probe so that work will see failure status | |
2228 | * and exit gracefully without trying to schedule another reset */ | |
2229 | flush_work(&dev->probe_work); | |
2230 | ||
2231 | /* Fail this device if reset occured during probe to avoid | |
2232 | * infinite initialization loops. */ | |
2233 | if (in_probe) { | |
de3eff2b | 2234 | nvme_dead_ctrl(dev); |
ffe7704d | 2235 | return; |
9a6b9458 | 2236 | } |
ffe7704d KB |
2237 | /* Schedule device resume asynchronously so the reset work is available |
2238 | * to cleanup errors that may occur during reinitialization */ | |
2239 | schedule_work(&dev->probe_work); | |
9a6b9458 KB |
2240 | } |
2241 | ||
90667892 | 2242 | static int __nvme_reset(struct nvme_dev *dev) |
9ca97374 | 2243 | { |
90667892 CH |
2244 | if (work_pending(&dev->reset_work)) |
2245 | return -EBUSY; | |
2246 | list_del_init(&dev->node); | |
2247 | queue_work(nvme_workq, &dev->reset_work); | |
2248 | return 0; | |
9ca97374 TH |
2249 | } |
2250 | ||
4cc06521 KB |
2251 | static int nvme_reset(struct nvme_dev *dev) |
2252 | { | |
90667892 | 2253 | int ret; |
4cc06521 | 2254 | |
1c63dc66 | 2255 | if (!dev->ctrl.admin_q || blk_queue_dying(dev->ctrl.admin_q)) |
4cc06521 KB |
2256 | return -ENODEV; |
2257 | ||
2258 | spin_lock(&dev_list_lock); | |
90667892 | 2259 | ret = __nvme_reset(dev); |
4cc06521 KB |
2260 | spin_unlock(&dev_list_lock); |
2261 | ||
2262 | if (!ret) { | |
2263 | flush_work(&dev->reset_work); | |
ffe7704d | 2264 | flush_work(&dev->probe_work); |
4cc06521 KB |
2265 | return 0; |
2266 | } | |
2267 | ||
2268 | return ret; | |
2269 | } | |
2270 | ||
1c63dc66 CH |
2271 | static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val) |
2272 | { | |
2273 | *val = readl(to_nvme_dev(ctrl)->bar + off); | |
2274 | return 0; | |
2275 | } | |
2276 | ||
5fd4ce1b CH |
2277 | static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val) |
2278 | { | |
2279 | writel(val, to_nvme_dev(ctrl)->bar + off); | |
2280 | return 0; | |
2281 | } | |
2282 | ||
7fd8930f CH |
2283 | static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val) |
2284 | { | |
2285 | *val = readq(to_nvme_dev(ctrl)->bar + off); | |
2286 | return 0; | |
2287 | } | |
2288 | ||
5bae7f73 CH |
2289 | static bool nvme_pci_io_incapable(struct nvme_ctrl *ctrl) |
2290 | { | |
2291 | struct nvme_dev *dev = to_nvme_dev(ctrl); | |
2292 | ||
2293 | return !dev->bar || dev->online_queues < 2; | |
2294 | } | |
2295 | ||
f3ca80fc CH |
2296 | static int nvme_pci_reset_ctrl(struct nvme_ctrl *ctrl) |
2297 | { | |
2298 | return nvme_reset(to_nvme_dev(ctrl)); | |
2299 | } | |
2300 | ||
1c63dc66 CH |
2301 | static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = { |
2302 | .reg_read32 = nvme_pci_reg_read32, | |
5fd4ce1b | 2303 | .reg_write32 = nvme_pci_reg_write32, |
7fd8930f | 2304 | .reg_read64 = nvme_pci_reg_read64, |
5bae7f73 | 2305 | .io_incapable = nvme_pci_io_incapable, |
f3ca80fc | 2306 | .reset_ctrl = nvme_pci_reset_ctrl, |
1673f1f0 | 2307 | .free_ctrl = nvme_pci_free_ctrl, |
1c63dc66 CH |
2308 | }; |
2309 | ||
8d85fce7 | 2310 | static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) |
b60503ba | 2311 | { |
a4aea562 | 2312 | int node, result = -ENOMEM; |
b60503ba MW |
2313 | struct nvme_dev *dev; |
2314 | ||
a4aea562 MB |
2315 | node = dev_to_node(&pdev->dev); |
2316 | if (node == NUMA_NO_NODE) | |
2317 | set_dev_node(&pdev->dev, 0); | |
2318 | ||
2319 | dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); | |
b60503ba MW |
2320 | if (!dev) |
2321 | return -ENOMEM; | |
a4aea562 MB |
2322 | dev->entry = kzalloc_node(num_possible_cpus() * sizeof(*dev->entry), |
2323 | GFP_KERNEL, node); | |
b60503ba MW |
2324 | if (!dev->entry) |
2325 | goto free; | |
a4aea562 MB |
2326 | dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *), |
2327 | GFP_KERNEL, node); | |
b60503ba MW |
2328 | if (!dev->queues) |
2329 | goto free; | |
2330 | ||
e75ec752 | 2331 | dev->dev = get_device(&pdev->dev); |
9a6b9458 | 2332 | pci_set_drvdata(pdev, dev); |
1c63dc66 | 2333 | |
f3ca80fc CH |
2334 | INIT_LIST_HEAD(&dev->node); |
2335 | INIT_WORK(&dev->scan_work, nvme_dev_scan); | |
2336 | INIT_WORK(&dev->probe_work, nvme_probe_work); | |
2337 | INIT_WORK(&dev->reset_work, nvme_reset_work); | |
77bf25ea | 2338 | mutex_init(&dev->shutdown_lock); |
1c63dc66 | 2339 | |
f3ca80fc | 2340 | result = nvme_setup_prp_pools(dev); |
cd58ad7d | 2341 | if (result) |
a96d4f5c | 2342 | goto put_pci; |
b60503ba | 2343 | |
f3ca80fc CH |
2344 | result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops, |
2345 | id->driver_data); | |
091b6092 | 2346 | if (result) |
2e1d8448 | 2347 | goto release_pools; |
740216fc | 2348 | |
2e1d8448 | 2349 | schedule_work(&dev->probe_work); |
b60503ba MW |
2350 | return 0; |
2351 | ||
0877cb0d | 2352 | release_pools: |
091b6092 | 2353 | nvme_release_prp_pools(dev); |
a96d4f5c | 2354 | put_pci: |
e75ec752 | 2355 | put_device(dev->dev); |
b60503ba MW |
2356 | free: |
2357 | kfree(dev->queues); | |
2358 | kfree(dev->entry); | |
2359 | kfree(dev); | |
2360 | return result; | |
2361 | } | |
2362 | ||
f0d54a54 KB |
2363 | static void nvme_reset_notify(struct pci_dev *pdev, bool prepare) |
2364 | { | |
a6739479 | 2365 | struct nvme_dev *dev = pci_get_drvdata(pdev); |
f0d54a54 | 2366 | |
a6739479 KB |
2367 | if (prepare) |
2368 | nvme_dev_shutdown(dev); | |
2369 | else | |
0a7385ad | 2370 | schedule_work(&dev->probe_work); |
f0d54a54 KB |
2371 | } |
2372 | ||
09ece142 KB |
2373 | static void nvme_shutdown(struct pci_dev *pdev) |
2374 | { | |
2375 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
2376 | nvme_dev_shutdown(dev); | |
2377 | } | |
2378 | ||
8d85fce7 | 2379 | static void nvme_remove(struct pci_dev *pdev) |
b60503ba MW |
2380 | { |
2381 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
9a6b9458 KB |
2382 | |
2383 | spin_lock(&dev_list_lock); | |
2384 | list_del_init(&dev->node); | |
2385 | spin_unlock(&dev_list_lock); | |
2386 | ||
2387 | pci_set_drvdata(pdev, NULL); | |
2e1d8448 | 2388 | flush_work(&dev->probe_work); |
9a6b9458 | 2389 | flush_work(&dev->reset_work); |
a5768aa8 | 2390 | flush_work(&dev->scan_work); |
5bae7f73 | 2391 | nvme_remove_namespaces(&dev->ctrl); |
3399a3f7 | 2392 | nvme_dev_shutdown(dev); |
a4aea562 | 2393 | nvme_dev_remove_admin(dev); |
a1a5ef99 | 2394 | nvme_free_queues(dev, 0); |
8ffaadf7 | 2395 | nvme_release_cmb(dev); |
9a6b9458 | 2396 | nvme_release_prp_pools(dev); |
1673f1f0 | 2397 | nvme_put_ctrl(&dev->ctrl); |
b60503ba MW |
2398 | } |
2399 | ||
2400 | /* These functions are yet to be implemented */ | |
2401 | #define nvme_error_detected NULL | |
2402 | #define nvme_dump_registers NULL | |
2403 | #define nvme_link_reset NULL | |
2404 | #define nvme_slot_reset NULL | |
2405 | #define nvme_error_resume NULL | |
cd638946 | 2406 | |
671a6018 | 2407 | #ifdef CONFIG_PM_SLEEP |
cd638946 KB |
2408 | static int nvme_suspend(struct device *dev) |
2409 | { | |
2410 | struct pci_dev *pdev = to_pci_dev(dev); | |
2411 | struct nvme_dev *ndev = pci_get_drvdata(pdev); | |
2412 | ||
2413 | nvme_dev_shutdown(ndev); | |
2414 | return 0; | |
2415 | } | |
2416 | ||
2417 | static int nvme_resume(struct device *dev) | |
2418 | { | |
2419 | struct pci_dev *pdev = to_pci_dev(dev); | |
2420 | struct nvme_dev *ndev = pci_get_drvdata(pdev); | |
cd638946 | 2421 | |
0a7385ad | 2422 | schedule_work(&ndev->probe_work); |
9a6b9458 | 2423 | return 0; |
cd638946 | 2424 | } |
671a6018 | 2425 | #endif |
cd638946 KB |
2426 | |
2427 | static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume); | |
b60503ba | 2428 | |
1d352035 | 2429 | static const struct pci_error_handlers nvme_err_handler = { |
b60503ba MW |
2430 | .error_detected = nvme_error_detected, |
2431 | .mmio_enabled = nvme_dump_registers, | |
2432 | .link_reset = nvme_link_reset, | |
2433 | .slot_reset = nvme_slot_reset, | |
2434 | .resume = nvme_error_resume, | |
f0d54a54 | 2435 | .reset_notify = nvme_reset_notify, |
b60503ba MW |
2436 | }; |
2437 | ||
2438 | /* Move to pci_ids.h later */ | |
2439 | #define PCI_CLASS_STORAGE_EXPRESS 0x010802 | |
2440 | ||
6eb0d698 | 2441 | static const struct pci_device_id nvme_id_table[] = { |
106198ed CH |
2442 | { PCI_VDEVICE(INTEL, 0x0953), |
2443 | .driver_data = NVME_QUIRK_STRIPE_SIZE, }, | |
b60503ba | 2444 | { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, |
c74dc780 | 2445 | { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) }, |
b60503ba MW |
2446 | { 0, } |
2447 | }; | |
2448 | MODULE_DEVICE_TABLE(pci, nvme_id_table); | |
2449 | ||
2450 | static struct pci_driver nvme_driver = { | |
2451 | .name = "nvme", | |
2452 | .id_table = nvme_id_table, | |
2453 | .probe = nvme_probe, | |
8d85fce7 | 2454 | .remove = nvme_remove, |
09ece142 | 2455 | .shutdown = nvme_shutdown, |
cd638946 KB |
2456 | .driver = { |
2457 | .pm = &nvme_dev_pm_ops, | |
2458 | }, | |
b60503ba MW |
2459 | .err_handler = &nvme_err_handler, |
2460 | }; | |
2461 | ||
2462 | static int __init nvme_init(void) | |
2463 | { | |
0ac13140 | 2464 | int result; |
1fa6aead | 2465 | |
b9afca3e | 2466 | init_waitqueue_head(&nvme_kthread_wait); |
b60503ba | 2467 | |
9a6b9458 KB |
2468 | nvme_workq = create_singlethread_workqueue("nvme"); |
2469 | if (!nvme_workq) | |
b9afca3e | 2470 | return -ENOMEM; |
9a6b9458 | 2471 | |
5bae7f73 | 2472 | result = nvme_core_init(); |
5c42ea16 | 2473 | if (result < 0) |
9a6b9458 | 2474 | goto kill_workq; |
b60503ba | 2475 | |
f3db22fe KB |
2476 | result = pci_register_driver(&nvme_driver); |
2477 | if (result) | |
f3ca80fc | 2478 | goto core_exit; |
1fa6aead | 2479 | return 0; |
b60503ba | 2480 | |
f3ca80fc | 2481 | core_exit: |
5bae7f73 | 2482 | nvme_core_exit(); |
9a6b9458 KB |
2483 | kill_workq: |
2484 | destroy_workqueue(nvme_workq); | |
b60503ba MW |
2485 | return result; |
2486 | } | |
2487 | ||
2488 | static void __exit nvme_exit(void) | |
2489 | { | |
2490 | pci_unregister_driver(&nvme_driver); | |
5bae7f73 | 2491 | nvme_core_exit(); |
9a6b9458 | 2492 | destroy_workqueue(nvme_workq); |
b9afca3e | 2493 | BUG_ON(nvme_thread && !IS_ERR(nvme_thread)); |
21bd78bc | 2494 | _nvme_check_size(); |
b60503ba MW |
2495 | } |
2496 | ||
2497 | MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); | |
2498 | MODULE_LICENSE("GPL"); | |
c78b4713 | 2499 | MODULE_VERSION("1.0"); |
b60503ba MW |
2500 | module_init(nvme_init); |
2501 | module_exit(nvme_exit); |