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block: enable batched allocation for blk_mq_alloc_request()
[linux-2.6-block.git] / drivers / nvme / host / pci.c
CommitLineData
5f37396d 1// SPDX-License-Identifier: GPL-2.0
b60503ba
MW		 2/*
3 * NVM Express device driver
6eb0d698 4 * Copyright (c) 2011-2014, Intel Corporation.
b60503ba
MW		 5 */
6
df4f9bc4 7#include <linux/acpi.h>
a0a3408e 8#include <linux/aer.h>
18119775 9#include <linux/async.h>
b60503ba 10#include <linux/blkdev.h>
a4aea562 11#include <linux/blk-mq.h>
dca51e78 12#include <linux/blk-mq-pci.h>
fe45e630 13#include <linux/blk-integrity.h>
ff5350a8 14#include <linux/dmi.h>
b60503ba
MW		 15#include <linux/init.h>
16#include <linux/interrupt.h>
17#include <linux/io.h>
dc90f084 18#include <linux/memremap.h>
b60503ba
MW		 19#include <linux/mm.h>
20#include <linux/module.h>
77bf25ea 21#include <linux/mutex.h>
d0877473 22#include <linux/once.h>
b60503ba 23#include <linux/pci.h>
d916b1be 24#include <linux/suspend.h>
e1e5e564 25#include <linux/t10-pi.h>
b60503ba 26#include <linux/types.h>
2f8e2c87 27#include <linux/io-64-nonatomic-lo-hi.h>
20d3bb92 28#include <linux/io-64-nonatomic-hi-lo.h>
a98e58e5 29#include <linux/sed-opal.h>
0f238ff5 30#include <linux/pci-p2pdma.h>
797a796a 31
604c01d5 32#include "trace.h"
f11bb3e2
CH		 33#include "nvme.h"
34
c1e0cc7e 35#define SQ_SIZE(q) ((q)->q_depth << (q)->sqes)
8a1d09a6 36#define CQ_SIZE(q) ((q)->q_depth * sizeof(struct nvme_completion))
c965809c 37
a7a7cbe3 38#define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc))
9d43cf64 39
943e942e
JA		 40/*
41 * These can be higher, but we need to ensure that any command doesn't
42 * require an sg allocation that needs more than a page of data.
43 */
44#define NVME_MAX_KB_SZ 4096
45#define NVME_MAX_SEGS 127
46
58ffacb5 47static int use_threaded_interrupts;
2e21e445 48module_param(use_threaded_interrupts, int, 0444);
58ffacb5 49
8ffaadf7 50static bool use_cmb_sqes = true;
69f4eb9f 51module_param(use_cmb_sqes, bool, 0444);
8ffaadf7
JD		 52MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
53
87ad72a5
CH		 54static unsigned int max_host_mem_size_mb = 128;
55module_param(max_host_mem_size_mb, uint, 0444);
56MODULE_PARM_DESC(max_host_mem_size_mb,
57 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
1fa6aead 58
a7a7cbe3
CK		 59static unsigned int sgl_threshold = SZ_32K;
60module_param(sgl_threshold, uint, 0644);
61MODULE_PARM_DESC(sgl_threshold,
62 "Use SGLs when average request segment size is larger or equal to "
63 "this size. Use 0 to disable SGLs.");
64
27453b45
SG		 65#define NVME_PCI_MIN_QUEUE_SIZE 2
66#define NVME_PCI_MAX_QUEUE_SIZE 4095
b27c1e68 67static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
68static const struct kernel_param_ops io_queue_depth_ops = {
69 .set = io_queue_depth_set,
61f3b896 70 .get = param_get_uint,
b27c1e68 71};
72
61f3b896 73static unsigned int io_queue_depth = 1024;
b27c1e68 74module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
27453b45 75MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2 and < 4096");
b27c1e68 76
9c9e76d5
WZ		 77static int io_queue_count_set(const char *val, const struct kernel_param *kp)
78{
79 unsigned int n;
80 int ret;
81
82 ret = kstrtouint(val, 10, &n);
83 if (ret != 0 || n > num_possible_cpus())
84 return -EINVAL;
85 return param_set_uint(val, kp);
86}
87
88static const struct kernel_param_ops io_queue_count_ops = {
89 .set = io_queue_count_set,
90 .get = param_get_uint,
91};
92
3f68baf7 93static unsigned int write_queues;
9c9e76d5 94module_param_cb(write_queues, &io_queue_count_ops, &write_queues, 0644);
3b6592f7
JA		 95MODULE_PARM_DESC(write_queues,
96 "Number of queues to use for writes. If not set, reads and writes "
97 "will share a queue set.");
98
3f68baf7 99static unsigned int poll_queues;
9c9e76d5 100module_param_cb(poll_queues, &io_queue_count_ops, &poll_queues, 0644);
4b04cc6a
JA		 101MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO.");
102
df4f9bc4
DB		 103static bool noacpi;
104module_param(noacpi, bool, 0444);
105MODULE_PARM_DESC(noacpi, "disable acpi bios quirks");
106
1c63dc66
CH		 107struct nvme_dev;
108struct nvme_queue;
b3fffdef 109
a5cdb68c 110static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
8fae268b 111static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode);
d4b4ff8e 112
1c63dc66
CH		 113/*
114 * Represents an NVM Express device. Each nvme_dev is a PCI function.
115 */
116struct nvme_dev {
147b27e4 117 struct nvme_queue *queues;
1c63dc66
CH		 118 struct blk_mq_tag_set tagset;
119 struct blk_mq_tag_set admin_tagset;
120 u32 __iomem *dbs;
121 struct device *dev;
122 struct dma_pool *prp_page_pool;
123 struct dma_pool *prp_small_pool;
1c63dc66
CH		 124 unsigned online_queues;
125 unsigned max_qid;
e20ba6e1 126 unsigned io_queues[HCTX_MAX_TYPES];
22b55601 127 unsigned int num_vecs;
7442ddce 128 u32 q_depth;
c1e0cc7e 129 int io_sqes;
1c63dc66 130 u32 db_stride;
1c63dc66 131 void __iomem *bar;
97f6ef64 132 unsigned long bar_mapped_size;
5c8809e6 133 struct work_struct remove_work;
77bf25ea 134 struct mutex shutdown_lock;
1c63dc66 135 bool subsystem;
1c63dc66 136 u64 cmb_size;
0f238ff5 137 bool cmb_use_sqes;
1c63dc66 138 u32 cmbsz;
202021c1 139 u32 cmbloc;
1c63dc66 140 struct nvme_ctrl ctrl;
d916b1be 141 u32 last_ps;
a5df5e79 142 bool hmb;
87ad72a5 143
943e942e
JA		 144 mempool_t *iod_mempool;
145
87ad72a5 146 /* shadow doorbell buffer support: */
f9f38e33
HK		 147 u32 *dbbuf_dbs;
148 dma_addr_t dbbuf_dbs_dma_addr;
149 u32 *dbbuf_eis;
150 dma_addr_t dbbuf_eis_dma_addr;
87ad72a5
CH		 151
152 /* host memory buffer support: */
153 u64 host_mem_size;
154 u32 nr_host_mem_descs;
4033f35d 155 dma_addr_t host_mem_descs_dma;
87ad72a5
CH		 156 struct nvme_host_mem_buf_desc *host_mem_descs;
157 void **host_mem_desc_bufs;
2a5bcfdd
WZ		 158 unsigned int nr_allocated_queues;
159 unsigned int nr_write_queues;
160 unsigned int nr_poll_queues;
0521905e
KB		 161
162 bool attrs_added;
4d115420 163};
1fa6aead 164
b27c1e68 165static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
166{
27453b45
SG		 167 return param_set_uint_minmax(val, kp, NVME_PCI_MIN_QUEUE_SIZE,
168 NVME_PCI_MAX_QUEUE_SIZE);
b27c1e68 169}
170
f9f38e33
HK		 171static inline unsigned int sq_idx(unsigned int qid, u32 stride)
172{
173 return qid * 2 * stride;
174}
175
176static inline unsigned int cq_idx(unsigned int qid, u32 stride)
177{
178 return (qid * 2 + 1) * stride;
179}
180
1c63dc66
CH		 181static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
182{
183 return container_of(ctrl, struct nvme_dev, ctrl);
184}
185
b60503ba
MW		 186/*
187 * An NVM Express queue. Each device has at least two (one for admin
188 * commands and one for I/O commands).
189 */
190struct nvme_queue {
091b6092 191 struct nvme_dev *dev;
1ab0cd69 192 spinlock_t sq_lock;
c1e0cc7e 193 void *sq_cmds;
3a7afd8e
CH		 194 /* only used for poll queues: */
195 spinlock_t cq_poll_lock ____cacheline_aligned_in_smp;
74943d45 196 struct nvme_completion *cqes;
b60503ba
MW		 197 dma_addr_t sq_dma_addr;
198 dma_addr_t cq_dma_addr;
b60503ba 199 u32 __iomem *q_db;
7442ddce 200 u32 q_depth;
7c349dde 201 u16 cq_vector;
b60503ba 202 u16 sq_tail;
38210800 203 u16 last_sq_tail;
b60503ba 204 u16 cq_head;
c30341dc 205 u16 qid;
e9539f47 206 u8 cq_phase;
c1e0cc7e 207 u8 sqes;
4e224106
CH		 208 unsigned long flags;
209#define NVMEQ_ENABLED 0
63223078 210#define NVMEQ_SQ_CMB 1
d1ed6aa1 211#define NVMEQ_DELETE_ERROR 2
7c349dde 212#define NVMEQ_POLLED 3
f9f38e33
HK		 213 u32 *dbbuf_sq_db;
214 u32 *dbbuf_cq_db;
215 u32 *dbbuf_sq_ei;
216 u32 *dbbuf_cq_ei;
d1ed6aa1 217 struct completion delete_done;
b60503ba
MW		 218};
219
71bd150c 220/*
9b048119
CH		 221 * The nvme_iod describes the data in an I/O.
222 *
223 * The sg pointer contains the list of PRP/SGL chunk allocations in addition
224 * to the actual struct scatterlist.
71bd150c
CH		 225 */
226struct nvme_iod {
d49187e9 227 struct nvme_request req;
af7fae85 228 struct nvme_command cmd;
a7a7cbe3 229 bool use_sgl;
52da4f3f 230 bool aborted;
c372cdd1
KB		 231 s8 nr_allocations; /* PRP list pool allocations. 0 means small
232 pool in use */
dff824b2 233 unsigned int dma_len; /* length of single DMA segment mapping */
c4c22c52 234 dma_addr_t first_dma;
783b94bd 235 dma_addr_t meta_dma;
91fb2b60 236 struct sg_table sgt;
b60503ba
MW		 237};
238
2a5bcfdd 239static inline unsigned int nvme_dbbuf_size(struct nvme_dev *dev)
3b6592f7 240{
2a5bcfdd 241 return dev->nr_allocated_queues * 8 * dev->db_stride;
f9f38e33
HK		 242}
243
244static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
245{
2a5bcfdd 246 unsigned int mem_size = nvme_dbbuf_size(dev);
f9f38e33 247
58847f12
KB		 248 if (dev->dbbuf_dbs) {
249 /*
250 * Clear the dbbuf memory so the driver doesn't observe stale
251 * values from the previous instantiation.
252 */
253 memset(dev->dbbuf_dbs, 0, mem_size);
254 memset(dev->dbbuf_eis, 0, mem_size);
f9f38e33 255 return 0;
58847f12 256 }
f9f38e33
HK		 257
258 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
259 &dev->dbbuf_dbs_dma_addr,
260 GFP_KERNEL);
261 if (!dev->dbbuf_dbs)
262 return -ENOMEM;
263 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
264 &dev->dbbuf_eis_dma_addr,
265 GFP_KERNEL);
266 if (!dev->dbbuf_eis) {
267 dma_free_coherent(dev->dev, mem_size,
268 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
269 dev->dbbuf_dbs = NULL;
270 return -ENOMEM;
271 }
272
273 return 0;
274}
275
276static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
277{
2a5bcfdd 278 unsigned int mem_size = nvme_dbbuf_size(dev);
f9f38e33
HK		 279
280 if (dev->dbbuf_dbs) {
281 dma_free_coherent(dev->dev, mem_size,
282 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
283 dev->dbbuf_dbs = NULL;
284 }
285 if (dev->dbbuf_eis) {
286 dma_free_coherent(dev->dev, mem_size,
287 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
288 dev->dbbuf_eis = NULL;
289 }
290}
291
292static void nvme_dbbuf_init(struct nvme_dev *dev,
293 struct nvme_queue *nvmeq, int qid)
294{
295 if (!dev->dbbuf_dbs || !qid)
296 return;
297
298 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
299 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
300 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
301 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
302}
303
0f0d2c87
MI		 304static void nvme_dbbuf_free(struct nvme_queue *nvmeq)
305{
306 if (!nvmeq->qid)
307 return;
308
309 nvmeq->dbbuf_sq_db = NULL;
310 nvmeq->dbbuf_cq_db = NULL;
311 nvmeq->dbbuf_sq_ei = NULL;
312 nvmeq->dbbuf_cq_ei = NULL;
313}
314
f9f38e33
HK		 315static void nvme_dbbuf_set(struct nvme_dev *dev)
316{
f66e2804 317 struct nvme_command c = { };
0f0d2c87 318 unsigned int i;
f9f38e33
HK		 319
320 if (!dev->dbbuf_dbs)
321 return;
322
f9f38e33
HK		 323 c.dbbuf.opcode = nvme_admin_dbbuf;
324 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
325 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
326
327 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
9bdcfb10 328 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
f9f38e33
HK		 329 /* Free memory and continue on */
330 nvme_dbbuf_dma_free(dev);
0f0d2c87
MI		 331
332 for (i = 1; i <= dev->online_queues; i++)
333 nvme_dbbuf_free(&dev->queues[i]);
f9f38e33
HK		 334 }
335}
336
337static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
338{
339 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
340}
341
342/* Update dbbuf and return true if an MMIO is required */
343static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
344 volatile u32 *dbbuf_ei)
345{
346 if (dbbuf_db) {
347 u16 old_value;
348
349 /*
350 * Ensure that the queue is written before updating
351 * the doorbell in memory
352 */
353 wmb();
354
355 old_value = *dbbuf_db;
356 *dbbuf_db = value;
357
f1ed3df2
MW		 358 /*
359 * Ensure that the doorbell is updated before reading the event
360 * index from memory. The controller needs to provide similar
361 * ordering to ensure the envent index is updated before reading
362 * the doorbell.
363 */
364 mb();
365
f9f38e33
HK		 366 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value))
367 return false;
368 }
369
370 return true;
b60503ba
MW		 371}
372
ac3dd5bd
JA		 373/*
374 * Will slightly overestimate the number of pages needed. This is OK
375 * as it only leads to a small amount of wasted memory for the lifetime of
376 * the I/O.
377 */
b13c6393 378static int nvme_pci_npages_prp(void)
ac3dd5bd 379{
b13c6393 380 unsigned nprps = DIV_ROUND_UP(NVME_MAX_KB_SZ + NVME_CTRL_PAGE_SIZE,
6c3c05b0 381 NVME_CTRL_PAGE_SIZE);
ac3dd5bd
JA		 382 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
383}
384
a7a7cbe3
CK		 385/*
386 * Calculates the number of pages needed for the SGL segments. For example a 4k
387 * page can accommodate 256 SGL descriptors.
388 */
b13c6393 389static int nvme_pci_npages_sgl(void)
ac3dd5bd 390{
b13c6393
CK		 391 return DIV_ROUND_UP(NVME_MAX_SEGS * sizeof(struct nvme_sgl_desc),
392 PAGE_SIZE);
f4800d6d 393}
ac3dd5bd 394
b13c6393 395static size_t nvme_pci_iod_alloc_size(void)
f4800d6d 396{
b13c6393 397 size_t npages = max(nvme_pci_npages_prp(), nvme_pci_npages_sgl());
a7a7cbe3 398
b13c6393
CK		 399 return sizeof(__le64 *) * npages +
400 sizeof(struct scatterlist) * NVME_MAX_SEGS;
f4800d6d 401}
ac3dd5bd 402
a4aea562
MB		 403static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
404 unsigned int hctx_idx)
e85248e5 405{
a4aea562 406 struct nvme_dev *dev = data;
147b27e4 407 struct nvme_queue *nvmeq = &dev->queues[0];
a4aea562 408
42483228
KB		 409 WARN_ON(hctx_idx != 0);
410 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
42483228 411
a4aea562
MB		 412 hctx->driver_data = nvmeq;
413 return 0;
e85248e5
MW		 414}
415
a4aea562
MB		 416static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
417 unsigned int hctx_idx)
b60503ba 418{
a4aea562 419 struct nvme_dev *dev = data;
147b27e4 420 struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
a4aea562 421
42483228 422 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
a4aea562
MB		 423 hctx->driver_data = nvmeq;
424 return 0;
b60503ba
MW		 425}
426
e559398f
CH		 427static int nvme_pci_init_request(struct blk_mq_tag_set *set,
428 struct request *req, unsigned int hctx_idx,
429 unsigned int numa_node)
b60503ba 430{
d6296d39 431 struct nvme_dev *dev = set->driver_data;
f4800d6d 432 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
59e29ce6
SG		 433
434 nvme_req(req)->ctrl = &dev->ctrl;
f4b9e6c9 435 nvme_req(req)->cmd = &iod->cmd;
a4aea562
MB		 436 return 0;
437}
438
3b6592f7
JA		 439static int queue_irq_offset(struct nvme_dev *dev)
440{
441 /* if we have more than 1 vec, admin queue offsets us by 1 */
442 if (dev->num_vecs > 1)
443 return 1;
444
445 return 0;
446}
447
a4e1d0b7 448static void nvme_pci_map_queues(struct blk_mq_tag_set *set)
dca51e78
CH		 449{
450 struct nvme_dev *dev = set->driver_data;
3b6592f7
JA		 451 int i, qoff, offset;
452
453 offset = queue_irq_offset(dev);
454 for (i = 0, qoff = 0; i < set->nr_maps; i++) {
455 struct blk_mq_queue_map *map = &set->map[i];
456
457 map->nr_queues = dev->io_queues[i];
458 if (!map->nr_queues) {
e20ba6e1 459 BUG_ON(i == HCTX_TYPE_DEFAULT);
7e849dd9 460 continue;
3b6592f7
JA		 461 }
462
4b04cc6a
JA		 463 /*
464 * The poll queue(s) doesn't have an IRQ (and hence IRQ
465 * affinity), so use the regular blk-mq cpu mapping
466 */
3b6592f7 467 map->queue_offset = qoff;
cb9e0e50 468 if (i != HCTX_TYPE_POLL && offset)
4b04cc6a
JA		 469 blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset);
470 else
471 blk_mq_map_queues(map);
3b6592f7
JA		 472 qoff += map->nr_queues;
473 offset += map->nr_queues;
474 }
dca51e78
CH		 475}
476
38210800
KB		 477/*
478 * Write sq tail if we are asked to, or if the next command would wrap.
479 */
480static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq)
04f3eafd 481{
38210800
KB		 482 if (!write_sq) {
483 u16 next_tail = nvmeq->sq_tail + 1;
484
485 if (next_tail == nvmeq->q_depth)
486 next_tail = 0;
487 if (next_tail != nvmeq->last_sq_tail)
488 return;
489 }
490
04f3eafd
JA		 491 if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail,
492 nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei))
493 writel(nvmeq->sq_tail, nvmeq->q_db);
38210800 494 nvmeq->last_sq_tail = nvmeq->sq_tail;
04f3eafd
JA		 495}
496
3233b94c
JA		 497static inline void nvme_sq_copy_cmd(struct nvme_queue *nvmeq,
498 struct nvme_command *cmd)
b60503ba 499{
c1e0cc7e 500 memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes),
3233b94c 501 absolute_pointer(cmd), sizeof(*cmd));
90ea5ca4
CH		 502 if (++nvmeq->sq_tail == nvmeq->q_depth)
503 nvmeq->sq_tail = 0;
04f3eafd
JA		 504}
505
506static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx)
507{
508 struct nvme_queue *nvmeq = hctx->driver_data;
509
510 spin_lock(&nvmeq->sq_lock);
38210800
KB		 511 if (nvmeq->sq_tail != nvmeq->last_sq_tail)
512 nvme_write_sq_db(nvmeq, true);
90ea5ca4 513 spin_unlock(&nvmeq->sq_lock);
b60503ba
MW		 514}
515
a7a7cbe3 516static void **nvme_pci_iod_list(struct request *req)
b60503ba 517{
f4800d6d 518 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
91fb2b60 519 return (void **)(iod->sgt.sgl + blk_rq_nr_phys_segments(req));
b60503ba
MW		 520}
521
955b1b5a
MI		 522static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req)
523{
a53232cb 524 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
20469a37 525 int nseg = blk_rq_nr_phys_segments(req);
955b1b5a
MI		 526 unsigned int avg_seg_size;
527
20469a37 528 avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
955b1b5a 529
253a0b76 530 if (!nvme_ctrl_sgl_supported(&dev->ctrl))
955b1b5a 531 return false;
a53232cb 532 if (!nvmeq->qid)
955b1b5a
MI		 533 return false;
534 if (!sgl_threshold || avg_seg_size < sgl_threshold)
535 return false;
536 return true;
537}
538
9275c206 539static void nvme_free_prps(struct nvme_dev *dev, struct request *req)
b60503ba 540{
6c3c05b0 541 const int last_prp = NVME_CTRL_PAGE_SIZE / sizeof(__le64) - 1;
9275c206
CH		 542 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
543 dma_addr_t dma_addr = iod->first_dma;
eca18b23 544 int i;
eca18b23 545
c372cdd1 546 for (i = 0; i < iod->nr_allocations; i++) {
9275c206
CH		 547 __le64 *prp_list = nvme_pci_iod_list(req)[i];
548 dma_addr_t next_dma_addr = le64_to_cpu(prp_list[last_prp]);
549
550 dma_pool_free(dev->prp_page_pool, prp_list, dma_addr);
551 dma_addr = next_dma_addr;
7fe07d14 552 }
9275c206 553}
dff824b2 554
9275c206
CH		 555static void nvme_free_sgls(struct nvme_dev *dev, struct request *req)
556{
557 const int last_sg = SGES_PER_PAGE - 1;
558 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
559 dma_addr_t dma_addr = iod->first_dma;
560 int i;
dff824b2 561
c372cdd1 562 for (i = 0; i < iod->nr_allocations; i++) {
9275c206
CH		 563 struct nvme_sgl_desc *sg_list = nvme_pci_iod_list(req)[i];
564 dma_addr_t next_dma_addr = le64_to_cpu((sg_list[last_sg]).addr);
dff824b2 565
9275c206
CH		 566 dma_pool_free(dev->prp_page_pool, sg_list, dma_addr);
567 dma_addr = next_dma_addr;
568 }
9275c206 569}
a7a7cbe3 570
9275c206
CH		 571static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
572{
573 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3 574
9275c206
CH		 575 if (iod->dma_len) {
576 dma_unmap_page(dev->dev, iod->first_dma, iod->dma_len,
577 rq_dma_dir(req));
578 return;
eca18b23 579 }
ac3dd5bd 580
91fb2b60
LG		 581 WARN_ON_ONCE(!iod->sgt.nents);
582
583 dma_unmap_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req), 0);
9275c206 584
c372cdd1 585 if (iod->nr_allocations == 0)
9275c206
CH		 586 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0],
587 iod->first_dma);
588 else if (iod->use_sgl)
589 nvme_free_sgls(dev, req);
590 else
591 nvme_free_prps(dev, req);
91fb2b60 592 mempool_free(iod->sgt.sgl, dev->iod_mempool);
b4ff9c8d
KB		 593}
594
d0877473
KB		 595static void nvme_print_sgl(struct scatterlist *sgl, int nents)
596{
597 int i;
598 struct scatterlist *sg;
599
600 for_each_sg(sgl, sg, nents, i) {
601 dma_addr_t phys = sg_phys(sg);
602 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
603 "dma_address:%pad dma_length:%d\n",
604 i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
605 sg_dma_len(sg));
606 }
607}
608
a7a7cbe3
CK		 609static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
610 struct request *req, struct nvme_rw_command *cmnd)
ff22b54f 611{
f4800d6d 612 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
99802a7a 613 struct dma_pool *pool;
b131c61d 614 int length = blk_rq_payload_bytes(req);
91fb2b60 615 struct scatterlist *sg = iod->sgt.sgl;
ff22b54f
MW		 616 int dma_len = sg_dma_len(sg);
617 u64 dma_addr = sg_dma_address(sg);
6c3c05b0 618 int offset = dma_addr & (NVME_CTRL_PAGE_SIZE - 1);
e025344c 619 __le64 *prp_list;
a7a7cbe3 620 void **list = nvme_pci_iod_list(req);
e025344c 621 dma_addr_t prp_dma;
eca18b23 622 int nprps, i;
ff22b54f 623
6c3c05b0 624 length -= (NVME_CTRL_PAGE_SIZE - offset);
5228b328
JS		 625 if (length <= 0) {
626 iod->first_dma = 0;
a7a7cbe3 627 goto done;
5228b328 628 }
ff22b54f 629
6c3c05b0 630 dma_len -= (NVME_CTRL_PAGE_SIZE - offset);
ff22b54f 631 if (dma_len) {
6c3c05b0 632 dma_addr += (NVME_CTRL_PAGE_SIZE - offset);
ff22b54f
MW		 633 } else {
634 sg = sg_next(sg);
635 dma_addr = sg_dma_address(sg);
636 dma_len = sg_dma_len(sg);
637 }
638
6c3c05b0 639 if (length <= NVME_CTRL_PAGE_SIZE) {
edd10d33 640 iod->first_dma = dma_addr;
a7a7cbe3 641 goto done;
e025344c
SMM		 642 }
643
6c3c05b0 644 nprps = DIV_ROUND_UP(length, NVME_CTRL_PAGE_SIZE);
99802a7a
MW		 645 if (nprps <= (256 / 8)) {
646 pool = dev->prp_small_pool;
c372cdd1 647 iod->nr_allocations = 0;
99802a7a
MW		 648 } else {
649 pool = dev->prp_page_pool;
c372cdd1 650 iod->nr_allocations = 1;
99802a7a
MW		 651 }
652
69d2b571 653 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
b77954cb 654 if (!prp_list) {
c372cdd1 655 iod->nr_allocations = -1;
86eea289 656 return BLK_STS_RESOURCE;
b77954cb 657 }
eca18b23
MW		 658 list[0] = prp_list;
659 iod->first_dma = prp_dma;
e025344c
SMM		 660 i = 0;
661 for (;;) {
6c3c05b0 662 if (i == NVME_CTRL_PAGE_SIZE >> 3) {
e025344c 663 __le64 *old_prp_list = prp_list;
69d2b571 664 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
eca18b23 665 if (!prp_list)
fa073216 666 goto free_prps;
c372cdd1 667 list[iod->nr_allocations++] = prp_list;
7523d834
MW		 668 prp_list[0] = old_prp_list[i - 1];
669 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
670 i = 1;
e025344c
SMM		 671 }
672 prp_list[i++] = cpu_to_le64(dma_addr);
6c3c05b0
CK		 673 dma_len -= NVME_CTRL_PAGE_SIZE;
674 dma_addr += NVME_CTRL_PAGE_SIZE;
675 length -= NVME_CTRL_PAGE_SIZE;
e025344c
SMM		 676 if (length <= 0)
677 break;
678 if (dma_len > 0)
679 continue;
86eea289
KB		 680 if (unlikely(dma_len < 0))
681 goto bad_sgl;
e025344c
SMM		 682 sg = sg_next(sg);
683 dma_addr = sg_dma_address(sg);
684 dma_len = sg_dma_len(sg);
ff22b54f 685 }
a7a7cbe3 686done:
91fb2b60 687 cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sgt.sgl));
a7a7cbe3 688 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
86eea289 689 return BLK_STS_OK;
fa073216
CH		 690free_prps:
691 nvme_free_prps(dev, req);
692 return BLK_STS_RESOURCE;
693bad_sgl:
91fb2b60 694 WARN(DO_ONCE(nvme_print_sgl, iod->sgt.sgl, iod->sgt.nents),
d0877473 695 "Invalid SGL for payload:%d nents:%d\n",
91fb2b60 696 blk_rq_payload_bytes(req), iod->sgt.nents);
86eea289 697 return BLK_STS_IOERR;
ff22b54f
MW		 698}
699
a7a7cbe3
CK		 700static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
701 struct scatterlist *sg)
702{
703 sge->addr = cpu_to_le64(sg_dma_address(sg));
704 sge->length = cpu_to_le32(sg_dma_len(sg));
705 sge->type = NVME_SGL_FMT_DATA_DESC << 4;
706}
707
708static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
709 dma_addr_t dma_addr, int entries)
710{
711 sge->addr = cpu_to_le64(dma_addr);
712 if (entries < SGES_PER_PAGE) {
713 sge->length = cpu_to_le32(entries * sizeof(*sge));
714 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
715 } else {
716 sge->length = cpu_to_le32(PAGE_SIZE);
717 sge->type = NVME_SGL_FMT_SEG_DESC << 4;
718 }
719}
720
721static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
91fb2b60 722 struct request *req, struct nvme_rw_command *cmd)
a7a7cbe3
CK		 723{
724 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3
CK		 725 struct dma_pool *pool;
726 struct nvme_sgl_desc *sg_list;
91fb2b60
LG		 727 struct scatterlist *sg = iod->sgt.sgl;
728 unsigned int entries = iod->sgt.nents;
a7a7cbe3 729 dma_addr_t sgl_dma;
b0f2853b 730 int i = 0;
a7a7cbe3 731
a7a7cbe3
CK		 732 /* setting the transfer type as SGL */
733 cmd->flags = NVME_CMD_SGL_METABUF;
734
b0f2853b 735 if (entries == 1) {
a7a7cbe3
CK		 736 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
737 return BLK_STS_OK;
738 }
739
740 if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
741 pool = dev->prp_small_pool;
c372cdd1 742 iod->nr_allocations = 0;
a7a7cbe3
CK		 743 } else {
744 pool = dev->prp_page_pool;
c372cdd1 745 iod->nr_allocations = 1;
a7a7cbe3
CK		 746 }
747
748 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
749 if (!sg_list) {
c372cdd1 750 iod->nr_allocations = -1;
a7a7cbe3
CK		 751 return BLK_STS_RESOURCE;
752 }
753
754 nvme_pci_iod_list(req)[0] = sg_list;
755 iod->first_dma = sgl_dma;
756
757 nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
758
759 do {
760 if (i == SGES_PER_PAGE) {
761 struct nvme_sgl_desc *old_sg_desc = sg_list;
762 struct nvme_sgl_desc *link = &old_sg_desc[i - 1];
763
764 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
765 if (!sg_list)
fa073216 766 goto free_sgls;
a7a7cbe3
CK		 767
768 i = 0;
c372cdd1 769 nvme_pci_iod_list(req)[iod->nr_allocations++] = sg_list;
a7a7cbe3
CK		 770 sg_list[i++] = *link;
771 nvme_pci_sgl_set_seg(link, sgl_dma, entries);
772 }
773
774 nvme_pci_sgl_set_data(&sg_list[i++], sg);
a7a7cbe3 775 sg = sg_next(sg);
b0f2853b 776 } while (--entries > 0);
a7a7cbe3 777
a7a7cbe3 778 return BLK_STS_OK;
fa073216
CH		 779free_sgls:
780 nvme_free_sgls(dev, req);
781 return BLK_STS_RESOURCE;
a7a7cbe3
CK		 782}
783
dff824b2
CH		 784static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev,
785 struct request *req, struct nvme_rw_command *cmnd,
786 struct bio_vec *bv)
787{
788 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
6c3c05b0
CK		 789 unsigned int offset = bv->bv_offset & (NVME_CTRL_PAGE_SIZE - 1);
790 unsigned int first_prp_len = NVME_CTRL_PAGE_SIZE - offset;
dff824b2
CH		 791
792 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
793 if (dma_mapping_error(dev->dev, iod->first_dma))
794 return BLK_STS_RESOURCE;
795 iod->dma_len = bv->bv_len;
796
797 cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma);
798 if (bv->bv_len > first_prp_len)
799 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len);
359c1f88 800 return BLK_STS_OK;
dff824b2
CH		 801}
802
29791057
CH		 803static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev,
804 struct request *req, struct nvme_rw_command *cmnd,
805 struct bio_vec *bv)
806{
807 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
808
809 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
810 if (dma_mapping_error(dev->dev, iod->first_dma))
811 return BLK_STS_RESOURCE;
812 iod->dma_len = bv->bv_len;
813
049bf372 814 cmnd->flags = NVME_CMD_SGL_METABUF;
29791057
CH		 815 cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma);
816 cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len);
817 cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4;
359c1f88 818 return BLK_STS_OK;
29791057
CH		 819}
820
fc17b653 821static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
b131c61d 822 struct nvme_command *cmnd)
d29ec824 823{
f4800d6d 824 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
70479b71 825 blk_status_t ret = BLK_STS_RESOURCE;
91fb2b60 826 int rc;
d29ec824 827
dff824b2 828 if (blk_rq_nr_phys_segments(req) == 1) {
a53232cb 829 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
dff824b2
CH		 830 struct bio_vec bv = req_bvec(req);
831
832 if (!is_pci_p2pdma_page(bv.bv_page)) {
6c3c05b0 833 if (bv.bv_offset + bv.bv_len <= NVME_CTRL_PAGE_SIZE * 2)
dff824b2
CH		 834 return nvme_setup_prp_simple(dev, req,
835 &cmnd->rw, &bv);
29791057 836
a53232cb 837 if (nvmeq->qid && sgl_threshold &&
253a0b76 838 nvme_ctrl_sgl_supported(&dev->ctrl))
29791057
CH		 839 return nvme_setup_sgl_simple(dev, req,
840 &cmnd->rw, &bv);
dff824b2
CH		 841 }
842 }
843
844 iod->dma_len = 0;
91fb2b60
LG		 845 iod->sgt.sgl = mempool_alloc(dev->iod_mempool, GFP_ATOMIC);
846 if (!iod->sgt.sgl)
d43f1ccf 847 return BLK_STS_RESOURCE;
91fb2b60
LG		 848 sg_init_table(iod->sgt.sgl, blk_rq_nr_phys_segments(req));
849 iod->sgt.orig_nents = blk_rq_map_sg(req->q, req, iod->sgt.sgl);
850 if (!iod->sgt.orig_nents)
fa073216 851 goto out_free_sg;
d29ec824 852
91fb2b60
LG		 853 rc = dma_map_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req),
854 DMA_ATTR_NO_WARN);
855 if (rc) {
856 if (rc == -EREMOTEIO)
857 ret = BLK_STS_TARGET;
fa073216 858 goto out_free_sg;
91fb2b60 859 }
d29ec824 860
70479b71 861 iod->use_sgl = nvme_pci_use_sgls(dev, req);
955b1b5a 862 if (iod->use_sgl)
91fb2b60 863 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw);
a7a7cbe3
CK		 864 else
865 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
86eea289 866 if (ret != BLK_STS_OK)
fa073216
CH		 867 goto out_unmap_sg;
868 return BLK_STS_OK;
869
870out_unmap_sg:
91fb2b60 871 dma_unmap_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req), 0);
fa073216 872out_free_sg:
91fb2b60 873 mempool_free(iod->sgt.sgl, dev->iod_mempool);
4aedb705
CH		 874 return ret;
875}
3045c0d0 876
4aedb705
CH		 877static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req,
878 struct nvme_command *cmnd)
879{
880 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
00df5cb4 881
4aedb705
CH		 882 iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req),
883 rq_dma_dir(req), 0);
884 if (dma_mapping_error(dev->dev, iod->meta_dma))
885 return BLK_STS_IOERR;
886 cmnd->rw.metadata = cpu_to_le64(iod->meta_dma);
359c1f88 887 return BLK_STS_OK;
00df5cb4
MW		 888}
889
62451a2b 890static blk_status_t nvme_prep_rq(struct nvme_dev *dev, struct request *req)
edd10d33 891{
9b048119 892 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
ebe6d874 893 blk_status_t ret;
e1e5e564 894
52da4f3f 895 iod->aborted = false;
c372cdd1 896 iod->nr_allocations = -1;
91fb2b60 897 iod->sgt.nents = 0;
9b048119 898
62451a2b 899 ret = nvme_setup_cmd(req->q->queuedata, req);
fc17b653 900 if (ret)
f4800d6d 901 return ret;
a4aea562 902
fc17b653 903 if (blk_rq_nr_phys_segments(req)) {
62451a2b 904 ret = nvme_map_data(dev, req, &iod->cmd);
fc17b653 905 if (ret)
9b048119 906 goto out_free_cmd;
fc17b653 907 }
a4aea562 908
4aedb705 909 if (blk_integrity_rq(req)) {
62451a2b 910 ret = nvme_map_metadata(dev, req, &iod->cmd);
4aedb705
CH		 911 if (ret)
912 goto out_unmap_data;
913 }
914
aae239e1 915 blk_mq_start_request(req);
fc17b653 916 return BLK_STS_OK;
4aedb705
CH		 917out_unmap_data:
918 nvme_unmap_data(dev, req);
f9d03f96
CH		 919out_free_cmd:
920 nvme_cleanup_cmd(req);
ba1ca37e 921 return ret;
b60503ba 922}
e1e5e564 923
62451a2b
JA		 924/*
925 * NOTE: ns is NULL when called on the admin queue.
926 */
927static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
928 const struct blk_mq_queue_data *bd)
929{
930 struct nvme_queue *nvmeq = hctx->driver_data;
931 struct nvme_dev *dev = nvmeq->dev;
932 struct request *req = bd->rq;
933 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
934 blk_status_t ret;
935
936 /*
937 * We should not need to do this, but we're still using this to
938 * ensure we can drain requests on a dying queue.
939 */
940 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
941 return BLK_STS_IOERR;
942
943 if (unlikely(!nvme_check_ready(&dev->ctrl, req, true)))
944 return nvme_fail_nonready_command(&dev->ctrl, req);
945
946 ret = nvme_prep_rq(dev, req);
947 if (unlikely(ret))
948 return ret;
949 spin_lock(&nvmeq->sq_lock);
950 nvme_sq_copy_cmd(nvmeq, &iod->cmd);
951 nvme_write_sq_db(nvmeq, bd->last);
952 spin_unlock(&nvmeq->sq_lock);
953 return BLK_STS_OK;
954}
955
d62cbcf6
JA		 956static void nvme_submit_cmds(struct nvme_queue *nvmeq, struct request **rqlist)
957{
958 spin_lock(&nvmeq->sq_lock);
959 while (!rq_list_empty(*rqlist)) {
960 struct request *req = rq_list_pop(rqlist);
961 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
962
963 nvme_sq_copy_cmd(nvmeq, &iod->cmd);
964 }
965 nvme_write_sq_db(nvmeq, true);
966 spin_unlock(&nvmeq->sq_lock);
967}
968
969static bool nvme_prep_rq_batch(struct nvme_queue *nvmeq, struct request *req)
970{
971 /*
972 * We should not need to do this, but we're still using this to
973 * ensure we can drain requests on a dying queue.
974 */
975 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
976 return false;
977 if (unlikely(!nvme_check_ready(&nvmeq->dev->ctrl, req, true)))
978 return false;
979
980 req->mq_hctx->tags->rqs[req->tag] = req;
981 return nvme_prep_rq(nvmeq->dev, req) == BLK_STS_OK;
982}
983
984static void nvme_queue_rqs(struct request **rqlist)
985{
6bfec799 986 struct request *req, *next, *prev = NULL;
d62cbcf6
JA		 987 struct request *requeue_list = NULL;
988
6bfec799 989 rq_list_for_each_safe(rqlist, req, next) {
d62cbcf6
JA		 990 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
991
992 if (!nvme_prep_rq_batch(nvmeq, req)) {
993 /* detach 'req' and add to remainder list */
6bfec799
KB		 994 rq_list_move(rqlist, &requeue_list, req, prev);
995
996 req = prev;
997 if (!req)
998 continue;
d62cbcf6
JA		 999 }
1000
6bfec799 1001 if (!next || req->mq_hctx != next->mq_hctx) {
d62cbcf6 1002 /* detach rest of list, and submit */
6bfec799 1003 req->rq_next = NULL;
d62cbcf6 1004 nvme_submit_cmds(nvmeq, rqlist);
6bfec799
KB		 1005 *rqlist = next;
1006 prev = NULL;
1007 } else
1008 prev = req;
1009 }
d62cbcf6
JA		 1010
1011 *rqlist = requeue_list;
1012}
1013
c234a653 1014static __always_inline void nvme_pci_unmap_rq(struct request *req)
eee417b0 1015{
a53232cb
KB		 1016 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
1017 struct nvme_dev *dev = nvmeq->dev;
1018
1019 if (blk_integrity_rq(req)) {
1020 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a4aea562 1021
4aedb705
CH		 1022 dma_unmap_page(dev->dev, iod->meta_dma,
1023 rq_integrity_vec(req)->bv_len, rq_data_dir(req));
a53232cb
KB		 1024 }
1025
b15c592d 1026 if (blk_rq_nr_phys_segments(req))
4aedb705 1027 nvme_unmap_data(dev, req);
c234a653
JA		 1028}
1029
1030static void nvme_pci_complete_rq(struct request *req)
1031{
1032 nvme_pci_unmap_rq(req);
77f02a7a 1033 nvme_complete_rq(req);
b60503ba
MW		 1034}
1035
c234a653
JA		 1036static void nvme_pci_complete_batch(struct io_comp_batch *iob)
1037{
1038 nvme_complete_batch(iob, nvme_pci_unmap_rq);
1039}
1040
d783e0bd 1041/* We read the CQE phase first to check if the rest of the entry is valid */
750dde44 1042static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq)
d783e0bd 1043{
74943d45
KB		 1044 struct nvme_completion *hcqe = &nvmeq->cqes[nvmeq->cq_head];
1045
1046 return (le16_to_cpu(READ_ONCE(hcqe->status)) & 1) == nvmeq->cq_phase;
d783e0bd
MR		 1047}
1048
eb281c82 1049static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
b60503ba 1050{
eb281c82 1051 u16 head = nvmeq->cq_head;
adf68f21 1052
397c699f
KB		 1053 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
1054 nvmeq->dbbuf_cq_ei))
1055 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
eb281c82 1056}
aae239e1 1057
cfa27356
CH		 1058static inline struct blk_mq_tags *nvme_queue_tagset(struct nvme_queue *nvmeq)
1059{
1060 if (!nvmeq->qid)
1061 return nvmeq->dev->admin_tagset.tags[0];
1062 return nvmeq->dev->tagset.tags[nvmeq->qid - 1];
1063}
1064
c234a653
JA		 1065static inline void nvme_handle_cqe(struct nvme_queue *nvmeq,
1066 struct io_comp_batch *iob, u16 idx)
83a12fb7 1067{
74943d45 1068 struct nvme_completion *cqe = &nvmeq->cqes[idx];
62df8016 1069 __u16 command_id = READ_ONCE(cqe->command_id);
83a12fb7 1070 struct request *req;
adf68f21 1071
83a12fb7
SG		 1072 /*
1073 * AEN requests are special as they don't time out and can
1074 * survive any kind of queue freeze and often don't respond to
1075 * aborts. We don't even bother to allocate a struct request
1076 * for them but rather special case them here.
1077 */
62df8016 1078 if (unlikely(nvme_is_aen_req(nvmeq->qid, command_id))) {
83a12fb7
SG		 1079 nvme_complete_async_event(&nvmeq->dev->ctrl,
1080 cqe->status, &cqe->result);
a0fa9647 1081 return;
83a12fb7 1082 }
b60503ba 1083
e7006de6 1084 req = nvme_find_rq(nvme_queue_tagset(nvmeq), command_id);
50b7c243
XT		 1085 if (unlikely(!req)) {
1086 dev_warn(nvmeq->dev->ctrl.device,
1087 "invalid id %d completed on queue %d\n",
62df8016 1088 command_id, le16_to_cpu(cqe->sq_id));
50b7c243
XT		 1089 return;
1090 }
1091
604c01d5 1092 trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail);
c234a653
JA		 1093 if (!nvme_try_complete_req(req, cqe->status, cqe->result) &&
1094 !blk_mq_add_to_batch(req, iob, nvme_req(req)->status,
1095 nvme_pci_complete_batch))
ff029451 1096 nvme_pci_complete_rq(req);
83a12fb7 1097}
b60503ba 1098
5cb525c8
JA		 1099static inline void nvme_update_cq_head(struct nvme_queue *nvmeq)
1100{
a0aac973 1101 u32 tmp = nvmeq->cq_head + 1;
a8de6639
AD		 1102
1103 if (tmp == nvmeq->q_depth) {
5cb525c8 1104 nvmeq->cq_head = 0;
e2a366a4 1105 nvmeq->cq_phase ^= 1;
a8de6639
AD		 1106 } else {
1107 nvmeq->cq_head = tmp;
b60503ba 1108 }
a0fa9647
JA		 1109}
1110
c234a653
JA		 1111static inline int nvme_poll_cq(struct nvme_queue *nvmeq,
1112 struct io_comp_batch *iob)
a0fa9647 1113{
1052b8ac 1114 int found = 0;
b60503ba 1115
1052b8ac 1116 while (nvme_cqe_pending(nvmeq)) {
bf392a5d 1117 found++;
b69e2ef2
KB		 1118 /*
1119 * load-load control dependency between phase and the rest of
1120 * the cqe requires a full read memory barrier
1121 */
1122 dma_rmb();
c234a653 1123 nvme_handle_cqe(nvmeq, iob, nvmeq->cq_head);
5cb525c8 1124 nvme_update_cq_head(nvmeq);
920d13a8 1125 }
eb281c82 1126
324b494c 1127 if (found)
920d13a8 1128 nvme_ring_cq_doorbell(nvmeq);
5cb525c8 1129 return found;
b60503ba
MW		 1130}
1131
1132static irqreturn_t nvme_irq(int irq, void *data)
58ffacb5 1133{
58ffacb5 1134 struct nvme_queue *nvmeq = data;
4f502245 1135 DEFINE_IO_COMP_BATCH(iob);
5cb525c8 1136
4f502245
JA		 1137 if (nvme_poll_cq(nvmeq, &iob)) {
1138 if (!rq_list_empty(iob.req_list))
1139 nvme_pci_complete_batch(&iob);
05fae499 1140 return IRQ_HANDLED;
4f502245 1141 }
05fae499 1142 return IRQ_NONE;
58ffacb5
MW		 1143}
1144
1145static irqreturn_t nvme_irq_check(int irq, void *data)
1146{
1147 struct nvme_queue *nvmeq = data;
4e523547 1148
750dde44 1149 if (nvme_cqe_pending(nvmeq))
d783e0bd
MR		 1150 return IRQ_WAKE_THREAD;
1151 return IRQ_NONE;
58ffacb5
MW		 1152}
1153
0b2a8a9f 1154/*
fa059b85 1155 * Poll for completions for any interrupt driven queue
0b2a8a9f
CH		 1156 * Can be called from any context.
1157 */
fa059b85 1158static void nvme_poll_irqdisable(struct nvme_queue *nvmeq)
a0fa9647 1159{
3a7afd8e 1160 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
a0fa9647 1161
fa059b85 1162 WARN_ON_ONCE(test_bit(NVMEQ_POLLED, &nvmeq->flags));
442e19b7 1163
fa059b85 1164 disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
c234a653 1165 nvme_poll_cq(nvmeq, NULL);
fa059b85 1166 enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
a0fa9647
JA		 1167}
1168
5a72e899 1169static int nvme_poll(struct blk_mq_hw_ctx *hctx, struct io_comp_batch *iob)
dabcefab
JA		 1170{
1171 struct nvme_queue *nvmeq = hctx->driver_data;
dabcefab
JA		 1172 bool found;
1173
1174 if (!nvme_cqe_pending(nvmeq))
1175 return 0;
1176
3a7afd8e 1177 spin_lock(&nvmeq->cq_poll_lock);
c234a653 1178 found = nvme_poll_cq(nvmeq, iob);
3a7afd8e 1179 spin_unlock(&nvmeq->cq_poll_lock);
dabcefab 1180
dabcefab
JA		 1181 return found;
1182}
1183
ad22c355 1184static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
b60503ba 1185{
f866fc42 1186 struct nvme_dev *dev = to_nvme_dev(ctrl);
147b27e4 1187 struct nvme_queue *nvmeq = &dev->queues[0];
f66e2804 1188 struct nvme_command c = { };
b60503ba 1189
a4aea562 1190 c.common.opcode = nvme_admin_async_event;
ad22c355 1191 c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
3233b94c
JA		 1192
1193 spin_lock(&nvmeq->sq_lock);
1194 nvme_sq_copy_cmd(nvmeq, &c);
1195 nvme_write_sq_db(nvmeq, true);
1196 spin_unlock(&nvmeq->sq_lock);
f705f837
CH		 1197}
1198
b60503ba 1199static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
f705f837 1200{
f66e2804 1201 struct nvme_command c = { };
b60503ba 1202
b60503ba
MW		 1203 c.delete_queue.opcode = opcode;
1204 c.delete_queue.qid = cpu_to_le16(id);
1205
1c63dc66 1206 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1207}
1208
b60503ba 1209static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
a8e3e0bb 1210 struct nvme_queue *nvmeq, s16 vector)
b60503ba 1211{
f66e2804 1212 struct nvme_command c = { };
4b04cc6a
JA		 1213 int flags = NVME_QUEUE_PHYS_CONTIG;
1214
7c349dde 1215 if (!test_bit(NVMEQ_POLLED, &nvmeq->flags))
4b04cc6a 1216 flags |= NVME_CQ_IRQ_ENABLED;
b60503ba 1217
d29ec824 1218 /*
16772ae6 1219 * Note: we (ab)use the fact that the prp fields survive if no data
d29ec824
CH		 1220 * is attached to the request.
1221 */
b60503ba
MW		 1222 c.create_cq.opcode = nvme_admin_create_cq;
1223 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1224 c.create_cq.cqid = cpu_to_le16(qid);
1225 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1226 c.create_cq.cq_flags = cpu_to_le16(flags);
7c349dde 1227 c.create_cq.irq_vector = cpu_to_le16(vector);
b60503ba 1228
1c63dc66 1229 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1230}
1231
1232static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1233 struct nvme_queue *nvmeq)
1234{
9abd68ef 1235 struct nvme_ctrl *ctrl = &dev->ctrl;
f66e2804 1236 struct nvme_command c = { };
81c1cd98 1237 int flags = NVME_QUEUE_PHYS_CONTIG;
b60503ba 1238
9abd68ef
JA		 1239 /*
1240 * Some drives have a bug that auto-enables WRRU if MEDIUM isn't
1241 * set. Since URGENT priority is zeroes, it makes all queues
1242 * URGENT.
1243 */
1244 if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ)
1245 flags |= NVME_SQ_PRIO_MEDIUM;
1246
d29ec824 1247 /*
16772ae6 1248 * Note: we (ab)use the fact that the prp fields survive if no data
d29ec824
CH		 1249 * is attached to the request.
1250 */
b60503ba
MW		 1251 c.create_sq.opcode = nvme_admin_create_sq;
1252 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1253 c.create_sq.sqid = cpu_to_le16(qid);
1254 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1255 c.create_sq.sq_flags = cpu_to_le16(flags);
1256 c.create_sq.cqid = cpu_to_le16(qid);
1257
1c63dc66 1258 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1259}
1260
1261static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1262{
1263 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1264}
1265
1266static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1267{
1268 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1269}
1270
2a842aca 1271static void abort_endio(struct request *req, blk_status_t error)
bc5fc7e4 1272{
a53232cb 1273 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
e44ac588 1274
27fa9bc5
CH		 1275 dev_warn(nvmeq->dev->ctrl.device,
1276 "Abort status: 0x%x", nvme_req(req)->status);
e7a2a87d 1277 atomic_inc(&nvmeq->dev->ctrl.abort_limit);
e7a2a87d 1278 blk_mq_free_request(req);
bc5fc7e4
MW		 1279}
1280
b2a0eb1a
KB		 1281static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1282{
b2a0eb1a
KB		 1283 /* If true, indicates loss of adapter communication, possibly by a
1284 * NVMe Subsystem reset.
1285 */
1286 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1287
ad70062c
JW		 1288 /* If there is a reset/reinit ongoing, we shouldn't reset again. */
1289 switch (dev->ctrl.state) {
1290 case NVME_CTRL_RESETTING:
ad6a0a52 1291 case NVME_CTRL_CONNECTING:
b2a0eb1a 1292 return false;
ad70062c
JW		 1293 default:
1294 break;
1295 }
b2a0eb1a
KB		 1296
1297 /* We shouldn't reset unless the controller is on fatal error state
1298 * _or_ if we lost the communication with it.
1299 */
1300 if (!(csts & NVME_CSTS_CFS) && !nssro)
1301 return false;
1302
b2a0eb1a
KB		 1303 return true;
1304}
1305
1306static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1307{
1308 /* Read a config register to help see what died. */
1309 u16 pci_status;
1310 int result;
1311
1312 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1313 &pci_status);
1314 if (result == PCIBIOS_SUCCESSFUL)
1315 dev_warn(dev->ctrl.device,
1316 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1317 csts, pci_status);
1318 else
1319 dev_warn(dev->ctrl.device,
1320 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1321 csts, result);
4641a8e6
KB		 1322
1323 if (csts != ~0)
1324 return;
1325
1326 dev_warn(dev->ctrl.device,
1327 "Does your device have a faulty power saving mode enabled?\n");
1328 dev_warn(dev->ctrl.device,
1329 "Try \"nvme_core.default_ps_max_latency_us=0 pcie_aspm=off\" and report a bug\n");
b2a0eb1a
KB		 1330}
1331
9bdb4833 1332static enum blk_eh_timer_return nvme_timeout(struct request *req)
c30341dc 1333{
f4800d6d 1334 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a53232cb 1335 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
c30341dc 1336 struct nvme_dev *dev = nvmeq->dev;
a4aea562 1337 struct request *abort_req;
f66e2804 1338 struct nvme_command cmd = { };
b2a0eb1a
KB		 1339 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1340
651438bb
WX		 1341 /* If PCI error recovery process is happening, we cannot reset or
1342 * the recovery mechanism will surely fail.
1343 */
1344 mb();
1345 if (pci_channel_offline(to_pci_dev(dev->dev)))
1346 return BLK_EH_RESET_TIMER;
1347
b2a0eb1a
KB		 1348 /*
1349 * Reset immediately if the controller is failed
1350 */
1351 if (nvme_should_reset(dev, csts)) {
1352 nvme_warn_reset(dev, csts);
1353 nvme_dev_disable(dev, false);
d86c4d8e 1354 nvme_reset_ctrl(&dev->ctrl);
db8c48e4 1355 return BLK_EH_DONE;
b2a0eb1a 1356 }
c30341dc 1357
7776db1c
KB		 1358 /*
1359 * Did we miss an interrupt?
1360 */
fa059b85 1361 if (test_bit(NVMEQ_POLLED, &nvmeq->flags))
5a72e899 1362 nvme_poll(req->mq_hctx, NULL);
fa059b85
KB		 1363 else
1364 nvme_poll_irqdisable(nvmeq);
1365
bf392a5d 1366 if (blk_mq_request_completed(req)) {
7776db1c
KB		 1367 dev_warn(dev->ctrl.device,
1368 "I/O %d QID %d timeout, completion polled\n",
1369 req->tag, nvmeq->qid);
db8c48e4 1370 return BLK_EH_DONE;
7776db1c
KB		 1371 }
1372
31c7c7d2 1373 /*
fd634f41
CH		 1374 * Shutdown immediately if controller times out while starting. The
1375 * reset work will see the pci device disabled when it gets the forced
1376 * cancellation error. All outstanding requests are completed on
db8c48e4 1377 * shutdown, so we return BLK_EH_DONE.
fd634f41 1378 */
4244140d
KB		 1379 switch (dev->ctrl.state) {
1380 case NVME_CTRL_CONNECTING:
2036f726 1381 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
df561f66 1382 fallthrough;
2036f726 1383 case NVME_CTRL_DELETING:
b9cac43c 1384 dev_warn_ratelimited(dev->ctrl.device,
fd634f41
CH		 1385 "I/O %d QID %d timeout, disable controller\n",
1386 req->tag, nvmeq->qid);
27fa9bc5 1387 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
7ad92f65 1388 nvme_dev_disable(dev, true);
db8c48e4 1389 return BLK_EH_DONE;
39a9dd81
KB		 1390 case NVME_CTRL_RESETTING:
1391 return BLK_EH_RESET_TIMER;
4244140d
KB		 1392 default:
1393 break;
c30341dc
KB		 1394 }
1395
fd634f41 1396 /*
ee0d96d3
BW		 1397 * Shutdown the controller immediately and schedule a reset if the
1398 * command was already aborted once before and still hasn't been
1399 * returned to the driver, or if this is the admin queue.
31c7c7d2 1400 */
f4800d6d 1401 if (!nvmeq->qid || iod->aborted) {
1b3c47c1 1402 dev_warn(dev->ctrl.device,
e1569a16
KB		 1403 "I/O %d QID %d timeout, reset controller\n",
1404 req->tag, nvmeq->qid);
7ad92f65 1405 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
a5cdb68c 1406 nvme_dev_disable(dev, false);
d86c4d8e 1407 nvme_reset_ctrl(&dev->ctrl);
c30341dc 1408
db8c48e4 1409 return BLK_EH_DONE;
c30341dc 1410 }
c30341dc 1411
e7a2a87d 1412 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
6bf25d16 1413 atomic_inc(&dev->ctrl.abort_limit);
31c7c7d2 1414 return BLK_EH_RESET_TIMER;
6bf25d16 1415 }
52da4f3f 1416 iod->aborted = true;
a4aea562 1417
c30341dc 1418 cmd.abort.opcode = nvme_admin_abort_cmd;
85f74acf 1419 cmd.abort.cid = nvme_cid(req);
c30341dc 1420 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
c30341dc 1421
1b3c47c1 1422 dev_warn(nvmeq->dev->ctrl.device,
86141440
CH		 1423 "I/O %d (%s) QID %d timeout, aborting\n",
1424 req->tag,
1425 nvme_get_opcode_str(nvme_req(req)->cmd->common.opcode),
1426 nvmeq->qid);
e7a2a87d 1427
e559398f
CH		 1428 abort_req = blk_mq_alloc_request(dev->ctrl.admin_q, nvme_req_op(&cmd),
1429 BLK_MQ_REQ_NOWAIT);
e7a2a87d
CH		 1430 if (IS_ERR(abort_req)) {
1431 atomic_inc(&dev->ctrl.abort_limit);
1432 return BLK_EH_RESET_TIMER;
1433 }
e559398f 1434 nvme_init_request(abort_req, &cmd);
e7a2a87d 1435
e2e53086 1436 abort_req->end_io = abort_endio;
e7a2a87d 1437 abort_req->end_io_data = NULL;
128126a7 1438 abort_req->rq_flags |= RQF_QUIET;
e2e53086 1439 blk_execute_rq_nowait(abort_req, false);
c30341dc 1440
31c7c7d2
CH		 1441 /*
1442 * The aborted req will be completed on receiving the abort req.
1443 * We enable the timer again. If hit twice, it'll cause a device reset,
1444 * as the device then is in a faulty state.
1445 */
1446 return BLK_EH_RESET_TIMER;
c30341dc
KB		 1447}
1448
a4aea562
MB		 1449static void nvme_free_queue(struct nvme_queue *nvmeq)
1450{
8a1d09a6 1451 dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq),
9e866774 1452 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
63223078
CH		 1453 if (!nvmeq->sq_cmds)
1454 return;
0f238ff5 1455
63223078 1456 if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) {
88a041f4 1457 pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev),
8a1d09a6 1458 nvmeq->sq_cmds, SQ_SIZE(nvmeq));
63223078 1459 } else {
8a1d09a6 1460 dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq),
63223078 1461 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
0f238ff5 1462 }
9e866774
MW		 1463}
1464
a1a5ef99 1465static void nvme_free_queues(struct nvme_dev *dev, int lowest)
22404274
KB		 1466{
1467 int i;
1468
d858e5f0 1469 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
d858e5f0 1470 dev->ctrl.queue_count--;
147b27e4 1471 nvme_free_queue(&dev->queues[i]);
121c7ad4 1472 }
22404274
KB		 1473}
1474
4d115420
KB		 1475/**
1476 * nvme_suspend_queue - put queue into suspended state
40581d1a 1477 * @nvmeq: queue to suspend
4d115420
KB		 1478 */
1479static int nvme_suspend_queue(struct nvme_queue *nvmeq)
b60503ba 1480{
4e224106 1481 if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags))
2b25d981 1482 return 1;
a09115b2 1483
4e224106 1484 /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */
d1f06f4a 1485 mb();
a09115b2 1486
4e224106 1487 nvmeq->dev->online_queues--;
1c63dc66 1488 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
6ca1d902 1489 nvme_stop_admin_queue(&nvmeq->dev->ctrl);
7c349dde
KB		 1490 if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags))
1491 pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq);
4d115420
KB		 1492 return 0;
1493}
b60503ba 1494
8fae268b
KB		 1495static void nvme_suspend_io_queues(struct nvme_dev *dev)
1496{
1497 int i;
1498
1499 for (i = dev->ctrl.queue_count - 1; i > 0; i--)
1500 nvme_suspend_queue(&dev->queues[i]);
1501}
1502
a5cdb68c 1503static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
4d115420 1504{
147b27e4 1505 struct nvme_queue *nvmeq = &dev->queues[0];
4d115420 1506
a5cdb68c
KB		 1507 if (shutdown)
1508 nvme_shutdown_ctrl(&dev->ctrl);
1509 else
b5b05048 1510 nvme_disable_ctrl(&dev->ctrl);
07836e65 1511
bf392a5d 1512 nvme_poll_irqdisable(nvmeq);
b60503ba
MW		 1513}
1514
fa46c6fb
KB		 1515/*
1516 * Called only on a device that has been disabled and after all other threads
9210c075
DZ		 1517 * that can check this device's completion queues have synced, except
1518 * nvme_poll(). This is the last chance for the driver to see a natural
1519 * completion before nvme_cancel_request() terminates all incomplete requests.
fa46c6fb
KB		 1520 */
1521static void nvme_reap_pending_cqes(struct nvme_dev *dev)
1522{
fa46c6fb
KB		 1523 int i;
1524
9210c075
DZ		 1525 for (i = dev->ctrl.queue_count - 1; i > 0; i--) {
1526 spin_lock(&dev->queues[i].cq_poll_lock);
c234a653 1527 nvme_poll_cq(&dev->queues[i], NULL);
9210c075
DZ		 1528 spin_unlock(&dev->queues[i].cq_poll_lock);
1529 }
fa46c6fb
KB		 1530}
1531
8ffaadf7
JD		 1532static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1533 int entry_size)
1534{
1535 int q_depth = dev->q_depth;
5fd4ce1b 1536 unsigned q_size_aligned = roundup(q_depth * entry_size,
6c3c05b0 1537 NVME_CTRL_PAGE_SIZE);
8ffaadf7
JD		 1538
1539 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
c45f5c99 1540 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
4e523547 1541
6c3c05b0 1542 mem_per_q = round_down(mem_per_q, NVME_CTRL_PAGE_SIZE);
c45f5c99 1543 q_depth = div_u64(mem_per_q, entry_size);
8ffaadf7
JD		 1544
1545 /*
1546 * Ensure the reduced q_depth is above some threshold where it
1547 * would be better to map queues in system memory with the
1548 * original depth
1549 */
1550 if (q_depth < 64)
1551 return -ENOMEM;
1552 }
1553
1554 return q_depth;
1555}
1556
1557static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
8a1d09a6 1558 int qid)
8ffaadf7 1559{
0f238ff5
LG		 1560 struct pci_dev *pdev = to_pci_dev(dev->dev);
1561
1562 if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
8a1d09a6 1563 nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq));
bfac8e9f
AM		 1564 if (nvmeq->sq_cmds) {
1565 nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev,
1566 nvmeq->sq_cmds);
1567 if (nvmeq->sq_dma_addr) {
1568 set_bit(NVMEQ_SQ_CMB, &nvmeq->flags);
1569 return 0;
1570 }
1571
8a1d09a6 1572 pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq));
63223078 1573 }
0f238ff5 1574 }
8ffaadf7 1575
8a1d09a6 1576 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq),
63223078 1577 &nvmeq->sq_dma_addr, GFP_KERNEL);
815c6704
KB		 1578 if (!nvmeq->sq_cmds)
1579 return -ENOMEM;
8ffaadf7
JD		 1580 return 0;
1581}
1582
a6ff7262 1583static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
b60503ba 1584{
147b27e4 1585 struct nvme_queue *nvmeq = &dev->queues[qid];
b60503ba 1586
62314e40
KB		 1587 if (dev->ctrl.queue_count > qid)
1588 return 0;
b60503ba 1589
c1e0cc7e 1590 nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES;
8a1d09a6
BH		 1591 nvmeq->q_depth = depth;
1592 nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq),
750afb08 1593 &nvmeq->cq_dma_addr, GFP_KERNEL);
b60503ba
MW		 1594 if (!nvmeq->cqes)
1595 goto free_nvmeq;
b60503ba 1596
8a1d09a6 1597 if (nvme_alloc_sq_cmds(dev, nvmeq, qid))
b60503ba
MW		 1598 goto free_cqdma;
1599
091b6092 1600 nvmeq->dev = dev;
1ab0cd69 1601 spin_lock_init(&nvmeq->sq_lock);
3a7afd8e 1602 spin_lock_init(&nvmeq->cq_poll_lock);
b60503ba 1603 nvmeq->cq_head = 0;
82123460 1604 nvmeq->cq_phase = 1;
b80d5ccc 1605 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
c30341dc 1606 nvmeq->qid = qid;
d858e5f0 1607 dev->ctrl.queue_count++;
36a7e993 1608
147b27e4 1609 return 0;
b60503ba
MW		 1610
1611 free_cqdma:
8a1d09a6
BH		 1612 dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes,
1613 nvmeq->cq_dma_addr);
b60503ba 1614 free_nvmeq:
147b27e4 1615 return -ENOMEM;
b60503ba
MW		 1616}
1617
dca51e78 1618static int queue_request_irq(struct nvme_queue *nvmeq)
3001082c 1619{
0ff199cb
CH		 1620 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1621 int nr = nvmeq->dev->ctrl.instance;
1622
1623 if (use_threaded_interrupts) {
1624 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1625 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1626 } else {
1627 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1628 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1629 }
3001082c
MW		 1630}
1631
22404274 1632static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
b60503ba 1633{
22404274 1634 struct nvme_dev *dev = nvmeq->dev;
b60503ba 1635
22404274 1636 nvmeq->sq_tail = 0;
38210800 1637 nvmeq->last_sq_tail = 0;
22404274
KB		 1638 nvmeq->cq_head = 0;
1639 nvmeq->cq_phase = 1;
b80d5ccc 1640 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
8a1d09a6 1641 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq));
f9f38e33 1642 nvme_dbbuf_init(dev, nvmeq, qid);
42f61420 1643 dev->online_queues++;
3a7afd8e 1644 wmb(); /* ensure the first interrupt sees the initialization */
22404274
KB		 1645}
1646
e4b9852a
CC		 1647/*
1648 * Try getting shutdown_lock while setting up IO queues.
1649 */
1650static int nvme_setup_io_queues_trylock(struct nvme_dev *dev)
1651{
1652 /*
1653 * Give up if the lock is being held by nvme_dev_disable.
1654 */
1655 if (!mutex_trylock(&dev->shutdown_lock))
1656 return -ENODEV;
1657
1658 /*
1659 * Controller is in wrong state, fail early.
1660 */
1661 if (dev->ctrl.state != NVME_CTRL_CONNECTING) {
1662 mutex_unlock(&dev->shutdown_lock);
1663 return -ENODEV;
1664 }
1665
1666 return 0;
1667}
1668
4b04cc6a 1669static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled)
22404274
KB		 1670{
1671 struct nvme_dev *dev = nvmeq->dev;
1672 int result;
7c349dde 1673 u16 vector = 0;
3f85d50b 1674
d1ed6aa1
CH		 1675 clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
1676
22b55601
KB		 1677 /*
1678 * A queue's vector matches the queue identifier unless the controller
1679 * has only one vector available.
1680 */
4b04cc6a
JA		 1681 if (!polled)
1682 vector = dev->num_vecs == 1 ? 0 : qid;
1683 else
7c349dde 1684 set_bit(NVMEQ_POLLED, &nvmeq->flags);
4b04cc6a 1685
a8e3e0bb 1686 result = adapter_alloc_cq(dev, qid, nvmeq, vector);
ded45505
KB		 1687 if (result)
1688 return result;
b60503ba
MW		 1689
1690 result = adapter_alloc_sq(dev, qid, nvmeq);
1691 if (result < 0)
ded45505 1692 return result;
c80b36cd 1693 if (result)
b60503ba
MW		 1694 goto release_cq;
1695
a8e3e0bb 1696 nvmeq->cq_vector = vector;
4b04cc6a 1697
e4b9852a
CC		 1698 result = nvme_setup_io_queues_trylock(dev);
1699 if (result)
1700 return result;
1701 nvme_init_queue(nvmeq, qid);
7c349dde 1702 if (!polled) {
4b04cc6a
JA		 1703 result = queue_request_irq(nvmeq);
1704 if (result < 0)
1705 goto release_sq;
1706 }
b60503ba 1707
4e224106 1708 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
e4b9852a 1709 mutex_unlock(&dev->shutdown_lock);
22404274 1710 return result;
b60503ba 1711
a8e3e0bb 1712release_sq:
f25a2dfc 1713 dev->online_queues--;
e4b9852a 1714 mutex_unlock(&dev->shutdown_lock);
b60503ba 1715 adapter_delete_sq(dev, qid);
a8e3e0bb 1716release_cq:
b60503ba 1717 adapter_delete_cq(dev, qid);
22404274 1718 return result;
b60503ba
MW		 1719}
1720
f363b089 1721static const struct blk_mq_ops nvme_mq_admin_ops = {
d29ec824 1722 .queue_rq = nvme_queue_rq,
77f02a7a 1723 .complete = nvme_pci_complete_rq,
a4aea562 1724 .init_hctx = nvme_admin_init_hctx,
e559398f 1725 .init_request = nvme_pci_init_request,
a4aea562
MB		 1726 .timeout = nvme_timeout,
1727};
1728
f363b089 1729static const struct blk_mq_ops nvme_mq_ops = {
376f7ef8 1730 .queue_rq = nvme_queue_rq,
d62cbcf6 1731 .queue_rqs = nvme_queue_rqs,
376f7ef8
CH		 1732 .complete = nvme_pci_complete_rq,
1733 .commit_rqs = nvme_commit_rqs,
1734 .init_hctx = nvme_init_hctx,
e559398f 1735 .init_request = nvme_pci_init_request,
376f7ef8
CH		 1736 .map_queues = nvme_pci_map_queues,
1737 .timeout = nvme_timeout,
1738 .poll = nvme_poll,
dabcefab
JA		 1739};
1740
ea191d2f
KB		 1741static void nvme_dev_remove_admin(struct nvme_dev *dev)
1742{
1c63dc66 1743 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
69d9a99c
KB		 1744 /*
1745 * If the controller was reset during removal, it's possible
1746 * user requests may be waiting on a stopped queue. Start the
1747 * queue to flush these to completion.
1748 */
6ca1d902 1749 nvme_start_admin_queue(&dev->ctrl);
6f8191fd 1750 blk_mq_destroy_queue(dev->ctrl.admin_q);
ea191d2f
KB		 1751 blk_mq_free_tag_set(&dev->admin_tagset);
1752 }
1753}
1754
f91b727c 1755static int nvme_pci_alloc_admin_tag_set(struct nvme_dev *dev)
a4aea562 1756{
f91b727c 1757 struct blk_mq_tag_set *set = &dev->admin_tagset;
e3e9d50c 1758
f91b727c
CH		 1759 set->ops = &nvme_mq_admin_ops;
1760 set->nr_hw_queues = 1;
a4aea562 1761
f91b727c
CH		 1762 set->queue_depth = NVME_AQ_MQ_TAG_DEPTH;
1763 set->timeout = NVME_ADMIN_TIMEOUT;
1764 set->numa_node = dev->ctrl.numa_node;
1765 set->cmd_size = sizeof(struct nvme_iod);
1766 set->flags = BLK_MQ_F_NO_SCHED;
1767 set->driver_data = dev;
a4aea562 1768
f91b727c
CH		 1769 if (blk_mq_alloc_tag_set(set))
1770 return -ENOMEM;
1771 dev->ctrl.admin_tagset = set;
a4aea562 1772
f91b727c
CH		 1773 dev->ctrl.admin_q = blk_mq_init_queue(set);
1774 if (IS_ERR(dev->ctrl.admin_q)) {
1775 blk_mq_free_tag_set(set);
1776 dev->ctrl.admin_q = NULL;
1777 return -ENOMEM;
1778 }
1779 if (!blk_get_queue(dev->ctrl.admin_q)) {
1780 nvme_dev_remove_admin(dev);
1781 dev->ctrl.admin_q = NULL;
1782 return -ENODEV;
1783 }
a4aea562
MB		 1784 return 0;
1785}
1786
97f6ef64
XY		 1787static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1788{
1789 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1790}
1791
1792static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1793{
1794 struct pci_dev *pdev = to_pci_dev(dev->dev);
1795
1796 if (size <= dev->bar_mapped_size)
1797 return 0;
1798 if (size > pci_resource_len(pdev, 0))
1799 return -ENOMEM;
1800 if (dev->bar)
1801 iounmap(dev->bar);
1802 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1803 if (!dev->bar) {
1804 dev->bar_mapped_size = 0;
1805 return -ENOMEM;
1806 }
1807 dev->bar_mapped_size = size;
1808 dev->dbs = dev->bar + NVME_REG_DBS;
1809
1810 return 0;
1811}
1812
01ad0990 1813static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
b60503ba 1814{
ba47e386 1815 int result;
b60503ba
MW		 1816 u32 aqa;
1817 struct nvme_queue *nvmeq;
1818
97f6ef64
XY		 1819 result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1820 if (result < 0)
1821 return result;
1822
8ef2074d 1823 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
20d0dfe6 1824 NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
dfbac8c7 1825
7a67cbea
CH		 1826 if (dev->subsystem &&
1827 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1828 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
dfbac8c7 1829
b5b05048 1830 result = nvme_disable_ctrl(&dev->ctrl);
ba47e386
MW		 1831 if (result < 0)
1832 return result;
b60503ba 1833
a6ff7262 1834 result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
147b27e4
SG		 1835 if (result)
1836 return result;
b60503ba 1837
635333e4
MG		 1838 dev->ctrl.numa_node = dev_to_node(dev->dev);
1839
147b27e4 1840 nvmeq = &dev->queues[0];
b60503ba
MW		 1841 aqa = nvmeq->q_depth - 1;
1842 aqa |= aqa << 16;
1843
7a67cbea
CH		 1844 writel(aqa, dev->bar + NVME_REG_AQA);
1845 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1846 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
b60503ba 1847
c0f2f45b 1848 result = nvme_enable_ctrl(&dev->ctrl);
025c557a 1849 if (result)
d4875622 1850 return result;
a4aea562 1851
2b25d981 1852 nvmeq->cq_vector = 0;
161b8be2 1853 nvme_init_queue(nvmeq, 0);
dca51e78 1854 result = queue_request_irq(nvmeq);
758dd7fd 1855 if (result) {
7c349dde 1856 dev->online_queues--;
d4875622 1857 return result;
758dd7fd 1858 }
025c557a 1859
4e224106 1860 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
b60503ba
MW		 1861 return result;
1862}
1863
749941f2 1864static int nvme_create_io_queues(struct nvme_dev *dev)
42f61420 1865{
4b04cc6a 1866 unsigned i, max, rw_queues;
749941f2 1867 int ret = 0;
42f61420 1868
d858e5f0 1869 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
a6ff7262 1870 if (nvme_alloc_queue(dev, i, dev->q_depth)) {
749941f2 1871 ret = -ENOMEM;
42f61420 1872 break;
749941f2
CH		 1873 }
1874 }
42f61420 1875
d858e5f0 1876 max = min(dev->max_qid, dev->ctrl.queue_count - 1);
e20ba6e1
CH		 1877 if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) {
1878 rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] +
1879 dev->io_queues[HCTX_TYPE_READ];
4b04cc6a
JA		 1880 } else {
1881 rw_queues = max;
1882 }
1883
949928c1 1884 for (i = dev->online_queues; i <= max; i++) {
4b04cc6a
JA		 1885 bool polled = i > rw_queues;
1886
1887 ret = nvme_create_queue(&dev->queues[i], i, polled);
d4875622 1888 if (ret)
42f61420 1889 break;
27e8166c 1890 }
749941f2
CH		 1891
1892 /*
1893 * Ignore failing Create SQ/CQ commands, we can continue with less
8adb8c14
MI		 1894 * than the desired amount of queues, and even a controller without
1895 * I/O queues can still be used to issue admin commands. This might
749941f2
CH		 1896 * be useful to upgrade a buggy firmware for example.
1897 */
1898 return ret >= 0 ? 0 : ret;
b60503ba
MW		 1899}
1900
88de4598 1901static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
8ffaadf7 1902{
88de4598
CH		 1903 u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
1904
1905 return 1ULL << (12 + 4 * szu);
1906}
1907
1908static u32 nvme_cmb_size(struct nvme_dev *dev)
1909{
1910 return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
1911}
1912
f65efd6d 1913static void nvme_map_cmb(struct nvme_dev *dev)
8ffaadf7 1914{
88de4598 1915 u64 size, offset;
8ffaadf7
JD		 1916 resource_size_t bar_size;
1917 struct pci_dev *pdev = to_pci_dev(dev->dev);
8969f1f8 1918 int bar;
8ffaadf7 1919
9fe5c59f
KB		 1920 if (dev->cmb_size)
1921 return;
1922
20d3bb92
KJ		 1923 if (NVME_CAP_CMBS(dev->ctrl.cap))
1924 writel(NVME_CMBMSC_CRE, dev->bar + NVME_REG_CMBMSC);
1925
7a67cbea 1926 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
f65efd6d
CH		 1927 if (!dev->cmbsz)
1928 return;
202021c1 1929 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
8ffaadf7 1930
88de4598
CH		 1931 size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
1932 offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
8969f1f8
CH		 1933 bar = NVME_CMB_BIR(dev->cmbloc);
1934 bar_size = pci_resource_len(pdev, bar);
8ffaadf7
JD		 1935
1936 if (offset > bar_size)
f65efd6d 1937 return;
8ffaadf7 1938
20d3bb92
KJ		 1939 /*
1940 * Tell the controller about the host side address mapping the CMB,
1941 * and enable CMB decoding for the NVMe 1.4+ scheme:
1942 */
1943 if (NVME_CAP_CMBS(dev->ctrl.cap)) {
1944 hi_lo_writeq(NVME_CMBMSC_CRE | NVME_CMBMSC_CMSE |
1945 (pci_bus_address(pdev, bar) + offset),
1946 dev->bar + NVME_REG_CMBMSC);
1947 }
1948
8ffaadf7
JD		 1949 /*
1950 * Controllers may support a CMB size larger than their BAR,
1951 * for example, due to being behind a bridge. Reduce the CMB to
1952 * the reported size of the BAR
1953 */
1954 if (size > bar_size - offset)
1955 size = bar_size - offset;
1956
0f238ff5
LG		 1957 if (pci_p2pdma_add_resource(pdev, bar, size, offset)) {
1958 dev_warn(dev->ctrl.device,
1959 "failed to register the CMB\n");
f65efd6d 1960 return;
0f238ff5
LG		 1961 }
1962
8ffaadf7 1963 dev->cmb_size = size;
0f238ff5
LG		 1964 dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS);
1965
1966 if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) ==
1967 (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS))
1968 pci_p2pmem_publish(pdev, true);
8ffaadf7
JD		 1969}
1970
87ad72a5
CH		 1971static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1972{
6c3c05b0 1973 u32 host_mem_size = dev->host_mem_size >> NVME_CTRL_PAGE_SHIFT;
4033f35d 1974 u64 dma_addr = dev->host_mem_descs_dma;
f66e2804 1975 struct nvme_command c = { };
87ad72a5
CH		 1976 int ret;
1977
87ad72a5
CH		 1978 c.features.opcode = nvme_admin_set_features;
1979 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1980 c.features.dword11 = cpu_to_le32(bits);
6c3c05b0 1981 c.features.dword12 = cpu_to_le32(host_mem_size);
87ad72a5
CH		 1982 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr));
1983 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr));
1984 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs);
1985
1986 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1987 if (ret) {
1988 dev_warn(dev->ctrl.device,
1989 "failed to set host mem (err %d, flags %#x).\n",
1990 ret, bits);
a5df5e79
KB		 1991 } else
1992 dev->hmb = bits & NVME_HOST_MEM_ENABLE;
1993
87ad72a5
CH		 1994 return ret;
1995}
1996
1997static void nvme_free_host_mem(struct nvme_dev *dev)
1998{
1999 int i;
2000
2001 for (i = 0; i < dev->nr_host_mem_descs; i++) {
2002 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
6c3c05b0 2003 size_t size = le32_to_cpu(desc->size) * NVME_CTRL_PAGE_SIZE;
87ad72a5 2004
cc667f6d
LD		 2005 dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i],
2006 le64_to_cpu(desc->addr),
2007 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
87ad72a5
CH		 2008 }
2009
2010 kfree(dev->host_mem_desc_bufs);
2011 dev->host_mem_desc_bufs = NULL;
4033f35d
CH		 2012 dma_free_coherent(dev->dev,
2013 dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
2014 dev->host_mem_descs, dev->host_mem_descs_dma);
87ad72a5 2015 dev->host_mem_descs = NULL;
7e5dd57e 2016 dev->nr_host_mem_descs = 0;
87ad72a5
CH		 2017}
2018
92dc6895
CH		 2019static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
2020 u32 chunk_size)
9d713c2b 2021{
87ad72a5 2022 struct nvme_host_mem_buf_desc *descs;
92dc6895 2023 u32 max_entries, len;
4033f35d 2024 dma_addr_t descs_dma;
2ee0e4ed 2025 int i = 0;
87ad72a5 2026 void **bufs;
6fbcde66 2027 u64 size, tmp;
87ad72a5 2028
87ad72a5
CH		 2029 tmp = (preferred + chunk_size - 1);
2030 do_div(tmp, chunk_size);
2031 max_entries = tmp;
044a9df1
CH		 2032
2033 if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
2034 max_entries = dev->ctrl.hmmaxd;
2035
750afb08
LC		 2036 descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs),
2037 &descs_dma, GFP_KERNEL);
87ad72a5
CH		 2038 if (!descs)
2039 goto out;
2040
2041 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
2042 if (!bufs)
2043 goto out_free_descs;
2044
244a8fe4 2045 for (size = 0; size < preferred && i < max_entries; size += len) {
87ad72a5
CH		 2046 dma_addr_t dma_addr;
2047
50cdb7c6 2048 len = min_t(u64, chunk_size, preferred - size);
87ad72a5
CH		 2049 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
2050 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
2051 if (!bufs[i])
2052 break;
2053
2054 descs[i].addr = cpu_to_le64(dma_addr);
6c3c05b0 2055 descs[i].size = cpu_to_le32(len / NVME_CTRL_PAGE_SIZE);
87ad72a5
CH		 2056 i++;
2057 }
2058
92dc6895 2059 if (!size)
87ad72a5 2060 goto out_free_bufs;
87ad72a5 2061
87ad72a5
CH		 2062 dev->nr_host_mem_descs = i;
2063 dev->host_mem_size = size;
2064 dev->host_mem_descs = descs;
4033f35d 2065 dev->host_mem_descs_dma = descs_dma;
87ad72a5
CH		 2066 dev->host_mem_desc_bufs = bufs;
2067 return 0;
2068
2069out_free_bufs:
2070 while (--i >= 0) {
6c3c05b0 2071 size_t size = le32_to_cpu(descs[i].size) * NVME_CTRL_PAGE_SIZE;
87ad72a5 2072
cc667f6d
LD		 2073 dma_free_attrs(dev->dev, size, bufs[i],
2074 le64_to_cpu(descs[i].addr),
2075 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
87ad72a5
CH		 2076 }
2077
2078 kfree(bufs);
2079out_free_descs:
4033f35d
CH		 2080 dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
2081 descs_dma);
87ad72a5 2082out:
87ad72a5
CH		 2083 dev->host_mem_descs = NULL;
2084 return -ENOMEM;
2085}
2086
92dc6895
CH		 2087static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
2088{
9dc54a0d
CK		 2089 u64 min_chunk = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
2090 u64 hmminds = max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
2091 u64 chunk_size;
92dc6895
CH		 2092
2093 /* start big and work our way down */
9dc54a0d 2094 for (chunk_size = min_chunk; chunk_size >= hmminds; chunk_size /= 2) {
92dc6895
CH		 2095 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
2096 if (!min || dev->host_mem_size >= min)
2097 return 0;
2098 nvme_free_host_mem(dev);
2099 }
2100 }
2101
2102 return -ENOMEM;
2103}
2104
9620cfba 2105static int nvme_setup_host_mem(struct nvme_dev *dev)
87ad72a5
CH		 2106{
2107 u64 max = (u64)max_host_mem_size_mb * SZ_1M;
2108 u64 preferred = (u64)dev->ctrl.hmpre * 4096;
2109 u64 min = (u64)dev->ctrl.hmmin * 4096;
2110 u32 enable_bits = NVME_HOST_MEM_ENABLE;
6fbcde66 2111 int ret;
87ad72a5
CH		 2112
2113 preferred = min(preferred, max);
2114 if (min > max) {
2115 dev_warn(dev->ctrl.device,
2116 "min host memory (%lld MiB) above limit (%d MiB).\n",
2117 min >> ilog2(SZ_1M), max_host_mem_size_mb);
2118 nvme_free_host_mem(dev);
9620cfba 2119 return 0;
87ad72a5
CH		 2120 }
2121
2122 /*
2123 * If we already have a buffer allocated check if we can reuse it.
2124 */
2125 if (dev->host_mem_descs) {
2126 if (dev->host_mem_size >= min)
2127 enable_bits |= NVME_HOST_MEM_RETURN;
2128 else
2129 nvme_free_host_mem(dev);
2130 }
2131
2132 if (!dev->host_mem_descs) {
92dc6895
CH		 2133 if (nvme_alloc_host_mem(dev, min, preferred)) {
2134 dev_warn(dev->ctrl.device,
2135 "failed to allocate host memory buffer.\n");
9620cfba 2136 return 0; /* controller must work without HMB */
92dc6895
CH		 2137 }
2138
2139 dev_info(dev->ctrl.device,
2140 "allocated %lld MiB host memory buffer.\n",
2141 dev->host_mem_size >> ilog2(SZ_1M));
87ad72a5
CH		 2142 }
2143
9620cfba
CH		 2144 ret = nvme_set_host_mem(dev, enable_bits);
2145 if (ret)
87ad72a5 2146 nvme_free_host_mem(dev);
9620cfba 2147 return ret;
9d713c2b
KB		 2148}
2149
0521905e
KB		 2150static ssize_t cmb_show(struct device *dev, struct device_attribute *attr,
2151 char *buf)
2152{
2153 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2154
2155 return sysfs_emit(buf, "cmbloc : x%08x\ncmbsz : x%08x\n",
2156 ndev->cmbloc, ndev->cmbsz);
2157}
2158static DEVICE_ATTR_RO(cmb);
2159
1751e97a
KB		 2160static ssize_t cmbloc_show(struct device *dev, struct device_attribute *attr,
2161 char *buf)
2162{
2163 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2164
2165 return sysfs_emit(buf, "%u\n", ndev->cmbloc);
2166}
2167static DEVICE_ATTR_RO(cmbloc);
2168
2169static ssize_t cmbsz_show(struct device *dev, struct device_attribute *attr,
2170 char *buf)
2171{
2172 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2173
2174 return sysfs_emit(buf, "%u\n", ndev->cmbsz);
2175}
2176static DEVICE_ATTR_RO(cmbsz);
2177
a5df5e79
KB		 2178static ssize_t hmb_show(struct device *dev, struct device_attribute *attr,
2179 char *buf)
2180{
2181 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2182
2183 return sysfs_emit(buf, "%d\n", ndev->hmb);
2184}
2185
2186static ssize_t hmb_store(struct device *dev, struct device_attribute *attr,
2187 const char *buf, size_t count)
2188{
2189 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2190 bool new;
2191 int ret;
2192
2193 if (strtobool(buf, &new) < 0)
2194 return -EINVAL;
2195
2196 if (new == ndev->hmb)
2197 return count;
2198
2199 if (new) {
2200 ret = nvme_setup_host_mem(ndev);
2201 } else {
2202 ret = nvme_set_host_mem(ndev, 0);
2203 if (!ret)
2204 nvme_free_host_mem(ndev);
2205 }
2206
2207 if (ret < 0)
2208 return ret;
2209
2210 return count;
2211}
2212static DEVICE_ATTR_RW(hmb);
2213
0521905e
KB		 2214static umode_t nvme_pci_attrs_are_visible(struct kobject *kobj,
2215 struct attribute *a, int n)
2216{
2217 struct nvme_ctrl *ctrl =
2218 dev_get_drvdata(container_of(kobj, struct device, kobj));
2219 struct nvme_dev *dev = to_nvme_dev(ctrl);
2220
1751e97a
KB		 2221 if (a == &dev_attr_cmb.attr ||
2222 a == &dev_attr_cmbloc.attr ||
2223 a == &dev_attr_cmbsz.attr) {
2224 if (!dev->cmbsz)
2225 return 0;
2226 }
a5df5e79
KB		 2227 if (a == &dev_attr_hmb.attr && !ctrl->hmpre)
2228 return 0;
2229
0521905e
KB		 2230 return a->mode;
2231}
2232
2233static struct attribute *nvme_pci_attrs[] = {
2234 &dev_attr_cmb.attr,
1751e97a
KB		 2235 &dev_attr_cmbloc.attr,
2236 &dev_attr_cmbsz.attr,
a5df5e79 2237 &dev_attr_hmb.attr,
0521905e
KB		 2238 NULL,
2239};
2240
2241static const struct attribute_group nvme_pci_attr_group = {
2242 .attrs = nvme_pci_attrs,
2243 .is_visible = nvme_pci_attrs_are_visible,
2244};
2245
612b7286
ML		 2246/*
2247 * nirqs is the number of interrupts available for write and read
2248 * queues. The core already reserved an interrupt for the admin queue.
2249 */
2250static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs)
3b6592f7 2251{
612b7286 2252 struct nvme_dev *dev = affd->priv;
2a5bcfdd 2253 unsigned int nr_read_queues, nr_write_queues = dev->nr_write_queues;
3b6592f7
JA		 2254
2255 /*
ee0d96d3 2256 * If there is no interrupt available for queues, ensure that
612b7286
ML		 2257 * the default queue is set to 1. The affinity set size is
2258 * also set to one, but the irq core ignores it for this case.
2259 *
2260 * If only one interrupt is available or 'write_queue' == 0, combine
2261 * write and read queues.
2262 *
2263 * If 'write_queues' > 0, ensure it leaves room for at least one read
2264 * queue.
3b6592f7 2265 */
612b7286
ML		 2266 if (!nrirqs) {
2267 nrirqs = 1;
2268 nr_read_queues = 0;
2a5bcfdd 2269 } else if (nrirqs == 1 || !nr_write_queues) {
612b7286 2270 nr_read_queues = 0;
2a5bcfdd 2271 } else if (nr_write_queues >= nrirqs) {
612b7286 2272 nr_read_queues = 1;
3b6592f7 2273 } else {
2a5bcfdd 2274 nr_read_queues = nrirqs - nr_write_queues;
3b6592f7 2275 }
612b7286
ML		 2276
2277 dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2278 affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2279 dev->io_queues[HCTX_TYPE_READ] = nr_read_queues;
2280 affd->set_size[HCTX_TYPE_READ] = nr_read_queues;
2281 affd->nr_sets = nr_read_queues ? 2 : 1;
3b6592f7
JA		 2282}
2283
6451fe73 2284static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues)
3b6592f7
JA		 2285{
2286 struct pci_dev *pdev = to_pci_dev(dev->dev);
3b6592f7 2287 struct irq_affinity affd = {
9cfef55b 2288 .pre_vectors = 1,
612b7286
ML		 2289 .calc_sets = nvme_calc_irq_sets,
2290 .priv = dev,
3b6592f7 2291 };
21cc2f3f 2292 unsigned int irq_queues, poll_queues;
6451fe73
JA		 2293
2294 /*
21cc2f3f
JX		 2295 * Poll queues don't need interrupts, but we need at least one I/O queue
2296 * left over for non-polled I/O.
6451fe73 2297 */
21cc2f3f
JX		 2298 poll_queues = min(dev->nr_poll_queues, nr_io_queues - 1);
2299 dev->io_queues[HCTX_TYPE_POLL] = poll_queues;
3b6592f7 2300
21cc2f3f
JX		 2301 /*
2302 * Initialize for the single interrupt case, will be updated in
2303 * nvme_calc_irq_sets().
2304 */
612b7286
ML		 2305 dev->io_queues[HCTX_TYPE_DEFAULT] = 1;
2306 dev->io_queues[HCTX_TYPE_READ] = 0;
3b6592f7 2307
66341331 2308 /*
21cc2f3f
JX		 2309 * We need interrupts for the admin queue and each non-polled I/O queue,
2310 * but some Apple controllers require all queues to use the first
2311 * vector.
66341331 2312 */
21cc2f3f
JX		 2313 irq_queues = 1;
2314 if (!(dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR))
2315 irq_queues += (nr_io_queues - poll_queues);
612b7286
ML		 2316 return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues,
2317 PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd);
3b6592f7
JA		 2318}
2319
8fae268b
KB		 2320static void nvme_disable_io_queues(struct nvme_dev *dev)
2321{
2322 if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq))
2323 __nvme_disable_io_queues(dev, nvme_admin_delete_cq);
2324}
2325
2a5bcfdd
WZ		 2326static unsigned int nvme_max_io_queues(struct nvme_dev *dev)
2327{
e3aef095
NS		 2328 /*
2329 * If tags are shared with admin queue (Apple bug), then
2330 * make sure we only use one IO queue.
2331 */
2332 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2333 return 1;
2a5bcfdd
WZ		 2334 return num_possible_cpus() + dev->nr_write_queues + dev->nr_poll_queues;
2335}
2336
8d85fce7 2337static int nvme_setup_io_queues(struct nvme_dev *dev)
b60503ba 2338{
147b27e4 2339 struct nvme_queue *adminq = &dev->queues[0];
e75ec752 2340 struct pci_dev *pdev = to_pci_dev(dev->dev);
2a5bcfdd 2341 unsigned int nr_io_queues;
97f6ef64 2342 unsigned long size;
2a5bcfdd 2343 int result;
b60503ba 2344
2a5bcfdd
WZ		 2345 /*
2346 * Sample the module parameters once at reset time so that we have
2347 * stable values to work with.
2348 */
2349 dev->nr_write_queues = write_queues;
2350 dev->nr_poll_queues = poll_queues;
d38e9f04 2351
e3aef095 2352 nr_io_queues = dev->nr_allocated_queues - 1;
9a0be7ab
CH		 2353 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
2354 if (result < 0)
1b23484b 2355 return result;
9a0be7ab 2356
f5fa90dc 2357 if (nr_io_queues == 0)
a5229050 2358 return 0;
53dc180e 2359
e4b9852a
CC		 2360 /*
2361 * Free IRQ resources as soon as NVMEQ_ENABLED bit transitions
2362 * from set to unset. If there is a window to it is truely freed,
2363 * pci_free_irq_vectors() jumping into this window will crash.
2364 * And take lock to avoid racing with pci_free_irq_vectors() in
2365 * nvme_dev_disable() path.
2366 */
2367 result = nvme_setup_io_queues_trylock(dev);
2368 if (result)
2369 return result;
2370 if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags))
2371 pci_free_irq(pdev, 0, adminq);
b60503ba 2372
0f238ff5 2373 if (dev->cmb_use_sqes) {
8ffaadf7
JD		 2374 result = nvme_cmb_qdepth(dev, nr_io_queues,
2375 sizeof(struct nvme_command));
2376 if (result > 0)
2377 dev->q_depth = result;
2378 else
0f238ff5 2379 dev->cmb_use_sqes = false;
8ffaadf7
JD		 2380 }
2381
97f6ef64
XY		 2382 do {
2383 size = db_bar_size(dev, nr_io_queues);
2384 result = nvme_remap_bar(dev, size);
2385 if (!result)
2386 break;
e4b9852a
CC		 2387 if (!--nr_io_queues) {
2388 result = -ENOMEM;
2389 goto out_unlock;
2390 }
97f6ef64
XY		 2391 } while (1);
2392 adminq->q_db = dev->dbs;
f1938f6e 2393
8fae268b 2394 retry:
9d713c2b 2395 /* Deregister the admin queue's interrupt */
e4b9852a
CC		 2396 if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags))
2397 pci_free_irq(pdev, 0, adminq);
9d713c2b 2398
e32efbfc
JA		 2399 /*
2400 * If we enable msix early due to not intx, disable it again before
2401 * setting up the full range we need.
2402 */
dca51e78 2403 pci_free_irq_vectors(pdev);
3b6592f7
JA		 2404
2405 result = nvme_setup_irqs(dev, nr_io_queues);
e4b9852a
CC		 2406 if (result <= 0) {
2407 result = -EIO;
2408 goto out_unlock;
2409 }
3b6592f7 2410
22b55601 2411 dev->num_vecs = result;
4b04cc6a 2412 result = max(result - 1, 1);
e20ba6e1 2413 dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL];
fa08a396 2414
063a8096
MW		 2415 /*
2416 * Should investigate if there's a performance win from allocating
2417 * more queues than interrupt vectors; it might allow the submission
2418 * path to scale better, even if the receive path is limited by the
2419 * number of interrupts.
2420 */
dca51e78 2421 result = queue_request_irq(adminq);
7c349dde 2422 if (result)
e4b9852a 2423 goto out_unlock;
4e224106 2424 set_bit(NVMEQ_ENABLED, &adminq->flags);
e4b9852a 2425 mutex_unlock(&dev->shutdown_lock);
8fae268b
KB		 2426
2427 result = nvme_create_io_queues(dev);
2428 if (result || dev->online_queues < 2)
2429 return result;
2430
2431 if (dev->online_queues - 1 < dev->max_qid) {
2432 nr_io_queues = dev->online_queues - 1;
2433 nvme_disable_io_queues(dev);
e4b9852a
CC		 2434 result = nvme_setup_io_queues_trylock(dev);
2435 if (result)
2436 return result;
8fae268b
KB		 2437 nvme_suspend_io_queues(dev);
2438 goto retry;
2439 }
2440 dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n",
2441 dev->io_queues[HCTX_TYPE_DEFAULT],
2442 dev->io_queues[HCTX_TYPE_READ],
2443 dev->io_queues[HCTX_TYPE_POLL]);
2444 return 0;
e4b9852a
CC		 2445out_unlock:
2446 mutex_unlock(&dev->shutdown_lock);
2447 return result;
b60503ba
MW		 2448}
2449
2a842aca 2450static void nvme_del_queue_end(struct request *req, blk_status_t error)
a5768aa8 2451{
db3cbfff 2452 struct nvme_queue *nvmeq = req->end_io_data;
b5875222 2453
db3cbfff 2454 blk_mq_free_request(req);
d1ed6aa1 2455 complete(&nvmeq->delete_done);
a5768aa8
KB		 2456}
2457
2a842aca 2458static void nvme_del_cq_end(struct request *req, blk_status_t error)
a5768aa8 2459{
db3cbfff 2460 struct nvme_queue *nvmeq = req->end_io_data;
a5768aa8 2461
d1ed6aa1
CH		 2462 if (error)
2463 set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
db3cbfff
KB		 2464
2465 nvme_del_queue_end(req, error);
a5768aa8
KB		 2466}
2467
db3cbfff 2468static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
bda4e0fb 2469{
db3cbfff
KB		 2470 struct request_queue *q = nvmeq->dev->ctrl.admin_q;
2471 struct request *req;
f66e2804 2472 struct nvme_command cmd = { };
bda4e0fb 2473
db3cbfff
KB		 2474 cmd.delete_queue.opcode = opcode;
2475 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
bda4e0fb 2476
e559398f 2477 req = blk_mq_alloc_request(q, nvme_req_op(&cmd), BLK_MQ_REQ_NOWAIT);
db3cbfff
KB		 2478 if (IS_ERR(req))
2479 return PTR_ERR(req);
e559398f 2480 nvme_init_request(req, &cmd);
bda4e0fb 2481
e2e53086
CH		 2482 if (opcode == nvme_admin_delete_cq)
2483 req->end_io = nvme_del_cq_end;
2484 else
2485 req->end_io = nvme_del_queue_end;
db3cbfff
KB		 2486 req->end_io_data = nvmeq;
2487
d1ed6aa1 2488 init_completion(&nvmeq->delete_done);
128126a7 2489 req->rq_flags |= RQF_QUIET;
e2e53086 2490 blk_execute_rq_nowait(req, false);
db3cbfff 2491 return 0;
bda4e0fb
KB		 2492}
2493
8fae268b 2494static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode)
a5768aa8 2495{
5271edd4 2496 int nr_queues = dev->online_queues - 1, sent = 0;
db3cbfff 2497 unsigned long timeout;
a5768aa8 2498
db3cbfff 2499 retry:
dc96f938 2500 timeout = NVME_ADMIN_TIMEOUT;
5271edd4
CH		 2501 while (nr_queues > 0) {
2502 if (nvme_delete_queue(&dev->queues[nr_queues], opcode))
2503 break;
2504 nr_queues--;
2505 sent++;
db3cbfff 2506 }
d1ed6aa1
CH		 2507 while (sent) {
2508 struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent];
2509
2510 timeout = wait_for_completion_io_timeout(&nvmeq->delete_done,
5271edd4
CH		 2511 timeout);
2512 if (timeout == 0)
2513 return false;
d1ed6aa1 2514
d1ed6aa1 2515 sent--;
5271edd4
CH		 2516 if (nr_queues)
2517 goto retry;
2518 }
2519 return true;
a5768aa8
KB		 2520}
2521
2455a4b7 2522static void nvme_pci_alloc_tag_set(struct nvme_dev *dev)
b60503ba 2523{
2455a4b7 2524 struct blk_mq_tag_set * set = &dev->tagset;
2b1b7e78
JW		 2525 int ret;
2526
2455a4b7
CH		 2527 set->ops = &nvme_mq_ops;
2528 set->nr_hw_queues = dev->online_queues - 1;
6ee742fa
KB		 2529 set->nr_maps = 1;
2530 if (dev->io_queues[HCTX_TYPE_READ])
2531 set->nr_maps = 2;
2455a4b7 2532 if (dev->io_queues[HCTX_TYPE_POLL])
6ee742fa 2533 set->nr_maps = 3;
2455a4b7
CH		 2534 set->timeout = NVME_IO_TIMEOUT;
2535 set->numa_node = dev->ctrl.numa_node;
2536 set->queue_depth = min_t(unsigned, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
2537 set->cmd_size = sizeof(struct nvme_iod);
2538 set->flags = BLK_MQ_F_SHOULD_MERGE;
2539 set->driver_data = dev;
d38e9f04 2540
2455a4b7
CH		 2541 /*
2542 * Some Apple controllers requires tags to be unique
2543 * across admin and IO queue, so reserve the first 32
2544 * tags of the IO queue.
2545 */
2546 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2547 set->reserved_tags = NVME_AQ_DEPTH;
949928c1 2548
2455a4b7
CH		 2549 ret = blk_mq_alloc_tag_set(set);
2550 if (ret) {
2551 dev_warn(dev->ctrl.device,
2552 "IO queues tagset allocation failed %d\n", ret);
2553 return;
ffe7704d 2554 }
2455a4b7
CH		 2555 dev->ctrl.tagset = set;
2556}
949928c1 2557
2455a4b7
CH		 2558static void nvme_pci_update_nr_queues(struct nvme_dev *dev)
2559{
2560 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2561 /* free previously allocated queues that are no longer usable */
2562 nvme_free_queues(dev, dev->online_queues);
b60503ba
MW		 2563}
2564
b00a726a 2565static int nvme_pci_enable(struct nvme_dev *dev)
0877cb0d 2566{
b00a726a 2567 int result = -ENOMEM;
e75ec752 2568 struct pci_dev *pdev = to_pci_dev(dev->dev);
4bdf2603 2569 int dma_address_bits = 64;
0877cb0d
KB		 2570
2571 if (pci_enable_device_mem(pdev))
2572 return result;
2573
0877cb0d 2574 pci_set_master(pdev);
0877cb0d 2575
4bdf2603
FS		 2576 if (dev->ctrl.quirks & NVME_QUIRK_DMA_ADDRESS_BITS_48)
2577 dma_address_bits = 48;
2578 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(dma_address_bits)))
052d0efa 2579 goto disable;
0877cb0d 2580
7a67cbea 2581 if (readl(dev->bar + NVME_REG_CSTS) == -1) {
0e53d180 2582 result = -ENODEV;
b00a726a 2583 goto disable;
0e53d180 2584 }
e32efbfc
JA		 2585
2586 /*
a5229050
KB		 2587 * Some devices and/or platforms don't advertise or work with INTx
2588 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2589 * adjust this later.
e32efbfc 2590 */
dca51e78
CH		 2591 result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
2592 if (result < 0)
2593 return result;
e32efbfc 2594
20d0dfe6 2595 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
7a67cbea 2596
7442ddce 2597 dev->q_depth = min_t(u32, NVME_CAP_MQES(dev->ctrl.cap) + 1,
b27c1e68 2598 io_queue_depth);
aa22c8e6 2599 dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */
20d0dfe6 2600 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
7a67cbea 2601 dev->dbs = dev->bar + 4096;
1f390c1f 2602
66341331
BH		 2603 /*
2604 * Some Apple controllers require a non-standard SQE size.
2605 * Interestingly they also seem to ignore the CC:IOSQES register
2606 * so we don't bother updating it here.
2607 */
2608 if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES)
2609 dev->io_sqes = 7;
2610 else
2611 dev->io_sqes = NVME_NVM_IOSQES;
1f390c1f
SG		 2612
2613 /*
2614 * Temporary fix for the Apple controller found in the MacBook8,1 and
2615 * some MacBook7,1 to avoid controller resets and data loss.
2616 */
2617 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
2618 dev->q_depth = 2;
9bdcfb10
CH		 2619 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
2620 "set queue depth=%u to work around controller resets\n",
1f390c1f 2621 dev->q_depth);
d554b5e1
MP		 2622 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2623 (pdev->device == 0xa821 || pdev->device == 0xa822) &&
20d0dfe6 2624 NVME_CAP_MQES(dev->ctrl.cap) == 0) {
d554b5e1
MP		 2625 dev->q_depth = 64;
2626 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2627 "set queue depth=%u\n", dev->q_depth);
1f390c1f
SG		 2628 }
2629
d38e9f04
BH		 2630 /*
2631 * Controllers with the shared tags quirk need the IO queue to be
2632 * big enough so that we get 32 tags for the admin queue
2633 */
2634 if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) &&
2635 (dev->q_depth < (NVME_AQ_DEPTH + 2))) {
2636 dev->q_depth = NVME_AQ_DEPTH + 2;
2637 dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n",
2638 dev->q_depth);
2639 }
2640
2641
f65efd6d 2642 nvme_map_cmb(dev);
202021c1 2643
a0a3408e
KB		 2644 pci_enable_pcie_error_reporting(pdev);
2645 pci_save_state(pdev);
0877cb0d
KB		 2646 return 0;
2647
2648 disable:
0877cb0d
KB		 2649 pci_disable_device(pdev);
2650 return result;
2651}
2652
2653static void nvme_dev_unmap(struct nvme_dev *dev)
b00a726a
KB		 2654{
2655 if (dev->bar)
2656 iounmap(dev->bar);
a1f447b3 2657 pci_release_mem_regions(to_pci_dev(dev->dev));
b00a726a
KB		 2658}
2659
2660static void nvme_pci_disable(struct nvme_dev *dev)
0877cb0d 2661{
e75ec752
CH		 2662 struct pci_dev *pdev = to_pci_dev(dev->dev);
2663
dca51e78 2664 pci_free_irq_vectors(pdev);
0877cb0d 2665
a0a3408e
KB		 2666 if (pci_is_enabled(pdev)) {
2667 pci_disable_pcie_error_reporting(pdev);
e75ec752 2668 pci_disable_device(pdev);
4d115420 2669 }
4d115420
KB		 2670}
2671
a5cdb68c 2672static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
b60503ba 2673{
e43269e6 2674 bool dead = true, freeze = false;
302ad8cc 2675 struct pci_dev *pdev = to_pci_dev(dev->dev);
22404274 2676
77bf25ea 2677 mutex_lock(&dev->shutdown_lock);
081f5e75
KB		 2678 if (pci_is_enabled(pdev)) {
2679 u32 csts;
2680
2681 if (pci_device_is_present(pdev))
2682 csts = readl(dev->bar + NVME_REG_CSTS);
2683 else
2684 csts = ~0;
302ad8cc 2685
ebef7368 2686 if (dev->ctrl.state == NVME_CTRL_LIVE ||
e43269e6
KB		 2687 dev->ctrl.state == NVME_CTRL_RESETTING) {
2688 freeze = true;
302ad8cc 2689 nvme_start_freeze(&dev->ctrl);
e43269e6 2690 }
302ad8cc
KB		 2691 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
2692 pdev->error_state != pci_channel_io_normal);
c9d3bf88 2693 }
c21377f8 2694
302ad8cc
KB		 2695 /*
2696 * Give the controller a chance to complete all entered requests if
2697 * doing a safe shutdown.
2698 */
e43269e6
KB		 2699 if (!dead && shutdown && freeze)
2700 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
9a915a5b
JW		 2701
2702 nvme_stop_queues(&dev->ctrl);
87ad72a5 2703
64ee0ac0 2704 if (!dead && dev->ctrl.queue_count > 0) {
8fae268b 2705 nvme_disable_io_queues(dev);
a5cdb68c 2706 nvme_disable_admin_queue(dev, shutdown);
4d115420 2707 }
8fae268b
KB		 2708 nvme_suspend_io_queues(dev);
2709 nvme_suspend_queue(&dev->queues[0]);
b00a726a 2710 nvme_pci_disable(dev);
fa46c6fb 2711 nvme_reap_pending_cqes(dev);
07836e65 2712
1fcfca78
GL		 2713 nvme_cancel_tagset(&dev->ctrl);
2714 nvme_cancel_admin_tagset(&dev->ctrl);
302ad8cc
KB		 2715
2716 /*
2717 * The driver will not be starting up queues again if shutting down so
2718 * must flush all entered requests to their failed completion to avoid
2719 * deadlocking blk-mq hot-cpu notifier.
2720 */
c8e9e9b7 2721 if (shutdown) {
302ad8cc 2722 nvme_start_queues(&dev->ctrl);
c8e9e9b7 2723 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q))
6ca1d902 2724 nvme_start_admin_queue(&dev->ctrl);
c8e9e9b7 2725 }
77bf25ea 2726 mutex_unlock(&dev->shutdown_lock);
b60503ba
MW		 2727}
2728
c1ac9a4b
KB		 2729static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown)
2730{
2731 if (!nvme_wait_reset(&dev->ctrl))
2732 return -EBUSY;
2733 nvme_dev_disable(dev, shutdown);
2734 return 0;
2735}
2736
091b6092
MW		 2737static int nvme_setup_prp_pools(struct nvme_dev *dev)
2738{
e75ec752 2739 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
c61b82c7
CH		 2740 NVME_CTRL_PAGE_SIZE,
2741 NVME_CTRL_PAGE_SIZE, 0);
091b6092
MW		 2742 if (!dev->prp_page_pool)
2743 return -ENOMEM;
2744
99802a7a 2745 /* Optimisation for I/Os between 4k and 128k */
e75ec752 2746 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
99802a7a
MW		 2747 256, 256, 0);
2748 if (!dev->prp_small_pool) {
2749 dma_pool_destroy(dev->prp_page_pool);
2750 return -ENOMEM;
2751 }
091b6092
MW		 2752 return 0;
2753}
2754
2755static void nvme_release_prp_pools(struct nvme_dev *dev)
2756{
2757 dma_pool_destroy(dev->prp_page_pool);
99802a7a 2758 dma_pool_destroy(dev->prp_small_pool);
091b6092
MW		 2759}
2760
770597ec
KB		 2761static void nvme_free_tagset(struct nvme_dev *dev)
2762{
2763 if (dev->tagset.tags)
2764 blk_mq_free_tag_set(&dev->tagset);
2765 dev->ctrl.tagset = NULL;
2766}
2767
1673f1f0 2768static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
5e82e952 2769{
1673f1f0 2770 struct nvme_dev *dev = to_nvme_dev(ctrl);
9ac27090 2771
f9f38e33 2772 nvme_dbbuf_dma_free(dev);
770597ec 2773 nvme_free_tagset(dev);
1c63dc66
CH		 2774 if (dev->ctrl.admin_q)
2775 blk_put_queue(dev->ctrl.admin_q);
e286bcfc 2776 free_opal_dev(dev->ctrl.opal_dev);
943e942e 2777 mempool_destroy(dev->iod_mempool);
253fd4ac
IR		 2778 put_device(dev->dev);
2779 kfree(dev->queues);
5e82e952
KB		 2780 kfree(dev);
2781}
2782
7c1ce408 2783static void nvme_remove_dead_ctrl(struct nvme_dev *dev)
f58944e2 2784{
c1ac9a4b
KB		 2785 /*
2786 * Set state to deleting now to avoid blocking nvme_wait_reset(), which
2787 * may be holding this pci_dev's device lock.
2788 */
2789 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
d22524a4 2790 nvme_get_ctrl(&dev->ctrl);
69d9a99c 2791 nvme_dev_disable(dev, false);
9f9cafc1 2792 nvme_kill_queues(&dev->ctrl);
03e0f3a6 2793 if (!queue_work(nvme_wq, &dev->remove_work))
f58944e2
KB		 2794 nvme_put_ctrl(&dev->ctrl);
2795}
2796
fd634f41 2797static void nvme_reset_work(struct work_struct *work)
5e82e952 2798{
d86c4d8e
CH		 2799 struct nvme_dev *dev =
2800 container_of(work, struct nvme_dev, ctrl.reset_work);
a98e58e5 2801 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
e71afda4 2802 int result;
5e82e952 2803
7764656b
ZC		 2804 if (dev->ctrl.state != NVME_CTRL_RESETTING) {
2805 dev_warn(dev->ctrl.device, "ctrl state %d is not RESETTING\n",
2806 dev->ctrl.state);
e71afda4 2807 result = -ENODEV;
fd634f41 2808 goto out;
e71afda4 2809 }
5e82e952 2810
fd634f41
CH		 2811 /*
2812 * If we're called to reset a live controller first shut it down before
2813 * moving on.
2814 */
b00a726a 2815 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
a5cdb68c 2816 nvme_dev_disable(dev, false);
d6135c3a 2817 nvme_sync_queues(&dev->ctrl);
5e82e952 2818
5c959d73 2819 mutex_lock(&dev->shutdown_lock);
b00a726a 2820 result = nvme_pci_enable(dev);
f0b50732 2821 if (result)
4726bcf3 2822 goto out_unlock;
f0b50732 2823
01ad0990 2824 result = nvme_pci_configure_admin_queue(dev);
f0b50732 2825 if (result)
4726bcf3 2826 goto out_unlock;
f0b50732 2827
f91b727c
CH		 2828 if (!dev->ctrl.admin_q) {
2829 result = nvme_pci_alloc_admin_tag_set(dev);
2830 if (result)
2831 goto out_unlock;
2832 } else {
2833 nvme_start_admin_queue(&dev->ctrl);
2834 }
b9afca3e 2835
61ce339f
RB		 2836 dma_set_min_align_mask(dev->dev, NVME_CTRL_PAGE_SIZE - 1);
2837
943e942e
JA		 2838 /*
2839 * Limit the max command size to prevent iod->sg allocations going
2840 * over a single page.
2841 */
7637de31
CH		 2842 dev->ctrl.max_hw_sectors = min_t(u32,
2843 NVME_MAX_KB_SZ << 1, dma_max_mapping_size(dev->dev) >> 9);
943e942e 2844 dev->ctrl.max_segments = NVME_MAX_SEGS;
a48bc520
CH		 2845
2846 /*
2847 * Don't limit the IOMMU merged segment size.
2848 */
2849 dma_set_max_seg_size(dev->dev, 0xffffffff);
2850
5c959d73
KB		 2851 mutex_unlock(&dev->shutdown_lock);
2852
2853 /*
2854 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
2855 * initializing procedure here.
2856 */
2857 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
2858 dev_warn(dev->ctrl.device,
2859 "failed to mark controller CONNECTING\n");
cee6c269 2860 result = -EBUSY;
5c959d73
KB		 2861 goto out;
2862 }
943e942e 2863
95093350
MG		 2864 /*
2865 * We do not support an SGL for metadata (yet), so we are limited to a
2866 * single integrity segment for the separate metadata pointer.
2867 */
2868 dev->ctrl.max_integrity_segments = 1;
2869
f21c4769 2870 result = nvme_init_ctrl_finish(&dev->ctrl);
ce4541f4 2871 if (result)
f58944e2 2872 goto out;
ce4541f4 2873
e286bcfc
SB		 2874 if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
2875 if (!dev->ctrl.opal_dev)
2876 dev->ctrl.opal_dev =
2877 init_opal_dev(&dev->ctrl, &nvme_sec_submit);
2878 else if (was_suspend)
2879 opal_unlock_from_suspend(dev->ctrl.opal_dev);
2880 } else {
2881 free_opal_dev(dev->ctrl.opal_dev);
2882 dev->ctrl.opal_dev = NULL;
4f1244c8 2883 }
a98e58e5 2884
f9f38e33
HK		 2885 if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) {
2886 result = nvme_dbbuf_dma_alloc(dev);
2887 if (result)
2888 dev_warn(dev->dev,
2889 "unable to allocate dma for dbbuf\n");
2890 }
2891
9620cfba
CH		 2892 if (dev->ctrl.hmpre) {
2893 result = nvme_setup_host_mem(dev);
2894 if (result < 0)
2895 goto out;
2896 }
87ad72a5 2897
f0b50732 2898 result = nvme_setup_io_queues(dev);
badc34d4 2899 if (result)
f58944e2 2900 goto out;
f0b50732 2901
2659e57b
CH		 2902 /*
2903 * Keep the controller around but remove all namespaces if we don't have
2904 * any working I/O queue.
2905 */
3cf519b5 2906 if (dev->online_queues < 2) {
1b3c47c1 2907 dev_warn(dev->ctrl.device, "IO queues not created\n");
3b24774e 2908 nvme_kill_queues(&dev->ctrl);
5bae7f73 2909 nvme_remove_namespaces(&dev->ctrl);
770597ec 2910 nvme_free_tagset(dev);
3cf519b5 2911 } else {
25646264 2912 nvme_start_queues(&dev->ctrl);
302ad8cc 2913 nvme_wait_freeze(&dev->ctrl);
2455a4b7
CH		 2914 if (!dev->ctrl.tagset)
2915 nvme_pci_alloc_tag_set(dev);
2916 else
2917 nvme_pci_update_nr_queues(dev);
2918 nvme_dbbuf_set(dev);
302ad8cc 2919 nvme_unfreeze(&dev->ctrl);
3cf519b5
CH		 2920 }
2921
2b1b7e78
JW		 2922 /*
2923 * If only admin queue live, keep it to do further investigation or
2924 * recovery.
2925 */
5d02a5c1 2926 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
2b1b7e78 2927 dev_warn(dev->ctrl.device,
5d02a5c1 2928 "failed to mark controller live state\n");
e71afda4 2929 result = -ENODEV;
bb8d261e
CH		 2930 goto out;
2931 }
92911a55 2932
0521905e
KB		 2933 if (!dev->attrs_added && !sysfs_create_group(&dev->ctrl.device->kobj,
2934 &nvme_pci_attr_group))
2935 dev->attrs_added = true;
2936
d09f2b45 2937 nvme_start_ctrl(&dev->ctrl);
3cf519b5 2938 return;
f0b50732 2939
4726bcf3
KB		 2940 out_unlock:
2941 mutex_unlock(&dev->shutdown_lock);
3cf519b5 2942 out:
7c1ce408
CK		 2943 if (result)
2944 dev_warn(dev->ctrl.device,
2945 "Removing after probe failure status: %d\n", result);
2946 nvme_remove_dead_ctrl(dev);
f0b50732
KB		 2947}
2948
5c8809e6 2949static void nvme_remove_dead_ctrl_work(struct work_struct *work)
9a6b9458 2950{
5c8809e6 2951 struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
e75ec752 2952 struct pci_dev *pdev = to_pci_dev(dev->dev);
9a6b9458
KB		 2953
2954 if (pci_get_drvdata(pdev))
921920ab 2955 device_release_driver(&pdev->dev);
1673f1f0 2956 nvme_put_ctrl(&dev->ctrl);
9a6b9458
KB		 2957}
2958
1c63dc66 2959static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
9ca97374 2960{
1c63dc66 2961 *val = readl(to_nvme_dev(ctrl)->bar + off);
90667892 2962 return 0;
9ca97374
TH		 2963}
2964
5fd4ce1b 2965static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
4cc06521 2966{
5fd4ce1b
CH		 2967 writel(val, to_nvme_dev(ctrl)->bar + off);
2968 return 0;
2969}
4cc06521 2970
7fd8930f
CH		 2971static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2972{
3a8ecc93 2973 *val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off);
7fd8930f 2974 return 0;
4cc06521
KB		 2975}
2976
97c12223
KB		 2977static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
2978{
2979 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2980
2db24e4a 2981 return snprintf(buf, size, "%s\n", dev_name(&pdev->dev));
97c12223
KB		 2982}
2983
2f0dad17
KB		 2984static void nvme_pci_print_device_info(struct nvme_ctrl *ctrl)
2985{
2986 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2987 struct nvme_subsystem *subsys = ctrl->subsys;
2988
2989 dev_err(ctrl->device,
2990 "VID:DID %04x:%04x model:%.*s firmware:%.*s\n",
2991 pdev->vendor, pdev->device,
2992 nvme_strlen(subsys->model, sizeof(subsys->model)),
2993 subsys->model, nvme_strlen(subsys->firmware_rev,
2994 sizeof(subsys->firmware_rev)),
2995 subsys->firmware_rev);
2996}
2997
2f859441
LG		 2998static bool nvme_pci_supports_pci_p2pdma(struct nvme_ctrl *ctrl)
2999{
3000 struct nvme_dev *dev = to_nvme_dev(ctrl);
3001
3002 return dma_pci_p2pdma_supported(dev->dev);
3003}
3004
1c63dc66 3005static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
1a353d85 3006 .name = "pcie",
e439bb12 3007 .module = THIS_MODULE,
2f859441 3008 .flags = NVME_F_METADATA_SUPPORTED,
1c63dc66 3009 .reg_read32 = nvme_pci_reg_read32,
5fd4ce1b 3010 .reg_write32 = nvme_pci_reg_write32,
7fd8930f 3011 .reg_read64 = nvme_pci_reg_read64,
1673f1f0 3012 .free_ctrl = nvme_pci_free_ctrl,
f866fc42 3013 .submit_async_event = nvme_pci_submit_async_event,
97c12223 3014 .get_address = nvme_pci_get_address,
2f0dad17 3015 .print_device_info = nvme_pci_print_device_info,
2f859441 3016 .supports_pci_p2pdma = nvme_pci_supports_pci_p2pdma,
1c63dc66 3017};
4cc06521 3018
b00a726a
KB		 3019static int nvme_dev_map(struct nvme_dev *dev)
3020{
b00a726a
KB		 3021 struct pci_dev *pdev = to_pci_dev(dev->dev);
3022
a1f447b3 3023 if (pci_request_mem_regions(pdev, "nvme"))
b00a726a
KB		 3024 return -ENODEV;
3025
97f6ef64 3026 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
b00a726a
KB		 3027 goto release;
3028
9fa196e7 3029 return 0;
b00a726a 3030 release:
9fa196e7
MG		 3031 pci_release_mem_regions(pdev);
3032 return -ENODEV;
b00a726a
KB		 3033}
3034
8427bbc2 3035static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
ff5350a8
AL		 3036{
3037 if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
3038 /*
3039 * Several Samsung devices seem to drop off the PCIe bus
3040 * randomly when APST is on and uses the deepest sleep state.
3041 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
3042 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
3043 * 950 PRO 256GB", but it seems to be restricted to two Dell
3044 * laptops.
3045 */
3046 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
3047 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
3048 dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
3049 return NVME_QUIRK_NO_DEEPEST_PS;
8427bbc2
KHF		 3050 } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
3051 /*
3052 * Samsung SSD 960 EVO drops off the PCIe bus after system
467c77d4
JJ		 3053 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
3054 * within few minutes after bootup on a Coffee Lake board -
3055 * ASUS PRIME Z370-A
8427bbc2
KHF		 3056 */
3057 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
467c77d4
JJ		 3058 (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") ||
3059 dmi_match(DMI_BOARD_NAME, "PRIME Z370-A")))
8427bbc2 3060 return NVME_QUIRK_NO_APST;
1fae37ac
S		 3061 } else if ((pdev->vendor == 0x144d && (pdev->device == 0xa801 ||
3062 pdev->device == 0xa808 || pdev->device == 0xa809)) ||
3063 (pdev->vendor == 0x1e0f && pdev->device == 0x0001)) {
3064 /*
3065 * Forcing to use host managed nvme power settings for
3066 * lowest idle power with quick resume latency on
3067 * Samsung and Toshiba SSDs based on suspend behavior
3068 * on Coffee Lake board for LENOVO C640
3069 */
3070 if ((dmi_match(DMI_BOARD_VENDOR, "LENOVO")) &&
3071 dmi_match(DMI_BOARD_NAME, "LNVNB161216"))
3072 return NVME_QUIRK_SIMPLE_SUSPEND;
ff5350a8
AL		 3073 }
3074
3075 return 0;
3076}
3077
18119775
KB		 3078static void nvme_async_probe(void *data, async_cookie_t cookie)
3079{
3080 struct nvme_dev *dev = data;
80f513b5 3081
bd46a906 3082 flush_work(&dev->ctrl.reset_work);
18119775 3083 flush_work(&dev->ctrl.scan_work);
80f513b5 3084 nvme_put_ctrl(&dev->ctrl);
18119775
KB		 3085}
3086
8d85fce7 3087static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
b60503ba 3088{
a4aea562 3089 int node, result = -ENOMEM;
b60503ba 3090 struct nvme_dev *dev;
ff5350a8 3091 unsigned long quirks = id->driver_data;
943e942e 3092 size_t alloc_size;
b60503ba 3093
a4aea562
MB		 3094 node = dev_to_node(&pdev->dev);
3095 if (node == NUMA_NO_NODE)
2fa84351 3096 set_dev_node(&pdev->dev, first_memory_node);
a4aea562
MB		 3097
3098 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
b60503ba
MW		 3099 if (!dev)
3100 return -ENOMEM;
147b27e4 3101
2a5bcfdd
WZ		 3102 dev->nr_write_queues = write_queues;
3103 dev->nr_poll_queues = poll_queues;
3104 dev->nr_allocated_queues = nvme_max_io_queues(dev) + 1;
3105 dev->queues = kcalloc_node(dev->nr_allocated_queues,
3106 sizeof(struct nvme_queue), GFP_KERNEL, node);
b60503ba
MW		 3107 if (!dev->queues)
3108 goto free;
3109
e75ec752 3110 dev->dev = get_device(&pdev->dev);
9a6b9458 3111 pci_set_drvdata(pdev, dev);
1c63dc66 3112
b00a726a
KB		 3113 result = nvme_dev_map(dev);
3114 if (result)
b00c9b7a 3115 goto put_pci;
b00a726a 3116
d86c4d8e 3117 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
5c8809e6 3118 INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
77bf25ea 3119 mutex_init(&dev->shutdown_lock);
b60503ba 3120
091b6092
MW		 3121 result = nvme_setup_prp_pools(dev);
3122 if (result)
b00c9b7a 3123 goto unmap;
4cc06521 3124
8427bbc2 3125 quirks |= check_vendor_combination_bug(pdev);
ff5350a8 3126
2744d7a0 3127 if (!noacpi && acpi_storage_d3(&pdev->dev)) {
df4f9bc4
DB		 3128 /*
3129 * Some systems use a bios work around to ask for D3 on
3130 * platforms that support kernel managed suspend.
3131 */
3132 dev_info(&pdev->dev,
3133 "platform quirk: setting simple suspend\n");
3134 quirks |= NVME_QUIRK_SIMPLE_SUSPEND;
3135 }
3136
943e942e
JA		 3137 /*
3138 * Double check that our mempool alloc size will cover the biggest
3139 * command we support.
3140 */
b13c6393 3141 alloc_size = nvme_pci_iod_alloc_size();
943e942e
JA		 3142 WARN_ON_ONCE(alloc_size > PAGE_SIZE);
3143
3144 dev->iod_mempool = mempool_create_node(1, mempool_kmalloc,
3145 mempool_kfree,
3146 (void *) alloc_size,
3147 GFP_KERNEL, node);
3148 if (!dev->iod_mempool) {
3149 result = -ENOMEM;
3150 goto release_pools;
3151 }
3152
b6e44b4c
KB		 3153 result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
3154 quirks);
3155 if (result)
3156 goto release_mempool;
3157
1b3c47c1
SG		 3158 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
3159
bd46a906 3160 nvme_reset_ctrl(&dev->ctrl);
18119775 3161 async_schedule(nvme_async_probe, dev);
4caff8fc 3162
b60503ba
MW		 3163 return 0;
3164
b6e44b4c
KB		 3165 release_mempool:
3166 mempool_destroy(dev->iod_mempool);
0877cb0d 3167 release_pools:
091b6092 3168 nvme_release_prp_pools(dev);
b00c9b7a
CJ		 3169 unmap:
3170 nvme_dev_unmap(dev);
a96d4f5c 3171 put_pci:
e75ec752 3172 put_device(dev->dev);
b60503ba
MW		 3173 free:
3174 kfree(dev->queues);
b60503ba
MW		 3175 kfree(dev);
3176 return result;
3177}
3178
775755ed 3179static void nvme_reset_prepare(struct pci_dev *pdev)
f0d54a54 3180{
a6739479 3181 struct nvme_dev *dev = pci_get_drvdata(pdev);
c1ac9a4b
KB		 3182
3183 /*
3184 * We don't need to check the return value from waiting for the reset
3185 * state as pci_dev device lock is held, making it impossible to race
3186 * with ->remove().
3187 */
3188 nvme_disable_prepare_reset(dev, false);
3189 nvme_sync_queues(&dev->ctrl);
775755ed 3190}
f0d54a54 3191
775755ed
CH		 3192static void nvme_reset_done(struct pci_dev *pdev)
3193{
f263fbb8 3194 struct nvme_dev *dev = pci_get_drvdata(pdev);
c1ac9a4b
KB		 3195
3196 if (!nvme_try_sched_reset(&dev->ctrl))
3197 flush_work(&dev->ctrl.reset_work);
f0d54a54
KB		 3198}
3199
09ece142
KB		 3200static void nvme_shutdown(struct pci_dev *pdev)
3201{
3202 struct nvme_dev *dev = pci_get_drvdata(pdev);
4e523547 3203
c1ac9a4b 3204 nvme_disable_prepare_reset(dev, true);
09ece142
KB		 3205}
3206
0521905e
KB		 3207static void nvme_remove_attrs(struct nvme_dev *dev)
3208{
3209 if (dev->attrs_added)
3210 sysfs_remove_group(&dev->ctrl.device->kobj,
3211 &nvme_pci_attr_group);
3212}
3213
f58944e2
KB		 3214/*
3215 * The driver's remove may be called on a device in a partially initialized
3216 * state. This function must not have any dependencies on the device state in
3217 * order to proceed.
3218 */
8d85fce7 3219static void nvme_remove(struct pci_dev *pdev)
b60503ba
MW		 3220{
3221 struct nvme_dev *dev = pci_get_drvdata(pdev);
9a6b9458 3222
bb8d261e 3223 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
9a6b9458 3224 pci_set_drvdata(pdev, NULL);
0ff9d4e1 3225
6db28eda 3226 if (!pci_device_is_present(pdev)) {
0ff9d4e1 3227 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
1d39e692 3228 nvme_dev_disable(dev, true);
6db28eda 3229 }
0ff9d4e1 3230
d86c4d8e 3231 flush_work(&dev->ctrl.reset_work);
d09f2b45
SG		 3232 nvme_stop_ctrl(&dev->ctrl);
3233 nvme_remove_namespaces(&dev->ctrl);
a5cdb68c 3234 nvme_dev_disable(dev, true);
0521905e 3235 nvme_remove_attrs(dev);
87ad72a5 3236 nvme_free_host_mem(dev);
a4aea562 3237 nvme_dev_remove_admin(dev);
a1a5ef99 3238 nvme_free_queues(dev, 0);
9a6b9458 3239 nvme_release_prp_pools(dev);
b00a726a 3240 nvme_dev_unmap(dev);
726612b6 3241 nvme_uninit_ctrl(&dev->ctrl);
b60503ba
MW		 3242}
3243
671a6018 3244#ifdef CONFIG_PM_SLEEP
d916b1be
KB		 3245static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps)
3246{
3247 return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps);
3248}
3249
3250static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps)
3251{
3252 return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL);
3253}
3254
3255static int nvme_resume(struct device *dev)
3256{
3257 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
3258 struct nvme_ctrl *ctrl = &ndev->ctrl;
3259
4eaefe8c 3260 if (ndev->last_ps == U32_MAX ||
d916b1be 3261 nvme_set_power_state(ctrl, ndev->last_ps) != 0)
e5ad96f3
KB		 3262 goto reset;
3263 if (ctrl->hmpre && nvme_setup_host_mem(ndev))
3264 goto reset;
3265
d916b1be 3266 return 0;
e5ad96f3
KB		 3267reset:
3268 return nvme_try_sched_reset(ctrl);
d916b1be
KB		 3269}
3270
cd638946
KB		 3271static int nvme_suspend(struct device *dev)
3272{
3273 struct pci_dev *pdev = to_pci_dev(dev);
3274 struct nvme_dev *ndev = pci_get_drvdata(pdev);
d916b1be
KB		 3275 struct nvme_ctrl *ctrl = &ndev->ctrl;
3276 int ret = -EBUSY;
3277
4eaefe8c
RW		 3278 ndev->last_ps = U32_MAX;
3279
d916b1be
KB		 3280 /*
3281 * The platform does not remove power for a kernel managed suspend so
3282 * use host managed nvme power settings for lowest idle power if
3283 * possible. This should have quicker resume latency than a full device
3284 * shutdown. But if the firmware is involved after the suspend or the
3285 * device does not support any non-default power states, shut down the
3286 * device fully.
4eaefe8c
RW		 3287 *
3288 * If ASPM is not enabled for the device, shut down the device and allow
3289 * the PCI bus layer to put it into D3 in order to take the PCIe link
3290 * down, so as to allow the platform to achieve its minimum low-power
3291 * state (which may not be possible if the link is up).
d916b1be 3292 */
4eaefe8c 3293 if (pm_suspend_via_firmware() || !ctrl->npss ||
cb32de1b 3294 !pcie_aspm_enabled(pdev) ||
c1ac9a4b
KB		 3295 (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND))
3296 return nvme_disable_prepare_reset(ndev, true);
d916b1be
KB		 3297
3298 nvme_start_freeze(ctrl);
3299 nvme_wait_freeze(ctrl);
3300 nvme_sync_queues(ctrl);
3301
5d02a5c1 3302 if (ctrl->state != NVME_CTRL_LIVE)
d916b1be
KB		 3303 goto unfreeze;
3304
e5ad96f3
KB		 3305 /*
3306 * Host memory access may not be successful in a system suspend state,
3307 * but the specification allows the controller to access memory in a
3308 * non-operational power state.
3309 */
3310 if (ndev->hmb) {
3311 ret = nvme_set_host_mem(ndev, 0);
3312 if (ret < 0)
3313 goto unfreeze;
3314 }
3315
d916b1be
KB		 3316 ret = nvme_get_power_state(ctrl, &ndev->last_ps);
3317 if (ret < 0)
3318 goto unfreeze;
3319
7cbb5c6f
ML		 3320 /*
3321 * A saved state prevents pci pm from generically controlling the
3322 * device's power. If we're using protocol specific settings, we don't
3323 * want pci interfering.
3324 */
3325 pci_save_state(pdev);
3326
d916b1be
KB		 3327 ret = nvme_set_power_state(ctrl, ctrl->npss);
3328 if (ret < 0)
3329 goto unfreeze;
3330
3331 if (ret) {
7cbb5c6f
ML		 3332 /* discard the saved state */
3333 pci_load_saved_state(pdev, NULL);
3334
d916b1be
KB		 3335 /*
3336 * Clearing npss forces a controller reset on resume. The
05d3046f 3337 * correct value will be rediscovered then.
d916b1be 3338 */
c1ac9a4b 3339 ret = nvme_disable_prepare_reset(ndev, true);
d916b1be 3340 ctrl->npss = 0;
d916b1be 3341 }
d916b1be
KB		 3342unfreeze:
3343 nvme_unfreeze(ctrl);
3344 return ret;
3345}
3346
3347static int nvme_simple_suspend(struct device *dev)
3348{
3349 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
4e523547 3350
c1ac9a4b 3351 return nvme_disable_prepare_reset(ndev, true);
cd638946
KB		 3352}
3353
d916b1be 3354static int nvme_simple_resume(struct device *dev)
cd638946
KB		 3355{
3356 struct pci_dev *pdev = to_pci_dev(dev);
3357 struct nvme_dev *ndev = pci_get_drvdata(pdev);
cd638946 3358
c1ac9a4b 3359 return nvme_try_sched_reset(&ndev->ctrl);
cd638946
KB		 3360}
3361
21774222 3362static const struct dev_pm_ops nvme_dev_pm_ops = {
d916b1be
KB		 3363 .suspend = nvme_suspend,
3364 .resume = nvme_resume,
3365 .freeze = nvme_simple_suspend,
3366 .thaw = nvme_simple_resume,
3367 .poweroff = nvme_simple_suspend,
3368 .restore = nvme_simple_resume,
3369};
3370#endif /* CONFIG_PM_SLEEP */
b60503ba 3371
a0a3408e
KB		 3372static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
3373 pci_channel_state_t state)
3374{
3375 struct nvme_dev *dev = pci_get_drvdata(pdev);
3376
3377 /*
3378 * A frozen channel requires a reset. When detected, this method will
3379 * shutdown the controller to quiesce. The controller will be restarted
3380 * after the slot reset through driver's slot_reset callback.
3381 */
a0a3408e
KB		 3382 switch (state) {
3383 case pci_channel_io_normal:
3384 return PCI_ERS_RESULT_CAN_RECOVER;
3385 case pci_channel_io_frozen:
d011fb31
KB		 3386 dev_warn(dev->ctrl.device,
3387 "frozen state error detected, reset controller\n");
a5cdb68c 3388 nvme_dev_disable(dev, false);
a0a3408e
KB		 3389 return PCI_ERS_RESULT_NEED_RESET;
3390 case pci_channel_io_perm_failure:
d011fb31
KB		 3391 dev_warn(dev->ctrl.device,
3392 "failure state error detected, request disconnect\n");
a0a3408e
KB		 3393 return PCI_ERS_RESULT_DISCONNECT;
3394 }
3395 return PCI_ERS_RESULT_NEED_RESET;
3396}
3397
3398static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
3399{
3400 struct nvme_dev *dev = pci_get_drvdata(pdev);
3401
1b3c47c1 3402 dev_info(dev->ctrl.device, "restart after slot reset\n");
a0a3408e 3403 pci_restore_state(pdev);
d86c4d8e 3404 nvme_reset_ctrl(&dev->ctrl);
a0a3408e
KB		 3405 return PCI_ERS_RESULT_RECOVERED;
3406}
3407
3408static void nvme_error_resume(struct pci_dev *pdev)
3409{
72cd4cc2
KB		 3410 struct nvme_dev *dev = pci_get_drvdata(pdev);
3411
3412 flush_work(&dev->ctrl.reset_work);
a0a3408e
KB		 3413}
3414
1d352035 3415static const struct pci_error_handlers nvme_err_handler = {
b60503ba 3416 .error_detected = nvme_error_detected,
b60503ba
MW		 3417 .slot_reset = nvme_slot_reset,
3418 .resume = nvme_error_resume,
775755ed
CH		 3419 .reset_prepare = nvme_reset_prepare,
3420 .reset_done = nvme_reset_done,
b60503ba
MW		 3421};
3422
6eb0d698 3423static const struct pci_device_id nvme_id_table[] = {
972b13e2 3424 { PCI_VDEVICE(INTEL, 0x0953), /* Intel 750/P3500/P3600/P3700 */
08095e70 3425 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 3426 NVME_QUIRK_DEALLOCATE_ZEROES, },
972b13e2 3427 { PCI_VDEVICE(INTEL, 0x0a53), /* Intel P3520 */
99466e70 3428 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 3429 NVME_QUIRK_DEALLOCATE_ZEROES, },
972b13e2 3430 { PCI_VDEVICE(INTEL, 0x0a54), /* Intel P4500/P4600 */
99466e70 3431 .driver_data = NVME_QUIRK_STRIPE_SIZE |
25e58af4
WZ		 3432 NVME_QUIRK_DEALLOCATE_ZEROES |
3433 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
972b13e2 3434 { PCI_VDEVICE(INTEL, 0x0a55), /* Dell Express Flash P4600 */
f99cb7af
DWF		 3435 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3436 NVME_QUIRK_DEALLOCATE_ZEROES, },
50af47d0 3437 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */
9abd68ef 3438 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
6c6aa2f2 3439 NVME_QUIRK_MEDIUM_PRIO_SQ |
ce4cc313
DM		 3440 NVME_QUIRK_NO_TEMP_THRESH_CHANGE |
3441 NVME_QUIRK_DISABLE_WRITE_ZEROES, },
6299358d
JD		 3442 { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */
3443 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
540c801c 3444 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */
7b210e4e 3445 .driver_data = NVME_QUIRK_IDENTIFY_CNS |
66dd346b
CH		 3446 NVME_QUIRK_DISABLE_WRITE_ZEROES |
3447 NVME_QUIRK_BOGUS_NID, },
3448 { PCI_VDEVICE(REDHAT, 0x0010), /* Qemu emulated controller */
3449 .driver_data = NVME_QUIRK_BOGUS_NID, },
5bedd3af 3450 { PCI_DEVICE(0x126f, 0x2263), /* Silicon Motion unidentified */
c98a8793
KB		 3451 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST |
3452 NVME_QUIRK_BOGUS_NID, },
0302ae60 3453 { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */
5e112d3f
JE		 3454 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
3455 NVME_QUIRK_NO_NS_DESC_LIST, },
54adc010
GP		 3456 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
3457 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
8c97eecc
JL		 3458 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */
3459 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
015282c9
WW		 3460 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
3461 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
d554b5e1
MP		 3462 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */
3463 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3464 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */
7ee5c78c 3465 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
abbb5f59 3466 NVME_QUIRK_DISABLE_WRITE_ZEROES|
7ee5c78c 3467 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
2cf7a77e
KB		 3468 { PCI_DEVICE(0x1987, 0x5012), /* Phison E12 */
3469 .driver_data = NVME_QUIRK_BOGUS_NID, },
c9e95c39 3470 { PCI_DEVICE(0x1987, 0x5016), /* Phison E16 */
73029c9b
KB		 3471 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN |
3472 NVME_QUIRK_BOGUS_NID, },
6e6a6828
PT		 3473 { PCI_DEVICE(0x1b4b, 0x1092), /* Lexar 256 GB SSD */
3474 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST |
3475 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
e1c70d79
LVS		 3476 { PCI_DEVICE(0x1cc1, 0x33f8), /* ADATA IM2P33F8ABR1 1 TB */
3477 .driver_data = NVME_QUIRK_BOGUS_NID, },
08b903b5 3478 { PCI_DEVICE(0x10ec, 0x5762), /* ADATA SX6000LNP */
1629de0e
PG		 3479 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN |
3480 NVME_QUIRK_BOGUS_NID, },
f03e42c6
GC		 3481 { PCI_DEVICE(0x1cc1, 0x8201), /* ADATA SX8200PNP 512GB */
3482 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3483 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
41f38043
LS		 3484 { PCI_DEVICE(0x1344, 0x5407), /* Micron Technology Inc NVMe SSD */
3485 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN },
5611ec2b
KHF		 3486 { PCI_DEVICE(0x1c5c, 0x1504), /* SK Hynix PC400 */
3487 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
c4f01a77
KB		 3488 { PCI_DEVICE(0x1c5c, 0x174a), /* SK Hynix P31 SSD */
3489 .driver_data = NVME_QUIRK_BOGUS_NID, },
02ca079c
KHF		 3490 { PCI_DEVICE(0x15b7, 0x2001), /* Sandisk Skyhawk */
3491 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
89919929
CK		 3492 { PCI_DEVICE(0x1d97, 0x2263), /* SPCC */
3493 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
43047e08 3494 { PCI_DEVICE(0x144d, 0xa80b), /* Samsung PM9B1 256G and 512G */
3495 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3496 { PCI_DEVICE(0x144d, 0xa809), /* Samsung MZALQ256HBJD 256G */
3497 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3498 { PCI_DEVICE(0x1cc4, 0x6303), /* UMIS RPJTJ512MGE1QDY 512G */
3499 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3500 { PCI_DEVICE(0x1cc4, 0x6302), /* UMIS RPJTJ256MGE1QDY 256G */
3501 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
dc22c1c0
ZB		 3502 { PCI_DEVICE(0x2646, 0x2262), /* KINGSTON SKC2000 NVMe SSD */
3503 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
538e4a8c
TL		 3504 { PCI_DEVICE(0x2646, 0x2263), /* KINGSTON A2000 NVMe SSD */
3505 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
70ce3455
CH		 3506 { PCI_DEVICE(0x1e4B, 0x1001), /* MAXIO MAP1001 */
3507 .driver_data = NVME_QUIRK_BOGUS_NID, },
a98a945b
CH		 3508 { PCI_DEVICE(0x1e4B, 0x1002), /* MAXIO MAP1002 */
3509 .driver_data = NVME_QUIRK_BOGUS_NID, },
3510 { PCI_DEVICE(0x1e4B, 0x1202), /* MAXIO MAP1202 */
3511 .driver_data = NVME_QUIRK_BOGUS_NID, },
3765fad5
SR		 3512 { PCI_DEVICE(0x1cc1, 0x5350), /* ADATA XPG GAMMIX S50 */
3513 .driver_data = NVME_QUIRK_BOGUS_NID, },
f37527a0
DK		 3514 { PCI_DEVICE(0x1dbe, 0x5236), /* ADATA XPG GAMMIX S70 */
3515 .driver_data = NVME_QUIRK_BOGUS_NID, },
6b961bce
NW		 3516 { PCI_DEVICE(0x1e49, 0x0041), /* ZHITAI TiPro7000 NVMe SSD */
3517 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
d6c52fa3
TG		 3518 { PCI_DEVICE(0xc0a9, 0x540a), /* Crucial P2 */
3519 .driver_data = NVME_QUIRK_BOGUS_NID, },
200dccd0
SA		 3520 { PCI_DEVICE(0x1d97, 0x2263), /* Lexar NM610 */
3521 .driver_data = NVME_QUIRK_BOGUS_NID, },
4bdf2603
FS		 3522 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0061),
3523 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3524 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0065),
3525 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3526 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x8061),
3527 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3528 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd00),
3529 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3530 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd01),
3531 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3532 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd02),
3533 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
98f7b86a
AS		 3534 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001),
3535 .driver_data = NVME_QUIRK_SINGLE_VECTOR },
124298bd 3536 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
66341331
BH		 3537 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005),
3538 .driver_data = NVME_QUIRK_SINGLE_VECTOR |
d38e9f04 3539 NVME_QUIRK_128_BYTES_SQES |
a2941f6a
KB		 3540 NVME_QUIRK_SHARED_TAGS |
3541 NVME_QUIRK_SKIP_CID_GEN },
0b85f59d 3542 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
b60503ba
MW		 3543 { 0, }
3544};
3545MODULE_DEVICE_TABLE(pci, nvme_id_table);
3546
3547static struct pci_driver nvme_driver = {
3548 .name = "nvme",
3549 .id_table = nvme_id_table,
3550 .probe = nvme_probe,
8d85fce7 3551 .remove = nvme_remove,
09ece142 3552 .shutdown = nvme_shutdown,
d916b1be 3553#ifdef CONFIG_PM_SLEEP
cd638946
KB		 3554 .driver = {
3555 .pm = &nvme_dev_pm_ops,
3556 },
d916b1be 3557#endif
74d986ab 3558 .sriov_configure = pci_sriov_configure_simple,
b60503ba
MW		 3559 .err_handler = &nvme_err_handler,
3560};
3561
3562static int __init nvme_init(void)
3563{
81101540
CH		 3564 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
3565 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
3566 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
612b7286 3567 BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2);
c372cdd1
KB		 3568 BUILD_BUG_ON(DIV_ROUND_UP(nvme_pci_npages_prp(), NVME_CTRL_PAGE_SIZE) >
3569 S8_MAX);
17c33167 3570
9a6327d2 3571 return pci_register_driver(&nvme_driver);
b60503ba
MW		 3572}
3573
3574static void __exit nvme_exit(void)
3575{
3576 pci_unregister_driver(&nvme_driver);
03e0f3a6 3577 flush_workqueue(nvme_wq);
b60503ba
MW		 3578}
3579
3580MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3581MODULE_LICENSE("GPL");
c78b4713 3582MODULE_VERSION("1.0");
b60503ba
MW		 3583module_init(nvme_init);
3584module_exit(nvme_exit);
Linux 6.x block layer and io_uring tree(s)