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blk-throttle: use queue_is_rq_based
[linux-2.6-block.git] / drivers / nvme / host / pci.c
CommitLineData
b60503ba
MW		 1/*
2 * NVM Express device driver
6eb0d698 3 * Copyright (c) 2011-2014, Intel Corporation.
b60503ba
MW		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
b60503ba
MW		 13 */
14
a0a3408e 15#include <linux/aer.h>
b60503ba 16#include <linux/blkdev.h>
a4aea562 17#include <linux/blk-mq.h>
dca51e78 18#include <linux/blk-mq-pci.h>
ff5350a8 19#include <linux/dmi.h>
b60503ba
MW		 20#include <linux/init.h>
21#include <linux/interrupt.h>
22#include <linux/io.h>
b60503ba
MW		 23#include <linux/mm.h>
24#include <linux/module.h>
77bf25ea 25#include <linux/mutex.h>
d0877473 26#include <linux/once.h>
b60503ba 27#include <linux/pci.h>
e1e5e564 28#include <linux/t10-pi.h>
b60503ba 29#include <linux/types.h>
2f8e2c87 30#include <linux/io-64-nonatomic-lo-hi.h>
a98e58e5 31#include <linux/sed-opal.h>
797a796a 32
f11bb3e2
CH		 33#include "nvme.h"
34
b60503ba
MW		 35#define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
36#define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
c965809c 37
a7a7cbe3 38#define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc))
9d43cf64 39
58ffacb5
MW		 40static int use_threaded_interrupts;
41module_param(use_threaded_interrupts, int, 0);
42
8ffaadf7
JD		 43static bool use_cmb_sqes = true;
44module_param(use_cmb_sqes, bool, 0644);
45MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
46
87ad72a5
CH		 47static unsigned int max_host_mem_size_mb = 128;
48module_param(max_host_mem_size_mb, uint, 0444);
49MODULE_PARM_DESC(max_host_mem_size_mb,
50 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
1fa6aead 51
a7a7cbe3
CK		 52static unsigned int sgl_threshold = SZ_32K;
53module_param(sgl_threshold, uint, 0644);
54MODULE_PARM_DESC(sgl_threshold,
55 "Use SGLs when average request segment size is larger or equal to "
56 "this size. Use 0 to disable SGLs.");
57
b27c1e68 58static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
59static const struct kernel_param_ops io_queue_depth_ops = {
60 .set = io_queue_depth_set,
61 .get = param_get_int,
62};
63
64static int io_queue_depth = 1024;
65module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
66MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2");
67
1c63dc66
CH		 68struct nvme_dev;
69struct nvme_queue;
b3fffdef 70
a0fa9647 71static void nvme_process_cq(struct nvme_queue *nvmeq);
a5cdb68c 72static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
d4b4ff8e 73
1c63dc66
CH		 74/*
75 * Represents an NVM Express device. Each nvme_dev is a PCI function.
76 */
77struct nvme_dev {
147b27e4 78 struct nvme_queue *queues;
1c63dc66
CH		 79 struct blk_mq_tag_set tagset;
80 struct blk_mq_tag_set admin_tagset;
81 u32 __iomem *dbs;
82 struct device *dev;
83 struct dma_pool *prp_page_pool;
84 struct dma_pool *prp_small_pool;
1c63dc66
CH		 85 unsigned online_queues;
86 unsigned max_qid;
87 int q_depth;
88 u32 db_stride;
1c63dc66 89 void __iomem *bar;
97f6ef64 90 unsigned long bar_mapped_size;
5c8809e6 91 struct work_struct remove_work;
77bf25ea 92 struct mutex shutdown_lock;
1c63dc66 93 bool subsystem;
1c63dc66 94 void __iomem *cmb;
8969f1f8 95 pci_bus_addr_t cmb_bus_addr;
1c63dc66
CH		 96 u64 cmb_size;
97 u32 cmbsz;
202021c1 98 u32 cmbloc;
1c63dc66 99 struct nvme_ctrl ctrl;
db3cbfff 100 struct completion ioq_wait;
87ad72a5
CH		 101
102 /* shadow doorbell buffer support: */
f9f38e33
HK		 103 u32 *dbbuf_dbs;
104 dma_addr_t dbbuf_dbs_dma_addr;
105 u32 *dbbuf_eis;
106 dma_addr_t dbbuf_eis_dma_addr;
87ad72a5
CH		 107
108 /* host memory buffer support: */
109 u64 host_mem_size;
110 u32 nr_host_mem_descs;
4033f35d 111 dma_addr_t host_mem_descs_dma;
87ad72a5
CH		 112 struct nvme_host_mem_buf_desc *host_mem_descs;
113 void **host_mem_desc_bufs;
4d115420 114};
1fa6aead 115
b27c1e68 116static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
117{
118 int n = 0, ret;
119
120 ret = kstrtoint(val, 10, &n);
121 if (ret != 0 || n < 2)
122 return -EINVAL;
123
124 return param_set_int(val, kp);
125}
126
f9f38e33
HK		 127static inline unsigned int sq_idx(unsigned int qid, u32 stride)
128{
129 return qid * 2 * stride;
130}
131
132static inline unsigned int cq_idx(unsigned int qid, u32 stride)
133{
134 return (qid * 2 + 1) * stride;
135}
136
1c63dc66
CH		 137static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
138{
139 return container_of(ctrl, struct nvme_dev, ctrl);
140}
141
b60503ba
MW		 142/*
143 * An NVM Express queue. Each device has at least two (one for admin
144 * commands and one for I/O commands).
145 */
146struct nvme_queue {
147 struct device *q_dmadev;
091b6092 148 struct nvme_dev *dev;
b60503ba
MW		 149 spinlock_t q_lock;
150 struct nvme_command *sq_cmds;
8ffaadf7 151 struct nvme_command __iomem *sq_cmds_io;
b60503ba 152 volatile struct nvme_completion *cqes;
42483228 153 struct blk_mq_tags **tags;
b60503ba
MW		 154 dma_addr_t sq_dma_addr;
155 dma_addr_t cq_dma_addr;
b60503ba
MW		 156 u32 __iomem *q_db;
157 u16 q_depth;
6222d172 158 s16 cq_vector;
b60503ba
MW		 159 u16 sq_tail;
160 u16 cq_head;
c30341dc 161 u16 qid;
e9539f47
MW		 162 u8 cq_phase;
163 u8 cqe_seen;
f9f38e33
HK		 164 u32 *dbbuf_sq_db;
165 u32 *dbbuf_cq_db;
166 u32 *dbbuf_sq_ei;
167 u32 *dbbuf_cq_ei;
b60503ba
MW		 168};
169
71bd150c
CH		 170/*
171 * The nvme_iod describes the data in an I/O, including the list of PRP
172 * entries. You can't see it in this data structure because C doesn't let
f4800d6d 173 * me express that. Use nvme_init_iod to ensure there's enough space
71bd150c
CH		 174 * allocated to store the PRP list.
175 */
176struct nvme_iod {
d49187e9 177 struct nvme_request req;
f4800d6d 178 struct nvme_queue *nvmeq;
a7a7cbe3 179 bool use_sgl;
f4800d6d 180 int aborted;
71bd150c 181 int npages; /* In the PRP list. 0 means small pool in use */
71bd150c
CH		 182 int nents; /* Used in scatterlist */
183 int length; /* Of data, in bytes */
184 dma_addr_t first_dma;
bf684057 185 struct scatterlist meta_sg; /* metadata requires single contiguous buffer */
f4800d6d
CH		 186 struct scatterlist *sg;
187 struct scatterlist inline_sg[0];
b60503ba
MW		 188};
189
190/*
191 * Check we didin't inadvertently grow the command struct
192 */
193static inline void _nvme_check_size(void)
194{
195 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
196 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
197 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
198 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
199 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
f8ebf840 200 BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
c30341dc 201 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
b60503ba 202 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
0add5e8e
JT		 203 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != NVME_IDENTIFY_DATA_SIZE);
204 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != NVME_IDENTIFY_DATA_SIZE);
b60503ba 205 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
6ecec745 206 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
f9f38e33
HK		 207 BUILD_BUG_ON(sizeof(struct nvme_dbbuf) != 64);
208}
209
210static inline unsigned int nvme_dbbuf_size(u32 stride)
211{
212 return ((num_possible_cpus() + 1) * 8 * stride);
213}
214
215static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
216{
217 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
218
219 if (dev->dbbuf_dbs)
220 return 0;
221
222 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
223 &dev->dbbuf_dbs_dma_addr,
224 GFP_KERNEL);
225 if (!dev->dbbuf_dbs)
226 return -ENOMEM;
227 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
228 &dev->dbbuf_eis_dma_addr,
229 GFP_KERNEL);
230 if (!dev->dbbuf_eis) {
231 dma_free_coherent(dev->dev, mem_size,
232 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
233 dev->dbbuf_dbs = NULL;
234 return -ENOMEM;
235 }
236
237 return 0;
238}
239
240static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
241{
242 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
243
244 if (dev->dbbuf_dbs) {
245 dma_free_coherent(dev->dev, mem_size,
246 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
247 dev->dbbuf_dbs = NULL;
248 }
249 if (dev->dbbuf_eis) {
250 dma_free_coherent(dev->dev, mem_size,
251 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
252 dev->dbbuf_eis = NULL;
253 }
254}
255
256static void nvme_dbbuf_init(struct nvme_dev *dev,
257 struct nvme_queue *nvmeq, int qid)
258{
259 if (!dev->dbbuf_dbs || !qid)
260 return;
261
262 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
263 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
264 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
265 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
266}
267
268static void nvme_dbbuf_set(struct nvme_dev *dev)
269{
270 struct nvme_command c;
271
272 if (!dev->dbbuf_dbs)
273 return;
274
275 memset(&c, 0, sizeof(c));
276 c.dbbuf.opcode = nvme_admin_dbbuf;
277 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
278 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
279
280 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
9bdcfb10 281 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
f9f38e33
HK		 282 /* Free memory and continue on */
283 nvme_dbbuf_dma_free(dev);
284 }
285}
286
287static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
288{
289 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
290}
291
292/* Update dbbuf and return true if an MMIO is required */
293static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
294 volatile u32 *dbbuf_ei)
295{
296 if (dbbuf_db) {
297 u16 old_value;
298
299 /*
300 * Ensure that the queue is written before updating
301 * the doorbell in memory
302 */
303 wmb();
304
305 old_value = *dbbuf_db;
306 *dbbuf_db = value;
307
308 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value))
309 return false;
310 }
311
312 return true;
b60503ba
MW		 313}
314
ac3dd5bd
JA		 315/*
316 * Max size of iod being embedded in the request payload
317 */
318#define NVME_INT_PAGES 2
5fd4ce1b 319#define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size)
ac3dd5bd
JA		 320
321/*
322 * Will slightly overestimate the number of pages needed. This is OK
323 * as it only leads to a small amount of wasted memory for the lifetime of
324 * the I/O.
325 */
326static int nvme_npages(unsigned size, struct nvme_dev *dev)
327{
5fd4ce1b
CH		 328 unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size,
329 dev->ctrl.page_size);
ac3dd5bd
JA		 330 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
331}
332
a7a7cbe3
CK		 333/*
334 * Calculates the number of pages needed for the SGL segments. For example a 4k
335 * page can accommodate 256 SGL descriptors.
336 */
337static int nvme_pci_npages_sgl(unsigned int num_seg)
ac3dd5bd 338{
a7a7cbe3 339 return DIV_ROUND_UP(num_seg * sizeof(struct nvme_sgl_desc), PAGE_SIZE);
f4800d6d 340}
ac3dd5bd 341
a7a7cbe3
CK		 342static unsigned int nvme_pci_iod_alloc_size(struct nvme_dev *dev,
343 unsigned int size, unsigned int nseg, bool use_sgl)
f4800d6d 344{
a7a7cbe3
CK		 345 size_t alloc_size;
346
347 if (use_sgl)
348 alloc_size = sizeof(__le64 *) * nvme_pci_npages_sgl(nseg);
349 else
350 alloc_size = sizeof(__le64 *) * nvme_npages(size, dev);
351
352 return alloc_size + sizeof(struct scatterlist) * nseg;
f4800d6d 353}
ac3dd5bd 354
a7a7cbe3 355static unsigned int nvme_pci_cmd_size(struct nvme_dev *dev, bool use_sgl)
f4800d6d 356{
a7a7cbe3
CK		 357 unsigned int alloc_size = nvme_pci_iod_alloc_size(dev,
358 NVME_INT_BYTES(dev), NVME_INT_PAGES,
359 use_sgl);
360
361 return sizeof(struct nvme_iod) + alloc_size;
ac3dd5bd
JA		 362}
363
a4aea562
MB		 364static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
365 unsigned int hctx_idx)
e85248e5 366{
a4aea562 367 struct nvme_dev *dev = data;
147b27e4 368 struct nvme_queue *nvmeq = &dev->queues[0];
a4aea562 369
42483228
KB		 370 WARN_ON(hctx_idx != 0);
371 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
372 WARN_ON(nvmeq->tags);
373
a4aea562 374 hctx->driver_data = nvmeq;
42483228 375 nvmeq->tags = &dev->admin_tagset.tags[0];
a4aea562 376 return 0;
e85248e5
MW		 377}
378
4af0e21c
KB		 379static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
380{
381 struct nvme_queue *nvmeq = hctx->driver_data;
382
383 nvmeq->tags = NULL;
384}
385
a4aea562
MB		 386static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
387 unsigned int hctx_idx)
b60503ba 388{
a4aea562 389 struct nvme_dev *dev = data;
147b27e4 390 struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
a4aea562 391
42483228
KB		 392 if (!nvmeq->tags)
393 nvmeq->tags = &dev->tagset.tags[hctx_idx];
b60503ba 394
42483228 395 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
a4aea562
MB		 396 hctx->driver_data = nvmeq;
397 return 0;
b60503ba
MW		 398}
399
d6296d39
CH		 400static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req,
401 unsigned int hctx_idx, unsigned int numa_node)
b60503ba 402{
d6296d39 403 struct nvme_dev *dev = set->driver_data;
f4800d6d 404 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
0350815a 405 int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0;
147b27e4 406 struct nvme_queue *nvmeq = &dev->queues[queue_idx];
a4aea562
MB		 407
408 BUG_ON(!nvmeq);
f4800d6d 409 iod->nvmeq = nvmeq;
a4aea562
MB		 410 return 0;
411}
412
dca51e78
CH		 413static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
414{
415 struct nvme_dev *dev = set->driver_data;
416
417 return blk_mq_pci_map_queues(set, to_pci_dev(dev->dev));
418}
419
b60503ba 420/**
adf68f21 421 * __nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
b60503ba
MW		 422 * @nvmeq: The queue to use
423 * @cmd: The command to send
424 *
425 * Safe to use from interrupt context
426 */
e3f879bf
SB		 427static void __nvme_submit_cmd(struct nvme_queue *nvmeq,
428 struct nvme_command *cmd)
b60503ba 429{
a4aea562
MB		 430 u16 tail = nvmeq->sq_tail;
431
8ffaadf7
JD		 432 if (nvmeq->sq_cmds_io)
433 memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd));
434 else
435 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
436
b60503ba
MW		 437 if (++tail == nvmeq->q_depth)
438 tail = 0;
f9f38e33
HK		 439 if (nvme_dbbuf_update_and_check_event(tail, nvmeq->dbbuf_sq_db,
440 nvmeq->dbbuf_sq_ei))
441 writel(tail, nvmeq->q_db);
b60503ba 442 nvmeq->sq_tail = tail;
b60503ba
MW		 443}
444
a7a7cbe3 445static void **nvme_pci_iod_list(struct request *req)
b60503ba 446{
f4800d6d 447 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3 448 return (void **)(iod->sg + blk_rq_nr_phys_segments(req));
b60503ba
MW		 449}
450
fc17b653 451static blk_status_t nvme_init_iod(struct request *rq, struct nvme_dev *dev)
ac3dd5bd 452{
f4800d6d 453 struct nvme_iod *iod = blk_mq_rq_to_pdu(rq);
f9d03f96 454 int nseg = blk_rq_nr_phys_segments(rq);
b131c61d 455 unsigned int size = blk_rq_payload_bytes(rq);
ac3dd5bd 456
f4800d6d 457 if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) {
a7a7cbe3
CK		 458 size_t alloc_size = nvme_pci_iod_alloc_size(dev, size, nseg,
459 iod->use_sgl);
460
461 iod->sg = kmalloc(alloc_size, GFP_ATOMIC);
f4800d6d 462 if (!iod->sg)
fc17b653 463 return BLK_STS_RESOURCE;
f4800d6d
CH		 464 } else {
465 iod->sg = iod->inline_sg;
ac3dd5bd
JA		 466 }
467
f4800d6d
CH		 468 iod->aborted = 0;
469 iod->npages = -1;
470 iod->nents = 0;
471 iod->length = size;
f80ec966 472
fc17b653 473 return BLK_STS_OK;
ac3dd5bd
JA		 474}
475
f4800d6d 476static void nvme_free_iod(struct nvme_dev *dev, struct request *req)
b60503ba 477{
f4800d6d 478 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3
CK		 479 const int last_prp = dev->ctrl.page_size / sizeof(__le64) - 1;
480 dma_addr_t dma_addr = iod->first_dma, next_dma_addr;
481
eca18b23 482 int i;
eca18b23
MW		 483
484 if (iod->npages == 0)
a7a7cbe3
CK		 485 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0],
486 dma_addr);
487
eca18b23 488 for (i = 0; i < iod->npages; i++) {
a7a7cbe3
CK		 489 void *addr = nvme_pci_iod_list(req)[i];
490
491 if (iod->use_sgl) {
492 struct nvme_sgl_desc *sg_list = addr;
493
494 next_dma_addr =
495 le64_to_cpu((sg_list[SGES_PER_PAGE - 1]).addr);
496 } else {
497 __le64 *prp_list = addr;
498
499 next_dma_addr = le64_to_cpu(prp_list[last_prp]);
500 }
501
502 dma_pool_free(dev->prp_page_pool, addr, dma_addr);
503 dma_addr = next_dma_addr;
eca18b23 504 }
ac3dd5bd 505
f4800d6d
CH		 506 if (iod->sg != iod->inline_sg)
507 kfree(iod->sg);
b4ff9c8d
KB		 508}
509
52b68d7e 510#ifdef CONFIG_BLK_DEV_INTEGRITY
e1e5e564
KB		 511static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
512{
513 if (be32_to_cpu(pi->ref_tag) == v)
514 pi->ref_tag = cpu_to_be32(p);
515}
516
517static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
518{
519 if (be32_to_cpu(pi->ref_tag) == p)
520 pi->ref_tag = cpu_to_be32(v);
521}
522
523/**
524 * nvme_dif_remap - remaps ref tags to bip seed and physical lba
525 *
526 * The virtual start sector is the one that was originally submitted by the
527 * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical
528 * start sector may be different. Remap protection information to match the
529 * physical LBA on writes, and back to the original seed on reads.
530 *
531 * Type 0 and 3 do not have a ref tag, so no remapping required.
532 */
533static void nvme_dif_remap(struct request *req,
534 void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
535{
536 struct nvme_ns *ns = req->rq_disk->private_data;
537 struct bio_integrity_payload *bip;
538 struct t10_pi_tuple *pi;
539 void *p, *pmap;
540 u32 i, nlb, ts, phys, virt;
541
542 if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3)
543 return;
544
545 bip = bio_integrity(req->bio);
546 if (!bip)
547 return;
548
549 pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset;
e1e5e564
KB		 550
551 p = pmap;
552 virt = bip_get_seed(bip);
553 phys = nvme_block_nr(ns, blk_rq_pos(req));
554 nlb = (blk_rq_bytes(req) >> ns->lba_shift);
ac6fc48c 555 ts = ns->disk->queue->integrity.tuple_size;
e1e5e564
KB		 556
557 for (i = 0; i < nlb; i++, virt++, phys++) {
558 pi = (struct t10_pi_tuple *)p;
559 dif_swap(phys, virt, pi);
560 p += ts;
561 }
562 kunmap_atomic(pmap);
563}
52b68d7e
KB		 564#else /* CONFIG_BLK_DEV_INTEGRITY */
565static void nvme_dif_remap(struct request *req,
566 void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
567{
568}
569static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
570{
571}
572static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
573{
574}
52b68d7e
KB		 575#endif
576
d0877473
KB		 577static void nvme_print_sgl(struct scatterlist *sgl, int nents)
578{
579 int i;
580 struct scatterlist *sg;
581
582 for_each_sg(sgl, sg, nents, i) {
583 dma_addr_t phys = sg_phys(sg);
584 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
585 "dma_address:%pad dma_length:%d\n",
586 i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
587 sg_dma_len(sg));
588 }
589}
590
a7a7cbe3
CK		 591static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
592 struct request *req, struct nvme_rw_command *cmnd)
ff22b54f 593{
f4800d6d 594 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
99802a7a 595 struct dma_pool *pool;
b131c61d 596 int length = blk_rq_payload_bytes(req);
eca18b23 597 struct scatterlist *sg = iod->sg;
ff22b54f
MW		 598 int dma_len = sg_dma_len(sg);
599 u64 dma_addr = sg_dma_address(sg);
5fd4ce1b 600 u32 page_size = dev->ctrl.page_size;
f137e0f1 601 int offset = dma_addr & (page_size - 1);
e025344c 602 __le64 *prp_list;
a7a7cbe3 603 void **list = nvme_pci_iod_list(req);
e025344c 604 dma_addr_t prp_dma;
eca18b23 605 int nprps, i;
ff22b54f 606
a7a7cbe3
CK		 607 iod->use_sgl = false;
608
1d090624 609 length -= (page_size - offset);
5228b328
JS		 610 if (length <= 0) {
611 iod->first_dma = 0;
a7a7cbe3 612 goto done;
5228b328 613 }
ff22b54f 614
1d090624 615 dma_len -= (page_size - offset);
ff22b54f 616 if (dma_len) {
1d090624 617 dma_addr += (page_size - offset);
ff22b54f
MW		 618 } else {
619 sg = sg_next(sg);
620 dma_addr = sg_dma_address(sg);
621 dma_len = sg_dma_len(sg);
622 }
623
1d090624 624 if (length <= page_size) {
edd10d33 625 iod->first_dma = dma_addr;
a7a7cbe3 626 goto done;
e025344c
SMM		 627 }
628
1d090624 629 nprps = DIV_ROUND_UP(length, page_size);
99802a7a
MW		 630 if (nprps <= (256 / 8)) {
631 pool = dev->prp_small_pool;
eca18b23 632 iod->npages = 0;
99802a7a
MW		 633 } else {
634 pool = dev->prp_page_pool;
eca18b23 635 iod->npages = 1;
99802a7a
MW		 636 }
637
69d2b571 638 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
b77954cb 639 if (!prp_list) {
edd10d33 640 iod->first_dma = dma_addr;
eca18b23 641 iod->npages = -1;
86eea289 642 return BLK_STS_RESOURCE;
b77954cb 643 }
eca18b23
MW		 644 list[0] = prp_list;
645 iod->first_dma = prp_dma;
e025344c
SMM		 646 i = 0;
647 for (;;) {
1d090624 648 if (i == page_size >> 3) {
e025344c 649 __le64 *old_prp_list = prp_list;
69d2b571 650 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
eca18b23 651 if (!prp_list)
86eea289 652 return BLK_STS_RESOURCE;
eca18b23 653 list[iod->npages++] = prp_list;
7523d834
MW		 654 prp_list[0] = old_prp_list[i - 1];
655 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
656 i = 1;
e025344c
SMM		 657 }
658 prp_list[i++] = cpu_to_le64(dma_addr);
1d090624
KB		 659 dma_len -= page_size;
660 dma_addr += page_size;
661 length -= page_size;
e025344c
SMM		 662 if (length <= 0)
663 break;
664 if (dma_len > 0)
665 continue;
86eea289
KB		 666 if (unlikely(dma_len < 0))
667 goto bad_sgl;
e025344c
SMM		 668 sg = sg_next(sg);
669 dma_addr = sg_dma_address(sg);
670 dma_len = sg_dma_len(sg);
ff22b54f
MW		 671 }
672
a7a7cbe3
CK		 673done:
674 cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
675 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
676
86eea289
KB		 677 return BLK_STS_OK;
678
679 bad_sgl:
d0877473
KB		 680 WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents),
681 "Invalid SGL for payload:%d nents:%d\n",
682 blk_rq_payload_bytes(req), iod->nents);
86eea289 683 return BLK_STS_IOERR;
ff22b54f
MW		 684}
685
a7a7cbe3
CK		 686static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
687 struct scatterlist *sg)
688{
689 sge->addr = cpu_to_le64(sg_dma_address(sg));
690 sge->length = cpu_to_le32(sg_dma_len(sg));
691 sge->type = NVME_SGL_FMT_DATA_DESC << 4;
692}
693
694static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
695 dma_addr_t dma_addr, int entries)
696{
697 sge->addr = cpu_to_le64(dma_addr);
698 if (entries < SGES_PER_PAGE) {
699 sge->length = cpu_to_le32(entries * sizeof(*sge));
700 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
701 } else {
702 sge->length = cpu_to_le32(PAGE_SIZE);
703 sge->type = NVME_SGL_FMT_SEG_DESC << 4;
704 }
705}
706
707static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
708 struct request *req, struct nvme_rw_command *cmd)
709{
710 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
711 int length = blk_rq_payload_bytes(req);
712 struct dma_pool *pool;
713 struct nvme_sgl_desc *sg_list;
714 struct scatterlist *sg = iod->sg;
715 int entries = iod->nents, i = 0;
716 dma_addr_t sgl_dma;
717
718 iod->use_sgl = true;
719
720 /* setting the transfer type as SGL */
721 cmd->flags = NVME_CMD_SGL_METABUF;
722
723 if (length == sg_dma_len(sg)) {
724 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
725 return BLK_STS_OK;
726 }
727
728 if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
729 pool = dev->prp_small_pool;
730 iod->npages = 0;
731 } else {
732 pool = dev->prp_page_pool;
733 iod->npages = 1;
734 }
735
736 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
737 if (!sg_list) {
738 iod->npages = -1;
739 return BLK_STS_RESOURCE;
740 }
741
742 nvme_pci_iod_list(req)[0] = sg_list;
743 iod->first_dma = sgl_dma;
744
745 nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
746
747 do {
748 if (i == SGES_PER_PAGE) {
749 struct nvme_sgl_desc *old_sg_desc = sg_list;
750 struct nvme_sgl_desc *link = &old_sg_desc[i - 1];
751
752 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
753 if (!sg_list)
754 return BLK_STS_RESOURCE;
755
756 i = 0;
757 nvme_pci_iod_list(req)[iod->npages++] = sg_list;
758 sg_list[i++] = *link;
759 nvme_pci_sgl_set_seg(link, sgl_dma, entries);
760 }
761
762 nvme_pci_sgl_set_data(&sg_list[i++], sg);
763
764 length -= sg_dma_len(sg);
765 sg = sg_next(sg);
766 entries--;
767 } while (length > 0);
768
769 WARN_ON(entries > 0);
770 return BLK_STS_OK;
771}
772
773static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req)
774{
775 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
776 unsigned int avg_seg_size;
777
778 avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req),
779 blk_rq_nr_phys_segments(req));
780
781 if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1))))
782 return false;
783 if (!iod->nvmeq->qid)
784 return false;
785 if (!sgl_threshold || avg_seg_size < sgl_threshold)
786 return false;
787 return true;
788}
789
fc17b653 790static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
b131c61d 791 struct nvme_command *cmnd)
d29ec824 792{
f4800d6d 793 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
ba1ca37e
CH		 794 struct request_queue *q = req->q;
795 enum dma_data_direction dma_dir = rq_data_dir(req) ?
796 DMA_TO_DEVICE : DMA_FROM_DEVICE;
fc17b653 797 blk_status_t ret = BLK_STS_IOERR;
d29ec824 798
f9d03f96 799 sg_init_table(iod->sg, blk_rq_nr_phys_segments(req));
ba1ca37e
CH		 800 iod->nents = blk_rq_map_sg(q, req, iod->sg);
801 if (!iod->nents)
802 goto out;
d29ec824 803
fc17b653 804 ret = BLK_STS_RESOURCE;
2b6b535d
MFO		 805 if (!dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, dma_dir,
806 DMA_ATTR_NO_WARN))
ba1ca37e 807 goto out;
d29ec824 808
a7a7cbe3
CK		 809 if (nvme_pci_use_sgls(dev, req))
810 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw);
811 else
812 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
813
86eea289 814 if (ret != BLK_STS_OK)
ba1ca37e 815 goto out_unmap;
0e5e4f0e 816
fc17b653 817 ret = BLK_STS_IOERR;
ba1ca37e
CH		 818 if (blk_integrity_rq(req)) {
819 if (blk_rq_count_integrity_sg(q, req->bio) != 1)
820 goto out_unmap;
0e5e4f0e 821
bf684057
CH		 822 sg_init_table(&iod->meta_sg, 1);
823 if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1)
ba1ca37e 824 goto out_unmap;
0e5e4f0e 825
b5d8af5b 826 if (req_op(req) == REQ_OP_WRITE)
ba1ca37e 827 nvme_dif_remap(req, nvme_dif_prep);
0e5e4f0e 828
bf684057 829 if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir))
ba1ca37e 830 goto out_unmap;
d29ec824 831 }
00df5cb4 832
ba1ca37e 833 if (blk_integrity_rq(req))
bf684057 834 cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg));
fc17b653 835 return BLK_STS_OK;
00df5cb4 836
ba1ca37e
CH		 837out_unmap:
838 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
839out:
840 return ret;
00df5cb4
MW		 841}
842
f4800d6d 843static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
b60503ba 844{
f4800d6d 845 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
d4f6c3ab
CH		 846 enum dma_data_direction dma_dir = rq_data_dir(req) ?
847 DMA_TO_DEVICE : DMA_FROM_DEVICE;
848
849 if (iod->nents) {
850 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
851 if (blk_integrity_rq(req)) {
b5d8af5b 852 if (req_op(req) == REQ_OP_READ)
d4f6c3ab 853 nvme_dif_remap(req, nvme_dif_complete);
bf684057 854 dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir);
e1e5e564 855 }
e19b127f 856 }
e1e5e564 857
f9d03f96 858 nvme_cleanup_cmd(req);
f4800d6d 859 nvme_free_iod(dev, req);
d4f6c3ab 860}
b60503ba 861
d29ec824
CH		 862/*
863 * NOTE: ns is NULL when called on the admin queue.
864 */
fc17b653 865static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
a4aea562 866 const struct blk_mq_queue_data *bd)
edd10d33 867{
a4aea562
MB		 868 struct nvme_ns *ns = hctx->queue->queuedata;
869 struct nvme_queue *nvmeq = hctx->driver_data;
d29ec824 870 struct nvme_dev *dev = nvmeq->dev;
a4aea562 871 struct request *req = bd->rq;
ba1ca37e 872 struct nvme_command cmnd;
ebe6d874 873 blk_status_t ret;
e1e5e564 874
f9d03f96 875 ret = nvme_setup_cmd(ns, req, &cmnd);
fc17b653 876 if (ret)
f4800d6d 877 return ret;
a4aea562 878
b131c61d 879 ret = nvme_init_iod(req, dev);
fc17b653 880 if (ret)
f9d03f96 881 goto out_free_cmd;
a4aea562 882
fc17b653 883 if (blk_rq_nr_phys_segments(req)) {
b131c61d 884 ret = nvme_map_data(dev, req, &cmnd);
fc17b653
CH		 885 if (ret)
886 goto out_cleanup_iod;
887 }
a4aea562 888
aae239e1 889 blk_mq_start_request(req);
a4aea562 890
ba1ca37e 891 spin_lock_irq(&nvmeq->q_lock);
ae1fba20 892 if (unlikely(nvmeq->cq_vector < 0)) {
fc17b653 893 ret = BLK_STS_IOERR;
ae1fba20 894 spin_unlock_irq(&nvmeq->q_lock);
f9d03f96 895 goto out_cleanup_iod;
ae1fba20 896 }
ba1ca37e 897 __nvme_submit_cmd(nvmeq, &cmnd);
a4aea562
MB		 898 nvme_process_cq(nvmeq);
899 spin_unlock_irq(&nvmeq->q_lock);
fc17b653 900 return BLK_STS_OK;
f9d03f96 901out_cleanup_iod:
f4800d6d 902 nvme_free_iod(dev, req);
f9d03f96
CH		 903out_free_cmd:
904 nvme_cleanup_cmd(req);
ba1ca37e 905 return ret;
b60503ba 906}
e1e5e564 907
77f02a7a 908static void nvme_pci_complete_rq(struct request *req)
eee417b0 909{
f4800d6d 910 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a4aea562 911
77f02a7a
CH		 912 nvme_unmap_data(iod->nvmeq->dev, req);
913 nvme_complete_rq(req);
b60503ba
MW		 914}
915
d783e0bd
MR		 916/* We read the CQE phase first to check if the rest of the entry is valid */
917static inline bool nvme_cqe_valid(struct nvme_queue *nvmeq, u16 head,
918 u16 phase)
919{
920 return (le16_to_cpu(nvmeq->cqes[head].status) & 1) == phase;
921}
922
eb281c82 923static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
b60503ba 924{
eb281c82 925 u16 head = nvmeq->cq_head;
adf68f21 926
eb281c82
SG		 927 if (likely(nvmeq->cq_vector >= 0)) {
928 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
929 nvmeq->dbbuf_cq_ei))
930 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
931 }
932}
aae239e1 933
83a12fb7
SG		 934static inline void nvme_handle_cqe(struct nvme_queue *nvmeq,
935 struct nvme_completion *cqe)
936{
937 struct request *req;
adf68f21 938
83a12fb7
SG		 939 if (unlikely(cqe->command_id >= nvmeq->q_depth)) {
940 dev_warn(nvmeq->dev->ctrl.device,
941 "invalid id %d completed on queue %d\n",
942 cqe->command_id, le16_to_cpu(cqe->sq_id));
943 return;
b60503ba
MW		 944 }
945
83a12fb7
SG		 946 /*
947 * AEN requests are special as they don't time out and can
948 * survive any kind of queue freeze and often don't respond to
949 * aborts. We don't even bother to allocate a struct request
950 * for them but rather special case them here.
951 */
952 if (unlikely(nvmeq->qid == 0 &&
38dabe21 953 cqe->command_id >= NVME_AQ_BLK_MQ_DEPTH)) {
83a12fb7
SG		 954 nvme_complete_async_event(&nvmeq->dev->ctrl,
955 cqe->status, &cqe->result);
a0fa9647 956 return;
83a12fb7 957 }
b60503ba 958
e9d8a0fd 959 nvmeq->cqe_seen = 1;
83a12fb7
SG		 960 req = blk_mq_tag_to_rq(*nvmeq->tags, cqe->command_id);
961 nvme_end_request(req, cqe->status, cqe->result);
962}
b60503ba 963
920d13a8
SG		 964static inline bool nvme_read_cqe(struct nvme_queue *nvmeq,
965 struct nvme_completion *cqe)
b60503ba 966{
920d13a8
SG		 967 if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase)) {
968 *cqe = nvmeq->cqes[nvmeq->cq_head];
adf68f21 969
920d13a8
SG		 970 if (++nvmeq->cq_head == nvmeq->q_depth) {
971 nvmeq->cq_head = 0;
972 nvmeq->cq_phase = !nvmeq->cq_phase;
b60503ba 973 }
920d13a8 974 return true;
b60503ba 975 }
920d13a8 976 return false;
a0fa9647
JA		 977}
978
979static void nvme_process_cq(struct nvme_queue *nvmeq)
980{
920d13a8
SG		 981 struct nvme_completion cqe;
982 int consumed = 0;
b60503ba 983
920d13a8
SG		 984 while (nvme_read_cqe(nvmeq, &cqe)) {
985 nvme_handle_cqe(nvmeq, &cqe);
986 consumed++;
920d13a8 987 }
eb281c82 988
e9d8a0fd 989 if (consumed)
920d13a8 990 nvme_ring_cq_doorbell(nvmeq);
b60503ba
MW		 991}
992
993static irqreturn_t nvme_irq(int irq, void *data)
58ffacb5
MW		 994{
995 irqreturn_t result;
996 struct nvme_queue *nvmeq = data;
997 spin_lock(&nvmeq->q_lock);
e9539f47
MW		 998 nvme_process_cq(nvmeq);
999 result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE;
1000 nvmeq->cqe_seen = 0;
58ffacb5
MW		 1001 spin_unlock(&nvmeq->q_lock);
1002 return result;
1003}
1004
1005static irqreturn_t nvme_irq_check(int irq, void *data)
1006{
1007 struct nvme_queue *nvmeq = data;
d783e0bd
MR		 1008 if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase))
1009 return IRQ_WAKE_THREAD;
1010 return IRQ_NONE;
58ffacb5
MW		 1011}
1012
7776db1c 1013static int __nvme_poll(struct nvme_queue *nvmeq, unsigned int tag)
a0fa9647 1014{
442e19b7
SG		 1015 struct nvme_completion cqe;
1016 int found = 0, consumed = 0;
a0fa9647 1017
442e19b7
SG		 1018 if (!nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase))
1019 return 0;
a0fa9647 1020
442e19b7
SG		 1021 spin_lock_irq(&nvmeq->q_lock);
1022 while (nvme_read_cqe(nvmeq, &cqe)) {
1023 nvme_handle_cqe(nvmeq, &cqe);
1024 consumed++;
1025
1026 if (tag == cqe.command_id) {
1027 found = 1;
1028 break;
1029 }
1030 }
1031
1032 if (consumed)
1033 nvme_ring_cq_doorbell(nvmeq);
1034 spin_unlock_irq(&nvmeq->q_lock);
1035
1036 return found;
a0fa9647
JA		 1037}
1038
7776db1c
KB		 1039static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag)
1040{
1041 struct nvme_queue *nvmeq = hctx->driver_data;
1042
1043 return __nvme_poll(nvmeq, tag);
1044}
1045
ad22c355 1046static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
b60503ba 1047{
f866fc42 1048 struct nvme_dev *dev = to_nvme_dev(ctrl);
147b27e4 1049 struct nvme_queue *nvmeq = &dev->queues[0];
a4aea562 1050 struct nvme_command c;
b60503ba 1051
a4aea562
MB		 1052 memset(&c, 0, sizeof(c));
1053 c.common.opcode = nvme_admin_async_event;
ad22c355 1054 c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
3c0cf138 1055
9396dec9 1056 spin_lock_irq(&nvmeq->q_lock);
f866fc42 1057 __nvme_submit_cmd(nvmeq, &c);
9396dec9 1058 spin_unlock_irq(&nvmeq->q_lock);
f705f837
CH		 1059}
1060
b60503ba 1061static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
f705f837 1062{
b60503ba
MW		 1063 struct nvme_command c;
1064
1065 memset(&c, 0, sizeof(c));
1066 c.delete_queue.opcode = opcode;
1067 c.delete_queue.qid = cpu_to_le16(id);
1068
1c63dc66 1069 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1070}
1071
b60503ba
MW		 1072static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
1073 struct nvme_queue *nvmeq)
1074{
b60503ba
MW		 1075 struct nvme_command c;
1076 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
1077
d29ec824 1078 /*
16772ae6 1079 * Note: we (ab)use the fact that the prp fields survive if no data
d29ec824
CH		 1080 * is attached to the request.
1081 */
b60503ba
MW		 1082 memset(&c, 0, sizeof(c));
1083 c.create_cq.opcode = nvme_admin_create_cq;
1084 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1085 c.create_cq.cqid = cpu_to_le16(qid);
1086 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1087 c.create_cq.cq_flags = cpu_to_le16(flags);
1088 c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
1089
1c63dc66 1090 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1091}
1092
1093static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1094 struct nvme_queue *nvmeq)
1095{
b60503ba 1096 struct nvme_command c;
81c1cd98 1097 int flags = NVME_QUEUE_PHYS_CONTIG;
b60503ba 1098
d29ec824 1099 /*
16772ae6 1100 * Note: we (ab)use the fact that the prp fields survive if no data
d29ec824
CH		 1101 * is attached to the request.
1102 */
b60503ba
MW		 1103 memset(&c, 0, sizeof(c));
1104 c.create_sq.opcode = nvme_admin_create_sq;
1105 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1106 c.create_sq.sqid = cpu_to_le16(qid);
1107 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1108 c.create_sq.sq_flags = cpu_to_le16(flags);
1109 c.create_sq.cqid = cpu_to_le16(qid);
1110
1c63dc66 1111 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1112}
1113
1114static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1115{
1116 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1117}
1118
1119static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1120{
1121 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1122}
1123
2a842aca 1124static void abort_endio(struct request *req, blk_status_t error)
bc5fc7e4 1125{
f4800d6d
CH		 1126 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1127 struct nvme_queue *nvmeq = iod->nvmeq;
e44ac588 1128
27fa9bc5
CH		 1129 dev_warn(nvmeq->dev->ctrl.device,
1130 "Abort status: 0x%x", nvme_req(req)->status);
e7a2a87d 1131 atomic_inc(&nvmeq->dev->ctrl.abort_limit);
e7a2a87d 1132 blk_mq_free_request(req);
bc5fc7e4
MW		 1133}
1134
b2a0eb1a
KB		 1135static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1136{
1137
1138 /* If true, indicates loss of adapter communication, possibly by a
1139 * NVMe Subsystem reset.
1140 */
1141 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1142
1143 /* If there is a reset ongoing, we shouldn't reset again. */
1144 if (dev->ctrl.state == NVME_CTRL_RESETTING)
1145 return false;
1146
1147 /* We shouldn't reset unless the controller is on fatal error state
1148 * _or_ if we lost the communication with it.
1149 */
1150 if (!(csts & NVME_CSTS_CFS) && !nssro)
1151 return false;
1152
1153 /* If PCI error recovery process is happening, we cannot reset or
1154 * the recovery mechanism will surely fail.
1155 */
1156 if (pci_channel_offline(to_pci_dev(dev->dev)))
1157 return false;
1158
1159 return true;
1160}
1161
1162static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1163{
1164 /* Read a config register to help see what died. */
1165 u16 pci_status;
1166 int result;
1167
1168 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1169 &pci_status);
1170 if (result == PCIBIOS_SUCCESSFUL)
1171 dev_warn(dev->ctrl.device,
1172 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1173 csts, pci_status);
1174 else
1175 dev_warn(dev->ctrl.device,
1176 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1177 csts, result);
1178}
1179
31c7c7d2 1180static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
c30341dc 1181{
f4800d6d
CH		 1182 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1183 struct nvme_queue *nvmeq = iod->nvmeq;
c30341dc 1184 struct nvme_dev *dev = nvmeq->dev;
a4aea562 1185 struct request *abort_req;
a4aea562 1186 struct nvme_command cmd;
b2a0eb1a
KB		 1187 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1188
1189 /*
1190 * Reset immediately if the controller is failed
1191 */
1192 if (nvme_should_reset(dev, csts)) {
1193 nvme_warn_reset(dev, csts);
1194 nvme_dev_disable(dev, false);
d86c4d8e 1195 nvme_reset_ctrl(&dev->ctrl);
b2a0eb1a
KB		 1196 return BLK_EH_HANDLED;
1197 }
c30341dc 1198
7776db1c
KB		 1199 /*
1200 * Did we miss an interrupt?
1201 */
1202 if (__nvme_poll(nvmeq, req->tag)) {
1203 dev_warn(dev->ctrl.device,
1204 "I/O %d QID %d timeout, completion polled\n",
1205 req->tag, nvmeq->qid);
1206 return BLK_EH_HANDLED;
1207 }
1208
31c7c7d2 1209 /*
fd634f41
CH		 1210 * Shutdown immediately if controller times out while starting. The
1211 * reset work will see the pci device disabled when it gets the forced
1212 * cancellation error. All outstanding requests are completed on
1213 * shutdown, so we return BLK_EH_HANDLED.
1214 */
bb8d261e 1215 if (dev->ctrl.state == NVME_CTRL_RESETTING) {
1b3c47c1 1216 dev_warn(dev->ctrl.device,
fd634f41
CH		 1217 "I/O %d QID %d timeout, disable controller\n",
1218 req->tag, nvmeq->qid);
a5cdb68c 1219 nvme_dev_disable(dev, false);
27fa9bc5 1220 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
fd634f41 1221 return BLK_EH_HANDLED;
c30341dc
KB		 1222 }
1223
fd634f41
CH		 1224 /*
1225 * Shutdown the controller immediately and schedule a reset if the
1226 * command was already aborted once before and still hasn't been
1227 * returned to the driver, or if this is the admin queue.
31c7c7d2 1228 */
f4800d6d 1229 if (!nvmeq->qid || iod->aborted) {
1b3c47c1 1230 dev_warn(dev->ctrl.device,
e1569a16
KB		 1231 "I/O %d QID %d timeout, reset controller\n",
1232 req->tag, nvmeq->qid);
a5cdb68c 1233 nvme_dev_disable(dev, false);
d86c4d8e 1234 nvme_reset_ctrl(&dev->ctrl);
c30341dc 1235
e1569a16
KB		 1236 /*
1237 * Mark the request as handled, since the inline shutdown
1238 * forces all outstanding requests to complete.
1239 */
27fa9bc5 1240 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
e1569a16 1241 return BLK_EH_HANDLED;
c30341dc 1242 }
c30341dc 1243
e7a2a87d 1244 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
6bf25d16 1245 atomic_inc(&dev->ctrl.abort_limit);
31c7c7d2 1246 return BLK_EH_RESET_TIMER;
6bf25d16 1247 }
7bf7d778 1248 iod->aborted = 1;
a4aea562 1249
c30341dc
KB		 1250 memset(&cmd, 0, sizeof(cmd));
1251 cmd.abort.opcode = nvme_admin_abort_cmd;
a4aea562 1252 cmd.abort.cid = req->tag;
c30341dc 1253 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
c30341dc 1254
1b3c47c1
SG		 1255 dev_warn(nvmeq->dev->ctrl.device,
1256 "I/O %d QID %d timeout, aborting\n",
1257 req->tag, nvmeq->qid);
e7a2a87d
CH		 1258
1259 abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
eb71f435 1260 BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
e7a2a87d
CH		 1261 if (IS_ERR(abort_req)) {
1262 atomic_inc(&dev->ctrl.abort_limit);
1263 return BLK_EH_RESET_TIMER;
1264 }
1265
1266 abort_req->timeout = ADMIN_TIMEOUT;
1267 abort_req->end_io_data = NULL;
1268 blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio);
c30341dc 1269
31c7c7d2
CH		 1270 /*
1271 * The aborted req will be completed on receiving the abort req.
1272 * We enable the timer again. If hit twice, it'll cause a device reset,
1273 * as the device then is in a faulty state.
1274 */
1275 return BLK_EH_RESET_TIMER;
c30341dc
KB		 1276}
1277
a4aea562
MB		 1278static void nvme_free_queue(struct nvme_queue *nvmeq)
1279{
9e866774
MW		 1280 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1281 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
8ffaadf7
JD		 1282 if (nvmeq->sq_cmds)
1283 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
9e866774 1284 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
9e866774
MW		 1285}
1286
a1a5ef99 1287static void nvme_free_queues(struct nvme_dev *dev, int lowest)
22404274
KB		 1288{
1289 int i;
1290
d858e5f0 1291 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
d858e5f0 1292 dev->ctrl.queue_count--;
147b27e4 1293 nvme_free_queue(&dev->queues[i]);
121c7ad4 1294 }
22404274
KB		 1295}
1296
4d115420
KB		 1297/**
1298 * nvme_suspend_queue - put queue into suspended state
1299 * @nvmeq - queue to suspend
4d115420
KB		 1300 */
1301static int nvme_suspend_queue(struct nvme_queue *nvmeq)
b60503ba 1302{
2b25d981 1303 int vector;
b60503ba 1304
a09115b2 1305 spin_lock_irq(&nvmeq->q_lock);
2b25d981
KB		 1306 if (nvmeq->cq_vector == -1) {
1307 spin_unlock_irq(&nvmeq->q_lock);
1308 return 1;
1309 }
0ff199cb 1310 vector = nvmeq->cq_vector;
42f61420 1311 nvmeq->dev->online_queues--;
2b25d981 1312 nvmeq->cq_vector = -1;
a09115b2
MW		 1313 spin_unlock_irq(&nvmeq->q_lock);
1314
1c63dc66 1315 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
c81545f9 1316 blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q);
6df3dbc8 1317
0ff199cb 1318 pci_free_irq(to_pci_dev(nvmeq->dev->dev), vector, nvmeq);
b60503ba 1319
4d115420
KB		 1320 return 0;
1321}
b60503ba 1322
a5cdb68c 1323static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
4d115420 1324{
147b27e4 1325 struct nvme_queue *nvmeq = &dev->queues[0];
4d115420 1326
4d115420
KB		 1327 if (nvme_suspend_queue(nvmeq))
1328 return;
1329
a5cdb68c
KB		 1330 if (shutdown)
1331 nvme_shutdown_ctrl(&dev->ctrl);
1332 else
20d0dfe6 1333 nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap);
07836e65
KB		 1334
1335 spin_lock_irq(&nvmeq->q_lock);
1336 nvme_process_cq(nvmeq);
1337 spin_unlock_irq(&nvmeq->q_lock);
b60503ba
MW		 1338}
1339
8ffaadf7
JD		 1340static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1341 int entry_size)
1342{
1343 int q_depth = dev->q_depth;
5fd4ce1b
CH		 1344 unsigned q_size_aligned = roundup(q_depth * entry_size,
1345 dev->ctrl.page_size);
8ffaadf7
JD		 1346
1347 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
c45f5c99 1348 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
5fd4ce1b 1349 mem_per_q = round_down(mem_per_q, dev->ctrl.page_size);
c45f5c99 1350 q_depth = div_u64(mem_per_q, entry_size);
8ffaadf7
JD		 1351
1352 /*
1353 * Ensure the reduced q_depth is above some threshold where it
1354 * would be better to map queues in system memory with the
1355 * original depth
1356 */
1357 if (q_depth < 64)
1358 return -ENOMEM;
1359 }
1360
1361 return q_depth;
1362}
1363
1364static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1365 int qid, int depth)
1366{
88de4598 1367 if (qid && dev->cmb && use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
5fd4ce1b
CH		 1368 unsigned offset = (qid - 1) * roundup(SQ_SIZE(depth),
1369 dev->ctrl.page_size);
8969f1f8 1370 nvmeq->sq_dma_addr = dev->cmb_bus_addr + offset;
8ffaadf7
JD		 1371 nvmeq->sq_cmds_io = dev->cmb + offset;
1372 } else {
1373 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
1374 &nvmeq->sq_dma_addr, GFP_KERNEL);
1375 if (!nvmeq->sq_cmds)
1376 return -ENOMEM;
1377 }
1378
1379 return 0;
1380}
1381
147b27e4
SG		 1382static int nvme_alloc_queue(struct nvme_dev *dev, int qid,
1383 int depth, int node)
b60503ba 1384{
147b27e4 1385 struct nvme_queue *nvmeq = &dev->queues[qid];
b60503ba 1386
e75ec752 1387 nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth),
4d51abf9 1388 &nvmeq->cq_dma_addr, GFP_KERNEL);
b60503ba
MW		 1389 if (!nvmeq->cqes)
1390 goto free_nvmeq;
b60503ba 1391
8ffaadf7 1392 if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth))
b60503ba
MW		 1393 goto free_cqdma;
1394
e75ec752 1395 nvmeq->q_dmadev = dev->dev;
091b6092 1396 nvmeq->dev = dev;
b60503ba
MW		 1397 spin_lock_init(&nvmeq->q_lock);
1398 nvmeq->cq_head = 0;
82123460 1399 nvmeq->cq_phase = 1;
b80d5ccc 1400 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
b60503ba 1401 nvmeq->q_depth = depth;
c30341dc 1402 nvmeq->qid = qid;
758dd7fd 1403 nvmeq->cq_vector = -1;
d858e5f0 1404 dev->ctrl.queue_count++;
36a7e993 1405
147b27e4 1406 return 0;
b60503ba
MW		 1407
1408 free_cqdma:
e75ec752 1409 dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes,
b60503ba
MW		 1410 nvmeq->cq_dma_addr);
1411 free_nvmeq:
147b27e4 1412 return -ENOMEM;
b60503ba
MW		 1413}
1414
dca51e78 1415static int queue_request_irq(struct nvme_queue *nvmeq)
3001082c 1416{
0ff199cb
CH		 1417 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1418 int nr = nvmeq->dev->ctrl.instance;
1419
1420 if (use_threaded_interrupts) {
1421 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1422 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1423 } else {
1424 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1425 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1426 }
3001082c
MW		 1427}
1428
22404274 1429static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
b60503ba 1430{
22404274 1431 struct nvme_dev *dev = nvmeq->dev;
b60503ba 1432
7be50e93 1433 spin_lock_irq(&nvmeq->q_lock);
22404274
KB		 1434 nvmeq->sq_tail = 0;
1435 nvmeq->cq_head = 0;
1436 nvmeq->cq_phase = 1;
b80d5ccc 1437 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
22404274 1438 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
f9f38e33 1439 nvme_dbbuf_init(dev, nvmeq, qid);
42f61420 1440 dev->online_queues++;
7be50e93 1441 spin_unlock_irq(&nvmeq->q_lock);
22404274
KB		 1442}
1443
1444static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1445{
1446 struct nvme_dev *dev = nvmeq->dev;
1447 int result;
3f85d50b 1448
2b25d981 1449 nvmeq->cq_vector = qid - 1;
b60503ba
MW		 1450 result = adapter_alloc_cq(dev, qid, nvmeq);
1451 if (result < 0)
22404274 1452 return result;
b60503ba
MW		 1453
1454 result = adapter_alloc_sq(dev, qid, nvmeq);
1455 if (result < 0)
1456 goto release_cq;
1457
161b8be2 1458 nvme_init_queue(nvmeq, qid);
dca51e78 1459 result = queue_request_irq(nvmeq);
b60503ba
MW		 1460 if (result < 0)
1461 goto release_sq;
1462
22404274 1463 return result;
b60503ba
MW		 1464
1465 release_sq:
1466 adapter_delete_sq(dev, qid);
1467 release_cq:
1468 adapter_delete_cq(dev, qid);
22404274 1469 return result;
b60503ba
MW		 1470}
1471
f363b089 1472static const struct blk_mq_ops nvme_mq_admin_ops = {
d29ec824 1473 .queue_rq = nvme_queue_rq,
77f02a7a 1474 .complete = nvme_pci_complete_rq,
a4aea562 1475 .init_hctx = nvme_admin_init_hctx,
4af0e21c 1476 .exit_hctx = nvme_admin_exit_hctx,
0350815a 1477 .init_request = nvme_init_request,
a4aea562
MB		 1478 .timeout = nvme_timeout,
1479};
1480
f363b089 1481static const struct blk_mq_ops nvme_mq_ops = {
a4aea562 1482 .queue_rq = nvme_queue_rq,
77f02a7a 1483 .complete = nvme_pci_complete_rq,
a4aea562
MB		 1484 .init_hctx = nvme_init_hctx,
1485 .init_request = nvme_init_request,
dca51e78 1486 .map_queues = nvme_pci_map_queues,
a4aea562 1487 .timeout = nvme_timeout,
a0fa9647 1488 .poll = nvme_poll,
a4aea562
MB		 1489};
1490
ea191d2f
KB		 1491static void nvme_dev_remove_admin(struct nvme_dev *dev)
1492{
1c63dc66 1493 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
69d9a99c
KB		 1494 /*
1495 * If the controller was reset during removal, it's possible
1496 * user requests may be waiting on a stopped queue. Start the
1497 * queue to flush these to completion.
1498 */
c81545f9 1499 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1c63dc66 1500 blk_cleanup_queue(dev->ctrl.admin_q);
ea191d2f
KB		 1501 blk_mq_free_tag_set(&dev->admin_tagset);
1502 }
1503}
1504
a4aea562
MB		 1505static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1506{
1c63dc66 1507 if (!dev->ctrl.admin_q) {
a4aea562
MB		 1508 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1509 dev->admin_tagset.nr_hw_queues = 1;
e3e9d50c 1510
38dabe21 1511 dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH;
a4aea562 1512 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
e75ec752 1513 dev->admin_tagset.numa_node = dev_to_node(dev->dev);
a7a7cbe3 1514 dev->admin_tagset.cmd_size = nvme_pci_cmd_size(dev, false);
d3484991 1515 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED;
a4aea562
MB		 1516 dev->admin_tagset.driver_data = dev;
1517
1518 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1519 return -ENOMEM;
34b6c231 1520 dev->ctrl.admin_tagset = &dev->admin_tagset;
a4aea562 1521
1c63dc66
CH		 1522 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1523 if (IS_ERR(dev->ctrl.admin_q)) {
a4aea562
MB		 1524 blk_mq_free_tag_set(&dev->admin_tagset);
1525 return -ENOMEM;
1526 }
1c63dc66 1527 if (!blk_get_queue(dev->ctrl.admin_q)) {
ea191d2f 1528 nvme_dev_remove_admin(dev);
1c63dc66 1529 dev->ctrl.admin_q = NULL;
ea191d2f
KB		 1530 return -ENODEV;
1531 }
0fb59cbc 1532 } else
c81545f9 1533 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
a4aea562
MB		 1534
1535 return 0;
1536}
1537
97f6ef64
XY		 1538static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1539{
1540 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1541}
1542
1543static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1544{
1545 struct pci_dev *pdev = to_pci_dev(dev->dev);
1546
1547 if (size <= dev->bar_mapped_size)
1548 return 0;
1549 if (size > pci_resource_len(pdev, 0))
1550 return -ENOMEM;
1551 if (dev->bar)
1552 iounmap(dev->bar);
1553 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1554 if (!dev->bar) {
1555 dev->bar_mapped_size = 0;
1556 return -ENOMEM;
1557 }
1558 dev->bar_mapped_size = size;
1559 dev->dbs = dev->bar + NVME_REG_DBS;
1560
1561 return 0;
1562}
1563
01ad0990 1564static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
b60503ba 1565{
ba47e386 1566 int result;
b60503ba
MW		 1567 u32 aqa;
1568 struct nvme_queue *nvmeq;
1569
97f6ef64
XY		 1570 result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1571 if (result < 0)
1572 return result;
1573
8ef2074d 1574 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
20d0dfe6 1575 NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
dfbac8c7 1576
7a67cbea
CH		 1577 if (dev->subsystem &&
1578 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1579 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
dfbac8c7 1580
20d0dfe6 1581 result = nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap);
ba47e386
MW		 1582 if (result < 0)
1583 return result;
b60503ba 1584
147b27e4
SG		 1585 result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH,
1586 dev_to_node(dev->dev));
1587 if (result)
1588 return result;
b60503ba 1589
147b27e4 1590 nvmeq = &dev->queues[0];
b60503ba
MW		 1591 aqa = nvmeq->q_depth - 1;
1592 aqa |= aqa << 16;
1593
7a67cbea
CH		 1594 writel(aqa, dev->bar + NVME_REG_AQA);
1595 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1596 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
b60503ba 1597
20d0dfe6 1598 result = nvme_enable_ctrl(&dev->ctrl, dev->ctrl.cap);
025c557a 1599 if (result)
d4875622 1600 return result;
a4aea562 1601
2b25d981 1602 nvmeq->cq_vector = 0;
161b8be2 1603 nvme_init_queue(nvmeq, 0);
dca51e78 1604 result = queue_request_irq(nvmeq);
758dd7fd
JD		 1605 if (result) {
1606 nvmeq->cq_vector = -1;
d4875622 1607 return result;
758dd7fd 1608 }
025c557a 1609
b60503ba
MW		 1610 return result;
1611}
1612
749941f2 1613static int nvme_create_io_queues(struct nvme_dev *dev)
42f61420 1614{
949928c1 1615 unsigned i, max;
749941f2 1616 int ret = 0;
42f61420 1617
d858e5f0 1618 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
d3af3ecd 1619 /* vector == qid - 1, match nvme_create_queue */
147b27e4 1620 if (nvme_alloc_queue(dev, i, dev->q_depth,
d3af3ecd 1621 pci_irq_get_node(to_pci_dev(dev->dev), i - 1))) {
749941f2 1622 ret = -ENOMEM;
42f61420 1623 break;
749941f2
CH		 1624 }
1625 }
42f61420 1626
d858e5f0 1627 max = min(dev->max_qid, dev->ctrl.queue_count - 1);
949928c1 1628 for (i = dev->online_queues; i <= max; i++) {
147b27e4 1629 ret = nvme_create_queue(&dev->queues[i], i);
d4875622 1630 if (ret)
42f61420 1631 break;
27e8166c 1632 }
749941f2
CH		 1633
1634 /*
1635 * Ignore failing Create SQ/CQ commands, we can continue with less
8adb8c14
MI		 1636 * than the desired amount of queues, and even a controller without
1637 * I/O queues can still be used to issue admin commands. This might
749941f2
CH		 1638 * be useful to upgrade a buggy firmware for example.
1639 */
1640 return ret >= 0 ? 0 : ret;
b60503ba
MW		 1641}
1642
202021c1
SB		 1643static ssize_t nvme_cmb_show(struct device *dev,
1644 struct device_attribute *attr,
1645 char *buf)
1646{
1647 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
1648
c965809c 1649 return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n",
202021c1
SB		 1650 ndev->cmbloc, ndev->cmbsz);
1651}
1652static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL);
1653
88de4598
CH		 1654static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
1655{
1656 u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
1657
1658 return 1ULL << (12 + 4 * szu);
1659}
1660
1661static u32 nvme_cmb_size(struct nvme_dev *dev)
1662{
1663 return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
1664}
1665
f65efd6d 1666static void nvme_map_cmb(struct nvme_dev *dev)
8ffaadf7 1667{
88de4598 1668 u64 size, offset;
8ffaadf7
JD		 1669 resource_size_t bar_size;
1670 struct pci_dev *pdev = to_pci_dev(dev->dev);
8969f1f8 1671 int bar;
8ffaadf7 1672
7a67cbea 1673 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
f65efd6d
CH		 1674 if (!dev->cmbsz)
1675 return;
202021c1 1676 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
8ffaadf7 1677
202021c1 1678 if (!use_cmb_sqes)
f65efd6d 1679 return;
8ffaadf7 1680
88de4598
CH		 1681 size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
1682 offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
8969f1f8
CH		 1683 bar = NVME_CMB_BIR(dev->cmbloc);
1684 bar_size = pci_resource_len(pdev, bar);
8ffaadf7
JD		 1685
1686 if (offset > bar_size)
f65efd6d 1687 return;
8ffaadf7
JD		 1688
1689 /*
1690 * Controllers may support a CMB size larger than their BAR,
1691 * for example, due to being behind a bridge. Reduce the CMB to
1692 * the reported size of the BAR
1693 */
1694 if (size > bar_size - offset)
1695 size = bar_size - offset;
1696
f65efd6d
CH		 1697 dev->cmb = ioremap_wc(pci_resource_start(pdev, bar) + offset, size);
1698 if (!dev->cmb)
1699 return;
8969f1f8 1700 dev->cmb_bus_addr = pci_bus_address(pdev, bar) + offset;
8ffaadf7 1701 dev->cmb_size = size;
f65efd6d
CH		 1702
1703 if (sysfs_add_file_to_group(&dev->ctrl.device->kobj,
1704 &dev_attr_cmb.attr, NULL))
1705 dev_warn(dev->ctrl.device,
1706 "failed to add sysfs attribute for CMB\n");
8ffaadf7
JD		 1707}
1708
1709static inline void nvme_release_cmb(struct nvme_dev *dev)
1710{
1711 if (dev->cmb) {
1712 iounmap(dev->cmb);
1713 dev->cmb = NULL;
1c78f773
MG		 1714 sysfs_remove_file_from_group(&dev->ctrl.device->kobj,
1715 &dev_attr_cmb.attr, NULL);
1716 dev->cmbsz = 0;
8ffaadf7
JD		 1717 }
1718}
1719
87ad72a5
CH		 1720static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1721{
4033f35d 1722 u64 dma_addr = dev->host_mem_descs_dma;
87ad72a5 1723 struct nvme_command c;
87ad72a5
CH		 1724 int ret;
1725
87ad72a5
CH		 1726 memset(&c, 0, sizeof(c));
1727 c.features.opcode = nvme_admin_set_features;
1728 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1729 c.features.dword11 = cpu_to_le32(bits);
1730 c.features.dword12 = cpu_to_le32(dev->host_mem_size >>
1731 ilog2(dev->ctrl.page_size));
1732 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr));
1733 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr));
1734 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs);
1735
1736 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1737 if (ret) {
1738 dev_warn(dev->ctrl.device,
1739 "failed to set host mem (err %d, flags %#x).\n",
1740 ret, bits);
1741 }
87ad72a5
CH		 1742 return ret;
1743}
1744
1745static void nvme_free_host_mem(struct nvme_dev *dev)
1746{
1747 int i;
1748
1749 for (i = 0; i < dev->nr_host_mem_descs; i++) {
1750 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
1751 size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size;
1752
1753 dma_free_coherent(dev->dev, size, dev->host_mem_desc_bufs[i],
1754 le64_to_cpu(desc->addr));
1755 }
1756
1757 kfree(dev->host_mem_desc_bufs);
1758 dev->host_mem_desc_bufs = NULL;
4033f35d
CH		 1759 dma_free_coherent(dev->dev,
1760 dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
1761 dev->host_mem_descs, dev->host_mem_descs_dma);
87ad72a5 1762 dev->host_mem_descs = NULL;
7e5dd57e 1763 dev->nr_host_mem_descs = 0;
87ad72a5
CH		 1764}
1765
92dc6895
CH		 1766static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
1767 u32 chunk_size)
9d713c2b 1768{
87ad72a5 1769 struct nvme_host_mem_buf_desc *descs;
92dc6895 1770 u32 max_entries, len;
4033f35d 1771 dma_addr_t descs_dma;
2ee0e4ed 1772 int i = 0;
87ad72a5 1773 void **bufs;
6fbcde66 1774 u64 size, tmp;
87ad72a5 1775
87ad72a5
CH		 1776 tmp = (preferred + chunk_size - 1);
1777 do_div(tmp, chunk_size);
1778 max_entries = tmp;
044a9df1
CH		 1779
1780 if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
1781 max_entries = dev->ctrl.hmmaxd;
1782
4033f35d
CH		 1783 descs = dma_zalloc_coherent(dev->dev, max_entries * sizeof(*descs),
1784 &descs_dma, GFP_KERNEL);
87ad72a5
CH		 1785 if (!descs)
1786 goto out;
1787
1788 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
1789 if (!bufs)
1790 goto out_free_descs;
1791
244a8fe4 1792 for (size = 0; size < preferred && i < max_entries; size += len) {
87ad72a5
CH		 1793 dma_addr_t dma_addr;
1794
50cdb7c6 1795 len = min_t(u64, chunk_size, preferred - size);
87ad72a5
CH		 1796 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
1797 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1798 if (!bufs[i])
1799 break;
1800
1801 descs[i].addr = cpu_to_le64(dma_addr);
1802 descs[i].size = cpu_to_le32(len / dev->ctrl.page_size);
1803 i++;
1804 }
1805
92dc6895 1806 if (!size)
87ad72a5 1807 goto out_free_bufs;
87ad72a5 1808
87ad72a5
CH		 1809 dev->nr_host_mem_descs = i;
1810 dev->host_mem_size = size;
1811 dev->host_mem_descs = descs;
4033f35d 1812 dev->host_mem_descs_dma = descs_dma;
87ad72a5
CH		 1813 dev->host_mem_desc_bufs = bufs;
1814 return 0;
1815
1816out_free_bufs:
1817 while (--i >= 0) {
1818 size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size;
1819
1820 dma_free_coherent(dev->dev, size, bufs[i],
1821 le64_to_cpu(descs[i].addr));
1822 }
1823
1824 kfree(bufs);
1825out_free_descs:
4033f35d
CH		 1826 dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
1827 descs_dma);
87ad72a5 1828out:
87ad72a5
CH		 1829 dev->host_mem_descs = NULL;
1830 return -ENOMEM;
1831}
1832
92dc6895
CH		 1833static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
1834{
1835 u32 chunk_size;
1836
1837 /* start big and work our way down */
30f92d62 1838 for (chunk_size = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
044a9df1 1839 chunk_size >= max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
92dc6895
CH		 1840 chunk_size /= 2) {
1841 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
1842 if (!min || dev->host_mem_size >= min)
1843 return 0;
1844 nvme_free_host_mem(dev);
1845 }
1846 }
1847
1848 return -ENOMEM;
1849}
1850
9620cfba 1851static int nvme_setup_host_mem(struct nvme_dev *dev)
87ad72a5
CH		 1852{
1853 u64 max = (u64)max_host_mem_size_mb * SZ_1M;
1854 u64 preferred = (u64)dev->ctrl.hmpre * 4096;
1855 u64 min = (u64)dev->ctrl.hmmin * 4096;
1856 u32 enable_bits = NVME_HOST_MEM_ENABLE;
6fbcde66 1857 int ret;
87ad72a5
CH		 1858
1859 preferred = min(preferred, max);
1860 if (min > max) {
1861 dev_warn(dev->ctrl.device,
1862 "min host memory (%lld MiB) above limit (%d MiB).\n",
1863 min >> ilog2(SZ_1M), max_host_mem_size_mb);
1864 nvme_free_host_mem(dev);
9620cfba 1865 return 0;
87ad72a5
CH		 1866 }
1867
1868 /*
1869 * If we already have a buffer allocated check if we can reuse it.
1870 */
1871 if (dev->host_mem_descs) {
1872 if (dev->host_mem_size >= min)
1873 enable_bits |= NVME_HOST_MEM_RETURN;
1874 else
1875 nvme_free_host_mem(dev);
1876 }
1877
1878 if (!dev->host_mem_descs) {
92dc6895
CH		 1879 if (nvme_alloc_host_mem(dev, min, preferred)) {
1880 dev_warn(dev->ctrl.device,
1881 "failed to allocate host memory buffer.\n");
9620cfba 1882 return 0; /* controller must work without HMB */
92dc6895
CH		 1883 }
1884
1885 dev_info(dev->ctrl.device,
1886 "allocated %lld MiB host memory buffer.\n",
1887 dev->host_mem_size >> ilog2(SZ_1M));
87ad72a5
CH		 1888 }
1889
9620cfba
CH		 1890 ret = nvme_set_host_mem(dev, enable_bits);
1891 if (ret)
87ad72a5 1892 nvme_free_host_mem(dev);
9620cfba 1893 return ret;
9d713c2b
KB		 1894}
1895
8d85fce7 1896static int nvme_setup_io_queues(struct nvme_dev *dev)
b60503ba 1897{
147b27e4 1898 struct nvme_queue *adminq = &dev->queues[0];
e75ec752 1899 struct pci_dev *pdev = to_pci_dev(dev->dev);
97f6ef64
XY		 1900 int result, nr_io_queues;
1901 unsigned long size;
b60503ba 1902
425a17cb 1903 nr_io_queues = num_present_cpus();
9a0be7ab
CH		 1904 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
1905 if (result < 0)
1b23484b 1906 return result;
9a0be7ab 1907
f5fa90dc 1908 if (nr_io_queues == 0)
a5229050 1909 return 0;
b60503ba 1910
88de4598 1911 if (dev->cmb && (dev->cmbsz & NVME_CMBSZ_SQS)) {
8ffaadf7
JD		 1912 result = nvme_cmb_qdepth(dev, nr_io_queues,
1913 sizeof(struct nvme_command));
1914 if (result > 0)
1915 dev->q_depth = result;
1916 else
1917 nvme_release_cmb(dev);
1918 }
1919
97f6ef64
XY		 1920 do {
1921 size = db_bar_size(dev, nr_io_queues);
1922 result = nvme_remap_bar(dev, size);
1923 if (!result)
1924 break;
1925 if (!--nr_io_queues)
1926 return -ENOMEM;
1927 } while (1);
1928 adminq->q_db = dev->dbs;
f1938f6e 1929
9d713c2b 1930 /* Deregister the admin queue's interrupt */
0ff199cb 1931 pci_free_irq(pdev, 0, adminq);
9d713c2b 1932
e32efbfc
JA		 1933 /*
1934 * If we enable msix early due to not intx, disable it again before
1935 * setting up the full range we need.
1936 */
dca51e78
CH		 1937 pci_free_irq_vectors(pdev);
1938 nr_io_queues = pci_alloc_irq_vectors(pdev, 1, nr_io_queues,
1939 PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY);
1940 if (nr_io_queues <= 0)
1941 return -EIO;
1942 dev->max_qid = nr_io_queues;
fa08a396 1943
063a8096
MW		 1944 /*
1945 * Should investigate if there's a performance win from allocating
1946 * more queues than interrupt vectors; it might allow the submission
1947 * path to scale better, even if the receive path is limited by the
1948 * number of interrupts.
1949 */
063a8096 1950
dca51e78 1951 result = queue_request_irq(adminq);
758dd7fd
JD		 1952 if (result) {
1953 adminq->cq_vector = -1;
d4875622 1954 return result;
758dd7fd 1955 }
749941f2 1956 return nvme_create_io_queues(dev);
b60503ba
MW		 1957}
1958
2a842aca 1959static void nvme_del_queue_end(struct request *req, blk_status_t error)
a5768aa8 1960{
db3cbfff 1961 struct nvme_queue *nvmeq = req->end_io_data;
b5875222 1962
db3cbfff
KB		 1963 blk_mq_free_request(req);
1964 complete(&nvmeq->dev->ioq_wait);
a5768aa8
KB		 1965}
1966
2a842aca 1967static void nvme_del_cq_end(struct request *req, blk_status_t error)
a5768aa8 1968{
db3cbfff 1969 struct nvme_queue *nvmeq = req->end_io_data;
a5768aa8 1970
db3cbfff
KB		 1971 if (!error) {
1972 unsigned long flags;
1973
2e39e0f6
ML		 1974 /*
1975 * We might be called with the AQ q_lock held
1976 * and the I/O queue q_lock should always
1977 * nest inside the AQ one.
1978 */
1979 spin_lock_irqsave_nested(&nvmeq->q_lock, flags,
1980 SINGLE_DEPTH_NESTING);
db3cbfff
KB		 1981 nvme_process_cq(nvmeq);
1982 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
a5768aa8 1983 }
db3cbfff
KB		 1984
1985 nvme_del_queue_end(req, error);
a5768aa8
KB		 1986}
1987
db3cbfff 1988static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
bda4e0fb 1989{
db3cbfff
KB		 1990 struct request_queue *q = nvmeq->dev->ctrl.admin_q;
1991 struct request *req;
1992 struct nvme_command cmd;
bda4e0fb 1993
db3cbfff
KB		 1994 memset(&cmd, 0, sizeof(cmd));
1995 cmd.delete_queue.opcode = opcode;
1996 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
bda4e0fb 1997
eb71f435 1998 req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
db3cbfff
KB		 1999 if (IS_ERR(req))
2000 return PTR_ERR(req);
bda4e0fb 2001
db3cbfff
KB		 2002 req->timeout = ADMIN_TIMEOUT;
2003 req->end_io_data = nvmeq;
2004
2005 blk_execute_rq_nowait(q, NULL, req, false,
2006 opcode == nvme_admin_delete_cq ?
2007 nvme_del_cq_end : nvme_del_queue_end);
2008 return 0;
bda4e0fb
KB		 2009}
2010
70659060 2011static void nvme_disable_io_queues(struct nvme_dev *dev, int queues)
a5768aa8 2012{
70659060 2013 int pass;
db3cbfff
KB		 2014 unsigned long timeout;
2015 u8 opcode = nvme_admin_delete_sq;
a5768aa8 2016
db3cbfff 2017 for (pass = 0; pass < 2; pass++) {
014a0d60 2018 int sent = 0, i = queues;
db3cbfff
KB		 2019
2020 reinit_completion(&dev->ioq_wait);
2021 retry:
2022 timeout = ADMIN_TIMEOUT;
c21377f8 2023 for (; i > 0; i--, sent++)
147b27e4 2024 if (nvme_delete_queue(&dev->queues[i], opcode))
db3cbfff 2025 break;
c21377f8 2026
db3cbfff
KB		 2027 while (sent--) {
2028 timeout = wait_for_completion_io_timeout(&dev->ioq_wait, timeout);
2029 if (timeout == 0)
2030 return;
2031 if (i)
2032 goto retry;
2033 }
2034 opcode = nvme_admin_delete_cq;
2035 }
a5768aa8
KB		 2036}
2037
422ef0c7 2038/*
2b1b7e78 2039 * return error value only when tagset allocation failed
422ef0c7 2040 */
8d85fce7 2041static int nvme_dev_add(struct nvme_dev *dev)
b60503ba 2042{
2b1b7e78
JW		 2043 int ret;
2044
5bae7f73 2045 if (!dev->ctrl.tagset) {
ffe7704d
KB		 2046 dev->tagset.ops = &nvme_mq_ops;
2047 dev->tagset.nr_hw_queues = dev->online_queues - 1;
2048 dev->tagset.timeout = NVME_IO_TIMEOUT;
2049 dev->tagset.numa_node = dev_to_node(dev->dev);
2050 dev->tagset.queue_depth =
a4aea562 2051 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
a7a7cbe3
CK		 2052 dev->tagset.cmd_size = nvme_pci_cmd_size(dev, false);
2053 if ((dev->ctrl.sgls & ((1 << 0) | (1 << 1))) && sgl_threshold) {
2054 dev->tagset.cmd_size = max(dev->tagset.cmd_size,
2055 nvme_pci_cmd_size(dev, true));
2056 }
ffe7704d
KB		 2057 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2058 dev->tagset.driver_data = dev;
b60503ba 2059
2b1b7e78
JW		 2060 ret = blk_mq_alloc_tag_set(&dev->tagset);
2061 if (ret) {
2062 dev_warn(dev->ctrl.device,
2063 "IO queues tagset allocation failed %d\n", ret);
2064 return ret;
2065 }
5bae7f73 2066 dev->ctrl.tagset = &dev->tagset;
f9f38e33
HK		 2067
2068 nvme_dbbuf_set(dev);
949928c1
KB		 2069 } else {
2070 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2071
2072 /* Free previously allocated queues that are no longer usable */
2073 nvme_free_queues(dev, dev->online_queues);
ffe7704d 2074 }
949928c1 2075
e1e5e564 2076 return 0;
b60503ba
MW		 2077}
2078
b00a726a 2079static int nvme_pci_enable(struct nvme_dev *dev)
0877cb0d 2080{
b00a726a 2081 int result = -ENOMEM;
e75ec752 2082 struct pci_dev *pdev = to_pci_dev(dev->dev);
0877cb0d
KB		 2083
2084 if (pci_enable_device_mem(pdev))
2085 return result;
2086
0877cb0d 2087 pci_set_master(pdev);
0877cb0d 2088
e75ec752
CH		 2089 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) &&
2090 dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32)))
052d0efa 2091 goto disable;
0877cb0d 2092
7a67cbea 2093 if (readl(dev->bar + NVME_REG_CSTS) == -1) {
0e53d180 2094 result = -ENODEV;
b00a726a 2095 goto disable;
0e53d180 2096 }
e32efbfc
JA		 2097
2098 /*
a5229050
KB		 2099 * Some devices and/or platforms don't advertise or work with INTx
2100 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2101 * adjust this later.
e32efbfc 2102 */
dca51e78
CH		 2103 result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
2104 if (result < 0)
2105 return result;
e32efbfc 2106
20d0dfe6 2107 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
7a67cbea 2108
20d0dfe6 2109 dev->q_depth = min_t(int, NVME_CAP_MQES(dev->ctrl.cap) + 1,
b27c1e68 2110 io_queue_depth);
20d0dfe6 2111 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
7a67cbea 2112 dev->dbs = dev->bar + 4096;
1f390c1f
SG		 2113
2114 /*
2115 * Temporary fix for the Apple controller found in the MacBook8,1 and
2116 * some MacBook7,1 to avoid controller resets and data loss.
2117 */
2118 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
2119 dev->q_depth = 2;
9bdcfb10
CH		 2120 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
2121 "set queue depth=%u to work around controller resets\n",
1f390c1f 2122 dev->q_depth);
d554b5e1
MP		 2123 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2124 (pdev->device == 0xa821 || pdev->device == 0xa822) &&
20d0dfe6 2125 NVME_CAP_MQES(dev->ctrl.cap) == 0) {
d554b5e1
MP		 2126 dev->q_depth = 64;
2127 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2128 "set queue depth=%u\n", dev->q_depth);
1f390c1f
SG		 2129 }
2130
f65efd6d 2131 nvme_map_cmb(dev);
202021c1 2132
a0a3408e
KB		 2133 pci_enable_pcie_error_reporting(pdev);
2134 pci_save_state(pdev);
0877cb0d
KB		 2135 return 0;
2136
2137 disable:
0877cb0d
KB		 2138 pci_disable_device(pdev);
2139 return result;
2140}
2141
2142static void nvme_dev_unmap(struct nvme_dev *dev)
b00a726a
KB		 2143{
2144 if (dev->bar)
2145 iounmap(dev->bar);
a1f447b3 2146 pci_release_mem_regions(to_pci_dev(dev->dev));
b00a726a
KB		 2147}
2148
2149static void nvme_pci_disable(struct nvme_dev *dev)
0877cb0d 2150{
e75ec752
CH		 2151 struct pci_dev *pdev = to_pci_dev(dev->dev);
2152
f63572df 2153 nvme_release_cmb(dev);
dca51e78 2154 pci_free_irq_vectors(pdev);
0877cb0d 2155
a0a3408e
KB		 2156 if (pci_is_enabled(pdev)) {
2157 pci_disable_pcie_error_reporting(pdev);
e75ec752 2158 pci_disable_device(pdev);
4d115420 2159 }
4d115420
KB		 2160}
2161
a5cdb68c 2162static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
b60503ba 2163{
70659060 2164 int i, queues;
302ad8cc
KB		 2165 bool dead = true;
2166 struct pci_dev *pdev = to_pci_dev(dev->dev);
22404274 2167
77bf25ea 2168 mutex_lock(&dev->shutdown_lock);
302ad8cc
KB		 2169 if (pci_is_enabled(pdev)) {
2170 u32 csts = readl(dev->bar + NVME_REG_CSTS);
2171
ebef7368
KB		 2172 if (dev->ctrl.state == NVME_CTRL_LIVE ||
2173 dev->ctrl.state == NVME_CTRL_RESETTING)
302ad8cc
KB		 2174 nvme_start_freeze(&dev->ctrl);
2175 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
2176 pdev->error_state != pci_channel_io_normal);
c9d3bf88 2177 }
c21377f8 2178
302ad8cc
KB		 2179 /*
2180 * Give the controller a chance to complete all entered requests if
2181 * doing a safe shutdown.
2182 */
87ad72a5
CH		 2183 if (!dead) {
2184 if (shutdown)
2185 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
2186
2187 /*
2188 * If the controller is still alive tell it to stop using the
2189 * host memory buffer. In theory the shutdown / reset should
2190 * make sure that it doesn't access the host memoery anymore,
2191 * but I'd rather be safe than sorry..
2192 */
2193 if (dev->host_mem_descs)
2194 nvme_set_host_mem(dev, 0);
2195
2196 }
302ad8cc
KB		 2197 nvme_stop_queues(&dev->ctrl);
2198
70659060 2199 queues = dev->online_queues - 1;
d858e5f0 2200 for (i = dev->ctrl.queue_count - 1; i > 0; i--)
147b27e4 2201 nvme_suspend_queue(&dev->queues[i]);
c21377f8 2202
302ad8cc 2203 if (dead) {
82469c59
GKB		 2204 /* A device might become IO incapable very soon during
2205 * probe, before the admin queue is configured. Thus,
2206 * queue_count can be 0 here.
2207 */
d858e5f0 2208 if (dev->ctrl.queue_count)
147b27e4 2209 nvme_suspend_queue(&dev->queues[0]);
4d115420 2210 } else {
70659060 2211 nvme_disable_io_queues(dev, queues);
a5cdb68c 2212 nvme_disable_admin_queue(dev, shutdown);
4d115420 2213 }
b00a726a 2214 nvme_pci_disable(dev);
07836e65 2215
e1958e65
ML		 2216 blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
2217 blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
302ad8cc
KB		 2218
2219 /*
2220 * The driver will not be starting up queues again if shutting down so
2221 * must flush all entered requests to their failed completion to avoid
2222 * deadlocking blk-mq hot-cpu notifier.
2223 */
2224 if (shutdown)
2225 nvme_start_queues(&dev->ctrl);
77bf25ea 2226 mutex_unlock(&dev->shutdown_lock);
b60503ba
MW		 2227}
2228
091b6092
MW		 2229static int nvme_setup_prp_pools(struct nvme_dev *dev)
2230{
e75ec752 2231 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
091b6092
MW		 2232 PAGE_SIZE, PAGE_SIZE, 0);
2233 if (!dev->prp_page_pool)
2234 return -ENOMEM;
2235
99802a7a 2236 /* Optimisation for I/Os between 4k and 128k */
e75ec752 2237 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
99802a7a
MW		 2238 256, 256, 0);
2239 if (!dev->prp_small_pool) {
2240 dma_pool_destroy(dev->prp_page_pool);
2241 return -ENOMEM;
2242 }
091b6092
MW		 2243 return 0;
2244}
2245
2246static void nvme_release_prp_pools(struct nvme_dev *dev)
2247{
2248 dma_pool_destroy(dev->prp_page_pool);
99802a7a 2249 dma_pool_destroy(dev->prp_small_pool);
091b6092
MW		 2250}
2251
1673f1f0 2252static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
5e82e952 2253{
1673f1f0 2254 struct nvme_dev *dev = to_nvme_dev(ctrl);
9ac27090 2255
f9f38e33 2256 nvme_dbbuf_dma_free(dev);
e75ec752 2257 put_device(dev->dev);
4af0e21c
KB		 2258 if (dev->tagset.tags)
2259 blk_mq_free_tag_set(&dev->tagset);
1c63dc66
CH		 2260 if (dev->ctrl.admin_q)
2261 blk_put_queue(dev->ctrl.admin_q);
5e82e952 2262 kfree(dev->queues);
e286bcfc 2263 free_opal_dev(dev->ctrl.opal_dev);
5e82e952
KB		 2264 kfree(dev);
2265}
2266
f58944e2
KB		 2267static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status)
2268{
237045fc 2269 dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status);
f58944e2 2270
d22524a4 2271 nvme_get_ctrl(&dev->ctrl);
69d9a99c 2272 nvme_dev_disable(dev, false);
03e0f3a6 2273 if (!queue_work(nvme_wq, &dev->remove_work))
f58944e2
KB		 2274 nvme_put_ctrl(&dev->ctrl);
2275}
2276
fd634f41 2277static void nvme_reset_work(struct work_struct *work)
5e82e952 2278{
d86c4d8e
CH		 2279 struct nvme_dev *dev =
2280 container_of(work, struct nvme_dev, ctrl.reset_work);
a98e58e5 2281 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
f58944e2 2282 int result = -ENODEV;
2b1b7e78 2283 enum nvme_ctrl_state new_state = NVME_CTRL_LIVE;
5e82e952 2284
82b057ca 2285 if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING))
fd634f41 2286 goto out;
5e82e952 2287
fd634f41
CH		 2288 /*
2289 * If we're called to reset a live controller first shut it down before
2290 * moving on.
2291 */
b00a726a 2292 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
a5cdb68c 2293 nvme_dev_disable(dev, false);
5e82e952 2294
b00a726a 2295 result = nvme_pci_enable(dev);
f0b50732 2296 if (result)
3cf519b5 2297 goto out;
f0b50732 2298
01ad0990 2299 result = nvme_pci_configure_admin_queue(dev);
f0b50732 2300 if (result)
f58944e2 2301 goto out;
f0b50732 2302
0fb59cbc
KB		 2303 result = nvme_alloc_admin_tags(dev);
2304 if (result)
f58944e2 2305 goto out;
b9afca3e 2306
ce4541f4
CH		 2307 result = nvme_init_identify(&dev->ctrl);
2308 if (result)
f58944e2 2309 goto out;
ce4541f4 2310
e286bcfc
SB		 2311 if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
2312 if (!dev->ctrl.opal_dev)
2313 dev->ctrl.opal_dev =
2314 init_opal_dev(&dev->ctrl, &nvme_sec_submit);
2315 else if (was_suspend)
2316 opal_unlock_from_suspend(dev->ctrl.opal_dev);
2317 } else {
2318 free_opal_dev(dev->ctrl.opal_dev);
2319 dev->ctrl.opal_dev = NULL;
4f1244c8 2320 }
a98e58e5 2321
f9f38e33
HK		 2322 if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) {
2323 result = nvme_dbbuf_dma_alloc(dev);
2324 if (result)
2325 dev_warn(dev->dev,
2326 "unable to allocate dma for dbbuf\n");
2327 }
2328
9620cfba
CH		 2329 if (dev->ctrl.hmpre) {
2330 result = nvme_setup_host_mem(dev);
2331 if (result < 0)
2332 goto out;
2333 }
87ad72a5 2334
f0b50732 2335 result = nvme_setup_io_queues(dev);
badc34d4 2336 if (result)
f58944e2 2337 goto out;
f0b50732 2338
2659e57b
CH		 2339 /*
2340 * Keep the controller around but remove all namespaces if we don't have
2341 * any working I/O queue.
2342 */
3cf519b5 2343 if (dev->online_queues < 2) {
1b3c47c1 2344 dev_warn(dev->ctrl.device, "IO queues not created\n");
3b24774e 2345 nvme_kill_queues(&dev->ctrl);
5bae7f73 2346 nvme_remove_namespaces(&dev->ctrl);
2b1b7e78 2347 new_state = NVME_CTRL_ADMIN_ONLY;
3cf519b5 2348 } else {
25646264 2349 nvme_start_queues(&dev->ctrl);
302ad8cc 2350 nvme_wait_freeze(&dev->ctrl);
2b1b7e78
JW		 2351 /* hit this only when allocate tagset fails */
2352 if (nvme_dev_add(dev))
2353 new_state = NVME_CTRL_ADMIN_ONLY;
302ad8cc 2354 nvme_unfreeze(&dev->ctrl);
3cf519b5
CH		 2355 }
2356
2b1b7e78
JW		 2357 /*
2358 * If only admin queue live, keep it to do further investigation or
2359 * recovery.
2360 */
2361 if (!nvme_change_ctrl_state(&dev->ctrl, new_state)) {
2362 dev_warn(dev->ctrl.device,
2363 "failed to mark controller state %d\n", new_state);
bb8d261e
CH		 2364 goto out;
2365 }
92911a55 2366
d09f2b45 2367 nvme_start_ctrl(&dev->ctrl);
3cf519b5 2368 return;
f0b50732 2369
3cf519b5 2370 out:
f58944e2 2371 nvme_remove_dead_ctrl(dev, result);
f0b50732
KB		 2372}
2373
5c8809e6 2374static void nvme_remove_dead_ctrl_work(struct work_struct *work)
9a6b9458 2375{
5c8809e6 2376 struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
e75ec752 2377 struct pci_dev *pdev = to_pci_dev(dev->dev);
9a6b9458 2378
69d9a99c 2379 nvme_kill_queues(&dev->ctrl);
9a6b9458 2380 if (pci_get_drvdata(pdev))
921920ab 2381 device_release_driver(&pdev->dev);
1673f1f0 2382 nvme_put_ctrl(&dev->ctrl);
9a6b9458
KB		 2383}
2384
1c63dc66 2385static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
9ca97374 2386{
1c63dc66 2387 *val = readl(to_nvme_dev(ctrl)->bar + off);
90667892 2388 return 0;
9ca97374
TH		 2389}
2390
5fd4ce1b 2391static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
4cc06521 2392{
5fd4ce1b
CH		 2393 writel(val, to_nvme_dev(ctrl)->bar + off);
2394 return 0;
2395}
4cc06521 2396
7fd8930f
CH		 2397static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2398{
2399 *val = readq(to_nvme_dev(ctrl)->bar + off);
2400 return 0;
4cc06521
KB		 2401}
2402
1c63dc66 2403static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
1a353d85 2404 .name = "pcie",
e439bb12 2405 .module = THIS_MODULE,
c81bfba9 2406 .flags = NVME_F_METADATA_SUPPORTED,
1c63dc66 2407 .reg_read32 = nvme_pci_reg_read32,
5fd4ce1b 2408 .reg_write32 = nvme_pci_reg_write32,
7fd8930f 2409 .reg_read64 = nvme_pci_reg_read64,
1673f1f0 2410 .free_ctrl = nvme_pci_free_ctrl,
f866fc42 2411 .submit_async_event = nvme_pci_submit_async_event,
1c63dc66 2412};
4cc06521 2413
b00a726a
KB		 2414static int nvme_dev_map(struct nvme_dev *dev)
2415{
b00a726a
KB		 2416 struct pci_dev *pdev = to_pci_dev(dev->dev);
2417
a1f447b3 2418 if (pci_request_mem_regions(pdev, "nvme"))
b00a726a
KB		 2419 return -ENODEV;
2420
97f6ef64 2421 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
b00a726a
KB		 2422 goto release;
2423
9fa196e7 2424 return 0;
b00a726a 2425 release:
9fa196e7
MG		 2426 pci_release_mem_regions(pdev);
2427 return -ENODEV;
b00a726a
KB		 2428}
2429
8427bbc2 2430static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
ff5350a8
AL		 2431{
2432 if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
2433 /*
2434 * Several Samsung devices seem to drop off the PCIe bus
2435 * randomly when APST is on and uses the deepest sleep state.
2436 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2437 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2438 * 950 PRO 256GB", but it seems to be restricted to two Dell
2439 * laptops.
2440 */
2441 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
2442 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
2443 dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
2444 return NVME_QUIRK_NO_DEEPEST_PS;
8427bbc2
KHF		 2445 } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
2446 /*
2447 * Samsung SSD 960 EVO drops off the PCIe bus after system
2448 * suspend on a Ryzen board, ASUS PRIME B350M-A.
2449 */
2450 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
2451 dmi_match(DMI_BOARD_NAME, "PRIME B350M-A"))
2452 return NVME_QUIRK_NO_APST;
ff5350a8
AL		 2453 }
2454
2455 return 0;
2456}
2457
8d85fce7 2458static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
b60503ba 2459{
a4aea562 2460 int node, result = -ENOMEM;
b60503ba 2461 struct nvme_dev *dev;
ff5350a8 2462 unsigned long quirks = id->driver_data;
b60503ba 2463
a4aea562
MB		 2464 node = dev_to_node(&pdev->dev);
2465 if (node == NUMA_NO_NODE)
2fa84351 2466 set_dev_node(&pdev->dev, first_memory_node);
a4aea562
MB		 2467
2468 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
b60503ba
MW		 2469 if (!dev)
2470 return -ENOMEM;
147b27e4
SG		 2471
2472 dev->queues = kcalloc_node(num_possible_cpus() + 1,
2473 sizeof(struct nvme_queue), GFP_KERNEL, node);
b60503ba
MW		 2474 if (!dev->queues)
2475 goto free;
2476
e75ec752 2477 dev->dev = get_device(&pdev->dev);
9a6b9458 2478 pci_set_drvdata(pdev, dev);
1c63dc66 2479
b00a726a
KB		 2480 result = nvme_dev_map(dev);
2481 if (result)
b00c9b7a 2482 goto put_pci;
b00a726a 2483
d86c4d8e 2484 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
5c8809e6 2485 INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
77bf25ea 2486 mutex_init(&dev->shutdown_lock);
db3cbfff 2487 init_completion(&dev->ioq_wait);
b60503ba 2488
091b6092
MW		 2489 result = nvme_setup_prp_pools(dev);
2490 if (result)
b00c9b7a 2491 goto unmap;
4cc06521 2492
8427bbc2 2493 quirks |= check_vendor_combination_bug(pdev);
ff5350a8 2494
f3ca80fc 2495 result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
ff5350a8 2496 quirks);
4cc06521 2497 if (result)
2e1d8448 2498 goto release_pools;
740216fc 2499
1b3c47c1
SG		 2500 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
2501
4caff8fc
SG		 2502 nvme_reset_ctrl(&dev->ctrl);
2503
b60503ba
MW		 2504 return 0;
2505
0877cb0d 2506 release_pools:
091b6092 2507 nvme_release_prp_pools(dev);
b00c9b7a
CJ		 2508 unmap:
2509 nvme_dev_unmap(dev);
a96d4f5c 2510 put_pci:
e75ec752 2511 put_device(dev->dev);
b60503ba
MW		 2512 free:
2513 kfree(dev->queues);
b60503ba
MW		 2514 kfree(dev);
2515 return result;
2516}
2517
775755ed 2518static void nvme_reset_prepare(struct pci_dev *pdev)
f0d54a54 2519{
a6739479 2520 struct nvme_dev *dev = pci_get_drvdata(pdev);
f263fbb8 2521 nvme_dev_disable(dev, false);
775755ed 2522}
f0d54a54 2523
775755ed
CH		 2524static void nvme_reset_done(struct pci_dev *pdev)
2525{
f263fbb8 2526 struct nvme_dev *dev = pci_get_drvdata(pdev);
79c48ccf 2527 nvme_reset_ctrl_sync(&dev->ctrl);
f0d54a54
KB		 2528}
2529
09ece142
KB		 2530static void nvme_shutdown(struct pci_dev *pdev)
2531{
2532 struct nvme_dev *dev = pci_get_drvdata(pdev);
a5cdb68c 2533 nvme_dev_disable(dev, true);
09ece142
KB		 2534}
2535
f58944e2
KB		 2536/*
2537 * The driver's remove may be called on a device in a partially initialized
2538 * state. This function must not have any dependencies on the device state in
2539 * order to proceed.
2540 */
8d85fce7 2541static void nvme_remove(struct pci_dev *pdev)
b60503ba
MW		 2542{
2543 struct nvme_dev *dev = pci_get_drvdata(pdev);
9a6b9458 2544
bb8d261e
CH		 2545 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
2546
d86c4d8e 2547 cancel_work_sync(&dev->ctrl.reset_work);
9a6b9458 2548 pci_set_drvdata(pdev, NULL);
0ff9d4e1 2549
6db28eda 2550 if (!pci_device_is_present(pdev)) {
0ff9d4e1 2551 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
6db28eda
KB		 2552 nvme_dev_disable(dev, false);
2553 }
0ff9d4e1 2554
d86c4d8e 2555 flush_work(&dev->ctrl.reset_work);
d09f2b45
SG		 2556 nvme_stop_ctrl(&dev->ctrl);
2557 nvme_remove_namespaces(&dev->ctrl);
a5cdb68c 2558 nvme_dev_disable(dev, true);
87ad72a5 2559 nvme_free_host_mem(dev);
a4aea562 2560 nvme_dev_remove_admin(dev);
a1a5ef99 2561 nvme_free_queues(dev, 0);
d09f2b45 2562 nvme_uninit_ctrl(&dev->ctrl);
9a6b9458 2563 nvme_release_prp_pools(dev);
b00a726a 2564 nvme_dev_unmap(dev);
1673f1f0 2565 nvme_put_ctrl(&dev->ctrl);
b60503ba
MW		 2566}
2567
13880f5b
KB		 2568static int nvme_pci_sriov_configure(struct pci_dev *pdev, int numvfs)
2569{
2570 int ret = 0;
2571
2572 if (numvfs == 0) {
2573 if (pci_vfs_assigned(pdev)) {
2574 dev_warn(&pdev->dev,
2575 "Cannot disable SR-IOV VFs while assigned\n");
2576 return -EPERM;
2577 }
2578 pci_disable_sriov(pdev);
2579 return 0;
2580 }
2581
2582 ret = pci_enable_sriov(pdev, numvfs);
2583 return ret ? ret : numvfs;
2584}
2585
671a6018 2586#ifdef CONFIG_PM_SLEEP
cd638946
KB		 2587static int nvme_suspend(struct device *dev)
2588{
2589 struct pci_dev *pdev = to_pci_dev(dev);
2590 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2591
a5cdb68c 2592 nvme_dev_disable(ndev, true);
cd638946
KB		 2593 return 0;
2594}
2595
2596static int nvme_resume(struct device *dev)
2597{
2598 struct pci_dev *pdev = to_pci_dev(dev);
2599 struct nvme_dev *ndev = pci_get_drvdata(pdev);
cd638946 2600
d86c4d8e 2601 nvme_reset_ctrl(&ndev->ctrl);
9a6b9458 2602 return 0;
cd638946 2603}
671a6018 2604#endif
cd638946
KB		 2605
2606static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
b60503ba 2607
a0a3408e
KB		 2608static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
2609 pci_channel_state_t state)
2610{
2611 struct nvme_dev *dev = pci_get_drvdata(pdev);
2612
2613 /*
2614 * A frozen channel requires a reset. When detected, this method will
2615 * shutdown the controller to quiesce. The controller will be restarted
2616 * after the slot reset through driver's slot_reset callback.
2617 */
a0a3408e
KB		 2618 switch (state) {
2619 case pci_channel_io_normal:
2620 return PCI_ERS_RESULT_CAN_RECOVER;
2621 case pci_channel_io_frozen:
d011fb31
KB		 2622 dev_warn(dev->ctrl.device,
2623 "frozen state error detected, reset controller\n");
a5cdb68c 2624 nvme_dev_disable(dev, false);
a0a3408e
KB		 2625 return PCI_ERS_RESULT_NEED_RESET;
2626 case pci_channel_io_perm_failure:
d011fb31
KB		 2627 dev_warn(dev->ctrl.device,
2628 "failure state error detected, request disconnect\n");
a0a3408e
KB		 2629 return PCI_ERS_RESULT_DISCONNECT;
2630 }
2631 return PCI_ERS_RESULT_NEED_RESET;
2632}
2633
2634static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
2635{
2636 struct nvme_dev *dev = pci_get_drvdata(pdev);
2637
1b3c47c1 2638 dev_info(dev->ctrl.device, "restart after slot reset\n");
a0a3408e 2639 pci_restore_state(pdev);
d86c4d8e 2640 nvme_reset_ctrl(&dev->ctrl);
a0a3408e
KB		 2641 return PCI_ERS_RESULT_RECOVERED;
2642}
2643
2644static void nvme_error_resume(struct pci_dev *pdev)
2645{
2646 pci_cleanup_aer_uncorrect_error_status(pdev);
2647}
2648
1d352035 2649static const struct pci_error_handlers nvme_err_handler = {
b60503ba 2650 .error_detected = nvme_error_detected,
b60503ba
MW		 2651 .slot_reset = nvme_slot_reset,
2652 .resume = nvme_error_resume,
775755ed
CH		 2653 .reset_prepare = nvme_reset_prepare,
2654 .reset_done = nvme_reset_done,
b60503ba
MW		 2655};
2656
6eb0d698 2657static const struct pci_device_id nvme_id_table[] = {
106198ed 2658 { PCI_VDEVICE(INTEL, 0x0953),
08095e70 2659 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 2660 NVME_QUIRK_DEALLOCATE_ZEROES, },
99466e70
KB		 2661 { PCI_VDEVICE(INTEL, 0x0a53),
2662 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 2663 NVME_QUIRK_DEALLOCATE_ZEROES, },
99466e70
KB		 2664 { PCI_VDEVICE(INTEL, 0x0a54),
2665 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 2666 NVME_QUIRK_DEALLOCATE_ZEROES, },
f99cb7af
DWF		 2667 { PCI_VDEVICE(INTEL, 0x0a55),
2668 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2669 NVME_QUIRK_DEALLOCATE_ZEROES, },
50af47d0
AL		 2670 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */
2671 .driver_data = NVME_QUIRK_NO_DEEPEST_PS },
540c801c
KB		 2672 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */
2673 .driver_data = NVME_QUIRK_IDENTIFY_CNS, },
54adc010
GP		 2674 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
2675 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
8c97eecc
JL		 2676 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */
2677 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
015282c9
WW		 2678 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
2679 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
d554b5e1
MP		 2680 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */
2681 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2682 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */
2683 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
608cc4b1
CH		 2684 { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */
2685 .driver_data = NVME_QUIRK_LIGHTNVM, },
2686 { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */
2687 .driver_data = NVME_QUIRK_LIGHTNVM, },
b60503ba 2688 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
c74dc780 2689 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) },
124298bd 2690 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
b60503ba
MW		 2691 { 0, }
2692};
2693MODULE_DEVICE_TABLE(pci, nvme_id_table);
2694
2695static struct pci_driver nvme_driver = {
2696 .name = "nvme",
2697 .id_table = nvme_id_table,
2698 .probe = nvme_probe,
8d85fce7 2699 .remove = nvme_remove,
09ece142 2700 .shutdown = nvme_shutdown,
cd638946
KB		 2701 .driver = {
2702 .pm = &nvme_dev_pm_ops,
2703 },
13880f5b 2704 .sriov_configure = nvme_pci_sriov_configure,
b60503ba
MW		 2705 .err_handler = &nvme_err_handler,
2706};
2707
2708static int __init nvme_init(void)
2709{
9a6327d2 2710 return pci_register_driver(&nvme_driver);
b60503ba
MW		 2711}
2712
2713static void __exit nvme_exit(void)
2714{
2715 pci_unregister_driver(&nvme_driver);
03e0f3a6 2716 flush_workqueue(nvme_wq);
21bd78bc 2717 _nvme_check_size();
b60503ba
MW		 2718}
2719
2720MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2721MODULE_LICENSE("GPL");
c78b4713 2722MODULE_VERSION("1.0");
b60503ba
MW		 2723module_init(nvme_init);
2724module_exit(nvme_exit);
Linux 6.x block layer and io_uring tree(s)