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nvme-pci: add trouble shooting steps for timeouts
[linux-2.6-block.git] / drivers / nvme / host / pci.c
CommitLineData
5f37396d 1// SPDX-License-Identifier: GPL-2.0
b60503ba
MW		 2/*
3 * NVM Express device driver
6eb0d698 4 * Copyright (c) 2011-2014, Intel Corporation.
b60503ba
MW		 5 */
6
df4f9bc4 7#include <linux/acpi.h>
a0a3408e 8#include <linux/aer.h>
18119775 9#include <linux/async.h>
b60503ba 10#include <linux/blkdev.h>
a4aea562 11#include <linux/blk-mq.h>
dca51e78 12#include <linux/blk-mq-pci.h>
fe45e630 13#include <linux/blk-integrity.h>
ff5350a8 14#include <linux/dmi.h>
b60503ba
MW		 15#include <linux/init.h>
16#include <linux/interrupt.h>
17#include <linux/io.h>
dc90f084 18#include <linux/memremap.h>
b60503ba
MW		 19#include <linux/mm.h>
20#include <linux/module.h>
77bf25ea 21#include <linux/mutex.h>
d0877473 22#include <linux/once.h>
b60503ba 23#include <linux/pci.h>
d916b1be 24#include <linux/suspend.h>
e1e5e564 25#include <linux/t10-pi.h>
b60503ba 26#include <linux/types.h>
2f8e2c87 27#include <linux/io-64-nonatomic-lo-hi.h>
20d3bb92 28#include <linux/io-64-nonatomic-hi-lo.h>
a98e58e5 29#include <linux/sed-opal.h>
0f238ff5 30#include <linux/pci-p2pdma.h>
797a796a 31
604c01d5 32#include "trace.h"
f11bb3e2
CH		 33#include "nvme.h"
34
c1e0cc7e 35#define SQ_SIZE(q) ((q)->q_depth << (q)->sqes)
8a1d09a6 36#define CQ_SIZE(q) ((q)->q_depth * sizeof(struct nvme_completion))
c965809c 37
a7a7cbe3 38#define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc))
9d43cf64 39
943e942e
JA		 40/*
41 * These can be higher, but we need to ensure that any command doesn't
42 * require an sg allocation that needs more than a page of data.
43 */
44#define NVME_MAX_KB_SZ 4096
45#define NVME_MAX_SEGS 127
46
58ffacb5 47static int use_threaded_interrupts;
2e21e445 48module_param(use_threaded_interrupts, int, 0444);
58ffacb5 49
8ffaadf7 50static bool use_cmb_sqes = true;
69f4eb9f 51module_param(use_cmb_sqes, bool, 0444);
8ffaadf7
JD		 52MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
53
87ad72a5
CH		 54static unsigned int max_host_mem_size_mb = 128;
55module_param(max_host_mem_size_mb, uint, 0444);
56MODULE_PARM_DESC(max_host_mem_size_mb,
57 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
1fa6aead 58
a7a7cbe3
CK		 59static unsigned int sgl_threshold = SZ_32K;
60module_param(sgl_threshold, uint, 0644);
61MODULE_PARM_DESC(sgl_threshold,
62 "Use SGLs when average request segment size is larger or equal to "
63 "this size. Use 0 to disable SGLs.");
64
27453b45
SG		 65#define NVME_PCI_MIN_QUEUE_SIZE 2
66#define NVME_PCI_MAX_QUEUE_SIZE 4095
b27c1e68 67static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
68static const struct kernel_param_ops io_queue_depth_ops = {
69 .set = io_queue_depth_set,
61f3b896 70 .get = param_get_uint,
b27c1e68 71};
72
61f3b896 73static unsigned int io_queue_depth = 1024;
b27c1e68 74module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
27453b45 75MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2 and < 4096");
b27c1e68 76
9c9e76d5
WZ		 77static int io_queue_count_set(const char *val, const struct kernel_param *kp)
78{
79 unsigned int n;
80 int ret;
81
82 ret = kstrtouint(val, 10, &n);
83 if (ret != 0 || n > num_possible_cpus())
84 return -EINVAL;
85 return param_set_uint(val, kp);
86}
87
88static const struct kernel_param_ops io_queue_count_ops = {
89 .set = io_queue_count_set,
90 .get = param_get_uint,
91};
92
3f68baf7 93static unsigned int write_queues;
9c9e76d5 94module_param_cb(write_queues, &io_queue_count_ops, &write_queues, 0644);
3b6592f7
JA		 95MODULE_PARM_DESC(write_queues,
96 "Number of queues to use for writes. If not set, reads and writes "
97 "will share a queue set.");
98
3f68baf7 99static unsigned int poll_queues;
9c9e76d5 100module_param_cb(poll_queues, &io_queue_count_ops, &poll_queues, 0644);
4b04cc6a
JA		 101MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO.");
102
df4f9bc4
DB		 103static bool noacpi;
104module_param(noacpi, bool, 0444);
105MODULE_PARM_DESC(noacpi, "disable acpi bios quirks");
106
1c63dc66
CH		 107struct nvme_dev;
108struct nvme_queue;
b3fffdef 109
a5cdb68c 110static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
8fae268b 111static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode);
d4b4ff8e 112
1c63dc66
CH		 113/*
114 * Represents an NVM Express device. Each nvme_dev is a PCI function.
115 */
116struct nvme_dev {
147b27e4 117 struct nvme_queue *queues;
1c63dc66
CH		 118 struct blk_mq_tag_set tagset;
119 struct blk_mq_tag_set admin_tagset;
120 u32 __iomem *dbs;
121 struct device *dev;
122 struct dma_pool *prp_page_pool;
123 struct dma_pool *prp_small_pool;
1c63dc66
CH		 124 unsigned online_queues;
125 unsigned max_qid;
e20ba6e1 126 unsigned io_queues[HCTX_MAX_TYPES];
22b55601 127 unsigned int num_vecs;
7442ddce 128 u32 q_depth;
c1e0cc7e 129 int io_sqes;
1c63dc66 130 u32 db_stride;
1c63dc66 131 void __iomem *bar;
97f6ef64 132 unsigned long bar_mapped_size;
5c8809e6 133 struct work_struct remove_work;
77bf25ea 134 struct mutex shutdown_lock;
1c63dc66 135 bool subsystem;
1c63dc66 136 u64 cmb_size;
0f238ff5 137 bool cmb_use_sqes;
1c63dc66 138 u32 cmbsz;
202021c1 139 u32 cmbloc;
1c63dc66 140 struct nvme_ctrl ctrl;
d916b1be 141 u32 last_ps;
a5df5e79 142 bool hmb;
87ad72a5 143
943e942e
JA		 144 mempool_t *iod_mempool;
145
87ad72a5 146 /* shadow doorbell buffer support: */
f9f38e33
HK		 147 u32 *dbbuf_dbs;
148 dma_addr_t dbbuf_dbs_dma_addr;
149 u32 *dbbuf_eis;
150 dma_addr_t dbbuf_eis_dma_addr;
87ad72a5
CH		 151
152 /* host memory buffer support: */
153 u64 host_mem_size;
154 u32 nr_host_mem_descs;
4033f35d 155 dma_addr_t host_mem_descs_dma;
87ad72a5
CH		 156 struct nvme_host_mem_buf_desc *host_mem_descs;
157 void **host_mem_desc_bufs;
2a5bcfdd
WZ		 158 unsigned int nr_allocated_queues;
159 unsigned int nr_write_queues;
160 unsigned int nr_poll_queues;
0521905e
KB		 161
162 bool attrs_added;
4d115420 163};
1fa6aead 164
b27c1e68 165static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
166{
27453b45
SG		 167 return param_set_uint_minmax(val, kp, NVME_PCI_MIN_QUEUE_SIZE,
168 NVME_PCI_MAX_QUEUE_SIZE);
b27c1e68 169}
170
f9f38e33
HK		 171static inline unsigned int sq_idx(unsigned int qid, u32 stride)
172{
173 return qid * 2 * stride;
174}
175
176static inline unsigned int cq_idx(unsigned int qid, u32 stride)
177{
178 return (qid * 2 + 1) * stride;
179}
180
1c63dc66
CH		 181static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
182{
183 return container_of(ctrl, struct nvme_dev, ctrl);
184}
185
b60503ba
MW		 186/*
187 * An NVM Express queue. Each device has at least two (one for admin
188 * commands and one for I/O commands).
189 */
190struct nvme_queue {
091b6092 191 struct nvme_dev *dev;
1ab0cd69 192 spinlock_t sq_lock;
c1e0cc7e 193 void *sq_cmds;
3a7afd8e
CH		 194 /* only used for poll queues: */
195 spinlock_t cq_poll_lock ____cacheline_aligned_in_smp;
74943d45 196 struct nvme_completion *cqes;
b60503ba
MW		 197 dma_addr_t sq_dma_addr;
198 dma_addr_t cq_dma_addr;
b60503ba 199 u32 __iomem *q_db;
7442ddce 200 u32 q_depth;
7c349dde 201 u16 cq_vector;
b60503ba 202 u16 sq_tail;
38210800 203 u16 last_sq_tail;
b60503ba 204 u16 cq_head;
c30341dc 205 u16 qid;
e9539f47 206 u8 cq_phase;
c1e0cc7e 207 u8 sqes;
4e224106
CH		 208 unsigned long flags;
209#define NVMEQ_ENABLED 0
63223078 210#define NVMEQ_SQ_CMB 1
d1ed6aa1 211#define NVMEQ_DELETE_ERROR 2
7c349dde 212#define NVMEQ_POLLED 3
f9f38e33
HK		 213 u32 *dbbuf_sq_db;
214 u32 *dbbuf_cq_db;
215 u32 *dbbuf_sq_ei;
216 u32 *dbbuf_cq_ei;
d1ed6aa1 217 struct completion delete_done;
b60503ba
MW		 218};
219
71bd150c 220/*
9b048119
CH		 221 * The nvme_iod describes the data in an I/O.
222 *
223 * The sg pointer contains the list of PRP/SGL chunk allocations in addition
224 * to the actual struct scatterlist.
71bd150c
CH		 225 */
226struct nvme_iod {
d49187e9 227 struct nvme_request req;
af7fae85 228 struct nvme_command cmd;
f4800d6d 229 struct nvme_queue *nvmeq;
a7a7cbe3 230 bool use_sgl;
f4800d6d 231 int aborted;
71bd150c 232 int npages; /* In the PRP list. 0 means small pool in use */
71bd150c 233 int nents; /* Used in scatterlist */
71bd150c 234 dma_addr_t first_dma;
dff824b2 235 unsigned int dma_len; /* length of single DMA segment mapping */
783b94bd 236 dma_addr_t meta_dma;
f4800d6d 237 struct scatterlist *sg;
b60503ba
MW		 238};
239
2a5bcfdd 240static inline unsigned int nvme_dbbuf_size(struct nvme_dev *dev)
3b6592f7 241{
2a5bcfdd 242 return dev->nr_allocated_queues * 8 * dev->db_stride;
f9f38e33
HK		 243}
244
245static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
246{
2a5bcfdd 247 unsigned int mem_size = nvme_dbbuf_size(dev);
f9f38e33 248
58847f12
KB		 249 if (dev->dbbuf_dbs) {
250 /*
251 * Clear the dbbuf memory so the driver doesn't observe stale
252 * values from the previous instantiation.
253 */
254 memset(dev->dbbuf_dbs, 0, mem_size);
255 memset(dev->dbbuf_eis, 0, mem_size);
f9f38e33 256 return 0;
58847f12 257 }
f9f38e33
HK		 258
259 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
260 &dev->dbbuf_dbs_dma_addr,
261 GFP_KERNEL);
262 if (!dev->dbbuf_dbs)
263 return -ENOMEM;
264 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
265 &dev->dbbuf_eis_dma_addr,
266 GFP_KERNEL);
267 if (!dev->dbbuf_eis) {
268 dma_free_coherent(dev->dev, mem_size,
269 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
270 dev->dbbuf_dbs = NULL;
271 return -ENOMEM;
272 }
273
274 return 0;
275}
276
277static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
278{
2a5bcfdd 279 unsigned int mem_size = nvme_dbbuf_size(dev);
f9f38e33
HK		 280
281 if (dev->dbbuf_dbs) {
282 dma_free_coherent(dev->dev, mem_size,
283 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
284 dev->dbbuf_dbs = NULL;
285 }
286 if (dev->dbbuf_eis) {
287 dma_free_coherent(dev->dev, mem_size,
288 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
289 dev->dbbuf_eis = NULL;
290 }
291}
292
293static void nvme_dbbuf_init(struct nvme_dev *dev,
294 struct nvme_queue *nvmeq, int qid)
295{
296 if (!dev->dbbuf_dbs || !qid)
297 return;
298
299 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
300 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
301 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
302 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
303}
304
0f0d2c87
MI		 305static void nvme_dbbuf_free(struct nvme_queue *nvmeq)
306{
307 if (!nvmeq->qid)
308 return;
309
310 nvmeq->dbbuf_sq_db = NULL;
311 nvmeq->dbbuf_cq_db = NULL;
312 nvmeq->dbbuf_sq_ei = NULL;
313 nvmeq->dbbuf_cq_ei = NULL;
314}
315
f9f38e33
HK		 316static void nvme_dbbuf_set(struct nvme_dev *dev)
317{
f66e2804 318 struct nvme_command c = { };
0f0d2c87 319 unsigned int i;
f9f38e33
HK		 320
321 if (!dev->dbbuf_dbs)
322 return;
323
f9f38e33
HK		 324 c.dbbuf.opcode = nvme_admin_dbbuf;
325 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
326 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
327
328 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
9bdcfb10 329 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
f9f38e33
HK		 330 /* Free memory and continue on */
331 nvme_dbbuf_dma_free(dev);
0f0d2c87
MI		 332
333 for (i = 1; i <= dev->online_queues; i++)
334 nvme_dbbuf_free(&dev->queues[i]);
f9f38e33
HK		 335 }
336}
337
338static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
339{
340 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
341}
342
343/* Update dbbuf and return true if an MMIO is required */
344static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
345 volatile u32 *dbbuf_ei)
346{
347 if (dbbuf_db) {
348 u16 old_value;
349
350 /*
351 * Ensure that the queue is written before updating
352 * the doorbell in memory
353 */
354 wmb();
355
356 old_value = *dbbuf_db;
357 *dbbuf_db = value;
358
f1ed3df2
MW		 359 /*
360 * Ensure that the doorbell is updated before reading the event
361 * index from memory. The controller needs to provide similar
362 * ordering to ensure the envent index is updated before reading
363 * the doorbell.
364 */
365 mb();
366
f9f38e33
HK		 367 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value))
368 return false;
369 }
370
371 return true;
b60503ba
MW		 372}
373
ac3dd5bd
JA		 374/*
375 * Will slightly overestimate the number of pages needed. This is OK
376 * as it only leads to a small amount of wasted memory for the lifetime of
377 * the I/O.
378 */
b13c6393 379static int nvme_pci_npages_prp(void)
ac3dd5bd 380{
b13c6393 381 unsigned nprps = DIV_ROUND_UP(NVME_MAX_KB_SZ + NVME_CTRL_PAGE_SIZE,
6c3c05b0 382 NVME_CTRL_PAGE_SIZE);
ac3dd5bd
JA		 383 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
384}
385
a7a7cbe3
CK		 386/*
387 * Calculates the number of pages needed for the SGL segments. For example a 4k
388 * page can accommodate 256 SGL descriptors.
389 */
b13c6393 390static int nvme_pci_npages_sgl(void)
ac3dd5bd 391{
b13c6393
CK		 392 return DIV_ROUND_UP(NVME_MAX_SEGS * sizeof(struct nvme_sgl_desc),
393 PAGE_SIZE);
f4800d6d 394}
ac3dd5bd 395
b13c6393 396static size_t nvme_pci_iod_alloc_size(void)
f4800d6d 397{
b13c6393 398 size_t npages = max(nvme_pci_npages_prp(), nvme_pci_npages_sgl());
a7a7cbe3 399
b13c6393
CK		 400 return sizeof(__le64 *) * npages +
401 sizeof(struct scatterlist) * NVME_MAX_SEGS;
f4800d6d 402}
ac3dd5bd 403
a4aea562
MB		 404static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
405 unsigned int hctx_idx)
e85248e5 406{
a4aea562 407 struct nvme_dev *dev = data;
147b27e4 408 struct nvme_queue *nvmeq = &dev->queues[0];
a4aea562 409
42483228
KB		 410 WARN_ON(hctx_idx != 0);
411 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
42483228 412
a4aea562
MB		 413 hctx->driver_data = nvmeq;
414 return 0;
e85248e5
MW		 415}
416
a4aea562
MB		 417static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
418 unsigned int hctx_idx)
b60503ba 419{
a4aea562 420 struct nvme_dev *dev = data;
147b27e4 421 struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
a4aea562 422
42483228 423 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
a4aea562
MB		 424 hctx->driver_data = nvmeq;
425 return 0;
b60503ba
MW		 426}
427
e559398f
CH		 428static int nvme_pci_init_request(struct blk_mq_tag_set *set,
429 struct request *req, unsigned int hctx_idx,
430 unsigned int numa_node)
b60503ba 431{
d6296d39 432 struct nvme_dev *dev = set->driver_data;
f4800d6d 433 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
0350815a 434 int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0;
147b27e4 435 struct nvme_queue *nvmeq = &dev->queues[queue_idx];
a4aea562
MB		 436
437 BUG_ON(!nvmeq);
f4800d6d 438 iod->nvmeq = nvmeq;
59e29ce6
SG		 439
440 nvme_req(req)->ctrl = &dev->ctrl;
f4b9e6c9 441 nvme_req(req)->cmd = &iod->cmd;
a4aea562
MB		 442 return 0;
443}
444
3b6592f7
JA		 445static int queue_irq_offset(struct nvme_dev *dev)
446{
447 /* if we have more than 1 vec, admin queue offsets us by 1 */
448 if (dev->num_vecs > 1)
449 return 1;
450
451 return 0;
452}
453
dca51e78
CH		 454static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
455{
456 struct nvme_dev *dev = set->driver_data;
3b6592f7
JA		 457 int i, qoff, offset;
458
459 offset = queue_irq_offset(dev);
460 for (i = 0, qoff = 0; i < set->nr_maps; i++) {
461 struct blk_mq_queue_map *map = &set->map[i];
462
463 map->nr_queues = dev->io_queues[i];
464 if (!map->nr_queues) {
e20ba6e1 465 BUG_ON(i == HCTX_TYPE_DEFAULT);
7e849dd9 466 continue;
3b6592f7
JA		 467 }
468
4b04cc6a
JA		 469 /*
470 * The poll queue(s) doesn't have an IRQ (and hence IRQ
471 * affinity), so use the regular blk-mq cpu mapping
472 */
3b6592f7 473 map->queue_offset = qoff;
cb9e0e50 474 if (i != HCTX_TYPE_POLL && offset)
4b04cc6a
JA		 475 blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset);
476 else
477 blk_mq_map_queues(map);
3b6592f7
JA		 478 qoff += map->nr_queues;
479 offset += map->nr_queues;
480 }
481
482 return 0;
dca51e78
CH		 483}
484
38210800
KB		 485/*
486 * Write sq tail if we are asked to, or if the next command would wrap.
487 */
488static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq)
04f3eafd 489{
38210800
KB		 490 if (!write_sq) {
491 u16 next_tail = nvmeq->sq_tail + 1;
492
493 if (next_tail == nvmeq->q_depth)
494 next_tail = 0;
495 if (next_tail != nvmeq->last_sq_tail)
496 return;
497 }
498
04f3eafd
JA		 499 if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail,
500 nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei))
501 writel(nvmeq->sq_tail, nvmeq->q_db);
38210800 502 nvmeq->last_sq_tail = nvmeq->sq_tail;
04f3eafd
JA		 503}
504
3233b94c
JA		 505static inline void nvme_sq_copy_cmd(struct nvme_queue *nvmeq,
506 struct nvme_command *cmd)
b60503ba 507{
c1e0cc7e 508 memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes),
3233b94c 509 absolute_pointer(cmd), sizeof(*cmd));
90ea5ca4
CH		 510 if (++nvmeq->sq_tail == nvmeq->q_depth)
511 nvmeq->sq_tail = 0;
04f3eafd
JA		 512}
513
514static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx)
515{
516 struct nvme_queue *nvmeq = hctx->driver_data;
517
518 spin_lock(&nvmeq->sq_lock);
38210800
KB		 519 if (nvmeq->sq_tail != nvmeq->last_sq_tail)
520 nvme_write_sq_db(nvmeq, true);
90ea5ca4 521 spin_unlock(&nvmeq->sq_lock);
b60503ba
MW		 522}
523
a7a7cbe3 524static void **nvme_pci_iod_list(struct request *req)
b60503ba 525{
f4800d6d 526 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3 527 return (void **)(iod->sg + blk_rq_nr_phys_segments(req));
b60503ba
MW		 528}
529
955b1b5a
MI		 530static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req)
531{
532 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
20469a37 533 int nseg = blk_rq_nr_phys_segments(req);
955b1b5a
MI		 534 unsigned int avg_seg_size;
535
20469a37 536 avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
955b1b5a 537
253a0b76 538 if (!nvme_ctrl_sgl_supported(&dev->ctrl))
955b1b5a
MI		 539 return false;
540 if (!iod->nvmeq->qid)
541 return false;
542 if (!sgl_threshold || avg_seg_size < sgl_threshold)
543 return false;
544 return true;
545}
546
9275c206 547static void nvme_free_prps(struct nvme_dev *dev, struct request *req)
b60503ba 548{
6c3c05b0 549 const int last_prp = NVME_CTRL_PAGE_SIZE / sizeof(__le64) - 1;
9275c206
CH		 550 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
551 dma_addr_t dma_addr = iod->first_dma;
eca18b23 552 int i;
eca18b23 553
9275c206
CH		 554 for (i = 0; i < iod->npages; i++) {
555 __le64 *prp_list = nvme_pci_iod_list(req)[i];
556 dma_addr_t next_dma_addr = le64_to_cpu(prp_list[last_prp]);
557
558 dma_pool_free(dev->prp_page_pool, prp_list, dma_addr);
559 dma_addr = next_dma_addr;
7fe07d14 560 }
9275c206 561}
dff824b2 562
9275c206
CH		 563static void nvme_free_sgls(struct nvme_dev *dev, struct request *req)
564{
565 const int last_sg = SGES_PER_PAGE - 1;
566 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
567 dma_addr_t dma_addr = iod->first_dma;
568 int i;
dff824b2 569
9275c206
CH		 570 for (i = 0; i < iod->npages; i++) {
571 struct nvme_sgl_desc *sg_list = nvme_pci_iod_list(req)[i];
572 dma_addr_t next_dma_addr = le64_to_cpu((sg_list[last_sg]).addr);
dff824b2 573
9275c206
CH		 574 dma_pool_free(dev->prp_page_pool, sg_list, dma_addr);
575 dma_addr = next_dma_addr;
576 }
9275c206 577}
a7a7cbe3 578
9275c206
CH		 579static void nvme_unmap_sg(struct nvme_dev *dev, struct request *req)
580{
581 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3 582
9275c206
CH		 583 if (is_pci_p2pdma_page(sg_page(iod->sg)))
584 pci_p2pdma_unmap_sg(dev->dev, iod->sg, iod->nents,
585 rq_dma_dir(req));
586 else
587 dma_unmap_sg(dev->dev, iod->sg, iod->nents, rq_dma_dir(req));
588}
a7a7cbe3 589
9275c206
CH		 590static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
591{
592 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3 593
9275c206
CH		 594 if (iod->dma_len) {
595 dma_unmap_page(dev->dev, iod->first_dma, iod->dma_len,
596 rq_dma_dir(req));
597 return;
eca18b23 598 }
ac3dd5bd 599
9275c206
CH		 600 WARN_ON_ONCE(!iod->nents);
601
602 nvme_unmap_sg(dev, req);
603 if (iod->npages == 0)
604 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0],
605 iod->first_dma);
606 else if (iod->use_sgl)
607 nvme_free_sgls(dev, req);
608 else
609 nvme_free_prps(dev, req);
d43f1ccf 610 mempool_free(iod->sg, dev->iod_mempool);
b4ff9c8d
KB		 611}
612
d0877473
KB		 613static void nvme_print_sgl(struct scatterlist *sgl, int nents)
614{
615 int i;
616 struct scatterlist *sg;
617
618 for_each_sg(sgl, sg, nents, i) {
619 dma_addr_t phys = sg_phys(sg);
620 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
621 "dma_address:%pad dma_length:%d\n",
622 i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
623 sg_dma_len(sg));
624 }
625}
626
a7a7cbe3
CK		 627static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
628 struct request *req, struct nvme_rw_command *cmnd)
ff22b54f 629{
f4800d6d 630 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
99802a7a 631 struct dma_pool *pool;
b131c61d 632 int length = blk_rq_payload_bytes(req);
eca18b23 633 struct scatterlist *sg = iod->sg;
ff22b54f
MW		 634 int dma_len = sg_dma_len(sg);
635 u64 dma_addr = sg_dma_address(sg);
6c3c05b0 636 int offset = dma_addr & (NVME_CTRL_PAGE_SIZE - 1);
e025344c 637 __le64 *prp_list;
a7a7cbe3 638 void **list = nvme_pci_iod_list(req);
e025344c 639 dma_addr_t prp_dma;
eca18b23 640 int nprps, i;
ff22b54f 641
6c3c05b0 642 length -= (NVME_CTRL_PAGE_SIZE - offset);
5228b328
JS		 643 if (length <= 0) {
644 iod->first_dma = 0;
a7a7cbe3 645 goto done;
5228b328 646 }
ff22b54f 647
6c3c05b0 648 dma_len -= (NVME_CTRL_PAGE_SIZE - offset);
ff22b54f 649 if (dma_len) {
6c3c05b0 650 dma_addr += (NVME_CTRL_PAGE_SIZE - offset);
ff22b54f
MW		 651 } else {
652 sg = sg_next(sg);
653 dma_addr = sg_dma_address(sg);
654 dma_len = sg_dma_len(sg);
655 }
656
6c3c05b0 657 if (length <= NVME_CTRL_PAGE_SIZE) {
edd10d33 658 iod->first_dma = dma_addr;
a7a7cbe3 659 goto done;
e025344c
SMM		 660 }
661
6c3c05b0 662 nprps = DIV_ROUND_UP(length, NVME_CTRL_PAGE_SIZE);
99802a7a
MW		 663 if (nprps <= (256 / 8)) {
664 pool = dev->prp_small_pool;
eca18b23 665 iod->npages = 0;
99802a7a
MW		 666 } else {
667 pool = dev->prp_page_pool;
eca18b23 668 iod->npages = 1;
99802a7a
MW		 669 }
670
69d2b571 671 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
b77954cb 672 if (!prp_list) {
edd10d33 673 iod->first_dma = dma_addr;
eca18b23 674 iod->npages = -1;
86eea289 675 return BLK_STS_RESOURCE;
b77954cb 676 }
eca18b23
MW		 677 list[0] = prp_list;
678 iod->first_dma = prp_dma;
e025344c
SMM		 679 i = 0;
680 for (;;) {
6c3c05b0 681 if (i == NVME_CTRL_PAGE_SIZE >> 3) {
e025344c 682 __le64 *old_prp_list = prp_list;
69d2b571 683 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
eca18b23 684 if (!prp_list)
fa073216 685 goto free_prps;
eca18b23 686 list[iod->npages++] = prp_list;
7523d834
MW		 687 prp_list[0] = old_prp_list[i - 1];
688 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
689 i = 1;
e025344c
SMM		 690 }
691 prp_list[i++] = cpu_to_le64(dma_addr);
6c3c05b0
CK		 692 dma_len -= NVME_CTRL_PAGE_SIZE;
693 dma_addr += NVME_CTRL_PAGE_SIZE;
694 length -= NVME_CTRL_PAGE_SIZE;
e025344c
SMM		 695 if (length <= 0)
696 break;
697 if (dma_len > 0)
698 continue;
86eea289
KB		 699 if (unlikely(dma_len < 0))
700 goto bad_sgl;
e025344c
SMM		 701 sg = sg_next(sg);
702 dma_addr = sg_dma_address(sg);
703 dma_len = sg_dma_len(sg);
ff22b54f 704 }
a7a7cbe3
CK		 705done:
706 cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
707 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
86eea289 708 return BLK_STS_OK;
fa073216
CH		 709free_prps:
710 nvme_free_prps(dev, req);
711 return BLK_STS_RESOURCE;
712bad_sgl:
d0877473
KB		 713 WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents),
714 "Invalid SGL for payload:%d nents:%d\n",
715 blk_rq_payload_bytes(req), iod->nents);
86eea289 716 return BLK_STS_IOERR;
ff22b54f
MW		 717}
718
a7a7cbe3
CK		 719static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
720 struct scatterlist *sg)
721{
722 sge->addr = cpu_to_le64(sg_dma_address(sg));
723 sge->length = cpu_to_le32(sg_dma_len(sg));
724 sge->type = NVME_SGL_FMT_DATA_DESC << 4;
725}
726
727static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
728 dma_addr_t dma_addr, int entries)
729{
730 sge->addr = cpu_to_le64(dma_addr);
731 if (entries < SGES_PER_PAGE) {
732 sge->length = cpu_to_le32(entries * sizeof(*sge));
733 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
734 } else {
735 sge->length = cpu_to_le32(PAGE_SIZE);
736 sge->type = NVME_SGL_FMT_SEG_DESC << 4;
737 }
738}
739
740static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
b0f2853b 741 struct request *req, struct nvme_rw_command *cmd, int entries)
a7a7cbe3
CK		 742{
743 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3
CK		 744 struct dma_pool *pool;
745 struct nvme_sgl_desc *sg_list;
746 struct scatterlist *sg = iod->sg;
a7a7cbe3 747 dma_addr_t sgl_dma;
b0f2853b 748 int i = 0;
a7a7cbe3 749
a7a7cbe3
CK		 750 /* setting the transfer type as SGL */
751 cmd->flags = NVME_CMD_SGL_METABUF;
752
b0f2853b 753 if (entries == 1) {
a7a7cbe3
CK		 754 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
755 return BLK_STS_OK;
756 }
757
758 if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
759 pool = dev->prp_small_pool;
760 iod->npages = 0;
761 } else {
762 pool = dev->prp_page_pool;
763 iod->npages = 1;
764 }
765
766 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
767 if (!sg_list) {
768 iod->npages = -1;
769 return BLK_STS_RESOURCE;
770 }
771
772 nvme_pci_iod_list(req)[0] = sg_list;
773 iod->first_dma = sgl_dma;
774
775 nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
776
777 do {
778 if (i == SGES_PER_PAGE) {
779 struct nvme_sgl_desc *old_sg_desc = sg_list;
780 struct nvme_sgl_desc *link = &old_sg_desc[i - 1];
781
782 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
783 if (!sg_list)
fa073216 784 goto free_sgls;
a7a7cbe3
CK		 785
786 i = 0;
787 nvme_pci_iod_list(req)[iod->npages++] = sg_list;
788 sg_list[i++] = *link;
789 nvme_pci_sgl_set_seg(link, sgl_dma, entries);
790 }
791
792 nvme_pci_sgl_set_data(&sg_list[i++], sg);
a7a7cbe3 793 sg = sg_next(sg);
b0f2853b 794 } while (--entries > 0);
a7a7cbe3 795
a7a7cbe3 796 return BLK_STS_OK;
fa073216
CH		 797free_sgls:
798 nvme_free_sgls(dev, req);
799 return BLK_STS_RESOURCE;
a7a7cbe3
CK		 800}
801
dff824b2
CH		 802static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev,
803 struct request *req, struct nvme_rw_command *cmnd,
804 struct bio_vec *bv)
805{
806 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
6c3c05b0
CK		 807 unsigned int offset = bv->bv_offset & (NVME_CTRL_PAGE_SIZE - 1);
808 unsigned int first_prp_len = NVME_CTRL_PAGE_SIZE - offset;
dff824b2
CH		 809
810 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
811 if (dma_mapping_error(dev->dev, iod->first_dma))
812 return BLK_STS_RESOURCE;
813 iod->dma_len = bv->bv_len;
814
815 cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma);
816 if (bv->bv_len > first_prp_len)
817 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len);
359c1f88 818 return BLK_STS_OK;
dff824b2
CH		 819}
820
29791057
CH		 821static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev,
822 struct request *req, struct nvme_rw_command *cmnd,
823 struct bio_vec *bv)
824{
825 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
826
827 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
828 if (dma_mapping_error(dev->dev, iod->first_dma))
829 return BLK_STS_RESOURCE;
830 iod->dma_len = bv->bv_len;
831
049bf372 832 cmnd->flags = NVME_CMD_SGL_METABUF;
29791057
CH		 833 cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma);
834 cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len);
835 cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4;
359c1f88 836 return BLK_STS_OK;
29791057
CH		 837}
838
fc17b653 839static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
b131c61d 840 struct nvme_command *cmnd)
d29ec824 841{
f4800d6d 842 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
70479b71 843 blk_status_t ret = BLK_STS_RESOURCE;
b0f2853b 844 int nr_mapped;
d29ec824 845
dff824b2
CH		 846 if (blk_rq_nr_phys_segments(req) == 1) {
847 struct bio_vec bv = req_bvec(req);
848
849 if (!is_pci_p2pdma_page(bv.bv_page)) {
6c3c05b0 850 if (bv.bv_offset + bv.bv_len <= NVME_CTRL_PAGE_SIZE * 2)
dff824b2
CH		 851 return nvme_setup_prp_simple(dev, req,
852 &cmnd->rw, &bv);
29791057 853
e51183be 854 if (iod->nvmeq->qid && sgl_threshold &&
253a0b76 855 nvme_ctrl_sgl_supported(&dev->ctrl))
29791057
CH		 856 return nvme_setup_sgl_simple(dev, req,
857 &cmnd->rw, &bv);
dff824b2
CH		 858 }
859 }
860
861 iod->dma_len = 0;
d43f1ccf
CH		 862 iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC);
863 if (!iod->sg)
864 return BLK_STS_RESOURCE;
f9d03f96 865 sg_init_table(iod->sg, blk_rq_nr_phys_segments(req));
70479b71 866 iod->nents = blk_rq_map_sg(req->q, req, iod->sg);
ba1ca37e 867 if (!iod->nents)
fa073216 868 goto out_free_sg;
d29ec824 869
e0596ab2 870 if (is_pci_p2pdma_page(sg_page(iod->sg)))
2b9f4bb2
LG		 871 nr_mapped = pci_p2pdma_map_sg_attrs(dev->dev, iod->sg,
872 iod->nents, rq_dma_dir(req), DMA_ATTR_NO_WARN);
e0596ab2
LG		 873 else
874 nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents,
70479b71 875 rq_dma_dir(req), DMA_ATTR_NO_WARN);
b0f2853b 876 if (!nr_mapped)
fa073216 877 goto out_free_sg;
d29ec824 878
70479b71 879 iod->use_sgl = nvme_pci_use_sgls(dev, req);
955b1b5a 880 if (iod->use_sgl)
b0f2853b 881 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped);
a7a7cbe3
CK		 882 else
883 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
86eea289 884 if (ret != BLK_STS_OK)
fa073216
CH		 885 goto out_unmap_sg;
886 return BLK_STS_OK;
887
888out_unmap_sg:
889 nvme_unmap_sg(dev, req);
890out_free_sg:
891 mempool_free(iod->sg, dev->iod_mempool);
4aedb705
CH		 892 return ret;
893}
3045c0d0 894
4aedb705
CH		 895static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req,
896 struct nvme_command *cmnd)
897{
898 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
00df5cb4 899
4aedb705
CH		 900 iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req),
901 rq_dma_dir(req), 0);
902 if (dma_mapping_error(dev->dev, iod->meta_dma))
903 return BLK_STS_IOERR;
904 cmnd->rw.metadata = cpu_to_le64(iod->meta_dma);
359c1f88 905 return BLK_STS_OK;
00df5cb4
MW		 906}
907
62451a2b 908static blk_status_t nvme_prep_rq(struct nvme_dev *dev, struct request *req)
edd10d33 909{
9b048119 910 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
ebe6d874 911 blk_status_t ret;
e1e5e564 912
9b048119
CH		 913 iod->aborted = 0;
914 iod->npages = -1;
915 iod->nents = 0;
916
62451a2b 917 ret = nvme_setup_cmd(req->q->queuedata, req);
fc17b653 918 if (ret)
f4800d6d 919 return ret;
a4aea562 920
fc17b653 921 if (blk_rq_nr_phys_segments(req)) {
62451a2b 922 ret = nvme_map_data(dev, req, &iod->cmd);
fc17b653 923 if (ret)
9b048119 924 goto out_free_cmd;
fc17b653 925 }
a4aea562 926
4aedb705 927 if (blk_integrity_rq(req)) {
62451a2b 928 ret = nvme_map_metadata(dev, req, &iod->cmd);
4aedb705
CH		 929 if (ret)
930 goto out_unmap_data;
931 }
932
aae239e1 933 blk_mq_start_request(req);
fc17b653 934 return BLK_STS_OK;
4aedb705
CH		 935out_unmap_data:
936 nvme_unmap_data(dev, req);
f9d03f96
CH		 937out_free_cmd:
938 nvme_cleanup_cmd(req);
ba1ca37e 939 return ret;
b60503ba 940}
e1e5e564 941
62451a2b
JA		 942/*
943 * NOTE: ns is NULL when called on the admin queue.
944 */
945static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
946 const struct blk_mq_queue_data *bd)
947{
948 struct nvme_queue *nvmeq = hctx->driver_data;
949 struct nvme_dev *dev = nvmeq->dev;
950 struct request *req = bd->rq;
951 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
952 blk_status_t ret;
953
954 /*
955 * We should not need to do this, but we're still using this to
956 * ensure we can drain requests on a dying queue.
957 */
958 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
959 return BLK_STS_IOERR;
960
961 if (unlikely(!nvme_check_ready(&dev->ctrl, req, true)))
962 return nvme_fail_nonready_command(&dev->ctrl, req);
963
964 ret = nvme_prep_rq(dev, req);
965 if (unlikely(ret))
966 return ret;
967 spin_lock(&nvmeq->sq_lock);
968 nvme_sq_copy_cmd(nvmeq, &iod->cmd);
969 nvme_write_sq_db(nvmeq, bd->last);
970 spin_unlock(&nvmeq->sq_lock);
971 return BLK_STS_OK;
972}
973
d62cbcf6
JA		 974static void nvme_submit_cmds(struct nvme_queue *nvmeq, struct request **rqlist)
975{
976 spin_lock(&nvmeq->sq_lock);
977 while (!rq_list_empty(*rqlist)) {
978 struct request *req = rq_list_pop(rqlist);
979 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
980
981 nvme_sq_copy_cmd(nvmeq, &iod->cmd);
982 }
983 nvme_write_sq_db(nvmeq, true);
984 spin_unlock(&nvmeq->sq_lock);
985}
986
987static bool nvme_prep_rq_batch(struct nvme_queue *nvmeq, struct request *req)
988{
989 /*
990 * We should not need to do this, but we're still using this to
991 * ensure we can drain requests on a dying queue.
992 */
993 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
994 return false;
995 if (unlikely(!nvme_check_ready(&nvmeq->dev->ctrl, req, true)))
996 return false;
997
998 req->mq_hctx->tags->rqs[req->tag] = req;
999 return nvme_prep_rq(nvmeq->dev, req) == BLK_STS_OK;
1000}
1001
1002static void nvme_queue_rqs(struct request **rqlist)
1003{
6bfec799 1004 struct request *req, *next, *prev = NULL;
d62cbcf6
JA		 1005 struct request *requeue_list = NULL;
1006
6bfec799 1007 rq_list_for_each_safe(rqlist, req, next) {
d62cbcf6
JA		 1008 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
1009
1010 if (!nvme_prep_rq_batch(nvmeq, req)) {
1011 /* detach 'req' and add to remainder list */
6bfec799
KB		 1012 rq_list_move(rqlist, &requeue_list, req, prev);
1013
1014 req = prev;
1015 if (!req)
1016 continue;
d62cbcf6
JA		 1017 }
1018
6bfec799 1019 if (!next || req->mq_hctx != next->mq_hctx) {
d62cbcf6 1020 /* detach rest of list, and submit */
6bfec799 1021 req->rq_next = NULL;
d62cbcf6 1022 nvme_submit_cmds(nvmeq, rqlist);
6bfec799
KB		 1023 *rqlist = next;
1024 prev = NULL;
1025 } else
1026 prev = req;
1027 }
d62cbcf6
JA		 1028
1029 *rqlist = requeue_list;
1030}
1031
c234a653 1032static __always_inline void nvme_pci_unmap_rq(struct request *req)
eee417b0 1033{
f4800d6d 1034 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
4aedb705 1035 struct nvme_dev *dev = iod->nvmeq->dev;
a4aea562 1036
4aedb705
CH		 1037 if (blk_integrity_rq(req))
1038 dma_unmap_page(dev->dev, iod->meta_dma,
1039 rq_integrity_vec(req)->bv_len, rq_data_dir(req));
b15c592d 1040 if (blk_rq_nr_phys_segments(req))
4aedb705 1041 nvme_unmap_data(dev, req);
c234a653
JA		 1042}
1043
1044static void nvme_pci_complete_rq(struct request *req)
1045{
1046 nvme_pci_unmap_rq(req);
77f02a7a 1047 nvme_complete_rq(req);
b60503ba
MW		 1048}
1049
c234a653
JA		 1050static void nvme_pci_complete_batch(struct io_comp_batch *iob)
1051{
1052 nvme_complete_batch(iob, nvme_pci_unmap_rq);
1053}
1054
d783e0bd 1055/* We read the CQE phase first to check if the rest of the entry is valid */
750dde44 1056static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq)
d783e0bd 1057{
74943d45
KB		 1058 struct nvme_completion *hcqe = &nvmeq->cqes[nvmeq->cq_head];
1059
1060 return (le16_to_cpu(READ_ONCE(hcqe->status)) & 1) == nvmeq->cq_phase;
d783e0bd
MR		 1061}
1062
eb281c82 1063static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
b60503ba 1064{
eb281c82 1065 u16 head = nvmeq->cq_head;
adf68f21 1066
397c699f
KB		 1067 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
1068 nvmeq->dbbuf_cq_ei))
1069 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
eb281c82 1070}
aae239e1 1071
cfa27356
CH		 1072static inline struct blk_mq_tags *nvme_queue_tagset(struct nvme_queue *nvmeq)
1073{
1074 if (!nvmeq->qid)
1075 return nvmeq->dev->admin_tagset.tags[0];
1076 return nvmeq->dev->tagset.tags[nvmeq->qid - 1];
1077}
1078
c234a653
JA		 1079static inline void nvme_handle_cqe(struct nvme_queue *nvmeq,
1080 struct io_comp_batch *iob, u16 idx)
83a12fb7 1081{
74943d45 1082 struct nvme_completion *cqe = &nvmeq->cqes[idx];
62df8016 1083 __u16 command_id = READ_ONCE(cqe->command_id);
83a12fb7 1084 struct request *req;
adf68f21 1085
83a12fb7
SG		 1086 /*
1087 * AEN requests are special as they don't time out and can
1088 * survive any kind of queue freeze and often don't respond to
1089 * aborts. We don't even bother to allocate a struct request
1090 * for them but rather special case them here.
1091 */
62df8016 1092 if (unlikely(nvme_is_aen_req(nvmeq->qid, command_id))) {
83a12fb7
SG		 1093 nvme_complete_async_event(&nvmeq->dev->ctrl,
1094 cqe->status, &cqe->result);
a0fa9647 1095 return;
83a12fb7 1096 }
b60503ba 1097
e7006de6 1098 req = nvme_find_rq(nvme_queue_tagset(nvmeq), command_id);
50b7c243
XT		 1099 if (unlikely(!req)) {
1100 dev_warn(nvmeq->dev->ctrl.device,
1101 "invalid id %d completed on queue %d\n",
62df8016 1102 command_id, le16_to_cpu(cqe->sq_id));
50b7c243
XT		 1103 return;
1104 }
1105
604c01d5 1106 trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail);
c234a653
JA		 1107 if (!nvme_try_complete_req(req, cqe->status, cqe->result) &&
1108 !blk_mq_add_to_batch(req, iob, nvme_req(req)->status,
1109 nvme_pci_complete_batch))
ff029451 1110 nvme_pci_complete_rq(req);
83a12fb7 1111}
b60503ba 1112
5cb525c8
JA		 1113static inline void nvme_update_cq_head(struct nvme_queue *nvmeq)
1114{
a0aac973 1115 u32 tmp = nvmeq->cq_head + 1;
a8de6639
AD		 1116
1117 if (tmp == nvmeq->q_depth) {
5cb525c8 1118 nvmeq->cq_head = 0;
e2a366a4 1119 nvmeq->cq_phase ^= 1;
a8de6639
AD		 1120 } else {
1121 nvmeq->cq_head = tmp;
b60503ba 1122 }
a0fa9647
JA		 1123}
1124
c234a653
JA		 1125static inline int nvme_poll_cq(struct nvme_queue *nvmeq,
1126 struct io_comp_batch *iob)
a0fa9647 1127{
1052b8ac 1128 int found = 0;
b60503ba 1129
1052b8ac 1130 while (nvme_cqe_pending(nvmeq)) {
bf392a5d 1131 found++;
b69e2ef2
KB		 1132 /*
1133 * load-load control dependency between phase and the rest of
1134 * the cqe requires a full read memory barrier
1135 */
1136 dma_rmb();
c234a653 1137 nvme_handle_cqe(nvmeq, iob, nvmeq->cq_head);
5cb525c8 1138 nvme_update_cq_head(nvmeq);
920d13a8 1139 }
eb281c82 1140
324b494c 1141 if (found)
920d13a8 1142 nvme_ring_cq_doorbell(nvmeq);
5cb525c8 1143 return found;
b60503ba
MW		 1144}
1145
1146static irqreturn_t nvme_irq(int irq, void *data)
58ffacb5 1147{
58ffacb5 1148 struct nvme_queue *nvmeq = data;
4f502245 1149 DEFINE_IO_COMP_BATCH(iob);
5cb525c8 1150
4f502245
JA		 1151 if (nvme_poll_cq(nvmeq, &iob)) {
1152 if (!rq_list_empty(iob.req_list))
1153 nvme_pci_complete_batch(&iob);
05fae499 1154 return IRQ_HANDLED;
4f502245 1155 }
05fae499 1156 return IRQ_NONE;
58ffacb5
MW		 1157}
1158
1159static irqreturn_t nvme_irq_check(int irq, void *data)
1160{
1161 struct nvme_queue *nvmeq = data;
4e523547 1162
750dde44 1163 if (nvme_cqe_pending(nvmeq))
d783e0bd
MR		 1164 return IRQ_WAKE_THREAD;
1165 return IRQ_NONE;
58ffacb5
MW		 1166}
1167
0b2a8a9f 1168/*
fa059b85 1169 * Poll for completions for any interrupt driven queue
0b2a8a9f
CH		 1170 * Can be called from any context.
1171 */
fa059b85 1172static void nvme_poll_irqdisable(struct nvme_queue *nvmeq)
a0fa9647 1173{
3a7afd8e 1174 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
a0fa9647 1175
fa059b85 1176 WARN_ON_ONCE(test_bit(NVMEQ_POLLED, &nvmeq->flags));
442e19b7 1177
fa059b85 1178 disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
c234a653 1179 nvme_poll_cq(nvmeq, NULL);
fa059b85 1180 enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
a0fa9647
JA		 1181}
1182
5a72e899 1183static int nvme_poll(struct blk_mq_hw_ctx *hctx, struct io_comp_batch *iob)
dabcefab
JA		 1184{
1185 struct nvme_queue *nvmeq = hctx->driver_data;
dabcefab
JA		 1186 bool found;
1187
1188 if (!nvme_cqe_pending(nvmeq))
1189 return 0;
1190
3a7afd8e 1191 spin_lock(&nvmeq->cq_poll_lock);
c234a653 1192 found = nvme_poll_cq(nvmeq, iob);
3a7afd8e 1193 spin_unlock(&nvmeq->cq_poll_lock);
dabcefab 1194
dabcefab
JA		 1195 return found;
1196}
1197
ad22c355 1198static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
b60503ba 1199{
f866fc42 1200 struct nvme_dev *dev = to_nvme_dev(ctrl);
147b27e4 1201 struct nvme_queue *nvmeq = &dev->queues[0];
f66e2804 1202 struct nvme_command c = { };
b60503ba 1203
a4aea562 1204 c.common.opcode = nvme_admin_async_event;
ad22c355 1205 c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
3233b94c
JA		 1206
1207 spin_lock(&nvmeq->sq_lock);
1208 nvme_sq_copy_cmd(nvmeq, &c);
1209 nvme_write_sq_db(nvmeq, true);
1210 spin_unlock(&nvmeq->sq_lock);
f705f837
CH		 1211}
1212
b60503ba 1213static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
f705f837 1214{
f66e2804 1215 struct nvme_command c = { };
b60503ba 1216
b60503ba
MW		 1217 c.delete_queue.opcode = opcode;
1218 c.delete_queue.qid = cpu_to_le16(id);
1219
1c63dc66 1220 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1221}
1222
b60503ba 1223static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
a8e3e0bb 1224 struct nvme_queue *nvmeq, s16 vector)
b60503ba 1225{
f66e2804 1226 struct nvme_command c = { };
4b04cc6a
JA		 1227 int flags = NVME_QUEUE_PHYS_CONTIG;
1228
7c349dde 1229 if (!test_bit(NVMEQ_POLLED, &nvmeq->flags))
4b04cc6a 1230 flags |= NVME_CQ_IRQ_ENABLED;
b60503ba 1231
d29ec824 1232 /*
16772ae6 1233 * Note: we (ab)use the fact that the prp fields survive if no data
d29ec824
CH		 1234 * is attached to the request.
1235 */
b60503ba
MW		 1236 c.create_cq.opcode = nvme_admin_create_cq;
1237 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1238 c.create_cq.cqid = cpu_to_le16(qid);
1239 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1240 c.create_cq.cq_flags = cpu_to_le16(flags);
7c349dde 1241 c.create_cq.irq_vector = cpu_to_le16(vector);
b60503ba 1242
1c63dc66 1243 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1244}
1245
1246static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1247 struct nvme_queue *nvmeq)
1248{
9abd68ef 1249 struct nvme_ctrl *ctrl = &dev->ctrl;
f66e2804 1250 struct nvme_command c = { };
81c1cd98 1251 int flags = NVME_QUEUE_PHYS_CONTIG;
b60503ba 1252
9abd68ef
JA		 1253 /*
1254 * Some drives have a bug that auto-enables WRRU if MEDIUM isn't
1255 * set. Since URGENT priority is zeroes, it makes all queues
1256 * URGENT.
1257 */
1258 if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ)
1259 flags |= NVME_SQ_PRIO_MEDIUM;
1260
d29ec824 1261 /*
16772ae6 1262 * Note: we (ab)use the fact that the prp fields survive if no data
d29ec824
CH		 1263 * is attached to the request.
1264 */
b60503ba
MW		 1265 c.create_sq.opcode = nvme_admin_create_sq;
1266 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1267 c.create_sq.sqid = cpu_to_le16(qid);
1268 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1269 c.create_sq.sq_flags = cpu_to_le16(flags);
1270 c.create_sq.cqid = cpu_to_le16(qid);
1271
1c63dc66 1272 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1273}
1274
1275static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1276{
1277 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1278}
1279
1280static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1281{
1282 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1283}
1284
2a842aca 1285static void abort_endio(struct request *req, blk_status_t error)
bc5fc7e4 1286{
f4800d6d
CH		 1287 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1288 struct nvme_queue *nvmeq = iod->nvmeq;
e44ac588 1289
27fa9bc5
CH		 1290 dev_warn(nvmeq->dev->ctrl.device,
1291 "Abort status: 0x%x", nvme_req(req)->status);
e7a2a87d 1292 atomic_inc(&nvmeq->dev->ctrl.abort_limit);
e7a2a87d 1293 blk_mq_free_request(req);
bc5fc7e4
MW		 1294}
1295
b2a0eb1a
KB		 1296static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1297{
b2a0eb1a
KB		 1298 /* If true, indicates loss of adapter communication, possibly by a
1299 * NVMe Subsystem reset.
1300 */
1301 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1302
ad70062c
JW		 1303 /* If there is a reset/reinit ongoing, we shouldn't reset again. */
1304 switch (dev->ctrl.state) {
1305 case NVME_CTRL_RESETTING:
ad6a0a52 1306 case NVME_CTRL_CONNECTING:
b2a0eb1a 1307 return false;
ad70062c
JW		 1308 default:
1309 break;
1310 }
b2a0eb1a
KB		 1311
1312 /* We shouldn't reset unless the controller is on fatal error state
1313 * _or_ if we lost the communication with it.
1314 */
1315 if (!(csts & NVME_CSTS_CFS) && !nssro)
1316 return false;
1317
b2a0eb1a
KB		 1318 return true;
1319}
1320
1321static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1322{
1323 /* Read a config register to help see what died. */
1324 u16 pci_status;
1325 int result;
1326
1327 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1328 &pci_status);
1329 if (result == PCIBIOS_SUCCESSFUL)
1330 dev_warn(dev->ctrl.device,
1331 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1332 csts, pci_status);
1333 else
1334 dev_warn(dev->ctrl.device,
1335 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1336 csts, result);
4641a8e6
KB		 1337
1338 if (csts != ~0)
1339 return;
1340
1341 dev_warn(dev->ctrl.device,
1342 "Does your device have a faulty power saving mode enabled?\n");
1343 dev_warn(dev->ctrl.device,
1344 "Try \"nvme_core.default_ps_max_latency_us=0 pcie_aspm=off\" and report a bug\n");
b2a0eb1a
KB		 1345}
1346
31c7c7d2 1347static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
c30341dc 1348{
f4800d6d
CH		 1349 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1350 struct nvme_queue *nvmeq = iod->nvmeq;
c30341dc 1351 struct nvme_dev *dev = nvmeq->dev;
a4aea562 1352 struct request *abort_req;
f66e2804 1353 struct nvme_command cmd = { };
b2a0eb1a
KB		 1354 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1355
651438bb
WX		 1356 /* If PCI error recovery process is happening, we cannot reset or
1357 * the recovery mechanism will surely fail.
1358 */
1359 mb();
1360 if (pci_channel_offline(to_pci_dev(dev->dev)))
1361 return BLK_EH_RESET_TIMER;
1362
b2a0eb1a
KB		 1363 /*
1364 * Reset immediately if the controller is failed
1365 */
1366 if (nvme_should_reset(dev, csts)) {
1367 nvme_warn_reset(dev, csts);
1368 nvme_dev_disable(dev, false);
d86c4d8e 1369 nvme_reset_ctrl(&dev->ctrl);
db8c48e4 1370 return BLK_EH_DONE;
b2a0eb1a 1371 }
c30341dc 1372
7776db1c
KB		 1373 /*
1374 * Did we miss an interrupt?
1375 */
fa059b85 1376 if (test_bit(NVMEQ_POLLED, &nvmeq->flags))
5a72e899 1377 nvme_poll(req->mq_hctx, NULL);
fa059b85
KB		 1378 else
1379 nvme_poll_irqdisable(nvmeq);
1380
bf392a5d 1381 if (blk_mq_request_completed(req)) {
7776db1c
KB		 1382 dev_warn(dev->ctrl.device,
1383 "I/O %d QID %d timeout, completion polled\n",
1384 req->tag, nvmeq->qid);
db8c48e4 1385 return BLK_EH_DONE;
7776db1c
KB		 1386 }
1387
31c7c7d2 1388 /*
fd634f41
CH		 1389 * Shutdown immediately if controller times out while starting. The
1390 * reset work will see the pci device disabled when it gets the forced
1391 * cancellation error. All outstanding requests are completed on
db8c48e4 1392 * shutdown, so we return BLK_EH_DONE.
fd634f41 1393 */
4244140d
KB		 1394 switch (dev->ctrl.state) {
1395 case NVME_CTRL_CONNECTING:
2036f726 1396 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
df561f66 1397 fallthrough;
2036f726 1398 case NVME_CTRL_DELETING:
b9cac43c 1399 dev_warn_ratelimited(dev->ctrl.device,
fd634f41
CH		 1400 "I/O %d QID %d timeout, disable controller\n",
1401 req->tag, nvmeq->qid);
27fa9bc5 1402 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
7ad92f65 1403 nvme_dev_disable(dev, true);
db8c48e4 1404 return BLK_EH_DONE;
39a9dd81
KB		 1405 case NVME_CTRL_RESETTING:
1406 return BLK_EH_RESET_TIMER;
4244140d
KB		 1407 default:
1408 break;
c30341dc
KB		 1409 }
1410
fd634f41 1411 /*
ee0d96d3
BW		 1412 * Shutdown the controller immediately and schedule a reset if the
1413 * command was already aborted once before and still hasn't been
1414 * returned to the driver, or if this is the admin queue.
31c7c7d2 1415 */
f4800d6d 1416 if (!nvmeq->qid || iod->aborted) {
1b3c47c1 1417 dev_warn(dev->ctrl.device,
e1569a16
KB		 1418 "I/O %d QID %d timeout, reset controller\n",
1419 req->tag, nvmeq->qid);
7ad92f65 1420 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
a5cdb68c 1421 nvme_dev_disable(dev, false);
d86c4d8e 1422 nvme_reset_ctrl(&dev->ctrl);
c30341dc 1423
db8c48e4 1424 return BLK_EH_DONE;
c30341dc 1425 }
c30341dc 1426
e7a2a87d 1427 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
6bf25d16 1428 atomic_inc(&dev->ctrl.abort_limit);
31c7c7d2 1429 return BLK_EH_RESET_TIMER;
6bf25d16 1430 }
7bf7d778 1431 iod->aborted = 1;
a4aea562 1432
c30341dc 1433 cmd.abort.opcode = nvme_admin_abort_cmd;
85f74acf 1434 cmd.abort.cid = nvme_cid(req);
c30341dc 1435 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
c30341dc 1436
1b3c47c1
SG		 1437 dev_warn(nvmeq->dev->ctrl.device,
1438 "I/O %d QID %d timeout, aborting\n",
1439 req->tag, nvmeq->qid);
e7a2a87d 1440
e559398f
CH		 1441 abort_req = blk_mq_alloc_request(dev->ctrl.admin_q, nvme_req_op(&cmd),
1442 BLK_MQ_REQ_NOWAIT);
e7a2a87d
CH		 1443 if (IS_ERR(abort_req)) {
1444 atomic_inc(&dev->ctrl.abort_limit);
1445 return BLK_EH_RESET_TIMER;
1446 }
e559398f 1447 nvme_init_request(abort_req, &cmd);
e7a2a87d 1448
e2e53086 1449 abort_req->end_io = abort_endio;
e7a2a87d 1450 abort_req->end_io_data = NULL;
128126a7 1451 abort_req->rq_flags |= RQF_QUIET;
e2e53086 1452 blk_execute_rq_nowait(abort_req, false);
c30341dc 1453
31c7c7d2
CH		 1454 /*
1455 * The aborted req will be completed on receiving the abort req.
1456 * We enable the timer again. If hit twice, it'll cause a device reset,
1457 * as the device then is in a faulty state.
1458 */
1459 return BLK_EH_RESET_TIMER;
c30341dc
KB		 1460}
1461
a4aea562
MB		 1462static void nvme_free_queue(struct nvme_queue *nvmeq)
1463{
8a1d09a6 1464 dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq),
9e866774 1465 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
63223078
CH		 1466 if (!nvmeq->sq_cmds)
1467 return;
0f238ff5 1468
63223078 1469 if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) {
88a041f4 1470 pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev),
8a1d09a6 1471 nvmeq->sq_cmds, SQ_SIZE(nvmeq));
63223078 1472 } else {
8a1d09a6 1473 dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq),
63223078 1474 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
0f238ff5 1475 }
9e866774
MW		 1476}
1477
a1a5ef99 1478static void nvme_free_queues(struct nvme_dev *dev, int lowest)
22404274
KB		 1479{
1480 int i;
1481
d858e5f0 1482 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
d858e5f0 1483 dev->ctrl.queue_count--;
147b27e4 1484 nvme_free_queue(&dev->queues[i]);
121c7ad4 1485 }
22404274
KB		 1486}
1487
4d115420
KB		 1488/**
1489 * nvme_suspend_queue - put queue into suspended state
40581d1a 1490 * @nvmeq: queue to suspend
4d115420
KB		 1491 */
1492static int nvme_suspend_queue(struct nvme_queue *nvmeq)
b60503ba 1493{
4e224106 1494 if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags))
2b25d981 1495 return 1;
a09115b2 1496
4e224106 1497 /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */
d1f06f4a 1498 mb();
a09115b2 1499
4e224106 1500 nvmeq->dev->online_queues--;
1c63dc66 1501 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
6ca1d902 1502 nvme_stop_admin_queue(&nvmeq->dev->ctrl);
7c349dde
KB		 1503 if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags))
1504 pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq);
4d115420
KB		 1505 return 0;
1506}
b60503ba 1507
8fae268b
KB		 1508static void nvme_suspend_io_queues(struct nvme_dev *dev)
1509{
1510 int i;
1511
1512 for (i = dev->ctrl.queue_count - 1; i > 0; i--)
1513 nvme_suspend_queue(&dev->queues[i]);
1514}
1515
a5cdb68c 1516static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
4d115420 1517{
147b27e4 1518 struct nvme_queue *nvmeq = &dev->queues[0];
4d115420 1519
a5cdb68c
KB		 1520 if (shutdown)
1521 nvme_shutdown_ctrl(&dev->ctrl);
1522 else
b5b05048 1523 nvme_disable_ctrl(&dev->ctrl);
07836e65 1524
bf392a5d 1525 nvme_poll_irqdisable(nvmeq);
b60503ba
MW		 1526}
1527
fa46c6fb
KB		 1528/*
1529 * Called only on a device that has been disabled and after all other threads
9210c075
DZ		 1530 * that can check this device's completion queues have synced, except
1531 * nvme_poll(). This is the last chance for the driver to see a natural
1532 * completion before nvme_cancel_request() terminates all incomplete requests.
fa46c6fb
KB		 1533 */
1534static void nvme_reap_pending_cqes(struct nvme_dev *dev)
1535{
fa46c6fb
KB		 1536 int i;
1537
9210c075
DZ		 1538 for (i = dev->ctrl.queue_count - 1; i > 0; i--) {
1539 spin_lock(&dev->queues[i].cq_poll_lock);
c234a653 1540 nvme_poll_cq(&dev->queues[i], NULL);
9210c075
DZ		 1541 spin_unlock(&dev->queues[i].cq_poll_lock);
1542 }
fa46c6fb
KB		 1543}
1544
8ffaadf7
JD		 1545static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1546 int entry_size)
1547{
1548 int q_depth = dev->q_depth;
5fd4ce1b 1549 unsigned q_size_aligned = roundup(q_depth * entry_size,
6c3c05b0 1550 NVME_CTRL_PAGE_SIZE);
8ffaadf7
JD		 1551
1552 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
c45f5c99 1553 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
4e523547 1554
6c3c05b0 1555 mem_per_q = round_down(mem_per_q, NVME_CTRL_PAGE_SIZE);
c45f5c99 1556 q_depth = div_u64(mem_per_q, entry_size);
8ffaadf7
JD		 1557
1558 /*
1559 * Ensure the reduced q_depth is above some threshold where it
1560 * would be better to map queues in system memory with the
1561 * original depth
1562 */
1563 if (q_depth < 64)
1564 return -ENOMEM;
1565 }
1566
1567 return q_depth;
1568}
1569
1570static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
8a1d09a6 1571 int qid)
8ffaadf7 1572{
0f238ff5
LG		 1573 struct pci_dev *pdev = to_pci_dev(dev->dev);
1574
1575 if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
8a1d09a6 1576 nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq));
bfac8e9f
AM		 1577 if (nvmeq->sq_cmds) {
1578 nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev,
1579 nvmeq->sq_cmds);
1580 if (nvmeq->sq_dma_addr) {
1581 set_bit(NVMEQ_SQ_CMB, &nvmeq->flags);
1582 return 0;
1583 }
1584
8a1d09a6 1585 pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq));
63223078 1586 }
0f238ff5 1587 }
8ffaadf7 1588
8a1d09a6 1589 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq),
63223078 1590 &nvmeq->sq_dma_addr, GFP_KERNEL);
815c6704
KB		 1591 if (!nvmeq->sq_cmds)
1592 return -ENOMEM;
8ffaadf7
JD		 1593 return 0;
1594}
1595
a6ff7262 1596static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
b60503ba 1597{
147b27e4 1598 struct nvme_queue *nvmeq = &dev->queues[qid];
b60503ba 1599
62314e40
KB		 1600 if (dev->ctrl.queue_count > qid)
1601 return 0;
b60503ba 1602
c1e0cc7e 1603 nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES;
8a1d09a6
BH		 1604 nvmeq->q_depth = depth;
1605 nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq),
750afb08 1606 &nvmeq->cq_dma_addr, GFP_KERNEL);
b60503ba
MW		 1607 if (!nvmeq->cqes)
1608 goto free_nvmeq;
b60503ba 1609
8a1d09a6 1610 if (nvme_alloc_sq_cmds(dev, nvmeq, qid))
b60503ba
MW		 1611 goto free_cqdma;
1612
091b6092 1613 nvmeq->dev = dev;
1ab0cd69 1614 spin_lock_init(&nvmeq->sq_lock);
3a7afd8e 1615 spin_lock_init(&nvmeq->cq_poll_lock);
b60503ba 1616 nvmeq->cq_head = 0;
82123460 1617 nvmeq->cq_phase = 1;
b80d5ccc 1618 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
c30341dc 1619 nvmeq->qid = qid;
d858e5f0 1620 dev->ctrl.queue_count++;
36a7e993 1621
147b27e4 1622 return 0;
b60503ba
MW		 1623
1624 free_cqdma:
8a1d09a6
BH		 1625 dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes,
1626 nvmeq->cq_dma_addr);
b60503ba 1627 free_nvmeq:
147b27e4 1628 return -ENOMEM;
b60503ba
MW		 1629}
1630
dca51e78 1631static int queue_request_irq(struct nvme_queue *nvmeq)
3001082c 1632{
0ff199cb
CH		 1633 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1634 int nr = nvmeq->dev->ctrl.instance;
1635
1636 if (use_threaded_interrupts) {
1637 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1638 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1639 } else {
1640 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1641 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1642 }
3001082c
MW		 1643}
1644
22404274 1645static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
b60503ba 1646{
22404274 1647 struct nvme_dev *dev = nvmeq->dev;
b60503ba 1648
22404274 1649 nvmeq->sq_tail = 0;
38210800 1650 nvmeq->last_sq_tail = 0;
22404274
KB		 1651 nvmeq->cq_head = 0;
1652 nvmeq->cq_phase = 1;
b80d5ccc 1653 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
8a1d09a6 1654 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq));
f9f38e33 1655 nvme_dbbuf_init(dev, nvmeq, qid);
42f61420 1656 dev->online_queues++;
3a7afd8e 1657 wmb(); /* ensure the first interrupt sees the initialization */
22404274
KB		 1658}
1659
e4b9852a
CC		 1660/*
1661 * Try getting shutdown_lock while setting up IO queues.
1662 */
1663static int nvme_setup_io_queues_trylock(struct nvme_dev *dev)
1664{
1665 /*
1666 * Give up if the lock is being held by nvme_dev_disable.
1667 */
1668 if (!mutex_trylock(&dev->shutdown_lock))
1669 return -ENODEV;
1670
1671 /*
1672 * Controller is in wrong state, fail early.
1673 */
1674 if (dev->ctrl.state != NVME_CTRL_CONNECTING) {
1675 mutex_unlock(&dev->shutdown_lock);
1676 return -ENODEV;
1677 }
1678
1679 return 0;
1680}
1681
4b04cc6a 1682static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled)
22404274
KB		 1683{
1684 struct nvme_dev *dev = nvmeq->dev;
1685 int result;
7c349dde 1686 u16 vector = 0;
3f85d50b 1687
d1ed6aa1
CH		 1688 clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
1689
22b55601
KB		 1690 /*
1691 * A queue's vector matches the queue identifier unless the controller
1692 * has only one vector available.
1693 */
4b04cc6a
JA		 1694 if (!polled)
1695 vector = dev->num_vecs == 1 ? 0 : qid;
1696 else
7c349dde 1697 set_bit(NVMEQ_POLLED, &nvmeq->flags);
4b04cc6a 1698
a8e3e0bb 1699 result = adapter_alloc_cq(dev, qid, nvmeq, vector);
ded45505
KB		 1700 if (result)
1701 return result;
b60503ba
MW		 1702
1703 result = adapter_alloc_sq(dev, qid, nvmeq);
1704 if (result < 0)
ded45505 1705 return result;
c80b36cd 1706 if (result)
b60503ba
MW		 1707 goto release_cq;
1708
a8e3e0bb 1709 nvmeq->cq_vector = vector;
4b04cc6a 1710
e4b9852a
CC		 1711 result = nvme_setup_io_queues_trylock(dev);
1712 if (result)
1713 return result;
1714 nvme_init_queue(nvmeq, qid);
7c349dde 1715 if (!polled) {
4b04cc6a
JA		 1716 result = queue_request_irq(nvmeq);
1717 if (result < 0)
1718 goto release_sq;
1719 }
b60503ba 1720
4e224106 1721 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
e4b9852a 1722 mutex_unlock(&dev->shutdown_lock);
22404274 1723 return result;
b60503ba 1724
a8e3e0bb 1725release_sq:
f25a2dfc 1726 dev->online_queues--;
e4b9852a 1727 mutex_unlock(&dev->shutdown_lock);
b60503ba 1728 adapter_delete_sq(dev, qid);
a8e3e0bb 1729release_cq:
b60503ba 1730 adapter_delete_cq(dev, qid);
22404274 1731 return result;
b60503ba
MW		 1732}
1733
f363b089 1734static const struct blk_mq_ops nvme_mq_admin_ops = {
d29ec824 1735 .queue_rq = nvme_queue_rq,
77f02a7a 1736 .complete = nvme_pci_complete_rq,
a4aea562 1737 .init_hctx = nvme_admin_init_hctx,
e559398f 1738 .init_request = nvme_pci_init_request,
a4aea562
MB		 1739 .timeout = nvme_timeout,
1740};
1741
f363b089 1742static const struct blk_mq_ops nvme_mq_ops = {
376f7ef8 1743 .queue_rq = nvme_queue_rq,
d62cbcf6 1744 .queue_rqs = nvme_queue_rqs,
376f7ef8
CH		 1745 .complete = nvme_pci_complete_rq,
1746 .commit_rqs = nvme_commit_rqs,
1747 .init_hctx = nvme_init_hctx,
e559398f 1748 .init_request = nvme_pci_init_request,
376f7ef8
CH		 1749 .map_queues = nvme_pci_map_queues,
1750 .timeout = nvme_timeout,
1751 .poll = nvme_poll,
dabcefab
JA		 1752};
1753
ea191d2f
KB		 1754static void nvme_dev_remove_admin(struct nvme_dev *dev)
1755{
1c63dc66 1756 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
69d9a99c
KB		 1757 /*
1758 * If the controller was reset during removal, it's possible
1759 * user requests may be waiting on a stopped queue. Start the
1760 * queue to flush these to completion.
1761 */
6ca1d902 1762 nvme_start_admin_queue(&dev->ctrl);
1c63dc66 1763 blk_cleanup_queue(dev->ctrl.admin_q);
ea191d2f
KB		 1764 blk_mq_free_tag_set(&dev->admin_tagset);
1765 }
1766}
1767
a4aea562
MB		 1768static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1769{
1c63dc66 1770 if (!dev->ctrl.admin_q) {
a4aea562
MB		 1771 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1772 dev->admin_tagset.nr_hw_queues = 1;
e3e9d50c 1773
38dabe21 1774 dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH;
dc96f938 1775 dev->admin_tagset.timeout = NVME_ADMIN_TIMEOUT;
d4ec47f1 1776 dev->admin_tagset.numa_node = dev->ctrl.numa_node;
d43f1ccf 1777 dev->admin_tagset.cmd_size = sizeof(struct nvme_iod);
d3484991 1778 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED;
a4aea562
MB		 1779 dev->admin_tagset.driver_data = dev;
1780
1781 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1782 return -ENOMEM;
34b6c231 1783 dev->ctrl.admin_tagset = &dev->admin_tagset;
a4aea562 1784
1c63dc66
CH		 1785 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1786 if (IS_ERR(dev->ctrl.admin_q)) {
a4aea562 1787 blk_mq_free_tag_set(&dev->admin_tagset);
da427611 1788 dev->ctrl.admin_q = NULL;
a4aea562
MB		 1789 return -ENOMEM;
1790 }
1c63dc66 1791 if (!blk_get_queue(dev->ctrl.admin_q)) {
ea191d2f 1792 nvme_dev_remove_admin(dev);
1c63dc66 1793 dev->ctrl.admin_q = NULL;
ea191d2f
KB		 1794 return -ENODEV;
1795 }
0fb59cbc 1796 } else
6ca1d902 1797 nvme_start_admin_queue(&dev->ctrl);
a4aea562
MB		 1798
1799 return 0;
1800}
1801
97f6ef64
XY		 1802static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1803{
1804 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1805}
1806
1807static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1808{
1809 struct pci_dev *pdev = to_pci_dev(dev->dev);
1810
1811 if (size <= dev->bar_mapped_size)
1812 return 0;
1813 if (size > pci_resource_len(pdev, 0))
1814 return -ENOMEM;
1815 if (dev->bar)
1816 iounmap(dev->bar);
1817 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1818 if (!dev->bar) {
1819 dev->bar_mapped_size = 0;
1820 return -ENOMEM;
1821 }
1822 dev->bar_mapped_size = size;
1823 dev->dbs = dev->bar + NVME_REG_DBS;
1824
1825 return 0;
1826}
1827
01ad0990 1828static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
b60503ba 1829{
ba47e386 1830 int result;
b60503ba
MW		 1831 u32 aqa;
1832 struct nvme_queue *nvmeq;
1833
97f6ef64
XY		 1834 result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1835 if (result < 0)
1836 return result;
1837
8ef2074d 1838 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
20d0dfe6 1839 NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
dfbac8c7 1840
7a67cbea
CH		 1841 if (dev->subsystem &&
1842 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1843 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
dfbac8c7 1844
b5b05048 1845 result = nvme_disable_ctrl(&dev->ctrl);
ba47e386
MW		 1846 if (result < 0)
1847 return result;
b60503ba 1848
a6ff7262 1849 result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
147b27e4
SG		 1850 if (result)
1851 return result;
b60503ba 1852
635333e4
MG		 1853 dev->ctrl.numa_node = dev_to_node(dev->dev);
1854
147b27e4 1855 nvmeq = &dev->queues[0];
b60503ba
MW		 1856 aqa = nvmeq->q_depth - 1;
1857 aqa |= aqa << 16;
1858
7a67cbea
CH		 1859 writel(aqa, dev->bar + NVME_REG_AQA);
1860 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1861 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
b60503ba 1862
c0f2f45b 1863 result = nvme_enable_ctrl(&dev->ctrl);
025c557a 1864 if (result)
d4875622 1865 return result;
a4aea562 1866
2b25d981 1867 nvmeq->cq_vector = 0;
161b8be2 1868 nvme_init_queue(nvmeq, 0);
dca51e78 1869 result = queue_request_irq(nvmeq);
758dd7fd 1870 if (result) {
7c349dde 1871 dev->online_queues--;
d4875622 1872 return result;
758dd7fd 1873 }
025c557a 1874
4e224106 1875 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
b60503ba
MW		 1876 return result;
1877}
1878
749941f2 1879static int nvme_create_io_queues(struct nvme_dev *dev)
42f61420 1880{
4b04cc6a 1881 unsigned i, max, rw_queues;
749941f2 1882 int ret = 0;
42f61420 1883
d858e5f0 1884 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
a6ff7262 1885 if (nvme_alloc_queue(dev, i, dev->q_depth)) {
749941f2 1886 ret = -ENOMEM;
42f61420 1887 break;
749941f2
CH		 1888 }
1889 }
42f61420 1890
d858e5f0 1891 max = min(dev->max_qid, dev->ctrl.queue_count - 1);
e20ba6e1
CH		 1892 if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) {
1893 rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] +
1894 dev->io_queues[HCTX_TYPE_READ];
4b04cc6a
JA		 1895 } else {
1896 rw_queues = max;
1897 }
1898
949928c1 1899 for (i = dev->online_queues; i <= max; i++) {
4b04cc6a
JA		 1900 bool polled = i > rw_queues;
1901
1902 ret = nvme_create_queue(&dev->queues[i], i, polled);
d4875622 1903 if (ret)
42f61420 1904 break;
27e8166c 1905 }
749941f2
CH		 1906
1907 /*
1908 * Ignore failing Create SQ/CQ commands, we can continue with less
8adb8c14
MI		 1909 * than the desired amount of queues, and even a controller without
1910 * I/O queues can still be used to issue admin commands. This might
749941f2
CH		 1911 * be useful to upgrade a buggy firmware for example.
1912 */
1913 return ret >= 0 ? 0 : ret;
b60503ba
MW		 1914}
1915
88de4598 1916static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
8ffaadf7 1917{
88de4598
CH		 1918 u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
1919
1920 return 1ULL << (12 + 4 * szu);
1921}
1922
1923static u32 nvme_cmb_size(struct nvme_dev *dev)
1924{
1925 return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
1926}
1927
f65efd6d 1928static void nvme_map_cmb(struct nvme_dev *dev)
8ffaadf7 1929{
88de4598 1930 u64 size, offset;
8ffaadf7
JD		 1931 resource_size_t bar_size;
1932 struct pci_dev *pdev = to_pci_dev(dev->dev);
8969f1f8 1933 int bar;
8ffaadf7 1934
9fe5c59f
KB		 1935 if (dev->cmb_size)
1936 return;
1937
20d3bb92
KJ		 1938 if (NVME_CAP_CMBS(dev->ctrl.cap))
1939 writel(NVME_CMBMSC_CRE, dev->bar + NVME_REG_CMBMSC);
1940
7a67cbea 1941 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
f65efd6d
CH		 1942 if (!dev->cmbsz)
1943 return;
202021c1 1944 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
8ffaadf7 1945
88de4598
CH		 1946 size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
1947 offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
8969f1f8
CH		 1948 bar = NVME_CMB_BIR(dev->cmbloc);
1949 bar_size = pci_resource_len(pdev, bar);
8ffaadf7
JD		 1950
1951 if (offset > bar_size)
f65efd6d 1952 return;
8ffaadf7 1953
20d3bb92
KJ		 1954 /*
1955 * Tell the controller about the host side address mapping the CMB,
1956 * and enable CMB decoding for the NVMe 1.4+ scheme:
1957 */
1958 if (NVME_CAP_CMBS(dev->ctrl.cap)) {
1959 hi_lo_writeq(NVME_CMBMSC_CRE | NVME_CMBMSC_CMSE |
1960 (pci_bus_address(pdev, bar) + offset),
1961 dev->bar + NVME_REG_CMBMSC);
1962 }
1963
8ffaadf7
JD		 1964 /*
1965 * Controllers may support a CMB size larger than their BAR,
1966 * for example, due to being behind a bridge. Reduce the CMB to
1967 * the reported size of the BAR
1968 */
1969 if (size > bar_size - offset)
1970 size = bar_size - offset;
1971
0f238ff5
LG		 1972 if (pci_p2pdma_add_resource(pdev, bar, size, offset)) {
1973 dev_warn(dev->ctrl.device,
1974 "failed to register the CMB\n");
f65efd6d 1975 return;
0f238ff5
LG		 1976 }
1977
8ffaadf7 1978 dev->cmb_size = size;
0f238ff5
LG		 1979 dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS);
1980
1981 if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) ==
1982 (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS))
1983 pci_p2pmem_publish(pdev, true);
8ffaadf7
JD		 1984}
1985
87ad72a5
CH		 1986static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1987{
6c3c05b0 1988 u32 host_mem_size = dev->host_mem_size >> NVME_CTRL_PAGE_SHIFT;
4033f35d 1989 u64 dma_addr = dev->host_mem_descs_dma;
f66e2804 1990 struct nvme_command c = { };
87ad72a5
CH		 1991 int ret;
1992
87ad72a5
CH		 1993 c.features.opcode = nvme_admin_set_features;
1994 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1995 c.features.dword11 = cpu_to_le32(bits);
6c3c05b0 1996 c.features.dword12 = cpu_to_le32(host_mem_size);
87ad72a5
CH		 1997 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr));
1998 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr));
1999 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs);
2000
2001 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
2002 if (ret) {
2003 dev_warn(dev->ctrl.device,
2004 "failed to set host mem (err %d, flags %#x).\n",
2005 ret, bits);
a5df5e79
KB		 2006 } else
2007 dev->hmb = bits & NVME_HOST_MEM_ENABLE;
2008
87ad72a5
CH		 2009 return ret;
2010}
2011
2012static void nvme_free_host_mem(struct nvme_dev *dev)
2013{
2014 int i;
2015
2016 for (i = 0; i < dev->nr_host_mem_descs; i++) {
2017 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
6c3c05b0 2018 size_t size = le32_to_cpu(desc->size) * NVME_CTRL_PAGE_SIZE;
87ad72a5 2019
cc667f6d
LD		 2020 dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i],
2021 le64_to_cpu(desc->addr),
2022 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
87ad72a5
CH		 2023 }
2024
2025 kfree(dev->host_mem_desc_bufs);
2026 dev->host_mem_desc_bufs = NULL;
4033f35d
CH		 2027 dma_free_coherent(dev->dev,
2028 dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
2029 dev->host_mem_descs, dev->host_mem_descs_dma);
87ad72a5 2030 dev->host_mem_descs = NULL;
7e5dd57e 2031 dev->nr_host_mem_descs = 0;
87ad72a5
CH		 2032}
2033
92dc6895
CH		 2034static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
2035 u32 chunk_size)
9d713c2b 2036{
87ad72a5 2037 struct nvme_host_mem_buf_desc *descs;
92dc6895 2038 u32 max_entries, len;
4033f35d 2039 dma_addr_t descs_dma;
2ee0e4ed 2040 int i = 0;
87ad72a5 2041 void **bufs;
6fbcde66 2042 u64 size, tmp;
87ad72a5 2043
87ad72a5
CH		 2044 tmp = (preferred + chunk_size - 1);
2045 do_div(tmp, chunk_size);
2046 max_entries = tmp;
044a9df1
CH		 2047
2048 if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
2049 max_entries = dev->ctrl.hmmaxd;
2050
750afb08
LC		 2051 descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs),
2052 &descs_dma, GFP_KERNEL);
87ad72a5
CH		 2053 if (!descs)
2054 goto out;
2055
2056 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
2057 if (!bufs)
2058 goto out_free_descs;
2059
244a8fe4 2060 for (size = 0; size < preferred && i < max_entries; size += len) {
87ad72a5
CH		 2061 dma_addr_t dma_addr;
2062
50cdb7c6 2063 len = min_t(u64, chunk_size, preferred - size);
87ad72a5
CH		 2064 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
2065 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
2066 if (!bufs[i])
2067 break;
2068
2069 descs[i].addr = cpu_to_le64(dma_addr);
6c3c05b0 2070 descs[i].size = cpu_to_le32(len / NVME_CTRL_PAGE_SIZE);
87ad72a5
CH		 2071 i++;
2072 }
2073
92dc6895 2074 if (!size)
87ad72a5 2075 goto out_free_bufs;
87ad72a5 2076
87ad72a5
CH		 2077 dev->nr_host_mem_descs = i;
2078 dev->host_mem_size = size;
2079 dev->host_mem_descs = descs;
4033f35d 2080 dev->host_mem_descs_dma = descs_dma;
87ad72a5
CH		 2081 dev->host_mem_desc_bufs = bufs;
2082 return 0;
2083
2084out_free_bufs:
2085 while (--i >= 0) {
6c3c05b0 2086 size_t size = le32_to_cpu(descs[i].size) * NVME_CTRL_PAGE_SIZE;
87ad72a5 2087
cc667f6d
LD		 2088 dma_free_attrs(dev->dev, size, bufs[i],
2089 le64_to_cpu(descs[i].addr),
2090 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
87ad72a5
CH		 2091 }
2092
2093 kfree(bufs);
2094out_free_descs:
4033f35d
CH		 2095 dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
2096 descs_dma);
87ad72a5 2097out:
87ad72a5
CH		 2098 dev->host_mem_descs = NULL;
2099 return -ENOMEM;
2100}
2101
92dc6895
CH		 2102static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
2103{
9dc54a0d
CK		 2104 u64 min_chunk = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
2105 u64 hmminds = max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
2106 u64 chunk_size;
92dc6895
CH		 2107
2108 /* start big and work our way down */
9dc54a0d 2109 for (chunk_size = min_chunk; chunk_size >= hmminds; chunk_size /= 2) {
92dc6895
CH		 2110 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
2111 if (!min || dev->host_mem_size >= min)
2112 return 0;
2113 nvme_free_host_mem(dev);
2114 }
2115 }
2116
2117 return -ENOMEM;
2118}
2119
9620cfba 2120static int nvme_setup_host_mem(struct nvme_dev *dev)
87ad72a5
CH		 2121{
2122 u64 max = (u64)max_host_mem_size_mb * SZ_1M;
2123 u64 preferred = (u64)dev->ctrl.hmpre * 4096;
2124 u64 min = (u64)dev->ctrl.hmmin * 4096;
2125 u32 enable_bits = NVME_HOST_MEM_ENABLE;
6fbcde66 2126 int ret;
87ad72a5
CH		 2127
2128 preferred = min(preferred, max);
2129 if (min > max) {
2130 dev_warn(dev->ctrl.device,
2131 "min host memory (%lld MiB) above limit (%d MiB).\n",
2132 min >> ilog2(SZ_1M), max_host_mem_size_mb);
2133 nvme_free_host_mem(dev);
9620cfba 2134 return 0;
87ad72a5
CH		 2135 }
2136
2137 /*
2138 * If we already have a buffer allocated check if we can reuse it.
2139 */
2140 if (dev->host_mem_descs) {
2141 if (dev->host_mem_size >= min)
2142 enable_bits |= NVME_HOST_MEM_RETURN;
2143 else
2144 nvme_free_host_mem(dev);
2145 }
2146
2147 if (!dev->host_mem_descs) {
92dc6895
CH		 2148 if (nvme_alloc_host_mem(dev, min, preferred)) {
2149 dev_warn(dev->ctrl.device,
2150 "failed to allocate host memory buffer.\n");
9620cfba 2151 return 0; /* controller must work without HMB */
92dc6895
CH		 2152 }
2153
2154 dev_info(dev->ctrl.device,
2155 "allocated %lld MiB host memory buffer.\n",
2156 dev->host_mem_size >> ilog2(SZ_1M));
87ad72a5
CH		 2157 }
2158
9620cfba
CH		 2159 ret = nvme_set_host_mem(dev, enable_bits);
2160 if (ret)
87ad72a5 2161 nvme_free_host_mem(dev);
9620cfba 2162 return ret;
9d713c2b
KB		 2163}
2164
0521905e
KB		 2165static ssize_t cmb_show(struct device *dev, struct device_attribute *attr,
2166 char *buf)
2167{
2168 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2169
2170 return sysfs_emit(buf, "cmbloc : x%08x\ncmbsz : x%08x\n",
2171 ndev->cmbloc, ndev->cmbsz);
2172}
2173static DEVICE_ATTR_RO(cmb);
2174
1751e97a
KB		 2175static ssize_t cmbloc_show(struct device *dev, struct device_attribute *attr,
2176 char *buf)
2177{
2178 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2179
2180 return sysfs_emit(buf, "%u\n", ndev->cmbloc);
2181}
2182static DEVICE_ATTR_RO(cmbloc);
2183
2184static ssize_t cmbsz_show(struct device *dev, struct device_attribute *attr,
2185 char *buf)
2186{
2187 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2188
2189 return sysfs_emit(buf, "%u\n", ndev->cmbsz);
2190}
2191static DEVICE_ATTR_RO(cmbsz);
2192
a5df5e79
KB		 2193static ssize_t hmb_show(struct device *dev, struct device_attribute *attr,
2194 char *buf)
2195{
2196 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2197
2198 return sysfs_emit(buf, "%d\n", ndev->hmb);
2199}
2200
2201static ssize_t hmb_store(struct device *dev, struct device_attribute *attr,
2202 const char *buf, size_t count)
2203{
2204 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2205 bool new;
2206 int ret;
2207
2208 if (strtobool(buf, &new) < 0)
2209 return -EINVAL;
2210
2211 if (new == ndev->hmb)
2212 return count;
2213
2214 if (new) {
2215 ret = nvme_setup_host_mem(ndev);
2216 } else {
2217 ret = nvme_set_host_mem(ndev, 0);
2218 if (!ret)
2219 nvme_free_host_mem(ndev);
2220 }
2221
2222 if (ret < 0)
2223 return ret;
2224
2225 return count;
2226}
2227static DEVICE_ATTR_RW(hmb);
2228
0521905e
KB		 2229static umode_t nvme_pci_attrs_are_visible(struct kobject *kobj,
2230 struct attribute *a, int n)
2231{
2232 struct nvme_ctrl *ctrl =
2233 dev_get_drvdata(container_of(kobj, struct device, kobj));
2234 struct nvme_dev *dev = to_nvme_dev(ctrl);
2235
1751e97a
KB		 2236 if (a == &dev_attr_cmb.attr ||
2237 a == &dev_attr_cmbloc.attr ||
2238 a == &dev_attr_cmbsz.attr) {
2239 if (!dev->cmbsz)
2240 return 0;
2241 }
a5df5e79
KB		 2242 if (a == &dev_attr_hmb.attr && !ctrl->hmpre)
2243 return 0;
2244
0521905e
KB		 2245 return a->mode;
2246}
2247
2248static struct attribute *nvme_pci_attrs[] = {
2249 &dev_attr_cmb.attr,
1751e97a
KB		 2250 &dev_attr_cmbloc.attr,
2251 &dev_attr_cmbsz.attr,
a5df5e79 2252 &dev_attr_hmb.attr,
0521905e
KB		 2253 NULL,
2254};
2255
2256static const struct attribute_group nvme_pci_attr_group = {
2257 .attrs = nvme_pci_attrs,
2258 .is_visible = nvme_pci_attrs_are_visible,
2259};
2260
612b7286
ML		 2261/*
2262 * nirqs is the number of interrupts available for write and read
2263 * queues. The core already reserved an interrupt for the admin queue.
2264 */
2265static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs)
3b6592f7 2266{
612b7286 2267 struct nvme_dev *dev = affd->priv;
2a5bcfdd 2268 unsigned int nr_read_queues, nr_write_queues = dev->nr_write_queues;
3b6592f7
JA		 2269
2270 /*
ee0d96d3 2271 * If there is no interrupt available for queues, ensure that
612b7286
ML		 2272 * the default queue is set to 1. The affinity set size is
2273 * also set to one, but the irq core ignores it for this case.
2274 *
2275 * If only one interrupt is available or 'write_queue' == 0, combine
2276 * write and read queues.
2277 *
2278 * If 'write_queues' > 0, ensure it leaves room for at least one read
2279 * queue.
3b6592f7 2280 */
612b7286
ML		 2281 if (!nrirqs) {
2282 nrirqs = 1;
2283 nr_read_queues = 0;
2a5bcfdd 2284 } else if (nrirqs == 1 || !nr_write_queues) {
612b7286 2285 nr_read_queues = 0;
2a5bcfdd 2286 } else if (nr_write_queues >= nrirqs) {
612b7286 2287 nr_read_queues = 1;
3b6592f7 2288 } else {
2a5bcfdd 2289 nr_read_queues = nrirqs - nr_write_queues;
3b6592f7 2290 }
612b7286
ML		 2291
2292 dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2293 affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2294 dev->io_queues[HCTX_TYPE_READ] = nr_read_queues;
2295 affd->set_size[HCTX_TYPE_READ] = nr_read_queues;
2296 affd->nr_sets = nr_read_queues ? 2 : 1;
3b6592f7
JA		 2297}
2298
6451fe73 2299static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues)
3b6592f7
JA		 2300{
2301 struct pci_dev *pdev = to_pci_dev(dev->dev);
3b6592f7 2302 struct irq_affinity affd = {
9cfef55b 2303 .pre_vectors = 1,
612b7286
ML		 2304 .calc_sets = nvme_calc_irq_sets,
2305 .priv = dev,
3b6592f7 2306 };
21cc2f3f 2307 unsigned int irq_queues, poll_queues;
6451fe73
JA		 2308
2309 /*
21cc2f3f
JX		 2310 * Poll queues don't need interrupts, but we need at least one I/O queue
2311 * left over for non-polled I/O.
6451fe73 2312 */
21cc2f3f
JX		 2313 poll_queues = min(dev->nr_poll_queues, nr_io_queues - 1);
2314 dev->io_queues[HCTX_TYPE_POLL] = poll_queues;
3b6592f7 2315
21cc2f3f
JX		 2316 /*
2317 * Initialize for the single interrupt case, will be updated in
2318 * nvme_calc_irq_sets().
2319 */
612b7286
ML		 2320 dev->io_queues[HCTX_TYPE_DEFAULT] = 1;
2321 dev->io_queues[HCTX_TYPE_READ] = 0;
3b6592f7 2322
66341331 2323 /*
21cc2f3f
JX		 2324 * We need interrupts for the admin queue and each non-polled I/O queue,
2325 * but some Apple controllers require all queues to use the first
2326 * vector.
66341331 2327 */
21cc2f3f
JX		 2328 irq_queues = 1;
2329 if (!(dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR))
2330 irq_queues += (nr_io_queues - poll_queues);
612b7286
ML		 2331 return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues,
2332 PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd);
3b6592f7
JA		 2333}
2334
8fae268b
KB		 2335static void nvme_disable_io_queues(struct nvme_dev *dev)
2336{
2337 if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq))
2338 __nvme_disable_io_queues(dev, nvme_admin_delete_cq);
2339}
2340
2a5bcfdd
WZ		 2341static unsigned int nvme_max_io_queues(struct nvme_dev *dev)
2342{
e3aef095
NS		 2343 /*
2344 * If tags are shared with admin queue (Apple bug), then
2345 * make sure we only use one IO queue.
2346 */
2347 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2348 return 1;
2a5bcfdd
WZ		 2349 return num_possible_cpus() + dev->nr_write_queues + dev->nr_poll_queues;
2350}
2351
8d85fce7 2352static int nvme_setup_io_queues(struct nvme_dev *dev)
b60503ba 2353{
147b27e4 2354 struct nvme_queue *adminq = &dev->queues[0];
e75ec752 2355 struct pci_dev *pdev = to_pci_dev(dev->dev);
2a5bcfdd 2356 unsigned int nr_io_queues;
97f6ef64 2357 unsigned long size;
2a5bcfdd 2358 int result;
b60503ba 2359
2a5bcfdd
WZ		 2360 /*
2361 * Sample the module parameters once at reset time so that we have
2362 * stable values to work with.
2363 */
2364 dev->nr_write_queues = write_queues;
2365 dev->nr_poll_queues = poll_queues;
d38e9f04 2366
e3aef095 2367 nr_io_queues = dev->nr_allocated_queues - 1;
9a0be7ab
CH		 2368 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
2369 if (result < 0)
1b23484b 2370 return result;
9a0be7ab 2371
f5fa90dc 2372 if (nr_io_queues == 0)
a5229050 2373 return 0;
53dc180e 2374
e4b9852a
CC		 2375 /*
2376 * Free IRQ resources as soon as NVMEQ_ENABLED bit transitions
2377 * from set to unset. If there is a window to it is truely freed,
2378 * pci_free_irq_vectors() jumping into this window will crash.
2379 * And take lock to avoid racing with pci_free_irq_vectors() in
2380 * nvme_dev_disable() path.
2381 */
2382 result = nvme_setup_io_queues_trylock(dev);
2383 if (result)
2384 return result;
2385 if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags))
2386 pci_free_irq(pdev, 0, adminq);
b60503ba 2387
0f238ff5 2388 if (dev->cmb_use_sqes) {
8ffaadf7
JD		 2389 result = nvme_cmb_qdepth(dev, nr_io_queues,
2390 sizeof(struct nvme_command));
2391 if (result > 0)
2392 dev->q_depth = result;
2393 else
0f238ff5 2394 dev->cmb_use_sqes = false;
8ffaadf7
JD		 2395 }
2396
97f6ef64
XY		 2397 do {
2398 size = db_bar_size(dev, nr_io_queues);
2399 result = nvme_remap_bar(dev, size);
2400 if (!result)
2401 break;
e4b9852a
CC		 2402 if (!--nr_io_queues) {
2403 result = -ENOMEM;
2404 goto out_unlock;
2405 }
97f6ef64
XY		 2406 } while (1);
2407 adminq->q_db = dev->dbs;
f1938f6e 2408
8fae268b 2409 retry:
9d713c2b 2410 /* Deregister the admin queue's interrupt */
e4b9852a
CC		 2411 if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags))
2412 pci_free_irq(pdev, 0, adminq);
9d713c2b 2413
e32efbfc
JA		 2414 /*
2415 * If we enable msix early due to not intx, disable it again before
2416 * setting up the full range we need.
2417 */
dca51e78 2418 pci_free_irq_vectors(pdev);
3b6592f7
JA		 2419
2420 result = nvme_setup_irqs(dev, nr_io_queues);
e4b9852a
CC		 2421 if (result <= 0) {
2422 result = -EIO;
2423 goto out_unlock;
2424 }
3b6592f7 2425
22b55601 2426 dev->num_vecs = result;
4b04cc6a 2427 result = max(result - 1, 1);
e20ba6e1 2428 dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL];
fa08a396 2429
063a8096
MW		 2430 /*
2431 * Should investigate if there's a performance win from allocating
2432 * more queues than interrupt vectors; it might allow the submission
2433 * path to scale better, even if the receive path is limited by the
2434 * number of interrupts.
2435 */
dca51e78 2436 result = queue_request_irq(adminq);
7c349dde 2437 if (result)
e4b9852a 2438 goto out_unlock;
4e224106 2439 set_bit(NVMEQ_ENABLED, &adminq->flags);
e4b9852a 2440 mutex_unlock(&dev->shutdown_lock);
8fae268b
KB		 2441
2442 result = nvme_create_io_queues(dev);
2443 if (result || dev->online_queues < 2)
2444 return result;
2445
2446 if (dev->online_queues - 1 < dev->max_qid) {
2447 nr_io_queues = dev->online_queues - 1;
2448 nvme_disable_io_queues(dev);
e4b9852a
CC		 2449 result = nvme_setup_io_queues_trylock(dev);
2450 if (result)
2451 return result;
8fae268b
KB		 2452 nvme_suspend_io_queues(dev);
2453 goto retry;
2454 }
2455 dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n",
2456 dev->io_queues[HCTX_TYPE_DEFAULT],
2457 dev->io_queues[HCTX_TYPE_READ],
2458 dev->io_queues[HCTX_TYPE_POLL]);
2459 return 0;
e4b9852a
CC		 2460out_unlock:
2461 mutex_unlock(&dev->shutdown_lock);
2462 return result;
b60503ba
MW		 2463}
2464
2a842aca 2465static void nvme_del_queue_end(struct request *req, blk_status_t error)
a5768aa8 2466{
db3cbfff 2467 struct nvme_queue *nvmeq = req->end_io_data;
b5875222 2468
db3cbfff 2469 blk_mq_free_request(req);
d1ed6aa1 2470 complete(&nvmeq->delete_done);
a5768aa8
KB		 2471}
2472
2a842aca 2473static void nvme_del_cq_end(struct request *req, blk_status_t error)
a5768aa8 2474{
db3cbfff 2475 struct nvme_queue *nvmeq = req->end_io_data;
a5768aa8 2476
d1ed6aa1
CH		 2477 if (error)
2478 set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
db3cbfff
KB		 2479
2480 nvme_del_queue_end(req, error);
a5768aa8
KB		 2481}
2482
db3cbfff 2483static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
bda4e0fb 2484{
db3cbfff
KB		 2485 struct request_queue *q = nvmeq->dev->ctrl.admin_q;
2486 struct request *req;
f66e2804 2487 struct nvme_command cmd = { };
bda4e0fb 2488
db3cbfff
KB		 2489 cmd.delete_queue.opcode = opcode;
2490 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
bda4e0fb 2491
e559398f 2492 req = blk_mq_alloc_request(q, nvme_req_op(&cmd), BLK_MQ_REQ_NOWAIT);
db3cbfff
KB		 2493 if (IS_ERR(req))
2494 return PTR_ERR(req);
e559398f 2495 nvme_init_request(req, &cmd);
bda4e0fb 2496
e2e53086
CH		 2497 if (opcode == nvme_admin_delete_cq)
2498 req->end_io = nvme_del_cq_end;
2499 else
2500 req->end_io = nvme_del_queue_end;
db3cbfff
KB		 2501 req->end_io_data = nvmeq;
2502
d1ed6aa1 2503 init_completion(&nvmeq->delete_done);
128126a7 2504 req->rq_flags |= RQF_QUIET;
e2e53086 2505 blk_execute_rq_nowait(req, false);
db3cbfff 2506 return 0;
bda4e0fb
KB		 2507}
2508
8fae268b 2509static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode)
a5768aa8 2510{
5271edd4 2511 int nr_queues = dev->online_queues - 1, sent = 0;
db3cbfff 2512 unsigned long timeout;
a5768aa8 2513
db3cbfff 2514 retry:
dc96f938 2515 timeout = NVME_ADMIN_TIMEOUT;
5271edd4
CH		 2516 while (nr_queues > 0) {
2517 if (nvme_delete_queue(&dev->queues[nr_queues], opcode))
2518 break;
2519 nr_queues--;
2520 sent++;
db3cbfff 2521 }
d1ed6aa1
CH		 2522 while (sent) {
2523 struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent];
2524
2525 timeout = wait_for_completion_io_timeout(&nvmeq->delete_done,
5271edd4
CH		 2526 timeout);
2527 if (timeout == 0)
2528 return false;
d1ed6aa1 2529
d1ed6aa1 2530 sent--;
5271edd4
CH		 2531 if (nr_queues)
2532 goto retry;
2533 }
2534 return true;
a5768aa8
KB		 2535}
2536
5d02a5c1 2537static void nvme_dev_add(struct nvme_dev *dev)
b60503ba 2538{
2b1b7e78
JW		 2539 int ret;
2540
5bae7f73 2541 if (!dev->ctrl.tagset) {
376f7ef8 2542 dev->tagset.ops = &nvme_mq_ops;
ffe7704d 2543 dev->tagset.nr_hw_queues = dev->online_queues - 1;
8fe34be1 2544 dev->tagset.nr_maps = 2; /* default + read */
ed92ad37
CH		 2545 if (dev->io_queues[HCTX_TYPE_POLL])
2546 dev->tagset.nr_maps++;
ffe7704d 2547 dev->tagset.timeout = NVME_IO_TIMEOUT;
d4ec47f1 2548 dev->tagset.numa_node = dev->ctrl.numa_node;
61f3b896
CK		 2549 dev->tagset.queue_depth = min_t(unsigned int, dev->q_depth,
2550 BLK_MQ_MAX_DEPTH) - 1;
d43f1ccf 2551 dev->tagset.cmd_size = sizeof(struct nvme_iod);
ffe7704d
KB		 2552 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2553 dev->tagset.driver_data = dev;
b60503ba 2554
d38e9f04
BH		 2555 /*
2556 * Some Apple controllers requires tags to be unique
2557 * across admin and IO queue, so reserve the first 32
2558 * tags of the IO queue.
2559 */
2560 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2561 dev->tagset.reserved_tags = NVME_AQ_DEPTH;
2562
2b1b7e78
JW		 2563 ret = blk_mq_alloc_tag_set(&dev->tagset);
2564 if (ret) {
2565 dev_warn(dev->ctrl.device,
2566 "IO queues tagset allocation failed %d\n", ret);
5d02a5c1 2567 return;
2b1b7e78 2568 }
5bae7f73 2569 dev->ctrl.tagset = &dev->tagset;
949928c1
KB		 2570 } else {
2571 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2572
2573 /* Free previously allocated queues that are no longer usable */
2574 nvme_free_queues(dev, dev->online_queues);
ffe7704d 2575 }
949928c1 2576
e8fd41bb 2577 nvme_dbbuf_set(dev);
b60503ba
MW		 2578}
2579
b00a726a 2580static int nvme_pci_enable(struct nvme_dev *dev)
0877cb0d 2581{
b00a726a 2582 int result = -ENOMEM;
e75ec752 2583 struct pci_dev *pdev = to_pci_dev(dev->dev);
4bdf2603 2584 int dma_address_bits = 64;
0877cb0d
KB		 2585
2586 if (pci_enable_device_mem(pdev))
2587 return result;
2588
0877cb0d 2589 pci_set_master(pdev);
0877cb0d 2590
4bdf2603
FS		 2591 if (dev->ctrl.quirks & NVME_QUIRK_DMA_ADDRESS_BITS_48)
2592 dma_address_bits = 48;
2593 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(dma_address_bits)))
052d0efa 2594 goto disable;
0877cb0d 2595
7a67cbea 2596 if (readl(dev->bar + NVME_REG_CSTS) == -1) {
0e53d180 2597 result = -ENODEV;
b00a726a 2598 goto disable;
0e53d180 2599 }
e32efbfc
JA		 2600
2601 /*
a5229050
KB		 2602 * Some devices and/or platforms don't advertise or work with INTx
2603 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2604 * adjust this later.
e32efbfc 2605 */
dca51e78
CH		 2606 result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
2607 if (result < 0)
2608 return result;
e32efbfc 2609
20d0dfe6 2610 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
7a67cbea 2611
7442ddce 2612 dev->q_depth = min_t(u32, NVME_CAP_MQES(dev->ctrl.cap) + 1,
b27c1e68 2613 io_queue_depth);
aa22c8e6 2614 dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */
20d0dfe6 2615 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
7a67cbea 2616 dev->dbs = dev->bar + 4096;
1f390c1f 2617
66341331
BH		 2618 /*
2619 * Some Apple controllers require a non-standard SQE size.
2620 * Interestingly they also seem to ignore the CC:IOSQES register
2621 * so we don't bother updating it here.
2622 */
2623 if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES)
2624 dev->io_sqes = 7;
2625 else
2626 dev->io_sqes = NVME_NVM_IOSQES;
1f390c1f
SG		 2627
2628 /*
2629 * Temporary fix for the Apple controller found in the MacBook8,1 and
2630 * some MacBook7,1 to avoid controller resets and data loss.
2631 */
2632 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
2633 dev->q_depth = 2;
9bdcfb10
CH		 2634 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
2635 "set queue depth=%u to work around controller resets\n",
1f390c1f 2636 dev->q_depth);
d554b5e1
MP		 2637 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2638 (pdev->device == 0xa821 || pdev->device == 0xa822) &&
20d0dfe6 2639 NVME_CAP_MQES(dev->ctrl.cap) == 0) {
d554b5e1
MP		 2640 dev->q_depth = 64;
2641 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2642 "set queue depth=%u\n", dev->q_depth);
1f390c1f
SG		 2643 }
2644
d38e9f04
BH		 2645 /*
2646 * Controllers with the shared tags quirk need the IO queue to be
2647 * big enough so that we get 32 tags for the admin queue
2648 */
2649 if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) &&
2650 (dev->q_depth < (NVME_AQ_DEPTH + 2))) {
2651 dev->q_depth = NVME_AQ_DEPTH + 2;
2652 dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n",
2653 dev->q_depth);
2654 }
2655
2656
f65efd6d 2657 nvme_map_cmb(dev);
202021c1 2658
a0a3408e
KB		 2659 pci_enable_pcie_error_reporting(pdev);
2660 pci_save_state(pdev);
0877cb0d
KB		 2661 return 0;
2662
2663 disable:
0877cb0d
KB		 2664 pci_disable_device(pdev);
2665 return result;
2666}
2667
2668static void nvme_dev_unmap(struct nvme_dev *dev)
b00a726a
KB		 2669{
2670 if (dev->bar)
2671 iounmap(dev->bar);
a1f447b3 2672 pci_release_mem_regions(to_pci_dev(dev->dev));
b00a726a
KB		 2673}
2674
2675static void nvme_pci_disable(struct nvme_dev *dev)
0877cb0d 2676{
e75ec752
CH		 2677 struct pci_dev *pdev = to_pci_dev(dev->dev);
2678
dca51e78 2679 pci_free_irq_vectors(pdev);
0877cb0d 2680
a0a3408e
KB		 2681 if (pci_is_enabled(pdev)) {
2682 pci_disable_pcie_error_reporting(pdev);
e75ec752 2683 pci_disable_device(pdev);
4d115420 2684 }
4d115420
KB		 2685}
2686
a5cdb68c 2687static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
b60503ba 2688{
e43269e6 2689 bool dead = true, freeze = false;
302ad8cc 2690 struct pci_dev *pdev = to_pci_dev(dev->dev);
22404274 2691
77bf25ea 2692 mutex_lock(&dev->shutdown_lock);
b98235d3 2693 if (pci_device_is_present(pdev) && pci_is_enabled(pdev)) {
302ad8cc
KB		 2694 u32 csts = readl(dev->bar + NVME_REG_CSTS);
2695
ebef7368 2696 if (dev->ctrl.state == NVME_CTRL_LIVE ||
e43269e6
KB		 2697 dev->ctrl.state == NVME_CTRL_RESETTING) {
2698 freeze = true;
302ad8cc 2699 nvme_start_freeze(&dev->ctrl);
e43269e6 2700 }
302ad8cc
KB		 2701 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
2702 pdev->error_state != pci_channel_io_normal);
c9d3bf88 2703 }
c21377f8 2704
302ad8cc
KB		 2705 /*
2706 * Give the controller a chance to complete all entered requests if
2707 * doing a safe shutdown.
2708 */
e43269e6
KB		 2709 if (!dead && shutdown && freeze)
2710 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
9a915a5b
JW		 2711
2712 nvme_stop_queues(&dev->ctrl);
87ad72a5 2713
64ee0ac0 2714 if (!dead && dev->ctrl.queue_count > 0) {
8fae268b 2715 nvme_disable_io_queues(dev);
a5cdb68c 2716 nvme_disable_admin_queue(dev, shutdown);
4d115420 2717 }
8fae268b
KB		 2718 nvme_suspend_io_queues(dev);
2719 nvme_suspend_queue(&dev->queues[0]);
b00a726a 2720 nvme_pci_disable(dev);
fa46c6fb 2721 nvme_reap_pending_cqes(dev);
07836e65 2722
e1958e65
ML		 2723 blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
2724 blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
622b8b68
ML		 2725 blk_mq_tagset_wait_completed_request(&dev->tagset);
2726 blk_mq_tagset_wait_completed_request(&dev->admin_tagset);
302ad8cc
KB		 2727
2728 /*
2729 * The driver will not be starting up queues again if shutting down so
2730 * must flush all entered requests to their failed completion to avoid
2731 * deadlocking blk-mq hot-cpu notifier.
2732 */
c8e9e9b7 2733 if (shutdown) {
302ad8cc 2734 nvme_start_queues(&dev->ctrl);
c8e9e9b7 2735 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q))
6ca1d902 2736 nvme_start_admin_queue(&dev->ctrl);
c8e9e9b7 2737 }
77bf25ea 2738 mutex_unlock(&dev->shutdown_lock);
b60503ba
MW		 2739}
2740
c1ac9a4b
KB		 2741static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown)
2742{
2743 if (!nvme_wait_reset(&dev->ctrl))
2744 return -EBUSY;
2745 nvme_dev_disable(dev, shutdown);
2746 return 0;
2747}
2748
091b6092
MW		 2749static int nvme_setup_prp_pools(struct nvme_dev *dev)
2750{
e75ec752 2751 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
c61b82c7
CH		 2752 NVME_CTRL_PAGE_SIZE,
2753 NVME_CTRL_PAGE_SIZE, 0);
091b6092
MW		 2754 if (!dev->prp_page_pool)
2755 return -ENOMEM;
2756
99802a7a 2757 /* Optimisation for I/Os between 4k and 128k */
e75ec752 2758 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
99802a7a
MW		 2759 256, 256, 0);
2760 if (!dev->prp_small_pool) {
2761 dma_pool_destroy(dev->prp_page_pool);
2762 return -ENOMEM;
2763 }
091b6092
MW		 2764 return 0;
2765}
2766
2767static void nvme_release_prp_pools(struct nvme_dev *dev)
2768{
2769 dma_pool_destroy(dev->prp_page_pool);
99802a7a 2770 dma_pool_destroy(dev->prp_small_pool);
091b6092
MW		 2771}
2772
770597ec
KB		 2773static void nvme_free_tagset(struct nvme_dev *dev)
2774{
2775 if (dev->tagset.tags)
2776 blk_mq_free_tag_set(&dev->tagset);
2777 dev->ctrl.tagset = NULL;
2778}
2779
1673f1f0 2780static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
5e82e952 2781{
1673f1f0 2782 struct nvme_dev *dev = to_nvme_dev(ctrl);
9ac27090 2783
f9f38e33 2784 nvme_dbbuf_dma_free(dev);
770597ec 2785 nvme_free_tagset(dev);
1c63dc66
CH		 2786 if (dev->ctrl.admin_q)
2787 blk_put_queue(dev->ctrl.admin_q);
e286bcfc 2788 free_opal_dev(dev->ctrl.opal_dev);
943e942e 2789 mempool_destroy(dev->iod_mempool);
253fd4ac
IR		 2790 put_device(dev->dev);
2791 kfree(dev->queues);
5e82e952
KB		 2792 kfree(dev);
2793}
2794
7c1ce408 2795static void nvme_remove_dead_ctrl(struct nvme_dev *dev)
f58944e2 2796{
c1ac9a4b
KB		 2797 /*
2798 * Set state to deleting now to avoid blocking nvme_wait_reset(), which
2799 * may be holding this pci_dev's device lock.
2800 */
2801 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
d22524a4 2802 nvme_get_ctrl(&dev->ctrl);
69d9a99c 2803 nvme_dev_disable(dev, false);
9f9cafc1 2804 nvme_kill_queues(&dev->ctrl);
03e0f3a6 2805 if (!queue_work(nvme_wq, &dev->remove_work))
f58944e2
KB		 2806 nvme_put_ctrl(&dev->ctrl);
2807}
2808
fd634f41 2809static void nvme_reset_work(struct work_struct *work)
5e82e952 2810{
d86c4d8e
CH		 2811 struct nvme_dev *dev =
2812 container_of(work, struct nvme_dev, ctrl.reset_work);
a98e58e5 2813 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
e71afda4 2814 int result;
5e82e952 2815
7764656b
ZC		 2816 if (dev->ctrl.state != NVME_CTRL_RESETTING) {
2817 dev_warn(dev->ctrl.device, "ctrl state %d is not RESETTING\n",
2818 dev->ctrl.state);
e71afda4 2819 result = -ENODEV;
fd634f41 2820 goto out;
e71afda4 2821 }
5e82e952 2822
fd634f41
CH		 2823 /*
2824 * If we're called to reset a live controller first shut it down before
2825 * moving on.
2826 */
b00a726a 2827 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
a5cdb68c 2828 nvme_dev_disable(dev, false);
d6135c3a 2829 nvme_sync_queues(&dev->ctrl);
5e82e952 2830
5c959d73 2831 mutex_lock(&dev->shutdown_lock);
b00a726a 2832 result = nvme_pci_enable(dev);
f0b50732 2833 if (result)
4726bcf3 2834 goto out_unlock;
f0b50732 2835
01ad0990 2836 result = nvme_pci_configure_admin_queue(dev);
f0b50732 2837 if (result)
4726bcf3 2838 goto out_unlock;
f0b50732 2839
0fb59cbc
KB		 2840 result = nvme_alloc_admin_tags(dev);
2841 if (result)
4726bcf3 2842 goto out_unlock;
b9afca3e 2843
943e942e
JA		 2844 /*
2845 * Limit the max command size to prevent iod->sg allocations going
2846 * over a single page.
2847 */
7637de31
CH		 2848 dev->ctrl.max_hw_sectors = min_t(u32,
2849 NVME_MAX_KB_SZ << 1, dma_max_mapping_size(dev->dev) >> 9);
943e942e 2850 dev->ctrl.max_segments = NVME_MAX_SEGS;
a48bc520
CH		 2851
2852 /*
2853 * Don't limit the IOMMU merged segment size.
2854 */
2855 dma_set_max_seg_size(dev->dev, 0xffffffff);
3d2d861e 2856 dma_set_min_align_mask(dev->dev, NVME_CTRL_PAGE_SIZE - 1);
a48bc520 2857
5c959d73
KB		 2858 mutex_unlock(&dev->shutdown_lock);
2859
2860 /*
2861 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
2862 * initializing procedure here.
2863 */
2864 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
2865 dev_warn(dev->ctrl.device,
2866 "failed to mark controller CONNECTING\n");
cee6c269 2867 result = -EBUSY;
5c959d73
KB		 2868 goto out;
2869 }
943e942e 2870
95093350
MG		 2871 /*
2872 * We do not support an SGL for metadata (yet), so we are limited to a
2873 * single integrity segment for the separate metadata pointer.
2874 */
2875 dev->ctrl.max_integrity_segments = 1;
2876
f21c4769 2877 result = nvme_init_ctrl_finish(&dev->ctrl);
ce4541f4 2878 if (result)
f58944e2 2879 goto out;
ce4541f4 2880
e286bcfc
SB		 2881 if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
2882 if (!dev->ctrl.opal_dev)
2883 dev->ctrl.opal_dev =
2884 init_opal_dev(&dev->ctrl, &nvme_sec_submit);
2885 else if (was_suspend)
2886 opal_unlock_from_suspend(dev->ctrl.opal_dev);
2887 } else {
2888 free_opal_dev(dev->ctrl.opal_dev);
2889 dev->ctrl.opal_dev = NULL;
4f1244c8 2890 }
a98e58e5 2891
f9f38e33
HK		 2892 if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) {
2893 result = nvme_dbbuf_dma_alloc(dev);
2894 if (result)
2895 dev_warn(dev->dev,
2896 "unable to allocate dma for dbbuf\n");
2897 }
2898
9620cfba
CH		 2899 if (dev->ctrl.hmpre) {
2900 result = nvme_setup_host_mem(dev);
2901 if (result < 0)
2902 goto out;
2903 }
87ad72a5 2904
f0b50732 2905 result = nvme_setup_io_queues(dev);
badc34d4 2906 if (result)
f58944e2 2907 goto out;
f0b50732 2908
2659e57b
CH		 2909 /*
2910 * Keep the controller around but remove all namespaces if we don't have
2911 * any working I/O queue.
2912 */
3cf519b5 2913 if (dev->online_queues < 2) {
1b3c47c1 2914 dev_warn(dev->ctrl.device, "IO queues not created\n");
3b24774e 2915 nvme_kill_queues(&dev->ctrl);
5bae7f73 2916 nvme_remove_namespaces(&dev->ctrl);
770597ec 2917 nvme_free_tagset(dev);
3cf519b5 2918 } else {
25646264 2919 nvme_start_queues(&dev->ctrl);
302ad8cc 2920 nvme_wait_freeze(&dev->ctrl);
5d02a5c1 2921 nvme_dev_add(dev);
302ad8cc 2922 nvme_unfreeze(&dev->ctrl);
3cf519b5
CH		 2923 }
2924
2b1b7e78
JW		 2925 /*
2926 * If only admin queue live, keep it to do further investigation or
2927 * recovery.
2928 */
5d02a5c1 2929 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
2b1b7e78 2930 dev_warn(dev->ctrl.device,
5d02a5c1 2931 "failed to mark controller live state\n");
e71afda4 2932 result = -ENODEV;
bb8d261e
CH		 2933 goto out;
2934 }
92911a55 2935
0521905e
KB		 2936 if (!dev->attrs_added && !sysfs_create_group(&dev->ctrl.device->kobj,
2937 &nvme_pci_attr_group))
2938 dev->attrs_added = true;
2939
d09f2b45 2940 nvme_start_ctrl(&dev->ctrl);
3cf519b5 2941 return;
f0b50732 2942
4726bcf3
KB		 2943 out_unlock:
2944 mutex_unlock(&dev->shutdown_lock);
3cf519b5 2945 out:
7c1ce408
CK		 2946 if (result)
2947 dev_warn(dev->ctrl.device,
2948 "Removing after probe failure status: %d\n", result);
2949 nvme_remove_dead_ctrl(dev);
f0b50732
KB		 2950}
2951
5c8809e6 2952static void nvme_remove_dead_ctrl_work(struct work_struct *work)
9a6b9458 2953{
5c8809e6 2954 struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
e75ec752 2955 struct pci_dev *pdev = to_pci_dev(dev->dev);
9a6b9458
KB		 2956
2957 if (pci_get_drvdata(pdev))
921920ab 2958 device_release_driver(&pdev->dev);
1673f1f0 2959 nvme_put_ctrl(&dev->ctrl);
9a6b9458
KB		 2960}
2961
1c63dc66 2962static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
9ca97374 2963{
1c63dc66 2964 *val = readl(to_nvme_dev(ctrl)->bar + off);
90667892 2965 return 0;
9ca97374
TH		 2966}
2967
5fd4ce1b 2968static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
4cc06521 2969{
5fd4ce1b
CH		 2970 writel(val, to_nvme_dev(ctrl)->bar + off);
2971 return 0;
2972}
4cc06521 2973
7fd8930f
CH		 2974static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2975{
3a8ecc93 2976 *val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off);
7fd8930f 2977 return 0;
4cc06521
KB		 2978}
2979
97c12223
KB		 2980static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
2981{
2982 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2983
2db24e4a 2984 return snprintf(buf, size, "%s\n", dev_name(&pdev->dev));
97c12223
KB		 2985}
2986
2f0dad17
KB		 2987
2988static void nvme_pci_print_device_info(struct nvme_ctrl *ctrl)
2989{
2990 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2991 struct nvme_subsystem *subsys = ctrl->subsys;
2992
2993 dev_err(ctrl->device,
2994 "VID:DID %04x:%04x model:%.*s firmware:%.*s\n",
2995 pdev->vendor, pdev->device,
2996 nvme_strlen(subsys->model, sizeof(subsys->model)),
2997 subsys->model, nvme_strlen(subsys->firmware_rev,
2998 sizeof(subsys->firmware_rev)),
2999 subsys->firmware_rev);
3000}
3001
1c63dc66 3002static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
1a353d85 3003 .name = "pcie",
e439bb12 3004 .module = THIS_MODULE,
e0596ab2
LG		 3005 .flags = NVME_F_METADATA_SUPPORTED |
3006 NVME_F_PCI_P2PDMA,
1c63dc66 3007 .reg_read32 = nvme_pci_reg_read32,
5fd4ce1b 3008 .reg_write32 = nvme_pci_reg_write32,
7fd8930f 3009 .reg_read64 = nvme_pci_reg_read64,
1673f1f0 3010 .free_ctrl = nvme_pci_free_ctrl,
f866fc42 3011 .submit_async_event = nvme_pci_submit_async_event,
97c12223 3012 .get_address = nvme_pci_get_address,
2f0dad17 3013 .print_device_info = nvme_pci_print_device_info,
1c63dc66 3014};
4cc06521 3015
b00a726a
KB		 3016static int nvme_dev_map(struct nvme_dev *dev)
3017{
b00a726a
KB		 3018 struct pci_dev *pdev = to_pci_dev(dev->dev);
3019
a1f447b3 3020 if (pci_request_mem_regions(pdev, "nvme"))
b00a726a
KB		 3021 return -ENODEV;
3022
97f6ef64 3023 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
b00a726a
KB		 3024 goto release;
3025
9fa196e7 3026 return 0;
b00a726a 3027 release:
9fa196e7
MG		 3028 pci_release_mem_regions(pdev);
3029 return -ENODEV;
b00a726a
KB		 3030}
3031
8427bbc2 3032static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
ff5350a8
AL		 3033{
3034 if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
3035 /*
3036 * Several Samsung devices seem to drop off the PCIe bus
3037 * randomly when APST is on and uses the deepest sleep state.
3038 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
3039 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
3040 * 950 PRO 256GB", but it seems to be restricted to two Dell
3041 * laptops.
3042 */
3043 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
3044 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
3045 dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
3046 return NVME_QUIRK_NO_DEEPEST_PS;
8427bbc2
KHF		 3047 } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
3048 /*
3049 * Samsung SSD 960 EVO drops off the PCIe bus after system
467c77d4
JJ		 3050 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
3051 * within few minutes after bootup on a Coffee Lake board -
3052 * ASUS PRIME Z370-A
8427bbc2
KHF		 3053 */
3054 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
467c77d4
JJ		 3055 (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") ||
3056 dmi_match(DMI_BOARD_NAME, "PRIME Z370-A")))
8427bbc2 3057 return NVME_QUIRK_NO_APST;
1fae37ac
S		 3058 } else if ((pdev->vendor == 0x144d && (pdev->device == 0xa801 ||
3059 pdev->device == 0xa808 || pdev->device == 0xa809)) ||
3060 (pdev->vendor == 0x1e0f && pdev->device == 0x0001)) {
3061 /*
3062 * Forcing to use host managed nvme power settings for
3063 * lowest idle power with quick resume latency on
3064 * Samsung and Toshiba SSDs based on suspend behavior
3065 * on Coffee Lake board for LENOVO C640
3066 */
3067 if ((dmi_match(DMI_BOARD_VENDOR, "LENOVO")) &&
3068 dmi_match(DMI_BOARD_NAME, "LNVNB161216"))
3069 return NVME_QUIRK_SIMPLE_SUSPEND;
ff5350a8
AL		 3070 }
3071
3072 return 0;
3073}
3074
18119775
KB		 3075static void nvme_async_probe(void *data, async_cookie_t cookie)
3076{
3077 struct nvme_dev *dev = data;
80f513b5 3078
bd46a906 3079 flush_work(&dev->ctrl.reset_work);
18119775 3080 flush_work(&dev->ctrl.scan_work);
80f513b5 3081 nvme_put_ctrl(&dev->ctrl);
18119775
KB		 3082}
3083
8d85fce7 3084static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
b60503ba 3085{
a4aea562 3086 int node, result = -ENOMEM;
b60503ba 3087 struct nvme_dev *dev;
ff5350a8 3088 unsigned long quirks = id->driver_data;
943e942e 3089 size_t alloc_size;
b60503ba 3090
a4aea562
MB		 3091 node = dev_to_node(&pdev->dev);
3092 if (node == NUMA_NO_NODE)
2fa84351 3093 set_dev_node(&pdev->dev, first_memory_node);
a4aea562
MB		 3094
3095 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
b60503ba
MW		 3096 if (!dev)
3097 return -ENOMEM;
147b27e4 3098
2a5bcfdd
WZ		 3099 dev->nr_write_queues = write_queues;
3100 dev->nr_poll_queues = poll_queues;
3101 dev->nr_allocated_queues = nvme_max_io_queues(dev) + 1;
3102 dev->queues = kcalloc_node(dev->nr_allocated_queues,
3103 sizeof(struct nvme_queue), GFP_KERNEL, node);
b60503ba
MW		 3104 if (!dev->queues)
3105 goto free;
3106
e75ec752 3107 dev->dev = get_device(&pdev->dev);
9a6b9458 3108 pci_set_drvdata(pdev, dev);
1c63dc66 3109
b00a726a
KB		 3110 result = nvme_dev_map(dev);
3111 if (result)
b00c9b7a 3112 goto put_pci;
b00a726a 3113
d86c4d8e 3114 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
5c8809e6 3115 INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
77bf25ea 3116 mutex_init(&dev->shutdown_lock);
b60503ba 3117
091b6092
MW		 3118 result = nvme_setup_prp_pools(dev);
3119 if (result)
b00c9b7a 3120 goto unmap;
4cc06521 3121
8427bbc2 3122 quirks |= check_vendor_combination_bug(pdev);
ff5350a8 3123
2744d7a0 3124 if (!noacpi && acpi_storage_d3(&pdev->dev)) {
df4f9bc4
DB		 3125 /*
3126 * Some systems use a bios work around to ask for D3 on
3127 * platforms that support kernel managed suspend.
3128 */
3129 dev_info(&pdev->dev,
3130 "platform quirk: setting simple suspend\n");
3131 quirks |= NVME_QUIRK_SIMPLE_SUSPEND;
3132 }
3133
943e942e
JA		 3134 /*
3135 * Double check that our mempool alloc size will cover the biggest
3136 * command we support.
3137 */
b13c6393 3138 alloc_size = nvme_pci_iod_alloc_size();
943e942e
JA		 3139 WARN_ON_ONCE(alloc_size > PAGE_SIZE);
3140
3141 dev->iod_mempool = mempool_create_node(1, mempool_kmalloc,
3142 mempool_kfree,
3143 (void *) alloc_size,
3144 GFP_KERNEL, node);
3145 if (!dev->iod_mempool) {
3146 result = -ENOMEM;
3147 goto release_pools;
3148 }
3149
b6e44b4c
KB		 3150 result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
3151 quirks);
3152 if (result)
3153 goto release_mempool;
3154
1b3c47c1
SG		 3155 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
3156
bd46a906 3157 nvme_reset_ctrl(&dev->ctrl);
18119775 3158 async_schedule(nvme_async_probe, dev);
4caff8fc 3159
b60503ba
MW		 3160 return 0;
3161
b6e44b4c
KB		 3162 release_mempool:
3163 mempool_destroy(dev->iod_mempool);
0877cb0d 3164 release_pools:
091b6092 3165 nvme_release_prp_pools(dev);
b00c9b7a
CJ		 3166 unmap:
3167 nvme_dev_unmap(dev);
a96d4f5c 3168 put_pci:
e75ec752 3169 put_device(dev->dev);
b60503ba
MW		 3170 free:
3171 kfree(dev->queues);
b60503ba
MW		 3172 kfree(dev);
3173 return result;
3174}
3175
775755ed 3176static void nvme_reset_prepare(struct pci_dev *pdev)
f0d54a54 3177{
a6739479 3178 struct nvme_dev *dev = pci_get_drvdata(pdev);
c1ac9a4b
KB		 3179
3180 /*
3181 * We don't need to check the return value from waiting for the reset
3182 * state as pci_dev device lock is held, making it impossible to race
3183 * with ->remove().
3184 */
3185 nvme_disable_prepare_reset(dev, false);
3186 nvme_sync_queues(&dev->ctrl);
775755ed 3187}
f0d54a54 3188
775755ed
CH		 3189static void nvme_reset_done(struct pci_dev *pdev)
3190{
f263fbb8 3191 struct nvme_dev *dev = pci_get_drvdata(pdev);
c1ac9a4b
KB		 3192
3193 if (!nvme_try_sched_reset(&dev->ctrl))
3194 flush_work(&dev->ctrl.reset_work);
f0d54a54
KB		 3195}
3196
09ece142
KB		 3197static void nvme_shutdown(struct pci_dev *pdev)
3198{
3199 struct nvme_dev *dev = pci_get_drvdata(pdev);
4e523547 3200
c1ac9a4b 3201 nvme_disable_prepare_reset(dev, true);
09ece142
KB		 3202}
3203
0521905e
KB		 3204static void nvme_remove_attrs(struct nvme_dev *dev)
3205{
3206 if (dev->attrs_added)
3207 sysfs_remove_group(&dev->ctrl.device->kobj,
3208 &nvme_pci_attr_group);
3209}
3210
f58944e2
KB		 3211/*
3212 * The driver's remove may be called on a device in a partially initialized
3213 * state. This function must not have any dependencies on the device state in
3214 * order to proceed.
3215 */
8d85fce7 3216static void nvme_remove(struct pci_dev *pdev)
b60503ba
MW		 3217{
3218 struct nvme_dev *dev = pci_get_drvdata(pdev);
9a6b9458 3219
bb8d261e 3220 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
9a6b9458 3221 pci_set_drvdata(pdev, NULL);
0ff9d4e1 3222
6db28eda 3223 if (!pci_device_is_present(pdev)) {
0ff9d4e1 3224 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
1d39e692 3225 nvme_dev_disable(dev, true);
6db28eda 3226 }
0ff9d4e1 3227
d86c4d8e 3228 flush_work(&dev->ctrl.reset_work);
d09f2b45
SG		 3229 nvme_stop_ctrl(&dev->ctrl);
3230 nvme_remove_namespaces(&dev->ctrl);
a5cdb68c 3231 nvme_dev_disable(dev, true);
0521905e 3232 nvme_remove_attrs(dev);
87ad72a5 3233 nvme_free_host_mem(dev);
a4aea562 3234 nvme_dev_remove_admin(dev);
a1a5ef99 3235 nvme_free_queues(dev, 0);
9a6b9458 3236 nvme_release_prp_pools(dev);
b00a726a 3237 nvme_dev_unmap(dev);
726612b6 3238 nvme_uninit_ctrl(&dev->ctrl);
b60503ba
MW		 3239}
3240
671a6018 3241#ifdef CONFIG_PM_SLEEP
d916b1be
KB		 3242static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps)
3243{
3244 return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps);
3245}
3246
3247static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps)
3248{
3249 return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL);
3250}
3251
3252static int nvme_resume(struct device *dev)
3253{
3254 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
3255 struct nvme_ctrl *ctrl = &ndev->ctrl;
3256
4eaefe8c 3257 if (ndev->last_ps == U32_MAX ||
d916b1be 3258 nvme_set_power_state(ctrl, ndev->last_ps) != 0)
e5ad96f3
KB		 3259 goto reset;
3260 if (ctrl->hmpre && nvme_setup_host_mem(ndev))
3261 goto reset;
3262
d916b1be 3263 return 0;
e5ad96f3
KB		 3264reset:
3265 return nvme_try_sched_reset(ctrl);
d916b1be
KB		 3266}
3267
cd638946
KB		 3268static int nvme_suspend(struct device *dev)
3269{
3270 struct pci_dev *pdev = to_pci_dev(dev);
3271 struct nvme_dev *ndev = pci_get_drvdata(pdev);
d916b1be
KB		 3272 struct nvme_ctrl *ctrl = &ndev->ctrl;
3273 int ret = -EBUSY;
3274
4eaefe8c
RW		 3275 ndev->last_ps = U32_MAX;
3276
d916b1be
KB		 3277 /*
3278 * The platform does not remove power for a kernel managed suspend so
3279 * use host managed nvme power settings for lowest idle power if
3280 * possible. This should have quicker resume latency than a full device
3281 * shutdown. But if the firmware is involved after the suspend or the
3282 * device does not support any non-default power states, shut down the
3283 * device fully.
4eaefe8c
RW		 3284 *
3285 * If ASPM is not enabled for the device, shut down the device and allow
3286 * the PCI bus layer to put it into D3 in order to take the PCIe link
3287 * down, so as to allow the platform to achieve its minimum low-power
3288 * state (which may not be possible if the link is up).
d916b1be 3289 */
4eaefe8c 3290 if (pm_suspend_via_firmware() || !ctrl->npss ||
cb32de1b 3291 !pcie_aspm_enabled(pdev) ||
c1ac9a4b
KB		 3292 (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND))
3293 return nvme_disable_prepare_reset(ndev, true);
d916b1be
KB		 3294
3295 nvme_start_freeze(ctrl);
3296 nvme_wait_freeze(ctrl);
3297 nvme_sync_queues(ctrl);
3298
5d02a5c1 3299 if (ctrl->state != NVME_CTRL_LIVE)
d916b1be
KB		 3300 goto unfreeze;
3301
e5ad96f3
KB		 3302 /*
3303 * Host memory access may not be successful in a system suspend state,
3304 * but the specification allows the controller to access memory in a
3305 * non-operational power state.
3306 */
3307 if (ndev->hmb) {
3308 ret = nvme_set_host_mem(ndev, 0);
3309 if (ret < 0)
3310 goto unfreeze;
3311 }
3312
d916b1be
KB		 3313 ret = nvme_get_power_state(ctrl, &ndev->last_ps);
3314 if (ret < 0)
3315 goto unfreeze;
3316
7cbb5c6f
ML		 3317 /*
3318 * A saved state prevents pci pm from generically controlling the
3319 * device's power. If we're using protocol specific settings, we don't
3320 * want pci interfering.
3321 */
3322 pci_save_state(pdev);
3323
d916b1be
KB		 3324 ret = nvme_set_power_state(ctrl, ctrl->npss);
3325 if (ret < 0)
3326 goto unfreeze;
3327
3328 if (ret) {
7cbb5c6f
ML		 3329 /* discard the saved state */
3330 pci_load_saved_state(pdev, NULL);
3331
d916b1be
KB		 3332 /*
3333 * Clearing npss forces a controller reset on resume. The
05d3046f 3334 * correct value will be rediscovered then.
d916b1be 3335 */
c1ac9a4b 3336 ret = nvme_disable_prepare_reset(ndev, true);
d916b1be 3337 ctrl->npss = 0;
d916b1be 3338 }
d916b1be
KB		 3339unfreeze:
3340 nvme_unfreeze(ctrl);
3341 return ret;
3342}
3343
3344static int nvme_simple_suspend(struct device *dev)
3345{
3346 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
4e523547 3347
c1ac9a4b 3348 return nvme_disable_prepare_reset(ndev, true);
cd638946
KB		 3349}
3350
d916b1be 3351static int nvme_simple_resume(struct device *dev)
cd638946
KB		 3352{
3353 struct pci_dev *pdev = to_pci_dev(dev);
3354 struct nvme_dev *ndev = pci_get_drvdata(pdev);
cd638946 3355
c1ac9a4b 3356 return nvme_try_sched_reset(&ndev->ctrl);
cd638946
KB		 3357}
3358
21774222 3359static const struct dev_pm_ops nvme_dev_pm_ops = {
d916b1be
KB		 3360 .suspend = nvme_suspend,
3361 .resume = nvme_resume,
3362 .freeze = nvme_simple_suspend,
3363 .thaw = nvme_simple_resume,
3364 .poweroff = nvme_simple_suspend,
3365 .restore = nvme_simple_resume,
3366};
3367#endif /* CONFIG_PM_SLEEP */
b60503ba 3368
a0a3408e
KB		 3369static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
3370 pci_channel_state_t state)
3371{
3372 struct nvme_dev *dev = pci_get_drvdata(pdev);
3373
3374 /*
3375 * A frozen channel requires a reset. When detected, this method will
3376 * shutdown the controller to quiesce. The controller will be restarted
3377 * after the slot reset through driver's slot_reset callback.
3378 */
a0a3408e
KB		 3379 switch (state) {
3380 case pci_channel_io_normal:
3381 return PCI_ERS_RESULT_CAN_RECOVER;
3382 case pci_channel_io_frozen:
d011fb31
KB		 3383 dev_warn(dev->ctrl.device,
3384 "frozen state error detected, reset controller\n");
a5cdb68c 3385 nvme_dev_disable(dev, false);
a0a3408e
KB		 3386 return PCI_ERS_RESULT_NEED_RESET;
3387 case pci_channel_io_perm_failure:
d011fb31
KB		 3388 dev_warn(dev->ctrl.device,
3389 "failure state error detected, request disconnect\n");
a0a3408e
KB		 3390 return PCI_ERS_RESULT_DISCONNECT;
3391 }
3392 return PCI_ERS_RESULT_NEED_RESET;
3393}
3394
3395static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
3396{
3397 struct nvme_dev *dev = pci_get_drvdata(pdev);
3398
1b3c47c1 3399 dev_info(dev->ctrl.device, "restart after slot reset\n");
a0a3408e 3400 pci_restore_state(pdev);
d86c4d8e 3401 nvme_reset_ctrl(&dev->ctrl);
a0a3408e
KB		 3402 return PCI_ERS_RESULT_RECOVERED;
3403}
3404
3405static void nvme_error_resume(struct pci_dev *pdev)
3406{
72cd4cc2
KB		 3407 struct nvme_dev *dev = pci_get_drvdata(pdev);
3408
3409 flush_work(&dev->ctrl.reset_work);
a0a3408e
KB		 3410}
3411
1d352035 3412static const struct pci_error_handlers nvme_err_handler = {
b60503ba 3413 .error_detected = nvme_error_detected,
b60503ba
MW		 3414 .slot_reset = nvme_slot_reset,
3415 .resume = nvme_error_resume,
775755ed
CH		 3416 .reset_prepare = nvme_reset_prepare,
3417 .reset_done = nvme_reset_done,
b60503ba
MW		 3418};
3419
6eb0d698 3420static const struct pci_device_id nvme_id_table[] = {
972b13e2 3421 { PCI_VDEVICE(INTEL, 0x0953), /* Intel 750/P3500/P3600/P3700 */
08095e70 3422 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 3423 NVME_QUIRK_DEALLOCATE_ZEROES, },
972b13e2 3424 { PCI_VDEVICE(INTEL, 0x0a53), /* Intel P3520 */
99466e70 3425 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 3426 NVME_QUIRK_DEALLOCATE_ZEROES, },
972b13e2 3427 { PCI_VDEVICE(INTEL, 0x0a54), /* Intel P4500/P4600 */
99466e70 3428 .driver_data = NVME_QUIRK_STRIPE_SIZE |
25e58af4
WZ		 3429 NVME_QUIRK_DEALLOCATE_ZEROES |
3430 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
972b13e2 3431 { PCI_VDEVICE(INTEL, 0x0a55), /* Dell Express Flash P4600 */
f99cb7af
DWF		 3432 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3433 NVME_QUIRK_DEALLOCATE_ZEROES, },
50af47d0 3434 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */
9abd68ef 3435 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
6c6aa2f2 3436 NVME_QUIRK_MEDIUM_PRIO_SQ |
ce4cc313
DM		 3437 NVME_QUIRK_NO_TEMP_THRESH_CHANGE |
3438 NVME_QUIRK_DISABLE_WRITE_ZEROES, },
6299358d
JD		 3439 { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */
3440 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
540c801c 3441 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */
7b210e4e 3442 .driver_data = NVME_QUIRK_IDENTIFY_CNS |
66dd346b
CH		 3443 NVME_QUIRK_DISABLE_WRITE_ZEROES |
3444 NVME_QUIRK_BOGUS_NID, },
3445 { PCI_VDEVICE(REDHAT, 0x0010), /* Qemu emulated controller */
3446 .driver_data = NVME_QUIRK_BOGUS_NID, },
5bedd3af
CH		 3447 { PCI_DEVICE(0x126f, 0x2263), /* Silicon Motion unidentified */
3448 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST, },
0302ae60 3449 { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */
5e112d3f
JE		 3450 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
3451 NVME_QUIRK_NO_NS_DESC_LIST, },
54adc010
GP		 3452 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
3453 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
8c97eecc
JL		 3454 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */
3455 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
015282c9
WW		 3456 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
3457 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
d554b5e1
MP		 3458 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */
3459 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3460 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */
7ee5c78c 3461 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
abbb5f59 3462 NVME_QUIRK_DISABLE_WRITE_ZEROES|
7ee5c78c 3463 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
c9e95c39
CS		 3464 { PCI_DEVICE(0x1987, 0x5016), /* Phison E16 */
3465 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
6e6a6828
PT		 3466 { PCI_DEVICE(0x1b4b, 0x1092), /* Lexar 256 GB SSD */
3467 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST |
3468 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
08b903b5
MN		 3469 { PCI_DEVICE(0x10ec, 0x5762), /* ADATA SX6000LNP */
3470 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
f03e42c6
GC		 3471 { PCI_DEVICE(0x1cc1, 0x8201), /* ADATA SX8200PNP 512GB */
3472 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3473 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
5611ec2b
KHF		 3474 { PCI_DEVICE(0x1c5c, 0x1504), /* SK Hynix PC400 */
3475 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
02ca079c
KHF		 3476 { PCI_DEVICE(0x15b7, 0x2001), /* Sandisk Skyhawk */
3477 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
89919929
CK		 3478 { PCI_DEVICE(0x1d97, 0x2263), /* SPCC */
3479 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
dc22c1c0
ZB		 3480 { PCI_DEVICE(0x2646, 0x2262), /* KINGSTON SKC2000 NVMe SSD */
3481 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
538e4a8c
TL		 3482 { PCI_DEVICE(0x2646, 0x2263), /* KINGSTON A2000 NVMe SSD */
3483 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
70ce3455
CH		 3484 { PCI_DEVICE(0x1e4B, 0x1001), /* MAXIO MAP1001 */
3485 .driver_data = NVME_QUIRK_BOGUS_NID, },
a98a945b
CH		 3486 { PCI_DEVICE(0x1e4B, 0x1002), /* MAXIO MAP1002 */
3487 .driver_data = NVME_QUIRK_BOGUS_NID, },
3488 { PCI_DEVICE(0x1e4B, 0x1202), /* MAXIO MAP1202 */
3489 .driver_data = NVME_QUIRK_BOGUS_NID, },
4bdf2603
FS		 3490 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0061),
3491 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3492 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0065),
3493 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3494 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x8061),
3495 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3496 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd00),
3497 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3498 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd01),
3499 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3500 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd02),
3501 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
98f7b86a
AS		 3502 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001),
3503 .driver_data = NVME_QUIRK_SINGLE_VECTOR },
124298bd 3504 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
66341331
BH		 3505 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005),
3506 .driver_data = NVME_QUIRK_SINGLE_VECTOR |
d38e9f04 3507 NVME_QUIRK_128_BYTES_SQES |
a2941f6a
KB		 3508 NVME_QUIRK_SHARED_TAGS |
3509 NVME_QUIRK_SKIP_CID_GEN },
bc360b0b
MK		 3510 { PCI_DEVICE(0x144d, 0xa808), /* Samsung X5 */
3511 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY|
3512 NVME_QUIRK_NO_DEEPEST_PS |
3513 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
0b85f59d 3514 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
b60503ba
MW		 3515 { 0, }
3516};
3517MODULE_DEVICE_TABLE(pci, nvme_id_table);
3518
3519static struct pci_driver nvme_driver = {
3520 .name = "nvme",
3521 .id_table = nvme_id_table,
3522 .probe = nvme_probe,
8d85fce7 3523 .remove = nvme_remove,
09ece142 3524 .shutdown = nvme_shutdown,
d916b1be 3525#ifdef CONFIG_PM_SLEEP
cd638946
KB		 3526 .driver = {
3527 .pm = &nvme_dev_pm_ops,
3528 },
d916b1be 3529#endif
74d986ab 3530 .sriov_configure = pci_sriov_configure_simple,
b60503ba
MW		 3531 .err_handler = &nvme_err_handler,
3532};
3533
3534static int __init nvme_init(void)
3535{
81101540
CH		 3536 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
3537 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
3538 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
612b7286 3539 BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2);
17c33167 3540
9a6327d2 3541 return pci_register_driver(&nvme_driver);
b60503ba
MW		 3542}
3543
3544static void __exit nvme_exit(void)
3545{
3546 pci_unregister_driver(&nvme_driver);
03e0f3a6 3547 flush_workqueue(nvme_wq);
b60503ba
MW		 3548}
3549
3550MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3551MODULE_LICENSE("GPL");
c78b4713 3552MODULE_VERSION("1.0");
b60503ba
MW		 3553module_init(nvme_init);
3554module_exit(nvme_exit);
Linux 6.x block layer and io_uring tree(s)