Commit | Line | Data |
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b60503ba MW |
1 | /* |
2 | * NVM Express device driver | |
6eb0d698 | 3 | * Copyright (c) 2011-2014, Intel Corporation. |
b60503ba MW |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
b60503ba MW |
13 | */ |
14 | ||
a0a3408e | 15 | #include <linux/aer.h> |
8de05535 | 16 | #include <linux/bitops.h> |
b60503ba | 17 | #include <linux/blkdev.h> |
a4aea562 | 18 | #include <linux/blk-mq.h> |
42f61420 | 19 | #include <linux/cpu.h> |
fd63e9ce | 20 | #include <linux/delay.h> |
b60503ba MW |
21 | #include <linux/errno.h> |
22 | #include <linux/fs.h> | |
23 | #include <linux/genhd.h> | |
4cc09e2d | 24 | #include <linux/hdreg.h> |
5aff9382 | 25 | #include <linux/idr.h> |
b60503ba MW |
26 | #include <linux/init.h> |
27 | #include <linux/interrupt.h> | |
28 | #include <linux/io.h> | |
29 | #include <linux/kdev_t.h> | |
1fa6aead | 30 | #include <linux/kthread.h> |
b60503ba MW |
31 | #include <linux/kernel.h> |
32 | #include <linux/mm.h> | |
33 | #include <linux/module.h> | |
34 | #include <linux/moduleparam.h> | |
77bf25ea | 35 | #include <linux/mutex.h> |
b60503ba | 36 | #include <linux/pci.h> |
be7b6275 | 37 | #include <linux/poison.h> |
c3bfe717 | 38 | #include <linux/ptrace.h> |
b60503ba MW |
39 | #include <linux/sched.h> |
40 | #include <linux/slab.h> | |
e1e5e564 | 41 | #include <linux/t10-pi.h> |
b60503ba | 42 | #include <linux/types.h> |
2f8e2c87 | 43 | #include <linux/io-64-nonatomic-lo-hi.h> |
1d277a63 | 44 | #include <asm/unaligned.h> |
797a796a | 45 | |
f11bb3e2 CH |
46 | #include "nvme.h" |
47 | ||
9d43cf64 | 48 | #define NVME_Q_DEPTH 1024 |
d31af0a3 | 49 | #define NVME_AQ_DEPTH 256 |
b60503ba MW |
50 | #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command)) |
51 | #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion)) | |
adf68f21 CH |
52 | |
53 | /* | |
54 | * We handle AEN commands ourselves and don't even let the | |
55 | * block layer know about them. | |
56 | */ | |
57 | #define NVME_NR_AEN_COMMANDS 1 | |
58 | #define NVME_AQ_BLKMQ_DEPTH (NVME_AQ_DEPTH - NVME_NR_AEN_COMMANDS) | |
9d43cf64 | 59 | |
21d34711 | 60 | unsigned char admin_timeout = 60; |
9d43cf64 KB |
61 | module_param(admin_timeout, byte, 0644); |
62 | MODULE_PARM_DESC(admin_timeout, "timeout in seconds for admin commands"); | |
b60503ba | 63 | |
bd67608a MW |
64 | unsigned char nvme_io_timeout = 30; |
65 | module_param_named(io_timeout, nvme_io_timeout, byte, 0644); | |
b355084a | 66 | MODULE_PARM_DESC(io_timeout, "timeout in seconds for I/O"); |
b60503ba | 67 | |
5fd4ce1b | 68 | unsigned char shutdown_timeout = 5; |
2484f407 DM |
69 | module_param(shutdown_timeout, byte, 0644); |
70 | MODULE_PARM_DESC(shutdown_timeout, "timeout in seconds for controller shutdown"); | |
71 | ||
58ffacb5 MW |
72 | static int use_threaded_interrupts; |
73 | module_param(use_threaded_interrupts, int, 0); | |
74 | ||
8ffaadf7 JD |
75 | static bool use_cmb_sqes = true; |
76 | module_param(use_cmb_sqes, bool, 0644); | |
77 | MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes"); | |
78 | ||
1fa6aead MW |
79 | static LIST_HEAD(dev_list); |
80 | static struct task_struct *nvme_thread; | |
9a6b9458 | 81 | static struct workqueue_struct *nvme_workq; |
b9afca3e | 82 | static wait_queue_head_t nvme_kthread_wait; |
1fa6aead | 83 | |
1c63dc66 CH |
84 | struct nvme_dev; |
85 | struct nvme_queue; | |
86 | ||
4cc06521 | 87 | static int nvme_reset(struct nvme_dev *dev); |
a0fa9647 | 88 | static void nvme_process_cq(struct nvme_queue *nvmeq); |
5c8809e6 | 89 | static void nvme_remove_dead_ctrl(struct nvme_dev *dev); |
e1569a16 | 90 | static void nvme_dev_shutdown(struct nvme_dev *dev); |
d4b4ff8e | 91 | |
4d115420 KB |
92 | struct async_cmd_info { |
93 | struct kthread_work work; | |
94 | struct kthread_worker *worker; | |
4d115420 KB |
95 | int status; |
96 | void *ctx; | |
97 | }; | |
1fa6aead | 98 | |
1c63dc66 CH |
99 | /* |
100 | * Represents an NVM Express device. Each nvme_dev is a PCI function. | |
101 | */ | |
102 | struct nvme_dev { | |
103 | struct list_head node; | |
104 | struct nvme_queue **queues; | |
105 | struct blk_mq_tag_set tagset; | |
106 | struct blk_mq_tag_set admin_tagset; | |
107 | u32 __iomem *dbs; | |
108 | struct device *dev; | |
109 | struct dma_pool *prp_page_pool; | |
110 | struct dma_pool *prp_small_pool; | |
111 | unsigned queue_count; | |
112 | unsigned online_queues; | |
113 | unsigned max_qid; | |
114 | int q_depth; | |
115 | u32 db_stride; | |
1c63dc66 CH |
116 | struct msix_entry *entry; |
117 | void __iomem *bar; | |
1c63dc66 | 118 | struct work_struct reset_work; |
1c63dc66 | 119 | struct work_struct scan_work; |
5c8809e6 | 120 | struct work_struct remove_work; |
77bf25ea | 121 | struct mutex shutdown_lock; |
1c63dc66 | 122 | bool subsystem; |
1c63dc66 CH |
123 | void __iomem *cmb; |
124 | dma_addr_t cmb_dma_addr; | |
125 | u64 cmb_size; | |
126 | u32 cmbsz; | |
fd634f41 CH |
127 | unsigned long flags; |
128 | #define NVME_CTRL_RESETTING 0 | |
1c63dc66 CH |
129 | |
130 | struct nvme_ctrl ctrl; | |
131 | }; | |
132 | ||
133 | static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl) | |
134 | { | |
135 | return container_of(ctrl, struct nvme_dev, ctrl); | |
136 | } | |
137 | ||
b60503ba MW |
138 | /* |
139 | * An NVM Express queue. Each device has at least two (one for admin | |
140 | * commands and one for I/O commands). | |
141 | */ | |
142 | struct nvme_queue { | |
143 | struct device *q_dmadev; | |
091b6092 | 144 | struct nvme_dev *dev; |
3193f07b | 145 | char irqname[24]; /* nvme4294967295-65535\0 */ |
b60503ba MW |
146 | spinlock_t q_lock; |
147 | struct nvme_command *sq_cmds; | |
8ffaadf7 | 148 | struct nvme_command __iomem *sq_cmds_io; |
b60503ba | 149 | volatile struct nvme_completion *cqes; |
42483228 | 150 | struct blk_mq_tags **tags; |
b60503ba MW |
151 | dma_addr_t sq_dma_addr; |
152 | dma_addr_t cq_dma_addr; | |
b60503ba MW |
153 | u32 __iomem *q_db; |
154 | u16 q_depth; | |
6222d172 | 155 | s16 cq_vector; |
b60503ba MW |
156 | u16 sq_head; |
157 | u16 sq_tail; | |
158 | u16 cq_head; | |
c30341dc | 159 | u16 qid; |
e9539f47 MW |
160 | u8 cq_phase; |
161 | u8 cqe_seen; | |
4d115420 | 162 | struct async_cmd_info cmdinfo; |
b60503ba MW |
163 | }; |
164 | ||
71bd150c CH |
165 | /* |
166 | * The nvme_iod describes the data in an I/O, including the list of PRP | |
167 | * entries. You can't see it in this data structure because C doesn't let | |
f4800d6d | 168 | * me express that. Use nvme_init_iod to ensure there's enough space |
71bd150c CH |
169 | * allocated to store the PRP list. |
170 | */ | |
171 | struct nvme_iod { | |
f4800d6d CH |
172 | struct nvme_queue *nvmeq; |
173 | int aborted; | |
71bd150c | 174 | int npages; /* In the PRP list. 0 means small pool in use */ |
71bd150c CH |
175 | int nents; /* Used in scatterlist */ |
176 | int length; /* Of data, in bytes */ | |
177 | dma_addr_t first_dma; | |
bf684057 | 178 | struct scatterlist meta_sg; /* metadata requires single contiguous buffer */ |
f4800d6d CH |
179 | struct scatterlist *sg; |
180 | struct scatterlist inline_sg[0]; | |
71bd150c CH |
181 | }; |
182 | ||
b60503ba MW |
183 | /* |
184 | * Check we didin't inadvertently grow the command struct | |
185 | */ | |
186 | static inline void _nvme_check_size(void) | |
187 | { | |
188 | BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64); | |
189 | BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); | |
190 | BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); | |
191 | BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); | |
192 | BUILD_BUG_ON(sizeof(struct nvme_features) != 64); | |
f8ebf840 | 193 | BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64); |
c30341dc | 194 | BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64); |
b60503ba MW |
195 | BUILD_BUG_ON(sizeof(struct nvme_command) != 64); |
196 | BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096); | |
197 | BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096); | |
198 | BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64); | |
6ecec745 | 199 | BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512); |
b60503ba MW |
200 | } |
201 | ||
ac3dd5bd JA |
202 | /* |
203 | * Max size of iod being embedded in the request payload | |
204 | */ | |
205 | #define NVME_INT_PAGES 2 | |
5fd4ce1b | 206 | #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size) |
ac3dd5bd JA |
207 | |
208 | /* | |
209 | * Will slightly overestimate the number of pages needed. This is OK | |
210 | * as it only leads to a small amount of wasted memory for the lifetime of | |
211 | * the I/O. | |
212 | */ | |
213 | static int nvme_npages(unsigned size, struct nvme_dev *dev) | |
214 | { | |
5fd4ce1b CH |
215 | unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size, |
216 | dev->ctrl.page_size); | |
ac3dd5bd JA |
217 | return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); |
218 | } | |
219 | ||
f4800d6d CH |
220 | static unsigned int nvme_iod_alloc_size(struct nvme_dev *dev, |
221 | unsigned int size, unsigned int nseg) | |
ac3dd5bd | 222 | { |
f4800d6d CH |
223 | return sizeof(__le64 *) * nvme_npages(size, dev) + |
224 | sizeof(struct scatterlist) * nseg; | |
225 | } | |
ac3dd5bd | 226 | |
f4800d6d CH |
227 | static unsigned int nvme_cmd_size(struct nvme_dev *dev) |
228 | { | |
229 | return sizeof(struct nvme_iod) + | |
230 | nvme_iod_alloc_size(dev, NVME_INT_BYTES(dev), NVME_INT_PAGES); | |
ac3dd5bd JA |
231 | } |
232 | ||
a4aea562 MB |
233 | static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, |
234 | unsigned int hctx_idx) | |
e85248e5 | 235 | { |
a4aea562 MB |
236 | struct nvme_dev *dev = data; |
237 | struct nvme_queue *nvmeq = dev->queues[0]; | |
238 | ||
42483228 KB |
239 | WARN_ON(hctx_idx != 0); |
240 | WARN_ON(dev->admin_tagset.tags[0] != hctx->tags); | |
241 | WARN_ON(nvmeq->tags); | |
242 | ||
a4aea562 | 243 | hctx->driver_data = nvmeq; |
42483228 | 244 | nvmeq->tags = &dev->admin_tagset.tags[0]; |
a4aea562 | 245 | return 0; |
e85248e5 MW |
246 | } |
247 | ||
4af0e21c KB |
248 | static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx) |
249 | { | |
250 | struct nvme_queue *nvmeq = hctx->driver_data; | |
251 | ||
252 | nvmeq->tags = NULL; | |
253 | } | |
254 | ||
a4aea562 MB |
255 | static int nvme_admin_init_request(void *data, struct request *req, |
256 | unsigned int hctx_idx, unsigned int rq_idx, | |
257 | unsigned int numa_node) | |
22404274 | 258 | { |
a4aea562 | 259 | struct nvme_dev *dev = data; |
f4800d6d | 260 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
a4aea562 MB |
261 | struct nvme_queue *nvmeq = dev->queues[0]; |
262 | ||
263 | BUG_ON(!nvmeq); | |
f4800d6d | 264 | iod->nvmeq = nvmeq; |
a4aea562 | 265 | return 0; |
22404274 KB |
266 | } |
267 | ||
a4aea562 MB |
268 | static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, |
269 | unsigned int hctx_idx) | |
b60503ba | 270 | { |
a4aea562 | 271 | struct nvme_dev *dev = data; |
42483228 | 272 | struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1]; |
a4aea562 | 273 | |
42483228 KB |
274 | if (!nvmeq->tags) |
275 | nvmeq->tags = &dev->tagset.tags[hctx_idx]; | |
b60503ba | 276 | |
42483228 | 277 | WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags); |
a4aea562 MB |
278 | hctx->driver_data = nvmeq; |
279 | return 0; | |
b60503ba MW |
280 | } |
281 | ||
a4aea562 MB |
282 | static int nvme_init_request(void *data, struct request *req, |
283 | unsigned int hctx_idx, unsigned int rq_idx, | |
284 | unsigned int numa_node) | |
b60503ba | 285 | { |
a4aea562 | 286 | struct nvme_dev *dev = data; |
f4800d6d | 287 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
a4aea562 MB |
288 | struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1]; |
289 | ||
290 | BUG_ON(!nvmeq); | |
f4800d6d | 291 | iod->nvmeq = nvmeq; |
a4aea562 MB |
292 | return 0; |
293 | } | |
294 | ||
adf68f21 CH |
295 | static void nvme_complete_async_event(struct nvme_dev *dev, |
296 | struct nvme_completion *cqe) | |
3c0cf138 | 297 | { |
adf68f21 CH |
298 | u16 status = le16_to_cpu(cqe->status) >> 1; |
299 | u32 result = le32_to_cpu(cqe->result); | |
a4aea562 MB |
300 | |
301 | if (status == NVME_SC_SUCCESS || status == NVME_SC_ABORT_REQ) | |
adf68f21 | 302 | ++dev->ctrl.event_limit; |
a5768aa8 KB |
303 | if (status != NVME_SC_SUCCESS) |
304 | return; | |
305 | ||
306 | switch (result & 0xff07) { | |
307 | case NVME_AER_NOTICE_NS_CHANGED: | |
adf68f21 CH |
308 | dev_info(dev->dev, "rescanning\n"); |
309 | queue_work(nvme_workq, &dev->scan_work); | |
a5768aa8 | 310 | default: |
adf68f21 | 311 | dev_warn(dev->dev, "async event result %08x\n", result); |
a5768aa8 | 312 | } |
b60503ba MW |
313 | } |
314 | ||
b60503ba | 315 | /** |
adf68f21 | 316 | * __nvme_submit_cmd() - Copy a command into a queue and ring the doorbell |
b60503ba MW |
317 | * @nvmeq: The queue to use |
318 | * @cmd: The command to send | |
319 | * | |
320 | * Safe to use from interrupt context | |
321 | */ | |
e3f879bf SB |
322 | static void __nvme_submit_cmd(struct nvme_queue *nvmeq, |
323 | struct nvme_command *cmd) | |
b60503ba | 324 | { |
a4aea562 MB |
325 | u16 tail = nvmeq->sq_tail; |
326 | ||
8ffaadf7 JD |
327 | if (nvmeq->sq_cmds_io) |
328 | memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd)); | |
329 | else | |
330 | memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd)); | |
331 | ||
b60503ba MW |
332 | if (++tail == nvmeq->q_depth) |
333 | tail = 0; | |
7547881d | 334 | writel(tail, nvmeq->q_db); |
b60503ba | 335 | nvmeq->sq_tail = tail; |
b60503ba MW |
336 | } |
337 | ||
f4800d6d | 338 | static __le64 **iod_list(struct request *req) |
b60503ba | 339 | { |
f4800d6d CH |
340 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
341 | return (__le64 **)(iod->sg + req->nr_phys_segments); | |
b60503ba MW |
342 | } |
343 | ||
f4800d6d | 344 | static int nvme_init_iod(struct request *rq, struct nvme_dev *dev) |
ac3dd5bd | 345 | { |
f4800d6d CH |
346 | struct nvme_iod *iod = blk_mq_rq_to_pdu(rq); |
347 | int nseg = rq->nr_phys_segments; | |
348 | unsigned size; | |
ac3dd5bd | 349 | |
f4800d6d CH |
350 | if (rq->cmd_flags & REQ_DISCARD) |
351 | size = sizeof(struct nvme_dsm_range); | |
352 | else | |
353 | size = blk_rq_bytes(rq); | |
ac3dd5bd | 354 | |
f4800d6d CH |
355 | if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) { |
356 | iod->sg = kmalloc(nvme_iod_alloc_size(dev, size, nseg), GFP_ATOMIC); | |
357 | if (!iod->sg) | |
358 | return BLK_MQ_RQ_QUEUE_BUSY; | |
359 | } else { | |
360 | iod->sg = iod->inline_sg; | |
ac3dd5bd JA |
361 | } |
362 | ||
f4800d6d CH |
363 | iod->aborted = 0; |
364 | iod->npages = -1; | |
365 | iod->nents = 0; | |
366 | iod->length = size; | |
367 | return 0; | |
ac3dd5bd JA |
368 | } |
369 | ||
f4800d6d | 370 | static void nvme_free_iod(struct nvme_dev *dev, struct request *req) |
b60503ba | 371 | { |
f4800d6d | 372 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
5fd4ce1b | 373 | const int last_prp = dev->ctrl.page_size / 8 - 1; |
eca18b23 | 374 | int i; |
f4800d6d | 375 | __le64 **list = iod_list(req); |
eca18b23 MW |
376 | dma_addr_t prp_dma = iod->first_dma; |
377 | ||
378 | if (iod->npages == 0) | |
379 | dma_pool_free(dev->prp_small_pool, list[0], prp_dma); | |
380 | for (i = 0; i < iod->npages; i++) { | |
381 | __le64 *prp_list = list[i]; | |
382 | dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]); | |
383 | dma_pool_free(dev->prp_page_pool, prp_list, prp_dma); | |
384 | prp_dma = next_prp_dma; | |
385 | } | |
ac3dd5bd | 386 | |
f4800d6d CH |
387 | if (iod->sg != iod->inline_sg) |
388 | kfree(iod->sg); | |
b60503ba MW |
389 | } |
390 | ||
52b68d7e | 391 | #ifdef CONFIG_BLK_DEV_INTEGRITY |
e1e5e564 KB |
392 | static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi) |
393 | { | |
394 | if (be32_to_cpu(pi->ref_tag) == v) | |
395 | pi->ref_tag = cpu_to_be32(p); | |
396 | } | |
397 | ||
398 | static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi) | |
399 | { | |
400 | if (be32_to_cpu(pi->ref_tag) == p) | |
401 | pi->ref_tag = cpu_to_be32(v); | |
402 | } | |
403 | ||
404 | /** | |
405 | * nvme_dif_remap - remaps ref tags to bip seed and physical lba | |
406 | * | |
407 | * The virtual start sector is the one that was originally submitted by the | |
408 | * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical | |
409 | * start sector may be different. Remap protection information to match the | |
410 | * physical LBA on writes, and back to the original seed on reads. | |
411 | * | |
412 | * Type 0 and 3 do not have a ref tag, so no remapping required. | |
413 | */ | |
414 | static void nvme_dif_remap(struct request *req, | |
415 | void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi)) | |
416 | { | |
417 | struct nvme_ns *ns = req->rq_disk->private_data; | |
418 | struct bio_integrity_payload *bip; | |
419 | struct t10_pi_tuple *pi; | |
420 | void *p, *pmap; | |
421 | u32 i, nlb, ts, phys, virt; | |
422 | ||
423 | if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3) | |
424 | return; | |
425 | ||
426 | bip = bio_integrity(req->bio); | |
427 | if (!bip) | |
428 | return; | |
429 | ||
430 | pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset; | |
e1e5e564 KB |
431 | |
432 | p = pmap; | |
433 | virt = bip_get_seed(bip); | |
434 | phys = nvme_block_nr(ns, blk_rq_pos(req)); | |
435 | nlb = (blk_rq_bytes(req) >> ns->lba_shift); | |
ac6fc48c | 436 | ts = ns->disk->queue->integrity.tuple_size; |
e1e5e564 KB |
437 | |
438 | for (i = 0; i < nlb; i++, virt++, phys++) { | |
439 | pi = (struct t10_pi_tuple *)p; | |
440 | dif_swap(phys, virt, pi); | |
441 | p += ts; | |
442 | } | |
443 | kunmap_atomic(pmap); | |
444 | } | |
52b68d7e KB |
445 | #else /* CONFIG_BLK_DEV_INTEGRITY */ |
446 | static void nvme_dif_remap(struct request *req, | |
447 | void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi)) | |
448 | { | |
449 | } | |
450 | static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi) | |
451 | { | |
452 | } | |
453 | static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi) | |
454 | { | |
455 | } | |
52b68d7e KB |
456 | #endif |
457 | ||
f4800d6d | 458 | static bool nvme_setup_prps(struct nvme_dev *dev, struct request *req, |
69d2b571 | 459 | int total_len) |
ff22b54f | 460 | { |
f4800d6d | 461 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
99802a7a | 462 | struct dma_pool *pool; |
eca18b23 MW |
463 | int length = total_len; |
464 | struct scatterlist *sg = iod->sg; | |
ff22b54f MW |
465 | int dma_len = sg_dma_len(sg); |
466 | u64 dma_addr = sg_dma_address(sg); | |
5fd4ce1b | 467 | u32 page_size = dev->ctrl.page_size; |
f137e0f1 | 468 | int offset = dma_addr & (page_size - 1); |
e025344c | 469 | __le64 *prp_list; |
f4800d6d | 470 | __le64 **list = iod_list(req); |
e025344c | 471 | dma_addr_t prp_dma; |
eca18b23 | 472 | int nprps, i; |
ff22b54f | 473 | |
1d090624 | 474 | length -= (page_size - offset); |
ff22b54f | 475 | if (length <= 0) |
69d2b571 | 476 | return true; |
ff22b54f | 477 | |
1d090624 | 478 | dma_len -= (page_size - offset); |
ff22b54f | 479 | if (dma_len) { |
1d090624 | 480 | dma_addr += (page_size - offset); |
ff22b54f MW |
481 | } else { |
482 | sg = sg_next(sg); | |
483 | dma_addr = sg_dma_address(sg); | |
484 | dma_len = sg_dma_len(sg); | |
485 | } | |
486 | ||
1d090624 | 487 | if (length <= page_size) { |
edd10d33 | 488 | iod->first_dma = dma_addr; |
69d2b571 | 489 | return true; |
e025344c SMM |
490 | } |
491 | ||
1d090624 | 492 | nprps = DIV_ROUND_UP(length, page_size); |
99802a7a MW |
493 | if (nprps <= (256 / 8)) { |
494 | pool = dev->prp_small_pool; | |
eca18b23 | 495 | iod->npages = 0; |
99802a7a MW |
496 | } else { |
497 | pool = dev->prp_page_pool; | |
eca18b23 | 498 | iod->npages = 1; |
99802a7a MW |
499 | } |
500 | ||
69d2b571 | 501 | prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); |
b77954cb | 502 | if (!prp_list) { |
edd10d33 | 503 | iod->first_dma = dma_addr; |
eca18b23 | 504 | iod->npages = -1; |
69d2b571 | 505 | return false; |
b77954cb | 506 | } |
eca18b23 MW |
507 | list[0] = prp_list; |
508 | iod->first_dma = prp_dma; | |
e025344c SMM |
509 | i = 0; |
510 | for (;;) { | |
1d090624 | 511 | if (i == page_size >> 3) { |
e025344c | 512 | __le64 *old_prp_list = prp_list; |
69d2b571 | 513 | prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); |
eca18b23 | 514 | if (!prp_list) |
69d2b571 | 515 | return false; |
eca18b23 | 516 | list[iod->npages++] = prp_list; |
7523d834 MW |
517 | prp_list[0] = old_prp_list[i - 1]; |
518 | old_prp_list[i - 1] = cpu_to_le64(prp_dma); | |
519 | i = 1; | |
e025344c SMM |
520 | } |
521 | prp_list[i++] = cpu_to_le64(dma_addr); | |
1d090624 KB |
522 | dma_len -= page_size; |
523 | dma_addr += page_size; | |
524 | length -= page_size; | |
e025344c SMM |
525 | if (length <= 0) |
526 | break; | |
527 | if (dma_len > 0) | |
528 | continue; | |
529 | BUG_ON(dma_len < 0); | |
530 | sg = sg_next(sg); | |
531 | dma_addr = sg_dma_address(sg); | |
532 | dma_len = sg_dma_len(sg); | |
ff22b54f MW |
533 | } |
534 | ||
69d2b571 | 535 | return true; |
ff22b54f MW |
536 | } |
537 | ||
f4800d6d | 538 | static int nvme_map_data(struct nvme_dev *dev, struct request *req, |
ba1ca37e | 539 | struct nvme_command *cmnd) |
d29ec824 | 540 | { |
f4800d6d | 541 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
ba1ca37e CH |
542 | struct request_queue *q = req->q; |
543 | enum dma_data_direction dma_dir = rq_data_dir(req) ? | |
544 | DMA_TO_DEVICE : DMA_FROM_DEVICE; | |
545 | int ret = BLK_MQ_RQ_QUEUE_ERROR; | |
546 | ||
547 | sg_init_table(iod->sg, req->nr_phys_segments); | |
548 | iod->nents = blk_rq_map_sg(q, req, iod->sg); | |
549 | if (!iod->nents) | |
550 | goto out; | |
551 | ||
552 | ret = BLK_MQ_RQ_QUEUE_BUSY; | |
553 | if (!dma_map_sg(dev->dev, iod->sg, iod->nents, dma_dir)) | |
554 | goto out; | |
555 | ||
f4800d6d | 556 | if (!nvme_setup_prps(dev, req, blk_rq_bytes(req))) |
ba1ca37e CH |
557 | goto out_unmap; |
558 | ||
559 | ret = BLK_MQ_RQ_QUEUE_ERROR; | |
560 | if (blk_integrity_rq(req)) { | |
561 | if (blk_rq_count_integrity_sg(q, req->bio) != 1) | |
562 | goto out_unmap; | |
563 | ||
bf684057 CH |
564 | sg_init_table(&iod->meta_sg, 1); |
565 | if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1) | |
ba1ca37e | 566 | goto out_unmap; |
d29ec824 | 567 | |
ba1ca37e CH |
568 | if (rq_data_dir(req)) |
569 | nvme_dif_remap(req, nvme_dif_prep); | |
570 | ||
bf684057 | 571 | if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir)) |
ba1ca37e | 572 | goto out_unmap; |
d29ec824 CH |
573 | } |
574 | ||
ba1ca37e CH |
575 | cmnd->rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg)); |
576 | cmnd->rw.prp2 = cpu_to_le64(iod->first_dma); | |
577 | if (blk_integrity_rq(req)) | |
bf684057 | 578 | cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg)); |
ba1ca37e CH |
579 | return BLK_MQ_RQ_QUEUE_OK; |
580 | ||
581 | out_unmap: | |
582 | dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); | |
583 | out: | |
584 | return ret; | |
d29ec824 CH |
585 | } |
586 | ||
f4800d6d | 587 | static void nvme_unmap_data(struct nvme_dev *dev, struct request *req) |
d4f6c3ab | 588 | { |
f4800d6d | 589 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
d4f6c3ab CH |
590 | enum dma_data_direction dma_dir = rq_data_dir(req) ? |
591 | DMA_TO_DEVICE : DMA_FROM_DEVICE; | |
592 | ||
593 | if (iod->nents) { | |
594 | dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); | |
595 | if (blk_integrity_rq(req)) { | |
596 | if (!rq_data_dir(req)) | |
597 | nvme_dif_remap(req, nvme_dif_complete); | |
bf684057 | 598 | dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir); |
d4f6c3ab CH |
599 | } |
600 | } | |
601 | ||
f4800d6d | 602 | nvme_free_iod(dev, req); |
d4f6c3ab CH |
603 | } |
604 | ||
a4aea562 MB |
605 | /* |
606 | * We reuse the small pool to allocate the 16-byte range here as it is not | |
607 | * worth having a special pool for these or additional cases to handle freeing | |
608 | * the iod. | |
609 | */ | |
ba1ca37e | 610 | static int nvme_setup_discard(struct nvme_queue *nvmeq, struct nvme_ns *ns, |
f4800d6d | 611 | struct request *req, struct nvme_command *cmnd) |
0e5e4f0e | 612 | { |
f4800d6d | 613 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
ba1ca37e CH |
614 | struct nvme_dsm_range *range; |
615 | ||
616 | range = dma_pool_alloc(nvmeq->dev->prp_small_pool, GFP_ATOMIC, | |
617 | &iod->first_dma); | |
618 | if (!range) | |
619 | return BLK_MQ_RQ_QUEUE_BUSY; | |
f4800d6d | 620 | iod_list(req)[0] = (__le64 *)range; |
ba1ca37e | 621 | iod->npages = 0; |
0e5e4f0e | 622 | |
0e5e4f0e | 623 | range->cattr = cpu_to_le32(0); |
a4aea562 MB |
624 | range->nlb = cpu_to_le32(blk_rq_bytes(req) >> ns->lba_shift); |
625 | range->slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req))); | |
0e5e4f0e | 626 | |
ba1ca37e CH |
627 | memset(cmnd, 0, sizeof(*cmnd)); |
628 | cmnd->dsm.opcode = nvme_cmd_dsm; | |
629 | cmnd->dsm.nsid = cpu_to_le32(ns->ns_id); | |
630 | cmnd->dsm.prp1 = cpu_to_le64(iod->first_dma); | |
631 | cmnd->dsm.nr = 0; | |
632 | cmnd->dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD); | |
633 | return BLK_MQ_RQ_QUEUE_OK; | |
0e5e4f0e KB |
634 | } |
635 | ||
d29ec824 CH |
636 | /* |
637 | * NOTE: ns is NULL when called on the admin queue. | |
638 | */ | |
a4aea562 MB |
639 | static int nvme_queue_rq(struct blk_mq_hw_ctx *hctx, |
640 | const struct blk_mq_queue_data *bd) | |
edd10d33 | 641 | { |
a4aea562 MB |
642 | struct nvme_ns *ns = hctx->queue->queuedata; |
643 | struct nvme_queue *nvmeq = hctx->driver_data; | |
d29ec824 | 644 | struct nvme_dev *dev = nvmeq->dev; |
a4aea562 | 645 | struct request *req = bd->rq; |
ba1ca37e CH |
646 | struct nvme_command cmnd; |
647 | int ret = BLK_MQ_RQ_QUEUE_OK; | |
edd10d33 | 648 | |
e1e5e564 KB |
649 | /* |
650 | * If formated with metadata, require the block layer provide a buffer | |
651 | * unless this namespace is formated such that the metadata can be | |
652 | * stripped/generated by the controller with PRACT=1. | |
653 | */ | |
d29ec824 | 654 | if (ns && ns->ms && !blk_integrity_rq(req)) { |
71feb364 KB |
655 | if (!(ns->pi_type && ns->ms == 8) && |
656 | req->cmd_type != REQ_TYPE_DRV_PRIV) { | |
eee417b0 | 657 | blk_mq_end_request(req, -EFAULT); |
e1e5e564 KB |
658 | return BLK_MQ_RQ_QUEUE_OK; |
659 | } | |
660 | } | |
661 | ||
f4800d6d CH |
662 | ret = nvme_init_iod(req, dev); |
663 | if (ret) | |
664 | return ret; | |
a4aea562 | 665 | |
a4aea562 | 666 | if (req->cmd_flags & REQ_DISCARD) { |
f4800d6d | 667 | ret = nvme_setup_discard(nvmeq, ns, req, &cmnd); |
ba1ca37e CH |
668 | } else { |
669 | if (req->cmd_type == REQ_TYPE_DRV_PRIV) | |
670 | memcpy(&cmnd, req->cmd, sizeof(cmnd)); | |
671 | else if (req->cmd_flags & REQ_FLUSH) | |
672 | nvme_setup_flush(ns, &cmnd); | |
673 | else | |
674 | nvme_setup_rw(ns, req, &cmnd); | |
a4aea562 | 675 | |
ba1ca37e | 676 | if (req->nr_phys_segments) |
f4800d6d | 677 | ret = nvme_map_data(dev, req, &cmnd); |
edd10d33 | 678 | } |
1974b1ae | 679 | |
ba1ca37e CH |
680 | if (ret) |
681 | goto out; | |
682 | ||
683 | cmnd.common.command_id = req->tag; | |
aae239e1 | 684 | blk_mq_start_request(req); |
a4aea562 | 685 | |
ba1ca37e CH |
686 | spin_lock_irq(&nvmeq->q_lock); |
687 | __nvme_submit_cmd(nvmeq, &cmnd); | |
a4aea562 MB |
688 | nvme_process_cq(nvmeq); |
689 | spin_unlock_irq(&nvmeq->q_lock); | |
690 | return BLK_MQ_RQ_QUEUE_OK; | |
ba1ca37e | 691 | out: |
f4800d6d | 692 | nvme_free_iod(dev, req); |
ba1ca37e | 693 | return ret; |
b60503ba MW |
694 | } |
695 | ||
eee417b0 CH |
696 | static void nvme_complete_rq(struct request *req) |
697 | { | |
f4800d6d CH |
698 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
699 | struct nvme_dev *dev = iod->nvmeq->dev; | |
eee417b0 CH |
700 | int error = 0; |
701 | ||
f4800d6d | 702 | nvme_unmap_data(dev, req); |
eee417b0 CH |
703 | |
704 | if (unlikely(req->errors)) { | |
705 | if (nvme_req_needs_retry(req, req->errors)) { | |
706 | nvme_requeue_req(req); | |
707 | return; | |
708 | } | |
709 | ||
710 | if (req->cmd_type == REQ_TYPE_DRV_PRIV) | |
711 | error = req->errors; | |
712 | else | |
713 | error = nvme_error_status(req->errors); | |
714 | } | |
715 | ||
f4800d6d | 716 | if (unlikely(iod->aborted)) { |
eee417b0 CH |
717 | dev_warn(dev->dev, |
718 | "completing aborted command with status: %04x\n", | |
719 | req->errors); | |
720 | } | |
721 | ||
722 | blk_mq_end_request(req, error); | |
723 | } | |
724 | ||
a0fa9647 | 725 | static void __nvme_process_cq(struct nvme_queue *nvmeq, unsigned int *tag) |
b60503ba | 726 | { |
82123460 | 727 | u16 head, phase; |
b60503ba | 728 | |
b60503ba | 729 | head = nvmeq->cq_head; |
82123460 | 730 | phase = nvmeq->cq_phase; |
b60503ba MW |
731 | |
732 | for (;;) { | |
b60503ba | 733 | struct nvme_completion cqe = nvmeq->cqes[head]; |
adf68f21 | 734 | u16 status = le16_to_cpu(cqe.status); |
eee417b0 | 735 | struct request *req; |
adf68f21 CH |
736 | |
737 | if ((status & 1) != phase) | |
b60503ba MW |
738 | break; |
739 | nvmeq->sq_head = le16_to_cpu(cqe.sq_head); | |
740 | if (++head == nvmeq->q_depth) { | |
741 | head = 0; | |
82123460 | 742 | phase = !phase; |
b60503ba | 743 | } |
adf68f21 | 744 | |
a0fa9647 JA |
745 | if (tag && *tag == cqe.command_id) |
746 | *tag = -1; | |
adf68f21 | 747 | |
aae239e1 CH |
748 | if (unlikely(cqe.command_id >= nvmeq->q_depth)) { |
749 | dev_warn(nvmeq->q_dmadev, | |
750 | "invalid id %d completed on queue %d\n", | |
751 | cqe.command_id, le16_to_cpu(cqe.sq_id)); | |
752 | continue; | |
753 | } | |
754 | ||
adf68f21 CH |
755 | /* |
756 | * AEN requests are special as they don't time out and can | |
757 | * survive any kind of queue freeze and often don't respond to | |
758 | * aborts. We don't even bother to allocate a struct request | |
759 | * for them but rather special case them here. | |
760 | */ | |
761 | if (unlikely(nvmeq->qid == 0 && | |
762 | cqe.command_id >= NVME_AQ_BLKMQ_DEPTH)) { | |
763 | nvme_complete_async_event(nvmeq->dev, &cqe); | |
764 | continue; | |
765 | } | |
766 | ||
eee417b0 CH |
767 | req = blk_mq_tag_to_rq(*nvmeq->tags, cqe.command_id); |
768 | if (req->cmd_type == REQ_TYPE_DRV_PRIV) { | |
769 | u32 result = le32_to_cpu(cqe.result); | |
770 | req->special = (void *)(uintptr_t)result; | |
771 | } | |
772 | blk_mq_complete_request(req, status >> 1); | |
773 | ||
b60503ba MW |
774 | } |
775 | ||
776 | /* If the controller ignores the cq head doorbell and continuously | |
777 | * writes to the queue, it is theoretically possible to wrap around | |
778 | * the queue twice and mistakenly return IRQ_NONE. Linux only | |
779 | * requires that 0.1% of your interrupts are handled, so this isn't | |
780 | * a big problem. | |
781 | */ | |
82123460 | 782 | if (head == nvmeq->cq_head && phase == nvmeq->cq_phase) |
a0fa9647 | 783 | return; |
b60503ba | 784 | |
604e8c8d KB |
785 | if (likely(nvmeq->cq_vector >= 0)) |
786 | writel(head, nvmeq->q_db + nvmeq->dev->db_stride); | |
b60503ba | 787 | nvmeq->cq_head = head; |
82123460 | 788 | nvmeq->cq_phase = phase; |
b60503ba | 789 | |
e9539f47 | 790 | nvmeq->cqe_seen = 1; |
a0fa9647 JA |
791 | } |
792 | ||
793 | static void nvme_process_cq(struct nvme_queue *nvmeq) | |
794 | { | |
795 | __nvme_process_cq(nvmeq, NULL); | |
b60503ba MW |
796 | } |
797 | ||
798 | static irqreturn_t nvme_irq(int irq, void *data) | |
58ffacb5 MW |
799 | { |
800 | irqreturn_t result; | |
801 | struct nvme_queue *nvmeq = data; | |
802 | spin_lock(&nvmeq->q_lock); | |
e9539f47 MW |
803 | nvme_process_cq(nvmeq); |
804 | result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE; | |
805 | nvmeq->cqe_seen = 0; | |
58ffacb5 MW |
806 | spin_unlock(&nvmeq->q_lock); |
807 | return result; | |
808 | } | |
809 | ||
810 | static irqreturn_t nvme_irq_check(int irq, void *data) | |
811 | { | |
812 | struct nvme_queue *nvmeq = data; | |
813 | struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head]; | |
814 | if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase) | |
815 | return IRQ_NONE; | |
816 | return IRQ_WAKE_THREAD; | |
817 | } | |
818 | ||
a0fa9647 JA |
819 | static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag) |
820 | { | |
821 | struct nvme_queue *nvmeq = hctx->driver_data; | |
822 | ||
823 | if ((le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) == | |
824 | nvmeq->cq_phase) { | |
825 | spin_lock_irq(&nvmeq->q_lock); | |
826 | __nvme_process_cq(nvmeq, &tag); | |
827 | spin_unlock_irq(&nvmeq->q_lock); | |
828 | ||
829 | if (tag == -1) | |
830 | return 1; | |
831 | } | |
832 | ||
833 | return 0; | |
834 | } | |
835 | ||
adf68f21 | 836 | static void nvme_submit_async_event(struct nvme_dev *dev) |
a4aea562 | 837 | { |
a4aea562 | 838 | struct nvme_command c; |
a4aea562 MB |
839 | |
840 | memset(&c, 0, sizeof(c)); | |
841 | c.common.opcode = nvme_admin_async_event; | |
adf68f21 | 842 | c.common.command_id = NVME_AQ_BLKMQ_DEPTH + --dev->ctrl.event_limit; |
a4aea562 | 843 | |
adf68f21 | 844 | __nvme_submit_cmd(dev->queues[0], &c); |
a4aea562 MB |
845 | } |
846 | ||
d8f32166 | 847 | static void async_cmd_info_endio(struct request *req, int error) |
4d115420 | 848 | { |
d8f32166 | 849 | struct async_cmd_info *cmdinfo = req->end_io_data; |
a4aea562 | 850 | |
d8f32166 CH |
851 | cmdinfo->status = req->errors; |
852 | queue_kthread_work(cmdinfo->worker, &cmdinfo->work); | |
853 | blk_mq_free_request(req); | |
4d115420 KB |
854 | } |
855 | ||
b60503ba MW |
856 | static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) |
857 | { | |
b60503ba MW |
858 | struct nvme_command c; |
859 | ||
860 | memset(&c, 0, sizeof(c)); | |
861 | c.delete_queue.opcode = opcode; | |
862 | c.delete_queue.qid = cpu_to_le16(id); | |
863 | ||
1c63dc66 | 864 | return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); |
b60503ba MW |
865 | } |
866 | ||
867 | static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, | |
868 | struct nvme_queue *nvmeq) | |
869 | { | |
b60503ba MW |
870 | struct nvme_command c; |
871 | int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED; | |
872 | ||
d29ec824 CH |
873 | /* |
874 | * Note: we (ab)use the fact the the prp fields survive if no data | |
875 | * is attached to the request. | |
876 | */ | |
b60503ba MW |
877 | memset(&c, 0, sizeof(c)); |
878 | c.create_cq.opcode = nvme_admin_create_cq; | |
879 | c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); | |
880 | c.create_cq.cqid = cpu_to_le16(qid); | |
881 | c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); | |
882 | c.create_cq.cq_flags = cpu_to_le16(flags); | |
883 | c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector); | |
884 | ||
1c63dc66 | 885 | return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); |
b60503ba MW |
886 | } |
887 | ||
888 | static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, | |
889 | struct nvme_queue *nvmeq) | |
890 | { | |
b60503ba MW |
891 | struct nvme_command c; |
892 | int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM; | |
893 | ||
d29ec824 CH |
894 | /* |
895 | * Note: we (ab)use the fact the the prp fields survive if no data | |
896 | * is attached to the request. | |
897 | */ | |
b60503ba MW |
898 | memset(&c, 0, sizeof(c)); |
899 | c.create_sq.opcode = nvme_admin_create_sq; | |
900 | c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); | |
901 | c.create_sq.sqid = cpu_to_le16(qid); | |
902 | c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); | |
903 | c.create_sq.sq_flags = cpu_to_le16(flags); | |
904 | c.create_sq.cqid = cpu_to_le16(qid); | |
905 | ||
1c63dc66 | 906 | return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); |
b60503ba MW |
907 | } |
908 | ||
909 | static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) | |
910 | { | |
911 | return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); | |
912 | } | |
913 | ||
914 | static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) | |
915 | { | |
916 | return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); | |
917 | } | |
918 | ||
e7a2a87d CH |
919 | static void abort_endio(struct request *req, int error) |
920 | { | |
f4800d6d CH |
921 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
922 | struct nvme_queue *nvmeq = iod->nvmeq; | |
e7a2a87d CH |
923 | u32 result = (u32)(uintptr_t)req->special; |
924 | u16 status = req->errors; | |
925 | ||
926 | dev_warn(nvmeq->q_dmadev, "Abort status:%x result:%x", status, result); | |
927 | atomic_inc(&nvmeq->dev->ctrl.abort_limit); | |
928 | ||
929 | blk_mq_free_request(req); | |
930 | } | |
931 | ||
31c7c7d2 | 932 | static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved) |
c30341dc | 933 | { |
f4800d6d CH |
934 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
935 | struct nvme_queue *nvmeq = iod->nvmeq; | |
c30341dc | 936 | struct nvme_dev *dev = nvmeq->dev; |
a4aea562 | 937 | struct request *abort_req; |
a4aea562 | 938 | struct nvme_command cmd; |
c30341dc | 939 | |
31c7c7d2 | 940 | /* |
fd634f41 CH |
941 | * Shutdown immediately if controller times out while starting. The |
942 | * reset work will see the pci device disabled when it gets the forced | |
943 | * cancellation error. All outstanding requests are completed on | |
944 | * shutdown, so we return BLK_EH_HANDLED. | |
945 | */ | |
946 | if (test_bit(NVME_CTRL_RESETTING, &dev->flags)) { | |
947 | dev_warn(dev->dev, | |
948 | "I/O %d QID %d timeout, disable controller\n", | |
949 | req->tag, nvmeq->qid); | |
950 | nvme_dev_shutdown(dev); | |
951 | req->errors = NVME_SC_CANCELLED; | |
952 | return BLK_EH_HANDLED; | |
953 | } | |
954 | ||
955 | /* | |
956 | * Shutdown the controller immediately and schedule a reset if the | |
957 | * command was already aborted once before and still hasn't been | |
958 | * returned to the driver, or if this is the admin queue. | |
31c7c7d2 | 959 | */ |
f4800d6d | 960 | if (!nvmeq->qid || iod->aborted) { |
e1569a16 KB |
961 | dev_warn(dev->dev, |
962 | "I/O %d QID %d timeout, reset controller\n", | |
963 | req->tag, nvmeq->qid); | |
964 | nvme_dev_shutdown(dev); | |
965 | queue_work(nvme_workq, &dev->reset_work); | |
966 | ||
967 | /* | |
968 | * Mark the request as handled, since the inline shutdown | |
969 | * forces all outstanding requests to complete. | |
970 | */ | |
971 | req->errors = NVME_SC_CANCELLED; | |
972 | return BLK_EH_HANDLED; | |
c30341dc KB |
973 | } |
974 | ||
f4800d6d | 975 | iod->aborted = 1; |
c30341dc | 976 | |
e7a2a87d | 977 | if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) { |
6bf25d16 | 978 | atomic_inc(&dev->ctrl.abort_limit); |
31c7c7d2 | 979 | return BLK_EH_RESET_TIMER; |
6bf25d16 | 980 | } |
c30341dc KB |
981 | |
982 | memset(&cmd, 0, sizeof(cmd)); | |
983 | cmd.abort.opcode = nvme_admin_abort_cmd; | |
a4aea562 | 984 | cmd.abort.cid = req->tag; |
c30341dc | 985 | cmd.abort.sqid = cpu_to_le16(nvmeq->qid); |
c30341dc | 986 | |
31c7c7d2 CH |
987 | dev_warn(nvmeq->q_dmadev, "I/O %d QID %d timeout, aborting\n", |
988 | req->tag, nvmeq->qid); | |
e7a2a87d CH |
989 | |
990 | abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd, | |
991 | BLK_MQ_REQ_NOWAIT); | |
992 | if (IS_ERR(abort_req)) { | |
993 | atomic_inc(&dev->ctrl.abort_limit); | |
994 | return BLK_EH_RESET_TIMER; | |
995 | } | |
996 | ||
997 | abort_req->timeout = ADMIN_TIMEOUT; | |
998 | abort_req->end_io_data = NULL; | |
999 | blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio); | |
31c7c7d2 CH |
1000 | |
1001 | /* | |
1002 | * The aborted req will be completed on receiving the abort req. | |
1003 | * We enable the timer again. If hit twice, it'll cause a device reset, | |
1004 | * as the device then is in a faulty state. | |
1005 | */ | |
1006 | return BLK_EH_RESET_TIMER; | |
c30341dc KB |
1007 | } |
1008 | ||
42483228 | 1009 | static void nvme_cancel_queue_ios(struct request *req, void *data, bool reserved) |
a09115b2 | 1010 | { |
a4aea562 | 1011 | struct nvme_queue *nvmeq = data; |
aae239e1 | 1012 | int status; |
cef6a948 KB |
1013 | |
1014 | if (!blk_mq_request_started(req)) | |
1015 | return; | |
a09115b2 | 1016 | |
aae239e1 CH |
1017 | dev_warn(nvmeq->q_dmadev, |
1018 | "Cancelling I/O %d QID %d\n", req->tag, nvmeq->qid); | |
a4aea562 | 1019 | |
aae239e1 | 1020 | status = NVME_SC_CANCELLED; |
cef6a948 | 1021 | if (blk_queue_dying(req->q)) |
aae239e1 CH |
1022 | status |= NVME_SC_DNR; |
1023 | blk_mq_complete_request(req, status); | |
a09115b2 MW |
1024 | } |
1025 | ||
a4aea562 MB |
1026 | static void nvme_free_queue(struct nvme_queue *nvmeq) |
1027 | { | |
9e866774 MW |
1028 | dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth), |
1029 | (void *)nvmeq->cqes, nvmeq->cq_dma_addr); | |
8ffaadf7 JD |
1030 | if (nvmeq->sq_cmds) |
1031 | dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth), | |
9e866774 MW |
1032 | nvmeq->sq_cmds, nvmeq->sq_dma_addr); |
1033 | kfree(nvmeq); | |
1034 | } | |
1035 | ||
a1a5ef99 | 1036 | static void nvme_free_queues(struct nvme_dev *dev, int lowest) |
22404274 KB |
1037 | { |
1038 | int i; | |
1039 | ||
a1a5ef99 | 1040 | for (i = dev->queue_count - 1; i >= lowest; i--) { |
a4aea562 | 1041 | struct nvme_queue *nvmeq = dev->queues[i]; |
22404274 | 1042 | dev->queue_count--; |
a4aea562 | 1043 | dev->queues[i] = NULL; |
f435c282 | 1044 | nvme_free_queue(nvmeq); |
121c7ad4 | 1045 | } |
22404274 KB |
1046 | } |
1047 | ||
4d115420 KB |
1048 | /** |
1049 | * nvme_suspend_queue - put queue into suspended state | |
1050 | * @nvmeq - queue to suspend | |
4d115420 KB |
1051 | */ |
1052 | static int nvme_suspend_queue(struct nvme_queue *nvmeq) | |
b60503ba | 1053 | { |
2b25d981 | 1054 | int vector; |
b60503ba | 1055 | |
a09115b2 | 1056 | spin_lock_irq(&nvmeq->q_lock); |
2b25d981 KB |
1057 | if (nvmeq->cq_vector == -1) { |
1058 | spin_unlock_irq(&nvmeq->q_lock); | |
1059 | return 1; | |
1060 | } | |
1061 | vector = nvmeq->dev->entry[nvmeq->cq_vector].vector; | |
42f61420 | 1062 | nvmeq->dev->online_queues--; |
2b25d981 | 1063 | nvmeq->cq_vector = -1; |
a09115b2 MW |
1064 | spin_unlock_irq(&nvmeq->q_lock); |
1065 | ||
1c63dc66 CH |
1066 | if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q) |
1067 | blk_mq_freeze_queue_start(nvmeq->dev->ctrl.admin_q); | |
6df3dbc8 | 1068 | |
aba2080f MW |
1069 | irq_set_affinity_hint(vector, NULL); |
1070 | free_irq(vector, nvmeq); | |
b60503ba | 1071 | |
4d115420 KB |
1072 | return 0; |
1073 | } | |
b60503ba | 1074 | |
4d115420 KB |
1075 | static void nvme_clear_queue(struct nvme_queue *nvmeq) |
1076 | { | |
22404274 | 1077 | spin_lock_irq(&nvmeq->q_lock); |
42483228 KB |
1078 | if (nvmeq->tags && *nvmeq->tags) |
1079 | blk_mq_all_tag_busy_iter(*nvmeq->tags, nvme_cancel_queue_ios, nvmeq); | |
22404274 | 1080 | spin_unlock_irq(&nvmeq->q_lock); |
b60503ba MW |
1081 | } |
1082 | ||
4d115420 KB |
1083 | static void nvme_disable_queue(struct nvme_dev *dev, int qid) |
1084 | { | |
a4aea562 | 1085 | struct nvme_queue *nvmeq = dev->queues[qid]; |
4d115420 KB |
1086 | |
1087 | if (!nvmeq) | |
1088 | return; | |
1089 | if (nvme_suspend_queue(nvmeq)) | |
1090 | return; | |
1091 | ||
0e53d180 KB |
1092 | /* Don't tell the adapter to delete the admin queue. |
1093 | * Don't tell a removed adapter to delete IO queues. */ | |
7a67cbea | 1094 | if (qid && readl(dev->bar + NVME_REG_CSTS) != -1) { |
b60503ba MW |
1095 | adapter_delete_sq(dev, qid); |
1096 | adapter_delete_cq(dev, qid); | |
1097 | } | |
07836e65 KB |
1098 | |
1099 | spin_lock_irq(&nvmeq->q_lock); | |
1100 | nvme_process_cq(nvmeq); | |
1101 | spin_unlock_irq(&nvmeq->q_lock); | |
b60503ba MW |
1102 | } |
1103 | ||
8ffaadf7 JD |
1104 | static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues, |
1105 | int entry_size) | |
1106 | { | |
1107 | int q_depth = dev->q_depth; | |
5fd4ce1b CH |
1108 | unsigned q_size_aligned = roundup(q_depth * entry_size, |
1109 | dev->ctrl.page_size); | |
8ffaadf7 JD |
1110 | |
1111 | if (q_size_aligned * nr_io_queues > dev->cmb_size) { | |
c45f5c99 | 1112 | u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues); |
5fd4ce1b | 1113 | mem_per_q = round_down(mem_per_q, dev->ctrl.page_size); |
c45f5c99 | 1114 | q_depth = div_u64(mem_per_q, entry_size); |
8ffaadf7 JD |
1115 | |
1116 | /* | |
1117 | * Ensure the reduced q_depth is above some threshold where it | |
1118 | * would be better to map queues in system memory with the | |
1119 | * original depth | |
1120 | */ | |
1121 | if (q_depth < 64) | |
1122 | return -ENOMEM; | |
1123 | } | |
1124 | ||
1125 | return q_depth; | |
1126 | } | |
1127 | ||
1128 | static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq, | |
1129 | int qid, int depth) | |
1130 | { | |
1131 | if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz)) { | |
5fd4ce1b CH |
1132 | unsigned offset = (qid - 1) * roundup(SQ_SIZE(depth), |
1133 | dev->ctrl.page_size); | |
8ffaadf7 JD |
1134 | nvmeq->sq_dma_addr = dev->cmb_dma_addr + offset; |
1135 | nvmeq->sq_cmds_io = dev->cmb + offset; | |
1136 | } else { | |
1137 | nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth), | |
1138 | &nvmeq->sq_dma_addr, GFP_KERNEL); | |
1139 | if (!nvmeq->sq_cmds) | |
1140 | return -ENOMEM; | |
1141 | } | |
1142 | ||
1143 | return 0; | |
1144 | } | |
1145 | ||
b60503ba | 1146 | static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid, |
2b25d981 | 1147 | int depth) |
b60503ba | 1148 | { |
a4aea562 | 1149 | struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq), GFP_KERNEL); |
b60503ba MW |
1150 | if (!nvmeq) |
1151 | return NULL; | |
1152 | ||
e75ec752 | 1153 | nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth), |
4d51abf9 | 1154 | &nvmeq->cq_dma_addr, GFP_KERNEL); |
b60503ba MW |
1155 | if (!nvmeq->cqes) |
1156 | goto free_nvmeq; | |
b60503ba | 1157 | |
8ffaadf7 | 1158 | if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth)) |
b60503ba MW |
1159 | goto free_cqdma; |
1160 | ||
e75ec752 | 1161 | nvmeq->q_dmadev = dev->dev; |
091b6092 | 1162 | nvmeq->dev = dev; |
3193f07b | 1163 | snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d", |
1c63dc66 | 1164 | dev->ctrl.instance, qid); |
b60503ba MW |
1165 | spin_lock_init(&nvmeq->q_lock); |
1166 | nvmeq->cq_head = 0; | |
82123460 | 1167 | nvmeq->cq_phase = 1; |
b80d5ccc | 1168 | nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; |
b60503ba | 1169 | nvmeq->q_depth = depth; |
c30341dc | 1170 | nvmeq->qid = qid; |
758dd7fd | 1171 | nvmeq->cq_vector = -1; |
a4aea562 | 1172 | dev->queues[qid] = nvmeq; |
b60503ba | 1173 | |
36a7e993 JD |
1174 | /* make sure queue descriptor is set before queue count, for kthread */ |
1175 | mb(); | |
1176 | dev->queue_count++; | |
1177 | ||
b60503ba MW |
1178 | return nvmeq; |
1179 | ||
1180 | free_cqdma: | |
e75ec752 | 1181 | dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes, |
b60503ba MW |
1182 | nvmeq->cq_dma_addr); |
1183 | free_nvmeq: | |
1184 | kfree(nvmeq); | |
1185 | return NULL; | |
1186 | } | |
1187 | ||
3001082c MW |
1188 | static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq, |
1189 | const char *name) | |
1190 | { | |
58ffacb5 MW |
1191 | if (use_threaded_interrupts) |
1192 | return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector, | |
481e5bad | 1193 | nvme_irq_check, nvme_irq, IRQF_SHARED, |
58ffacb5 | 1194 | name, nvmeq); |
3001082c | 1195 | return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq, |
481e5bad | 1196 | IRQF_SHARED, name, nvmeq); |
3001082c MW |
1197 | } |
1198 | ||
22404274 | 1199 | static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) |
b60503ba | 1200 | { |
22404274 | 1201 | struct nvme_dev *dev = nvmeq->dev; |
b60503ba | 1202 | |
7be50e93 | 1203 | spin_lock_irq(&nvmeq->q_lock); |
22404274 KB |
1204 | nvmeq->sq_tail = 0; |
1205 | nvmeq->cq_head = 0; | |
1206 | nvmeq->cq_phase = 1; | |
b80d5ccc | 1207 | nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; |
22404274 | 1208 | memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth)); |
42f61420 | 1209 | dev->online_queues++; |
7be50e93 | 1210 | spin_unlock_irq(&nvmeq->q_lock); |
22404274 KB |
1211 | } |
1212 | ||
1213 | static int nvme_create_queue(struct nvme_queue *nvmeq, int qid) | |
1214 | { | |
1215 | struct nvme_dev *dev = nvmeq->dev; | |
1216 | int result; | |
3f85d50b | 1217 | |
2b25d981 | 1218 | nvmeq->cq_vector = qid - 1; |
b60503ba MW |
1219 | result = adapter_alloc_cq(dev, qid, nvmeq); |
1220 | if (result < 0) | |
22404274 | 1221 | return result; |
b60503ba MW |
1222 | |
1223 | result = adapter_alloc_sq(dev, qid, nvmeq); | |
1224 | if (result < 0) | |
1225 | goto release_cq; | |
1226 | ||
3193f07b | 1227 | result = queue_request_irq(dev, nvmeq, nvmeq->irqname); |
b60503ba MW |
1228 | if (result < 0) |
1229 | goto release_sq; | |
1230 | ||
22404274 | 1231 | nvme_init_queue(nvmeq, qid); |
22404274 | 1232 | return result; |
b60503ba MW |
1233 | |
1234 | release_sq: | |
1235 | adapter_delete_sq(dev, qid); | |
1236 | release_cq: | |
1237 | adapter_delete_cq(dev, qid); | |
22404274 | 1238 | return result; |
b60503ba MW |
1239 | } |
1240 | ||
a4aea562 | 1241 | static struct blk_mq_ops nvme_mq_admin_ops = { |
d29ec824 | 1242 | .queue_rq = nvme_queue_rq, |
eee417b0 | 1243 | .complete = nvme_complete_rq, |
a4aea562 MB |
1244 | .map_queue = blk_mq_map_queue, |
1245 | .init_hctx = nvme_admin_init_hctx, | |
4af0e21c | 1246 | .exit_hctx = nvme_admin_exit_hctx, |
a4aea562 MB |
1247 | .init_request = nvme_admin_init_request, |
1248 | .timeout = nvme_timeout, | |
1249 | }; | |
1250 | ||
1251 | static struct blk_mq_ops nvme_mq_ops = { | |
1252 | .queue_rq = nvme_queue_rq, | |
eee417b0 | 1253 | .complete = nvme_complete_rq, |
a4aea562 MB |
1254 | .map_queue = blk_mq_map_queue, |
1255 | .init_hctx = nvme_init_hctx, | |
1256 | .init_request = nvme_init_request, | |
1257 | .timeout = nvme_timeout, | |
a0fa9647 | 1258 | .poll = nvme_poll, |
a4aea562 MB |
1259 | }; |
1260 | ||
ea191d2f KB |
1261 | static void nvme_dev_remove_admin(struct nvme_dev *dev) |
1262 | { | |
1c63dc66 CH |
1263 | if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) { |
1264 | blk_cleanup_queue(dev->ctrl.admin_q); | |
ea191d2f KB |
1265 | blk_mq_free_tag_set(&dev->admin_tagset); |
1266 | } | |
1267 | } | |
1268 | ||
a4aea562 MB |
1269 | static int nvme_alloc_admin_tags(struct nvme_dev *dev) |
1270 | { | |
1c63dc66 | 1271 | if (!dev->ctrl.admin_q) { |
a4aea562 MB |
1272 | dev->admin_tagset.ops = &nvme_mq_admin_ops; |
1273 | dev->admin_tagset.nr_hw_queues = 1; | |
adf68f21 | 1274 | dev->admin_tagset.queue_depth = NVME_AQ_BLKMQ_DEPTH; |
a4aea562 | 1275 | dev->admin_tagset.timeout = ADMIN_TIMEOUT; |
e75ec752 | 1276 | dev->admin_tagset.numa_node = dev_to_node(dev->dev); |
ac3dd5bd | 1277 | dev->admin_tagset.cmd_size = nvme_cmd_size(dev); |
a4aea562 MB |
1278 | dev->admin_tagset.driver_data = dev; |
1279 | ||
1280 | if (blk_mq_alloc_tag_set(&dev->admin_tagset)) | |
1281 | return -ENOMEM; | |
1282 | ||
1c63dc66 CH |
1283 | dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset); |
1284 | if (IS_ERR(dev->ctrl.admin_q)) { | |
a4aea562 MB |
1285 | blk_mq_free_tag_set(&dev->admin_tagset); |
1286 | return -ENOMEM; | |
1287 | } | |
1c63dc66 | 1288 | if (!blk_get_queue(dev->ctrl.admin_q)) { |
ea191d2f | 1289 | nvme_dev_remove_admin(dev); |
1c63dc66 | 1290 | dev->ctrl.admin_q = NULL; |
ea191d2f KB |
1291 | return -ENODEV; |
1292 | } | |
0fb59cbc | 1293 | } else |
1c63dc66 | 1294 | blk_mq_unfreeze_queue(dev->ctrl.admin_q); |
a4aea562 MB |
1295 | |
1296 | return 0; | |
1297 | } | |
1298 | ||
8d85fce7 | 1299 | static int nvme_configure_admin_queue(struct nvme_dev *dev) |
b60503ba | 1300 | { |
ba47e386 | 1301 | int result; |
b60503ba | 1302 | u32 aqa; |
7a67cbea | 1303 | u64 cap = lo_hi_readq(dev->bar + NVME_REG_CAP); |
b60503ba MW |
1304 | struct nvme_queue *nvmeq; |
1305 | ||
7a67cbea | 1306 | dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1) ? |
dfbac8c7 KB |
1307 | NVME_CAP_NSSRC(cap) : 0; |
1308 | ||
7a67cbea CH |
1309 | if (dev->subsystem && |
1310 | (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO)) | |
1311 | writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS); | |
dfbac8c7 | 1312 | |
5fd4ce1b | 1313 | result = nvme_disable_ctrl(&dev->ctrl, cap); |
ba47e386 MW |
1314 | if (result < 0) |
1315 | return result; | |
b60503ba | 1316 | |
a4aea562 | 1317 | nvmeq = dev->queues[0]; |
cd638946 | 1318 | if (!nvmeq) { |
2b25d981 | 1319 | nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH); |
cd638946 KB |
1320 | if (!nvmeq) |
1321 | return -ENOMEM; | |
cd638946 | 1322 | } |
b60503ba MW |
1323 | |
1324 | aqa = nvmeq->q_depth - 1; | |
1325 | aqa |= aqa << 16; | |
1326 | ||
7a67cbea CH |
1327 | writel(aqa, dev->bar + NVME_REG_AQA); |
1328 | lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ); | |
1329 | lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ); | |
b60503ba | 1330 | |
5fd4ce1b | 1331 | result = nvme_enable_ctrl(&dev->ctrl, cap); |
025c557a | 1332 | if (result) |
a4aea562 MB |
1333 | goto free_nvmeq; |
1334 | ||
2b25d981 | 1335 | nvmeq->cq_vector = 0; |
3193f07b | 1336 | result = queue_request_irq(dev, nvmeq, nvmeq->irqname); |
758dd7fd JD |
1337 | if (result) { |
1338 | nvmeq->cq_vector = -1; | |
0fb59cbc | 1339 | goto free_nvmeq; |
758dd7fd | 1340 | } |
025c557a | 1341 | |
b60503ba | 1342 | return result; |
a4aea562 | 1343 | |
a4aea562 MB |
1344 | free_nvmeq: |
1345 | nvme_free_queues(dev, 0); | |
1346 | return result; | |
b60503ba MW |
1347 | } |
1348 | ||
1fa6aead MW |
1349 | static int nvme_kthread(void *data) |
1350 | { | |
d4b4ff8e | 1351 | struct nvme_dev *dev, *next; |
1fa6aead MW |
1352 | |
1353 | while (!kthread_should_stop()) { | |
564a232c | 1354 | set_current_state(TASK_INTERRUPTIBLE); |
1fa6aead | 1355 | spin_lock(&dev_list_lock); |
d4b4ff8e | 1356 | list_for_each_entry_safe(dev, next, &dev_list, node) { |
1fa6aead | 1357 | int i; |
7a67cbea | 1358 | u32 csts = readl(dev->bar + NVME_REG_CSTS); |
dfbac8c7 | 1359 | |
846cc05f CH |
1360 | /* |
1361 | * Skip controllers currently under reset. | |
1362 | */ | |
1363 | if (work_pending(&dev->reset_work) || work_busy(&dev->reset_work)) | |
1364 | continue; | |
1365 | ||
dfbac8c7 KB |
1366 | if ((dev->subsystem && (csts & NVME_CSTS_NSSRO)) || |
1367 | csts & NVME_CSTS_CFS) { | |
846cc05f | 1368 | if (queue_work(nvme_workq, &dev->reset_work)) { |
90667892 CH |
1369 | dev_warn(dev->dev, |
1370 | "Failed status: %x, reset controller\n", | |
7a67cbea | 1371 | readl(dev->bar + NVME_REG_CSTS)); |
90667892 | 1372 | } |
d4b4ff8e KB |
1373 | continue; |
1374 | } | |
1fa6aead | 1375 | for (i = 0; i < dev->queue_count; i++) { |
a4aea562 | 1376 | struct nvme_queue *nvmeq = dev->queues[i]; |
740216fc MW |
1377 | if (!nvmeq) |
1378 | continue; | |
1fa6aead | 1379 | spin_lock_irq(&nvmeq->q_lock); |
bc57a0f7 | 1380 | nvme_process_cq(nvmeq); |
6fccf938 | 1381 | |
adf68f21 CH |
1382 | while (i == 0 && dev->ctrl.event_limit > 0) |
1383 | nvme_submit_async_event(dev); | |
1fa6aead MW |
1384 | spin_unlock_irq(&nvmeq->q_lock); |
1385 | } | |
1386 | } | |
1387 | spin_unlock(&dev_list_lock); | |
acb7aa0d | 1388 | schedule_timeout(round_jiffies_relative(HZ)); |
1fa6aead MW |
1389 | } |
1390 | return 0; | |
1391 | } | |
1392 | ||
749941f2 | 1393 | static int nvme_create_io_queues(struct nvme_dev *dev) |
42f61420 | 1394 | { |
a4aea562 | 1395 | unsigned i; |
749941f2 | 1396 | int ret = 0; |
42f61420 | 1397 | |
749941f2 CH |
1398 | for (i = dev->queue_count; i <= dev->max_qid; i++) { |
1399 | if (!nvme_alloc_queue(dev, i, dev->q_depth)) { | |
1400 | ret = -ENOMEM; | |
42f61420 | 1401 | break; |
749941f2 CH |
1402 | } |
1403 | } | |
42f61420 | 1404 | |
749941f2 CH |
1405 | for (i = dev->online_queues; i <= dev->queue_count - 1; i++) { |
1406 | ret = nvme_create_queue(dev->queues[i], i); | |
1407 | if (ret) { | |
2659e57b | 1408 | nvme_free_queues(dev, i); |
42f61420 | 1409 | break; |
2659e57b | 1410 | } |
749941f2 CH |
1411 | } |
1412 | ||
1413 | /* | |
1414 | * Ignore failing Create SQ/CQ commands, we can continue with less | |
1415 | * than the desired aount of queues, and even a controller without | |
1416 | * I/O queues an still be used to issue admin commands. This might | |
1417 | * be useful to upgrade a buggy firmware for example. | |
1418 | */ | |
1419 | return ret >= 0 ? 0 : ret; | |
42f61420 KB |
1420 | } |
1421 | ||
8ffaadf7 JD |
1422 | static void __iomem *nvme_map_cmb(struct nvme_dev *dev) |
1423 | { | |
1424 | u64 szu, size, offset; | |
1425 | u32 cmbloc; | |
1426 | resource_size_t bar_size; | |
1427 | struct pci_dev *pdev = to_pci_dev(dev->dev); | |
1428 | void __iomem *cmb; | |
1429 | dma_addr_t dma_addr; | |
1430 | ||
1431 | if (!use_cmb_sqes) | |
1432 | return NULL; | |
1433 | ||
7a67cbea | 1434 | dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ); |
8ffaadf7 JD |
1435 | if (!(NVME_CMB_SZ(dev->cmbsz))) |
1436 | return NULL; | |
1437 | ||
7a67cbea | 1438 | cmbloc = readl(dev->bar + NVME_REG_CMBLOC); |
8ffaadf7 JD |
1439 | |
1440 | szu = (u64)1 << (12 + 4 * NVME_CMB_SZU(dev->cmbsz)); | |
1441 | size = szu * NVME_CMB_SZ(dev->cmbsz); | |
1442 | offset = szu * NVME_CMB_OFST(cmbloc); | |
1443 | bar_size = pci_resource_len(pdev, NVME_CMB_BIR(cmbloc)); | |
1444 | ||
1445 | if (offset > bar_size) | |
1446 | return NULL; | |
1447 | ||
1448 | /* | |
1449 | * Controllers may support a CMB size larger than their BAR, | |
1450 | * for example, due to being behind a bridge. Reduce the CMB to | |
1451 | * the reported size of the BAR | |
1452 | */ | |
1453 | if (size > bar_size - offset) | |
1454 | size = bar_size - offset; | |
1455 | ||
1456 | dma_addr = pci_resource_start(pdev, NVME_CMB_BIR(cmbloc)) + offset; | |
1457 | cmb = ioremap_wc(dma_addr, size); | |
1458 | if (!cmb) | |
1459 | return NULL; | |
1460 | ||
1461 | dev->cmb_dma_addr = dma_addr; | |
1462 | dev->cmb_size = size; | |
1463 | return cmb; | |
1464 | } | |
1465 | ||
1466 | static inline void nvme_release_cmb(struct nvme_dev *dev) | |
1467 | { | |
1468 | if (dev->cmb) { | |
1469 | iounmap(dev->cmb); | |
1470 | dev->cmb = NULL; | |
1471 | } | |
1472 | } | |
1473 | ||
9d713c2b KB |
1474 | static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) |
1475 | { | |
b80d5ccc | 1476 | return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride); |
9d713c2b KB |
1477 | } |
1478 | ||
8d85fce7 | 1479 | static int nvme_setup_io_queues(struct nvme_dev *dev) |
b60503ba | 1480 | { |
a4aea562 | 1481 | struct nvme_queue *adminq = dev->queues[0]; |
e75ec752 | 1482 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
42f61420 | 1483 | int result, i, vecs, nr_io_queues, size; |
b60503ba | 1484 | |
42f61420 | 1485 | nr_io_queues = num_possible_cpus(); |
9a0be7ab CH |
1486 | result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues); |
1487 | if (result < 0) | |
1b23484b | 1488 | return result; |
9a0be7ab CH |
1489 | |
1490 | /* | |
1491 | * Degraded controllers might return an error when setting the queue | |
1492 | * count. We still want to be able to bring them online and offer | |
1493 | * access to the admin queue, as that might be only way to fix them up. | |
1494 | */ | |
1495 | if (result > 0) { | |
1496 | dev_err(dev->dev, "Could not set queue count (%d)\n", result); | |
1497 | nr_io_queues = 0; | |
1498 | result = 0; | |
1499 | } | |
b60503ba | 1500 | |
8ffaadf7 JD |
1501 | if (dev->cmb && NVME_CMB_SQS(dev->cmbsz)) { |
1502 | result = nvme_cmb_qdepth(dev, nr_io_queues, | |
1503 | sizeof(struct nvme_command)); | |
1504 | if (result > 0) | |
1505 | dev->q_depth = result; | |
1506 | else | |
1507 | nvme_release_cmb(dev); | |
1508 | } | |
1509 | ||
9d713c2b KB |
1510 | size = db_bar_size(dev, nr_io_queues); |
1511 | if (size > 8192) { | |
f1938f6e | 1512 | iounmap(dev->bar); |
9d713c2b KB |
1513 | do { |
1514 | dev->bar = ioremap(pci_resource_start(pdev, 0), size); | |
1515 | if (dev->bar) | |
1516 | break; | |
1517 | if (!--nr_io_queues) | |
1518 | return -ENOMEM; | |
1519 | size = db_bar_size(dev, nr_io_queues); | |
1520 | } while (1); | |
7a67cbea | 1521 | dev->dbs = dev->bar + 4096; |
5a92e700 | 1522 | adminq->q_db = dev->dbs; |
f1938f6e MW |
1523 | } |
1524 | ||
9d713c2b | 1525 | /* Deregister the admin queue's interrupt */ |
3193f07b | 1526 | free_irq(dev->entry[0].vector, adminq); |
9d713c2b | 1527 | |
e32efbfc JA |
1528 | /* |
1529 | * If we enable msix early due to not intx, disable it again before | |
1530 | * setting up the full range we need. | |
1531 | */ | |
1532 | if (!pdev->irq) | |
1533 | pci_disable_msix(pdev); | |
1534 | ||
be577fab | 1535 | for (i = 0; i < nr_io_queues; i++) |
1b23484b | 1536 | dev->entry[i].entry = i; |
be577fab AG |
1537 | vecs = pci_enable_msix_range(pdev, dev->entry, 1, nr_io_queues); |
1538 | if (vecs < 0) { | |
1539 | vecs = pci_enable_msi_range(pdev, 1, min(nr_io_queues, 32)); | |
1540 | if (vecs < 0) { | |
1541 | vecs = 1; | |
1542 | } else { | |
1543 | for (i = 0; i < vecs; i++) | |
1544 | dev->entry[i].vector = i + pdev->irq; | |
fa08a396 RRG |
1545 | } |
1546 | } | |
1547 | ||
063a8096 MW |
1548 | /* |
1549 | * Should investigate if there's a performance win from allocating | |
1550 | * more queues than interrupt vectors; it might allow the submission | |
1551 | * path to scale better, even if the receive path is limited by the | |
1552 | * number of interrupts. | |
1553 | */ | |
1554 | nr_io_queues = vecs; | |
42f61420 | 1555 | dev->max_qid = nr_io_queues; |
063a8096 | 1556 | |
3193f07b | 1557 | result = queue_request_irq(dev, adminq, adminq->irqname); |
758dd7fd JD |
1558 | if (result) { |
1559 | adminq->cq_vector = -1; | |
22404274 | 1560 | goto free_queues; |
758dd7fd | 1561 | } |
1b23484b | 1562 | |
cd638946 | 1563 | /* Free previously allocated queues that are no longer usable */ |
42f61420 | 1564 | nvme_free_queues(dev, nr_io_queues + 1); |
749941f2 | 1565 | return nvme_create_io_queues(dev); |
b60503ba | 1566 | |
22404274 | 1567 | free_queues: |
a1a5ef99 | 1568 | nvme_free_queues(dev, 1); |
22404274 | 1569 | return result; |
b60503ba MW |
1570 | } |
1571 | ||
bda4e0fb KB |
1572 | static void nvme_set_irq_hints(struct nvme_dev *dev) |
1573 | { | |
1574 | struct nvme_queue *nvmeq; | |
1575 | int i; | |
1576 | ||
1577 | for (i = 0; i < dev->online_queues; i++) { | |
1578 | nvmeq = dev->queues[i]; | |
1579 | ||
1580 | if (!nvmeq->tags || !(*nvmeq->tags)) | |
1581 | continue; | |
1582 | ||
1583 | irq_set_affinity_hint(dev->entry[nvmeq->cq_vector].vector, | |
1584 | blk_mq_tags_cpumask(*nvmeq->tags)); | |
1585 | } | |
1586 | } | |
1587 | ||
a5768aa8 KB |
1588 | static void nvme_dev_scan(struct work_struct *work) |
1589 | { | |
1590 | struct nvme_dev *dev = container_of(work, struct nvme_dev, scan_work); | |
a5768aa8 KB |
1591 | |
1592 | if (!dev->tagset.tags) | |
1593 | return; | |
5bae7f73 | 1594 | nvme_scan_namespaces(&dev->ctrl); |
bda4e0fb | 1595 | nvme_set_irq_hints(dev); |
a5768aa8 KB |
1596 | } |
1597 | ||
422ef0c7 MW |
1598 | /* |
1599 | * Return: error value if an error occurred setting up the queues or calling | |
1600 | * Identify Device. 0 if these succeeded, even if adding some of the | |
1601 | * namespaces failed. At the moment, these failures are silent. TBD which | |
1602 | * failures should be reported. | |
1603 | */ | |
8d85fce7 | 1604 | static int nvme_dev_add(struct nvme_dev *dev) |
b60503ba | 1605 | { |
5bae7f73 | 1606 | if (!dev->ctrl.tagset) { |
ffe7704d KB |
1607 | dev->tagset.ops = &nvme_mq_ops; |
1608 | dev->tagset.nr_hw_queues = dev->online_queues - 1; | |
1609 | dev->tagset.timeout = NVME_IO_TIMEOUT; | |
1610 | dev->tagset.numa_node = dev_to_node(dev->dev); | |
1611 | dev->tagset.queue_depth = | |
a4aea562 | 1612 | min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1; |
ffe7704d KB |
1613 | dev->tagset.cmd_size = nvme_cmd_size(dev); |
1614 | dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE; | |
1615 | dev->tagset.driver_data = dev; | |
b60503ba | 1616 | |
ffe7704d KB |
1617 | if (blk_mq_alloc_tag_set(&dev->tagset)) |
1618 | return 0; | |
5bae7f73 | 1619 | dev->ctrl.tagset = &dev->tagset; |
ffe7704d | 1620 | } |
92f7a162 | 1621 | queue_work(nvme_workq, &dev->scan_work); |
e1e5e564 | 1622 | return 0; |
b60503ba MW |
1623 | } |
1624 | ||
0877cb0d KB |
1625 | static int nvme_dev_map(struct nvme_dev *dev) |
1626 | { | |
42f61420 | 1627 | u64 cap; |
0877cb0d | 1628 | int bars, result = -ENOMEM; |
e75ec752 | 1629 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
0877cb0d KB |
1630 | |
1631 | if (pci_enable_device_mem(pdev)) | |
1632 | return result; | |
1633 | ||
1634 | dev->entry[0].vector = pdev->irq; | |
1635 | pci_set_master(pdev); | |
1636 | bars = pci_select_bars(pdev, IORESOURCE_MEM); | |
be7837e8 JA |
1637 | if (!bars) |
1638 | goto disable_pci; | |
1639 | ||
0877cb0d KB |
1640 | if (pci_request_selected_regions(pdev, bars, "nvme")) |
1641 | goto disable_pci; | |
1642 | ||
e75ec752 CH |
1643 | if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) && |
1644 | dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32))) | |
052d0efa | 1645 | goto disable; |
0877cb0d | 1646 | |
0877cb0d KB |
1647 | dev->bar = ioremap(pci_resource_start(pdev, 0), 8192); |
1648 | if (!dev->bar) | |
1649 | goto disable; | |
e32efbfc | 1650 | |
7a67cbea | 1651 | if (readl(dev->bar + NVME_REG_CSTS) == -1) { |
0e53d180 KB |
1652 | result = -ENODEV; |
1653 | goto unmap; | |
1654 | } | |
e32efbfc JA |
1655 | |
1656 | /* | |
1657 | * Some devices don't advertse INTx interrupts, pre-enable a single | |
1658 | * MSIX vec for setup. We'll adjust this later. | |
1659 | */ | |
1660 | if (!pdev->irq) { | |
1661 | result = pci_enable_msix(pdev, dev->entry, 1); | |
1662 | if (result < 0) | |
1663 | goto unmap; | |
1664 | } | |
1665 | ||
7a67cbea CH |
1666 | cap = lo_hi_readq(dev->bar + NVME_REG_CAP); |
1667 | ||
42f61420 KB |
1668 | dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH); |
1669 | dev->db_stride = 1 << NVME_CAP_STRIDE(cap); | |
7a67cbea CH |
1670 | dev->dbs = dev->bar + 4096; |
1671 | if (readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 2)) | |
8ffaadf7 | 1672 | dev->cmb = nvme_map_cmb(dev); |
0877cb0d | 1673 | |
a0a3408e KB |
1674 | pci_enable_pcie_error_reporting(pdev); |
1675 | pci_save_state(pdev); | |
0877cb0d KB |
1676 | return 0; |
1677 | ||
0e53d180 KB |
1678 | unmap: |
1679 | iounmap(dev->bar); | |
1680 | dev->bar = NULL; | |
0877cb0d KB |
1681 | disable: |
1682 | pci_release_regions(pdev); | |
1683 | disable_pci: | |
1684 | pci_disable_device(pdev); | |
1685 | return result; | |
1686 | } | |
1687 | ||
1688 | static void nvme_dev_unmap(struct nvme_dev *dev) | |
1689 | { | |
e75ec752 CH |
1690 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
1691 | ||
1692 | if (pdev->msi_enabled) | |
1693 | pci_disable_msi(pdev); | |
1694 | else if (pdev->msix_enabled) | |
1695 | pci_disable_msix(pdev); | |
0877cb0d KB |
1696 | |
1697 | if (dev->bar) { | |
1698 | iounmap(dev->bar); | |
1699 | dev->bar = NULL; | |
e75ec752 | 1700 | pci_release_regions(pdev); |
0877cb0d KB |
1701 | } |
1702 | ||
a0a3408e KB |
1703 | if (pci_is_enabled(pdev)) { |
1704 | pci_disable_pcie_error_reporting(pdev); | |
e75ec752 | 1705 | pci_disable_device(pdev); |
a0a3408e | 1706 | } |
0877cb0d KB |
1707 | } |
1708 | ||
4d115420 KB |
1709 | struct nvme_delq_ctx { |
1710 | struct task_struct *waiter; | |
1711 | struct kthread_worker *worker; | |
1712 | atomic_t refcount; | |
1713 | }; | |
1714 | ||
1715 | static void nvme_wait_dq(struct nvme_delq_ctx *dq, struct nvme_dev *dev) | |
1716 | { | |
1717 | dq->waiter = current; | |
1718 | mb(); | |
1719 | ||
1720 | for (;;) { | |
1721 | set_current_state(TASK_KILLABLE); | |
1722 | if (!atomic_read(&dq->refcount)) | |
1723 | break; | |
1724 | if (!schedule_timeout(ADMIN_TIMEOUT) || | |
1725 | fatal_signal_pending(current)) { | |
0fb59cbc KB |
1726 | /* |
1727 | * Disable the controller first since we can't trust it | |
1728 | * at this point, but leave the admin queue enabled | |
1729 | * until all queue deletion requests are flushed. | |
1730 | * FIXME: This may take a while if there are more h/w | |
1731 | * queues than admin tags. | |
1732 | */ | |
4d115420 | 1733 | set_current_state(TASK_RUNNING); |
5fd4ce1b | 1734 | nvme_disable_ctrl(&dev->ctrl, |
7a67cbea | 1735 | lo_hi_readq(dev->bar + NVME_REG_CAP)); |
0fb59cbc | 1736 | nvme_clear_queue(dev->queues[0]); |
4d115420 | 1737 | flush_kthread_worker(dq->worker); |
0fb59cbc | 1738 | nvme_disable_queue(dev, 0); |
4d115420 KB |
1739 | return; |
1740 | } | |
1741 | } | |
1742 | set_current_state(TASK_RUNNING); | |
1743 | } | |
1744 | ||
1745 | static void nvme_put_dq(struct nvme_delq_ctx *dq) | |
1746 | { | |
1747 | atomic_dec(&dq->refcount); | |
1748 | if (dq->waiter) | |
1749 | wake_up_process(dq->waiter); | |
1750 | } | |
1751 | ||
1752 | static struct nvme_delq_ctx *nvme_get_dq(struct nvme_delq_ctx *dq) | |
1753 | { | |
1754 | atomic_inc(&dq->refcount); | |
1755 | return dq; | |
1756 | } | |
1757 | ||
1758 | static void nvme_del_queue_end(struct nvme_queue *nvmeq) | |
1759 | { | |
1760 | struct nvme_delq_ctx *dq = nvmeq->cmdinfo.ctx; | |
4d115420 | 1761 | nvme_put_dq(dq); |
604e8c8d KB |
1762 | |
1763 | spin_lock_irq(&nvmeq->q_lock); | |
1764 | nvme_process_cq(nvmeq); | |
1765 | spin_unlock_irq(&nvmeq->q_lock); | |
4d115420 KB |
1766 | } |
1767 | ||
1768 | static int adapter_async_del_queue(struct nvme_queue *nvmeq, u8 opcode, | |
1769 | kthread_work_func_t fn) | |
1770 | { | |
d8f32166 | 1771 | struct request *req; |
4d115420 KB |
1772 | struct nvme_command c; |
1773 | ||
1774 | memset(&c, 0, sizeof(c)); | |
1775 | c.delete_queue.opcode = opcode; | |
1776 | c.delete_queue.qid = cpu_to_le16(nvmeq->qid); | |
1777 | ||
1778 | init_kthread_work(&nvmeq->cmdinfo.work, fn); | |
d8f32166 CH |
1779 | |
1780 | req = nvme_alloc_request(nvmeq->dev->ctrl.admin_q, &c, 0); | |
1781 | if (IS_ERR(req)) | |
1782 | return PTR_ERR(req); | |
1783 | ||
1784 | req->timeout = ADMIN_TIMEOUT; | |
1785 | req->end_io_data = &nvmeq->cmdinfo; | |
1786 | blk_execute_rq_nowait(req->q, NULL, req, 0, async_cmd_info_endio); | |
1787 | return 0; | |
4d115420 KB |
1788 | } |
1789 | ||
1790 | static void nvme_del_cq_work_handler(struct kthread_work *work) | |
1791 | { | |
1792 | struct nvme_queue *nvmeq = container_of(work, struct nvme_queue, | |
1793 | cmdinfo.work); | |
1794 | nvme_del_queue_end(nvmeq); | |
1795 | } | |
1796 | ||
1797 | static int nvme_delete_cq(struct nvme_queue *nvmeq) | |
1798 | { | |
1799 | return adapter_async_del_queue(nvmeq, nvme_admin_delete_cq, | |
1800 | nvme_del_cq_work_handler); | |
1801 | } | |
1802 | ||
1803 | static void nvme_del_sq_work_handler(struct kthread_work *work) | |
1804 | { | |
1805 | struct nvme_queue *nvmeq = container_of(work, struct nvme_queue, | |
1806 | cmdinfo.work); | |
1807 | int status = nvmeq->cmdinfo.status; | |
1808 | ||
1809 | if (!status) | |
1810 | status = nvme_delete_cq(nvmeq); | |
1811 | if (status) | |
1812 | nvme_del_queue_end(nvmeq); | |
1813 | } | |
1814 | ||
1815 | static int nvme_delete_sq(struct nvme_queue *nvmeq) | |
1816 | { | |
1817 | return adapter_async_del_queue(nvmeq, nvme_admin_delete_sq, | |
1818 | nvme_del_sq_work_handler); | |
1819 | } | |
1820 | ||
1821 | static void nvme_del_queue_start(struct kthread_work *work) | |
1822 | { | |
1823 | struct nvme_queue *nvmeq = container_of(work, struct nvme_queue, | |
1824 | cmdinfo.work); | |
4d115420 KB |
1825 | if (nvme_delete_sq(nvmeq)) |
1826 | nvme_del_queue_end(nvmeq); | |
1827 | } | |
1828 | ||
1829 | static void nvme_disable_io_queues(struct nvme_dev *dev) | |
1830 | { | |
1831 | int i; | |
1832 | DEFINE_KTHREAD_WORKER_ONSTACK(worker); | |
1833 | struct nvme_delq_ctx dq; | |
1834 | struct task_struct *kworker_task = kthread_run(kthread_worker_fn, | |
1c63dc66 | 1835 | &worker, "nvme%d", dev->ctrl.instance); |
4d115420 KB |
1836 | |
1837 | if (IS_ERR(kworker_task)) { | |
e75ec752 | 1838 | dev_err(dev->dev, |
4d115420 KB |
1839 | "Failed to create queue del task\n"); |
1840 | for (i = dev->queue_count - 1; i > 0; i--) | |
1841 | nvme_disable_queue(dev, i); | |
1842 | return; | |
1843 | } | |
1844 | ||
1845 | dq.waiter = NULL; | |
1846 | atomic_set(&dq.refcount, 0); | |
1847 | dq.worker = &worker; | |
1848 | for (i = dev->queue_count - 1; i > 0; i--) { | |
a4aea562 | 1849 | struct nvme_queue *nvmeq = dev->queues[i]; |
4d115420 KB |
1850 | |
1851 | if (nvme_suspend_queue(nvmeq)) | |
1852 | continue; | |
1853 | nvmeq->cmdinfo.ctx = nvme_get_dq(&dq); | |
1854 | nvmeq->cmdinfo.worker = dq.worker; | |
1855 | init_kthread_work(&nvmeq->cmdinfo.work, nvme_del_queue_start); | |
1856 | queue_kthread_work(dq.worker, &nvmeq->cmdinfo.work); | |
1857 | } | |
1858 | nvme_wait_dq(&dq, dev); | |
1859 | kthread_stop(kworker_task); | |
1860 | } | |
1861 | ||
7385014c CH |
1862 | static int nvme_dev_list_add(struct nvme_dev *dev) |
1863 | { | |
1864 | bool start_thread = false; | |
1865 | ||
1866 | spin_lock(&dev_list_lock); | |
1867 | if (list_empty(&dev_list) && IS_ERR_OR_NULL(nvme_thread)) { | |
1868 | start_thread = true; | |
1869 | nvme_thread = NULL; | |
1870 | } | |
1871 | list_add(&dev->node, &dev_list); | |
1872 | spin_unlock(&dev_list_lock); | |
1873 | ||
1874 | if (start_thread) { | |
1875 | nvme_thread = kthread_run(nvme_kthread, NULL, "nvme"); | |
1876 | wake_up_all(&nvme_kthread_wait); | |
1877 | } else | |
1878 | wait_event_killable(nvme_kthread_wait, nvme_thread); | |
1879 | ||
1880 | if (IS_ERR_OR_NULL(nvme_thread)) | |
1881 | return nvme_thread ? PTR_ERR(nvme_thread) : -EINTR; | |
1882 | ||
1883 | return 0; | |
1884 | } | |
1885 | ||
b9afca3e DM |
1886 | /* |
1887 | * Remove the node from the device list and check | |
1888 | * for whether or not we need to stop the nvme_thread. | |
1889 | */ | |
1890 | static void nvme_dev_list_remove(struct nvme_dev *dev) | |
1891 | { | |
1892 | struct task_struct *tmp = NULL; | |
1893 | ||
1894 | spin_lock(&dev_list_lock); | |
1895 | list_del_init(&dev->node); | |
1896 | if (list_empty(&dev_list) && !IS_ERR_OR_NULL(nvme_thread)) { | |
1897 | tmp = nvme_thread; | |
1898 | nvme_thread = NULL; | |
1899 | } | |
1900 | spin_unlock(&dev_list_lock); | |
1901 | ||
1902 | if (tmp) | |
1903 | kthread_stop(tmp); | |
1904 | } | |
1905 | ||
f0b50732 | 1906 | static void nvme_dev_shutdown(struct nvme_dev *dev) |
b60503ba | 1907 | { |
22404274 | 1908 | int i; |
7c1b2450 | 1909 | u32 csts = -1; |
22404274 | 1910 | |
b9afca3e | 1911 | nvme_dev_list_remove(dev); |
1fa6aead | 1912 | |
77bf25ea | 1913 | mutex_lock(&dev->shutdown_lock); |
c9d3bf88 | 1914 | if (dev->bar) { |
363c9aac | 1915 | nvme_freeze_queues(&dev->ctrl); |
7a67cbea | 1916 | csts = readl(dev->bar + NVME_REG_CSTS); |
c9d3bf88 | 1917 | } |
7c1b2450 | 1918 | if (csts & NVME_CSTS_CFS || !(csts & NVME_CSTS_RDY)) { |
4d115420 | 1919 | for (i = dev->queue_count - 1; i >= 0; i--) { |
a4aea562 | 1920 | struct nvme_queue *nvmeq = dev->queues[i]; |
4d115420 | 1921 | nvme_suspend_queue(nvmeq); |
4d115420 KB |
1922 | } |
1923 | } else { | |
1924 | nvme_disable_io_queues(dev); | |
5fd4ce1b | 1925 | nvme_shutdown_ctrl(&dev->ctrl); |
4d115420 KB |
1926 | nvme_disable_queue(dev, 0); |
1927 | } | |
f0b50732 | 1928 | nvme_dev_unmap(dev); |
07836e65 KB |
1929 | |
1930 | for (i = dev->queue_count - 1; i >= 0; i--) | |
1931 | nvme_clear_queue(dev->queues[i]); | |
77bf25ea | 1932 | mutex_unlock(&dev->shutdown_lock); |
f0b50732 KB |
1933 | } |
1934 | ||
091b6092 MW |
1935 | static int nvme_setup_prp_pools(struct nvme_dev *dev) |
1936 | { | |
e75ec752 | 1937 | dev->prp_page_pool = dma_pool_create("prp list page", dev->dev, |
091b6092 MW |
1938 | PAGE_SIZE, PAGE_SIZE, 0); |
1939 | if (!dev->prp_page_pool) | |
1940 | return -ENOMEM; | |
1941 | ||
99802a7a | 1942 | /* Optimisation for I/Os between 4k and 128k */ |
e75ec752 | 1943 | dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev, |
99802a7a MW |
1944 | 256, 256, 0); |
1945 | if (!dev->prp_small_pool) { | |
1946 | dma_pool_destroy(dev->prp_page_pool); | |
1947 | return -ENOMEM; | |
1948 | } | |
091b6092 MW |
1949 | return 0; |
1950 | } | |
1951 | ||
1952 | static void nvme_release_prp_pools(struct nvme_dev *dev) | |
1953 | { | |
1954 | dma_pool_destroy(dev->prp_page_pool); | |
99802a7a | 1955 | dma_pool_destroy(dev->prp_small_pool); |
091b6092 MW |
1956 | } |
1957 | ||
1673f1f0 | 1958 | static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl) |
5e82e952 | 1959 | { |
1673f1f0 | 1960 | struct nvme_dev *dev = to_nvme_dev(ctrl); |
9ac27090 | 1961 | |
e75ec752 | 1962 | put_device(dev->dev); |
4af0e21c KB |
1963 | if (dev->tagset.tags) |
1964 | blk_mq_free_tag_set(&dev->tagset); | |
1c63dc66 CH |
1965 | if (dev->ctrl.admin_q) |
1966 | blk_put_queue(dev->ctrl.admin_q); | |
5e82e952 KB |
1967 | kfree(dev->queues); |
1968 | kfree(dev->entry); | |
1969 | kfree(dev); | |
1970 | } | |
1971 | ||
fd634f41 | 1972 | static void nvme_reset_work(struct work_struct *work) |
f0b50732 | 1973 | { |
fd634f41 | 1974 | struct nvme_dev *dev = container_of(work, struct nvme_dev, reset_work); |
3cf519b5 | 1975 | int result; |
f0b50732 | 1976 | |
fd634f41 CH |
1977 | if (WARN_ON(test_bit(NVME_CTRL_RESETTING, &dev->flags))) |
1978 | goto out; | |
1979 | ||
1980 | /* | |
1981 | * If we're called to reset a live controller first shut it down before | |
1982 | * moving on. | |
1983 | */ | |
1984 | if (dev->bar) | |
1985 | nvme_dev_shutdown(dev); | |
1986 | ||
1987 | set_bit(NVME_CTRL_RESETTING, &dev->flags); | |
1988 | ||
f0b50732 KB |
1989 | result = nvme_dev_map(dev); |
1990 | if (result) | |
3cf519b5 | 1991 | goto out; |
f0b50732 KB |
1992 | |
1993 | result = nvme_configure_admin_queue(dev); | |
1994 | if (result) | |
1995 | goto unmap; | |
1996 | ||
a4aea562 | 1997 | nvme_init_queue(dev->queues[0], 0); |
0fb59cbc KB |
1998 | result = nvme_alloc_admin_tags(dev); |
1999 | if (result) | |
2000 | goto disable; | |
b9afca3e | 2001 | |
ce4541f4 CH |
2002 | result = nvme_init_identify(&dev->ctrl); |
2003 | if (result) | |
2004 | goto free_tags; | |
2005 | ||
f0b50732 | 2006 | result = nvme_setup_io_queues(dev); |
badc34d4 | 2007 | if (result) |
0fb59cbc | 2008 | goto free_tags; |
f0b50732 | 2009 | |
adf68f21 | 2010 | dev->ctrl.event_limit = NVME_NR_AEN_COMMANDS; |
3cf519b5 | 2011 | |
7385014c CH |
2012 | result = nvme_dev_list_add(dev); |
2013 | if (result) | |
2014 | goto remove; | |
2015 | ||
2659e57b CH |
2016 | /* |
2017 | * Keep the controller around but remove all namespaces if we don't have | |
2018 | * any working I/O queue. | |
2019 | */ | |
3cf519b5 CH |
2020 | if (dev->online_queues < 2) { |
2021 | dev_warn(dev->dev, "IO queues not created\n"); | |
5bae7f73 | 2022 | nvme_remove_namespaces(&dev->ctrl); |
3cf519b5 | 2023 | } else { |
363c9aac | 2024 | nvme_unfreeze_queues(&dev->ctrl); |
3cf519b5 CH |
2025 | nvme_dev_add(dev); |
2026 | } | |
2027 | ||
fd634f41 | 2028 | clear_bit(NVME_CTRL_RESETTING, &dev->flags); |
3cf519b5 | 2029 | return; |
f0b50732 | 2030 | |
7385014c CH |
2031 | remove: |
2032 | nvme_dev_list_remove(dev); | |
0fb59cbc KB |
2033 | free_tags: |
2034 | nvme_dev_remove_admin(dev); | |
1c63dc66 CH |
2035 | blk_put_queue(dev->ctrl.admin_q); |
2036 | dev->ctrl.admin_q = NULL; | |
4af0e21c | 2037 | dev->queues[0]->tags = NULL; |
f0b50732 | 2038 | disable: |
a1a5ef99 | 2039 | nvme_disable_queue(dev, 0); |
f0b50732 KB |
2040 | unmap: |
2041 | nvme_dev_unmap(dev); | |
3cf519b5 | 2042 | out: |
5c8809e6 | 2043 | nvme_remove_dead_ctrl(dev); |
f0b50732 KB |
2044 | } |
2045 | ||
5c8809e6 | 2046 | static void nvme_remove_dead_ctrl_work(struct work_struct *work) |
9a6b9458 | 2047 | { |
5c8809e6 | 2048 | struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work); |
e75ec752 | 2049 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
9a6b9458 KB |
2050 | |
2051 | if (pci_get_drvdata(pdev)) | |
c81f4975 | 2052 | pci_stop_and_remove_bus_device_locked(pdev); |
1673f1f0 | 2053 | nvme_put_ctrl(&dev->ctrl); |
9a6b9458 KB |
2054 | } |
2055 | ||
5c8809e6 | 2056 | static void nvme_remove_dead_ctrl(struct nvme_dev *dev) |
de3eff2b | 2057 | { |
5c8809e6 | 2058 | dev_warn(dev->dev, "Removing after probe failure\n"); |
1673f1f0 | 2059 | kref_get(&dev->ctrl.kref); |
5c8809e6 | 2060 | if (!schedule_work(&dev->remove_work)) |
1673f1f0 | 2061 | nvme_put_ctrl(&dev->ctrl); |
de3eff2b KB |
2062 | } |
2063 | ||
4cc06521 KB |
2064 | static int nvme_reset(struct nvme_dev *dev) |
2065 | { | |
1c63dc66 | 2066 | if (!dev->ctrl.admin_q || blk_queue_dying(dev->ctrl.admin_q)) |
4cc06521 KB |
2067 | return -ENODEV; |
2068 | ||
846cc05f CH |
2069 | if (!queue_work(nvme_workq, &dev->reset_work)) |
2070 | return -EBUSY; | |
4cc06521 | 2071 | |
846cc05f | 2072 | flush_work(&dev->reset_work); |
846cc05f | 2073 | return 0; |
4cc06521 KB |
2074 | } |
2075 | ||
1c63dc66 CH |
2076 | static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val) |
2077 | { | |
2078 | *val = readl(to_nvme_dev(ctrl)->bar + off); | |
2079 | return 0; | |
2080 | } | |
2081 | ||
5fd4ce1b CH |
2082 | static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val) |
2083 | { | |
2084 | writel(val, to_nvme_dev(ctrl)->bar + off); | |
2085 | return 0; | |
2086 | } | |
2087 | ||
7fd8930f CH |
2088 | static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val) |
2089 | { | |
2090 | *val = readq(to_nvme_dev(ctrl)->bar + off); | |
2091 | return 0; | |
2092 | } | |
2093 | ||
5bae7f73 CH |
2094 | static bool nvme_pci_io_incapable(struct nvme_ctrl *ctrl) |
2095 | { | |
2096 | struct nvme_dev *dev = to_nvme_dev(ctrl); | |
2097 | ||
2098 | return !dev->bar || dev->online_queues < 2; | |
2099 | } | |
2100 | ||
f3ca80fc CH |
2101 | static int nvme_pci_reset_ctrl(struct nvme_ctrl *ctrl) |
2102 | { | |
2103 | return nvme_reset(to_nvme_dev(ctrl)); | |
2104 | } | |
2105 | ||
1c63dc66 CH |
2106 | static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = { |
2107 | .reg_read32 = nvme_pci_reg_read32, | |
5fd4ce1b | 2108 | .reg_write32 = nvme_pci_reg_write32, |
7fd8930f | 2109 | .reg_read64 = nvme_pci_reg_read64, |
5bae7f73 | 2110 | .io_incapable = nvme_pci_io_incapable, |
f3ca80fc | 2111 | .reset_ctrl = nvme_pci_reset_ctrl, |
1673f1f0 | 2112 | .free_ctrl = nvme_pci_free_ctrl, |
1c63dc66 CH |
2113 | }; |
2114 | ||
8d85fce7 | 2115 | static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) |
b60503ba | 2116 | { |
a4aea562 | 2117 | int node, result = -ENOMEM; |
b60503ba MW |
2118 | struct nvme_dev *dev; |
2119 | ||
a4aea562 MB |
2120 | node = dev_to_node(&pdev->dev); |
2121 | if (node == NUMA_NO_NODE) | |
2122 | set_dev_node(&pdev->dev, 0); | |
2123 | ||
2124 | dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); | |
b60503ba MW |
2125 | if (!dev) |
2126 | return -ENOMEM; | |
a4aea562 MB |
2127 | dev->entry = kzalloc_node(num_possible_cpus() * sizeof(*dev->entry), |
2128 | GFP_KERNEL, node); | |
b60503ba MW |
2129 | if (!dev->entry) |
2130 | goto free; | |
a4aea562 MB |
2131 | dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *), |
2132 | GFP_KERNEL, node); | |
b60503ba MW |
2133 | if (!dev->queues) |
2134 | goto free; | |
2135 | ||
e75ec752 | 2136 | dev->dev = get_device(&pdev->dev); |
9a6b9458 | 2137 | pci_set_drvdata(pdev, dev); |
1c63dc66 | 2138 | |
f3ca80fc CH |
2139 | INIT_LIST_HEAD(&dev->node); |
2140 | INIT_WORK(&dev->scan_work, nvme_dev_scan); | |
f3ca80fc | 2141 | INIT_WORK(&dev->reset_work, nvme_reset_work); |
5c8809e6 | 2142 | INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work); |
77bf25ea | 2143 | mutex_init(&dev->shutdown_lock); |
1c63dc66 | 2144 | |
f3ca80fc | 2145 | result = nvme_setup_prp_pools(dev); |
cd58ad7d | 2146 | if (result) |
a96d4f5c | 2147 | goto put_pci; |
b60503ba | 2148 | |
f3ca80fc CH |
2149 | result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops, |
2150 | id->driver_data); | |
091b6092 | 2151 | if (result) |
2e1d8448 | 2152 | goto release_pools; |
740216fc | 2153 | |
92f7a162 | 2154 | queue_work(nvme_workq, &dev->reset_work); |
b60503ba MW |
2155 | return 0; |
2156 | ||
0877cb0d | 2157 | release_pools: |
091b6092 | 2158 | nvme_release_prp_pools(dev); |
a96d4f5c | 2159 | put_pci: |
e75ec752 | 2160 | put_device(dev->dev); |
b60503ba MW |
2161 | free: |
2162 | kfree(dev->queues); | |
2163 | kfree(dev->entry); | |
2164 | kfree(dev); | |
2165 | return result; | |
2166 | } | |
2167 | ||
f0d54a54 KB |
2168 | static void nvme_reset_notify(struct pci_dev *pdev, bool prepare) |
2169 | { | |
a6739479 | 2170 | struct nvme_dev *dev = pci_get_drvdata(pdev); |
f0d54a54 | 2171 | |
a6739479 KB |
2172 | if (prepare) |
2173 | nvme_dev_shutdown(dev); | |
2174 | else | |
92f7a162 | 2175 | queue_work(nvme_workq, &dev->reset_work); |
f0d54a54 KB |
2176 | } |
2177 | ||
09ece142 KB |
2178 | static void nvme_shutdown(struct pci_dev *pdev) |
2179 | { | |
2180 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
2181 | nvme_dev_shutdown(dev); | |
2182 | } | |
2183 | ||
8d85fce7 | 2184 | static void nvme_remove(struct pci_dev *pdev) |
b60503ba MW |
2185 | { |
2186 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
9a6b9458 KB |
2187 | |
2188 | spin_lock(&dev_list_lock); | |
2189 | list_del_init(&dev->node); | |
2190 | spin_unlock(&dev_list_lock); | |
2191 | ||
2192 | pci_set_drvdata(pdev, NULL); | |
2193 | flush_work(&dev->reset_work); | |
a5768aa8 | 2194 | flush_work(&dev->scan_work); |
5bae7f73 | 2195 | nvme_remove_namespaces(&dev->ctrl); |
53029b04 | 2196 | nvme_uninit_ctrl(&dev->ctrl); |
3399a3f7 | 2197 | nvme_dev_shutdown(dev); |
a4aea562 | 2198 | nvme_dev_remove_admin(dev); |
a1a5ef99 | 2199 | nvme_free_queues(dev, 0); |
8ffaadf7 | 2200 | nvme_release_cmb(dev); |
9a6b9458 | 2201 | nvme_release_prp_pools(dev); |
1673f1f0 | 2202 | nvme_put_ctrl(&dev->ctrl); |
b60503ba MW |
2203 | } |
2204 | ||
671a6018 | 2205 | #ifdef CONFIG_PM_SLEEP |
cd638946 KB |
2206 | static int nvme_suspend(struct device *dev) |
2207 | { | |
2208 | struct pci_dev *pdev = to_pci_dev(dev); | |
2209 | struct nvme_dev *ndev = pci_get_drvdata(pdev); | |
2210 | ||
2211 | nvme_dev_shutdown(ndev); | |
2212 | return 0; | |
2213 | } | |
2214 | ||
2215 | static int nvme_resume(struct device *dev) | |
2216 | { | |
2217 | struct pci_dev *pdev = to_pci_dev(dev); | |
2218 | struct nvme_dev *ndev = pci_get_drvdata(pdev); | |
cd638946 | 2219 | |
92f7a162 | 2220 | queue_work(nvme_workq, &ndev->reset_work); |
9a6b9458 | 2221 | return 0; |
cd638946 | 2222 | } |
671a6018 | 2223 | #endif |
cd638946 KB |
2224 | |
2225 | static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume); | |
b60503ba | 2226 | |
a0a3408e KB |
2227 | static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev, |
2228 | pci_channel_state_t state) | |
2229 | { | |
2230 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
2231 | ||
2232 | /* | |
2233 | * A frozen channel requires a reset. When detected, this method will | |
2234 | * shutdown the controller to quiesce. The controller will be restarted | |
2235 | * after the slot reset through driver's slot_reset callback. | |
2236 | */ | |
2237 | dev_warn(&pdev->dev, "error detected: state:%d\n", state); | |
2238 | switch (state) { | |
2239 | case pci_channel_io_normal: | |
2240 | return PCI_ERS_RESULT_CAN_RECOVER; | |
2241 | case pci_channel_io_frozen: | |
2242 | nvme_dev_shutdown(dev); | |
2243 | return PCI_ERS_RESULT_NEED_RESET; | |
2244 | case pci_channel_io_perm_failure: | |
2245 | return PCI_ERS_RESULT_DISCONNECT; | |
2246 | } | |
2247 | return PCI_ERS_RESULT_NEED_RESET; | |
2248 | } | |
2249 | ||
2250 | static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev) | |
2251 | { | |
2252 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
2253 | ||
2254 | dev_info(&pdev->dev, "restart after slot reset\n"); | |
2255 | pci_restore_state(pdev); | |
2256 | queue_work(nvme_workq, &dev->reset_work); | |
2257 | return PCI_ERS_RESULT_RECOVERED; | |
2258 | } | |
2259 | ||
2260 | static void nvme_error_resume(struct pci_dev *pdev) | |
2261 | { | |
2262 | pci_cleanup_aer_uncorrect_error_status(pdev); | |
2263 | } | |
2264 | ||
1d352035 | 2265 | static const struct pci_error_handlers nvme_err_handler = { |
b60503ba | 2266 | .error_detected = nvme_error_detected, |
b60503ba MW |
2267 | .slot_reset = nvme_slot_reset, |
2268 | .resume = nvme_error_resume, | |
f0d54a54 | 2269 | .reset_notify = nvme_reset_notify, |
b60503ba MW |
2270 | }; |
2271 | ||
2272 | /* Move to pci_ids.h later */ | |
2273 | #define PCI_CLASS_STORAGE_EXPRESS 0x010802 | |
2274 | ||
6eb0d698 | 2275 | static const struct pci_device_id nvme_id_table[] = { |
106198ed CH |
2276 | { PCI_VDEVICE(INTEL, 0x0953), |
2277 | .driver_data = NVME_QUIRK_STRIPE_SIZE, }, | |
540c801c KB |
2278 | { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */ |
2279 | .driver_data = NVME_QUIRK_IDENTIFY_CNS, }, | |
b60503ba | 2280 | { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, |
c74dc780 | 2281 | { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) }, |
b60503ba MW |
2282 | { 0, } |
2283 | }; | |
2284 | MODULE_DEVICE_TABLE(pci, nvme_id_table); | |
2285 | ||
2286 | static struct pci_driver nvme_driver = { | |
2287 | .name = "nvme", | |
2288 | .id_table = nvme_id_table, | |
2289 | .probe = nvme_probe, | |
8d85fce7 | 2290 | .remove = nvme_remove, |
09ece142 | 2291 | .shutdown = nvme_shutdown, |
cd638946 KB |
2292 | .driver = { |
2293 | .pm = &nvme_dev_pm_ops, | |
2294 | }, | |
b60503ba MW |
2295 | .err_handler = &nvme_err_handler, |
2296 | }; | |
2297 | ||
2298 | static int __init nvme_init(void) | |
2299 | { | |
0ac13140 | 2300 | int result; |
1fa6aead | 2301 | |
b9afca3e | 2302 | init_waitqueue_head(&nvme_kthread_wait); |
b60503ba | 2303 | |
92f7a162 | 2304 | nvme_workq = alloc_workqueue("nvme", WQ_UNBOUND | WQ_MEM_RECLAIM, 0); |
9a6b9458 | 2305 | if (!nvme_workq) |
b9afca3e | 2306 | return -ENOMEM; |
9a6b9458 | 2307 | |
5bae7f73 | 2308 | result = nvme_core_init(); |
5c42ea16 | 2309 | if (result < 0) |
9a6b9458 | 2310 | goto kill_workq; |
b60503ba | 2311 | |
f3db22fe KB |
2312 | result = pci_register_driver(&nvme_driver); |
2313 | if (result) | |
f3ca80fc | 2314 | goto core_exit; |
1fa6aead | 2315 | return 0; |
b60503ba | 2316 | |
f3ca80fc | 2317 | core_exit: |
5bae7f73 | 2318 | nvme_core_exit(); |
9a6b9458 KB |
2319 | kill_workq: |
2320 | destroy_workqueue(nvme_workq); | |
b60503ba MW |
2321 | return result; |
2322 | } | |
2323 | ||
2324 | static void __exit nvme_exit(void) | |
2325 | { | |
2326 | pci_unregister_driver(&nvme_driver); | |
5bae7f73 | 2327 | nvme_core_exit(); |
9a6b9458 | 2328 | destroy_workqueue(nvme_workq); |
b9afca3e | 2329 | BUG_ON(nvme_thread && !IS_ERR(nvme_thread)); |
21bd78bc | 2330 | _nvme_check_size(); |
b60503ba MW |
2331 | } |
2332 | ||
2333 | MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); | |
2334 | MODULE_LICENSE("GPL"); | |
c78b4713 | 2335 | MODULE_VERSION("1.0"); |
b60503ba MW |
2336 | module_init(nvme_init); |
2337 | module_exit(nvme_exit); |