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nvme: fix 32-bit build warning
[linux-2.6-block.git] / drivers / nvme / host / pci.c
CommitLineData
b60503ba
MW		 1/*
2 * NVM Express device driver
6eb0d698 3 * Copyright (c) 2011-2014, Intel Corporation.
b60503ba
MW		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
b60503ba
MW		 13 */
14
8de05535 15#include <linux/bitops.h>
b60503ba 16#include <linux/blkdev.h>
a4aea562 17#include <linux/blk-mq.h>
42f61420 18#include <linux/cpu.h>
fd63e9ce 19#include <linux/delay.h>
b60503ba
MW		 20#include <linux/errno.h>
21#include <linux/fs.h>
22#include <linux/genhd.h>
4cc09e2d 23#include <linux/hdreg.h>
5aff9382 24#include <linux/idr.h>
b60503ba
MW		 25#include <linux/init.h>
26#include <linux/interrupt.h>
27#include <linux/io.h>
28#include <linux/kdev_t.h>
1fa6aead 29#include <linux/kthread.h>
b60503ba 30#include <linux/kernel.h>
a5768aa8 31#include <linux/list_sort.h>
b60503ba
MW		 32#include <linux/mm.h>
33#include <linux/module.h>
34#include <linux/moduleparam.h>
35#include <linux/pci.h>
be7b6275 36#include <linux/poison.h>
c3bfe717 37#include <linux/ptrace.h>
b60503ba
MW		 38#include <linux/sched.h>
39#include <linux/slab.h>
e1e5e564 40#include <linux/t10-pi.h>
b60503ba 41#include <linux/types.h>
5d0f6131 42#include <scsi/sg.h>
797a796a
HM		 43#include <asm-generic/io-64-nonatomic-lo-hi.h>
44
9d99a8dd 45#include <uapi/linux/nvme_ioctl.h>
f11bb3e2
CH		 46#include "nvme.h"
47
b3fffdef 48#define NVME_MINORS (1U << MINORBITS)
9d43cf64 49#define NVME_Q_DEPTH 1024
d31af0a3 50#define NVME_AQ_DEPTH 256
b60503ba
MW		 51#define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
52#define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
9d43cf64 53#define ADMIN_TIMEOUT (admin_timeout * HZ)
2484f407 54#define SHUTDOWN_TIMEOUT (shutdown_timeout * HZ)
9d43cf64
KB		 55
56static unsigned char admin_timeout = 60;
57module_param(admin_timeout, byte, 0644);
58MODULE_PARM_DESC(admin_timeout, "timeout in seconds for admin commands");
b60503ba 59
bd67608a
MW		 60unsigned char nvme_io_timeout = 30;
61module_param_named(io_timeout, nvme_io_timeout, byte, 0644);
b355084a 62MODULE_PARM_DESC(io_timeout, "timeout in seconds for I/O");
b60503ba 63
2484f407
DM		 64static unsigned char shutdown_timeout = 5;
65module_param(shutdown_timeout, byte, 0644);
66MODULE_PARM_DESC(shutdown_timeout, "timeout in seconds for controller shutdown");
67
b60503ba
MW		 68static int nvme_major;
69module_param(nvme_major, int, 0);
70
b3fffdef
KB		 71static int nvme_char_major;
72module_param(nvme_char_major, int, 0);
73
58ffacb5
MW		 74static int use_threaded_interrupts;
75module_param(use_threaded_interrupts, int, 0);
76
8ffaadf7
JD		 77static bool use_cmb_sqes = true;
78module_param(use_cmb_sqes, bool, 0644);
79MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
80
1fa6aead
MW		 81static DEFINE_SPINLOCK(dev_list_lock);
82static LIST_HEAD(dev_list);
83static struct task_struct *nvme_thread;
9a6b9458 84static struct workqueue_struct *nvme_workq;
b9afca3e 85static wait_queue_head_t nvme_kthread_wait;
1fa6aead 86
b3fffdef
KB		 87static struct class *nvme_class;
88
90667892 89static int __nvme_reset(struct nvme_dev *dev);
4cc06521 90static int nvme_reset(struct nvme_dev *dev);
a4aea562 91static int nvme_process_cq(struct nvme_queue *nvmeq);
3cf519b5 92static void nvme_dead_ctrl(struct nvme_dev *dev);
d4b4ff8e 93
4d115420
KB		 94struct async_cmd_info {
95 struct kthread_work work;
96 struct kthread_worker *worker;
a4aea562 97 struct request *req;
4d115420
KB		 98 u32 result;
99 int status;
100 void *ctx;
101};
1fa6aead 102
b60503ba
MW		 103/*
104 * An NVM Express queue. Each device has at least two (one for admin
105 * commands and one for I/O commands).
106 */
107struct nvme_queue {
108 struct device *q_dmadev;
091b6092 109 struct nvme_dev *dev;
3193f07b 110 char irqname[24]; /* nvme4294967295-65535\0 */
b60503ba
MW		 111 spinlock_t q_lock;
112 struct nvme_command *sq_cmds;
8ffaadf7 113 struct nvme_command __iomem *sq_cmds_io;
b60503ba 114 volatile struct nvme_completion *cqes;
42483228 115 struct blk_mq_tags **tags;
b60503ba
MW		 116 dma_addr_t sq_dma_addr;
117 dma_addr_t cq_dma_addr;
b60503ba
MW		 118 u32 __iomem *q_db;
119 u16 q_depth;
6222d172 120 s16 cq_vector;
b60503ba
MW		 121 u16 sq_head;
122 u16 sq_tail;
123 u16 cq_head;
c30341dc 124 u16 qid;
e9539f47
MW		 125 u8 cq_phase;
126 u8 cqe_seen;
4d115420 127 struct async_cmd_info cmdinfo;
b60503ba
MW		 128};
129
130/*
131 * Check we didin't inadvertently grow the command struct
132 */
133static inline void _nvme_check_size(void)
134{
135 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
136 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
137 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
138 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
139 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
f8ebf840 140 BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
c30341dc 141 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
b60503ba
MW		 142 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
143 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
144 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
145 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
6ecec745 146 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
b60503ba
MW		 147}
148
edd10d33 149typedef void (*nvme_completion_fn)(struct nvme_queue *, void *,
c2f5b650
MW		 150 struct nvme_completion *);
151
e85248e5 152struct nvme_cmd_info {
c2f5b650
MW		 153 nvme_completion_fn fn;
154 void *ctx;
c30341dc 155 int aborted;
a4aea562 156 struct nvme_queue *nvmeq;
ac3dd5bd 157 struct nvme_iod iod[0];
e85248e5
MW		 158};
159
ac3dd5bd
JA		 160/*
161 * Max size of iod being embedded in the request payload
162 */
163#define NVME_INT_PAGES 2
164#define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->page_size)
fda631ff 165#define NVME_INT_MASK 0x01
ac3dd5bd
JA		 166
167/*
168 * Will slightly overestimate the number of pages needed. This is OK
169 * as it only leads to a small amount of wasted memory for the lifetime of
170 * the I/O.
171 */
172static int nvme_npages(unsigned size, struct nvme_dev *dev)
173{
174 unsigned nprps = DIV_ROUND_UP(size + dev->page_size, dev->page_size);
175 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
176}
177
178static unsigned int nvme_cmd_size(struct nvme_dev *dev)
179{
180 unsigned int ret = sizeof(struct nvme_cmd_info);
181
182 ret += sizeof(struct nvme_iod);
183 ret += sizeof(__le64 *) * nvme_npages(NVME_INT_BYTES(dev), dev);
184 ret += sizeof(struct scatterlist) * NVME_INT_PAGES;
185
186 return ret;
187}
188
a4aea562
MB		 189static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
190 unsigned int hctx_idx)
e85248e5 191{
a4aea562
MB		 192 struct nvme_dev *dev = data;
193 struct nvme_queue *nvmeq = dev->queues[0];
194
42483228
KB		 195 WARN_ON(hctx_idx != 0);
196 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
197 WARN_ON(nvmeq->tags);
198
a4aea562 199 hctx->driver_data = nvmeq;
42483228 200 nvmeq->tags = &dev->admin_tagset.tags[0];
a4aea562 201 return 0;
e85248e5
MW		 202}
203
4af0e21c
KB		 204static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
205{
206 struct nvme_queue *nvmeq = hctx->driver_data;
207
208 nvmeq->tags = NULL;
209}
210
a4aea562
MB		 211static int nvme_admin_init_request(void *data, struct request *req,
212 unsigned int hctx_idx, unsigned int rq_idx,
213 unsigned int numa_node)
22404274 214{
a4aea562
MB		 215 struct nvme_dev *dev = data;
216 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
217 struct nvme_queue *nvmeq = dev->queues[0];
218
219 BUG_ON(!nvmeq);
220 cmd->nvmeq = nvmeq;
221 return 0;
22404274
KB		 222}
223
a4aea562
MB		 224static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
225 unsigned int hctx_idx)
b60503ba 226{
a4aea562 227 struct nvme_dev *dev = data;
42483228 228 struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
a4aea562 229
42483228
KB		 230 if (!nvmeq->tags)
231 nvmeq->tags = &dev->tagset.tags[hctx_idx];
b60503ba 232
42483228 233 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
a4aea562
MB		 234 hctx->driver_data = nvmeq;
235 return 0;
b60503ba
MW		 236}
237
a4aea562
MB		 238static int nvme_init_request(void *data, struct request *req,
239 unsigned int hctx_idx, unsigned int rq_idx,
240 unsigned int numa_node)
b60503ba 241{
a4aea562
MB		 242 struct nvme_dev *dev = data;
243 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
244 struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
245
246 BUG_ON(!nvmeq);
247 cmd->nvmeq = nvmeq;
248 return 0;
249}
250
251static void nvme_set_info(struct nvme_cmd_info *cmd, void *ctx,
252 nvme_completion_fn handler)
253{
254 cmd->fn = handler;
255 cmd->ctx = ctx;
256 cmd->aborted = 0;
c917dfe5 257 blk_mq_start_request(blk_mq_rq_from_pdu(cmd));
b60503ba
MW		 258}
259
ac3dd5bd
JA		 260static void *iod_get_private(struct nvme_iod *iod)
261{
262 return (void *) (iod->private & ~0x1UL);
263}
264
265/*
266 * If bit 0 is set, the iod is embedded in the request payload.
267 */
268static bool iod_should_kfree(struct nvme_iod *iod)
269{
fda631ff 270 return (iod->private & NVME_INT_MASK) == 0;
ac3dd5bd
JA		 271}
272
c2f5b650
MW		 273/* Special values must be less than 0x1000 */
274#define CMD_CTX_BASE ((void *)POISON_POINTER_DELTA)
d2d87034
MW		 275#define CMD_CTX_CANCELLED (0x30C + CMD_CTX_BASE)
276#define CMD_CTX_COMPLETED (0x310 + CMD_CTX_BASE)
277#define CMD_CTX_INVALID (0x314 + CMD_CTX_BASE)
be7b6275 278
edd10d33 279static void special_completion(struct nvme_queue *nvmeq, void *ctx,
c2f5b650
MW		 280 struct nvme_completion *cqe)
281{
282 if (ctx == CMD_CTX_CANCELLED)
283 return;
c2f5b650 284 if (ctx == CMD_CTX_COMPLETED) {
edd10d33 285 dev_warn(nvmeq->q_dmadev,
c2f5b650
MW		 286 "completed id %d twice on queue %d\n",
287 cqe->command_id, le16_to_cpup(&cqe->sq_id));
288 return;
289 }
290 if (ctx == CMD_CTX_INVALID) {
edd10d33 291 dev_warn(nvmeq->q_dmadev,
c2f5b650
MW		 292 "invalid id %d completed on queue %d\n",
293 cqe->command_id, le16_to_cpup(&cqe->sq_id));
294 return;
295 }
edd10d33 296 dev_warn(nvmeq->q_dmadev, "Unknown special completion %p\n", ctx);
c2f5b650
MW		 297}
298
a4aea562 299static void *cancel_cmd_info(struct nvme_cmd_info *cmd, nvme_completion_fn *fn)
b60503ba 300{
c2f5b650 301 void *ctx;
b60503ba 302
859361a2 303 if (fn)
a4aea562
MB		 304 *fn = cmd->fn;
305 ctx = cmd->ctx;
306 cmd->fn = special_completion;
307 cmd->ctx = CMD_CTX_CANCELLED;
c2f5b650 308 return ctx;
b60503ba
MW		 309}
310
a4aea562
MB		 311static void async_req_completion(struct nvme_queue *nvmeq, void *ctx,
312 struct nvme_completion *cqe)
3c0cf138 313{
a4aea562
MB		 314 u32 result = le32_to_cpup(&cqe->result);
315 u16 status = le16_to_cpup(&cqe->status) >> 1;
316
317 if (status == NVME_SC_SUCCESS || status == NVME_SC_ABORT_REQ)
318 ++nvmeq->dev->event_limit;
a5768aa8
KB		 319 if (status != NVME_SC_SUCCESS)
320 return;
321
322 switch (result & 0xff07) {
323 case NVME_AER_NOTICE_NS_CHANGED:
324 dev_info(nvmeq->q_dmadev, "rescanning\n");
325 schedule_work(&nvmeq->dev->scan_work);
326 default:
327 dev_warn(nvmeq->q_dmadev, "async event result %08x\n", result);
328 }
b60503ba
MW		 329}
330
a4aea562
MB		 331static void abort_completion(struct nvme_queue *nvmeq, void *ctx,
332 struct nvme_completion *cqe)
5a92e700 333{
a4aea562
MB		 334 struct request *req = ctx;
335
336 u16 status = le16_to_cpup(&cqe->status) >> 1;
337 u32 result = le32_to_cpup(&cqe->result);
a51afb54 338
42483228 339 blk_mq_free_request(req);
a51afb54 340
a4aea562
MB		 341 dev_warn(nvmeq->q_dmadev, "Abort status:%x result:%x", status, result);
342 ++nvmeq->dev->abort_limit;
5a92e700
KB		 343}
344
a4aea562
MB		 345static void async_completion(struct nvme_queue *nvmeq, void *ctx,
346 struct nvme_completion *cqe)
b60503ba 347{
a4aea562
MB		 348 struct async_cmd_info *cmdinfo = ctx;
349 cmdinfo->result = le32_to_cpup(&cqe->result);
350 cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
351 queue_kthread_work(cmdinfo->worker, &cmdinfo->work);
42483228 352 blk_mq_free_request(cmdinfo->req);
b60503ba
MW		 353}
354
a4aea562
MB		 355static inline struct nvme_cmd_info *get_cmd_from_tag(struct nvme_queue *nvmeq,
356 unsigned int tag)
b60503ba 357{
42483228 358 struct request *req = blk_mq_tag_to_rq(*nvmeq->tags, tag);
a51afb54 359
a4aea562 360 return blk_mq_rq_to_pdu(req);
4f5099af
KB		 361}
362
a4aea562
MB		 363/*
364 * Called with local interrupts disabled and the q_lock held. May not sleep.
365 */
366static void *nvme_finish_cmd(struct nvme_queue *nvmeq, int tag,
367 nvme_completion_fn *fn)
4f5099af 368{
a4aea562
MB		 369 struct nvme_cmd_info *cmd = get_cmd_from_tag(nvmeq, tag);
370 void *ctx;
371 if (tag >= nvmeq->q_depth) {
372 *fn = special_completion;
373 return CMD_CTX_INVALID;
374 }
375 if (fn)
376 *fn = cmd->fn;
377 ctx = cmd->ctx;
378 cmd->fn = special_completion;
379 cmd->ctx = CMD_CTX_COMPLETED;
380 return ctx;
b60503ba
MW		 381}
382
383/**
714a7a22 384 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
b60503ba
MW		 385 * @nvmeq: The queue to use
386 * @cmd: The command to send
387 *
388 * Safe to use from interrupt context
389 */
e3f879bf
SB		 390static void __nvme_submit_cmd(struct nvme_queue *nvmeq,
391 struct nvme_command *cmd)
b60503ba 392{
a4aea562
MB		 393 u16 tail = nvmeq->sq_tail;
394
8ffaadf7
JD		 395 if (nvmeq->sq_cmds_io)
396 memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd));
397 else
398 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
399
b60503ba
MW		 400 if (++tail == nvmeq->q_depth)
401 tail = 0;
7547881d 402 writel(tail, nvmeq->q_db);
b60503ba 403 nvmeq->sq_tail = tail;
b60503ba
MW		 404}
405
e3f879bf 406static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
a4aea562
MB		 407{
408 unsigned long flags;
a4aea562 409 spin_lock_irqsave(&nvmeq->q_lock, flags);
e3f879bf 410 __nvme_submit_cmd(nvmeq, cmd);
a4aea562 411 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
a4aea562
MB		 412}
413
eca18b23 414static __le64 **iod_list(struct nvme_iod *iod)
e025344c 415{
eca18b23 416 return ((void *)iod) + iod->offset;
e025344c
SMM		 417}
418
ac3dd5bd
JA		 419static inline void iod_init(struct nvme_iod *iod, unsigned nbytes,
420 unsigned nseg, unsigned long private)
eca18b23 421{
ac3dd5bd
JA		 422 iod->private = private;
423 iod->offset = offsetof(struct nvme_iod, sg[nseg]);
424 iod->npages = -1;
425 iod->length = nbytes;
426 iod->nents = 0;
eca18b23 427}
b60503ba 428
eca18b23 429static struct nvme_iod *
ac3dd5bd
JA		 430__nvme_alloc_iod(unsigned nseg, unsigned bytes, struct nvme_dev *dev,
431 unsigned long priv, gfp_t gfp)
b60503ba 432{
eca18b23 433 struct nvme_iod *iod = kmalloc(sizeof(struct nvme_iod) +
ac3dd5bd 434 sizeof(__le64 *) * nvme_npages(bytes, dev) +
eca18b23
MW		 435 sizeof(struct scatterlist) * nseg, gfp);
436
ac3dd5bd
JA		 437 if (iod)
438 iod_init(iod, bytes, nseg, priv);
eca18b23
MW		 439
440 return iod;
b60503ba
MW		 441}
442
ac3dd5bd
JA		 443static struct nvme_iod *nvme_alloc_iod(struct request *rq, struct nvme_dev *dev,
444 gfp_t gfp)
445{
446 unsigned size = !(rq->cmd_flags & REQ_DISCARD) ? blk_rq_bytes(rq) :
447 sizeof(struct nvme_dsm_range);
ac3dd5bd
JA		 448 struct nvme_iod *iod;
449
450 if (rq->nr_phys_segments <= NVME_INT_PAGES &&
451 size <= NVME_INT_BYTES(dev)) {
452 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(rq);
453
454 iod = cmd->iod;
ac3dd5bd 455 iod_init(iod, size, rq->nr_phys_segments,
fda631ff 456 (unsigned long) rq | NVME_INT_MASK);
ac3dd5bd
JA		 457 return iod;
458 }
459
460 return __nvme_alloc_iod(rq->nr_phys_segments, size, dev,
461 (unsigned long) rq, gfp);
462}
463
d29ec824 464static void nvme_free_iod(struct nvme_dev *dev, struct nvme_iod *iod)
b60503ba 465{
1d090624 466 const int last_prp = dev->page_size / 8 - 1;
eca18b23
MW		 467 int i;
468 __le64 **list = iod_list(iod);
469 dma_addr_t prp_dma = iod->first_dma;
470
471 if (iod->npages == 0)
472 dma_pool_free(dev->prp_small_pool, list[0], prp_dma);
473 for (i = 0; i < iod->npages; i++) {
474 __le64 *prp_list = list[i];
475 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
476 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
477 prp_dma = next_prp_dma;
478 }
ac3dd5bd
JA		 479
480 if (iod_should_kfree(iod))
481 kfree(iod);
b60503ba
MW		 482}
483
b4ff9c8d
KB		 484static int nvme_error_status(u16 status)
485{
486 switch (status & 0x7ff) {
487 case NVME_SC_SUCCESS:
488 return 0;
489 case NVME_SC_CAP_EXCEEDED:
490 return -ENOSPC;
491 default:
492 return -EIO;
493 }
494}
495
52b68d7e 496#ifdef CONFIG_BLK_DEV_INTEGRITY
e1e5e564
KB		 497static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
498{
499 if (be32_to_cpu(pi->ref_tag) == v)
500 pi->ref_tag = cpu_to_be32(p);
501}
502
503static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
504{
505 if (be32_to_cpu(pi->ref_tag) == p)
506 pi->ref_tag = cpu_to_be32(v);
507}
508
509/**
510 * nvme_dif_remap - remaps ref tags to bip seed and physical lba
511 *
512 * The virtual start sector is the one that was originally submitted by the
513 * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical
514 * start sector may be different. Remap protection information to match the
515 * physical LBA on writes, and back to the original seed on reads.
516 *
517 * Type 0 and 3 do not have a ref tag, so no remapping required.
518 */
519static void nvme_dif_remap(struct request *req,
520 void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
521{
522 struct nvme_ns *ns = req->rq_disk->private_data;
523 struct bio_integrity_payload *bip;
524 struct t10_pi_tuple *pi;
525 void *p, *pmap;
526 u32 i, nlb, ts, phys, virt;
527
528 if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3)
529 return;
530
531 bip = bio_integrity(req->bio);
532 if (!bip)
533 return;
534
535 pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset;
e1e5e564
KB		 536
537 p = pmap;
538 virt = bip_get_seed(bip);
539 phys = nvme_block_nr(ns, blk_rq_pos(req));
540 nlb = (blk_rq_bytes(req) >> ns->lba_shift);
541 ts = ns->disk->integrity->tuple_size;
542
543 for (i = 0; i < nlb; i++, virt++, phys++) {
544 pi = (struct t10_pi_tuple *)p;
545 dif_swap(phys, virt, pi);
546 p += ts;
547 }
548 kunmap_atomic(pmap);
549}
550
52b68d7e
KB		 551static int nvme_noop_verify(struct blk_integrity_iter *iter)
552{
553 return 0;
554}
555
556static int nvme_noop_generate(struct blk_integrity_iter *iter)
557{
558 return 0;
559}
560
561struct blk_integrity nvme_meta_noop = {
562 .name = "NVME_META_NOOP",
563 .generate_fn = nvme_noop_generate,
564 .verify_fn = nvme_noop_verify,
565};
566
567static void nvme_init_integrity(struct nvme_ns *ns)
568{
569 struct blk_integrity integrity;
570
571 switch (ns->pi_type) {
572 case NVME_NS_DPS_PI_TYPE3:
573 integrity = t10_pi_type3_crc;
574 break;
575 case NVME_NS_DPS_PI_TYPE1:
576 case NVME_NS_DPS_PI_TYPE2:
577 integrity = t10_pi_type1_crc;
578 break;
579 default:
580 integrity = nvme_meta_noop;
581 break;
582 }
583 integrity.tuple_size = ns->ms;
584 blk_integrity_register(ns->disk, &integrity);
585 blk_queue_max_integrity_segments(ns->queue, 1);
586}
587#else /* CONFIG_BLK_DEV_INTEGRITY */
588static void nvme_dif_remap(struct request *req,
589 void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
590{
591}
592static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
593{
594}
595static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
596{
597}
598static void nvme_init_integrity(struct nvme_ns *ns)
599{
600}
601#endif
602
a4aea562 603static void req_completion(struct nvme_queue *nvmeq, void *ctx,
b60503ba
MW		 604 struct nvme_completion *cqe)
605{
eca18b23 606 struct nvme_iod *iod = ctx;
ac3dd5bd 607 struct request *req = iod_get_private(iod);
a4aea562
MB		 608 struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req);
609
b60503ba
MW		 610 u16 status = le16_to_cpup(&cqe->status) >> 1;
611
edd10d33 612 if (unlikely(status)) {
a4aea562
MB		 613 if (!(status & NVME_SC_DNR || blk_noretry_request(req))
614 && (jiffies - req->start_time) < req->timeout) {
c9d3bf88
KB		 615 unsigned long flags;
616
a4aea562 617 blk_mq_requeue_request(req);
c9d3bf88
KB		 618 spin_lock_irqsave(req->q->queue_lock, flags);
619 if (!blk_queue_stopped(req->q))
620 blk_mq_kick_requeue_list(req->q);
621 spin_unlock_irqrestore(req->q->queue_lock, flags);
edd10d33
KB		 622 return;
623 }
f4829a9b 624
d29ec824 625 if (req->cmd_type == REQ_TYPE_DRV_PRIV) {
17188bb4 626 if (cmd_rq->ctx == CMD_CTX_CANCELLED)
f4829a9b 627 status = -EINTR;
d29ec824 628 } else {
f4829a9b 629 status = nvme_error_status(status);
d29ec824 630 }
f4829a9b
CH		 631 }
632
a0a931d6
KB		 633 if (req->cmd_type == REQ_TYPE_DRV_PRIV) {
634 u32 result = le32_to_cpup(&cqe->result);
635 req->special = (void *)(uintptr_t)result;
636 }
a4aea562
MB		 637
638 if (cmd_rq->aborted)
e75ec752 639 dev_warn(nvmeq->dev->dev,
a4aea562
MB		 640 "completing aborted command with status:%04x\n",
641 status);
642
e1e5e564 643 if (iod->nents) {
e75ec752 644 dma_unmap_sg(nvmeq->dev->dev, iod->sg, iod->nents,
a4aea562 645 rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
e1e5e564
KB		 646 if (blk_integrity_rq(req)) {
647 if (!rq_data_dir(req))
648 nvme_dif_remap(req, nvme_dif_complete);
e75ec752 649 dma_unmap_sg(nvmeq->dev->dev, iod->meta_sg, 1,
e1e5e564
KB		 650 rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
651 }
652 }
edd10d33 653 nvme_free_iod(nvmeq->dev, iod);
3291fa57 654
f4829a9b 655 blk_mq_complete_request(req, status);
b60503ba
MW		 656}
657
184d2944 658/* length is in bytes. gfp flags indicates whether we may sleep. */
d29ec824
CH		 659static int nvme_setup_prps(struct nvme_dev *dev, struct nvme_iod *iod,
660 int total_len, gfp_t gfp)
ff22b54f 661{
99802a7a 662 struct dma_pool *pool;
eca18b23
MW		 663 int length = total_len;
664 struct scatterlist *sg = iod->sg;
ff22b54f
MW		 665 int dma_len = sg_dma_len(sg);
666 u64 dma_addr = sg_dma_address(sg);
f137e0f1
MI		 667 u32 page_size = dev->page_size;
668 int offset = dma_addr & (page_size - 1);
e025344c 669 __le64 *prp_list;
eca18b23 670 __le64 **list = iod_list(iod);
e025344c 671 dma_addr_t prp_dma;
eca18b23 672 int nprps, i;
ff22b54f 673
1d090624 674 length -= (page_size - offset);
ff22b54f 675 if (length <= 0)
eca18b23 676 return total_len;
ff22b54f 677
1d090624 678 dma_len -= (page_size - offset);
ff22b54f 679 if (dma_len) {
1d090624 680 dma_addr += (page_size - offset);
ff22b54f
MW		 681 } else {
682 sg = sg_next(sg);
683 dma_addr = sg_dma_address(sg);
684 dma_len = sg_dma_len(sg);
685 }
686
1d090624 687 if (length <= page_size) {
edd10d33 688 iod->first_dma = dma_addr;
eca18b23 689 return total_len;
e025344c
SMM		 690 }
691
1d090624 692 nprps = DIV_ROUND_UP(length, page_size);
99802a7a
MW		 693 if (nprps <= (256 / 8)) {
694 pool = dev->prp_small_pool;
eca18b23 695 iod->npages = 0;
99802a7a
MW		 696 } else {
697 pool = dev->prp_page_pool;
eca18b23 698 iod->npages = 1;
99802a7a
MW		 699 }
700
b77954cb
MW		 701 prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
702 if (!prp_list) {
edd10d33 703 iod->first_dma = dma_addr;
eca18b23 704 iod->npages = -1;
1d090624 705 return (total_len - length) + page_size;
b77954cb 706 }
eca18b23
MW		 707 list[0] = prp_list;
708 iod->first_dma = prp_dma;
e025344c
SMM		 709 i = 0;
710 for (;;) {
1d090624 711 if (i == page_size >> 3) {
e025344c 712 __le64 *old_prp_list = prp_list;
b77954cb 713 prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
eca18b23
MW		 714 if (!prp_list)
715 return total_len - length;
716 list[iod->npages++] = prp_list;
7523d834
MW		 717 prp_list[0] = old_prp_list[i - 1];
718 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
719 i = 1;
e025344c
SMM		 720 }
721 prp_list[i++] = cpu_to_le64(dma_addr);
1d090624
KB		 722 dma_len -= page_size;
723 dma_addr += page_size;
724 length -= page_size;
e025344c
SMM		 725 if (length <= 0)
726 break;
727 if (dma_len > 0)
728 continue;
729 BUG_ON(dma_len < 0);
730 sg = sg_next(sg);
731 dma_addr = sg_dma_address(sg);
732 dma_len = sg_dma_len(sg);
ff22b54f
MW		 733 }
734
eca18b23 735 return total_len;
ff22b54f
MW		 736}
737
d29ec824
CH		 738static void nvme_submit_priv(struct nvme_queue *nvmeq, struct request *req,
739 struct nvme_iod *iod)
740{
498c4394 741 struct nvme_command cmnd;
d29ec824 742
498c4394
JD		 743 memcpy(&cmnd, req->cmd, sizeof(cmnd));
744 cmnd.rw.command_id = req->tag;
d29ec824 745 if (req->nr_phys_segments) {
498c4394
JD		 746 cmnd.rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
747 cmnd.rw.prp2 = cpu_to_le64(iod->first_dma);
d29ec824
CH		 748 }
749
498c4394 750 __nvme_submit_cmd(nvmeq, &cmnd);
d29ec824
CH		 751}
752
a4aea562
MB		 753/*
754 * We reuse the small pool to allocate the 16-byte range here as it is not
755 * worth having a special pool for these or additional cases to handle freeing
756 * the iod.
757 */
758static void nvme_submit_discard(struct nvme_queue *nvmeq, struct nvme_ns *ns,
759 struct request *req, struct nvme_iod *iod)
0e5e4f0e 760{
edd10d33
KB		 761 struct nvme_dsm_range *range =
762 (struct nvme_dsm_range *)iod_list(iod)[0];
498c4394 763 struct nvme_command cmnd;
0e5e4f0e 764
0e5e4f0e 765 range->cattr = cpu_to_le32(0);
a4aea562
MB		 766 range->nlb = cpu_to_le32(blk_rq_bytes(req) >> ns->lba_shift);
767 range->slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
0e5e4f0e 768
498c4394
JD		 769 memset(&cmnd, 0, sizeof(cmnd));
770 cmnd.dsm.opcode = nvme_cmd_dsm;
771 cmnd.dsm.command_id = req->tag;
772 cmnd.dsm.nsid = cpu_to_le32(ns->ns_id);
773 cmnd.dsm.prp1 = cpu_to_le64(iod->first_dma);
774 cmnd.dsm.nr = 0;
775 cmnd.dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD);
0e5e4f0e 776
498c4394 777 __nvme_submit_cmd(nvmeq, &cmnd);
0e5e4f0e
KB		 778}
779
a4aea562 780static void nvme_submit_flush(struct nvme_queue *nvmeq, struct nvme_ns *ns,
00df5cb4
MW		 781 int cmdid)
782{
498c4394 783 struct nvme_command cmnd;
00df5cb4 784
498c4394
JD		 785 memset(&cmnd, 0, sizeof(cmnd));
786 cmnd.common.opcode = nvme_cmd_flush;
787 cmnd.common.command_id = cmdid;
788 cmnd.common.nsid = cpu_to_le32(ns->ns_id);
00df5cb4 789
498c4394 790 __nvme_submit_cmd(nvmeq, &cmnd);
00df5cb4
MW		 791}
792
a4aea562
MB		 793static int nvme_submit_iod(struct nvme_queue *nvmeq, struct nvme_iod *iod,
794 struct nvme_ns *ns)
b60503ba 795{
ac3dd5bd 796 struct request *req = iod_get_private(iod);
498c4394 797 struct nvme_command cmnd;
a4aea562
MB		 798 u16 control = 0;
799 u32 dsmgmt = 0;
00df5cb4 800
a4aea562 801 if (req->cmd_flags & REQ_FUA)
b60503ba 802 control |= NVME_RW_FUA;
a4aea562 803 if (req->cmd_flags & (REQ_FAILFAST_DEV | REQ_RAHEAD))
b60503ba
MW		 804 control |= NVME_RW_LR;
805
a4aea562 806 if (req->cmd_flags & REQ_RAHEAD)
b60503ba
MW		 807 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
808
498c4394
JD		 809 memset(&cmnd, 0, sizeof(cmnd));
810 cmnd.rw.opcode = (rq_data_dir(req) ? nvme_cmd_write : nvme_cmd_read);
811 cmnd.rw.command_id = req->tag;
812 cmnd.rw.nsid = cpu_to_le32(ns->ns_id);
813 cmnd.rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
814 cmnd.rw.prp2 = cpu_to_le64(iod->first_dma);
815 cmnd.rw.slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
816 cmnd.rw.length = cpu_to_le16((blk_rq_bytes(req) >> ns->lba_shift) - 1);
b60503ba 817
e19b127f 818 if (ns->ms) {
e1e5e564
KB		 819 switch (ns->pi_type) {
820 case NVME_NS_DPS_PI_TYPE3:
821 control |= NVME_RW_PRINFO_PRCHK_GUARD;
822 break;
823 case NVME_NS_DPS_PI_TYPE1:
824 case NVME_NS_DPS_PI_TYPE2:
825 control |= NVME_RW_PRINFO_PRCHK_GUARD |
826 NVME_RW_PRINFO_PRCHK_REF;
498c4394 827 cmnd.rw.reftag = cpu_to_le32(
e1e5e564
KB		 828 nvme_block_nr(ns, blk_rq_pos(req)));
829 break;
830 }
e19b127f
AP		 831 if (blk_integrity_rq(req))
832 cmnd.rw.metadata =
833 cpu_to_le64(sg_dma_address(iod->meta_sg));
834 else
835 control |= NVME_RW_PRINFO_PRACT;
836 }
e1e5e564 837
498c4394
JD		 838 cmnd.rw.control = cpu_to_le16(control);
839 cmnd.rw.dsmgmt = cpu_to_le32(dsmgmt);
b60503ba 840
498c4394 841 __nvme_submit_cmd(nvmeq, &cmnd);
b60503ba 842
1974b1ae 843 return 0;
edd10d33
KB		 844}
845
d29ec824
CH		 846/*
847 * NOTE: ns is NULL when called on the admin queue.
848 */
a4aea562
MB		 849static int nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
850 const struct blk_mq_queue_data *bd)
edd10d33 851{
a4aea562
MB		 852 struct nvme_ns *ns = hctx->queue->queuedata;
853 struct nvme_queue *nvmeq = hctx->driver_data;
d29ec824 854 struct nvme_dev *dev = nvmeq->dev;
a4aea562
MB		 855 struct request *req = bd->rq;
856 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
edd10d33 857 struct nvme_iod *iod;
a4aea562 858 enum dma_data_direction dma_dir;
edd10d33 859
e1e5e564
KB		 860 /*
861 * If formated with metadata, require the block layer provide a buffer
862 * unless this namespace is formated such that the metadata can be
863 * stripped/generated by the controller with PRACT=1.
864 */
d29ec824 865 if (ns && ns->ms && !blk_integrity_rq(req)) {
71feb364
KB		 866 if (!(ns->pi_type && ns->ms == 8) &&
867 req->cmd_type != REQ_TYPE_DRV_PRIV) {
f4829a9b 868 blk_mq_complete_request(req, -EFAULT);
e1e5e564
KB		 869 return BLK_MQ_RQ_QUEUE_OK;
870 }
871 }
872
d29ec824 873 iod = nvme_alloc_iod(req, dev, GFP_ATOMIC);
edd10d33 874 if (!iod)
fe54303e 875 return BLK_MQ_RQ_QUEUE_BUSY;
a4aea562 876
a4aea562 877 if (req->cmd_flags & REQ_DISCARD) {
edd10d33
KB		 878 void *range;
879 /*
880 * We reuse the small pool to allocate the 16-byte range here
881 * as it is not worth having a special pool for these or
882 * additional cases to handle freeing the iod.
883 */
d29ec824 884 range = dma_pool_alloc(dev->prp_small_pool, GFP_ATOMIC,
edd10d33 885 &iod->first_dma);
a4aea562 886 if (!range)
fe54303e 887 goto retry_cmd;
edd10d33
KB		 888 iod_list(iod)[0] = (__le64 *)range;
889 iod->npages = 0;
ac3dd5bd 890 } else if (req->nr_phys_segments) {
a4aea562
MB		 891 dma_dir = rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
892
ac3dd5bd 893 sg_init_table(iod->sg, req->nr_phys_segments);
a4aea562 894 iod->nents = blk_rq_map_sg(req->q, req, iod->sg);
fe54303e
JA		 895 if (!iod->nents)
896 goto error_cmd;
a4aea562
MB		 897
898 if (!dma_map_sg(nvmeq->q_dmadev, iod->sg, iod->nents, dma_dir))
fe54303e 899 goto retry_cmd;
a4aea562 900
fe54303e 901 if (blk_rq_bytes(req) !=
d29ec824
CH		 902 nvme_setup_prps(dev, iod, blk_rq_bytes(req), GFP_ATOMIC)) {
903 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
fe54303e
JA		 904 goto retry_cmd;
905 }
e1e5e564
KB		 906 if (blk_integrity_rq(req)) {
907 if (blk_rq_count_integrity_sg(req->q, req->bio) != 1)
908 goto error_cmd;
909
910 sg_init_table(iod->meta_sg, 1);
911 if (blk_rq_map_integrity_sg(
912 req->q, req->bio, iod->meta_sg) != 1)
913 goto error_cmd;
914
915 if (rq_data_dir(req))
916 nvme_dif_remap(req, nvme_dif_prep);
917
918 if (!dma_map_sg(nvmeq->q_dmadev, iod->meta_sg, 1, dma_dir))
919 goto error_cmd;
920 }
edd10d33 921 }
1974b1ae 922
9af8785a 923 nvme_set_info(cmd, iod, req_completion);
a4aea562 924 spin_lock_irq(&nvmeq->q_lock);
d29ec824
CH		 925 if (req->cmd_type == REQ_TYPE_DRV_PRIV)
926 nvme_submit_priv(nvmeq, req, iod);
927 else if (req->cmd_flags & REQ_DISCARD)
a4aea562
MB		 928 nvme_submit_discard(nvmeq, ns, req, iod);
929 else if (req->cmd_flags & REQ_FLUSH)
930 nvme_submit_flush(nvmeq, ns, req->tag);
931 else
932 nvme_submit_iod(nvmeq, iod, ns);
933
934 nvme_process_cq(nvmeq);
935 spin_unlock_irq(&nvmeq->q_lock);
936 return BLK_MQ_RQ_QUEUE_OK;
937
fe54303e 938 error_cmd:
d29ec824 939 nvme_free_iod(dev, iod);
fe54303e
JA		 940 return BLK_MQ_RQ_QUEUE_ERROR;
941 retry_cmd:
d29ec824 942 nvme_free_iod(dev, iod);
fe54303e 943 return BLK_MQ_RQ_QUEUE_BUSY;
b60503ba
MW		 944}
945
e9539f47 946static int nvme_process_cq(struct nvme_queue *nvmeq)
b60503ba 947{
82123460 948 u16 head, phase;
b60503ba 949
b60503ba 950 head = nvmeq->cq_head;
82123460 951 phase = nvmeq->cq_phase;
b60503ba
MW		 952
953 for (;;) {
c2f5b650
MW		 954 void *ctx;
955 nvme_completion_fn fn;
b60503ba 956 struct nvme_completion cqe = nvmeq->cqes[head];
82123460 957 if ((le16_to_cpu(cqe.status) & 1) != phase)
b60503ba
MW		 958 break;
959 nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
960 if (++head == nvmeq->q_depth) {
961 head = 0;
82123460 962 phase = !phase;
b60503ba 963 }
a4aea562 964 ctx = nvme_finish_cmd(nvmeq, cqe.command_id, &fn);
edd10d33 965 fn(nvmeq, ctx, &cqe);
b60503ba
MW		 966 }
967
968 /* If the controller ignores the cq head doorbell and continuously
969 * writes to the queue, it is theoretically possible to wrap around
970 * the queue twice and mistakenly return IRQ_NONE. Linux only
971 * requires that 0.1% of your interrupts are handled, so this isn't
972 * a big problem.
973 */
82123460 974 if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
e9539f47 975 return 0;
b60503ba 976
b80d5ccc 977 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
b60503ba 978 nvmeq->cq_head = head;
82123460 979 nvmeq->cq_phase = phase;
b60503ba 980
e9539f47
MW		 981 nvmeq->cqe_seen = 1;
982 return 1;
b60503ba
MW		 983}
984
985static irqreturn_t nvme_irq(int irq, void *data)
58ffacb5
MW		 986{
987 irqreturn_t result;
988 struct nvme_queue *nvmeq = data;
989 spin_lock(&nvmeq->q_lock);
e9539f47
MW		 990 nvme_process_cq(nvmeq);
991 result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE;
992 nvmeq->cqe_seen = 0;
58ffacb5
MW		 993 spin_unlock(&nvmeq->q_lock);
994 return result;
995}
996
997static irqreturn_t nvme_irq_check(int irq, void *data)
998{
999 struct nvme_queue *nvmeq = data;
1000 struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head];
1001 if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase)
1002 return IRQ_NONE;
1003 return IRQ_WAKE_THREAD;
1004}
1005
b60503ba
MW		 1006/*
1007 * Returns 0 on success. If the result is negative, it's a Linux error code;
1008 * if the result is positive, it's an NVM Express status code
1009 */
d29ec824
CH		 1010int __nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
1011 void *buffer, void __user *ubuffer, unsigned bufflen,
1012 u32 *result, unsigned timeout)
b60503ba 1013{
d29ec824
CH		 1014 bool write = cmd->common.opcode & 1;
1015 struct bio *bio = NULL;
f705f837 1016 struct request *req;
d29ec824 1017 int ret;
b60503ba 1018
d29ec824 1019 req = blk_mq_alloc_request(q, write, GFP_KERNEL, false);
f705f837
CH		 1020 if (IS_ERR(req))
1021 return PTR_ERR(req);
b60503ba 1022
d29ec824 1023 req->cmd_type = REQ_TYPE_DRV_PRIV;
e112af0d 1024 req->cmd_flags |= REQ_FAILFAST_DRIVER;
d29ec824
CH		 1025 req->__data_len = 0;
1026 req->__sector = (sector_t) -1;
1027 req->bio = req->biotail = NULL;
b60503ba 1028
f4ff414a 1029 req->timeout = timeout ? timeout : ADMIN_TIMEOUT;
a4aea562 1030
d29ec824
CH		 1031 req->cmd = (unsigned char *)cmd;
1032 req->cmd_len = sizeof(struct nvme_command);
a0a931d6 1033 req->special = (void *)0;
b60503ba 1034
d29ec824
CH		 1035 if (buffer && bufflen) {
1036 ret = blk_rq_map_kern(q, req, buffer, bufflen, __GFP_WAIT);
1037 if (ret)
1038 goto out;
1039 } else if (ubuffer && bufflen) {
1040 ret = blk_rq_map_user(q, req, NULL, ubuffer, bufflen, __GFP_WAIT);
1041 if (ret)
1042 goto out;
1043 bio = req->bio;
1044 }
3c0cf138 1045
d29ec824
CH		 1046 blk_execute_rq(req->q, NULL, req, 0);
1047 if (bio)
1048 blk_rq_unmap_user(bio);
b60503ba 1049 if (result)
a0a931d6 1050 *result = (u32)(uintptr_t)req->special;
d29ec824
CH		 1051 ret = req->errors;
1052 out:
f705f837 1053 blk_mq_free_request(req);
d29ec824 1054 return ret;
f705f837
CH		 1055}
1056
d29ec824
CH		 1057int nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
1058 void *buffer, unsigned bufflen)
f705f837 1059{
d29ec824 1060 return __nvme_submit_sync_cmd(q, cmd, buffer, NULL, bufflen, NULL, 0);
b60503ba
MW		 1061}
1062
a4aea562
MB		 1063static int nvme_submit_async_admin_req(struct nvme_dev *dev)
1064{
1065 struct nvme_queue *nvmeq = dev->queues[0];
1066 struct nvme_command c;
1067 struct nvme_cmd_info *cmd_info;
1068 struct request *req;
1069
1efccc9d 1070 req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_ATOMIC, true);
9f173b33
DC		 1071 if (IS_ERR(req))
1072 return PTR_ERR(req);
a4aea562 1073
c917dfe5 1074 req->cmd_flags |= REQ_NO_TIMEOUT;
a4aea562 1075 cmd_info = blk_mq_rq_to_pdu(req);
1efccc9d 1076 nvme_set_info(cmd_info, NULL, async_req_completion);
a4aea562
MB		 1077
1078 memset(&c, 0, sizeof(c));
1079 c.common.opcode = nvme_admin_async_event;
1080 c.common.command_id = req->tag;
1081
42483228 1082 blk_mq_free_request(req);
e3f879bf
SB		 1083 __nvme_submit_cmd(nvmeq, &c);
1084 return 0;
a4aea562
MB		 1085}
1086
1087static int nvme_submit_admin_async_cmd(struct nvme_dev *dev,
4d115420
KB		 1088 struct nvme_command *cmd,
1089 struct async_cmd_info *cmdinfo, unsigned timeout)
1090{
a4aea562
MB		 1091 struct nvme_queue *nvmeq = dev->queues[0];
1092 struct request *req;
1093 struct nvme_cmd_info *cmd_rq;
4d115420 1094
a4aea562 1095 req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_KERNEL, false);
9f173b33
DC		 1096 if (IS_ERR(req))
1097 return PTR_ERR(req);
a4aea562
MB		 1098
1099 req->timeout = timeout;
1100 cmd_rq = blk_mq_rq_to_pdu(req);
1101 cmdinfo->req = req;
1102 nvme_set_info(cmd_rq, cmdinfo, async_completion);
4d115420 1103 cmdinfo->status = -EINTR;
a4aea562
MB		 1104
1105 cmd->common.command_id = req->tag;
1106
e3f879bf
SB		 1107 nvme_submit_cmd(nvmeq, cmd);
1108 return 0;
4d115420
KB		 1109}
1110
b60503ba
MW		 1111static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
1112{
b60503ba
MW		 1113 struct nvme_command c;
1114
1115 memset(&c, 0, sizeof(c));
1116 c.delete_queue.opcode = opcode;
1117 c.delete_queue.qid = cpu_to_le16(id);
1118
d29ec824 1119 return nvme_submit_sync_cmd(dev->admin_q, &c, NULL, 0);
b60503ba
MW		 1120}
1121
1122static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
1123 struct nvme_queue *nvmeq)
1124{
b60503ba
MW		 1125 struct nvme_command c;
1126 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
1127
d29ec824
CH		 1128 /*
1129 * Note: we (ab)use the fact the the prp fields survive if no data
1130 * is attached to the request.
1131 */
b60503ba
MW		 1132 memset(&c, 0, sizeof(c));
1133 c.create_cq.opcode = nvme_admin_create_cq;
1134 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1135 c.create_cq.cqid = cpu_to_le16(qid);
1136 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1137 c.create_cq.cq_flags = cpu_to_le16(flags);
1138 c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
1139
d29ec824 1140 return nvme_submit_sync_cmd(dev->admin_q, &c, NULL, 0);
b60503ba
MW		 1141}
1142
1143static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1144 struct nvme_queue *nvmeq)
1145{
b60503ba
MW		 1146 struct nvme_command c;
1147 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
1148
d29ec824
CH		 1149 /*
1150 * Note: we (ab)use the fact the the prp fields survive if no data
1151 * is attached to the request.
1152 */
b60503ba
MW		 1153 memset(&c, 0, sizeof(c));
1154 c.create_sq.opcode = nvme_admin_create_sq;
1155 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1156 c.create_sq.sqid = cpu_to_le16(qid);
1157 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1158 c.create_sq.sq_flags = cpu_to_le16(flags);
1159 c.create_sq.cqid = cpu_to_le16(qid);
1160
d29ec824 1161 return nvme_submit_sync_cmd(dev->admin_q, &c, NULL, 0);
b60503ba
MW		 1162}
1163
1164static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1165{
1166 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1167}
1168
1169static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1170{
1171 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1172}
1173
d29ec824 1174int nvme_identify_ctrl(struct nvme_dev *dev, struct nvme_id_ctrl **id)
bc5fc7e4 1175{
e44ac588 1176 struct nvme_command c = { };
d29ec824 1177 int error;
bc5fc7e4 1178
e44ac588
AM		 1179 /* gcc-4.4.4 (at least) has issues with initializers and anon unions */
1180 c.identify.opcode = nvme_admin_identify;
1181 c.identify.cns = cpu_to_le32(1);
1182
d29ec824
CH		 1183 *id = kmalloc(sizeof(struct nvme_id_ctrl), GFP_KERNEL);
1184 if (!*id)
1185 return -ENOMEM;
bc5fc7e4 1186
d29ec824
CH		 1187 error = nvme_submit_sync_cmd(dev->admin_q, &c, *id,
1188 sizeof(struct nvme_id_ctrl));
1189 if (error)
1190 kfree(*id);
1191 return error;
1192}
1193
1194int nvme_identify_ns(struct nvme_dev *dev, unsigned nsid,
1195 struct nvme_id_ns **id)
1196{
e44ac588 1197 struct nvme_command c = { };
d29ec824 1198 int error;
bc5fc7e4 1199
e44ac588
AM		 1200 /* gcc-4.4.4 (at least) has issues with initializers and anon unions */
1201 c.identify.opcode = nvme_admin_identify,
1202 c.identify.nsid = cpu_to_le32(nsid),
1203
d29ec824
CH		 1204 *id = kmalloc(sizeof(struct nvme_id_ns), GFP_KERNEL);
1205 if (!*id)
1206 return -ENOMEM;
1207
1208 error = nvme_submit_sync_cmd(dev->admin_q, &c, *id,
1209 sizeof(struct nvme_id_ns));
1210 if (error)
1211 kfree(*id);
1212 return error;
bc5fc7e4
MW		 1213}
1214
5d0f6131 1215int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid,
08df1e05 1216 dma_addr_t dma_addr, u32 *result)
bc5fc7e4
MW		 1217{
1218 struct nvme_command c;
1219
1220 memset(&c, 0, sizeof(c));
1221 c.features.opcode = nvme_admin_get_features;
a42cecce 1222 c.features.nsid = cpu_to_le32(nsid);
bc5fc7e4
MW		 1223 c.features.prp1 = cpu_to_le64(dma_addr);
1224 c.features.fid = cpu_to_le32(fid);
bc5fc7e4 1225
d29ec824
CH		 1226 return __nvme_submit_sync_cmd(dev->admin_q, &c, NULL, NULL, 0,
1227 result, 0);
df348139
MW		 1228}
1229
5d0f6131
VV		 1230int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11,
1231 dma_addr_t dma_addr, u32 *result)
df348139
MW		 1232{
1233 struct nvme_command c;
1234
1235 memset(&c, 0, sizeof(c));
1236 c.features.opcode = nvme_admin_set_features;
1237 c.features.prp1 = cpu_to_le64(dma_addr);
1238 c.features.fid = cpu_to_le32(fid);
1239 c.features.dword11 = cpu_to_le32(dword11);
1240
d29ec824
CH		 1241 return __nvme_submit_sync_cmd(dev->admin_q, &c, NULL, NULL, 0,
1242 result, 0);
1243}
1244
1245int nvme_get_log_page(struct nvme_dev *dev, struct nvme_smart_log **log)
1246{
e44ac588
AM		 1247 struct nvme_command c = { };
1248 int error;
1249
1250 c.common.opcode = nvme_admin_get_log_page,
1251 c.common.nsid = cpu_to_le32(0xFFFFFFFF),
1252 c.common.cdw10[0] = cpu_to_le32(
d29ec824
CH		 1253 (((sizeof(struct nvme_smart_log) / 4) - 1) << 16) |
1254 NVME_LOG_SMART),
d29ec824
CH		 1255
1256 *log = kmalloc(sizeof(struct nvme_smart_log), GFP_KERNEL);
1257 if (!*log)
1258 return -ENOMEM;
1259
1260 error = nvme_submit_sync_cmd(dev->admin_q, &c, *log,
1261 sizeof(struct nvme_smart_log));
1262 if (error)
1263 kfree(*log);
1264 return error;
bc5fc7e4
MW		 1265}
1266
c30341dc 1267/**
a4aea562 1268 * nvme_abort_req - Attempt aborting a request
c30341dc
KB		 1269 *
1270 * Schedule controller reset if the command was already aborted once before and
1271 * still hasn't been returned to the driver, or if this is the admin queue.
1272 */
a4aea562 1273static void nvme_abort_req(struct request *req)
c30341dc 1274{
a4aea562
MB		 1275 struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req);
1276 struct nvme_queue *nvmeq = cmd_rq->nvmeq;
c30341dc 1277 struct nvme_dev *dev = nvmeq->dev;
a4aea562
MB		 1278 struct request *abort_req;
1279 struct nvme_cmd_info *abort_cmd;
1280 struct nvme_command cmd;
c30341dc 1281
a4aea562 1282 if (!nvmeq->qid || cmd_rq->aborted) {
90667892
CH		 1283 spin_lock(&dev_list_lock);
1284 if (!__nvme_reset(dev)) {
1285 dev_warn(dev->dev,
1286 "I/O %d QID %d timeout, reset controller\n",
1287 req->tag, nvmeq->qid);
1288 }
1289 spin_unlock(&dev_list_lock);
c30341dc
KB		 1290 return;
1291 }
1292
1293 if (!dev->abort_limit)
1294 return;
1295
a4aea562
MB		 1296 abort_req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_ATOMIC,
1297 false);
9f173b33 1298 if (IS_ERR(abort_req))
c30341dc
KB		 1299 return;
1300
a4aea562
MB		 1301 abort_cmd = blk_mq_rq_to_pdu(abort_req);
1302 nvme_set_info(abort_cmd, abort_req, abort_completion);
1303
c30341dc
KB		 1304 memset(&cmd, 0, sizeof(cmd));
1305 cmd.abort.opcode = nvme_admin_abort_cmd;
a4aea562 1306 cmd.abort.cid = req->tag;
c30341dc 1307 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
a4aea562 1308 cmd.abort.command_id = abort_req->tag;
c30341dc
KB		 1309
1310 --dev->abort_limit;
a4aea562 1311 cmd_rq->aborted = 1;
c30341dc 1312
a4aea562 1313 dev_warn(nvmeq->q_dmadev, "Aborting I/O %d QID %d\n", req->tag,
c30341dc 1314 nvmeq->qid);
e3f879bf 1315 nvme_submit_cmd(dev->queues[0], &cmd);
c30341dc
KB		 1316}
1317
42483228 1318static void nvme_cancel_queue_ios(struct request *req, void *data, bool reserved)
a09115b2 1319{
a4aea562
MB		 1320 struct nvme_queue *nvmeq = data;
1321 void *ctx;
1322 nvme_completion_fn fn;
1323 struct nvme_cmd_info *cmd;
cef6a948
KB		 1324 struct nvme_completion cqe;
1325
1326 if (!blk_mq_request_started(req))
1327 return;
a09115b2 1328
a4aea562 1329 cmd = blk_mq_rq_to_pdu(req);
a09115b2 1330
a4aea562
MB		 1331 if (cmd->ctx == CMD_CTX_CANCELLED)
1332 return;
1333
cef6a948
KB		 1334 if (blk_queue_dying(req->q))
1335 cqe.status = cpu_to_le16((NVME_SC_ABORT_REQ | NVME_SC_DNR) << 1);
1336 else
1337 cqe.status = cpu_to_le16(NVME_SC_ABORT_REQ << 1);
1338
1339
a4aea562
MB		 1340 dev_warn(nvmeq->q_dmadev, "Cancelling I/O %d QID %d\n",
1341 req->tag, nvmeq->qid);
1342 ctx = cancel_cmd_info(cmd, &fn);
1343 fn(nvmeq, ctx, &cqe);
a09115b2
MW		 1344}
1345
a4aea562 1346static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
9e866774 1347{
a4aea562
MB		 1348 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
1349 struct nvme_queue *nvmeq = cmd->nvmeq;
1350
1351 dev_warn(nvmeq->q_dmadev, "Timeout I/O %d QID %d\n", req->tag,
1352 nvmeq->qid);
7a509a6b 1353 spin_lock_irq(&nvmeq->q_lock);
07836e65 1354 nvme_abort_req(req);
7a509a6b 1355 spin_unlock_irq(&nvmeq->q_lock);
a4aea562 1356
07836e65
KB		 1357 /*
1358 * The aborted req will be completed on receiving the abort req.
1359 * We enable the timer again. If hit twice, it'll cause a device reset,
1360 * as the device then is in a faulty state.
1361 */
1362 return BLK_EH_RESET_TIMER;
a4aea562 1363}
22404274 1364
a4aea562
MB		 1365static void nvme_free_queue(struct nvme_queue *nvmeq)
1366{
9e866774
MW		 1367 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1368 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
8ffaadf7
JD		 1369 if (nvmeq->sq_cmds)
1370 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
9e866774
MW		 1371 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1372 kfree(nvmeq);
1373}
1374
a1a5ef99 1375static void nvme_free_queues(struct nvme_dev *dev, int lowest)
22404274
KB		 1376{
1377 int i;
1378
a1a5ef99 1379 for (i = dev->queue_count - 1; i >= lowest; i--) {
a4aea562 1380 struct nvme_queue *nvmeq = dev->queues[i];
22404274 1381 dev->queue_count--;
a4aea562 1382 dev->queues[i] = NULL;
f435c282 1383 nvme_free_queue(nvmeq);
121c7ad4 1384 }
22404274
KB		 1385}
1386
4d115420
KB		 1387/**
1388 * nvme_suspend_queue - put queue into suspended state
1389 * @nvmeq - queue to suspend
4d115420
KB		 1390 */
1391static int nvme_suspend_queue(struct nvme_queue *nvmeq)
b60503ba 1392{
2b25d981 1393 int vector;
b60503ba 1394
a09115b2 1395 spin_lock_irq(&nvmeq->q_lock);
2b25d981
KB		 1396 if (nvmeq->cq_vector == -1) {
1397 spin_unlock_irq(&nvmeq->q_lock);
1398 return 1;
1399 }
1400 vector = nvmeq->dev->entry[nvmeq->cq_vector].vector;
42f61420 1401 nvmeq->dev->online_queues--;
2b25d981 1402 nvmeq->cq_vector = -1;
a09115b2
MW		 1403 spin_unlock_irq(&nvmeq->q_lock);
1404
6df3dbc8
KB		 1405 if (!nvmeq->qid && nvmeq->dev->admin_q)
1406 blk_mq_freeze_queue_start(nvmeq->dev->admin_q);
1407
aba2080f
MW		 1408 irq_set_affinity_hint(vector, NULL);
1409 free_irq(vector, nvmeq);
b60503ba 1410
4d115420
KB		 1411 return 0;
1412}
b60503ba 1413
4d115420
KB		 1414static void nvme_clear_queue(struct nvme_queue *nvmeq)
1415{
22404274 1416 spin_lock_irq(&nvmeq->q_lock);
42483228
KB		 1417 if (nvmeq->tags && *nvmeq->tags)
1418 blk_mq_all_tag_busy_iter(*nvmeq->tags, nvme_cancel_queue_ios, nvmeq);
22404274 1419 spin_unlock_irq(&nvmeq->q_lock);
b60503ba
MW		 1420}
1421
4d115420
KB		 1422static void nvme_disable_queue(struct nvme_dev *dev, int qid)
1423{
a4aea562 1424 struct nvme_queue *nvmeq = dev->queues[qid];
4d115420
KB		 1425
1426 if (!nvmeq)
1427 return;
1428 if (nvme_suspend_queue(nvmeq))
1429 return;
1430
0e53d180
KB		 1431 /* Don't tell the adapter to delete the admin queue.
1432 * Don't tell a removed adapter to delete IO queues. */
1433 if (qid && readl(&dev->bar->csts) != -1) {
b60503ba
MW		 1434 adapter_delete_sq(dev, qid);
1435 adapter_delete_cq(dev, qid);
1436 }
07836e65
KB		 1437
1438 spin_lock_irq(&nvmeq->q_lock);
1439 nvme_process_cq(nvmeq);
1440 spin_unlock_irq(&nvmeq->q_lock);
b60503ba
MW		 1441}
1442
8ffaadf7
JD		 1443static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1444 int entry_size)
1445{
1446 int q_depth = dev->q_depth;
1447 unsigned q_size_aligned = roundup(q_depth * entry_size, dev->page_size);
1448
1449 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
c45f5c99
JD		 1450 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
1451 mem_per_q = round_down(mem_per_q, dev->page_size);
1452 q_depth = div_u64(mem_per_q, entry_size);
8ffaadf7
JD		 1453
1454 /*
1455 * Ensure the reduced q_depth is above some threshold where it
1456 * would be better to map queues in system memory with the
1457 * original depth
1458 */
1459 if (q_depth < 64)
1460 return -ENOMEM;
1461 }
1462
1463 return q_depth;
1464}
1465
1466static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1467 int qid, int depth)
1468{
1469 if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz)) {
1470 unsigned offset = (qid - 1) *
1471 roundup(SQ_SIZE(depth), dev->page_size);
1472 nvmeq->sq_dma_addr = dev->cmb_dma_addr + offset;
1473 nvmeq->sq_cmds_io = dev->cmb + offset;
1474 } else {
1475 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
1476 &nvmeq->sq_dma_addr, GFP_KERNEL);
1477 if (!nvmeq->sq_cmds)
1478 return -ENOMEM;
1479 }
1480
1481 return 0;
1482}
1483
b60503ba 1484static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
2b25d981 1485 int depth)
b60503ba 1486{
a4aea562 1487 struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq), GFP_KERNEL);
b60503ba
MW		 1488 if (!nvmeq)
1489 return NULL;
1490
e75ec752 1491 nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth),
4d51abf9 1492 &nvmeq->cq_dma_addr, GFP_KERNEL);
b60503ba
MW		 1493 if (!nvmeq->cqes)
1494 goto free_nvmeq;
b60503ba 1495
8ffaadf7 1496 if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth))
b60503ba
MW		 1497 goto free_cqdma;
1498
e75ec752 1499 nvmeq->q_dmadev = dev->dev;
091b6092 1500 nvmeq->dev = dev;
3193f07b
MW		 1501 snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d",
1502 dev->instance, qid);
b60503ba
MW		 1503 spin_lock_init(&nvmeq->q_lock);
1504 nvmeq->cq_head = 0;
82123460 1505 nvmeq->cq_phase = 1;
b80d5ccc 1506 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
b60503ba 1507 nvmeq->q_depth = depth;
c30341dc 1508 nvmeq->qid = qid;
758dd7fd 1509 nvmeq->cq_vector = -1;
a4aea562 1510 dev->queues[qid] = nvmeq;
b60503ba 1511
36a7e993
JD		 1512 /* make sure queue descriptor is set before queue count, for kthread */
1513 mb();
1514 dev->queue_count++;
1515
b60503ba
MW		 1516 return nvmeq;
1517
1518 free_cqdma:
e75ec752 1519 dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes,
b60503ba
MW		 1520 nvmeq->cq_dma_addr);
1521 free_nvmeq:
1522 kfree(nvmeq);
1523 return NULL;
1524}
1525
3001082c
MW		 1526static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1527 const char *name)
1528{
58ffacb5
MW		 1529 if (use_threaded_interrupts)
1530 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
481e5bad 1531 nvme_irq_check, nvme_irq, IRQF_SHARED,
58ffacb5 1532 name, nvmeq);
3001082c 1533 return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
481e5bad 1534 IRQF_SHARED, name, nvmeq);
3001082c
MW		 1535}
1536
22404274 1537static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
b60503ba 1538{
22404274 1539 struct nvme_dev *dev = nvmeq->dev;
b60503ba 1540
7be50e93 1541 spin_lock_irq(&nvmeq->q_lock);
22404274
KB		 1542 nvmeq->sq_tail = 0;
1543 nvmeq->cq_head = 0;
1544 nvmeq->cq_phase = 1;
b80d5ccc 1545 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
22404274 1546 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
42f61420 1547 dev->online_queues++;
7be50e93 1548 spin_unlock_irq(&nvmeq->q_lock);
22404274
KB		 1549}
1550
1551static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1552{
1553 struct nvme_dev *dev = nvmeq->dev;
1554 int result;
3f85d50b 1555
2b25d981 1556 nvmeq->cq_vector = qid - 1;
b60503ba
MW		 1557 result = adapter_alloc_cq(dev, qid, nvmeq);
1558 if (result < 0)
22404274 1559 return result;
b60503ba
MW		 1560
1561 result = adapter_alloc_sq(dev, qid, nvmeq);
1562 if (result < 0)
1563 goto release_cq;
1564
3193f07b 1565 result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
b60503ba
MW		 1566 if (result < 0)
1567 goto release_sq;
1568
22404274 1569 nvme_init_queue(nvmeq, qid);
22404274 1570 return result;
b60503ba
MW		 1571
1572 release_sq:
1573 adapter_delete_sq(dev, qid);
1574 release_cq:
1575 adapter_delete_cq(dev, qid);
22404274 1576 return result;
b60503ba
MW		 1577}
1578
ba47e386
MW		 1579static int nvme_wait_ready(struct nvme_dev *dev, u64 cap, bool enabled)
1580{
1581 unsigned long timeout;
1582 u32 bit = enabled ? NVME_CSTS_RDY : 0;
1583
1584 timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
1585
1586 while ((readl(&dev->bar->csts) & NVME_CSTS_RDY) != bit) {
1587 msleep(100);
1588 if (fatal_signal_pending(current))
1589 return -EINTR;
1590 if (time_after(jiffies, timeout)) {
e75ec752 1591 dev_err(dev->dev,
27e8166c
MW		 1592 "Device not ready; aborting %s\n", enabled ?
1593 "initialisation" : "reset");
ba47e386
MW		 1594 return -ENODEV;
1595 }
1596 }
1597
1598 return 0;
1599}
1600
1601/*
1602 * If the device has been passed off to us in an enabled state, just clear
1603 * the enabled bit. The spec says we should set the 'shutdown notification
1604 * bits', but doing so may cause the device to complete commands to the
1605 * admin queue ... and we don't know what memory that might be pointing at!
1606 */
1607static int nvme_disable_ctrl(struct nvme_dev *dev, u64 cap)
1608{
01079522
DM		 1609 dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1610 dev->ctrl_config &= ~NVME_CC_ENABLE;
1611 writel(dev->ctrl_config, &dev->bar->cc);
44af146a 1612
ba47e386
MW		 1613 return nvme_wait_ready(dev, cap, false);
1614}
1615
1616static int nvme_enable_ctrl(struct nvme_dev *dev, u64 cap)
1617{
01079522
DM		 1618 dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1619 dev->ctrl_config |= NVME_CC_ENABLE;
1620 writel(dev->ctrl_config, &dev->bar->cc);
1621
ba47e386
MW		 1622 return nvme_wait_ready(dev, cap, true);
1623}
1624
1894d8f1
KB		 1625static int nvme_shutdown_ctrl(struct nvme_dev *dev)
1626{
1627 unsigned long timeout;
1894d8f1 1628
01079522
DM		 1629 dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1630 dev->ctrl_config |= NVME_CC_SHN_NORMAL;
1631
1632 writel(dev->ctrl_config, &dev->bar->cc);
1894d8f1 1633
2484f407 1634 timeout = SHUTDOWN_TIMEOUT + jiffies;
1894d8f1
KB		 1635 while ((readl(&dev->bar->csts) & NVME_CSTS_SHST_MASK) !=
1636 NVME_CSTS_SHST_CMPLT) {
1637 msleep(100);
1638 if (fatal_signal_pending(current))
1639 return -EINTR;
1640 if (time_after(jiffies, timeout)) {
e75ec752 1641 dev_err(dev->dev,
1894d8f1
KB		 1642 "Device shutdown incomplete; abort shutdown\n");
1643 return -ENODEV;
1644 }
1645 }
1646
1647 return 0;
1648}
1649
a4aea562 1650static struct blk_mq_ops nvme_mq_admin_ops = {
d29ec824 1651 .queue_rq = nvme_queue_rq,
a4aea562
MB		 1652 .map_queue = blk_mq_map_queue,
1653 .init_hctx = nvme_admin_init_hctx,
4af0e21c 1654 .exit_hctx = nvme_admin_exit_hctx,
a4aea562
MB		 1655 .init_request = nvme_admin_init_request,
1656 .timeout = nvme_timeout,
1657};
1658
1659static struct blk_mq_ops nvme_mq_ops = {
1660 .queue_rq = nvme_queue_rq,
1661 .map_queue = blk_mq_map_queue,
1662 .init_hctx = nvme_init_hctx,
1663 .init_request = nvme_init_request,
1664 .timeout = nvme_timeout,
1665};
1666
ea191d2f
KB		 1667static void nvme_dev_remove_admin(struct nvme_dev *dev)
1668{
1669 if (dev->admin_q && !blk_queue_dying(dev->admin_q)) {
1670 blk_cleanup_queue(dev->admin_q);
1671 blk_mq_free_tag_set(&dev->admin_tagset);
1672 }
1673}
1674
a4aea562
MB		 1675static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1676{
1677 if (!dev->admin_q) {
1678 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1679 dev->admin_tagset.nr_hw_queues = 1;
1680 dev->admin_tagset.queue_depth = NVME_AQ_DEPTH - 1;
1efccc9d 1681 dev->admin_tagset.reserved_tags = 1;
a4aea562 1682 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
e75ec752 1683 dev->admin_tagset.numa_node = dev_to_node(dev->dev);
ac3dd5bd 1684 dev->admin_tagset.cmd_size = nvme_cmd_size(dev);
a4aea562
MB		 1685 dev->admin_tagset.driver_data = dev;
1686
1687 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1688 return -ENOMEM;
1689
1690 dev->admin_q = blk_mq_init_queue(&dev->admin_tagset);
35b489d3 1691 if (IS_ERR(dev->admin_q)) {
a4aea562
MB		 1692 blk_mq_free_tag_set(&dev->admin_tagset);
1693 return -ENOMEM;
1694 }
ea191d2f
KB		 1695 if (!blk_get_queue(dev->admin_q)) {
1696 nvme_dev_remove_admin(dev);
4af0e21c 1697 dev->admin_q = NULL;
ea191d2f
KB		 1698 return -ENODEV;
1699 }
0fb59cbc
KB		 1700 } else
1701 blk_mq_unfreeze_queue(dev->admin_q);
a4aea562
MB		 1702
1703 return 0;
1704}
1705
8d85fce7 1706static int nvme_configure_admin_queue(struct nvme_dev *dev)
b60503ba 1707{
ba47e386 1708 int result;
b60503ba 1709 u32 aqa;
ba47e386 1710 u64 cap = readq(&dev->bar->cap);
b60503ba 1711 struct nvme_queue *nvmeq;
1d090624
KB		 1712 unsigned page_shift = PAGE_SHIFT;
1713 unsigned dev_page_min = NVME_CAP_MPSMIN(cap) + 12;
1714 unsigned dev_page_max = NVME_CAP_MPSMAX(cap) + 12;
1715
1716 if (page_shift < dev_page_min) {
e75ec752 1717 dev_err(dev->dev,
1d090624
KB		 1718 "Minimum device page size (%u) too large for "
1719 "host (%u)\n", 1 << dev_page_min,
1720 1 << page_shift);
1721 return -ENODEV;
1722 }
1723 if (page_shift > dev_page_max) {
e75ec752 1724 dev_info(dev->dev,
1d090624
KB		 1725 "Device maximum page size (%u) smaller than "
1726 "host (%u); enabling work-around\n",
1727 1 << dev_page_max, 1 << page_shift);
1728 page_shift = dev_page_max;
1729 }
b60503ba 1730
dfbac8c7
KB		 1731 dev->subsystem = readl(&dev->bar->vs) >= NVME_VS(1, 1) ?
1732 NVME_CAP_NSSRC(cap) : 0;
1733
1734 if (dev->subsystem && (readl(&dev->bar->csts) & NVME_CSTS_NSSRO))
1735 writel(NVME_CSTS_NSSRO, &dev->bar->csts);
1736
ba47e386
MW		 1737 result = nvme_disable_ctrl(dev, cap);
1738 if (result < 0)
1739 return result;
b60503ba 1740
a4aea562 1741 nvmeq = dev->queues[0];
cd638946 1742 if (!nvmeq) {
2b25d981 1743 nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
cd638946
KB		 1744 if (!nvmeq)
1745 return -ENOMEM;
cd638946 1746 }
b60503ba
MW		 1747
1748 aqa = nvmeq->q_depth - 1;
1749 aqa |= aqa << 16;
1750
1d090624
KB		 1751 dev->page_size = 1 << page_shift;
1752
01079522 1753 dev->ctrl_config = NVME_CC_CSS_NVM;
1d090624 1754 dev->ctrl_config |= (page_shift - 12) << NVME_CC_MPS_SHIFT;
b60503ba 1755 dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
7f53f9d2 1756 dev->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
b60503ba
MW		 1757
1758 writel(aqa, &dev->bar->aqa);
1759 writeq(nvmeq->sq_dma_addr, &dev->bar->asq);
1760 writeq(nvmeq->cq_dma_addr, &dev->bar->acq);
b60503ba 1761
ba47e386 1762 result = nvme_enable_ctrl(dev, cap);
025c557a 1763 if (result)
a4aea562
MB		 1764 goto free_nvmeq;
1765
2b25d981 1766 nvmeq->cq_vector = 0;
3193f07b 1767 result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
758dd7fd
JD		 1768 if (result) {
1769 nvmeq->cq_vector = -1;
0fb59cbc 1770 goto free_nvmeq;
758dd7fd 1771 }
025c557a 1772
b60503ba 1773 return result;
a4aea562 1774
a4aea562
MB		 1775 free_nvmeq:
1776 nvme_free_queues(dev, 0);
1777 return result;
b60503ba
MW		 1778}
1779
a53295b6
MW		 1780static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
1781{
1782 struct nvme_dev *dev = ns->dev;
a53295b6
MW		 1783 struct nvme_user_io io;
1784 struct nvme_command c;
d29ec824 1785 unsigned length, meta_len;
a67a9513 1786 int status, write;
a67a9513
KB		 1787 dma_addr_t meta_dma = 0;
1788 void *meta = NULL;
fec558b5 1789 void __user *metadata;
a53295b6
MW		 1790
1791 if (copy_from_user(&io, uio, sizeof(io)))
1792 return -EFAULT;
6c7d4945
MW		 1793
1794 switch (io.opcode) {
1795 case nvme_cmd_write:
1796 case nvme_cmd_read:
6bbf1acd 1797 case nvme_cmd_compare:
6413214c 1798 break;
6c7d4945 1799 default:
6bbf1acd 1800 return -EINVAL;
6c7d4945
MW		 1801 }
1802
d29ec824
CH		 1803 length = (io.nblocks + 1) << ns->lba_shift;
1804 meta_len = (io.nblocks + 1) * ns->ms;
3d42e67f 1805 metadata = (void __user *)(uintptr_t)io.metadata;
d29ec824 1806 write = io.opcode & 1;
a53295b6 1807
71feb364
KB		 1808 if (ns->ext) {
1809 length += meta_len;
1810 meta_len = 0;
a67a9513
KB		 1811 }
1812 if (meta_len) {
d29ec824
CH		 1813 if (((io.metadata & 3) || !io.metadata) && !ns->ext)
1814 return -EINVAL;
1815
e75ec752 1816 meta = dma_alloc_coherent(dev->dev, meta_len,
a67a9513 1817 &meta_dma, GFP_KERNEL);
fec558b5 1818
a67a9513
KB		 1819 if (!meta) {
1820 status = -ENOMEM;
1821 goto unmap;
1822 }
1823 if (write) {
fec558b5 1824 if (copy_from_user(meta, metadata, meta_len)) {
a67a9513
KB		 1825 status = -EFAULT;
1826 goto unmap;
1827 }
1828 }
1829 }
1830
a53295b6
MW		 1831 memset(&c, 0, sizeof(c));
1832 c.rw.opcode = io.opcode;
1833 c.rw.flags = io.flags;
6c7d4945 1834 c.rw.nsid = cpu_to_le32(ns->ns_id);
a53295b6 1835 c.rw.slba = cpu_to_le64(io.slba);
6c7d4945 1836 c.rw.length = cpu_to_le16(io.nblocks);
a53295b6 1837 c.rw.control = cpu_to_le16(io.control);
1c9b5265
MW		 1838 c.rw.dsmgmt = cpu_to_le32(io.dsmgmt);
1839 c.rw.reftag = cpu_to_le32(io.reftag);
1840 c.rw.apptag = cpu_to_le16(io.apptag);
1841 c.rw.appmask = cpu_to_le16(io.appmask);
a67a9513 1842 c.rw.metadata = cpu_to_le64(meta_dma);
d29ec824
CH		 1843
1844 status = __nvme_submit_sync_cmd(ns->queue, &c, NULL,
3d42e67f 1845 (void __user *)(uintptr_t)io.addr, length, NULL, 0);
f410c680 1846 unmap:
a67a9513
KB		 1847 if (meta) {
1848 if (status == NVME_SC_SUCCESS && !write) {
fec558b5 1849 if (copy_to_user(metadata, meta, meta_len))
a67a9513
KB		 1850 status = -EFAULT;
1851 }
e75ec752 1852 dma_free_coherent(dev->dev, meta_len, meta, meta_dma);
f410c680 1853 }
a53295b6
MW		 1854 return status;
1855}
1856
a4aea562
MB		 1857static int nvme_user_cmd(struct nvme_dev *dev, struct nvme_ns *ns,
1858 struct nvme_passthru_cmd __user *ucmd)
6ee44cdc 1859{
7963e521 1860 struct nvme_passthru_cmd cmd;
6ee44cdc 1861 struct nvme_command c;
d29ec824
CH		 1862 unsigned timeout = 0;
1863 int status;
6ee44cdc 1864
6bbf1acd
MW		 1865 if (!capable(CAP_SYS_ADMIN))
1866 return -EACCES;
1867 if (copy_from_user(&cmd, ucmd, sizeof(cmd)))
6ee44cdc 1868 return -EFAULT;
6ee44cdc
MW		 1869
1870 memset(&c, 0, sizeof(c));
6bbf1acd
MW		 1871 c.common.opcode = cmd.opcode;
1872 c.common.flags = cmd.flags;
1873 c.common.nsid = cpu_to_le32(cmd.nsid);
1874 c.common.cdw2[0] = cpu_to_le32(cmd.cdw2);
1875 c.common.cdw2[1] = cpu_to_le32(cmd.cdw3);
1876 c.common.cdw10[0] = cpu_to_le32(cmd.cdw10);
1877 c.common.cdw10[1] = cpu_to_le32(cmd.cdw11);
1878 c.common.cdw10[2] = cpu_to_le32(cmd.cdw12);
1879 c.common.cdw10[3] = cpu_to_le32(cmd.cdw13);
1880 c.common.cdw10[4] = cpu_to_le32(cmd.cdw14);
1881 c.common.cdw10[5] = cpu_to_le32(cmd.cdw15);
1882
d29ec824
CH		 1883 if (cmd.timeout_ms)
1884 timeout = msecs_to_jiffies(cmd.timeout_ms);
eca18b23 1885
f705f837 1886 status = __nvme_submit_sync_cmd(ns ? ns->queue : dev->admin_q, &c,
3d42e67f 1887 NULL, (void __user *)(uintptr_t)cmd.addr, cmd.data_len,
d29ec824
CH		 1888 &cmd.result, timeout);
1889 if (status >= 0) {
1890 if (put_user(cmd.result, &ucmd->result))
1891 return -EFAULT;
6bbf1acd 1892 }
f4f117f6 1893
6ee44cdc
MW		 1894 return status;
1895}
1896
81f03fed
JD		 1897static int nvme_subsys_reset(struct nvme_dev *dev)
1898{
1899 if (!dev->subsystem)
1900 return -ENOTTY;
1901
1902 writel(0x4E564D65, &dev->bar->nssr); /* "NVMe" */
1903 return 0;
1904}
1905
b60503ba
MW		 1906static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd,
1907 unsigned long arg)
1908{
1909 struct nvme_ns *ns = bdev->bd_disk->private_data;
1910
1911 switch (cmd) {
6bbf1acd 1912 case NVME_IOCTL_ID:
c3bfe717 1913 force_successful_syscall_return();
6bbf1acd
MW		 1914 return ns->ns_id;
1915 case NVME_IOCTL_ADMIN_CMD:
a4aea562 1916 return nvme_user_cmd(ns->dev, NULL, (void __user *)arg);
7963e521 1917 case NVME_IOCTL_IO_CMD:
a4aea562 1918 return nvme_user_cmd(ns->dev, ns, (void __user *)arg);
a53295b6
MW		 1919 case NVME_IOCTL_SUBMIT_IO:
1920 return nvme_submit_io(ns, (void __user *)arg);
5d0f6131
VV		 1921 case SG_GET_VERSION_NUM:
1922 return nvme_sg_get_version_num((void __user *)arg);
1923 case SG_IO:
1924 return nvme_sg_io(ns, (void __user *)arg);
b60503ba
MW		 1925 default:
1926 return -ENOTTY;
1927 }
1928}
1929
320a3827
KB		 1930#ifdef CONFIG_COMPAT
1931static int nvme_compat_ioctl(struct block_device *bdev, fmode_t mode,
1932 unsigned int cmd, unsigned long arg)
1933{
320a3827
KB		 1934 switch (cmd) {
1935 case SG_IO:
e179729a 1936 return -ENOIOCTLCMD;
320a3827
KB		 1937 }
1938 return nvme_ioctl(bdev, mode, cmd, arg);
1939}
1940#else
1941#define nvme_compat_ioctl NULL
1942#endif
1943
5105aa55 1944static void nvme_free_dev(struct kref *kref);
188c3568
KB		 1945static void nvme_free_ns(struct kref *kref)
1946{
1947 struct nvme_ns *ns = container_of(kref, struct nvme_ns, kref);
1948
1949 spin_lock(&dev_list_lock);
1950 ns->disk->private_data = NULL;
1951 spin_unlock(&dev_list_lock);
1952
5105aa55 1953 kref_put(&ns->dev->kref, nvme_free_dev);
188c3568
KB		 1954 put_disk(ns->disk);
1955 kfree(ns);
1956}
1957
9ac27090
KB		 1958static int nvme_open(struct block_device *bdev, fmode_t mode)
1959{
9e60352c
KB		 1960 int ret = 0;
1961 struct nvme_ns *ns;
9ac27090 1962
9e60352c
KB		 1963 spin_lock(&dev_list_lock);
1964 ns = bdev->bd_disk->private_data;
1965 if (!ns)
1966 ret = -ENXIO;
188c3568 1967 else if (!kref_get_unless_zero(&ns->kref))
9e60352c
KB		 1968 ret = -ENXIO;
1969 spin_unlock(&dev_list_lock);
1970
1971 return ret;
9ac27090
KB		 1972}
1973
9ac27090
KB		 1974static void nvme_release(struct gendisk *disk, fmode_t mode)
1975{
1976 struct nvme_ns *ns = disk->private_data;
188c3568 1977 kref_put(&ns->kref, nvme_free_ns);
9ac27090
KB		 1978}
1979
4cc09e2d
KB		 1980static int nvme_getgeo(struct block_device *bd, struct hd_geometry *geo)
1981{
1982 /* some standard values */
1983 geo->heads = 1 << 6;
1984 geo->sectors = 1 << 5;
1985 geo->cylinders = get_capacity(bd->bd_disk) >> 11;
1986 return 0;
1987}
1988
e1e5e564
KB		 1989static void nvme_config_discard(struct nvme_ns *ns)
1990{
1991 u32 logical_block_size = queue_logical_block_size(ns->queue);
1992 ns->queue->limits.discard_zeroes_data = 0;
1993 ns->queue->limits.discard_alignment = logical_block_size;
1994 ns->queue->limits.discard_granularity = logical_block_size;
2bb4cd5c 1995 blk_queue_max_discard_sectors(ns->queue, 0xffffffff);
e1e5e564
KB		 1996 queue_flag_set_unlocked(QUEUE_FLAG_DISCARD, ns->queue);
1997}
1998
1b9dbf7f
KB		 1999static int nvme_revalidate_disk(struct gendisk *disk)
2000{
2001 struct nvme_ns *ns = disk->private_data;
2002 struct nvme_dev *dev = ns->dev;
2003 struct nvme_id_ns *id;
a67a9513
KB		 2004 u8 lbaf, pi_type;
2005 u16 old_ms;
e1e5e564 2006 unsigned short bs;
1b9dbf7f 2007
d29ec824 2008 if (nvme_identify_ns(dev, ns->ns_id, &id)) {
a5768aa8
KB		 2009 dev_warn(dev->dev, "%s: Identify failure nvme%dn%d\n", __func__,
2010 dev->instance, ns->ns_id);
2011 return -ENODEV;
1b9dbf7f 2012 }
a5768aa8
KB		 2013 if (id->ncap == 0) {
2014 kfree(id);
2015 return -ENODEV;
e1e5e564 2016 }
1b9dbf7f 2017
e1e5e564
KB		 2018 old_ms = ns->ms;
2019 lbaf = id->flbas & NVME_NS_FLBAS_LBA_MASK;
1b9dbf7f 2020 ns->lba_shift = id->lbaf[lbaf].ds;
e1e5e564 2021 ns->ms = le16_to_cpu(id->lbaf[lbaf].ms);
a67a9513 2022 ns->ext = ns->ms && (id->flbas & NVME_NS_FLBAS_META_EXT);
e1e5e564
KB		 2023
2024 /*
2025 * If identify namespace failed, use default 512 byte block size so
2026 * block layer can use before failing read/write for 0 capacity.
2027 */
2028 if (ns->lba_shift == 0)
2029 ns->lba_shift = 9;
2030 bs = 1 << ns->lba_shift;
2031
2032 /* XXX: PI implementation requires metadata equal t10 pi tuple size */
2033 pi_type = ns->ms == sizeof(struct t10_pi_tuple) ?
2034 id->dps & NVME_NS_DPS_PI_MASK : 0;
2035
52b68d7e
KB		 2036 if (blk_get_integrity(disk) && (ns->pi_type != pi_type ||
2037 ns->ms != old_ms ||
e1e5e564 2038 bs != queue_logical_block_size(disk->queue) ||
a67a9513 2039 (ns->ms && ns->ext)))
e1e5e564
KB		 2040 blk_integrity_unregister(disk);
2041
2042 ns->pi_type = pi_type;
2043 blk_queue_logical_block_size(ns->queue, bs);
2044
52b68d7e 2045 if (ns->ms && !blk_get_integrity(disk) && (disk->flags & GENHD_FL_UP) &&
a67a9513 2046 !ns->ext)
e1e5e564
KB		 2047 nvme_init_integrity(ns);
2048
e19b127f 2049 if (ns->ms && !(ns->ms == 8 && ns->pi_type) && !blk_get_integrity(disk))
e1e5e564
KB		 2050 set_capacity(disk, 0);
2051 else
2052 set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
2053
2054 if (dev->oncs & NVME_CTRL_ONCS_DSM)
2055 nvme_config_discard(ns);
1b9dbf7f 2056
d29ec824 2057 kfree(id);
1b9dbf7f
KB		 2058 return 0;
2059}
2060
b60503ba
MW		 2061static const struct block_device_operations nvme_fops = {
2062 .owner = THIS_MODULE,
2063 .ioctl = nvme_ioctl,
320a3827 2064 .compat_ioctl = nvme_compat_ioctl,
9ac27090
KB		 2065 .open = nvme_open,
2066 .release = nvme_release,
4cc09e2d 2067 .getgeo = nvme_getgeo,
1b9dbf7f 2068 .revalidate_disk= nvme_revalidate_disk,
b60503ba
MW		 2069};
2070
1fa6aead
MW		 2071static int nvme_kthread(void *data)
2072{
d4b4ff8e 2073 struct nvme_dev *dev, *next;
1fa6aead
MW		 2074
2075 while (!kthread_should_stop()) {
564a232c 2076 set_current_state(TASK_INTERRUPTIBLE);
1fa6aead 2077 spin_lock(&dev_list_lock);
d4b4ff8e 2078 list_for_each_entry_safe(dev, next, &dev_list, node) {
1fa6aead 2079 int i;
dfbac8c7
KB		 2080 u32 csts = readl(&dev->bar->csts);
2081
2082 if ((dev->subsystem && (csts & NVME_CSTS_NSSRO)) ||
2083 csts & NVME_CSTS_CFS) {
90667892
CH		 2084 if (!__nvme_reset(dev)) {
2085 dev_warn(dev->dev,
2086 "Failed status: %x, reset controller\n",
2087 readl(&dev->bar->csts));
2088 }
d4b4ff8e
KB		 2089 continue;
2090 }
1fa6aead 2091 for (i = 0; i < dev->queue_count; i++) {
a4aea562 2092 struct nvme_queue *nvmeq = dev->queues[i];
740216fc
MW		 2093 if (!nvmeq)
2094 continue;
1fa6aead 2095 spin_lock_irq(&nvmeq->q_lock);
bc57a0f7 2096 nvme_process_cq(nvmeq);
6fccf938
KB		 2097
2098 while ((i == 0) && (dev->event_limit > 0)) {
a4aea562 2099 if (nvme_submit_async_admin_req(dev))
6fccf938
KB		 2100 break;
2101 dev->event_limit--;
2102 }
1fa6aead
MW		 2103 spin_unlock_irq(&nvmeq->q_lock);
2104 }
2105 }
2106 spin_unlock(&dev_list_lock);
acb7aa0d 2107 schedule_timeout(round_jiffies_relative(HZ));
1fa6aead
MW		 2108 }
2109 return 0;
2110}
2111
e1e5e564 2112static void nvme_alloc_ns(struct nvme_dev *dev, unsigned nsid)
b60503ba
MW		 2113{
2114 struct nvme_ns *ns;
2115 struct gendisk *disk;
e75ec752 2116 int node = dev_to_node(dev->dev);
b60503ba 2117
a4aea562 2118 ns = kzalloc_node(sizeof(*ns), GFP_KERNEL, node);
b60503ba 2119 if (!ns)
e1e5e564
KB		 2120 return;
2121
a4aea562 2122 ns->queue = blk_mq_init_queue(&dev->tagset);
9f173b33 2123 if (IS_ERR(ns->queue))
b60503ba 2124 goto out_free_ns;
4eeb9215
MW		 2125 queue_flag_set_unlocked(QUEUE_FLAG_NOMERGES, ns->queue);
2126 queue_flag_set_unlocked(QUEUE_FLAG_NONROT, ns->queue);
b60503ba
MW		 2127 ns->dev = dev;
2128 ns->queue->queuedata = ns;
2129
a4aea562 2130 disk = alloc_disk_node(0, node);
b60503ba
MW		 2131 if (!disk)
2132 goto out_free_queue;
a4aea562 2133
188c3568 2134 kref_init(&ns->kref);
5aff9382 2135 ns->ns_id = nsid;
b60503ba 2136 ns->disk = disk;
e1e5e564
KB		 2137 ns->lba_shift = 9; /* set to a default value for 512 until disk is validated */
2138 list_add_tail(&ns->list, &dev->namespaces);
2139
e9ef4636 2140 blk_queue_logical_block_size(ns->queue, 1 << ns->lba_shift);
e824410f 2141 if (dev->max_hw_sectors) {
8fc23e03 2142 blk_queue_max_hw_sectors(ns->queue, dev->max_hw_sectors);
e824410f
KB		 2143 blk_queue_max_segments(ns->queue,
2144 ((dev->max_hw_sectors << 9) / dev->page_size) + 1);
2145 }
a4aea562
MB		 2146 if (dev->stripe_size)
2147 blk_queue_chunk_sectors(ns->queue, dev->stripe_size >> 9);
a7d2ce28
KB		 2148 if (dev->vwc & NVME_CTRL_VWC_PRESENT)
2149 blk_queue_flush(ns->queue, REQ_FLUSH | REQ_FUA);
03100aad 2150 blk_queue_virt_boundary(ns->queue, dev->page_size - 1);
b60503ba
MW		 2151
2152 disk->major = nvme_major;
469071a3 2153 disk->first_minor = 0;
b60503ba
MW		 2154 disk->fops = &nvme_fops;
2155 disk->private_data = ns;
2156 disk->queue = ns->queue;
b3fffdef 2157 disk->driverfs_dev = dev->device;
469071a3 2158 disk->flags = GENHD_FL_EXT_DEVT;
5aff9382 2159 sprintf(disk->disk_name, "nvme%dn%d", dev->instance, nsid);
b60503ba 2160
e1e5e564
KB		 2161 /*
2162 * Initialize capacity to 0 until we establish the namespace format and
2163 * setup integrity extentions if necessary. The revalidate_disk after
2164 * add_disk allows the driver to register with integrity if the format
2165 * requires it.
2166 */
2167 set_capacity(disk, 0);
a5768aa8
KB		 2168 if (nvme_revalidate_disk(ns->disk))
2169 goto out_free_disk;
2170
5105aa55 2171 kref_get(&dev->kref);
e1e5e564 2172 add_disk(ns->disk);
7bee6074
KB		 2173 if (ns->ms) {
2174 struct block_device *bd = bdget_disk(ns->disk, 0);
2175 if (!bd)
2176 return;
2177 if (blkdev_get(bd, FMODE_READ, NULL)) {
2178 bdput(bd);
2179 return;
2180 }
2181 blkdev_reread_part(bd);
2182 blkdev_put(bd, FMODE_READ);
2183 }
e1e5e564 2184 return;
a5768aa8
KB		 2185 out_free_disk:
2186 kfree(disk);
2187 list_del(&ns->list);
b60503ba
MW		 2188 out_free_queue:
2189 blk_cleanup_queue(ns->queue);
2190 out_free_ns:
2191 kfree(ns);
b60503ba
MW		 2192}
2193
2659e57b
CH		 2194/*
2195 * Create I/O queues. Failing to create an I/O queue is not an issue,
2196 * we can continue with less than the desired amount of queues, and
2197 * even a controller without I/O queues an still be used to issue
2198 * admin commands. This might be useful to upgrade a buggy firmware
2199 * for example.
2200 */
42f61420
KB		 2201static void nvme_create_io_queues(struct nvme_dev *dev)
2202{
a4aea562 2203 unsigned i;
42f61420 2204
a4aea562 2205 for (i = dev->queue_count; i <= dev->max_qid; i++)
2b25d981 2206 if (!nvme_alloc_queue(dev, i, dev->q_depth))
42f61420
KB		 2207 break;
2208
a4aea562 2209 for (i = dev->online_queues; i <= dev->queue_count - 1; i++)
2659e57b
CH		 2210 if (nvme_create_queue(dev->queues[i], i)) {
2211 nvme_free_queues(dev, i);
42f61420 2212 break;
2659e57b 2213 }
42f61420
KB		 2214}
2215
b3b06812 2216static int set_queue_count(struct nvme_dev *dev, int count)
b60503ba
MW		 2217{
2218 int status;
2219 u32 result;
b3b06812 2220 u32 q_count = (count - 1) | ((count - 1) << 16);
b60503ba 2221
df348139 2222 status = nvme_set_features(dev, NVME_FEAT_NUM_QUEUES, q_count, 0,
bc5fc7e4 2223 &result);
27e8166c
MW		 2224 if (status < 0)
2225 return status;
2226 if (status > 0) {
e75ec752 2227 dev_err(dev->dev, "Could not set queue count (%d)\n", status);
badc34d4 2228 return 0;
27e8166c 2229 }
b60503ba
MW		 2230 return min(result & 0xffff, result >> 16) + 1;
2231}
2232
8ffaadf7
JD		 2233static void __iomem *nvme_map_cmb(struct nvme_dev *dev)
2234{
2235 u64 szu, size, offset;
2236 u32 cmbloc;
2237 resource_size_t bar_size;
2238 struct pci_dev *pdev = to_pci_dev(dev->dev);
2239 void __iomem *cmb;
2240 dma_addr_t dma_addr;
2241
2242 if (!use_cmb_sqes)
2243 return NULL;
2244
2245 dev->cmbsz = readl(&dev->bar->cmbsz);
2246 if (!(NVME_CMB_SZ(dev->cmbsz)))
2247 return NULL;
2248
2249 cmbloc = readl(&dev->bar->cmbloc);
2250
2251 szu = (u64)1 << (12 + 4 * NVME_CMB_SZU(dev->cmbsz));
2252 size = szu * NVME_CMB_SZ(dev->cmbsz);
2253 offset = szu * NVME_CMB_OFST(cmbloc);
2254 bar_size = pci_resource_len(pdev, NVME_CMB_BIR(cmbloc));
2255
2256 if (offset > bar_size)
2257 return NULL;
2258
2259 /*
2260 * Controllers may support a CMB size larger than their BAR,
2261 * for example, due to being behind a bridge. Reduce the CMB to
2262 * the reported size of the BAR
2263 */
2264 if (size > bar_size - offset)
2265 size = bar_size - offset;
2266
2267 dma_addr = pci_resource_start(pdev, NVME_CMB_BIR(cmbloc)) + offset;
2268 cmb = ioremap_wc(dma_addr, size);
2269 if (!cmb)
2270 return NULL;
2271
2272 dev->cmb_dma_addr = dma_addr;
2273 dev->cmb_size = size;
2274 return cmb;
2275}
2276
2277static inline void nvme_release_cmb(struct nvme_dev *dev)
2278{
2279 if (dev->cmb) {
2280 iounmap(dev->cmb);
2281 dev->cmb = NULL;
2282 }
2283}
2284
9d713c2b
KB		 2285static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
2286{
b80d5ccc 2287 return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride);
9d713c2b
KB		 2288}
2289
8d85fce7 2290static int nvme_setup_io_queues(struct nvme_dev *dev)
b60503ba 2291{
a4aea562 2292 struct nvme_queue *adminq = dev->queues[0];
e75ec752 2293 struct pci_dev *pdev = to_pci_dev(dev->dev);
42f61420 2294 int result, i, vecs, nr_io_queues, size;
b60503ba 2295
42f61420 2296 nr_io_queues = num_possible_cpus();
b348b7d5 2297 result = set_queue_count(dev, nr_io_queues);
badc34d4 2298 if (result <= 0)
1b23484b 2299 return result;
b348b7d5
MW		 2300 if (result < nr_io_queues)
2301 nr_io_queues = result;
b60503ba 2302
8ffaadf7
JD		 2303 if (dev->cmb && NVME_CMB_SQS(dev->cmbsz)) {
2304 result = nvme_cmb_qdepth(dev, nr_io_queues,
2305 sizeof(struct nvme_command));
2306 if (result > 0)
2307 dev->q_depth = result;
2308 else
2309 nvme_release_cmb(dev);
2310 }
2311
9d713c2b
KB		 2312 size = db_bar_size(dev, nr_io_queues);
2313 if (size > 8192) {
f1938f6e 2314 iounmap(dev->bar);
9d713c2b
KB		 2315 do {
2316 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
2317 if (dev->bar)
2318 break;
2319 if (!--nr_io_queues)
2320 return -ENOMEM;
2321 size = db_bar_size(dev, nr_io_queues);
2322 } while (1);
f1938f6e 2323 dev->dbs = ((void __iomem *)dev->bar) + 4096;
5a92e700 2324 adminq->q_db = dev->dbs;
f1938f6e
MW		 2325 }
2326
9d713c2b 2327 /* Deregister the admin queue's interrupt */
3193f07b 2328 free_irq(dev->entry[0].vector, adminq);
9d713c2b 2329
e32efbfc
JA		 2330 /*
2331 * If we enable msix early due to not intx, disable it again before
2332 * setting up the full range we need.
2333 */
2334 if (!pdev->irq)
2335 pci_disable_msix(pdev);
2336
be577fab 2337 for (i = 0; i < nr_io_queues; i++)
1b23484b 2338 dev->entry[i].entry = i;
be577fab
AG		 2339 vecs = pci_enable_msix_range(pdev, dev->entry, 1, nr_io_queues);
2340 if (vecs < 0) {
2341 vecs = pci_enable_msi_range(pdev, 1, min(nr_io_queues, 32));
2342 if (vecs < 0) {
2343 vecs = 1;
2344 } else {
2345 for (i = 0; i < vecs; i++)
2346 dev->entry[i].vector = i + pdev->irq;
fa08a396
RRG		 2347 }
2348 }
2349
063a8096
MW		 2350 /*
2351 * Should investigate if there's a performance win from allocating
2352 * more queues than interrupt vectors; it might allow the submission
2353 * path to scale better, even if the receive path is limited by the
2354 * number of interrupts.
2355 */
2356 nr_io_queues = vecs;
42f61420 2357 dev->max_qid = nr_io_queues;
063a8096 2358
3193f07b 2359 result = queue_request_irq(dev, adminq, adminq->irqname);
758dd7fd
JD		 2360 if (result) {
2361 adminq->cq_vector = -1;
22404274 2362 goto free_queues;
758dd7fd 2363 }
1b23484b 2364
cd638946 2365 /* Free previously allocated queues that are no longer usable */
42f61420 2366 nvme_free_queues(dev, nr_io_queues + 1);
a4aea562 2367 nvme_create_io_queues(dev);
9ecdc946 2368
22404274 2369 return 0;
b60503ba 2370
22404274 2371 free_queues:
a1a5ef99 2372 nvme_free_queues(dev, 1);
22404274 2373 return result;
b60503ba
MW		 2374}
2375
a5768aa8
KB		 2376static int ns_cmp(void *priv, struct list_head *a, struct list_head *b)
2377{
2378 struct nvme_ns *nsa = container_of(a, struct nvme_ns, list);
2379 struct nvme_ns *nsb = container_of(b, struct nvme_ns, list);
2380
2381 return nsa->ns_id - nsb->ns_id;
2382}
2383
2384static struct nvme_ns *nvme_find_ns(struct nvme_dev *dev, unsigned nsid)
2385{
2386 struct nvme_ns *ns;
2387
2388 list_for_each_entry(ns, &dev->namespaces, list) {
2389 if (ns->ns_id == nsid)
2390 return ns;
2391 if (ns->ns_id > nsid)
2392 break;
2393 }
2394 return NULL;
2395}
2396
2397static inline bool nvme_io_incapable(struct nvme_dev *dev)
2398{
2399 return (!dev->bar || readl(&dev->bar->csts) & NVME_CSTS_CFS ||
2400 dev->online_queues < 2);
2401}
2402
2403static void nvme_ns_remove(struct nvme_ns *ns)
2404{
2405 bool kill = nvme_io_incapable(ns->dev) && !blk_queue_dying(ns->queue);
2406
2407 if (kill)
2408 blk_set_queue_dying(ns->queue);
2409 if (ns->disk->flags & GENHD_FL_UP) {
2410 if (blk_get_integrity(ns->disk))
2411 blk_integrity_unregister(ns->disk);
2412 del_gendisk(ns->disk);
2413 }
2414 if (kill || !blk_queue_dying(ns->queue)) {
2415 blk_mq_abort_requeue_list(ns->queue);
2416 blk_cleanup_queue(ns->queue);
5105aa55
KB		 2417 }
2418 list_del_init(&ns->list);
2419 kref_put(&ns->kref, nvme_free_ns);
a5768aa8
KB		 2420}
2421
2422static void nvme_scan_namespaces(struct nvme_dev *dev, unsigned nn)
2423{
2424 struct nvme_ns *ns, *next;
2425 unsigned i;
2426
2427 for (i = 1; i <= nn; i++) {
2428 ns = nvme_find_ns(dev, i);
2429 if (ns) {
5105aa55 2430 if (revalidate_disk(ns->disk))
a5768aa8 2431 nvme_ns_remove(ns);
a5768aa8
KB		 2432 } else
2433 nvme_alloc_ns(dev, i);
2434 }
2435 list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
5105aa55 2436 if (ns->ns_id > nn)
a5768aa8 2437 nvme_ns_remove(ns);
a5768aa8
KB		 2438 }
2439 list_sort(NULL, &dev->namespaces, ns_cmp);
2440}
2441
bda4e0fb
KB		 2442static void nvme_set_irq_hints(struct nvme_dev *dev)
2443{
2444 struct nvme_queue *nvmeq;
2445 int i;
2446
2447 for (i = 0; i < dev->online_queues; i++) {
2448 nvmeq = dev->queues[i];
2449
2450 if (!nvmeq->tags || !(*nvmeq->tags))
2451 continue;
2452
2453 irq_set_affinity_hint(dev->entry[nvmeq->cq_vector].vector,
2454 blk_mq_tags_cpumask(*nvmeq->tags));
2455 }
2456}
2457
a5768aa8
KB		 2458static void nvme_dev_scan(struct work_struct *work)
2459{
2460 struct nvme_dev *dev = container_of(work, struct nvme_dev, scan_work);
2461 struct nvme_id_ctrl *ctrl;
2462
2463 if (!dev->tagset.tags)
2464 return;
2465 if (nvme_identify_ctrl(dev, &ctrl))
2466 return;
2467 nvme_scan_namespaces(dev, le32_to_cpup(&ctrl->nn));
2468 kfree(ctrl);
bda4e0fb 2469 nvme_set_irq_hints(dev);
a5768aa8
KB		 2470}
2471
422ef0c7
MW		 2472/*
2473 * Return: error value if an error occurred setting up the queues or calling
2474 * Identify Device. 0 if these succeeded, even if adding some of the
2475 * namespaces failed. At the moment, these failures are silent. TBD which
2476 * failures should be reported.
2477 */
8d85fce7 2478static int nvme_dev_add(struct nvme_dev *dev)
b60503ba 2479{
e75ec752 2480 struct pci_dev *pdev = to_pci_dev(dev->dev);
c3bfe717 2481 int res;
51814232 2482 struct nvme_id_ctrl *ctrl;
159b67d7 2483 int shift = NVME_CAP_MPSMIN(readq(&dev->bar->cap)) + 12;
b60503ba 2484
d29ec824 2485 res = nvme_identify_ctrl(dev, &ctrl);
b60503ba 2486 if (res) {
e75ec752 2487 dev_err(dev->dev, "Identify Controller failed (%d)\n", res);
e1e5e564 2488 return -EIO;
b60503ba
MW		 2489 }
2490
0e5e4f0e 2491 dev->oncs = le16_to_cpup(&ctrl->oncs);
c30341dc 2492 dev->abort_limit = ctrl->acl + 1;
a7d2ce28 2493 dev->vwc = ctrl->vwc;
51814232
MW		 2494 memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn));
2495 memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn));
2496 memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr));
159b67d7 2497 if (ctrl->mdts)
8fc23e03 2498 dev->max_hw_sectors = 1 << (ctrl->mdts + shift - 9);
68608c26 2499 if ((pdev->vendor == PCI_VENDOR_ID_INTEL) &&
a4aea562
MB		 2500 (pdev->device == 0x0953) && ctrl->vs[3]) {
2501 unsigned int max_hw_sectors;
2502
159b67d7 2503 dev->stripe_size = 1 << (ctrl->vs[3] + shift);
a4aea562
MB		 2504 max_hw_sectors = dev->stripe_size >> (shift - 9);
2505 if (dev->max_hw_sectors) {
2506 dev->max_hw_sectors = min(max_hw_sectors,
2507 dev->max_hw_sectors);
2508 } else
2509 dev->max_hw_sectors = max_hw_sectors;
2510 }
d29ec824 2511 kfree(ctrl);
a4aea562 2512
ffe7704d
KB		 2513 if (!dev->tagset.tags) {
2514 dev->tagset.ops = &nvme_mq_ops;
2515 dev->tagset.nr_hw_queues = dev->online_queues - 1;
2516 dev->tagset.timeout = NVME_IO_TIMEOUT;
2517 dev->tagset.numa_node = dev_to_node(dev->dev);
2518 dev->tagset.queue_depth =
a4aea562 2519 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
ffe7704d
KB		 2520 dev->tagset.cmd_size = nvme_cmd_size(dev);
2521 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2522 dev->tagset.driver_data = dev;
b60503ba 2523
ffe7704d
KB		 2524 if (blk_mq_alloc_tag_set(&dev->tagset))
2525 return 0;
2526 }
a5768aa8 2527 schedule_work(&dev->scan_work);
e1e5e564 2528 return 0;
b60503ba
MW		 2529}
2530
0877cb0d
KB		 2531static int nvme_dev_map(struct nvme_dev *dev)
2532{
42f61420 2533 u64 cap;
0877cb0d 2534 int bars, result = -ENOMEM;
e75ec752 2535 struct pci_dev *pdev = to_pci_dev(dev->dev);
0877cb0d
KB		 2536
2537 if (pci_enable_device_mem(pdev))
2538 return result;
2539
2540 dev->entry[0].vector = pdev->irq;
2541 pci_set_master(pdev);
2542 bars = pci_select_bars(pdev, IORESOURCE_MEM);
be7837e8
JA		 2543 if (!bars)
2544 goto disable_pci;
2545
0877cb0d
KB		 2546 if (pci_request_selected_regions(pdev, bars, "nvme"))
2547 goto disable_pci;
2548
e75ec752
CH		 2549 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) &&
2550 dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32)))
052d0efa 2551 goto disable;
0877cb0d 2552
0877cb0d
KB		 2553 dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
2554 if (!dev->bar)
2555 goto disable;
e32efbfc 2556
0e53d180
KB		 2557 if (readl(&dev->bar->csts) == -1) {
2558 result = -ENODEV;
2559 goto unmap;
2560 }
e32efbfc
JA		 2561
2562 /*
2563 * Some devices don't advertse INTx interrupts, pre-enable a single
2564 * MSIX vec for setup. We'll adjust this later.
2565 */
2566 if (!pdev->irq) {
2567 result = pci_enable_msix(pdev, dev->entry, 1);
2568 if (result < 0)
2569 goto unmap;
2570 }
2571
42f61420
KB		 2572 cap = readq(&dev->bar->cap);
2573 dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH);
2574 dev->db_stride = 1 << NVME_CAP_STRIDE(cap);
0877cb0d 2575 dev->dbs = ((void __iomem *)dev->bar) + 4096;
8ffaadf7
JD		 2576 if (readl(&dev->bar->vs) >= NVME_VS(1, 2))
2577 dev->cmb = nvme_map_cmb(dev);
0877cb0d
KB		 2578
2579 return 0;
2580
0e53d180
KB		 2581 unmap:
2582 iounmap(dev->bar);
2583 dev->bar = NULL;
0877cb0d
KB		 2584 disable:
2585 pci_release_regions(pdev);
2586 disable_pci:
2587 pci_disable_device(pdev);
2588 return result;
2589}
2590
2591static void nvme_dev_unmap(struct nvme_dev *dev)
2592{
e75ec752
CH		 2593 struct pci_dev *pdev = to_pci_dev(dev->dev);
2594
2595 if (pdev->msi_enabled)
2596 pci_disable_msi(pdev);
2597 else if (pdev->msix_enabled)
2598 pci_disable_msix(pdev);
0877cb0d
KB		 2599
2600 if (dev->bar) {
2601 iounmap(dev->bar);
2602 dev->bar = NULL;
e75ec752 2603 pci_release_regions(pdev);
0877cb0d
KB		 2604 }
2605
e75ec752
CH		 2606 if (pci_is_enabled(pdev))
2607 pci_disable_device(pdev);
0877cb0d
KB		 2608}
2609
4d115420
KB		 2610struct nvme_delq_ctx {
2611 struct task_struct *waiter;
2612 struct kthread_worker *worker;
2613 atomic_t refcount;
2614};
2615
2616static void nvme_wait_dq(struct nvme_delq_ctx *dq, struct nvme_dev *dev)
2617{
2618 dq->waiter = current;
2619 mb();
2620
2621 for (;;) {
2622 set_current_state(TASK_KILLABLE);
2623 if (!atomic_read(&dq->refcount))
2624 break;
2625 if (!schedule_timeout(ADMIN_TIMEOUT) ||
2626 fatal_signal_pending(current)) {
0fb59cbc
KB		 2627 /*
2628 * Disable the controller first since we can't trust it
2629 * at this point, but leave the admin queue enabled
2630 * until all queue deletion requests are flushed.
2631 * FIXME: This may take a while if there are more h/w
2632 * queues than admin tags.
2633 */
4d115420 2634 set_current_state(TASK_RUNNING);
4d115420 2635 nvme_disable_ctrl(dev, readq(&dev->bar->cap));
0fb59cbc 2636 nvme_clear_queue(dev->queues[0]);
4d115420 2637 flush_kthread_worker(dq->worker);
0fb59cbc 2638 nvme_disable_queue(dev, 0);
4d115420
KB		 2639 return;
2640 }
2641 }
2642 set_current_state(TASK_RUNNING);
2643}
2644
2645static void nvme_put_dq(struct nvme_delq_ctx *dq)
2646{
2647 atomic_dec(&dq->refcount);
2648 if (dq->waiter)
2649 wake_up_process(dq->waiter);
2650}
2651
2652static struct nvme_delq_ctx *nvme_get_dq(struct nvme_delq_ctx *dq)
2653{
2654 atomic_inc(&dq->refcount);
2655 return dq;
2656}
2657
2658static void nvme_del_queue_end(struct nvme_queue *nvmeq)
2659{
2660 struct nvme_delq_ctx *dq = nvmeq->cmdinfo.ctx;
4d115420
KB		 2661 nvme_put_dq(dq);
2662}
2663
2664static int adapter_async_del_queue(struct nvme_queue *nvmeq, u8 opcode,
2665 kthread_work_func_t fn)
2666{
2667 struct nvme_command c;
2668
2669 memset(&c, 0, sizeof(c));
2670 c.delete_queue.opcode = opcode;
2671 c.delete_queue.qid = cpu_to_le16(nvmeq->qid);
2672
2673 init_kthread_work(&nvmeq->cmdinfo.work, fn);
a4aea562
MB		 2674 return nvme_submit_admin_async_cmd(nvmeq->dev, &c, &nvmeq->cmdinfo,
2675 ADMIN_TIMEOUT);
4d115420
KB		 2676}
2677
2678static void nvme_del_cq_work_handler(struct kthread_work *work)
2679{
2680 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2681 cmdinfo.work);
2682 nvme_del_queue_end(nvmeq);
2683}
2684
2685static int nvme_delete_cq(struct nvme_queue *nvmeq)
2686{
2687 return adapter_async_del_queue(nvmeq, nvme_admin_delete_cq,
2688 nvme_del_cq_work_handler);
2689}
2690
2691static void nvme_del_sq_work_handler(struct kthread_work *work)
2692{
2693 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2694 cmdinfo.work);
2695 int status = nvmeq->cmdinfo.status;
2696
2697 if (!status)
2698 status = nvme_delete_cq(nvmeq);
2699 if (status)
2700 nvme_del_queue_end(nvmeq);
2701}
2702
2703static int nvme_delete_sq(struct nvme_queue *nvmeq)
2704{
2705 return adapter_async_del_queue(nvmeq, nvme_admin_delete_sq,
2706 nvme_del_sq_work_handler);
2707}
2708
2709static void nvme_del_queue_start(struct kthread_work *work)
2710{
2711 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2712 cmdinfo.work);
4d115420
KB		 2713 if (nvme_delete_sq(nvmeq))
2714 nvme_del_queue_end(nvmeq);
2715}
2716
2717static void nvme_disable_io_queues(struct nvme_dev *dev)
2718{
2719 int i;
2720 DEFINE_KTHREAD_WORKER_ONSTACK(worker);
2721 struct nvme_delq_ctx dq;
2722 struct task_struct *kworker_task = kthread_run(kthread_worker_fn,
2723 &worker, "nvme%d", dev->instance);
2724
2725 if (IS_ERR(kworker_task)) {
e75ec752 2726 dev_err(dev->dev,
4d115420
KB		 2727 "Failed to create queue del task\n");
2728 for (i = dev->queue_count - 1; i > 0; i--)
2729 nvme_disable_queue(dev, i);
2730 return;
2731 }
2732
2733 dq.waiter = NULL;
2734 atomic_set(&dq.refcount, 0);
2735 dq.worker = &worker;
2736 for (i = dev->queue_count - 1; i > 0; i--) {
a4aea562 2737 struct nvme_queue *nvmeq = dev->queues[i];
4d115420
KB		 2738
2739 if (nvme_suspend_queue(nvmeq))
2740 continue;
2741 nvmeq->cmdinfo.ctx = nvme_get_dq(&dq);
2742 nvmeq->cmdinfo.worker = dq.worker;
2743 init_kthread_work(&nvmeq->cmdinfo.work, nvme_del_queue_start);
2744 queue_kthread_work(dq.worker, &nvmeq->cmdinfo.work);
2745 }
2746 nvme_wait_dq(&dq, dev);
2747 kthread_stop(kworker_task);
2748}
2749
b9afca3e
DM		 2750/*
2751* Remove the node from the device list and check
2752* for whether or not we need to stop the nvme_thread.
2753*/
2754static void nvme_dev_list_remove(struct nvme_dev *dev)
2755{
2756 struct task_struct *tmp = NULL;
2757
2758 spin_lock(&dev_list_lock);
2759 list_del_init(&dev->node);
2760 if (list_empty(&dev_list) && !IS_ERR_OR_NULL(nvme_thread)) {
2761 tmp = nvme_thread;
2762 nvme_thread = NULL;
2763 }
2764 spin_unlock(&dev_list_lock);
2765
2766 if (tmp)
2767 kthread_stop(tmp);
2768}
2769
c9d3bf88
KB		 2770static void nvme_freeze_queues(struct nvme_dev *dev)
2771{
2772 struct nvme_ns *ns;
2773
2774 list_for_each_entry(ns, &dev->namespaces, list) {
2775 blk_mq_freeze_queue_start(ns->queue);
2776
cddcd72b 2777 spin_lock_irq(ns->queue->queue_lock);
c9d3bf88 2778 queue_flag_set(QUEUE_FLAG_STOPPED, ns->queue);
cddcd72b 2779 spin_unlock_irq(ns->queue->queue_lock);
c9d3bf88
KB		 2780
2781 blk_mq_cancel_requeue_work(ns->queue);
2782 blk_mq_stop_hw_queues(ns->queue);
2783 }
2784}
2785
2786static void nvme_unfreeze_queues(struct nvme_dev *dev)
2787{
2788 struct nvme_ns *ns;
2789
2790 list_for_each_entry(ns, &dev->namespaces, list) {
2791 queue_flag_clear_unlocked(QUEUE_FLAG_STOPPED, ns->queue);
2792 blk_mq_unfreeze_queue(ns->queue);
2793 blk_mq_start_stopped_hw_queues(ns->queue, true);
2794 blk_mq_kick_requeue_list(ns->queue);
2795 }
2796}
2797
f0b50732 2798static void nvme_dev_shutdown(struct nvme_dev *dev)
b60503ba 2799{
22404274 2800 int i;
7c1b2450 2801 u32 csts = -1;
22404274 2802
b9afca3e 2803 nvme_dev_list_remove(dev);
1fa6aead 2804
c9d3bf88
KB		 2805 if (dev->bar) {
2806 nvme_freeze_queues(dev);
7c1b2450 2807 csts = readl(&dev->bar->csts);
c9d3bf88 2808 }
7c1b2450 2809 if (csts & NVME_CSTS_CFS || !(csts & NVME_CSTS_RDY)) {
4d115420 2810 for (i = dev->queue_count - 1; i >= 0; i--) {
a4aea562 2811 struct nvme_queue *nvmeq = dev->queues[i];
4d115420 2812 nvme_suspend_queue(nvmeq);
4d115420
KB		 2813 }
2814 } else {
2815 nvme_disable_io_queues(dev);
1894d8f1 2816 nvme_shutdown_ctrl(dev);
4d115420
KB		 2817 nvme_disable_queue(dev, 0);
2818 }
f0b50732 2819 nvme_dev_unmap(dev);
07836e65
KB		 2820
2821 for (i = dev->queue_count - 1; i >= 0; i--)
2822 nvme_clear_queue(dev->queues[i]);
f0b50732
KB		 2823}
2824
2825static void nvme_dev_remove(struct nvme_dev *dev)
2826{
5105aa55 2827 struct nvme_ns *ns, *next;
f0b50732 2828
5105aa55 2829 list_for_each_entry_safe(ns, next, &dev->namespaces, list)
a5768aa8 2830 nvme_ns_remove(ns);
b60503ba
MW		 2831}
2832
091b6092
MW		 2833static int nvme_setup_prp_pools(struct nvme_dev *dev)
2834{
e75ec752 2835 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
091b6092
MW		 2836 PAGE_SIZE, PAGE_SIZE, 0);
2837 if (!dev->prp_page_pool)
2838 return -ENOMEM;
2839
99802a7a 2840 /* Optimisation for I/Os between 4k and 128k */
e75ec752 2841 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
99802a7a
MW		 2842 256, 256, 0);
2843 if (!dev->prp_small_pool) {
2844 dma_pool_destroy(dev->prp_page_pool);
2845 return -ENOMEM;
2846 }
091b6092
MW		 2847 return 0;
2848}
2849
2850static void nvme_release_prp_pools(struct nvme_dev *dev)
2851{
2852 dma_pool_destroy(dev->prp_page_pool);
99802a7a 2853 dma_pool_destroy(dev->prp_small_pool);
091b6092
MW		 2854}
2855
cd58ad7d
QSA		 2856static DEFINE_IDA(nvme_instance_ida);
2857
2858static int nvme_set_instance(struct nvme_dev *dev)
b60503ba 2859{
cd58ad7d
QSA		 2860 int instance, error;
2861
2862 do {
2863 if (!ida_pre_get(&nvme_instance_ida, GFP_KERNEL))
2864 return -ENODEV;
2865
2866 spin_lock(&dev_list_lock);
2867 error = ida_get_new(&nvme_instance_ida, &instance);
2868 spin_unlock(&dev_list_lock);
2869 } while (error == -EAGAIN);
2870
2871 if (error)
2872 return -ENODEV;
2873
2874 dev->instance = instance;
2875 return 0;
b60503ba
MW		 2876}
2877
2878static void nvme_release_instance(struct nvme_dev *dev)
2879{
cd58ad7d
QSA		 2880 spin_lock(&dev_list_lock);
2881 ida_remove(&nvme_instance_ida, dev->instance);
2882 spin_unlock(&dev_list_lock);
b60503ba
MW		 2883}
2884
5e82e952
KB		 2885static void nvme_free_dev(struct kref *kref)
2886{
2887 struct nvme_dev *dev = container_of(kref, struct nvme_dev, kref);
9ac27090 2888
e75ec752 2889 put_device(dev->dev);
b3fffdef 2890 put_device(dev->device);
285dffc9 2891 nvme_release_instance(dev);
4af0e21c
KB		 2892 if (dev->tagset.tags)
2893 blk_mq_free_tag_set(&dev->tagset);
2894 if (dev->admin_q)
2895 blk_put_queue(dev->admin_q);
5e82e952
KB		 2896 kfree(dev->queues);
2897 kfree(dev->entry);
2898 kfree(dev);
2899}
2900
2901static int nvme_dev_open(struct inode *inode, struct file *f)
2902{
b3fffdef
KB		 2903 struct nvme_dev *dev;
2904 int instance = iminor(inode);
2905 int ret = -ENODEV;
2906
2907 spin_lock(&dev_list_lock);
2908 list_for_each_entry(dev, &dev_list, node) {
2909 if (dev->instance == instance) {
2e1d8448
KB		 2910 if (!dev->admin_q) {
2911 ret = -EWOULDBLOCK;
2912 break;
2913 }
b3fffdef
KB		 2914 if (!kref_get_unless_zero(&dev->kref))
2915 break;
2916 f->private_data = dev;
2917 ret = 0;
2918 break;
2919 }
2920 }
2921 spin_unlock(&dev_list_lock);
2922
2923 return ret;
5e82e952
KB		 2924}
2925
2926static int nvme_dev_release(struct inode *inode, struct file *f)
2927{
2928 struct nvme_dev *dev = f->private_data;
2929 kref_put(&dev->kref, nvme_free_dev);
2930 return 0;
2931}
2932
2933static long nvme_dev_ioctl(struct file *f, unsigned int cmd, unsigned long arg)
2934{
2935 struct nvme_dev *dev = f->private_data;
a4aea562
MB		 2936 struct nvme_ns *ns;
2937
5e82e952
KB		 2938 switch (cmd) {
2939 case NVME_IOCTL_ADMIN_CMD:
a4aea562 2940 return nvme_user_cmd(dev, NULL, (void __user *)arg);
7963e521 2941 case NVME_IOCTL_IO_CMD:
a4aea562
MB		 2942 if (list_empty(&dev->namespaces))
2943 return -ENOTTY;
2944 ns = list_first_entry(&dev->namespaces, struct nvme_ns, list);
2945 return nvme_user_cmd(dev, ns, (void __user *)arg);
4cc06521
KB		 2946 case NVME_IOCTL_RESET:
2947 dev_warn(dev->dev, "resetting controller\n");
2948 return nvme_reset(dev);
81f03fed
JD		 2949 case NVME_IOCTL_SUBSYS_RESET:
2950 return nvme_subsys_reset(dev);
5e82e952
KB		 2951 default:
2952 return -ENOTTY;
2953 }
2954}
2955
2956static const struct file_operations nvme_dev_fops = {
2957 .owner = THIS_MODULE,
2958 .open = nvme_dev_open,
2959 .release = nvme_dev_release,
2960 .unlocked_ioctl = nvme_dev_ioctl,
2961 .compat_ioctl = nvme_dev_ioctl,
2962};
2963
3cf519b5 2964static void nvme_probe_work(struct work_struct *work)
f0b50732 2965{
3cf519b5 2966 struct nvme_dev *dev = container_of(work, struct nvme_dev, probe_work);
b9afca3e 2967 bool start_thread = false;
3cf519b5 2968 int result;
f0b50732
KB		 2969
2970 result = nvme_dev_map(dev);
2971 if (result)
3cf519b5 2972 goto out;
f0b50732
KB		 2973
2974 result = nvme_configure_admin_queue(dev);
2975 if (result)
2976 goto unmap;
2977
2978 spin_lock(&dev_list_lock);
b9afca3e
DM		 2979 if (list_empty(&dev_list) && IS_ERR_OR_NULL(nvme_thread)) {
2980 start_thread = true;
2981 nvme_thread = NULL;
2982 }
f0b50732
KB		 2983 list_add(&dev->node, &dev_list);
2984 spin_unlock(&dev_list_lock);
2985
b9afca3e
DM		 2986 if (start_thread) {
2987 nvme_thread = kthread_run(nvme_kthread, NULL, "nvme");
387caa5a 2988 wake_up_all(&nvme_kthread_wait);
b9afca3e
DM		 2989 } else
2990 wait_event_killable(nvme_kthread_wait, nvme_thread);
2991
2992 if (IS_ERR_OR_NULL(nvme_thread)) {
2993 result = nvme_thread ? PTR_ERR(nvme_thread) : -EINTR;
2994 goto disable;
2995 }
a4aea562
MB		 2996
2997 nvme_init_queue(dev->queues[0], 0);
0fb59cbc
KB		 2998 result = nvme_alloc_admin_tags(dev);
2999 if (result)
3000 goto disable;
b9afca3e 3001
f0b50732 3002 result = nvme_setup_io_queues(dev);
badc34d4 3003 if (result)
0fb59cbc 3004 goto free_tags;
f0b50732 3005
1efccc9d 3006 dev->event_limit = 1;
3cf519b5 3007
2659e57b
CH		 3008 /*
3009 * Keep the controller around but remove all namespaces if we don't have
3010 * any working I/O queue.
3011 */
3cf519b5
CH		 3012 if (dev->online_queues < 2) {
3013 dev_warn(dev->dev, "IO queues not created\n");
3cf519b5
CH		 3014 nvme_dev_remove(dev);
3015 } else {
3016 nvme_unfreeze_queues(dev);
3017 nvme_dev_add(dev);
3018 }
3019
3020 return;
f0b50732 3021
0fb59cbc
KB		 3022 free_tags:
3023 nvme_dev_remove_admin(dev);
4af0e21c
KB		 3024 blk_put_queue(dev->admin_q);
3025 dev->admin_q = NULL;
3026 dev->queues[0]->tags = NULL;
f0b50732 3027 disable:
a1a5ef99 3028 nvme_disable_queue(dev, 0);
b9afca3e 3029 nvme_dev_list_remove(dev);
f0b50732
KB		 3030 unmap:
3031 nvme_dev_unmap(dev);
3cf519b5
CH		 3032 out:
3033 if (!work_busy(&dev->reset_work))
3034 nvme_dead_ctrl(dev);
f0b50732
KB		 3035}
3036
9a6b9458
KB		 3037static int nvme_remove_dead_ctrl(void *arg)
3038{
3039 struct nvme_dev *dev = (struct nvme_dev *)arg;
e75ec752 3040 struct pci_dev *pdev = to_pci_dev(dev->dev);
9a6b9458
KB		 3041
3042 if (pci_get_drvdata(pdev))
c81f4975 3043 pci_stop_and_remove_bus_device_locked(pdev);
9a6b9458
KB		 3044 kref_put(&dev->kref, nvme_free_dev);
3045 return 0;
3046}
3047
de3eff2b
KB		 3048static void nvme_dead_ctrl(struct nvme_dev *dev)
3049{
3050 dev_warn(dev->dev, "Device failed to resume\n");
3051 kref_get(&dev->kref);
3052 if (IS_ERR(kthread_run(nvme_remove_dead_ctrl, dev, "nvme%d",
3053 dev->instance))) {
3054 dev_err(dev->dev,
3055 "Failed to start controller remove task\n");
3056 kref_put(&dev->kref, nvme_free_dev);
3057 }
3058}
3059
77b50d9e 3060static void nvme_reset_work(struct work_struct *ws)
9a6b9458 3061{
77b50d9e 3062 struct nvme_dev *dev = container_of(ws, struct nvme_dev, reset_work);
ffe7704d
KB		 3063 bool in_probe = work_busy(&dev->probe_work);
3064
9a6b9458 3065 nvme_dev_shutdown(dev);
ffe7704d
KB		 3066
3067 /* Synchronize with device probe so that work will see failure status
3068 * and exit gracefully without trying to schedule another reset */
3069 flush_work(&dev->probe_work);
3070
3071 /* Fail this device if reset occured during probe to avoid
3072 * infinite initialization loops. */
3073 if (in_probe) {
de3eff2b 3074 nvme_dead_ctrl(dev);
ffe7704d 3075 return;
9a6b9458 3076 }
ffe7704d
KB		 3077 /* Schedule device resume asynchronously so the reset work is available
3078 * to cleanup errors that may occur during reinitialization */
3079 schedule_work(&dev->probe_work);
9a6b9458
KB		 3080}
3081
90667892
CH		 3082static int __nvme_reset(struct nvme_dev *dev)
3083{
3084 if (work_pending(&dev->reset_work))
3085 return -EBUSY;
3086 list_del_init(&dev->node);
3087 queue_work(nvme_workq, &dev->reset_work);
3088 return 0;
3089}
3090
4cc06521
KB		 3091static int nvme_reset(struct nvme_dev *dev)
3092{
90667892 3093 int ret;
4cc06521
KB		 3094
3095 if (!dev->admin_q || blk_queue_dying(dev->admin_q))
3096 return -ENODEV;
3097
3098 spin_lock(&dev_list_lock);
90667892 3099 ret = __nvme_reset(dev);
4cc06521
KB		 3100 spin_unlock(&dev_list_lock);
3101
3102 if (!ret) {
3103 flush_work(&dev->reset_work);
ffe7704d 3104 flush_work(&dev->probe_work);
4cc06521
KB		 3105 return 0;
3106 }
3107
3108 return ret;
3109}
3110
3111static ssize_t nvme_sysfs_reset(struct device *dev,
3112 struct device_attribute *attr, const char *buf,
3113 size_t count)
3114{
3115 struct nvme_dev *ndev = dev_get_drvdata(dev);
3116 int ret;
3117
3118 ret = nvme_reset(ndev);
3119 if (ret < 0)
3120 return ret;
3121
3122 return count;
3123}
3124static DEVICE_ATTR(reset_controller, S_IWUSR, NULL, nvme_sysfs_reset);
3125
8d85fce7 3126static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
b60503ba 3127{
a4aea562 3128 int node, result = -ENOMEM;
b60503ba
MW		 3129 struct nvme_dev *dev;
3130
a4aea562
MB		 3131 node = dev_to_node(&pdev->dev);
3132 if (node == NUMA_NO_NODE)
3133 set_dev_node(&pdev->dev, 0);
3134
3135 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
b60503ba
MW		 3136 if (!dev)
3137 return -ENOMEM;
a4aea562
MB		 3138 dev->entry = kzalloc_node(num_possible_cpus() * sizeof(*dev->entry),
3139 GFP_KERNEL, node);
b60503ba
MW		 3140 if (!dev->entry)
3141 goto free;
a4aea562
MB		 3142 dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *),
3143 GFP_KERNEL, node);
b60503ba
MW		 3144 if (!dev->queues)
3145 goto free;
3146
3147 INIT_LIST_HEAD(&dev->namespaces);
77b50d9e 3148 INIT_WORK(&dev->reset_work, nvme_reset_work);
e75ec752 3149 dev->dev = get_device(&pdev->dev);
9a6b9458 3150 pci_set_drvdata(pdev, dev);
cd58ad7d
QSA		 3151 result = nvme_set_instance(dev);
3152 if (result)
a96d4f5c 3153 goto put_pci;
b60503ba 3154
091b6092
MW		 3155 result = nvme_setup_prp_pools(dev);
3156 if (result)
0877cb0d 3157 goto release;
091b6092 3158
fb35e914 3159 kref_init(&dev->kref);
b3fffdef
KB		 3160 dev->device = device_create(nvme_class, &pdev->dev,
3161 MKDEV(nvme_char_major, dev->instance),
3162 dev, "nvme%d", dev->instance);
3163 if (IS_ERR(dev->device)) {
3164 result = PTR_ERR(dev->device);
2e1d8448 3165 goto release_pools;
b3fffdef
KB		 3166 }
3167 get_device(dev->device);
4cc06521
KB		 3168 dev_set_drvdata(dev->device, dev);
3169
3170 result = device_create_file(dev->device, &dev_attr_reset_controller);
3171 if (result)
3172 goto put_dev;
740216fc 3173
e6e96d73 3174 INIT_LIST_HEAD(&dev->node);
a5768aa8 3175 INIT_WORK(&dev->scan_work, nvme_dev_scan);
3cf519b5 3176 INIT_WORK(&dev->probe_work, nvme_probe_work);
2e1d8448 3177 schedule_work(&dev->probe_work);
b60503ba
MW		 3178 return 0;
3179
4cc06521
KB		 3180 put_dev:
3181 device_destroy(nvme_class, MKDEV(nvme_char_major, dev->instance));
3182 put_device(dev->device);
0877cb0d 3183 release_pools:
091b6092 3184 nvme_release_prp_pools(dev);
0877cb0d
KB		 3185 release:
3186 nvme_release_instance(dev);
a96d4f5c 3187 put_pci:
e75ec752 3188 put_device(dev->dev);
b60503ba
MW		 3189 free:
3190 kfree(dev->queues);
3191 kfree(dev->entry);
3192 kfree(dev);
3193 return result;
3194}
3195
f0d54a54
KB		 3196static void nvme_reset_notify(struct pci_dev *pdev, bool prepare)
3197{
a6739479 3198 struct nvme_dev *dev = pci_get_drvdata(pdev);
f0d54a54 3199
a6739479
KB		 3200 if (prepare)
3201 nvme_dev_shutdown(dev);
3202 else
0a7385ad 3203 schedule_work(&dev->probe_work);
f0d54a54
KB		 3204}
3205
09ece142
KB		 3206static void nvme_shutdown(struct pci_dev *pdev)
3207{
3208 struct nvme_dev *dev = pci_get_drvdata(pdev);
3209 nvme_dev_shutdown(dev);
3210}
3211
8d85fce7 3212static void nvme_remove(struct pci_dev *pdev)
b60503ba
MW		 3213{
3214 struct nvme_dev *dev = pci_get_drvdata(pdev);
9a6b9458
KB		 3215
3216 spin_lock(&dev_list_lock);
3217 list_del_init(&dev->node);
3218 spin_unlock(&dev_list_lock);
3219
3220 pci_set_drvdata(pdev, NULL);
2e1d8448 3221 flush_work(&dev->probe_work);
9a6b9458 3222 flush_work(&dev->reset_work);
a5768aa8 3223 flush_work(&dev->scan_work);
4cc06521 3224 device_remove_file(dev->device, &dev_attr_reset_controller);
c9d3bf88 3225 nvme_dev_remove(dev);
3399a3f7 3226 nvme_dev_shutdown(dev);
a4aea562 3227 nvme_dev_remove_admin(dev);
b3fffdef 3228 device_destroy(nvme_class, MKDEV(nvme_char_major, dev->instance));
a1a5ef99 3229 nvme_free_queues(dev, 0);
8ffaadf7 3230 nvme_release_cmb(dev);
9a6b9458 3231 nvme_release_prp_pools(dev);
5e82e952 3232 kref_put(&dev->kref, nvme_free_dev);
b60503ba
MW		 3233}
3234
3235/* These functions are yet to be implemented */
3236#define nvme_error_detected NULL
3237#define nvme_dump_registers NULL
3238#define nvme_link_reset NULL
3239#define nvme_slot_reset NULL
3240#define nvme_error_resume NULL
cd638946 3241
671a6018 3242#ifdef CONFIG_PM_SLEEP
cd638946
KB		 3243static int nvme_suspend(struct device *dev)
3244{
3245 struct pci_dev *pdev = to_pci_dev(dev);
3246 struct nvme_dev *ndev = pci_get_drvdata(pdev);
3247
3248 nvme_dev_shutdown(ndev);
3249 return 0;
3250}
3251
3252static int nvme_resume(struct device *dev)
3253{
3254 struct pci_dev *pdev = to_pci_dev(dev);
3255 struct nvme_dev *ndev = pci_get_drvdata(pdev);
cd638946 3256
0a7385ad 3257 schedule_work(&ndev->probe_work);
9a6b9458 3258 return 0;
cd638946 3259}
671a6018 3260#endif
cd638946
KB		 3261
3262static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
b60503ba 3263
1d352035 3264static const struct pci_error_handlers nvme_err_handler = {
b60503ba
MW		 3265 .error_detected = nvme_error_detected,
3266 .mmio_enabled = nvme_dump_registers,
3267 .link_reset = nvme_link_reset,
3268 .slot_reset = nvme_slot_reset,
3269 .resume = nvme_error_resume,
f0d54a54 3270 .reset_notify = nvme_reset_notify,
b60503ba
MW		 3271};
3272
3273/* Move to pci_ids.h later */
3274#define PCI_CLASS_STORAGE_EXPRESS 0x010802
3275
6eb0d698 3276static const struct pci_device_id nvme_id_table[] = {
b60503ba
MW		 3277 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
3278 { 0, }
3279};
3280MODULE_DEVICE_TABLE(pci, nvme_id_table);
3281
3282static struct pci_driver nvme_driver = {
3283 .name = "nvme",
3284 .id_table = nvme_id_table,
3285 .probe = nvme_probe,
8d85fce7 3286 .remove = nvme_remove,
09ece142 3287 .shutdown = nvme_shutdown,
cd638946
KB		 3288 .driver = {
3289 .pm = &nvme_dev_pm_ops,
3290 },
b60503ba
MW		 3291 .err_handler = &nvme_err_handler,
3292};
3293
3294static int __init nvme_init(void)
3295{
0ac13140 3296 int result;
1fa6aead 3297
b9afca3e 3298 init_waitqueue_head(&nvme_kthread_wait);
b60503ba 3299
9a6b9458
KB		 3300 nvme_workq = create_singlethread_workqueue("nvme");
3301 if (!nvme_workq)
b9afca3e 3302 return -ENOMEM;
9a6b9458 3303
5c42ea16
KB		 3304 result = register_blkdev(nvme_major, "nvme");
3305 if (result < 0)
9a6b9458 3306 goto kill_workq;
5c42ea16 3307 else if (result > 0)
0ac13140 3308 nvme_major = result;
b60503ba 3309
b3fffdef
KB		 3310 result = __register_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme",
3311 &nvme_dev_fops);
3312 if (result < 0)
3313 goto unregister_blkdev;
3314 else if (result > 0)
3315 nvme_char_major = result;
3316
3317 nvme_class = class_create(THIS_MODULE, "nvme");
c727040b
AK		 3318 if (IS_ERR(nvme_class)) {
3319 result = PTR_ERR(nvme_class);
b3fffdef 3320 goto unregister_chrdev;
c727040b 3321 }
b3fffdef 3322
f3db22fe
KB		 3323 result = pci_register_driver(&nvme_driver);
3324 if (result)
b3fffdef 3325 goto destroy_class;
1fa6aead 3326 return 0;
b60503ba 3327
b3fffdef
KB		 3328 destroy_class:
3329 class_destroy(nvme_class);
3330 unregister_chrdev:
3331 __unregister_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme");
1fa6aead 3332 unregister_blkdev:
b60503ba 3333 unregister_blkdev(nvme_major, "nvme");
9a6b9458
KB		 3334 kill_workq:
3335 destroy_workqueue(nvme_workq);
b60503ba
MW		 3336 return result;
3337}
3338
3339static void __exit nvme_exit(void)
3340{
3341 pci_unregister_driver(&nvme_driver);
3342 unregister_blkdev(nvme_major, "nvme");
9a6b9458 3343 destroy_workqueue(nvme_workq);
b3fffdef
KB		 3344 class_destroy(nvme_class);
3345 __unregister_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme");
b9afca3e 3346 BUG_ON(nvme_thread && !IS_ERR(nvme_thread));
21bd78bc 3347 _nvme_check_size();
b60503ba
MW		 3348}
3349
3350MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3351MODULE_LICENSE("GPL");
c78b4713 3352MODULE_VERSION("1.0");
b60503ba
MW		 3353module_init(nvme_init);
3354module_exit(nvme_exit);
Linux 6.x block layer and io_uring tree(s)