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Merge branch 'nvme-4.15' of git://git.infradead.org/nvme into for-linus
[linux-2.6-block.git] / drivers / nvme / host / pci.c
CommitLineData
b60503ba
MW		 1/*
2 * NVM Express device driver
6eb0d698 3 * Copyright (c) 2011-2014, Intel Corporation.
b60503ba
MW		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
b60503ba
MW		 13 */
14
a0a3408e 15#include <linux/aer.h>
b60503ba 16#include <linux/blkdev.h>
a4aea562 17#include <linux/blk-mq.h>
dca51e78 18#include <linux/blk-mq-pci.h>
ff5350a8 19#include <linux/dmi.h>
b60503ba
MW		 20#include <linux/init.h>
21#include <linux/interrupt.h>
22#include <linux/io.h>
b60503ba
MW		 23#include <linux/mm.h>
24#include <linux/module.h>
77bf25ea 25#include <linux/mutex.h>
d0877473 26#include <linux/once.h>
b60503ba 27#include <linux/pci.h>
e1e5e564 28#include <linux/t10-pi.h>
b60503ba 29#include <linux/types.h>
2f8e2c87 30#include <linux/io-64-nonatomic-lo-hi.h>
a98e58e5 31#include <linux/sed-opal.h>
797a796a 32
f11bb3e2
CH		 33#include "nvme.h"
34
b60503ba
MW		 35#define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
36#define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
c965809c 37
a7a7cbe3 38#define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc))
9d43cf64 39
58ffacb5
MW		 40static int use_threaded_interrupts;
41module_param(use_threaded_interrupts, int, 0);
42
8ffaadf7
JD		 43static bool use_cmb_sqes = true;
44module_param(use_cmb_sqes, bool, 0644);
45MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
46
87ad72a5
CH		 47static unsigned int max_host_mem_size_mb = 128;
48module_param(max_host_mem_size_mb, uint, 0444);
49MODULE_PARM_DESC(max_host_mem_size_mb,
50 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
1fa6aead 51
a7a7cbe3
CK		 52static unsigned int sgl_threshold = SZ_32K;
53module_param(sgl_threshold, uint, 0644);
54MODULE_PARM_DESC(sgl_threshold,
55 "Use SGLs when average request segment size is larger or equal to "
56 "this size. Use 0 to disable SGLs.");
57
b27c1e68 58static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
59static const struct kernel_param_ops io_queue_depth_ops = {
60 .set = io_queue_depth_set,
61 .get = param_get_int,
62};
63
64static int io_queue_depth = 1024;
65module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
66MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2");
67
1c63dc66
CH		 68struct nvme_dev;
69struct nvme_queue;
b3fffdef 70
a0fa9647 71static void nvme_process_cq(struct nvme_queue *nvmeq);
a5cdb68c 72static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
d4b4ff8e 73
1c63dc66
CH		 74/*
75 * Represents an NVM Express device. Each nvme_dev is a PCI function.
76 */
77struct nvme_dev {
1c63dc66
CH		 78 struct nvme_queue **queues;
79 struct blk_mq_tag_set tagset;
80 struct blk_mq_tag_set admin_tagset;
81 u32 __iomem *dbs;
82 struct device *dev;
83 struct dma_pool *prp_page_pool;
84 struct dma_pool *prp_small_pool;
1c63dc66
CH		 85 unsigned online_queues;
86 unsigned max_qid;
87 int q_depth;
88 u32 db_stride;
1c63dc66 89 void __iomem *bar;
97f6ef64 90 unsigned long bar_mapped_size;
5c8809e6 91 struct work_struct remove_work;
77bf25ea 92 struct mutex shutdown_lock;
1c63dc66 93 bool subsystem;
1c63dc66 94 void __iomem *cmb;
8969f1f8 95 pci_bus_addr_t cmb_bus_addr;
1c63dc66
CH		 96 u64 cmb_size;
97 u32 cmbsz;
202021c1 98 u32 cmbloc;
1c63dc66 99 struct nvme_ctrl ctrl;
db3cbfff 100 struct completion ioq_wait;
87ad72a5
CH		 101
102 /* shadow doorbell buffer support: */
f9f38e33
HK		 103 u32 *dbbuf_dbs;
104 dma_addr_t dbbuf_dbs_dma_addr;
105 u32 *dbbuf_eis;
106 dma_addr_t dbbuf_eis_dma_addr;
87ad72a5
CH		 107
108 /* host memory buffer support: */
109 u64 host_mem_size;
110 u32 nr_host_mem_descs;
4033f35d 111 dma_addr_t host_mem_descs_dma;
87ad72a5
CH		 112 struct nvme_host_mem_buf_desc *host_mem_descs;
113 void **host_mem_desc_bufs;
4d115420 114};
1fa6aead 115
b27c1e68 116static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
117{
118 int n = 0, ret;
119
120 ret = kstrtoint(val, 10, &n);
121 if (ret != 0 || n < 2)
122 return -EINVAL;
123
124 return param_set_int(val, kp);
125}
126
f9f38e33
HK		 127static inline unsigned int sq_idx(unsigned int qid, u32 stride)
128{
129 return qid * 2 * stride;
130}
131
132static inline unsigned int cq_idx(unsigned int qid, u32 stride)
133{
134 return (qid * 2 + 1) * stride;
135}
136
1c63dc66
CH		 137static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
138{
139 return container_of(ctrl, struct nvme_dev, ctrl);
140}
141
b60503ba
MW		 142/*
143 * An NVM Express queue. Each device has at least two (one for admin
144 * commands and one for I/O commands).
145 */
146struct nvme_queue {
147 struct device *q_dmadev;
091b6092 148 struct nvme_dev *dev;
b60503ba
MW		 149 spinlock_t q_lock;
150 struct nvme_command *sq_cmds;
8ffaadf7 151 struct nvme_command __iomem *sq_cmds_io;
b60503ba 152 volatile struct nvme_completion *cqes;
42483228 153 struct blk_mq_tags **tags;
b60503ba
MW		 154 dma_addr_t sq_dma_addr;
155 dma_addr_t cq_dma_addr;
b60503ba
MW		 156 u32 __iomem *q_db;
157 u16 q_depth;
6222d172 158 s16 cq_vector;
b60503ba
MW		 159 u16 sq_tail;
160 u16 cq_head;
c30341dc 161 u16 qid;
e9539f47
MW		 162 u8 cq_phase;
163 u8 cqe_seen;
f9f38e33
HK		 164 u32 *dbbuf_sq_db;
165 u32 *dbbuf_cq_db;
166 u32 *dbbuf_sq_ei;
167 u32 *dbbuf_cq_ei;
b60503ba
MW		 168};
169
71bd150c
CH		 170/*
171 * The nvme_iod describes the data in an I/O, including the list of PRP
172 * entries. You can't see it in this data structure because C doesn't let
f4800d6d 173 * me express that. Use nvme_init_iod to ensure there's enough space
71bd150c
CH		 174 * allocated to store the PRP list.
175 */
176struct nvme_iod {
d49187e9 177 struct nvme_request req;
f4800d6d 178 struct nvme_queue *nvmeq;
a7a7cbe3 179 bool use_sgl;
f4800d6d 180 int aborted;
71bd150c 181 int npages; /* In the PRP list. 0 means small pool in use */
71bd150c
CH		 182 int nents; /* Used in scatterlist */
183 int length; /* Of data, in bytes */
184 dma_addr_t first_dma;
bf684057 185 struct scatterlist meta_sg; /* metadata requires single contiguous buffer */
f4800d6d
CH		 186 struct scatterlist *sg;
187 struct scatterlist inline_sg[0];
b60503ba
MW		 188};
189
190/*
191 * Check we didin't inadvertently grow the command struct
192 */
193static inline void _nvme_check_size(void)
194{
195 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
196 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
197 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
198 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
199 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
f8ebf840 200 BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
c30341dc 201 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
b60503ba 202 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
0add5e8e
JT		 203 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != NVME_IDENTIFY_DATA_SIZE);
204 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != NVME_IDENTIFY_DATA_SIZE);
b60503ba 205 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
6ecec745 206 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
f9f38e33
HK		 207 BUILD_BUG_ON(sizeof(struct nvme_dbbuf) != 64);
208}
209
210static inline unsigned int nvme_dbbuf_size(u32 stride)
211{
212 return ((num_possible_cpus() + 1) * 8 * stride);
213}
214
215static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
216{
217 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
218
219 if (dev->dbbuf_dbs)
220 return 0;
221
222 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
223 &dev->dbbuf_dbs_dma_addr,
224 GFP_KERNEL);
225 if (!dev->dbbuf_dbs)
226 return -ENOMEM;
227 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
228 &dev->dbbuf_eis_dma_addr,
229 GFP_KERNEL);
230 if (!dev->dbbuf_eis) {
231 dma_free_coherent(dev->dev, mem_size,
232 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
233 dev->dbbuf_dbs = NULL;
234 return -ENOMEM;
235 }
236
237 return 0;
238}
239
240static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
241{
242 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
243
244 if (dev->dbbuf_dbs) {
245 dma_free_coherent(dev->dev, mem_size,
246 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
247 dev->dbbuf_dbs = NULL;
248 }
249 if (dev->dbbuf_eis) {
250 dma_free_coherent(dev->dev, mem_size,
251 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
252 dev->dbbuf_eis = NULL;
253 }
254}
255
256static void nvme_dbbuf_init(struct nvme_dev *dev,
257 struct nvme_queue *nvmeq, int qid)
258{
259 if (!dev->dbbuf_dbs || !qid)
260 return;
261
262 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
263 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
264 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
265 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
266}
267
268static void nvme_dbbuf_set(struct nvme_dev *dev)
269{
270 struct nvme_command c;
271
272 if (!dev->dbbuf_dbs)
273 return;
274
275 memset(&c, 0, sizeof(c));
276 c.dbbuf.opcode = nvme_admin_dbbuf;
277 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
278 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
279
280 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
9bdcfb10 281 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
f9f38e33
HK		 282 /* Free memory and continue on */
283 nvme_dbbuf_dma_free(dev);
284 }
285}
286
287static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
288{
289 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
290}
291
292/* Update dbbuf and return true if an MMIO is required */
293static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
294 volatile u32 *dbbuf_ei)
295{
296 if (dbbuf_db) {
297 u16 old_value;
298
299 /*
300 * Ensure that the queue is written before updating
301 * the doorbell in memory
302 */
303 wmb();
304
305 old_value = *dbbuf_db;
306 *dbbuf_db = value;
307
308 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value))
309 return false;
310 }
311
312 return true;
b60503ba
MW		 313}
314
ac3dd5bd
JA		 315/*
316 * Max size of iod being embedded in the request payload
317 */
318#define NVME_INT_PAGES 2
5fd4ce1b 319#define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size)
ac3dd5bd
JA		 320
321/*
322 * Will slightly overestimate the number of pages needed. This is OK
323 * as it only leads to a small amount of wasted memory for the lifetime of
324 * the I/O.
325 */
326static int nvme_npages(unsigned size, struct nvme_dev *dev)
327{
5fd4ce1b
CH		 328 unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size,
329 dev->ctrl.page_size);
ac3dd5bd
JA		 330 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
331}
332
a7a7cbe3
CK		 333/*
334 * Calculates the number of pages needed for the SGL segments. For example a 4k
335 * page can accommodate 256 SGL descriptors.
336 */
337static int nvme_pci_npages_sgl(unsigned int num_seg)
ac3dd5bd 338{
a7a7cbe3 339 return DIV_ROUND_UP(num_seg * sizeof(struct nvme_sgl_desc), PAGE_SIZE);
f4800d6d 340}
ac3dd5bd 341
a7a7cbe3
CK		 342static unsigned int nvme_pci_iod_alloc_size(struct nvme_dev *dev,
343 unsigned int size, unsigned int nseg, bool use_sgl)
f4800d6d 344{
a7a7cbe3
CK		 345 size_t alloc_size;
346
347 if (use_sgl)
348 alloc_size = sizeof(__le64 *) * nvme_pci_npages_sgl(nseg);
349 else
350 alloc_size = sizeof(__le64 *) * nvme_npages(size, dev);
351
352 return alloc_size + sizeof(struct scatterlist) * nseg;
f4800d6d 353}
ac3dd5bd 354
a7a7cbe3 355static unsigned int nvme_pci_cmd_size(struct nvme_dev *dev, bool use_sgl)
f4800d6d 356{
a7a7cbe3
CK		 357 unsigned int alloc_size = nvme_pci_iod_alloc_size(dev,
358 NVME_INT_BYTES(dev), NVME_INT_PAGES,
359 use_sgl);
360
361 return sizeof(struct nvme_iod) + alloc_size;
ac3dd5bd
JA		 362}
363
a4aea562
MB		 364static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
365 unsigned int hctx_idx)
e85248e5 366{
a4aea562
MB		 367 struct nvme_dev *dev = data;
368 struct nvme_queue *nvmeq = dev->queues[0];
369
42483228
KB		 370 WARN_ON(hctx_idx != 0);
371 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
372 WARN_ON(nvmeq->tags);
373
a4aea562 374 hctx->driver_data = nvmeq;
42483228 375 nvmeq->tags = &dev->admin_tagset.tags[0];
a4aea562 376 return 0;
e85248e5
MW		 377}
378
4af0e21c
KB		 379static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
380{
381 struct nvme_queue *nvmeq = hctx->driver_data;
382
383 nvmeq->tags = NULL;
384}
385
a4aea562
MB		 386static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
387 unsigned int hctx_idx)
b60503ba 388{
a4aea562 389 struct nvme_dev *dev = data;
42483228 390 struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
a4aea562 391
42483228
KB		 392 if (!nvmeq->tags)
393 nvmeq->tags = &dev->tagset.tags[hctx_idx];
b60503ba 394
42483228 395 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
a4aea562
MB		 396 hctx->driver_data = nvmeq;
397 return 0;
b60503ba
MW		 398}
399
d6296d39
CH		 400static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req,
401 unsigned int hctx_idx, unsigned int numa_node)
b60503ba 402{
d6296d39 403 struct nvme_dev *dev = set->driver_data;
f4800d6d 404 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
0350815a
CH		 405 int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0;
406 struct nvme_queue *nvmeq = dev->queues[queue_idx];
a4aea562
MB		 407
408 BUG_ON(!nvmeq);
f4800d6d 409 iod->nvmeq = nvmeq;
a4aea562
MB		 410 return 0;
411}
412
dca51e78
CH		 413static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
414{
415 struct nvme_dev *dev = set->driver_data;
416
417 return blk_mq_pci_map_queues(set, to_pci_dev(dev->dev));
418}
419
b60503ba 420/**
adf68f21 421 * __nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
b60503ba
MW		 422 * @nvmeq: The queue to use
423 * @cmd: The command to send
424 *
425 * Safe to use from interrupt context
426 */
e3f879bf
SB		 427static void __nvme_submit_cmd(struct nvme_queue *nvmeq,
428 struct nvme_command *cmd)
b60503ba 429{
a4aea562
MB		 430 u16 tail = nvmeq->sq_tail;
431
8ffaadf7
JD		 432 if (nvmeq->sq_cmds_io)
433 memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd));
434 else
435 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
436
b60503ba
MW		 437 if (++tail == nvmeq->q_depth)
438 tail = 0;
f9f38e33
HK		 439 if (nvme_dbbuf_update_and_check_event(tail, nvmeq->dbbuf_sq_db,
440 nvmeq->dbbuf_sq_ei))
441 writel(tail, nvmeq->q_db);
b60503ba 442 nvmeq->sq_tail = tail;
b60503ba
MW		 443}
444
a7a7cbe3 445static void **nvme_pci_iod_list(struct request *req)
b60503ba 446{
f4800d6d 447 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3 448 return (void **)(iod->sg + blk_rq_nr_phys_segments(req));
b60503ba
MW		 449}
450
955b1b5a
MI		 451static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req)
452{
453 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
454 unsigned int avg_seg_size;
455
456 avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req),
457 blk_rq_nr_phys_segments(req));
458
459 if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1))))
460 return false;
461 if (!iod->nvmeq->qid)
462 return false;
463 if (!sgl_threshold || avg_seg_size < sgl_threshold)
464 return false;
465 return true;
466}
467
fc17b653 468static blk_status_t nvme_init_iod(struct request *rq, struct nvme_dev *dev)
ac3dd5bd 469{
f4800d6d 470 struct nvme_iod *iod = blk_mq_rq_to_pdu(rq);
f9d03f96 471 int nseg = blk_rq_nr_phys_segments(rq);
b131c61d 472 unsigned int size = blk_rq_payload_bytes(rq);
ac3dd5bd 473
955b1b5a
MI		 474 iod->use_sgl = nvme_pci_use_sgls(dev, rq);
475
f4800d6d 476 if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) {
a7a7cbe3
CK		 477 size_t alloc_size = nvme_pci_iod_alloc_size(dev, size, nseg,
478 iod->use_sgl);
479
480 iod->sg = kmalloc(alloc_size, GFP_ATOMIC);
f4800d6d 481 if (!iod->sg)
fc17b653 482 return BLK_STS_RESOURCE;
f4800d6d
CH		 483 } else {
484 iod->sg = iod->inline_sg;
ac3dd5bd
JA		 485 }
486
f4800d6d
CH		 487 iod->aborted = 0;
488 iod->npages = -1;
489 iod->nents = 0;
490 iod->length = size;
f80ec966 491
fc17b653 492 return BLK_STS_OK;
ac3dd5bd
JA		 493}
494
f4800d6d 495static void nvme_free_iod(struct nvme_dev *dev, struct request *req)
b60503ba 496{
f4800d6d 497 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3
CK		 498 const int last_prp = dev->ctrl.page_size / sizeof(__le64) - 1;
499 dma_addr_t dma_addr = iod->first_dma, next_dma_addr;
500
eca18b23 501 int i;
eca18b23
MW		 502
503 if (iod->npages == 0)
a7a7cbe3
CK		 504 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0],
505 dma_addr);
506
eca18b23 507 for (i = 0; i < iod->npages; i++) {
a7a7cbe3
CK		 508 void *addr = nvme_pci_iod_list(req)[i];
509
510 if (iod->use_sgl) {
511 struct nvme_sgl_desc *sg_list = addr;
512
513 next_dma_addr =
514 le64_to_cpu((sg_list[SGES_PER_PAGE - 1]).addr);
515 } else {
516 __le64 *prp_list = addr;
517
518 next_dma_addr = le64_to_cpu(prp_list[last_prp]);
519 }
520
521 dma_pool_free(dev->prp_page_pool, addr, dma_addr);
522 dma_addr = next_dma_addr;
eca18b23 523 }
ac3dd5bd 524
f4800d6d
CH		 525 if (iod->sg != iod->inline_sg)
526 kfree(iod->sg);
b4ff9c8d
KB		 527}
528
52b68d7e 529#ifdef CONFIG_BLK_DEV_INTEGRITY
e1e5e564
KB		 530static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
531{
532 if (be32_to_cpu(pi->ref_tag) == v)
533 pi->ref_tag = cpu_to_be32(p);
534}
535
536static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
537{
538 if (be32_to_cpu(pi->ref_tag) == p)
539 pi->ref_tag = cpu_to_be32(v);
540}
541
542/**
543 * nvme_dif_remap - remaps ref tags to bip seed and physical lba
544 *
545 * The virtual start sector is the one that was originally submitted by the
546 * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical
547 * start sector may be different. Remap protection information to match the
548 * physical LBA on writes, and back to the original seed on reads.
549 *
550 * Type 0 and 3 do not have a ref tag, so no remapping required.
551 */
552static void nvme_dif_remap(struct request *req,
553 void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
554{
555 struct nvme_ns *ns = req->rq_disk->private_data;
556 struct bio_integrity_payload *bip;
557 struct t10_pi_tuple *pi;
558 void *p, *pmap;
559 u32 i, nlb, ts, phys, virt;
560
561 if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3)
562 return;
563
564 bip = bio_integrity(req->bio);
565 if (!bip)
566 return;
567
568 pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset;
e1e5e564
KB		 569
570 p = pmap;
571 virt = bip_get_seed(bip);
572 phys = nvme_block_nr(ns, blk_rq_pos(req));
573 nlb = (blk_rq_bytes(req) >> ns->lba_shift);
ac6fc48c 574 ts = ns->disk->queue->integrity.tuple_size;
e1e5e564
KB		 575
576 for (i = 0; i < nlb; i++, virt++, phys++) {
577 pi = (struct t10_pi_tuple *)p;
578 dif_swap(phys, virt, pi);
579 p += ts;
580 }
581 kunmap_atomic(pmap);
582}
52b68d7e
KB		 583#else /* CONFIG_BLK_DEV_INTEGRITY */
584static void nvme_dif_remap(struct request *req,
585 void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
586{
587}
588static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
589{
590}
591static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
592{
593}
52b68d7e
KB		 594#endif
595
d0877473
KB		 596static void nvme_print_sgl(struct scatterlist *sgl, int nents)
597{
598 int i;
599 struct scatterlist *sg;
600
601 for_each_sg(sgl, sg, nents, i) {
602 dma_addr_t phys = sg_phys(sg);
603 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
604 "dma_address:%pad dma_length:%d\n",
605 i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
606 sg_dma_len(sg));
607 }
608}
609
a7a7cbe3
CK		 610static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
611 struct request *req, struct nvme_rw_command *cmnd)
ff22b54f 612{
f4800d6d 613 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
99802a7a 614 struct dma_pool *pool;
b131c61d 615 int length = blk_rq_payload_bytes(req);
eca18b23 616 struct scatterlist *sg = iod->sg;
ff22b54f
MW		 617 int dma_len = sg_dma_len(sg);
618 u64 dma_addr = sg_dma_address(sg);
5fd4ce1b 619 u32 page_size = dev->ctrl.page_size;
f137e0f1 620 int offset = dma_addr & (page_size - 1);
e025344c 621 __le64 *prp_list;
a7a7cbe3 622 void **list = nvme_pci_iod_list(req);
e025344c 623 dma_addr_t prp_dma;
eca18b23 624 int nprps, i;
ff22b54f 625
1d090624 626 length -= (page_size - offset);
5228b328
JS		 627 if (length <= 0) {
628 iod->first_dma = 0;
a7a7cbe3 629 goto done;
5228b328 630 }
ff22b54f 631
1d090624 632 dma_len -= (page_size - offset);
ff22b54f 633 if (dma_len) {
1d090624 634 dma_addr += (page_size - offset);
ff22b54f
MW		 635 } else {
636 sg = sg_next(sg);
637 dma_addr = sg_dma_address(sg);
638 dma_len = sg_dma_len(sg);
639 }
640
1d090624 641 if (length <= page_size) {
edd10d33 642 iod->first_dma = dma_addr;
a7a7cbe3 643 goto done;
e025344c
SMM		 644 }
645
1d090624 646 nprps = DIV_ROUND_UP(length, page_size);
99802a7a
MW		 647 if (nprps <= (256 / 8)) {
648 pool = dev->prp_small_pool;
eca18b23 649 iod->npages = 0;
99802a7a
MW		 650 } else {
651 pool = dev->prp_page_pool;
eca18b23 652 iod->npages = 1;
99802a7a
MW		 653 }
654
69d2b571 655 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
b77954cb 656 if (!prp_list) {
edd10d33 657 iod->first_dma = dma_addr;
eca18b23 658 iod->npages = -1;
86eea289 659 return BLK_STS_RESOURCE;
b77954cb 660 }
eca18b23
MW		 661 list[0] = prp_list;
662 iod->first_dma = prp_dma;
e025344c
SMM		 663 i = 0;
664 for (;;) {
1d090624 665 if (i == page_size >> 3) {
e025344c 666 __le64 *old_prp_list = prp_list;
69d2b571 667 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
eca18b23 668 if (!prp_list)
86eea289 669 return BLK_STS_RESOURCE;
eca18b23 670 list[iod->npages++] = prp_list;
7523d834
MW		 671 prp_list[0] = old_prp_list[i - 1];
672 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
673 i = 1;
e025344c
SMM		 674 }
675 prp_list[i++] = cpu_to_le64(dma_addr);
1d090624
KB		 676 dma_len -= page_size;
677 dma_addr += page_size;
678 length -= page_size;
e025344c
SMM		 679 if (length <= 0)
680 break;
681 if (dma_len > 0)
682 continue;
86eea289
KB		 683 if (unlikely(dma_len < 0))
684 goto bad_sgl;
e025344c
SMM		 685 sg = sg_next(sg);
686 dma_addr = sg_dma_address(sg);
687 dma_len = sg_dma_len(sg);
ff22b54f
MW		 688 }
689
a7a7cbe3
CK		 690done:
691 cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
692 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
693
86eea289
KB		 694 return BLK_STS_OK;
695
696 bad_sgl:
d0877473
KB		 697 WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents),
698 "Invalid SGL for payload:%d nents:%d\n",
699 blk_rq_payload_bytes(req), iod->nents);
86eea289 700 return BLK_STS_IOERR;
ff22b54f
MW		 701}
702
a7a7cbe3
CK		 703static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
704 struct scatterlist *sg)
705{
706 sge->addr = cpu_to_le64(sg_dma_address(sg));
707 sge->length = cpu_to_le32(sg_dma_len(sg));
708 sge->type = NVME_SGL_FMT_DATA_DESC << 4;
709}
710
711static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
712 dma_addr_t dma_addr, int entries)
713{
714 sge->addr = cpu_to_le64(dma_addr);
715 if (entries < SGES_PER_PAGE) {
716 sge->length = cpu_to_le32(entries * sizeof(*sge));
717 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
718 } else {
719 sge->length = cpu_to_le32(PAGE_SIZE);
720 sge->type = NVME_SGL_FMT_SEG_DESC << 4;
721 }
722}
723
724static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
725 struct request *req, struct nvme_rw_command *cmd)
726{
727 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
728 int length = blk_rq_payload_bytes(req);
729 struct dma_pool *pool;
730 struct nvme_sgl_desc *sg_list;
731 struct scatterlist *sg = iod->sg;
732 int entries = iod->nents, i = 0;
733 dma_addr_t sgl_dma;
734
a7a7cbe3
CK		 735 /* setting the transfer type as SGL */
736 cmd->flags = NVME_CMD_SGL_METABUF;
737
738 if (length == sg_dma_len(sg)) {
739 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
740 return BLK_STS_OK;
741 }
742
743 if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
744 pool = dev->prp_small_pool;
745 iod->npages = 0;
746 } else {
747 pool = dev->prp_page_pool;
748 iod->npages = 1;
749 }
750
751 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
752 if (!sg_list) {
753 iod->npages = -1;
754 return BLK_STS_RESOURCE;
755 }
756
757 nvme_pci_iod_list(req)[0] = sg_list;
758 iod->first_dma = sgl_dma;
759
760 nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
761
762 do {
763 if (i == SGES_PER_PAGE) {
764 struct nvme_sgl_desc *old_sg_desc = sg_list;
765 struct nvme_sgl_desc *link = &old_sg_desc[i - 1];
766
767 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
768 if (!sg_list)
769 return BLK_STS_RESOURCE;
770
771 i = 0;
772 nvme_pci_iod_list(req)[iod->npages++] = sg_list;
773 sg_list[i++] = *link;
774 nvme_pci_sgl_set_seg(link, sgl_dma, entries);
775 }
776
777 nvme_pci_sgl_set_data(&sg_list[i++], sg);
778
779 length -= sg_dma_len(sg);
780 sg = sg_next(sg);
781 entries--;
782 } while (length > 0);
783
784 WARN_ON(entries > 0);
785 return BLK_STS_OK;
786}
787
fc17b653 788static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
b131c61d 789 struct nvme_command *cmnd)
d29ec824 790{
f4800d6d 791 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
ba1ca37e
CH		 792 struct request_queue *q = req->q;
793 enum dma_data_direction dma_dir = rq_data_dir(req) ?
794 DMA_TO_DEVICE : DMA_FROM_DEVICE;
fc17b653 795 blk_status_t ret = BLK_STS_IOERR;
d29ec824 796
f9d03f96 797 sg_init_table(iod->sg, blk_rq_nr_phys_segments(req));
ba1ca37e
CH		 798 iod->nents = blk_rq_map_sg(q, req, iod->sg);
799 if (!iod->nents)
800 goto out;
d29ec824 801
fc17b653 802 ret = BLK_STS_RESOURCE;
2b6b535d
MFO		 803 if (!dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, dma_dir,
804 DMA_ATTR_NO_WARN))
ba1ca37e 805 goto out;
d29ec824 806
955b1b5a 807 if (iod->use_sgl)
a7a7cbe3
CK		 808 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw);
809 else
810 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
811
86eea289 812 if (ret != BLK_STS_OK)
ba1ca37e 813 goto out_unmap;
0e5e4f0e 814
fc17b653 815 ret = BLK_STS_IOERR;
ba1ca37e
CH		 816 if (blk_integrity_rq(req)) {
817 if (blk_rq_count_integrity_sg(q, req->bio) != 1)
818 goto out_unmap;
0e5e4f0e 819
bf684057
CH		 820 sg_init_table(&iod->meta_sg, 1);
821 if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1)
ba1ca37e 822 goto out_unmap;
0e5e4f0e 823
b5d8af5b 824 if (req_op(req) == REQ_OP_WRITE)
ba1ca37e 825 nvme_dif_remap(req, nvme_dif_prep);
0e5e4f0e 826
bf684057 827 if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir))
ba1ca37e 828 goto out_unmap;
d29ec824 829 }
00df5cb4 830
ba1ca37e 831 if (blk_integrity_rq(req))
bf684057 832 cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg));
fc17b653 833 return BLK_STS_OK;
00df5cb4 834
ba1ca37e
CH		 835out_unmap:
836 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
837out:
838 return ret;
00df5cb4
MW		 839}
840
f4800d6d 841static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
b60503ba 842{
f4800d6d 843 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
d4f6c3ab
CH		 844 enum dma_data_direction dma_dir = rq_data_dir(req) ?
845 DMA_TO_DEVICE : DMA_FROM_DEVICE;
846
847 if (iod->nents) {
848 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
849 if (blk_integrity_rq(req)) {
b5d8af5b 850 if (req_op(req) == REQ_OP_READ)
d4f6c3ab 851 nvme_dif_remap(req, nvme_dif_complete);
bf684057 852 dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir);
e1e5e564 853 }
e19b127f 854 }
e1e5e564 855
f9d03f96 856 nvme_cleanup_cmd(req);
f4800d6d 857 nvme_free_iod(dev, req);
d4f6c3ab 858}
b60503ba 859
d29ec824
CH		 860/*
861 * NOTE: ns is NULL when called on the admin queue.
862 */
fc17b653 863static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
a4aea562 864 const struct blk_mq_queue_data *bd)
edd10d33 865{
a4aea562
MB		 866 struct nvme_ns *ns = hctx->queue->queuedata;
867 struct nvme_queue *nvmeq = hctx->driver_data;
d29ec824 868 struct nvme_dev *dev = nvmeq->dev;
a4aea562 869 struct request *req = bd->rq;
ba1ca37e 870 struct nvme_command cmnd;
ebe6d874 871 blk_status_t ret;
e1e5e564 872
f9d03f96 873 ret = nvme_setup_cmd(ns, req, &cmnd);
fc17b653 874 if (ret)
f4800d6d 875 return ret;
a4aea562 876
b131c61d 877 ret = nvme_init_iod(req, dev);
fc17b653 878 if (ret)
f9d03f96 879 goto out_free_cmd;
a4aea562 880
fc17b653 881 if (blk_rq_nr_phys_segments(req)) {
b131c61d 882 ret = nvme_map_data(dev, req, &cmnd);
fc17b653
CH		 883 if (ret)
884 goto out_cleanup_iod;
885 }
a4aea562 886
aae239e1 887 blk_mq_start_request(req);
a4aea562 888
ba1ca37e 889 spin_lock_irq(&nvmeq->q_lock);
ae1fba20 890 if (unlikely(nvmeq->cq_vector < 0)) {
fc17b653 891 ret = BLK_STS_IOERR;
ae1fba20 892 spin_unlock_irq(&nvmeq->q_lock);
f9d03f96 893 goto out_cleanup_iod;
ae1fba20 894 }
ba1ca37e 895 __nvme_submit_cmd(nvmeq, &cmnd);
a4aea562
MB		 896 nvme_process_cq(nvmeq);
897 spin_unlock_irq(&nvmeq->q_lock);
fc17b653 898 return BLK_STS_OK;
f9d03f96 899out_cleanup_iod:
f4800d6d 900 nvme_free_iod(dev, req);
f9d03f96
CH		 901out_free_cmd:
902 nvme_cleanup_cmd(req);
ba1ca37e 903 return ret;
b60503ba 904}
e1e5e564 905
77f02a7a 906static void nvme_pci_complete_rq(struct request *req)
eee417b0 907{
f4800d6d 908 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a4aea562 909
77f02a7a
CH		 910 nvme_unmap_data(iod->nvmeq->dev, req);
911 nvme_complete_rq(req);
b60503ba
MW		 912}
913
d783e0bd
MR		 914/* We read the CQE phase first to check if the rest of the entry is valid */
915static inline bool nvme_cqe_valid(struct nvme_queue *nvmeq, u16 head,
916 u16 phase)
917{
918 return (le16_to_cpu(nvmeq->cqes[head].status) & 1) == phase;
919}
920
eb281c82 921static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
b60503ba 922{
eb281c82 923 u16 head = nvmeq->cq_head;
adf68f21 924
eb281c82
SG		 925 if (likely(nvmeq->cq_vector >= 0)) {
926 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
927 nvmeq->dbbuf_cq_ei))
928 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
929 }
930}
aae239e1 931
83a12fb7
SG		 932static inline void nvme_handle_cqe(struct nvme_queue *nvmeq,
933 struct nvme_completion *cqe)
934{
935 struct request *req;
adf68f21 936
83a12fb7
SG		 937 if (unlikely(cqe->command_id >= nvmeq->q_depth)) {
938 dev_warn(nvmeq->dev->ctrl.device,
939 "invalid id %d completed on queue %d\n",
940 cqe->command_id, le16_to_cpu(cqe->sq_id));
941 return;
b60503ba
MW		 942 }
943
83a12fb7
SG		 944 /*
945 * AEN requests are special as they don't time out and can
946 * survive any kind of queue freeze and often don't respond to
947 * aborts. We don't even bother to allocate a struct request
948 * for them but rather special case them here.
949 */
950 if (unlikely(nvmeq->qid == 0 &&
38dabe21 951 cqe->command_id >= NVME_AQ_BLK_MQ_DEPTH)) {
83a12fb7
SG		 952 nvme_complete_async_event(&nvmeq->dev->ctrl,
953 cqe->status, &cqe->result);
a0fa9647 954 return;
83a12fb7 955 }
b60503ba 956
e9d8a0fd 957 nvmeq->cqe_seen = 1;
83a12fb7
SG		 958 req = blk_mq_tag_to_rq(*nvmeq->tags, cqe->command_id);
959 nvme_end_request(req, cqe->status, cqe->result);
960}
b60503ba 961
920d13a8
SG		 962static inline bool nvme_read_cqe(struct nvme_queue *nvmeq,
963 struct nvme_completion *cqe)
b60503ba 964{
920d13a8
SG		 965 if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase)) {
966 *cqe = nvmeq->cqes[nvmeq->cq_head];
adf68f21 967
920d13a8
SG		 968 if (++nvmeq->cq_head == nvmeq->q_depth) {
969 nvmeq->cq_head = 0;
970 nvmeq->cq_phase = !nvmeq->cq_phase;
b60503ba 971 }
920d13a8 972 return true;
b60503ba 973 }
920d13a8 974 return false;
a0fa9647
JA		 975}
976
977static void nvme_process_cq(struct nvme_queue *nvmeq)
978{
920d13a8
SG		 979 struct nvme_completion cqe;
980 int consumed = 0;
b60503ba 981
920d13a8
SG		 982 while (nvme_read_cqe(nvmeq, &cqe)) {
983 nvme_handle_cqe(nvmeq, &cqe);
984 consumed++;
920d13a8 985 }
eb281c82 986
e9d8a0fd 987 if (consumed)
920d13a8 988 nvme_ring_cq_doorbell(nvmeq);
b60503ba
MW		 989}
990
991static irqreturn_t nvme_irq(int irq, void *data)
58ffacb5
MW		 992{
993 irqreturn_t result;
994 struct nvme_queue *nvmeq = data;
995 spin_lock(&nvmeq->q_lock);
e9539f47
MW		 996 nvme_process_cq(nvmeq);
997 result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE;
998 nvmeq->cqe_seen = 0;
58ffacb5
MW		 999 spin_unlock(&nvmeq->q_lock);
1000 return result;
1001}
1002
1003static irqreturn_t nvme_irq_check(int irq, void *data)
1004{
1005 struct nvme_queue *nvmeq = data;
d783e0bd
MR		 1006 if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase))
1007 return IRQ_WAKE_THREAD;
1008 return IRQ_NONE;
58ffacb5
MW		 1009}
1010
7776db1c 1011static int __nvme_poll(struct nvme_queue *nvmeq, unsigned int tag)
a0fa9647 1012{
442e19b7
SG		 1013 struct nvme_completion cqe;
1014 int found = 0, consumed = 0;
a0fa9647 1015
442e19b7
SG		 1016 if (!nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase))
1017 return 0;
a0fa9647 1018
442e19b7
SG		 1019 spin_lock_irq(&nvmeq->q_lock);
1020 while (nvme_read_cqe(nvmeq, &cqe)) {
1021 nvme_handle_cqe(nvmeq, &cqe);
1022 consumed++;
1023
1024 if (tag == cqe.command_id) {
1025 found = 1;
1026 break;
1027 }
1028 }
1029
1030 if (consumed)
1031 nvme_ring_cq_doorbell(nvmeq);
1032 spin_unlock_irq(&nvmeq->q_lock);
1033
1034 return found;
a0fa9647
JA		 1035}
1036
7776db1c
KB		 1037static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag)
1038{
1039 struct nvme_queue *nvmeq = hctx->driver_data;
1040
1041 return __nvme_poll(nvmeq, tag);
1042}
1043
ad22c355 1044static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
b60503ba 1045{
f866fc42 1046 struct nvme_dev *dev = to_nvme_dev(ctrl);
9396dec9 1047 struct nvme_queue *nvmeq = dev->queues[0];
a4aea562 1048 struct nvme_command c;
b60503ba 1049
a4aea562
MB		 1050 memset(&c, 0, sizeof(c));
1051 c.common.opcode = nvme_admin_async_event;
ad22c355 1052 c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
3c0cf138 1053
9396dec9 1054 spin_lock_irq(&nvmeq->q_lock);
f866fc42 1055 __nvme_submit_cmd(nvmeq, &c);
9396dec9 1056 spin_unlock_irq(&nvmeq->q_lock);
f705f837
CH		 1057}
1058
b60503ba 1059static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
f705f837 1060{
b60503ba
MW		 1061 struct nvme_command c;
1062
1063 memset(&c, 0, sizeof(c));
1064 c.delete_queue.opcode = opcode;
1065 c.delete_queue.qid = cpu_to_le16(id);
1066
1c63dc66 1067 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1068}
1069
b60503ba
MW		 1070static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
1071 struct nvme_queue *nvmeq)
1072{
b60503ba
MW		 1073 struct nvme_command c;
1074 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
1075
d29ec824 1076 /*
16772ae6 1077 * Note: we (ab)use the fact that the prp fields survive if no data
d29ec824
CH		 1078 * is attached to the request.
1079 */
b60503ba
MW		 1080 memset(&c, 0, sizeof(c));
1081 c.create_cq.opcode = nvme_admin_create_cq;
1082 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1083 c.create_cq.cqid = cpu_to_le16(qid);
1084 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1085 c.create_cq.cq_flags = cpu_to_le16(flags);
1086 c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
1087
1c63dc66 1088 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1089}
1090
1091static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1092 struct nvme_queue *nvmeq)
1093{
b60503ba 1094 struct nvme_command c;
81c1cd98 1095 int flags = NVME_QUEUE_PHYS_CONTIG;
b60503ba 1096
d29ec824 1097 /*
16772ae6 1098 * Note: we (ab)use the fact that the prp fields survive if no data
d29ec824
CH		 1099 * is attached to the request.
1100 */
b60503ba
MW		 1101 memset(&c, 0, sizeof(c));
1102 c.create_sq.opcode = nvme_admin_create_sq;
1103 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1104 c.create_sq.sqid = cpu_to_le16(qid);
1105 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1106 c.create_sq.sq_flags = cpu_to_le16(flags);
1107 c.create_sq.cqid = cpu_to_le16(qid);
1108
1c63dc66 1109 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1110}
1111
1112static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1113{
1114 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1115}
1116
1117static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1118{
1119 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1120}
1121
2a842aca 1122static void abort_endio(struct request *req, blk_status_t error)
bc5fc7e4 1123{
f4800d6d
CH		 1124 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1125 struct nvme_queue *nvmeq = iod->nvmeq;
e44ac588 1126
27fa9bc5
CH		 1127 dev_warn(nvmeq->dev->ctrl.device,
1128 "Abort status: 0x%x", nvme_req(req)->status);
e7a2a87d 1129 atomic_inc(&nvmeq->dev->ctrl.abort_limit);
e7a2a87d 1130 blk_mq_free_request(req);
bc5fc7e4
MW		 1131}
1132
b2a0eb1a
KB		 1133static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1134{
1135
1136 /* If true, indicates loss of adapter communication, possibly by a
1137 * NVMe Subsystem reset.
1138 */
1139 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1140
1141 /* If there is a reset ongoing, we shouldn't reset again. */
1142 if (dev->ctrl.state == NVME_CTRL_RESETTING)
1143 return false;
1144
1145 /* We shouldn't reset unless the controller is on fatal error state
1146 * _or_ if we lost the communication with it.
1147 */
1148 if (!(csts & NVME_CSTS_CFS) && !nssro)
1149 return false;
1150
1151 /* If PCI error recovery process is happening, we cannot reset or
1152 * the recovery mechanism will surely fail.
1153 */
1154 if (pci_channel_offline(to_pci_dev(dev->dev)))
1155 return false;
1156
1157 return true;
1158}
1159
1160static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1161{
1162 /* Read a config register to help see what died. */
1163 u16 pci_status;
1164 int result;
1165
1166 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1167 &pci_status);
1168 if (result == PCIBIOS_SUCCESSFUL)
1169 dev_warn(dev->ctrl.device,
1170 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1171 csts, pci_status);
1172 else
1173 dev_warn(dev->ctrl.device,
1174 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1175 csts, result);
1176}
1177
31c7c7d2 1178static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
c30341dc 1179{
f4800d6d
CH		 1180 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1181 struct nvme_queue *nvmeq = iod->nvmeq;
c30341dc 1182 struct nvme_dev *dev = nvmeq->dev;
a4aea562 1183 struct request *abort_req;
a4aea562 1184 struct nvme_command cmd;
b2a0eb1a
KB		 1185 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1186
1187 /*
1188 * Reset immediately if the controller is failed
1189 */
1190 if (nvme_should_reset(dev, csts)) {
1191 nvme_warn_reset(dev, csts);
1192 nvme_dev_disable(dev, false);
d86c4d8e 1193 nvme_reset_ctrl(&dev->ctrl);
b2a0eb1a
KB		 1194 return BLK_EH_HANDLED;
1195 }
c30341dc 1196
7776db1c
KB		 1197 /*
1198 * Did we miss an interrupt?
1199 */
1200 if (__nvme_poll(nvmeq, req->tag)) {
1201 dev_warn(dev->ctrl.device,
1202 "I/O %d QID %d timeout, completion polled\n",
1203 req->tag, nvmeq->qid);
1204 return BLK_EH_HANDLED;
1205 }
1206
31c7c7d2 1207 /*
fd634f41
CH		 1208 * Shutdown immediately if controller times out while starting. The
1209 * reset work will see the pci device disabled when it gets the forced
1210 * cancellation error. All outstanding requests are completed on
1211 * shutdown, so we return BLK_EH_HANDLED.
1212 */
bb8d261e 1213 if (dev->ctrl.state == NVME_CTRL_RESETTING) {
1b3c47c1 1214 dev_warn(dev->ctrl.device,
fd634f41
CH		 1215 "I/O %d QID %d timeout, disable controller\n",
1216 req->tag, nvmeq->qid);
a5cdb68c 1217 nvme_dev_disable(dev, false);
27fa9bc5 1218 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
fd634f41 1219 return BLK_EH_HANDLED;
c30341dc
KB		 1220 }
1221
fd634f41
CH		 1222 /*
1223 * Shutdown the controller immediately and schedule a reset if the
1224 * command was already aborted once before and still hasn't been
1225 * returned to the driver, or if this is the admin queue.
31c7c7d2 1226 */
f4800d6d 1227 if (!nvmeq->qid || iod->aborted) {
1b3c47c1 1228 dev_warn(dev->ctrl.device,
e1569a16
KB		 1229 "I/O %d QID %d timeout, reset controller\n",
1230 req->tag, nvmeq->qid);
a5cdb68c 1231 nvme_dev_disable(dev, false);
d86c4d8e 1232 nvme_reset_ctrl(&dev->ctrl);
c30341dc 1233
e1569a16
KB		 1234 /*
1235 * Mark the request as handled, since the inline shutdown
1236 * forces all outstanding requests to complete.
1237 */
27fa9bc5 1238 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
e1569a16 1239 return BLK_EH_HANDLED;
c30341dc 1240 }
c30341dc 1241
e7a2a87d 1242 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
6bf25d16 1243 atomic_inc(&dev->ctrl.abort_limit);
31c7c7d2 1244 return BLK_EH_RESET_TIMER;
6bf25d16 1245 }
7bf7d778 1246 iod->aborted = 1;
a4aea562 1247
c30341dc
KB		 1248 memset(&cmd, 0, sizeof(cmd));
1249 cmd.abort.opcode = nvme_admin_abort_cmd;
a4aea562 1250 cmd.abort.cid = req->tag;
c30341dc 1251 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
c30341dc 1252
1b3c47c1
SG		 1253 dev_warn(nvmeq->dev->ctrl.device,
1254 "I/O %d QID %d timeout, aborting\n",
1255 req->tag, nvmeq->qid);
e7a2a87d
CH		 1256
1257 abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
eb71f435 1258 BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
e7a2a87d
CH		 1259 if (IS_ERR(abort_req)) {
1260 atomic_inc(&dev->ctrl.abort_limit);
1261 return BLK_EH_RESET_TIMER;
1262 }
1263
1264 abort_req->timeout = ADMIN_TIMEOUT;
1265 abort_req->end_io_data = NULL;
1266 blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio);
c30341dc 1267
31c7c7d2
CH		 1268 /*
1269 * The aborted req will be completed on receiving the abort req.
1270 * We enable the timer again. If hit twice, it'll cause a device reset,
1271 * as the device then is in a faulty state.
1272 */
1273 return BLK_EH_RESET_TIMER;
c30341dc
KB		 1274}
1275
a4aea562
MB		 1276static void nvme_free_queue(struct nvme_queue *nvmeq)
1277{
9e866774
MW		 1278 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1279 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
8ffaadf7
JD		 1280 if (nvmeq->sq_cmds)
1281 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
9e866774
MW		 1282 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1283 kfree(nvmeq);
1284}
1285
a1a5ef99 1286static void nvme_free_queues(struct nvme_dev *dev, int lowest)
22404274
KB		 1287{
1288 int i;
1289
d858e5f0 1290 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
a4aea562 1291 struct nvme_queue *nvmeq = dev->queues[i];
d858e5f0 1292 dev->ctrl.queue_count--;
a4aea562 1293 dev->queues[i] = NULL;
f435c282 1294 nvme_free_queue(nvmeq);
121c7ad4 1295 }
22404274
KB		 1296}
1297
4d115420
KB		 1298/**
1299 * nvme_suspend_queue - put queue into suspended state
1300 * @nvmeq - queue to suspend
4d115420
KB		 1301 */
1302static int nvme_suspend_queue(struct nvme_queue *nvmeq)
b60503ba 1303{
2b25d981 1304 int vector;
b60503ba 1305
a09115b2 1306 spin_lock_irq(&nvmeq->q_lock);
2b25d981
KB		 1307 if (nvmeq->cq_vector == -1) {
1308 spin_unlock_irq(&nvmeq->q_lock);
1309 return 1;
1310 }
0ff199cb 1311 vector = nvmeq->cq_vector;
42f61420 1312 nvmeq->dev->online_queues--;
2b25d981 1313 nvmeq->cq_vector = -1;
a09115b2
MW		 1314 spin_unlock_irq(&nvmeq->q_lock);
1315
1c63dc66 1316 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
c81545f9 1317 blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q);
6df3dbc8 1318
0ff199cb 1319 pci_free_irq(to_pci_dev(nvmeq->dev->dev), vector, nvmeq);
b60503ba 1320
4d115420
KB		 1321 return 0;
1322}
b60503ba 1323
a5cdb68c 1324static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
4d115420 1325{
a5cdb68c 1326 struct nvme_queue *nvmeq = dev->queues[0];
4d115420
KB		 1327
1328 if (!nvmeq)
1329 return;
1330 if (nvme_suspend_queue(nvmeq))
1331 return;
1332
a5cdb68c
KB		 1333 if (shutdown)
1334 nvme_shutdown_ctrl(&dev->ctrl);
1335 else
20d0dfe6 1336 nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap);
07836e65
KB		 1337
1338 spin_lock_irq(&nvmeq->q_lock);
1339 nvme_process_cq(nvmeq);
1340 spin_unlock_irq(&nvmeq->q_lock);
b60503ba
MW		 1341}
1342
8ffaadf7
JD		 1343static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1344 int entry_size)
1345{
1346 int q_depth = dev->q_depth;
5fd4ce1b
CH		 1347 unsigned q_size_aligned = roundup(q_depth * entry_size,
1348 dev->ctrl.page_size);
8ffaadf7
JD		 1349
1350 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
c45f5c99 1351 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
5fd4ce1b 1352 mem_per_q = round_down(mem_per_q, dev->ctrl.page_size);
c45f5c99 1353 q_depth = div_u64(mem_per_q, entry_size);
8ffaadf7
JD		 1354
1355 /*
1356 * Ensure the reduced q_depth is above some threshold where it
1357 * would be better to map queues in system memory with the
1358 * original depth
1359 */
1360 if (q_depth < 64)
1361 return -ENOMEM;
1362 }
1363
1364 return q_depth;
1365}
1366
1367static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1368 int qid, int depth)
1369{
1370 if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz)) {
5fd4ce1b
CH		 1371 unsigned offset = (qid - 1) * roundup(SQ_SIZE(depth),
1372 dev->ctrl.page_size);
8969f1f8 1373 nvmeq->sq_dma_addr = dev->cmb_bus_addr + offset;
8ffaadf7
JD		 1374 nvmeq->sq_cmds_io = dev->cmb + offset;
1375 } else {
1376 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
1377 &nvmeq->sq_dma_addr, GFP_KERNEL);
1378 if (!nvmeq->sq_cmds)
1379 return -ENOMEM;
1380 }
1381
1382 return 0;
1383}
1384
b60503ba 1385static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
d3af3ecd 1386 int depth, int node)
b60503ba 1387{
d3af3ecd
SL		 1388 struct nvme_queue *nvmeq = kzalloc_node(sizeof(*nvmeq), GFP_KERNEL,
1389 node);
b60503ba
MW		 1390 if (!nvmeq)
1391 return NULL;
1392
e75ec752 1393 nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth),
4d51abf9 1394 &nvmeq->cq_dma_addr, GFP_KERNEL);
b60503ba
MW		 1395 if (!nvmeq->cqes)
1396 goto free_nvmeq;
b60503ba 1397
8ffaadf7 1398 if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth))
b60503ba
MW		 1399 goto free_cqdma;
1400
e75ec752 1401 nvmeq->q_dmadev = dev->dev;
091b6092 1402 nvmeq->dev = dev;
b60503ba
MW		 1403 spin_lock_init(&nvmeq->q_lock);
1404 nvmeq->cq_head = 0;
82123460 1405 nvmeq->cq_phase = 1;
b80d5ccc 1406 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
b60503ba 1407 nvmeq->q_depth = depth;
c30341dc 1408 nvmeq->qid = qid;
758dd7fd 1409 nvmeq->cq_vector = -1;
a4aea562 1410 dev->queues[qid] = nvmeq;
d858e5f0 1411 dev->ctrl.queue_count++;
36a7e993 1412
b60503ba
MW		 1413 return nvmeq;
1414
1415 free_cqdma:
e75ec752 1416 dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes,
b60503ba
MW		 1417 nvmeq->cq_dma_addr);
1418 free_nvmeq:
1419 kfree(nvmeq);
1420 return NULL;
1421}
1422
dca51e78 1423static int queue_request_irq(struct nvme_queue *nvmeq)
3001082c 1424{
0ff199cb
CH		 1425 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1426 int nr = nvmeq->dev->ctrl.instance;
1427
1428 if (use_threaded_interrupts) {
1429 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1430 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1431 } else {
1432 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1433 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1434 }
3001082c
MW		 1435}
1436
22404274 1437static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
b60503ba 1438{
22404274 1439 struct nvme_dev *dev = nvmeq->dev;
b60503ba 1440
7be50e93 1441 spin_lock_irq(&nvmeq->q_lock);
22404274
KB		 1442 nvmeq->sq_tail = 0;
1443 nvmeq->cq_head = 0;
1444 nvmeq->cq_phase = 1;
b80d5ccc 1445 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
22404274 1446 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
f9f38e33 1447 nvme_dbbuf_init(dev, nvmeq, qid);
42f61420 1448 dev->online_queues++;
7be50e93 1449 spin_unlock_irq(&nvmeq->q_lock);
22404274
KB		 1450}
1451
1452static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1453{
1454 struct nvme_dev *dev = nvmeq->dev;
1455 int result;
3f85d50b 1456
2b25d981 1457 nvmeq->cq_vector = qid - 1;
b60503ba
MW		 1458 result = adapter_alloc_cq(dev, qid, nvmeq);
1459 if (result < 0)
22404274 1460 return result;
b60503ba
MW		 1461
1462 result = adapter_alloc_sq(dev, qid, nvmeq);
1463 if (result < 0)
1464 goto release_cq;
1465
161b8be2 1466 nvme_init_queue(nvmeq, qid);
dca51e78 1467 result = queue_request_irq(nvmeq);
b60503ba
MW		 1468 if (result < 0)
1469 goto release_sq;
1470
22404274 1471 return result;
b60503ba
MW		 1472
1473 release_sq:
1474 adapter_delete_sq(dev, qid);
1475 release_cq:
1476 adapter_delete_cq(dev, qid);
22404274 1477 return result;
b60503ba
MW		 1478}
1479
f363b089 1480static const struct blk_mq_ops nvme_mq_admin_ops = {
d29ec824 1481 .queue_rq = nvme_queue_rq,
77f02a7a 1482 .complete = nvme_pci_complete_rq,
a4aea562 1483 .init_hctx = nvme_admin_init_hctx,
4af0e21c 1484 .exit_hctx = nvme_admin_exit_hctx,
0350815a 1485 .init_request = nvme_init_request,
a4aea562
MB		 1486 .timeout = nvme_timeout,
1487};
1488
f363b089 1489static const struct blk_mq_ops nvme_mq_ops = {
a4aea562 1490 .queue_rq = nvme_queue_rq,
77f02a7a 1491 .complete = nvme_pci_complete_rq,
a4aea562
MB		 1492 .init_hctx = nvme_init_hctx,
1493 .init_request = nvme_init_request,
dca51e78 1494 .map_queues = nvme_pci_map_queues,
a4aea562 1495 .timeout = nvme_timeout,
a0fa9647 1496 .poll = nvme_poll,
a4aea562
MB		 1497};
1498
ea191d2f
KB		 1499static void nvme_dev_remove_admin(struct nvme_dev *dev)
1500{
1c63dc66 1501 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
69d9a99c
KB		 1502 /*
1503 * If the controller was reset during removal, it's possible
1504 * user requests may be waiting on a stopped queue. Start the
1505 * queue to flush these to completion.
1506 */
c81545f9 1507 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1c63dc66 1508 blk_cleanup_queue(dev->ctrl.admin_q);
ea191d2f
KB		 1509 blk_mq_free_tag_set(&dev->admin_tagset);
1510 }
1511}
1512
a4aea562
MB		 1513static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1514{
1c63dc66 1515 if (!dev->ctrl.admin_q) {
a4aea562
MB		 1516 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1517 dev->admin_tagset.nr_hw_queues = 1;
e3e9d50c 1518
38dabe21 1519 dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH;
a4aea562 1520 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
e75ec752 1521 dev->admin_tagset.numa_node = dev_to_node(dev->dev);
a7a7cbe3 1522 dev->admin_tagset.cmd_size = nvme_pci_cmd_size(dev, false);
d3484991 1523 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED;
a4aea562
MB		 1524 dev->admin_tagset.driver_data = dev;
1525
1526 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1527 return -ENOMEM;
34b6c231 1528 dev->ctrl.admin_tagset = &dev->admin_tagset;
a4aea562 1529
1c63dc66
CH		 1530 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1531 if (IS_ERR(dev->ctrl.admin_q)) {
a4aea562
MB		 1532 blk_mq_free_tag_set(&dev->admin_tagset);
1533 return -ENOMEM;
1534 }
1c63dc66 1535 if (!blk_get_queue(dev->ctrl.admin_q)) {
ea191d2f 1536 nvme_dev_remove_admin(dev);
1c63dc66 1537 dev->ctrl.admin_q = NULL;
ea191d2f
KB		 1538 return -ENODEV;
1539 }
0fb59cbc 1540 } else
c81545f9 1541 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
a4aea562
MB		 1542
1543 return 0;
1544}
1545
97f6ef64
XY		 1546static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1547{
1548 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1549}
1550
1551static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1552{
1553 struct pci_dev *pdev = to_pci_dev(dev->dev);
1554
1555 if (size <= dev->bar_mapped_size)
1556 return 0;
1557 if (size > pci_resource_len(pdev, 0))
1558 return -ENOMEM;
1559 if (dev->bar)
1560 iounmap(dev->bar);
1561 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1562 if (!dev->bar) {
1563 dev->bar_mapped_size = 0;
1564 return -ENOMEM;
1565 }
1566 dev->bar_mapped_size = size;
1567 dev->dbs = dev->bar + NVME_REG_DBS;
1568
1569 return 0;
1570}
1571
01ad0990 1572static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
b60503ba 1573{
ba47e386 1574 int result;
b60503ba
MW		 1575 u32 aqa;
1576 struct nvme_queue *nvmeq;
1577
97f6ef64
XY		 1578 result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1579 if (result < 0)
1580 return result;
1581
8ef2074d 1582 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
20d0dfe6 1583 NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
dfbac8c7 1584
7a67cbea
CH		 1585 if (dev->subsystem &&
1586 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1587 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
dfbac8c7 1588
20d0dfe6 1589 result = nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap);
ba47e386
MW		 1590 if (result < 0)
1591 return result;
b60503ba 1592
a4aea562 1593 nvmeq = dev->queues[0];
cd638946 1594 if (!nvmeq) {
d3af3ecd
SL		 1595 nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH,
1596 dev_to_node(dev->dev));
cd638946
KB		 1597 if (!nvmeq)
1598 return -ENOMEM;
cd638946 1599 }
b60503ba
MW		 1600
1601 aqa = nvmeq->q_depth - 1;
1602 aqa |= aqa << 16;
1603
7a67cbea
CH		 1604 writel(aqa, dev->bar + NVME_REG_AQA);
1605 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1606 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
b60503ba 1607
20d0dfe6 1608 result = nvme_enable_ctrl(&dev->ctrl, dev->ctrl.cap);
025c557a 1609 if (result)
d4875622 1610 return result;
a4aea562 1611
2b25d981 1612 nvmeq->cq_vector = 0;
161b8be2 1613 nvme_init_queue(nvmeq, 0);
dca51e78 1614 result = queue_request_irq(nvmeq);
758dd7fd
JD		 1615 if (result) {
1616 nvmeq->cq_vector = -1;
d4875622 1617 return result;
758dd7fd 1618 }
025c557a 1619
b60503ba
MW		 1620 return result;
1621}
1622
749941f2 1623static int nvme_create_io_queues(struct nvme_dev *dev)
42f61420 1624{
949928c1 1625 unsigned i, max;
749941f2 1626 int ret = 0;
42f61420 1627
d858e5f0 1628 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
d3af3ecd
SL		 1629 /* vector == qid - 1, match nvme_create_queue */
1630 if (!nvme_alloc_queue(dev, i, dev->q_depth,
1631 pci_irq_get_node(to_pci_dev(dev->dev), i - 1))) {
749941f2 1632 ret = -ENOMEM;
42f61420 1633 break;
749941f2
CH		 1634 }
1635 }
42f61420 1636
d858e5f0 1637 max = min(dev->max_qid, dev->ctrl.queue_count - 1);
949928c1 1638 for (i = dev->online_queues; i <= max; i++) {
749941f2 1639 ret = nvme_create_queue(dev->queues[i], i);
d4875622 1640 if (ret)
42f61420 1641 break;
27e8166c 1642 }
749941f2
CH		 1643
1644 /*
1645 * Ignore failing Create SQ/CQ commands, we can continue with less
1646 * than the desired aount of queues, and even a controller without
1647 * I/O queues an still be used to issue admin commands. This might
1648 * be useful to upgrade a buggy firmware for example.
1649 */
1650 return ret >= 0 ? 0 : ret;
b60503ba
MW		 1651}
1652
202021c1
SB		 1653static ssize_t nvme_cmb_show(struct device *dev,
1654 struct device_attribute *attr,
1655 char *buf)
1656{
1657 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
1658
c965809c 1659 return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n",
202021c1
SB		 1660 ndev->cmbloc, ndev->cmbsz);
1661}
1662static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL);
1663
8ffaadf7
JD		 1664static void __iomem *nvme_map_cmb(struct nvme_dev *dev)
1665{
1666 u64 szu, size, offset;
8ffaadf7
JD		 1667 resource_size_t bar_size;
1668 struct pci_dev *pdev = to_pci_dev(dev->dev);
1669 void __iomem *cmb;
8969f1f8 1670 int bar;
8ffaadf7 1671
7a67cbea 1672 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
8ffaadf7
JD		 1673 if (!(NVME_CMB_SZ(dev->cmbsz)))
1674 return NULL;
202021c1 1675 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
8ffaadf7 1676
202021c1
SB		 1677 if (!use_cmb_sqes)
1678 return NULL;
8ffaadf7
JD		 1679
1680 szu = (u64)1 << (12 + 4 * NVME_CMB_SZU(dev->cmbsz));
1681 size = szu * NVME_CMB_SZ(dev->cmbsz);
202021c1 1682 offset = szu * NVME_CMB_OFST(dev->cmbloc);
8969f1f8
CH		 1683 bar = NVME_CMB_BIR(dev->cmbloc);
1684 bar_size = pci_resource_len(pdev, bar);
8ffaadf7
JD		 1685
1686 if (offset > bar_size)
1687 return NULL;
1688
1689 /*
1690 * Controllers may support a CMB size larger than their BAR,
1691 * for example, due to being behind a bridge. Reduce the CMB to
1692 * the reported size of the BAR
1693 */
1694 if (size > bar_size - offset)
1695 size = bar_size - offset;
1696
8969f1f8 1697 cmb = ioremap_wc(pci_resource_start(pdev, bar) + offset, size);
8ffaadf7
JD		 1698 if (!cmb)
1699 return NULL;
1700
8969f1f8 1701 dev->cmb_bus_addr = pci_bus_address(pdev, bar) + offset;
8ffaadf7
JD		 1702 dev->cmb_size = size;
1703 return cmb;
1704}
1705
1706static inline void nvme_release_cmb(struct nvme_dev *dev)
1707{
1708 if (dev->cmb) {
1709 iounmap(dev->cmb);
1710 dev->cmb = NULL;
1c78f773
MG		 1711 sysfs_remove_file_from_group(&dev->ctrl.device->kobj,
1712 &dev_attr_cmb.attr, NULL);
1713 dev->cmbsz = 0;
8ffaadf7
JD		 1714 }
1715}
1716
87ad72a5
CH		 1717static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1718{
4033f35d 1719 u64 dma_addr = dev->host_mem_descs_dma;
87ad72a5 1720 struct nvme_command c;
87ad72a5
CH		 1721 int ret;
1722
87ad72a5
CH		 1723 memset(&c, 0, sizeof(c));
1724 c.features.opcode = nvme_admin_set_features;
1725 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1726 c.features.dword11 = cpu_to_le32(bits);
1727 c.features.dword12 = cpu_to_le32(dev->host_mem_size >>
1728 ilog2(dev->ctrl.page_size));
1729 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr));
1730 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr));
1731 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs);
1732
1733 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1734 if (ret) {
1735 dev_warn(dev->ctrl.device,
1736 "failed to set host mem (err %d, flags %#x).\n",
1737 ret, bits);
1738 }
87ad72a5
CH		 1739 return ret;
1740}
1741
1742static void nvme_free_host_mem(struct nvme_dev *dev)
1743{
1744 int i;
1745
1746 for (i = 0; i < dev->nr_host_mem_descs; i++) {
1747 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
1748 size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size;
1749
1750 dma_free_coherent(dev->dev, size, dev->host_mem_desc_bufs[i],
1751 le64_to_cpu(desc->addr));
1752 }
1753
1754 kfree(dev->host_mem_desc_bufs);
1755 dev->host_mem_desc_bufs = NULL;
4033f35d
CH		 1756 dma_free_coherent(dev->dev,
1757 dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
1758 dev->host_mem_descs, dev->host_mem_descs_dma);
87ad72a5 1759 dev->host_mem_descs = NULL;
7e5dd57e 1760 dev->nr_host_mem_descs = 0;
87ad72a5
CH		 1761}
1762
92dc6895
CH		 1763static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
1764 u32 chunk_size)
9d713c2b 1765{
87ad72a5 1766 struct nvme_host_mem_buf_desc *descs;
92dc6895 1767 u32 max_entries, len;
4033f35d 1768 dma_addr_t descs_dma;
2ee0e4ed 1769 int i = 0;
87ad72a5 1770 void **bufs;
2ee0e4ed 1771 u64 size = 0, tmp;
87ad72a5 1772
87ad72a5
CH		 1773 tmp = (preferred + chunk_size - 1);
1774 do_div(tmp, chunk_size);
1775 max_entries = tmp;
044a9df1
CH		 1776
1777 if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
1778 max_entries = dev->ctrl.hmmaxd;
1779
4033f35d
CH		 1780 descs = dma_zalloc_coherent(dev->dev, max_entries * sizeof(*descs),
1781 &descs_dma, GFP_KERNEL);
87ad72a5
CH		 1782 if (!descs)
1783 goto out;
1784
1785 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
1786 if (!bufs)
1787 goto out_free_descs;
1788
244a8fe4 1789 for (size = 0; size < preferred && i < max_entries; size += len) {
87ad72a5
CH		 1790 dma_addr_t dma_addr;
1791
50cdb7c6 1792 len = min_t(u64, chunk_size, preferred - size);
87ad72a5
CH		 1793 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
1794 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1795 if (!bufs[i])
1796 break;
1797
1798 descs[i].addr = cpu_to_le64(dma_addr);
1799 descs[i].size = cpu_to_le32(len / dev->ctrl.page_size);
1800 i++;
1801 }
1802
92dc6895 1803 if (!size)
87ad72a5 1804 goto out_free_bufs;
87ad72a5 1805
87ad72a5
CH		 1806 dev->nr_host_mem_descs = i;
1807 dev->host_mem_size = size;
1808 dev->host_mem_descs = descs;
4033f35d 1809 dev->host_mem_descs_dma = descs_dma;
87ad72a5
CH		 1810 dev->host_mem_desc_bufs = bufs;
1811 return 0;
1812
1813out_free_bufs:
1814 while (--i >= 0) {
1815 size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size;
1816
1817 dma_free_coherent(dev->dev, size, bufs[i],
1818 le64_to_cpu(descs[i].addr));
1819 }
1820
1821 kfree(bufs);
1822out_free_descs:
4033f35d
CH		 1823 dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
1824 descs_dma);
87ad72a5 1825out:
87ad72a5
CH		 1826 dev->host_mem_descs = NULL;
1827 return -ENOMEM;
1828}
1829
92dc6895
CH		 1830static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
1831{
1832 u32 chunk_size;
1833
1834 /* start big and work our way down */
30f92d62 1835 for (chunk_size = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
044a9df1 1836 chunk_size >= max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
92dc6895
CH		 1837 chunk_size /= 2) {
1838 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
1839 if (!min || dev->host_mem_size >= min)
1840 return 0;
1841 nvme_free_host_mem(dev);
1842 }
1843 }
1844
1845 return -ENOMEM;
1846}
1847
9620cfba 1848static int nvme_setup_host_mem(struct nvme_dev *dev)
87ad72a5
CH		 1849{
1850 u64 max = (u64)max_host_mem_size_mb * SZ_1M;
1851 u64 preferred = (u64)dev->ctrl.hmpre * 4096;
1852 u64 min = (u64)dev->ctrl.hmmin * 4096;
1853 u32 enable_bits = NVME_HOST_MEM_ENABLE;
9620cfba 1854 int ret = 0;
87ad72a5
CH		 1855
1856 preferred = min(preferred, max);
1857 if (min > max) {
1858 dev_warn(dev->ctrl.device,
1859 "min host memory (%lld MiB) above limit (%d MiB).\n",
1860 min >> ilog2(SZ_1M), max_host_mem_size_mb);
1861 nvme_free_host_mem(dev);
9620cfba 1862 return 0;
87ad72a5
CH		 1863 }
1864
1865 /*
1866 * If we already have a buffer allocated check if we can reuse it.
1867 */
1868 if (dev->host_mem_descs) {
1869 if (dev->host_mem_size >= min)
1870 enable_bits |= NVME_HOST_MEM_RETURN;
1871 else
1872 nvme_free_host_mem(dev);
1873 }
1874
1875 if (!dev->host_mem_descs) {
92dc6895
CH		 1876 if (nvme_alloc_host_mem(dev, min, preferred)) {
1877 dev_warn(dev->ctrl.device,
1878 "failed to allocate host memory buffer.\n");
9620cfba 1879 return 0; /* controller must work without HMB */
92dc6895
CH		 1880 }
1881
1882 dev_info(dev->ctrl.device,
1883 "allocated %lld MiB host memory buffer.\n",
1884 dev->host_mem_size >> ilog2(SZ_1M));
87ad72a5
CH		 1885 }
1886
9620cfba
CH		 1887 ret = nvme_set_host_mem(dev, enable_bits);
1888 if (ret)
87ad72a5 1889 nvme_free_host_mem(dev);
9620cfba 1890 return ret;
9d713c2b
KB		 1891}
1892
8d85fce7 1893static int nvme_setup_io_queues(struct nvme_dev *dev)
b60503ba 1894{
a4aea562 1895 struct nvme_queue *adminq = dev->queues[0];
e75ec752 1896 struct pci_dev *pdev = to_pci_dev(dev->dev);
97f6ef64
XY		 1897 int result, nr_io_queues;
1898 unsigned long size;
b60503ba 1899
425a17cb 1900 nr_io_queues = num_present_cpus();
9a0be7ab
CH		 1901 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
1902 if (result < 0)
1b23484b 1903 return result;
9a0be7ab 1904
f5fa90dc 1905 if (nr_io_queues == 0)
a5229050 1906 return 0;
b60503ba 1907
8ffaadf7
JD		 1908 if (dev->cmb && NVME_CMB_SQS(dev->cmbsz)) {
1909 result = nvme_cmb_qdepth(dev, nr_io_queues,
1910 sizeof(struct nvme_command));
1911 if (result > 0)
1912 dev->q_depth = result;
1913 else
1914 nvme_release_cmb(dev);
1915 }
1916
97f6ef64
XY		 1917 do {
1918 size = db_bar_size(dev, nr_io_queues);
1919 result = nvme_remap_bar(dev, size);
1920 if (!result)
1921 break;
1922 if (!--nr_io_queues)
1923 return -ENOMEM;
1924 } while (1);
1925 adminq->q_db = dev->dbs;
f1938f6e 1926
9d713c2b 1927 /* Deregister the admin queue's interrupt */
0ff199cb 1928 pci_free_irq(pdev, 0, adminq);
9d713c2b 1929
e32efbfc
JA		 1930 /*
1931 * If we enable msix early due to not intx, disable it again before
1932 * setting up the full range we need.
1933 */
dca51e78
CH		 1934 pci_free_irq_vectors(pdev);
1935 nr_io_queues = pci_alloc_irq_vectors(pdev, 1, nr_io_queues,
1936 PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY);
1937 if (nr_io_queues <= 0)
1938 return -EIO;
1939 dev->max_qid = nr_io_queues;
fa08a396 1940
063a8096
MW		 1941 /*
1942 * Should investigate if there's a performance win from allocating
1943 * more queues than interrupt vectors; it might allow the submission
1944 * path to scale better, even if the receive path is limited by the
1945 * number of interrupts.
1946 */
063a8096 1947
dca51e78 1948 result = queue_request_irq(adminq);
758dd7fd
JD		 1949 if (result) {
1950 adminq->cq_vector = -1;
d4875622 1951 return result;
758dd7fd 1952 }
749941f2 1953 return nvme_create_io_queues(dev);
b60503ba
MW		 1954}
1955
2a842aca 1956static void nvme_del_queue_end(struct request *req, blk_status_t error)
a5768aa8 1957{
db3cbfff 1958 struct nvme_queue *nvmeq = req->end_io_data;
b5875222 1959
db3cbfff
KB		 1960 blk_mq_free_request(req);
1961 complete(&nvmeq->dev->ioq_wait);
a5768aa8
KB		 1962}
1963
2a842aca 1964static void nvme_del_cq_end(struct request *req, blk_status_t error)
a5768aa8 1965{
db3cbfff 1966 struct nvme_queue *nvmeq = req->end_io_data;
a5768aa8 1967
db3cbfff
KB		 1968 if (!error) {
1969 unsigned long flags;
1970
2e39e0f6
ML		 1971 /*
1972 * We might be called with the AQ q_lock held
1973 * and the I/O queue q_lock should always
1974 * nest inside the AQ one.
1975 */
1976 spin_lock_irqsave_nested(&nvmeq->q_lock, flags,
1977 SINGLE_DEPTH_NESTING);
db3cbfff
KB		 1978 nvme_process_cq(nvmeq);
1979 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
a5768aa8 1980 }
db3cbfff
KB		 1981
1982 nvme_del_queue_end(req, error);
a5768aa8
KB		 1983}
1984
db3cbfff 1985static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
bda4e0fb 1986{
db3cbfff
KB		 1987 struct request_queue *q = nvmeq->dev->ctrl.admin_q;
1988 struct request *req;
1989 struct nvme_command cmd;
bda4e0fb 1990
db3cbfff
KB		 1991 memset(&cmd, 0, sizeof(cmd));
1992 cmd.delete_queue.opcode = opcode;
1993 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
bda4e0fb 1994
eb71f435 1995 req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
db3cbfff
KB		 1996 if (IS_ERR(req))
1997 return PTR_ERR(req);
bda4e0fb 1998
db3cbfff
KB		 1999 req->timeout = ADMIN_TIMEOUT;
2000 req->end_io_data = nvmeq;
2001
2002 blk_execute_rq_nowait(q, NULL, req, false,
2003 opcode == nvme_admin_delete_cq ?
2004 nvme_del_cq_end : nvme_del_queue_end);
2005 return 0;
bda4e0fb
KB		 2006}
2007
70659060 2008static void nvme_disable_io_queues(struct nvme_dev *dev, int queues)
a5768aa8 2009{
70659060 2010 int pass;
db3cbfff
KB		 2011 unsigned long timeout;
2012 u8 opcode = nvme_admin_delete_sq;
a5768aa8 2013
db3cbfff 2014 for (pass = 0; pass < 2; pass++) {
014a0d60 2015 int sent = 0, i = queues;
db3cbfff
KB		 2016
2017 reinit_completion(&dev->ioq_wait);
2018 retry:
2019 timeout = ADMIN_TIMEOUT;
c21377f8
GKB		 2020 for (; i > 0; i--, sent++)
2021 if (nvme_delete_queue(dev->queues[i], opcode))
db3cbfff 2022 break;
c21377f8 2023
db3cbfff
KB		 2024 while (sent--) {
2025 timeout = wait_for_completion_io_timeout(&dev->ioq_wait, timeout);
2026 if (timeout == 0)
2027 return;
2028 if (i)
2029 goto retry;
2030 }
2031 opcode = nvme_admin_delete_cq;
2032 }
a5768aa8
KB		 2033}
2034
422ef0c7
MW		 2035/*
2036 * Return: error value if an error occurred setting up the queues or calling
2037 * Identify Device. 0 if these succeeded, even if adding some of the
2038 * namespaces failed. At the moment, these failures are silent. TBD which
2039 * failures should be reported.
2040 */
8d85fce7 2041static int nvme_dev_add(struct nvme_dev *dev)
b60503ba 2042{
5bae7f73 2043 if (!dev->ctrl.tagset) {
ffe7704d
KB		 2044 dev->tagset.ops = &nvme_mq_ops;
2045 dev->tagset.nr_hw_queues = dev->online_queues - 1;
2046 dev->tagset.timeout = NVME_IO_TIMEOUT;
2047 dev->tagset.numa_node = dev_to_node(dev->dev);
2048 dev->tagset.queue_depth =
a4aea562 2049 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
a7a7cbe3
CK		 2050 dev->tagset.cmd_size = nvme_pci_cmd_size(dev, false);
2051 if ((dev->ctrl.sgls & ((1 << 0) | (1 << 1))) && sgl_threshold) {
2052 dev->tagset.cmd_size = max(dev->tagset.cmd_size,
2053 nvme_pci_cmd_size(dev, true));
2054 }
ffe7704d
KB		 2055 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2056 dev->tagset.driver_data = dev;
b60503ba 2057
ffe7704d
KB		 2058 if (blk_mq_alloc_tag_set(&dev->tagset))
2059 return 0;
5bae7f73 2060 dev->ctrl.tagset = &dev->tagset;
f9f38e33
HK		 2061
2062 nvme_dbbuf_set(dev);
949928c1
KB		 2063 } else {
2064 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2065
2066 /* Free previously allocated queues that are no longer usable */
2067 nvme_free_queues(dev, dev->online_queues);
ffe7704d 2068 }
949928c1 2069
e1e5e564 2070 return 0;
b60503ba
MW		 2071}
2072
b00a726a 2073static int nvme_pci_enable(struct nvme_dev *dev)
0877cb0d 2074{
b00a726a 2075 int result = -ENOMEM;
e75ec752 2076 struct pci_dev *pdev = to_pci_dev(dev->dev);
0877cb0d
KB		 2077
2078 if (pci_enable_device_mem(pdev))
2079 return result;
2080
0877cb0d 2081 pci_set_master(pdev);
0877cb0d 2082
e75ec752
CH		 2083 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) &&
2084 dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32)))
052d0efa 2085 goto disable;
0877cb0d 2086
7a67cbea 2087 if (readl(dev->bar + NVME_REG_CSTS) == -1) {
0e53d180 2088 result = -ENODEV;
b00a726a 2089 goto disable;
0e53d180 2090 }
e32efbfc
JA		 2091
2092 /*
a5229050
KB		 2093 * Some devices and/or platforms don't advertise or work with INTx
2094 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2095 * adjust this later.
e32efbfc 2096 */
dca51e78
CH		 2097 result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
2098 if (result < 0)
2099 return result;
e32efbfc 2100
20d0dfe6 2101 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
7a67cbea 2102
20d0dfe6 2103 dev->q_depth = min_t(int, NVME_CAP_MQES(dev->ctrl.cap) + 1,
b27c1e68 2104 io_queue_depth);
20d0dfe6 2105 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
7a67cbea 2106 dev->dbs = dev->bar + 4096;
1f390c1f
SG		 2107
2108 /*
2109 * Temporary fix for the Apple controller found in the MacBook8,1 and
2110 * some MacBook7,1 to avoid controller resets and data loss.
2111 */
2112 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
2113 dev->q_depth = 2;
9bdcfb10
CH		 2114 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
2115 "set queue depth=%u to work around controller resets\n",
1f390c1f 2116 dev->q_depth);
d554b5e1
MP		 2117 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2118 (pdev->device == 0xa821 || pdev->device == 0xa822) &&
20d0dfe6 2119 NVME_CAP_MQES(dev->ctrl.cap) == 0) {
d554b5e1
MP		 2120 dev->q_depth = 64;
2121 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2122 "set queue depth=%u\n", dev->q_depth);
1f390c1f
SG		 2123 }
2124
202021c1
SB		 2125 /*
2126 * CMBs can currently only exist on >=1.2 PCIe devices. We only
1c78f773
MG		 2127 * populate sysfs if a CMB is implemented. Since nvme_dev_attrs_group
2128 * has no name we can pass NULL as final argument to
2129 * sysfs_add_file_to_group.
202021c1
SB		 2130 */
2131
8ef2074d 2132 if (readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 2, 0)) {
8ffaadf7 2133 dev->cmb = nvme_map_cmb(dev);
1c78f773 2134 if (dev->cmb) {
202021c1
SB		 2135 if (sysfs_add_file_to_group(&dev->ctrl.device->kobj,
2136 &dev_attr_cmb.attr, NULL))
9bdcfb10 2137 dev_warn(dev->ctrl.device,
202021c1
SB		 2138 "failed to add sysfs attribute for CMB\n");
2139 }
2140 }
2141
a0a3408e
KB		 2142 pci_enable_pcie_error_reporting(pdev);
2143 pci_save_state(pdev);
0877cb0d
KB		 2144 return 0;
2145
2146 disable:
0877cb0d
KB		 2147 pci_disable_device(pdev);
2148 return result;
2149}
2150
2151static void nvme_dev_unmap(struct nvme_dev *dev)
b00a726a
KB		 2152{
2153 if (dev->bar)
2154 iounmap(dev->bar);
a1f447b3 2155 pci_release_mem_regions(to_pci_dev(dev->dev));
b00a726a
KB		 2156}
2157
2158static void nvme_pci_disable(struct nvme_dev *dev)
0877cb0d 2159{
e75ec752
CH		 2160 struct pci_dev *pdev = to_pci_dev(dev->dev);
2161
f63572df 2162 nvme_release_cmb(dev);
dca51e78 2163 pci_free_irq_vectors(pdev);
0877cb0d 2164
a0a3408e
KB		 2165 if (pci_is_enabled(pdev)) {
2166 pci_disable_pcie_error_reporting(pdev);
e75ec752 2167 pci_disable_device(pdev);
4d115420 2168 }
4d115420
KB		 2169}
2170
a5cdb68c 2171static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
b60503ba 2172{
70659060 2173 int i, queues;
302ad8cc
KB		 2174 bool dead = true;
2175 struct pci_dev *pdev = to_pci_dev(dev->dev);
22404274 2176
77bf25ea 2177 mutex_lock(&dev->shutdown_lock);
302ad8cc
KB		 2178 if (pci_is_enabled(pdev)) {
2179 u32 csts = readl(dev->bar + NVME_REG_CSTS);
2180
ebef7368
KB		 2181 if (dev->ctrl.state == NVME_CTRL_LIVE ||
2182 dev->ctrl.state == NVME_CTRL_RESETTING)
302ad8cc
KB		 2183 nvme_start_freeze(&dev->ctrl);
2184 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
2185 pdev->error_state != pci_channel_io_normal);
c9d3bf88 2186 }
c21377f8 2187
302ad8cc
KB		 2188 /*
2189 * Give the controller a chance to complete all entered requests if
2190 * doing a safe shutdown.
2191 */
87ad72a5
CH		 2192 if (!dead) {
2193 if (shutdown)
2194 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
2195
2196 /*
2197 * If the controller is still alive tell it to stop using the
2198 * host memory buffer. In theory the shutdown / reset should
2199 * make sure that it doesn't access the host memoery anymore,
2200 * but I'd rather be safe than sorry..
2201 */
2202 if (dev->host_mem_descs)
2203 nvme_set_host_mem(dev, 0);
2204
2205 }
302ad8cc
KB		 2206 nvme_stop_queues(&dev->ctrl);
2207
70659060 2208 queues = dev->online_queues - 1;
d858e5f0 2209 for (i = dev->ctrl.queue_count - 1; i > 0; i--)
c21377f8
GKB		 2210 nvme_suspend_queue(dev->queues[i]);
2211
302ad8cc 2212 if (dead) {
82469c59
GKB		 2213 /* A device might become IO incapable very soon during
2214 * probe, before the admin queue is configured. Thus,
2215 * queue_count can be 0 here.
2216 */
d858e5f0 2217 if (dev->ctrl.queue_count)
82469c59 2218 nvme_suspend_queue(dev->queues[0]);
4d115420 2219 } else {
70659060 2220 nvme_disable_io_queues(dev, queues);
a5cdb68c 2221 nvme_disable_admin_queue(dev, shutdown);
4d115420 2222 }
b00a726a 2223 nvme_pci_disable(dev);
07836e65 2224
e1958e65
ML		 2225 blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
2226 blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
302ad8cc
KB		 2227
2228 /*
2229 * The driver will not be starting up queues again if shutting down so
2230 * must flush all entered requests to their failed completion to avoid
2231 * deadlocking blk-mq hot-cpu notifier.
2232 */
2233 if (shutdown)
2234 nvme_start_queues(&dev->ctrl);
77bf25ea 2235 mutex_unlock(&dev->shutdown_lock);
b60503ba
MW		 2236}
2237
091b6092
MW		 2238static int nvme_setup_prp_pools(struct nvme_dev *dev)
2239{
e75ec752 2240 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
091b6092
MW		 2241 PAGE_SIZE, PAGE_SIZE, 0);
2242 if (!dev->prp_page_pool)
2243 return -ENOMEM;
2244
99802a7a 2245 /* Optimisation for I/Os between 4k and 128k */
e75ec752 2246 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
99802a7a
MW		 2247 256, 256, 0);
2248 if (!dev->prp_small_pool) {
2249 dma_pool_destroy(dev->prp_page_pool);
2250 return -ENOMEM;
2251 }
091b6092
MW		 2252 return 0;
2253}
2254
2255static void nvme_release_prp_pools(struct nvme_dev *dev)
2256{
2257 dma_pool_destroy(dev->prp_page_pool);
99802a7a 2258 dma_pool_destroy(dev->prp_small_pool);
091b6092
MW		 2259}
2260
1673f1f0 2261static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
5e82e952 2262{
1673f1f0 2263 struct nvme_dev *dev = to_nvme_dev(ctrl);
9ac27090 2264
f9f38e33 2265 nvme_dbbuf_dma_free(dev);
e75ec752 2266 put_device(dev->dev);
4af0e21c
KB		 2267 if (dev->tagset.tags)
2268 blk_mq_free_tag_set(&dev->tagset);
1c63dc66
CH		 2269 if (dev->ctrl.admin_q)
2270 blk_put_queue(dev->ctrl.admin_q);
5e82e952 2271 kfree(dev->queues);
e286bcfc 2272 free_opal_dev(dev->ctrl.opal_dev);
5e82e952
KB		 2273 kfree(dev);
2274}
2275
f58944e2
KB		 2276static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status)
2277{
237045fc 2278 dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status);
f58944e2 2279
d22524a4 2280 nvme_get_ctrl(&dev->ctrl);
69d9a99c 2281 nvme_dev_disable(dev, false);
03e0f3a6 2282 if (!queue_work(nvme_wq, &dev->remove_work))
f58944e2
KB		 2283 nvme_put_ctrl(&dev->ctrl);
2284}
2285
fd634f41 2286static void nvme_reset_work(struct work_struct *work)
5e82e952 2287{
d86c4d8e
CH		 2288 struct nvme_dev *dev =
2289 container_of(work, struct nvme_dev, ctrl.reset_work);
a98e58e5 2290 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
f58944e2 2291 int result = -ENODEV;
5e82e952 2292
82b057ca 2293 if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING))
fd634f41 2294 goto out;
5e82e952 2295
fd634f41
CH		 2296 /*
2297 * If we're called to reset a live controller first shut it down before
2298 * moving on.
2299 */
b00a726a 2300 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
a5cdb68c 2301 nvme_dev_disable(dev, false);
5e82e952 2302
b00a726a 2303 result = nvme_pci_enable(dev);
f0b50732 2304 if (result)
3cf519b5 2305 goto out;
f0b50732 2306
01ad0990 2307 result = nvme_pci_configure_admin_queue(dev);
f0b50732 2308 if (result)
f58944e2 2309 goto out;
f0b50732 2310
0fb59cbc
KB		 2311 result = nvme_alloc_admin_tags(dev);
2312 if (result)
f58944e2 2313 goto out;
b9afca3e 2314
ce4541f4
CH		 2315 result = nvme_init_identify(&dev->ctrl);
2316 if (result)
f58944e2 2317 goto out;
ce4541f4 2318
e286bcfc
SB		 2319 if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
2320 if (!dev->ctrl.opal_dev)
2321 dev->ctrl.opal_dev =
2322 init_opal_dev(&dev->ctrl, &nvme_sec_submit);
2323 else if (was_suspend)
2324 opal_unlock_from_suspend(dev->ctrl.opal_dev);
2325 } else {
2326 free_opal_dev(dev->ctrl.opal_dev);
2327 dev->ctrl.opal_dev = NULL;
4f1244c8 2328 }
a98e58e5 2329
f9f38e33
HK		 2330 if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) {
2331 result = nvme_dbbuf_dma_alloc(dev);
2332 if (result)
2333 dev_warn(dev->dev,
2334 "unable to allocate dma for dbbuf\n");
2335 }
2336
9620cfba
CH		 2337 if (dev->ctrl.hmpre) {
2338 result = nvme_setup_host_mem(dev);
2339 if (result < 0)
2340 goto out;
2341 }
87ad72a5 2342
f0b50732 2343 result = nvme_setup_io_queues(dev);
badc34d4 2344 if (result)
f58944e2 2345 goto out;
f0b50732 2346
2659e57b
CH		 2347 /*
2348 * Keep the controller around but remove all namespaces if we don't have
2349 * any working I/O queue.
2350 */
3cf519b5 2351 if (dev->online_queues < 2) {
1b3c47c1 2352 dev_warn(dev->ctrl.device, "IO queues not created\n");
3b24774e 2353 nvme_kill_queues(&dev->ctrl);
5bae7f73 2354 nvme_remove_namespaces(&dev->ctrl);
3cf519b5 2355 } else {
25646264 2356 nvme_start_queues(&dev->ctrl);
302ad8cc 2357 nvme_wait_freeze(&dev->ctrl);
3cf519b5 2358 nvme_dev_add(dev);
302ad8cc 2359 nvme_unfreeze(&dev->ctrl);
3cf519b5
CH		 2360 }
2361
bb8d261e
CH		 2362 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
2363 dev_warn(dev->ctrl.device, "failed to mark controller live\n");
2364 goto out;
2365 }
92911a55 2366
d09f2b45 2367 nvme_start_ctrl(&dev->ctrl);
3cf519b5 2368 return;
f0b50732 2369
3cf519b5 2370 out:
f58944e2 2371 nvme_remove_dead_ctrl(dev, result);
f0b50732
KB		 2372}
2373
5c8809e6 2374static void nvme_remove_dead_ctrl_work(struct work_struct *work)
9a6b9458 2375{
5c8809e6 2376 struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
e75ec752 2377 struct pci_dev *pdev = to_pci_dev(dev->dev);
9a6b9458 2378
69d9a99c 2379 nvme_kill_queues(&dev->ctrl);
9a6b9458 2380 if (pci_get_drvdata(pdev))
921920ab 2381 device_release_driver(&pdev->dev);
1673f1f0 2382 nvme_put_ctrl(&dev->ctrl);
9a6b9458
KB		 2383}
2384
1c63dc66 2385static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
9ca97374 2386{
1c63dc66 2387 *val = readl(to_nvme_dev(ctrl)->bar + off);
90667892 2388 return 0;
9ca97374
TH		 2389}
2390
5fd4ce1b 2391static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
4cc06521 2392{
5fd4ce1b
CH		 2393 writel(val, to_nvme_dev(ctrl)->bar + off);
2394 return 0;
2395}
4cc06521 2396
7fd8930f
CH		 2397static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2398{
2399 *val = readq(to_nvme_dev(ctrl)->bar + off);
2400 return 0;
4cc06521
KB		 2401}
2402
1c63dc66 2403static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
1a353d85 2404 .name = "pcie",
e439bb12 2405 .module = THIS_MODULE,
c81bfba9 2406 .flags = NVME_F_METADATA_SUPPORTED,
1c63dc66 2407 .reg_read32 = nvme_pci_reg_read32,
5fd4ce1b 2408 .reg_write32 = nvme_pci_reg_write32,
7fd8930f 2409 .reg_read64 = nvme_pci_reg_read64,
1673f1f0 2410 .free_ctrl = nvme_pci_free_ctrl,
f866fc42 2411 .submit_async_event = nvme_pci_submit_async_event,
1c63dc66 2412};
4cc06521 2413
b00a726a
KB		 2414static int nvme_dev_map(struct nvme_dev *dev)
2415{
b00a726a
KB		 2416 struct pci_dev *pdev = to_pci_dev(dev->dev);
2417
a1f447b3 2418 if (pci_request_mem_regions(pdev, "nvme"))
b00a726a
KB		 2419 return -ENODEV;
2420
97f6ef64 2421 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
b00a726a
KB		 2422 goto release;
2423
9fa196e7 2424 return 0;
b00a726a 2425 release:
9fa196e7
MG		 2426 pci_release_mem_regions(pdev);
2427 return -ENODEV;
b00a726a
KB		 2428}
2429
8427bbc2 2430static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
ff5350a8
AL		 2431{
2432 if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
2433 /*
2434 * Several Samsung devices seem to drop off the PCIe bus
2435 * randomly when APST is on and uses the deepest sleep state.
2436 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2437 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2438 * 950 PRO 256GB", but it seems to be restricted to two Dell
2439 * laptops.
2440 */
2441 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
2442 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
2443 dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
2444 return NVME_QUIRK_NO_DEEPEST_PS;
8427bbc2
KHF		 2445 } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
2446 /*
2447 * Samsung SSD 960 EVO drops off the PCIe bus after system
2448 * suspend on a Ryzen board, ASUS PRIME B350M-A.
2449 */
2450 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
2451 dmi_match(DMI_BOARD_NAME, "PRIME B350M-A"))
2452 return NVME_QUIRK_NO_APST;
ff5350a8
AL		 2453 }
2454
2455 return 0;
2456}
2457
8d85fce7 2458static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
b60503ba 2459{
a4aea562 2460 int node, result = -ENOMEM;
b60503ba 2461 struct nvme_dev *dev;
ff5350a8 2462 unsigned long quirks = id->driver_data;
b60503ba 2463
a4aea562
MB		 2464 node = dev_to_node(&pdev->dev);
2465 if (node == NUMA_NO_NODE)
2fa84351 2466 set_dev_node(&pdev->dev, first_memory_node);
a4aea562
MB		 2467
2468 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
b60503ba
MW		 2469 if (!dev)
2470 return -ENOMEM;
a4aea562
MB		 2471 dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *),
2472 GFP_KERNEL, node);
b60503ba
MW		 2473 if (!dev->queues)
2474 goto free;
2475
e75ec752 2476 dev->dev = get_device(&pdev->dev);
9a6b9458 2477 pci_set_drvdata(pdev, dev);
1c63dc66 2478
b00a726a
KB		 2479 result = nvme_dev_map(dev);
2480 if (result)
b00c9b7a 2481 goto put_pci;
b00a726a 2482
d86c4d8e 2483 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
5c8809e6 2484 INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
77bf25ea 2485 mutex_init(&dev->shutdown_lock);
db3cbfff 2486 init_completion(&dev->ioq_wait);
b60503ba 2487
091b6092
MW		 2488 result = nvme_setup_prp_pools(dev);
2489 if (result)
b00c9b7a 2490 goto unmap;
4cc06521 2491
8427bbc2 2492 quirks |= check_vendor_combination_bug(pdev);
ff5350a8 2493
f3ca80fc 2494 result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
ff5350a8 2495 quirks);
4cc06521 2496 if (result)
2e1d8448 2497 goto release_pools;
740216fc 2498
82b057ca 2499 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_RESETTING);
1b3c47c1
SG		 2500 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
2501
d86c4d8e 2502 queue_work(nvme_wq, &dev->ctrl.reset_work);
b60503ba
MW		 2503 return 0;
2504
0877cb0d 2505 release_pools:
091b6092 2506 nvme_release_prp_pools(dev);
b00c9b7a
CJ		 2507 unmap:
2508 nvme_dev_unmap(dev);
a96d4f5c 2509 put_pci:
e75ec752 2510 put_device(dev->dev);
b60503ba
MW		 2511 free:
2512 kfree(dev->queues);
b60503ba
MW		 2513 kfree(dev);
2514 return result;
2515}
2516
775755ed 2517static void nvme_reset_prepare(struct pci_dev *pdev)
f0d54a54 2518{
a6739479 2519 struct nvme_dev *dev = pci_get_drvdata(pdev);
f263fbb8 2520 nvme_dev_disable(dev, false);
775755ed 2521}
f0d54a54 2522
775755ed
CH		 2523static void nvme_reset_done(struct pci_dev *pdev)
2524{
f263fbb8
LT		 2525 struct nvme_dev *dev = pci_get_drvdata(pdev);
2526 nvme_reset_ctrl(&dev->ctrl);
f0d54a54
KB		 2527}
2528
09ece142
KB		 2529static void nvme_shutdown(struct pci_dev *pdev)
2530{
2531 struct nvme_dev *dev = pci_get_drvdata(pdev);
a5cdb68c 2532 nvme_dev_disable(dev, true);
09ece142
KB		 2533}
2534
f58944e2
KB		 2535/*
2536 * The driver's remove may be called on a device in a partially initialized
2537 * state. This function must not have any dependencies on the device state in
2538 * order to proceed.
2539 */
8d85fce7 2540static void nvme_remove(struct pci_dev *pdev)
b60503ba
MW		 2541{
2542 struct nvme_dev *dev = pci_get_drvdata(pdev);
9a6b9458 2543
bb8d261e
CH		 2544 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
2545
d86c4d8e 2546 cancel_work_sync(&dev->ctrl.reset_work);
9a6b9458 2547 pci_set_drvdata(pdev, NULL);
0ff9d4e1 2548
6db28eda 2549 if (!pci_device_is_present(pdev)) {
0ff9d4e1 2550 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
6db28eda
KB		 2551 nvme_dev_disable(dev, false);
2552 }
0ff9d4e1 2553
d86c4d8e 2554 flush_work(&dev->ctrl.reset_work);
d09f2b45
SG		 2555 nvme_stop_ctrl(&dev->ctrl);
2556 nvme_remove_namespaces(&dev->ctrl);
a5cdb68c 2557 nvme_dev_disable(dev, true);
87ad72a5 2558 nvme_free_host_mem(dev);
a4aea562 2559 nvme_dev_remove_admin(dev);
a1a5ef99 2560 nvme_free_queues(dev, 0);
d09f2b45 2561 nvme_uninit_ctrl(&dev->ctrl);
9a6b9458 2562 nvme_release_prp_pools(dev);
b00a726a 2563 nvme_dev_unmap(dev);
1673f1f0 2564 nvme_put_ctrl(&dev->ctrl);
b60503ba
MW		 2565}
2566
13880f5b
KB		 2567static int nvme_pci_sriov_configure(struct pci_dev *pdev, int numvfs)
2568{
2569 int ret = 0;
2570
2571 if (numvfs == 0) {
2572 if (pci_vfs_assigned(pdev)) {
2573 dev_warn(&pdev->dev,
2574 "Cannot disable SR-IOV VFs while assigned\n");
2575 return -EPERM;
2576 }
2577 pci_disable_sriov(pdev);
2578 return 0;
2579 }
2580
2581 ret = pci_enable_sriov(pdev, numvfs);
2582 return ret ? ret : numvfs;
2583}
2584
671a6018 2585#ifdef CONFIG_PM_SLEEP
cd638946
KB		 2586static int nvme_suspend(struct device *dev)
2587{
2588 struct pci_dev *pdev = to_pci_dev(dev);
2589 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2590
a5cdb68c 2591 nvme_dev_disable(ndev, true);
cd638946
KB		 2592 return 0;
2593}
2594
2595static int nvme_resume(struct device *dev)
2596{
2597 struct pci_dev *pdev = to_pci_dev(dev);
2598 struct nvme_dev *ndev = pci_get_drvdata(pdev);
cd638946 2599
d86c4d8e 2600 nvme_reset_ctrl(&ndev->ctrl);
9a6b9458 2601 return 0;
cd638946 2602}
671a6018 2603#endif
cd638946
KB		 2604
2605static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
b60503ba 2606
a0a3408e
KB		 2607static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
2608 pci_channel_state_t state)
2609{
2610 struct nvme_dev *dev = pci_get_drvdata(pdev);
2611
2612 /*
2613 * A frozen channel requires a reset. When detected, this method will
2614 * shutdown the controller to quiesce. The controller will be restarted
2615 * after the slot reset through driver's slot_reset callback.
2616 */
a0a3408e
KB		 2617 switch (state) {
2618 case pci_channel_io_normal:
2619 return PCI_ERS_RESULT_CAN_RECOVER;
2620 case pci_channel_io_frozen:
d011fb31
KB		 2621 dev_warn(dev->ctrl.device,
2622 "frozen state error detected, reset controller\n");
a5cdb68c 2623 nvme_dev_disable(dev, false);
a0a3408e
KB		 2624 return PCI_ERS_RESULT_NEED_RESET;
2625 case pci_channel_io_perm_failure:
d011fb31
KB		 2626 dev_warn(dev->ctrl.device,
2627 "failure state error detected, request disconnect\n");
a0a3408e
KB		 2628 return PCI_ERS_RESULT_DISCONNECT;
2629 }
2630 return PCI_ERS_RESULT_NEED_RESET;
2631}
2632
2633static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
2634{
2635 struct nvme_dev *dev = pci_get_drvdata(pdev);
2636
1b3c47c1 2637 dev_info(dev->ctrl.device, "restart after slot reset\n");
a0a3408e 2638 pci_restore_state(pdev);
d86c4d8e 2639 nvme_reset_ctrl(&dev->ctrl);
a0a3408e
KB		 2640 return PCI_ERS_RESULT_RECOVERED;
2641}
2642
2643static void nvme_error_resume(struct pci_dev *pdev)
2644{
2645 pci_cleanup_aer_uncorrect_error_status(pdev);
2646}
2647
1d352035 2648static const struct pci_error_handlers nvme_err_handler = {
b60503ba 2649 .error_detected = nvme_error_detected,
b60503ba
MW		 2650 .slot_reset = nvme_slot_reset,
2651 .resume = nvme_error_resume,
775755ed
CH		 2652 .reset_prepare = nvme_reset_prepare,
2653 .reset_done = nvme_reset_done,
b60503ba
MW		 2654};
2655
6eb0d698 2656static const struct pci_device_id nvme_id_table[] = {
106198ed 2657 { PCI_VDEVICE(INTEL, 0x0953),
08095e70 2658 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 2659 NVME_QUIRK_DEALLOCATE_ZEROES, },
99466e70
KB		 2660 { PCI_VDEVICE(INTEL, 0x0a53),
2661 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 2662 NVME_QUIRK_DEALLOCATE_ZEROES, },
99466e70
KB		 2663 { PCI_VDEVICE(INTEL, 0x0a54),
2664 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 2665 NVME_QUIRK_DEALLOCATE_ZEROES, },
f99cb7af
DWF		 2666 { PCI_VDEVICE(INTEL, 0x0a55),
2667 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2668 NVME_QUIRK_DEALLOCATE_ZEROES, },
50af47d0
AL		 2669 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */
2670 .driver_data = NVME_QUIRK_NO_DEEPEST_PS },
540c801c
KB		 2671 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */
2672 .driver_data = NVME_QUIRK_IDENTIFY_CNS, },
54adc010
GP		 2673 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
2674 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
8c97eecc
JL		 2675 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */
2676 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
015282c9
WW		 2677 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
2678 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
d554b5e1
MP		 2679 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */
2680 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2681 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */
2682 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
608cc4b1
CH		 2683 { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */
2684 .driver_data = NVME_QUIRK_LIGHTNVM, },
2685 { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */
2686 .driver_data = NVME_QUIRK_LIGHTNVM, },
b60503ba 2687 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
c74dc780 2688 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) },
124298bd 2689 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
b60503ba
MW		 2690 { 0, }
2691};
2692MODULE_DEVICE_TABLE(pci, nvme_id_table);
2693
2694static struct pci_driver nvme_driver = {
2695 .name = "nvme",
2696 .id_table = nvme_id_table,
2697 .probe = nvme_probe,
8d85fce7 2698 .remove = nvme_remove,
09ece142 2699 .shutdown = nvme_shutdown,
cd638946
KB		 2700 .driver = {
2701 .pm = &nvme_dev_pm_ops,
2702 },
13880f5b 2703 .sriov_configure = nvme_pci_sriov_configure,
b60503ba
MW		 2704 .err_handler = &nvme_err_handler,
2705};
2706
2707static int __init nvme_init(void)
2708{
9a6327d2 2709 return pci_register_driver(&nvme_driver);
b60503ba
MW		 2710}
2711
2712static void __exit nvme_exit(void)
2713{
2714 pci_unregister_driver(&nvme_driver);
03e0f3a6 2715 flush_workqueue(nvme_wq);
21bd78bc 2716 _nvme_check_size();
b60503ba
MW		 2717}
2718
2719MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2720MODULE_LICENSE("GPL");
c78b4713 2721MODULE_VERSION("1.0");
b60503ba
MW		 2722module_init(nvme_init);
2723module_exit(nvme_exit);
Linux 6.x block layer and io_uring tree(s)