projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
nvme: split command copy into a helper
[linux-2.6-block.git] / drivers / nvme / host / pci.c
CommitLineData
5f37396d 1// SPDX-License-Identifier: GPL-2.0
b60503ba
MW		 2/*
3 * NVM Express device driver
6eb0d698 4 * Copyright (c) 2011-2014, Intel Corporation.
b60503ba
MW		 5 */
6
df4f9bc4 7#include <linux/acpi.h>
a0a3408e 8#include <linux/aer.h>
18119775 9#include <linux/async.h>
b60503ba 10#include <linux/blkdev.h>
a4aea562 11#include <linux/blk-mq.h>
dca51e78 12#include <linux/blk-mq-pci.h>
fe45e630 13#include <linux/blk-integrity.h>
ff5350a8 14#include <linux/dmi.h>
b60503ba
MW		 15#include <linux/init.h>
16#include <linux/interrupt.h>
17#include <linux/io.h>
b60503ba
MW		 18#include <linux/mm.h>
19#include <linux/module.h>
77bf25ea 20#include <linux/mutex.h>
d0877473 21#include <linux/once.h>
b60503ba 22#include <linux/pci.h>
d916b1be 23#include <linux/suspend.h>
e1e5e564 24#include <linux/t10-pi.h>
b60503ba 25#include <linux/types.h>
2f8e2c87 26#include <linux/io-64-nonatomic-lo-hi.h>
20d3bb92 27#include <linux/io-64-nonatomic-hi-lo.h>
a98e58e5 28#include <linux/sed-opal.h>
0f238ff5 29#include <linux/pci-p2pdma.h>
797a796a 30
604c01d5 31#include "trace.h"
f11bb3e2
CH		 32#include "nvme.h"
33
c1e0cc7e 34#define SQ_SIZE(q) ((q)->q_depth << (q)->sqes)
8a1d09a6 35#define CQ_SIZE(q) ((q)->q_depth * sizeof(struct nvme_completion))
c965809c 36
a7a7cbe3 37#define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc))
9d43cf64 38
943e942e
JA		 39/*
40 * These can be higher, but we need to ensure that any command doesn't
41 * require an sg allocation that needs more than a page of data.
42 */
43#define NVME_MAX_KB_SZ 4096
44#define NVME_MAX_SEGS 127
45
58ffacb5
MW		 46static int use_threaded_interrupts;
47module_param(use_threaded_interrupts, int, 0);
48
8ffaadf7 49static bool use_cmb_sqes = true;
69f4eb9f 50module_param(use_cmb_sqes, bool, 0444);
8ffaadf7
JD		 51MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
52
87ad72a5
CH		 53static unsigned int max_host_mem_size_mb = 128;
54module_param(max_host_mem_size_mb, uint, 0444);
55MODULE_PARM_DESC(max_host_mem_size_mb,
56 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
1fa6aead 57
a7a7cbe3
CK		 58static unsigned int sgl_threshold = SZ_32K;
59module_param(sgl_threshold, uint, 0644);
60MODULE_PARM_DESC(sgl_threshold,
61 "Use SGLs when average request segment size is larger or equal to "
62 "this size. Use 0 to disable SGLs.");
63
27453b45
SG		 64#define NVME_PCI_MIN_QUEUE_SIZE 2
65#define NVME_PCI_MAX_QUEUE_SIZE 4095
b27c1e68 66static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
67static const struct kernel_param_ops io_queue_depth_ops = {
68 .set = io_queue_depth_set,
61f3b896 69 .get = param_get_uint,
b27c1e68 70};
71
61f3b896 72static unsigned int io_queue_depth = 1024;
b27c1e68 73module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
27453b45 74MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2 and < 4096");
b27c1e68 75
9c9e76d5
WZ		 76static int io_queue_count_set(const char *val, const struct kernel_param *kp)
77{
78 unsigned int n;
79 int ret;
80
81 ret = kstrtouint(val, 10, &n);
82 if (ret != 0 || n > num_possible_cpus())
83 return -EINVAL;
84 return param_set_uint(val, kp);
85}
86
87static const struct kernel_param_ops io_queue_count_ops = {
88 .set = io_queue_count_set,
89 .get = param_get_uint,
90};
91
3f68baf7 92static unsigned int write_queues;
9c9e76d5 93module_param_cb(write_queues, &io_queue_count_ops, &write_queues, 0644);
3b6592f7
JA		 94MODULE_PARM_DESC(write_queues,
95 "Number of queues to use for writes. If not set, reads and writes "
96 "will share a queue set.");
97
3f68baf7 98static unsigned int poll_queues;
9c9e76d5 99module_param_cb(poll_queues, &io_queue_count_ops, &poll_queues, 0644);
4b04cc6a
JA		 100MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO.");
101
df4f9bc4
DB		 102static bool noacpi;
103module_param(noacpi, bool, 0444);
104MODULE_PARM_DESC(noacpi, "disable acpi bios quirks");
105
1c63dc66
CH		 106struct nvme_dev;
107struct nvme_queue;
b3fffdef 108
a5cdb68c 109static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
8fae268b 110static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode);
d4b4ff8e 111
1c63dc66
CH		 112/*
113 * Represents an NVM Express device. Each nvme_dev is a PCI function.
114 */
115struct nvme_dev {
147b27e4 116 struct nvme_queue *queues;
1c63dc66
CH		 117 struct blk_mq_tag_set tagset;
118 struct blk_mq_tag_set admin_tagset;
119 u32 __iomem *dbs;
120 struct device *dev;
121 struct dma_pool *prp_page_pool;
122 struct dma_pool *prp_small_pool;
1c63dc66
CH		 123 unsigned online_queues;
124 unsigned max_qid;
e20ba6e1 125 unsigned io_queues[HCTX_MAX_TYPES];
22b55601 126 unsigned int num_vecs;
7442ddce 127 u32 q_depth;
c1e0cc7e 128 int io_sqes;
1c63dc66 129 u32 db_stride;
1c63dc66 130 void __iomem *bar;
97f6ef64 131 unsigned long bar_mapped_size;
5c8809e6 132 struct work_struct remove_work;
77bf25ea 133 struct mutex shutdown_lock;
1c63dc66 134 bool subsystem;
1c63dc66 135 u64 cmb_size;
0f238ff5 136 bool cmb_use_sqes;
1c63dc66 137 u32 cmbsz;
202021c1 138 u32 cmbloc;
1c63dc66 139 struct nvme_ctrl ctrl;
d916b1be 140 u32 last_ps;
a5df5e79 141 bool hmb;
87ad72a5 142
943e942e
JA		 143 mempool_t *iod_mempool;
144
87ad72a5 145 /* shadow doorbell buffer support: */
f9f38e33
HK		 146 u32 *dbbuf_dbs;
147 dma_addr_t dbbuf_dbs_dma_addr;
148 u32 *dbbuf_eis;
149 dma_addr_t dbbuf_eis_dma_addr;
87ad72a5
CH		 150
151 /* host memory buffer support: */
152 u64 host_mem_size;
153 u32 nr_host_mem_descs;
4033f35d 154 dma_addr_t host_mem_descs_dma;
87ad72a5
CH		 155 struct nvme_host_mem_buf_desc *host_mem_descs;
156 void **host_mem_desc_bufs;
2a5bcfdd
WZ		 157 unsigned int nr_allocated_queues;
158 unsigned int nr_write_queues;
159 unsigned int nr_poll_queues;
0521905e
KB		 160
161 bool attrs_added;
4d115420 162};
1fa6aead 163
b27c1e68 164static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
165{
27453b45
SG		 166 return param_set_uint_minmax(val, kp, NVME_PCI_MIN_QUEUE_SIZE,
167 NVME_PCI_MAX_QUEUE_SIZE);
b27c1e68 168}
169
f9f38e33
HK		 170static inline unsigned int sq_idx(unsigned int qid, u32 stride)
171{
172 return qid * 2 * stride;
173}
174
175static inline unsigned int cq_idx(unsigned int qid, u32 stride)
176{
177 return (qid * 2 + 1) * stride;
178}
179
1c63dc66
CH		 180static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
181{
182 return container_of(ctrl, struct nvme_dev, ctrl);
183}
184
b60503ba
MW		 185/*
186 * An NVM Express queue. Each device has at least two (one for admin
187 * commands and one for I/O commands).
188 */
189struct nvme_queue {
091b6092 190 struct nvme_dev *dev;
1ab0cd69 191 spinlock_t sq_lock;
c1e0cc7e 192 void *sq_cmds;
3a7afd8e
CH		 193 /* only used for poll queues: */
194 spinlock_t cq_poll_lock ____cacheline_aligned_in_smp;
74943d45 195 struct nvme_completion *cqes;
b60503ba
MW		 196 dma_addr_t sq_dma_addr;
197 dma_addr_t cq_dma_addr;
b60503ba 198 u32 __iomem *q_db;
7442ddce 199 u32 q_depth;
7c349dde 200 u16 cq_vector;
b60503ba 201 u16 sq_tail;
38210800 202 u16 last_sq_tail;
b60503ba 203 u16 cq_head;
c30341dc 204 u16 qid;
e9539f47 205 u8 cq_phase;
c1e0cc7e 206 u8 sqes;
4e224106
CH		 207 unsigned long flags;
208#define NVMEQ_ENABLED 0
63223078 209#define NVMEQ_SQ_CMB 1
d1ed6aa1 210#define NVMEQ_DELETE_ERROR 2
7c349dde 211#define NVMEQ_POLLED 3
f9f38e33
HK		 212 u32 *dbbuf_sq_db;
213 u32 *dbbuf_cq_db;
214 u32 *dbbuf_sq_ei;
215 u32 *dbbuf_cq_ei;
d1ed6aa1 216 struct completion delete_done;
b60503ba
MW		 217};
218
71bd150c 219/*
9b048119
CH		 220 * The nvme_iod describes the data in an I/O.
221 *
222 * The sg pointer contains the list of PRP/SGL chunk allocations in addition
223 * to the actual struct scatterlist.
71bd150c
CH		 224 */
225struct nvme_iod {
d49187e9 226 struct nvme_request req;
af7fae85 227 struct nvme_command cmd;
f4800d6d 228 struct nvme_queue *nvmeq;
a7a7cbe3 229 bool use_sgl;
f4800d6d 230 int aborted;
71bd150c 231 int npages; /* In the PRP list. 0 means small pool in use */
71bd150c 232 int nents; /* Used in scatterlist */
71bd150c 233 dma_addr_t first_dma;
dff824b2 234 unsigned int dma_len; /* length of single DMA segment mapping */
783b94bd 235 dma_addr_t meta_dma;
f4800d6d 236 struct scatterlist *sg;
b60503ba
MW		 237};
238
2a5bcfdd 239static inline unsigned int nvme_dbbuf_size(struct nvme_dev *dev)
3b6592f7 240{
2a5bcfdd 241 return dev->nr_allocated_queues * 8 * dev->db_stride;
f9f38e33
HK		 242}
243
244static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
245{
2a5bcfdd 246 unsigned int mem_size = nvme_dbbuf_size(dev);
f9f38e33 247
58847f12
KB		 248 if (dev->dbbuf_dbs) {
249 /*
250 * Clear the dbbuf memory so the driver doesn't observe stale
251 * values from the previous instantiation.
252 */
253 memset(dev->dbbuf_dbs, 0, mem_size);
254 memset(dev->dbbuf_eis, 0, mem_size);
f9f38e33 255 return 0;
58847f12 256 }
f9f38e33
HK		 257
258 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
259 &dev->dbbuf_dbs_dma_addr,
260 GFP_KERNEL);
261 if (!dev->dbbuf_dbs)
262 return -ENOMEM;
263 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
264 &dev->dbbuf_eis_dma_addr,
265 GFP_KERNEL);
266 if (!dev->dbbuf_eis) {
267 dma_free_coherent(dev->dev, mem_size,
268 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
269 dev->dbbuf_dbs = NULL;
270 return -ENOMEM;
271 }
272
273 return 0;
274}
275
276static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
277{
2a5bcfdd 278 unsigned int mem_size = nvme_dbbuf_size(dev);
f9f38e33
HK		 279
280 if (dev->dbbuf_dbs) {
281 dma_free_coherent(dev->dev, mem_size,
282 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
283 dev->dbbuf_dbs = NULL;
284 }
285 if (dev->dbbuf_eis) {
286 dma_free_coherent(dev->dev, mem_size,
287 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
288 dev->dbbuf_eis = NULL;
289 }
290}
291
292static void nvme_dbbuf_init(struct nvme_dev *dev,
293 struct nvme_queue *nvmeq, int qid)
294{
295 if (!dev->dbbuf_dbs || !qid)
296 return;
297
298 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
299 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
300 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
301 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
302}
303
0f0d2c87
MI		 304static void nvme_dbbuf_free(struct nvme_queue *nvmeq)
305{
306 if (!nvmeq->qid)
307 return;
308
309 nvmeq->dbbuf_sq_db = NULL;
310 nvmeq->dbbuf_cq_db = NULL;
311 nvmeq->dbbuf_sq_ei = NULL;
312 nvmeq->dbbuf_cq_ei = NULL;
313}
314
f9f38e33
HK		 315static void nvme_dbbuf_set(struct nvme_dev *dev)
316{
f66e2804 317 struct nvme_command c = { };
0f0d2c87 318 unsigned int i;
f9f38e33
HK		 319
320 if (!dev->dbbuf_dbs)
321 return;
322
f9f38e33
HK		 323 c.dbbuf.opcode = nvme_admin_dbbuf;
324 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
325 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
326
327 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
9bdcfb10 328 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
f9f38e33
HK		 329 /* Free memory and continue on */
330 nvme_dbbuf_dma_free(dev);
0f0d2c87
MI		 331
332 for (i = 1; i <= dev->online_queues; i++)
333 nvme_dbbuf_free(&dev->queues[i]);
f9f38e33
HK		 334 }
335}
336
337static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
338{
339 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
340}
341
342/* Update dbbuf and return true if an MMIO is required */
343static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
344 volatile u32 *dbbuf_ei)
345{
346 if (dbbuf_db) {
347 u16 old_value;
348
349 /*
350 * Ensure that the queue is written before updating
351 * the doorbell in memory
352 */
353 wmb();
354
355 old_value = *dbbuf_db;
356 *dbbuf_db = value;
357
f1ed3df2
MW		 358 /*
359 * Ensure that the doorbell is updated before reading the event
360 * index from memory. The controller needs to provide similar
361 * ordering to ensure the envent index is updated before reading
362 * the doorbell.
363 */
364 mb();
365
f9f38e33
HK		 366 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value))
367 return false;
368 }
369
370 return true;
b60503ba
MW		 371}
372
ac3dd5bd
JA		 373/*
374 * Will slightly overestimate the number of pages needed. This is OK
375 * as it only leads to a small amount of wasted memory for the lifetime of
376 * the I/O.
377 */
b13c6393 378static int nvme_pci_npages_prp(void)
ac3dd5bd 379{
b13c6393 380 unsigned nprps = DIV_ROUND_UP(NVME_MAX_KB_SZ + NVME_CTRL_PAGE_SIZE,
6c3c05b0 381 NVME_CTRL_PAGE_SIZE);
ac3dd5bd
JA		 382 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
383}
384
a7a7cbe3
CK		 385/*
386 * Calculates the number of pages needed for the SGL segments. For example a 4k
387 * page can accommodate 256 SGL descriptors.
388 */
b13c6393 389static int nvme_pci_npages_sgl(void)
ac3dd5bd 390{
b13c6393
CK		 391 return DIV_ROUND_UP(NVME_MAX_SEGS * sizeof(struct nvme_sgl_desc),
392 PAGE_SIZE);
f4800d6d 393}
ac3dd5bd 394
b13c6393 395static size_t nvme_pci_iod_alloc_size(void)
f4800d6d 396{
b13c6393 397 size_t npages = max(nvme_pci_npages_prp(), nvme_pci_npages_sgl());
a7a7cbe3 398
b13c6393
CK		 399 return sizeof(__le64 *) * npages +
400 sizeof(struct scatterlist) * NVME_MAX_SEGS;
f4800d6d 401}
ac3dd5bd 402
a4aea562
MB		 403static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
404 unsigned int hctx_idx)
e85248e5 405{
a4aea562 406 struct nvme_dev *dev = data;
147b27e4 407 struct nvme_queue *nvmeq = &dev->queues[0];
a4aea562 408
42483228
KB		 409 WARN_ON(hctx_idx != 0);
410 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
42483228 411
a4aea562
MB		 412 hctx->driver_data = nvmeq;
413 return 0;
e85248e5
MW		 414}
415
a4aea562
MB		 416static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
417 unsigned int hctx_idx)
b60503ba 418{
a4aea562 419 struct nvme_dev *dev = data;
147b27e4 420 struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
a4aea562 421
42483228 422 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
a4aea562
MB		 423 hctx->driver_data = nvmeq;
424 return 0;
b60503ba
MW		 425}
426
d6296d39
CH		 427static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req,
428 unsigned int hctx_idx, unsigned int numa_node)
b60503ba 429{
d6296d39 430 struct nvme_dev *dev = set->driver_data;
f4800d6d 431 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
0350815a 432 int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0;
147b27e4 433 struct nvme_queue *nvmeq = &dev->queues[queue_idx];
a4aea562
MB		 434
435 BUG_ON(!nvmeq);
f4800d6d 436 iod->nvmeq = nvmeq;
59e29ce6
SG		 437
438 nvme_req(req)->ctrl = &dev->ctrl;
f4b9e6c9 439 nvme_req(req)->cmd = &iod->cmd;
a4aea562
MB		 440 return 0;
441}
442
3b6592f7
JA		 443static int queue_irq_offset(struct nvme_dev *dev)
444{
445 /* if we have more than 1 vec, admin queue offsets us by 1 */
446 if (dev->num_vecs > 1)
447 return 1;
448
449 return 0;
450}
451
dca51e78
CH		 452static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
453{
454 struct nvme_dev *dev = set->driver_data;
3b6592f7
JA		 455 int i, qoff, offset;
456
457 offset = queue_irq_offset(dev);
458 for (i = 0, qoff = 0; i < set->nr_maps; i++) {
459 struct blk_mq_queue_map *map = &set->map[i];
460
461 map->nr_queues = dev->io_queues[i];
462 if (!map->nr_queues) {
e20ba6e1 463 BUG_ON(i == HCTX_TYPE_DEFAULT);
7e849dd9 464 continue;
3b6592f7
JA		 465 }
466
4b04cc6a
JA		 467 /*
468 * The poll queue(s) doesn't have an IRQ (and hence IRQ
469 * affinity), so use the regular blk-mq cpu mapping
470 */
3b6592f7 471 map->queue_offset = qoff;
cb9e0e50 472 if (i != HCTX_TYPE_POLL && offset)
4b04cc6a
JA		 473 blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset);
474 else
475 blk_mq_map_queues(map);
3b6592f7
JA		 476 qoff += map->nr_queues;
477 offset += map->nr_queues;
478 }
479
480 return 0;
dca51e78
CH		 481}
482
38210800
KB		 483/*
484 * Write sq tail if we are asked to, or if the next command would wrap.
485 */
486static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq)
04f3eafd 487{
38210800
KB		 488 if (!write_sq) {
489 u16 next_tail = nvmeq->sq_tail + 1;
490
491 if (next_tail == nvmeq->q_depth)
492 next_tail = 0;
493 if (next_tail != nvmeq->last_sq_tail)
494 return;
495 }
496
04f3eafd
JA		 497 if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail,
498 nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei))
499 writel(nvmeq->sq_tail, nvmeq->q_db);
38210800 500 nvmeq->last_sq_tail = nvmeq->sq_tail;
04f3eafd
JA		 501}
502
3233b94c
JA		 503static inline void nvme_sq_copy_cmd(struct nvme_queue *nvmeq,
504 struct nvme_command *cmd)
b60503ba 505{
c1e0cc7e 506 memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes),
3233b94c 507 absolute_pointer(cmd), sizeof(*cmd));
90ea5ca4
CH		 508 if (++nvmeq->sq_tail == nvmeq->q_depth)
509 nvmeq->sq_tail = 0;
04f3eafd
JA		 510}
511
512static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx)
513{
514 struct nvme_queue *nvmeq = hctx->driver_data;
515
516 spin_lock(&nvmeq->sq_lock);
38210800
KB		 517 if (nvmeq->sq_tail != nvmeq->last_sq_tail)
518 nvme_write_sq_db(nvmeq, true);
90ea5ca4 519 spin_unlock(&nvmeq->sq_lock);
b60503ba
MW		 520}
521
a7a7cbe3 522static void **nvme_pci_iod_list(struct request *req)
b60503ba 523{
f4800d6d 524 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3 525 return (void **)(iod->sg + blk_rq_nr_phys_segments(req));
b60503ba
MW		 526}
527
955b1b5a
MI		 528static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req)
529{
530 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
20469a37 531 int nseg = blk_rq_nr_phys_segments(req);
955b1b5a
MI		 532 unsigned int avg_seg_size;
533
20469a37 534 avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
955b1b5a 535
253a0b76 536 if (!nvme_ctrl_sgl_supported(&dev->ctrl))
955b1b5a
MI		 537 return false;
538 if (!iod->nvmeq->qid)
539 return false;
540 if (!sgl_threshold || avg_seg_size < sgl_threshold)
541 return false;
542 return true;
543}
544
9275c206 545static void nvme_free_prps(struct nvme_dev *dev, struct request *req)
b60503ba 546{
6c3c05b0 547 const int last_prp = NVME_CTRL_PAGE_SIZE / sizeof(__le64) - 1;
9275c206
CH		 548 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
549 dma_addr_t dma_addr = iod->first_dma;
eca18b23 550 int i;
eca18b23 551
9275c206
CH		 552 for (i = 0; i < iod->npages; i++) {
553 __le64 *prp_list = nvme_pci_iod_list(req)[i];
554 dma_addr_t next_dma_addr = le64_to_cpu(prp_list[last_prp]);
555
556 dma_pool_free(dev->prp_page_pool, prp_list, dma_addr);
557 dma_addr = next_dma_addr;
7fe07d14 558 }
9275c206 559}
dff824b2 560
9275c206
CH		 561static void nvme_free_sgls(struct nvme_dev *dev, struct request *req)
562{
563 const int last_sg = SGES_PER_PAGE - 1;
564 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
565 dma_addr_t dma_addr = iod->first_dma;
566 int i;
dff824b2 567
9275c206
CH		 568 for (i = 0; i < iod->npages; i++) {
569 struct nvme_sgl_desc *sg_list = nvme_pci_iod_list(req)[i];
570 dma_addr_t next_dma_addr = le64_to_cpu((sg_list[last_sg]).addr);
dff824b2 571
9275c206
CH		 572 dma_pool_free(dev->prp_page_pool, sg_list, dma_addr);
573 dma_addr = next_dma_addr;
574 }
9275c206 575}
a7a7cbe3 576
9275c206
CH		 577static void nvme_unmap_sg(struct nvme_dev *dev, struct request *req)
578{
579 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3 580
9275c206
CH		 581 if (is_pci_p2pdma_page(sg_page(iod->sg)))
582 pci_p2pdma_unmap_sg(dev->dev, iod->sg, iod->nents,
583 rq_dma_dir(req));
584 else
585 dma_unmap_sg(dev->dev, iod->sg, iod->nents, rq_dma_dir(req));
586}
a7a7cbe3 587
9275c206
CH		 588static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
589{
590 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3 591
9275c206
CH		 592 if (iod->dma_len) {
593 dma_unmap_page(dev->dev, iod->first_dma, iod->dma_len,
594 rq_dma_dir(req));
595 return;
eca18b23 596 }
ac3dd5bd 597
9275c206
CH		 598 WARN_ON_ONCE(!iod->nents);
599
600 nvme_unmap_sg(dev, req);
601 if (iod->npages == 0)
602 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0],
603 iod->first_dma);
604 else if (iod->use_sgl)
605 nvme_free_sgls(dev, req);
606 else
607 nvme_free_prps(dev, req);
d43f1ccf 608 mempool_free(iod->sg, dev->iod_mempool);
b4ff9c8d
KB		 609}
610
d0877473
KB		 611static void nvme_print_sgl(struct scatterlist *sgl, int nents)
612{
613 int i;
614 struct scatterlist *sg;
615
616 for_each_sg(sgl, sg, nents, i) {
617 dma_addr_t phys = sg_phys(sg);
618 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
619 "dma_address:%pad dma_length:%d\n",
620 i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
621 sg_dma_len(sg));
622 }
623}
624
a7a7cbe3
CK		 625static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
626 struct request *req, struct nvme_rw_command *cmnd)
ff22b54f 627{
f4800d6d 628 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
99802a7a 629 struct dma_pool *pool;
b131c61d 630 int length = blk_rq_payload_bytes(req);
eca18b23 631 struct scatterlist *sg = iod->sg;
ff22b54f
MW		 632 int dma_len = sg_dma_len(sg);
633 u64 dma_addr = sg_dma_address(sg);
6c3c05b0 634 int offset = dma_addr & (NVME_CTRL_PAGE_SIZE - 1);
e025344c 635 __le64 *prp_list;
a7a7cbe3 636 void **list = nvme_pci_iod_list(req);
e025344c 637 dma_addr_t prp_dma;
eca18b23 638 int nprps, i;
ff22b54f 639
6c3c05b0 640 length -= (NVME_CTRL_PAGE_SIZE - offset);
5228b328
JS		 641 if (length <= 0) {
642 iod->first_dma = 0;
a7a7cbe3 643 goto done;
5228b328 644 }
ff22b54f 645
6c3c05b0 646 dma_len -= (NVME_CTRL_PAGE_SIZE - offset);
ff22b54f 647 if (dma_len) {
6c3c05b0 648 dma_addr += (NVME_CTRL_PAGE_SIZE - offset);
ff22b54f
MW		 649 } else {
650 sg = sg_next(sg);
651 dma_addr = sg_dma_address(sg);
652 dma_len = sg_dma_len(sg);
653 }
654
6c3c05b0 655 if (length <= NVME_CTRL_PAGE_SIZE) {
edd10d33 656 iod->first_dma = dma_addr;
a7a7cbe3 657 goto done;
e025344c
SMM		 658 }
659
6c3c05b0 660 nprps = DIV_ROUND_UP(length, NVME_CTRL_PAGE_SIZE);
99802a7a
MW		 661 if (nprps <= (256 / 8)) {
662 pool = dev->prp_small_pool;
eca18b23 663 iod->npages = 0;
99802a7a
MW		 664 } else {
665 pool = dev->prp_page_pool;
eca18b23 666 iod->npages = 1;
99802a7a
MW		 667 }
668
69d2b571 669 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
b77954cb 670 if (!prp_list) {
edd10d33 671 iod->first_dma = dma_addr;
eca18b23 672 iod->npages = -1;
86eea289 673 return BLK_STS_RESOURCE;
b77954cb 674 }
eca18b23
MW		 675 list[0] = prp_list;
676 iod->first_dma = prp_dma;
e025344c
SMM		 677 i = 0;
678 for (;;) {
6c3c05b0 679 if (i == NVME_CTRL_PAGE_SIZE >> 3) {
e025344c 680 __le64 *old_prp_list = prp_list;
69d2b571 681 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
eca18b23 682 if (!prp_list)
fa073216 683 goto free_prps;
eca18b23 684 list[iod->npages++] = prp_list;
7523d834
MW		 685 prp_list[0] = old_prp_list[i - 1];
686 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
687 i = 1;
e025344c
SMM		 688 }
689 prp_list[i++] = cpu_to_le64(dma_addr);
6c3c05b0
CK		 690 dma_len -= NVME_CTRL_PAGE_SIZE;
691 dma_addr += NVME_CTRL_PAGE_SIZE;
692 length -= NVME_CTRL_PAGE_SIZE;
e025344c
SMM		 693 if (length <= 0)
694 break;
695 if (dma_len > 0)
696 continue;
86eea289
KB		 697 if (unlikely(dma_len < 0))
698 goto bad_sgl;
e025344c
SMM		 699 sg = sg_next(sg);
700 dma_addr = sg_dma_address(sg);
701 dma_len = sg_dma_len(sg);
ff22b54f 702 }
a7a7cbe3
CK		 703done:
704 cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
705 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
86eea289 706 return BLK_STS_OK;
fa073216
CH		 707free_prps:
708 nvme_free_prps(dev, req);
709 return BLK_STS_RESOURCE;
710bad_sgl:
d0877473
KB		 711 WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents),
712 "Invalid SGL for payload:%d nents:%d\n",
713 blk_rq_payload_bytes(req), iod->nents);
86eea289 714 return BLK_STS_IOERR;
ff22b54f
MW		 715}
716
a7a7cbe3
CK		 717static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
718 struct scatterlist *sg)
719{
720 sge->addr = cpu_to_le64(sg_dma_address(sg));
721 sge->length = cpu_to_le32(sg_dma_len(sg));
722 sge->type = NVME_SGL_FMT_DATA_DESC << 4;
723}
724
725static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
726 dma_addr_t dma_addr, int entries)
727{
728 sge->addr = cpu_to_le64(dma_addr);
729 if (entries < SGES_PER_PAGE) {
730 sge->length = cpu_to_le32(entries * sizeof(*sge));
731 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
732 } else {
733 sge->length = cpu_to_le32(PAGE_SIZE);
734 sge->type = NVME_SGL_FMT_SEG_DESC << 4;
735 }
736}
737
738static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
b0f2853b 739 struct request *req, struct nvme_rw_command *cmd, int entries)
a7a7cbe3
CK		 740{
741 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3
CK		 742 struct dma_pool *pool;
743 struct nvme_sgl_desc *sg_list;
744 struct scatterlist *sg = iod->sg;
a7a7cbe3 745 dma_addr_t sgl_dma;
b0f2853b 746 int i = 0;
a7a7cbe3 747
a7a7cbe3
CK		 748 /* setting the transfer type as SGL */
749 cmd->flags = NVME_CMD_SGL_METABUF;
750
b0f2853b 751 if (entries == 1) {
a7a7cbe3
CK		 752 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
753 return BLK_STS_OK;
754 }
755
756 if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
757 pool = dev->prp_small_pool;
758 iod->npages = 0;
759 } else {
760 pool = dev->prp_page_pool;
761 iod->npages = 1;
762 }
763
764 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
765 if (!sg_list) {
766 iod->npages = -1;
767 return BLK_STS_RESOURCE;
768 }
769
770 nvme_pci_iod_list(req)[0] = sg_list;
771 iod->first_dma = sgl_dma;
772
773 nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
774
775 do {
776 if (i == SGES_PER_PAGE) {
777 struct nvme_sgl_desc *old_sg_desc = sg_list;
778 struct nvme_sgl_desc *link = &old_sg_desc[i - 1];
779
780 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
781 if (!sg_list)
fa073216 782 goto free_sgls;
a7a7cbe3
CK		 783
784 i = 0;
785 nvme_pci_iod_list(req)[iod->npages++] = sg_list;
786 sg_list[i++] = *link;
787 nvme_pci_sgl_set_seg(link, sgl_dma, entries);
788 }
789
790 nvme_pci_sgl_set_data(&sg_list[i++], sg);
a7a7cbe3 791 sg = sg_next(sg);
b0f2853b 792 } while (--entries > 0);
a7a7cbe3 793
a7a7cbe3 794 return BLK_STS_OK;
fa073216
CH		 795free_sgls:
796 nvme_free_sgls(dev, req);
797 return BLK_STS_RESOURCE;
a7a7cbe3
CK		 798}
799
dff824b2
CH		 800static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev,
801 struct request *req, struct nvme_rw_command *cmnd,
802 struct bio_vec *bv)
803{
804 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
6c3c05b0
CK		 805 unsigned int offset = bv->bv_offset & (NVME_CTRL_PAGE_SIZE - 1);
806 unsigned int first_prp_len = NVME_CTRL_PAGE_SIZE - offset;
dff824b2
CH		 807
808 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
809 if (dma_mapping_error(dev->dev, iod->first_dma))
810 return BLK_STS_RESOURCE;
811 iod->dma_len = bv->bv_len;
812
813 cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma);
814 if (bv->bv_len > first_prp_len)
815 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len);
359c1f88 816 return BLK_STS_OK;
dff824b2
CH		 817}
818
29791057
CH		 819static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev,
820 struct request *req, struct nvme_rw_command *cmnd,
821 struct bio_vec *bv)
822{
823 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
824
825 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
826 if (dma_mapping_error(dev->dev, iod->first_dma))
827 return BLK_STS_RESOURCE;
828 iod->dma_len = bv->bv_len;
829
049bf372 830 cmnd->flags = NVME_CMD_SGL_METABUF;
29791057
CH		 831 cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma);
832 cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len);
833 cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4;
359c1f88 834 return BLK_STS_OK;
29791057
CH		 835}
836
fc17b653 837static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
b131c61d 838 struct nvme_command *cmnd)
d29ec824 839{
f4800d6d 840 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
70479b71 841 blk_status_t ret = BLK_STS_RESOURCE;
b0f2853b 842 int nr_mapped;
d29ec824 843
dff824b2
CH		 844 if (blk_rq_nr_phys_segments(req) == 1) {
845 struct bio_vec bv = req_bvec(req);
846
847 if (!is_pci_p2pdma_page(bv.bv_page)) {
6c3c05b0 848 if (bv.bv_offset + bv.bv_len <= NVME_CTRL_PAGE_SIZE * 2)
dff824b2
CH		 849 return nvme_setup_prp_simple(dev, req,
850 &cmnd->rw, &bv);
29791057 851
e51183be 852 if (iod->nvmeq->qid && sgl_threshold &&
253a0b76 853 nvme_ctrl_sgl_supported(&dev->ctrl))
29791057
CH		 854 return nvme_setup_sgl_simple(dev, req,
855 &cmnd->rw, &bv);
dff824b2
CH		 856 }
857 }
858
859 iod->dma_len = 0;
d43f1ccf
CH		 860 iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC);
861 if (!iod->sg)
862 return BLK_STS_RESOURCE;
f9d03f96 863 sg_init_table(iod->sg, blk_rq_nr_phys_segments(req));
70479b71 864 iod->nents = blk_rq_map_sg(req->q, req, iod->sg);
ba1ca37e 865 if (!iod->nents)
fa073216 866 goto out_free_sg;
d29ec824 867
e0596ab2 868 if (is_pci_p2pdma_page(sg_page(iod->sg)))
2b9f4bb2
LG		 869 nr_mapped = pci_p2pdma_map_sg_attrs(dev->dev, iod->sg,
870 iod->nents, rq_dma_dir(req), DMA_ATTR_NO_WARN);
e0596ab2
LG		 871 else
872 nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents,
70479b71 873 rq_dma_dir(req), DMA_ATTR_NO_WARN);
b0f2853b 874 if (!nr_mapped)
fa073216 875 goto out_free_sg;
d29ec824 876
70479b71 877 iod->use_sgl = nvme_pci_use_sgls(dev, req);
955b1b5a 878 if (iod->use_sgl)
b0f2853b 879 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped);
a7a7cbe3
CK		 880 else
881 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
86eea289 882 if (ret != BLK_STS_OK)
fa073216
CH		 883 goto out_unmap_sg;
884 return BLK_STS_OK;
885
886out_unmap_sg:
887 nvme_unmap_sg(dev, req);
888out_free_sg:
889 mempool_free(iod->sg, dev->iod_mempool);
4aedb705
CH		 890 return ret;
891}
3045c0d0 892
4aedb705
CH		 893static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req,
894 struct nvme_command *cmnd)
895{
896 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
00df5cb4 897
4aedb705
CH		 898 iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req),
899 rq_dma_dir(req), 0);
900 if (dma_mapping_error(dev->dev, iod->meta_dma))
901 return BLK_STS_IOERR;
902 cmnd->rw.metadata = cpu_to_le64(iod->meta_dma);
359c1f88 903 return BLK_STS_OK;
00df5cb4
MW		 904}
905
d29ec824
CH		 906/*
907 * NOTE: ns is NULL when called on the admin queue.
908 */
fc17b653 909static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
a4aea562 910 const struct blk_mq_queue_data *bd)
edd10d33 911{
a4aea562
MB		 912 struct nvme_ns *ns = hctx->queue->queuedata;
913 struct nvme_queue *nvmeq = hctx->driver_data;
d29ec824 914 struct nvme_dev *dev = nvmeq->dev;
a4aea562 915 struct request *req = bd->rq;
9b048119 916 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
af7fae85 917 struct nvme_command *cmnd = &iod->cmd;
ebe6d874 918 blk_status_t ret;
e1e5e564 919
9b048119
CH		 920 iod->aborted = 0;
921 iod->npages = -1;
922 iod->nents = 0;
923
d1f06f4a
JA		 924 /*
925 * We should not need to do this, but we're still using this to
926 * ensure we can drain requests on a dying queue.
927 */
4e224106 928 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
d1f06f4a
JA		 929 return BLK_STS_IOERR;
930
d4060d2b
TC		 931 if (!nvme_check_ready(&dev->ctrl, req, true))
932 return nvme_fail_nonready_command(&dev->ctrl, req);
933
f4b9e6c9 934 ret = nvme_setup_cmd(ns, req);
fc17b653 935 if (ret)
f4800d6d 936 return ret;
a4aea562 937
fc17b653 938 if (blk_rq_nr_phys_segments(req)) {
af7fae85 939 ret = nvme_map_data(dev, req, cmnd);
fc17b653 940 if (ret)
9b048119 941 goto out_free_cmd;
fc17b653 942 }
a4aea562 943
4aedb705 944 if (blk_integrity_rq(req)) {
af7fae85 945 ret = nvme_map_metadata(dev, req, cmnd);
4aedb705
CH		 946 if (ret)
947 goto out_unmap_data;
948 }
949
aae239e1 950 blk_mq_start_request(req);
3233b94c
JA		 951 spin_lock(&nvmeq->sq_lock);
952 nvme_sq_copy_cmd(nvmeq, &iod->cmd);
953 nvme_write_sq_db(nvmeq, bd->last);
954 spin_unlock(&nvmeq->sq_lock);
fc17b653 955 return BLK_STS_OK;
4aedb705
CH		 956out_unmap_data:
957 nvme_unmap_data(dev, req);
f9d03f96
CH		 958out_free_cmd:
959 nvme_cleanup_cmd(req);
ba1ca37e 960 return ret;
b60503ba 961}
e1e5e564 962
c234a653 963static __always_inline void nvme_pci_unmap_rq(struct request *req)
eee417b0 964{
f4800d6d 965 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
4aedb705 966 struct nvme_dev *dev = iod->nvmeq->dev;
a4aea562 967
4aedb705
CH		 968 if (blk_integrity_rq(req))
969 dma_unmap_page(dev->dev, iod->meta_dma,
970 rq_integrity_vec(req)->bv_len, rq_data_dir(req));
b15c592d 971 if (blk_rq_nr_phys_segments(req))
4aedb705 972 nvme_unmap_data(dev, req);
c234a653
JA		 973}
974
975static void nvme_pci_complete_rq(struct request *req)
976{
977 nvme_pci_unmap_rq(req);
77f02a7a 978 nvme_complete_rq(req);
b60503ba
MW		 979}
980
c234a653
JA		 981static void nvme_pci_complete_batch(struct io_comp_batch *iob)
982{
983 nvme_complete_batch(iob, nvme_pci_unmap_rq);
984}
985
d783e0bd 986/* We read the CQE phase first to check if the rest of the entry is valid */
750dde44 987static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq)
d783e0bd 988{
74943d45
KB		 989 struct nvme_completion *hcqe = &nvmeq->cqes[nvmeq->cq_head];
990
991 return (le16_to_cpu(READ_ONCE(hcqe->status)) & 1) == nvmeq->cq_phase;
d783e0bd
MR		 992}
993
eb281c82 994static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
b60503ba 995{
eb281c82 996 u16 head = nvmeq->cq_head;
adf68f21 997
397c699f
KB		 998 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
999 nvmeq->dbbuf_cq_ei))
1000 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
eb281c82 1001}
aae239e1 1002
cfa27356
CH		 1003static inline struct blk_mq_tags *nvme_queue_tagset(struct nvme_queue *nvmeq)
1004{
1005 if (!nvmeq->qid)
1006 return nvmeq->dev->admin_tagset.tags[0];
1007 return nvmeq->dev->tagset.tags[nvmeq->qid - 1];
1008}
1009
c234a653
JA		 1010static inline void nvme_handle_cqe(struct nvme_queue *nvmeq,
1011 struct io_comp_batch *iob, u16 idx)
83a12fb7 1012{
74943d45 1013 struct nvme_completion *cqe = &nvmeq->cqes[idx];
62df8016 1014 __u16 command_id = READ_ONCE(cqe->command_id);
83a12fb7 1015 struct request *req;
adf68f21 1016
83a12fb7
SG		 1017 /*
1018 * AEN requests are special as they don't time out and can
1019 * survive any kind of queue freeze and often don't respond to
1020 * aborts. We don't even bother to allocate a struct request
1021 * for them but rather special case them here.
1022 */
62df8016 1023 if (unlikely(nvme_is_aen_req(nvmeq->qid, command_id))) {
83a12fb7
SG		 1024 nvme_complete_async_event(&nvmeq->dev->ctrl,
1025 cqe->status, &cqe->result);
a0fa9647 1026 return;
83a12fb7 1027 }
b60503ba 1028
e7006de6 1029 req = nvme_find_rq(nvme_queue_tagset(nvmeq), command_id);
50b7c243
XT		 1030 if (unlikely(!req)) {
1031 dev_warn(nvmeq->dev->ctrl.device,
1032 "invalid id %d completed on queue %d\n",
62df8016 1033 command_id, le16_to_cpu(cqe->sq_id));
50b7c243
XT		 1034 return;
1035 }
1036
604c01d5 1037 trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail);
c234a653
JA		 1038 if (!nvme_try_complete_req(req, cqe->status, cqe->result) &&
1039 !blk_mq_add_to_batch(req, iob, nvme_req(req)->status,
1040 nvme_pci_complete_batch))
ff029451 1041 nvme_pci_complete_rq(req);
83a12fb7 1042}
b60503ba 1043
5cb525c8
JA		 1044static inline void nvme_update_cq_head(struct nvme_queue *nvmeq)
1045{
a0aac973 1046 u32 tmp = nvmeq->cq_head + 1;
a8de6639
AD		 1047
1048 if (tmp == nvmeq->q_depth) {
5cb525c8 1049 nvmeq->cq_head = 0;
e2a366a4 1050 nvmeq->cq_phase ^= 1;
a8de6639
AD		 1051 } else {
1052 nvmeq->cq_head = tmp;
b60503ba 1053 }
a0fa9647
JA		 1054}
1055
c234a653
JA		 1056static inline int nvme_poll_cq(struct nvme_queue *nvmeq,
1057 struct io_comp_batch *iob)
a0fa9647 1058{
1052b8ac 1059 int found = 0;
b60503ba 1060
1052b8ac 1061 while (nvme_cqe_pending(nvmeq)) {
bf392a5d 1062 found++;
b69e2ef2
KB		 1063 /*
1064 * load-load control dependency between phase and the rest of
1065 * the cqe requires a full read memory barrier
1066 */
1067 dma_rmb();
c234a653 1068 nvme_handle_cqe(nvmeq, iob, nvmeq->cq_head);
5cb525c8 1069 nvme_update_cq_head(nvmeq);
920d13a8 1070 }
eb281c82 1071
324b494c 1072 if (found)
920d13a8 1073 nvme_ring_cq_doorbell(nvmeq);
5cb525c8 1074 return found;
b60503ba
MW		 1075}
1076
1077static irqreturn_t nvme_irq(int irq, void *data)
58ffacb5 1078{
58ffacb5 1079 struct nvme_queue *nvmeq = data;
4f502245 1080 DEFINE_IO_COMP_BATCH(iob);
5cb525c8 1081
4f502245
JA		 1082 if (nvme_poll_cq(nvmeq, &iob)) {
1083 if (!rq_list_empty(iob.req_list))
1084 nvme_pci_complete_batch(&iob);
05fae499 1085 return IRQ_HANDLED;
4f502245 1086 }
05fae499 1087 return IRQ_NONE;
58ffacb5
MW		 1088}
1089
1090static irqreturn_t nvme_irq_check(int irq, void *data)
1091{
1092 struct nvme_queue *nvmeq = data;
4e523547 1093
750dde44 1094 if (nvme_cqe_pending(nvmeq))
d783e0bd
MR		 1095 return IRQ_WAKE_THREAD;
1096 return IRQ_NONE;
58ffacb5
MW		 1097}
1098
0b2a8a9f 1099/*
fa059b85 1100 * Poll for completions for any interrupt driven queue
0b2a8a9f
CH		 1101 * Can be called from any context.
1102 */
fa059b85 1103static void nvme_poll_irqdisable(struct nvme_queue *nvmeq)
a0fa9647 1104{
3a7afd8e 1105 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
a0fa9647 1106
fa059b85 1107 WARN_ON_ONCE(test_bit(NVMEQ_POLLED, &nvmeq->flags));
442e19b7 1108
fa059b85 1109 disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
c234a653 1110 nvme_poll_cq(nvmeq, NULL);
fa059b85 1111 enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
a0fa9647
JA		 1112}
1113
5a72e899 1114static int nvme_poll(struct blk_mq_hw_ctx *hctx, struct io_comp_batch *iob)
dabcefab
JA		 1115{
1116 struct nvme_queue *nvmeq = hctx->driver_data;
dabcefab
JA		 1117 bool found;
1118
1119 if (!nvme_cqe_pending(nvmeq))
1120 return 0;
1121
3a7afd8e 1122 spin_lock(&nvmeq->cq_poll_lock);
c234a653 1123 found = nvme_poll_cq(nvmeq, iob);
3a7afd8e 1124 spin_unlock(&nvmeq->cq_poll_lock);
dabcefab 1125
dabcefab
JA		 1126 return found;
1127}
1128
ad22c355 1129static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
b60503ba 1130{
f866fc42 1131 struct nvme_dev *dev = to_nvme_dev(ctrl);
147b27e4 1132 struct nvme_queue *nvmeq = &dev->queues[0];
f66e2804 1133 struct nvme_command c = { };
b60503ba 1134
a4aea562 1135 c.common.opcode = nvme_admin_async_event;
ad22c355 1136 c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
3233b94c
JA		 1137
1138 spin_lock(&nvmeq->sq_lock);
1139 nvme_sq_copy_cmd(nvmeq, &c);
1140 nvme_write_sq_db(nvmeq, true);
1141 spin_unlock(&nvmeq->sq_lock);
f705f837
CH		 1142}
1143
b60503ba 1144static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
f705f837 1145{
f66e2804 1146 struct nvme_command c = { };
b60503ba 1147
b60503ba
MW		 1148 c.delete_queue.opcode = opcode;
1149 c.delete_queue.qid = cpu_to_le16(id);
1150
1c63dc66 1151 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1152}
1153
b60503ba 1154static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
a8e3e0bb 1155 struct nvme_queue *nvmeq, s16 vector)
b60503ba 1156{
f66e2804 1157 struct nvme_command c = { };
4b04cc6a
JA		 1158 int flags = NVME_QUEUE_PHYS_CONTIG;
1159
7c349dde 1160 if (!test_bit(NVMEQ_POLLED, &nvmeq->flags))
4b04cc6a 1161 flags |= NVME_CQ_IRQ_ENABLED;
b60503ba 1162
d29ec824 1163 /*
16772ae6 1164 * Note: we (ab)use the fact that the prp fields survive if no data
d29ec824
CH		 1165 * is attached to the request.
1166 */
b60503ba
MW		 1167 c.create_cq.opcode = nvme_admin_create_cq;
1168 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1169 c.create_cq.cqid = cpu_to_le16(qid);
1170 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1171 c.create_cq.cq_flags = cpu_to_le16(flags);
7c349dde 1172 c.create_cq.irq_vector = cpu_to_le16(vector);
b60503ba 1173
1c63dc66 1174 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1175}
1176
1177static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1178 struct nvme_queue *nvmeq)
1179{
9abd68ef 1180 struct nvme_ctrl *ctrl = &dev->ctrl;
f66e2804 1181 struct nvme_command c = { };
81c1cd98 1182 int flags = NVME_QUEUE_PHYS_CONTIG;
b60503ba 1183
9abd68ef
JA		 1184 /*
1185 * Some drives have a bug that auto-enables WRRU if MEDIUM isn't
1186 * set. Since URGENT priority is zeroes, it makes all queues
1187 * URGENT.
1188 */
1189 if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ)
1190 flags |= NVME_SQ_PRIO_MEDIUM;
1191
d29ec824 1192 /*
16772ae6 1193 * Note: we (ab)use the fact that the prp fields survive if no data
d29ec824
CH		 1194 * is attached to the request.
1195 */
b60503ba
MW		 1196 c.create_sq.opcode = nvme_admin_create_sq;
1197 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1198 c.create_sq.sqid = cpu_to_le16(qid);
1199 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1200 c.create_sq.sq_flags = cpu_to_le16(flags);
1201 c.create_sq.cqid = cpu_to_le16(qid);
1202
1c63dc66 1203 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1204}
1205
1206static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1207{
1208 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1209}
1210
1211static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1212{
1213 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1214}
1215
2a842aca 1216static void abort_endio(struct request *req, blk_status_t error)
bc5fc7e4 1217{
f4800d6d
CH		 1218 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1219 struct nvme_queue *nvmeq = iod->nvmeq;
e44ac588 1220
27fa9bc5
CH		 1221 dev_warn(nvmeq->dev->ctrl.device,
1222 "Abort status: 0x%x", nvme_req(req)->status);
e7a2a87d 1223 atomic_inc(&nvmeq->dev->ctrl.abort_limit);
e7a2a87d 1224 blk_mq_free_request(req);
bc5fc7e4
MW		 1225}
1226
b2a0eb1a
KB		 1227static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1228{
b2a0eb1a
KB		 1229 /* If true, indicates loss of adapter communication, possibly by a
1230 * NVMe Subsystem reset.
1231 */
1232 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1233
ad70062c
JW		 1234 /* If there is a reset/reinit ongoing, we shouldn't reset again. */
1235 switch (dev->ctrl.state) {
1236 case NVME_CTRL_RESETTING:
ad6a0a52 1237 case NVME_CTRL_CONNECTING:
b2a0eb1a 1238 return false;
ad70062c
JW		 1239 default:
1240 break;
1241 }
b2a0eb1a
KB		 1242
1243 /* We shouldn't reset unless the controller is on fatal error state
1244 * _or_ if we lost the communication with it.
1245 */
1246 if (!(csts & NVME_CSTS_CFS) && !nssro)
1247 return false;
1248
b2a0eb1a
KB		 1249 return true;
1250}
1251
1252static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1253{
1254 /* Read a config register to help see what died. */
1255 u16 pci_status;
1256 int result;
1257
1258 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1259 &pci_status);
1260 if (result == PCIBIOS_SUCCESSFUL)
1261 dev_warn(dev->ctrl.device,
1262 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1263 csts, pci_status);
1264 else
1265 dev_warn(dev->ctrl.device,
1266 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1267 csts, result);
1268}
1269
31c7c7d2 1270static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
c30341dc 1271{
f4800d6d
CH		 1272 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1273 struct nvme_queue *nvmeq = iod->nvmeq;
c30341dc 1274 struct nvme_dev *dev = nvmeq->dev;
a4aea562 1275 struct request *abort_req;
f66e2804 1276 struct nvme_command cmd = { };
b2a0eb1a
KB		 1277 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1278
651438bb
WX		 1279 /* If PCI error recovery process is happening, we cannot reset or
1280 * the recovery mechanism will surely fail.
1281 */
1282 mb();
1283 if (pci_channel_offline(to_pci_dev(dev->dev)))
1284 return BLK_EH_RESET_TIMER;
1285
b2a0eb1a
KB		 1286 /*
1287 * Reset immediately if the controller is failed
1288 */
1289 if (nvme_should_reset(dev, csts)) {
1290 nvme_warn_reset(dev, csts);
1291 nvme_dev_disable(dev, false);
d86c4d8e 1292 nvme_reset_ctrl(&dev->ctrl);
db8c48e4 1293 return BLK_EH_DONE;
b2a0eb1a 1294 }
c30341dc 1295
7776db1c
KB		 1296 /*
1297 * Did we miss an interrupt?
1298 */
fa059b85 1299 if (test_bit(NVMEQ_POLLED, &nvmeq->flags))
5a72e899 1300 nvme_poll(req->mq_hctx, NULL);
fa059b85
KB		 1301 else
1302 nvme_poll_irqdisable(nvmeq);
1303
bf392a5d 1304 if (blk_mq_request_completed(req)) {
7776db1c
KB		 1305 dev_warn(dev->ctrl.device,
1306 "I/O %d QID %d timeout, completion polled\n",
1307 req->tag, nvmeq->qid);
db8c48e4 1308 return BLK_EH_DONE;
7776db1c
KB		 1309 }
1310
31c7c7d2 1311 /*
fd634f41
CH		 1312 * Shutdown immediately if controller times out while starting. The
1313 * reset work will see the pci device disabled when it gets the forced
1314 * cancellation error. All outstanding requests are completed on
db8c48e4 1315 * shutdown, so we return BLK_EH_DONE.
fd634f41 1316 */
4244140d
KB		 1317 switch (dev->ctrl.state) {
1318 case NVME_CTRL_CONNECTING:
2036f726 1319 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
df561f66 1320 fallthrough;
2036f726 1321 case NVME_CTRL_DELETING:
b9cac43c 1322 dev_warn_ratelimited(dev->ctrl.device,
fd634f41
CH		 1323 "I/O %d QID %d timeout, disable controller\n",
1324 req->tag, nvmeq->qid);
27fa9bc5 1325 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
7ad92f65 1326 nvme_dev_disable(dev, true);
db8c48e4 1327 return BLK_EH_DONE;
39a9dd81
KB		 1328 case NVME_CTRL_RESETTING:
1329 return BLK_EH_RESET_TIMER;
4244140d
KB		 1330 default:
1331 break;
c30341dc
KB		 1332 }
1333
fd634f41 1334 /*
ee0d96d3
BW		 1335 * Shutdown the controller immediately and schedule a reset if the
1336 * command was already aborted once before and still hasn't been
1337 * returned to the driver, or if this is the admin queue.
31c7c7d2 1338 */
f4800d6d 1339 if (!nvmeq->qid || iod->aborted) {
1b3c47c1 1340 dev_warn(dev->ctrl.device,
e1569a16
KB		 1341 "I/O %d QID %d timeout, reset controller\n",
1342 req->tag, nvmeq->qid);
7ad92f65 1343 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
a5cdb68c 1344 nvme_dev_disable(dev, false);
d86c4d8e 1345 nvme_reset_ctrl(&dev->ctrl);
c30341dc 1346
db8c48e4 1347 return BLK_EH_DONE;
c30341dc 1348 }
c30341dc 1349
e7a2a87d 1350 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
6bf25d16 1351 atomic_inc(&dev->ctrl.abort_limit);
31c7c7d2 1352 return BLK_EH_RESET_TIMER;
6bf25d16 1353 }
7bf7d778 1354 iod->aborted = 1;
a4aea562 1355
c30341dc 1356 cmd.abort.opcode = nvme_admin_abort_cmd;
85f74acf 1357 cmd.abort.cid = nvme_cid(req);
c30341dc 1358 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
c30341dc 1359
1b3c47c1
SG		 1360 dev_warn(nvmeq->dev->ctrl.device,
1361 "I/O %d QID %d timeout, aborting\n",
1362 req->tag, nvmeq->qid);
e7a2a87d
CH		 1363
1364 abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
39dfe844 1365 BLK_MQ_REQ_NOWAIT);
e7a2a87d
CH		 1366 if (IS_ERR(abort_req)) {
1367 atomic_inc(&dev->ctrl.abort_limit);
1368 return BLK_EH_RESET_TIMER;
1369 }
1370
e7a2a87d 1371 abort_req->end_io_data = NULL;
b84ba30b 1372 blk_execute_rq_nowait(abort_req, false, abort_endio);
c30341dc 1373
31c7c7d2
CH		 1374 /*
1375 * The aborted req will be completed on receiving the abort req.
1376 * We enable the timer again. If hit twice, it'll cause a device reset,
1377 * as the device then is in a faulty state.
1378 */
1379 return BLK_EH_RESET_TIMER;
c30341dc
KB		 1380}
1381
a4aea562
MB		 1382static void nvme_free_queue(struct nvme_queue *nvmeq)
1383{
8a1d09a6 1384 dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq),
9e866774 1385 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
63223078
CH		 1386 if (!nvmeq->sq_cmds)
1387 return;
0f238ff5 1388
63223078 1389 if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) {
88a041f4 1390 pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev),
8a1d09a6 1391 nvmeq->sq_cmds, SQ_SIZE(nvmeq));
63223078 1392 } else {
8a1d09a6 1393 dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq),
63223078 1394 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
0f238ff5 1395 }
9e866774
MW		 1396}
1397
a1a5ef99 1398static void nvme_free_queues(struct nvme_dev *dev, int lowest)
22404274
KB		 1399{
1400 int i;
1401
d858e5f0 1402 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
d858e5f0 1403 dev->ctrl.queue_count--;
147b27e4 1404 nvme_free_queue(&dev->queues[i]);
121c7ad4 1405 }
22404274
KB		 1406}
1407
4d115420
KB		 1408/**
1409 * nvme_suspend_queue - put queue into suspended state
40581d1a 1410 * @nvmeq: queue to suspend
4d115420
KB		 1411 */
1412static int nvme_suspend_queue(struct nvme_queue *nvmeq)
b60503ba 1413{
4e224106 1414 if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags))
2b25d981 1415 return 1;
a09115b2 1416
4e224106 1417 /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */
d1f06f4a 1418 mb();
a09115b2 1419
4e224106 1420 nvmeq->dev->online_queues--;
1c63dc66 1421 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
6ca1d902 1422 nvme_stop_admin_queue(&nvmeq->dev->ctrl);
7c349dde
KB		 1423 if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags))
1424 pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq);
4d115420
KB		 1425 return 0;
1426}
b60503ba 1427
8fae268b
KB		 1428static void nvme_suspend_io_queues(struct nvme_dev *dev)
1429{
1430 int i;
1431
1432 for (i = dev->ctrl.queue_count - 1; i > 0; i--)
1433 nvme_suspend_queue(&dev->queues[i]);
1434}
1435
a5cdb68c 1436static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
4d115420 1437{
147b27e4 1438 struct nvme_queue *nvmeq = &dev->queues[0];
4d115420 1439
a5cdb68c
KB		 1440 if (shutdown)
1441 nvme_shutdown_ctrl(&dev->ctrl);
1442 else
b5b05048 1443 nvme_disable_ctrl(&dev->ctrl);
07836e65 1444
bf392a5d 1445 nvme_poll_irqdisable(nvmeq);
b60503ba
MW		 1446}
1447
fa46c6fb
KB		 1448/*
1449 * Called only on a device that has been disabled and after all other threads
9210c075
DZ		 1450 * that can check this device's completion queues have synced, except
1451 * nvme_poll(). This is the last chance for the driver to see a natural
1452 * completion before nvme_cancel_request() terminates all incomplete requests.
fa46c6fb
KB		 1453 */
1454static void nvme_reap_pending_cqes(struct nvme_dev *dev)
1455{
fa46c6fb
KB		 1456 int i;
1457
9210c075
DZ		 1458 for (i = dev->ctrl.queue_count - 1; i > 0; i--) {
1459 spin_lock(&dev->queues[i].cq_poll_lock);
c234a653 1460 nvme_poll_cq(&dev->queues[i], NULL);
9210c075
DZ		 1461 spin_unlock(&dev->queues[i].cq_poll_lock);
1462 }
fa46c6fb
KB		 1463}
1464
8ffaadf7
JD		 1465static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1466 int entry_size)
1467{
1468 int q_depth = dev->q_depth;
5fd4ce1b 1469 unsigned q_size_aligned = roundup(q_depth * entry_size,
6c3c05b0 1470 NVME_CTRL_PAGE_SIZE);
8ffaadf7
JD		 1471
1472 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
c45f5c99 1473 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
4e523547 1474
6c3c05b0 1475 mem_per_q = round_down(mem_per_q, NVME_CTRL_PAGE_SIZE);
c45f5c99 1476 q_depth = div_u64(mem_per_q, entry_size);
8ffaadf7
JD		 1477
1478 /*
1479 * Ensure the reduced q_depth is above some threshold where it
1480 * would be better to map queues in system memory with the
1481 * original depth
1482 */
1483 if (q_depth < 64)
1484 return -ENOMEM;
1485 }
1486
1487 return q_depth;
1488}
1489
1490static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
8a1d09a6 1491 int qid)
8ffaadf7 1492{
0f238ff5
LG		 1493 struct pci_dev *pdev = to_pci_dev(dev->dev);
1494
1495 if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
8a1d09a6 1496 nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq));
bfac8e9f
AM		 1497 if (nvmeq->sq_cmds) {
1498 nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev,
1499 nvmeq->sq_cmds);
1500 if (nvmeq->sq_dma_addr) {
1501 set_bit(NVMEQ_SQ_CMB, &nvmeq->flags);
1502 return 0;
1503 }
1504
8a1d09a6 1505 pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq));
63223078 1506 }
0f238ff5 1507 }
8ffaadf7 1508
8a1d09a6 1509 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq),
63223078 1510 &nvmeq->sq_dma_addr, GFP_KERNEL);
815c6704
KB		 1511 if (!nvmeq->sq_cmds)
1512 return -ENOMEM;
8ffaadf7
JD		 1513 return 0;
1514}
1515
a6ff7262 1516static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
b60503ba 1517{
147b27e4 1518 struct nvme_queue *nvmeq = &dev->queues[qid];
b60503ba 1519
62314e40
KB		 1520 if (dev->ctrl.queue_count > qid)
1521 return 0;
b60503ba 1522
c1e0cc7e 1523 nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES;
8a1d09a6
BH		 1524 nvmeq->q_depth = depth;
1525 nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq),
750afb08 1526 &nvmeq->cq_dma_addr, GFP_KERNEL);
b60503ba
MW		 1527 if (!nvmeq->cqes)
1528 goto free_nvmeq;
b60503ba 1529
8a1d09a6 1530 if (nvme_alloc_sq_cmds(dev, nvmeq, qid))
b60503ba
MW		 1531 goto free_cqdma;
1532
091b6092 1533 nvmeq->dev = dev;
1ab0cd69 1534 spin_lock_init(&nvmeq->sq_lock);
3a7afd8e 1535 spin_lock_init(&nvmeq->cq_poll_lock);
b60503ba 1536 nvmeq->cq_head = 0;
82123460 1537 nvmeq->cq_phase = 1;
b80d5ccc 1538 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
c30341dc 1539 nvmeq->qid = qid;
d858e5f0 1540 dev->ctrl.queue_count++;
36a7e993 1541
147b27e4 1542 return 0;
b60503ba
MW		 1543
1544 free_cqdma:
8a1d09a6
BH		 1545 dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes,
1546 nvmeq->cq_dma_addr);
b60503ba 1547 free_nvmeq:
147b27e4 1548 return -ENOMEM;
b60503ba
MW		 1549}
1550
dca51e78 1551static int queue_request_irq(struct nvme_queue *nvmeq)
3001082c 1552{
0ff199cb
CH		 1553 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1554 int nr = nvmeq->dev->ctrl.instance;
1555
1556 if (use_threaded_interrupts) {
1557 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1558 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1559 } else {
1560 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1561 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1562 }
3001082c
MW		 1563}
1564
22404274 1565static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
b60503ba 1566{
22404274 1567 struct nvme_dev *dev = nvmeq->dev;
b60503ba 1568
22404274 1569 nvmeq->sq_tail = 0;
38210800 1570 nvmeq->last_sq_tail = 0;
22404274
KB		 1571 nvmeq->cq_head = 0;
1572 nvmeq->cq_phase = 1;
b80d5ccc 1573 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
8a1d09a6 1574 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq));
f9f38e33 1575 nvme_dbbuf_init(dev, nvmeq, qid);
42f61420 1576 dev->online_queues++;
3a7afd8e 1577 wmb(); /* ensure the first interrupt sees the initialization */
22404274
KB		 1578}
1579
e4b9852a
CC		 1580/*
1581 * Try getting shutdown_lock while setting up IO queues.
1582 */
1583static int nvme_setup_io_queues_trylock(struct nvme_dev *dev)
1584{
1585 /*
1586 * Give up if the lock is being held by nvme_dev_disable.
1587 */
1588 if (!mutex_trylock(&dev->shutdown_lock))
1589 return -ENODEV;
1590
1591 /*
1592 * Controller is in wrong state, fail early.
1593 */
1594 if (dev->ctrl.state != NVME_CTRL_CONNECTING) {
1595 mutex_unlock(&dev->shutdown_lock);
1596 return -ENODEV;
1597 }
1598
1599 return 0;
1600}
1601
4b04cc6a 1602static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled)
22404274
KB		 1603{
1604 struct nvme_dev *dev = nvmeq->dev;
1605 int result;
7c349dde 1606 u16 vector = 0;
3f85d50b 1607
d1ed6aa1
CH		 1608 clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
1609
22b55601
KB		 1610 /*
1611 * A queue's vector matches the queue identifier unless the controller
1612 * has only one vector available.
1613 */
4b04cc6a
JA		 1614 if (!polled)
1615 vector = dev->num_vecs == 1 ? 0 : qid;
1616 else
7c349dde 1617 set_bit(NVMEQ_POLLED, &nvmeq->flags);
4b04cc6a 1618
a8e3e0bb 1619 result = adapter_alloc_cq(dev, qid, nvmeq, vector);
ded45505
KB		 1620 if (result)
1621 return result;
b60503ba
MW		 1622
1623 result = adapter_alloc_sq(dev, qid, nvmeq);
1624 if (result < 0)
ded45505 1625 return result;
c80b36cd 1626 if (result)
b60503ba
MW		 1627 goto release_cq;
1628
a8e3e0bb 1629 nvmeq->cq_vector = vector;
4b04cc6a 1630
e4b9852a
CC		 1631 result = nvme_setup_io_queues_trylock(dev);
1632 if (result)
1633 return result;
1634 nvme_init_queue(nvmeq, qid);
7c349dde 1635 if (!polled) {
4b04cc6a
JA		 1636 result = queue_request_irq(nvmeq);
1637 if (result < 0)
1638 goto release_sq;
1639 }
b60503ba 1640
4e224106 1641 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
e4b9852a 1642 mutex_unlock(&dev->shutdown_lock);
22404274 1643 return result;
b60503ba 1644
a8e3e0bb 1645release_sq:
f25a2dfc 1646 dev->online_queues--;
e4b9852a 1647 mutex_unlock(&dev->shutdown_lock);
b60503ba 1648 adapter_delete_sq(dev, qid);
a8e3e0bb 1649release_cq:
b60503ba 1650 adapter_delete_cq(dev, qid);
22404274 1651 return result;
b60503ba
MW		 1652}
1653
f363b089 1654static const struct blk_mq_ops nvme_mq_admin_ops = {
d29ec824 1655 .queue_rq = nvme_queue_rq,
77f02a7a 1656 .complete = nvme_pci_complete_rq,
a4aea562 1657 .init_hctx = nvme_admin_init_hctx,
0350815a 1658 .init_request = nvme_init_request,
a4aea562
MB		 1659 .timeout = nvme_timeout,
1660};
1661
f363b089 1662static const struct blk_mq_ops nvme_mq_ops = {
376f7ef8
CH		 1663 .queue_rq = nvme_queue_rq,
1664 .complete = nvme_pci_complete_rq,
1665 .commit_rqs = nvme_commit_rqs,
1666 .init_hctx = nvme_init_hctx,
1667 .init_request = nvme_init_request,
1668 .map_queues = nvme_pci_map_queues,
1669 .timeout = nvme_timeout,
1670 .poll = nvme_poll,
dabcefab
JA		 1671};
1672
ea191d2f
KB		 1673static void nvme_dev_remove_admin(struct nvme_dev *dev)
1674{
1c63dc66 1675 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
69d9a99c
KB		 1676 /*
1677 * If the controller was reset during removal, it's possible
1678 * user requests may be waiting on a stopped queue. Start the
1679 * queue to flush these to completion.
1680 */
6ca1d902 1681 nvme_start_admin_queue(&dev->ctrl);
1c63dc66 1682 blk_cleanup_queue(dev->ctrl.admin_q);
ea191d2f
KB		 1683 blk_mq_free_tag_set(&dev->admin_tagset);
1684 }
1685}
1686
a4aea562
MB		 1687static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1688{
1c63dc66 1689 if (!dev->ctrl.admin_q) {
a4aea562
MB		 1690 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1691 dev->admin_tagset.nr_hw_queues = 1;
e3e9d50c 1692
38dabe21 1693 dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH;
dc96f938 1694 dev->admin_tagset.timeout = NVME_ADMIN_TIMEOUT;
d4ec47f1 1695 dev->admin_tagset.numa_node = dev->ctrl.numa_node;
d43f1ccf 1696 dev->admin_tagset.cmd_size = sizeof(struct nvme_iod);
d3484991 1697 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED;
a4aea562
MB		 1698 dev->admin_tagset.driver_data = dev;
1699
1700 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1701 return -ENOMEM;
34b6c231 1702 dev->ctrl.admin_tagset = &dev->admin_tagset;
a4aea562 1703
1c63dc66
CH		 1704 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1705 if (IS_ERR(dev->ctrl.admin_q)) {
a4aea562
MB		 1706 blk_mq_free_tag_set(&dev->admin_tagset);
1707 return -ENOMEM;
1708 }
1c63dc66 1709 if (!blk_get_queue(dev->ctrl.admin_q)) {
ea191d2f 1710 nvme_dev_remove_admin(dev);
1c63dc66 1711 dev->ctrl.admin_q = NULL;
ea191d2f
KB		 1712 return -ENODEV;
1713 }
0fb59cbc 1714 } else
6ca1d902 1715 nvme_start_admin_queue(&dev->ctrl);
a4aea562
MB		 1716
1717 return 0;
1718}
1719
97f6ef64
XY		 1720static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1721{
1722 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1723}
1724
1725static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1726{
1727 struct pci_dev *pdev = to_pci_dev(dev->dev);
1728
1729 if (size <= dev->bar_mapped_size)
1730 return 0;
1731 if (size > pci_resource_len(pdev, 0))
1732 return -ENOMEM;
1733 if (dev->bar)
1734 iounmap(dev->bar);
1735 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1736 if (!dev->bar) {
1737 dev->bar_mapped_size = 0;
1738 return -ENOMEM;
1739 }
1740 dev->bar_mapped_size = size;
1741 dev->dbs = dev->bar + NVME_REG_DBS;
1742
1743 return 0;
1744}
1745
01ad0990 1746static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
b60503ba 1747{
ba47e386 1748 int result;
b60503ba
MW		 1749 u32 aqa;
1750 struct nvme_queue *nvmeq;
1751
97f6ef64
XY		 1752 result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1753 if (result < 0)
1754 return result;
1755
8ef2074d 1756 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
20d0dfe6 1757 NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
dfbac8c7 1758
7a67cbea
CH		 1759 if (dev->subsystem &&
1760 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1761 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
dfbac8c7 1762
b5b05048 1763 result = nvme_disable_ctrl(&dev->ctrl);
ba47e386
MW		 1764 if (result < 0)
1765 return result;
b60503ba 1766
a6ff7262 1767 result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
147b27e4
SG		 1768 if (result)
1769 return result;
b60503ba 1770
635333e4
MG		 1771 dev->ctrl.numa_node = dev_to_node(dev->dev);
1772
147b27e4 1773 nvmeq = &dev->queues[0];
b60503ba
MW		 1774 aqa = nvmeq->q_depth - 1;
1775 aqa |= aqa << 16;
1776
7a67cbea
CH		 1777 writel(aqa, dev->bar + NVME_REG_AQA);
1778 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1779 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
b60503ba 1780
c0f2f45b 1781 result = nvme_enable_ctrl(&dev->ctrl);
025c557a 1782 if (result)
d4875622 1783 return result;
a4aea562 1784
2b25d981 1785 nvmeq->cq_vector = 0;
161b8be2 1786 nvme_init_queue(nvmeq, 0);
dca51e78 1787 result = queue_request_irq(nvmeq);
758dd7fd 1788 if (result) {
7c349dde 1789 dev->online_queues--;
d4875622 1790 return result;
758dd7fd 1791 }
025c557a 1792
4e224106 1793 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
b60503ba
MW		 1794 return result;
1795}
1796
749941f2 1797static int nvme_create_io_queues(struct nvme_dev *dev)
42f61420 1798{
4b04cc6a 1799 unsigned i, max, rw_queues;
749941f2 1800 int ret = 0;
42f61420 1801
d858e5f0 1802 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
a6ff7262 1803 if (nvme_alloc_queue(dev, i, dev->q_depth)) {
749941f2 1804 ret = -ENOMEM;
42f61420 1805 break;
749941f2
CH		 1806 }
1807 }
42f61420 1808
d858e5f0 1809 max = min(dev->max_qid, dev->ctrl.queue_count - 1);
e20ba6e1
CH		 1810 if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) {
1811 rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] +
1812 dev->io_queues[HCTX_TYPE_READ];
4b04cc6a
JA		 1813 } else {
1814 rw_queues = max;
1815 }
1816
949928c1 1817 for (i = dev->online_queues; i <= max; i++) {
4b04cc6a
JA		 1818 bool polled = i > rw_queues;
1819
1820 ret = nvme_create_queue(&dev->queues[i], i, polled);
d4875622 1821 if (ret)
42f61420 1822 break;
27e8166c 1823 }
749941f2
CH		 1824
1825 /*
1826 * Ignore failing Create SQ/CQ commands, we can continue with less
8adb8c14
MI		 1827 * than the desired amount of queues, and even a controller without
1828 * I/O queues can still be used to issue admin commands. This might
749941f2
CH		 1829 * be useful to upgrade a buggy firmware for example.
1830 */
1831 return ret >= 0 ? 0 : ret;
b60503ba
MW		 1832}
1833
88de4598 1834static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
8ffaadf7 1835{
88de4598
CH		 1836 u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
1837
1838 return 1ULL << (12 + 4 * szu);
1839}
1840
1841static u32 nvme_cmb_size(struct nvme_dev *dev)
1842{
1843 return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
1844}
1845
f65efd6d 1846static void nvme_map_cmb(struct nvme_dev *dev)
8ffaadf7 1847{
88de4598 1848 u64 size, offset;
8ffaadf7
JD		 1849 resource_size_t bar_size;
1850 struct pci_dev *pdev = to_pci_dev(dev->dev);
8969f1f8 1851 int bar;
8ffaadf7 1852
9fe5c59f
KB		 1853 if (dev->cmb_size)
1854 return;
1855
20d3bb92
KJ		 1856 if (NVME_CAP_CMBS(dev->ctrl.cap))
1857 writel(NVME_CMBMSC_CRE, dev->bar + NVME_REG_CMBMSC);
1858
7a67cbea 1859 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
f65efd6d
CH		 1860 if (!dev->cmbsz)
1861 return;
202021c1 1862 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
8ffaadf7 1863
88de4598
CH		 1864 size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
1865 offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
8969f1f8
CH		 1866 bar = NVME_CMB_BIR(dev->cmbloc);
1867 bar_size = pci_resource_len(pdev, bar);
8ffaadf7
JD		 1868
1869 if (offset > bar_size)
f65efd6d 1870 return;
8ffaadf7 1871
20d3bb92
KJ		 1872 /*
1873 * Tell the controller about the host side address mapping the CMB,
1874 * and enable CMB decoding for the NVMe 1.4+ scheme:
1875 */
1876 if (NVME_CAP_CMBS(dev->ctrl.cap)) {
1877 hi_lo_writeq(NVME_CMBMSC_CRE | NVME_CMBMSC_CMSE |
1878 (pci_bus_address(pdev, bar) + offset),
1879 dev->bar + NVME_REG_CMBMSC);
1880 }
1881
8ffaadf7
JD		 1882 /*
1883 * Controllers may support a CMB size larger than their BAR,
1884 * for example, due to being behind a bridge. Reduce the CMB to
1885 * the reported size of the BAR
1886 */
1887 if (size > bar_size - offset)
1888 size = bar_size - offset;
1889
0f238ff5
LG		 1890 if (pci_p2pdma_add_resource(pdev, bar, size, offset)) {
1891 dev_warn(dev->ctrl.device,
1892 "failed to register the CMB\n");
f65efd6d 1893 return;
0f238ff5
LG		 1894 }
1895
8ffaadf7 1896 dev->cmb_size = size;
0f238ff5
LG		 1897 dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS);
1898
1899 if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) ==
1900 (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS))
1901 pci_p2pmem_publish(pdev, true);
8ffaadf7
JD		 1902}
1903
87ad72a5
CH		 1904static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1905{
6c3c05b0 1906 u32 host_mem_size = dev->host_mem_size >> NVME_CTRL_PAGE_SHIFT;
4033f35d 1907 u64 dma_addr = dev->host_mem_descs_dma;
f66e2804 1908 struct nvme_command c = { };
87ad72a5
CH		 1909 int ret;
1910
87ad72a5
CH		 1911 c.features.opcode = nvme_admin_set_features;
1912 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1913 c.features.dword11 = cpu_to_le32(bits);
6c3c05b0 1914 c.features.dword12 = cpu_to_le32(host_mem_size);
87ad72a5
CH		 1915 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr));
1916 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr));
1917 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs);
1918
1919 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1920 if (ret) {
1921 dev_warn(dev->ctrl.device,
1922 "failed to set host mem (err %d, flags %#x).\n",
1923 ret, bits);
a5df5e79
KB		 1924 } else
1925 dev->hmb = bits & NVME_HOST_MEM_ENABLE;
1926
87ad72a5
CH		 1927 return ret;
1928}
1929
1930static void nvme_free_host_mem(struct nvme_dev *dev)
1931{
1932 int i;
1933
1934 for (i = 0; i < dev->nr_host_mem_descs; i++) {
1935 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
6c3c05b0 1936 size_t size = le32_to_cpu(desc->size) * NVME_CTRL_PAGE_SIZE;
87ad72a5 1937
cc667f6d
LD		 1938 dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i],
1939 le64_to_cpu(desc->addr),
1940 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
87ad72a5
CH		 1941 }
1942
1943 kfree(dev->host_mem_desc_bufs);
1944 dev->host_mem_desc_bufs = NULL;
4033f35d
CH		 1945 dma_free_coherent(dev->dev,
1946 dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
1947 dev->host_mem_descs, dev->host_mem_descs_dma);
87ad72a5 1948 dev->host_mem_descs = NULL;
7e5dd57e 1949 dev->nr_host_mem_descs = 0;
87ad72a5
CH		 1950}
1951
92dc6895
CH		 1952static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
1953 u32 chunk_size)
9d713c2b 1954{
87ad72a5 1955 struct nvme_host_mem_buf_desc *descs;
92dc6895 1956 u32 max_entries, len;
4033f35d 1957 dma_addr_t descs_dma;
2ee0e4ed 1958 int i = 0;
87ad72a5 1959 void **bufs;
6fbcde66 1960 u64 size, tmp;
87ad72a5 1961
87ad72a5
CH		 1962 tmp = (preferred + chunk_size - 1);
1963 do_div(tmp, chunk_size);
1964 max_entries = tmp;
044a9df1
CH		 1965
1966 if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
1967 max_entries = dev->ctrl.hmmaxd;
1968
750afb08
LC		 1969 descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs),
1970 &descs_dma, GFP_KERNEL);
87ad72a5
CH		 1971 if (!descs)
1972 goto out;
1973
1974 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
1975 if (!bufs)
1976 goto out_free_descs;
1977
244a8fe4 1978 for (size = 0; size < preferred && i < max_entries; size += len) {
87ad72a5
CH		 1979 dma_addr_t dma_addr;
1980
50cdb7c6 1981 len = min_t(u64, chunk_size, preferred - size);
87ad72a5
CH		 1982 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
1983 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1984 if (!bufs[i])
1985 break;
1986
1987 descs[i].addr = cpu_to_le64(dma_addr);
6c3c05b0 1988 descs[i].size = cpu_to_le32(len / NVME_CTRL_PAGE_SIZE);
87ad72a5
CH		 1989 i++;
1990 }
1991
92dc6895 1992 if (!size)
87ad72a5 1993 goto out_free_bufs;
87ad72a5 1994
87ad72a5
CH		 1995 dev->nr_host_mem_descs = i;
1996 dev->host_mem_size = size;
1997 dev->host_mem_descs = descs;
4033f35d 1998 dev->host_mem_descs_dma = descs_dma;
87ad72a5
CH		 1999 dev->host_mem_desc_bufs = bufs;
2000 return 0;
2001
2002out_free_bufs:
2003 while (--i >= 0) {
6c3c05b0 2004 size_t size = le32_to_cpu(descs[i].size) * NVME_CTRL_PAGE_SIZE;
87ad72a5 2005
cc667f6d
LD		 2006 dma_free_attrs(dev->dev, size, bufs[i],
2007 le64_to_cpu(descs[i].addr),
2008 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
87ad72a5
CH		 2009 }
2010
2011 kfree(bufs);
2012out_free_descs:
4033f35d
CH		 2013 dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
2014 descs_dma);
87ad72a5 2015out:
87ad72a5
CH		 2016 dev->host_mem_descs = NULL;
2017 return -ENOMEM;
2018}
2019
92dc6895
CH		 2020static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
2021{
9dc54a0d
CK		 2022 u64 min_chunk = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
2023 u64 hmminds = max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
2024 u64 chunk_size;
92dc6895
CH		 2025
2026 /* start big and work our way down */
9dc54a0d 2027 for (chunk_size = min_chunk; chunk_size >= hmminds; chunk_size /= 2) {
92dc6895
CH		 2028 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
2029 if (!min || dev->host_mem_size >= min)
2030 return 0;
2031 nvme_free_host_mem(dev);
2032 }
2033 }
2034
2035 return -ENOMEM;
2036}
2037
9620cfba 2038static int nvme_setup_host_mem(struct nvme_dev *dev)
87ad72a5
CH		 2039{
2040 u64 max = (u64)max_host_mem_size_mb * SZ_1M;
2041 u64 preferred = (u64)dev->ctrl.hmpre * 4096;
2042 u64 min = (u64)dev->ctrl.hmmin * 4096;
2043 u32 enable_bits = NVME_HOST_MEM_ENABLE;
6fbcde66 2044 int ret;
87ad72a5
CH		 2045
2046 preferred = min(preferred, max);
2047 if (min > max) {
2048 dev_warn(dev->ctrl.device,
2049 "min host memory (%lld MiB) above limit (%d MiB).\n",
2050 min >> ilog2(SZ_1M), max_host_mem_size_mb);
2051 nvme_free_host_mem(dev);
9620cfba 2052 return 0;
87ad72a5
CH		 2053 }
2054
2055 /*
2056 * If we already have a buffer allocated check if we can reuse it.
2057 */
2058 if (dev->host_mem_descs) {
2059 if (dev->host_mem_size >= min)
2060 enable_bits |= NVME_HOST_MEM_RETURN;
2061 else
2062 nvme_free_host_mem(dev);
2063 }
2064
2065 if (!dev->host_mem_descs) {
92dc6895
CH		 2066 if (nvme_alloc_host_mem(dev, min, preferred)) {
2067 dev_warn(dev->ctrl.device,
2068 "failed to allocate host memory buffer.\n");
9620cfba 2069 return 0; /* controller must work without HMB */
92dc6895
CH		 2070 }
2071
2072 dev_info(dev->ctrl.device,
2073 "allocated %lld MiB host memory buffer.\n",
2074 dev->host_mem_size >> ilog2(SZ_1M));
87ad72a5
CH		 2075 }
2076
9620cfba
CH		 2077 ret = nvme_set_host_mem(dev, enable_bits);
2078 if (ret)
87ad72a5 2079 nvme_free_host_mem(dev);
9620cfba 2080 return ret;
9d713c2b
KB		 2081}
2082
0521905e
KB		 2083static ssize_t cmb_show(struct device *dev, struct device_attribute *attr,
2084 char *buf)
2085{
2086 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2087
2088 return sysfs_emit(buf, "cmbloc : x%08x\ncmbsz : x%08x\n",
2089 ndev->cmbloc, ndev->cmbsz);
2090}
2091static DEVICE_ATTR_RO(cmb);
2092
1751e97a
KB		 2093static ssize_t cmbloc_show(struct device *dev, struct device_attribute *attr,
2094 char *buf)
2095{
2096 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2097
2098 return sysfs_emit(buf, "%u\n", ndev->cmbloc);
2099}
2100static DEVICE_ATTR_RO(cmbloc);
2101
2102static ssize_t cmbsz_show(struct device *dev, struct device_attribute *attr,
2103 char *buf)
2104{
2105 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2106
2107 return sysfs_emit(buf, "%u\n", ndev->cmbsz);
2108}
2109static DEVICE_ATTR_RO(cmbsz);
2110
a5df5e79
KB		 2111static ssize_t hmb_show(struct device *dev, struct device_attribute *attr,
2112 char *buf)
2113{
2114 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2115
2116 return sysfs_emit(buf, "%d\n", ndev->hmb);
2117}
2118
2119static ssize_t hmb_store(struct device *dev, struct device_attribute *attr,
2120 const char *buf, size_t count)
2121{
2122 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2123 bool new;
2124 int ret;
2125
2126 if (strtobool(buf, &new) < 0)
2127 return -EINVAL;
2128
2129 if (new == ndev->hmb)
2130 return count;
2131
2132 if (new) {
2133 ret = nvme_setup_host_mem(ndev);
2134 } else {
2135 ret = nvme_set_host_mem(ndev, 0);
2136 if (!ret)
2137 nvme_free_host_mem(ndev);
2138 }
2139
2140 if (ret < 0)
2141 return ret;
2142
2143 return count;
2144}
2145static DEVICE_ATTR_RW(hmb);
2146
0521905e
KB		 2147static umode_t nvme_pci_attrs_are_visible(struct kobject *kobj,
2148 struct attribute *a, int n)
2149{
2150 struct nvme_ctrl *ctrl =
2151 dev_get_drvdata(container_of(kobj, struct device, kobj));
2152 struct nvme_dev *dev = to_nvme_dev(ctrl);
2153
1751e97a
KB		 2154 if (a == &dev_attr_cmb.attr ||
2155 a == &dev_attr_cmbloc.attr ||
2156 a == &dev_attr_cmbsz.attr) {
2157 if (!dev->cmbsz)
2158 return 0;
2159 }
a5df5e79
KB		 2160 if (a == &dev_attr_hmb.attr && !ctrl->hmpre)
2161 return 0;
2162
0521905e
KB		 2163 return a->mode;
2164}
2165
2166static struct attribute *nvme_pci_attrs[] = {
2167 &dev_attr_cmb.attr,
1751e97a
KB		 2168 &dev_attr_cmbloc.attr,
2169 &dev_attr_cmbsz.attr,
a5df5e79 2170 &dev_attr_hmb.attr,
0521905e
KB		 2171 NULL,
2172};
2173
2174static const struct attribute_group nvme_pci_attr_group = {
2175 .attrs = nvme_pci_attrs,
2176 .is_visible = nvme_pci_attrs_are_visible,
2177};
2178
612b7286
ML		 2179/*
2180 * nirqs is the number of interrupts available for write and read
2181 * queues. The core already reserved an interrupt for the admin queue.
2182 */
2183static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs)
3b6592f7 2184{
612b7286 2185 struct nvme_dev *dev = affd->priv;
2a5bcfdd 2186 unsigned int nr_read_queues, nr_write_queues = dev->nr_write_queues;
3b6592f7
JA		 2187
2188 /*
ee0d96d3 2189 * If there is no interrupt available for queues, ensure that
612b7286
ML		 2190 * the default queue is set to 1. The affinity set size is
2191 * also set to one, but the irq core ignores it for this case.
2192 *
2193 * If only one interrupt is available or 'write_queue' == 0, combine
2194 * write and read queues.
2195 *
2196 * If 'write_queues' > 0, ensure it leaves room for at least one read
2197 * queue.
3b6592f7 2198 */
612b7286
ML		 2199 if (!nrirqs) {
2200 nrirqs = 1;
2201 nr_read_queues = 0;
2a5bcfdd 2202 } else if (nrirqs == 1 || !nr_write_queues) {
612b7286 2203 nr_read_queues = 0;
2a5bcfdd 2204 } else if (nr_write_queues >= nrirqs) {
612b7286 2205 nr_read_queues = 1;
3b6592f7 2206 } else {
2a5bcfdd 2207 nr_read_queues = nrirqs - nr_write_queues;
3b6592f7 2208 }
612b7286
ML		 2209
2210 dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2211 affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2212 dev->io_queues[HCTX_TYPE_READ] = nr_read_queues;
2213 affd->set_size[HCTX_TYPE_READ] = nr_read_queues;
2214 affd->nr_sets = nr_read_queues ? 2 : 1;
3b6592f7
JA		 2215}
2216
6451fe73 2217static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues)
3b6592f7
JA		 2218{
2219 struct pci_dev *pdev = to_pci_dev(dev->dev);
3b6592f7 2220 struct irq_affinity affd = {
9cfef55b 2221 .pre_vectors = 1,
612b7286
ML		 2222 .calc_sets = nvme_calc_irq_sets,
2223 .priv = dev,
3b6592f7 2224 };
21cc2f3f 2225 unsigned int irq_queues, poll_queues;
6451fe73
JA		 2226
2227 /*
21cc2f3f
JX		 2228 * Poll queues don't need interrupts, but we need at least one I/O queue
2229 * left over for non-polled I/O.
6451fe73 2230 */
21cc2f3f
JX		 2231 poll_queues = min(dev->nr_poll_queues, nr_io_queues - 1);
2232 dev->io_queues[HCTX_TYPE_POLL] = poll_queues;
3b6592f7 2233
21cc2f3f
JX		 2234 /*
2235 * Initialize for the single interrupt case, will be updated in
2236 * nvme_calc_irq_sets().
2237 */
612b7286
ML		 2238 dev->io_queues[HCTX_TYPE_DEFAULT] = 1;
2239 dev->io_queues[HCTX_TYPE_READ] = 0;
3b6592f7 2240
66341331 2241 /*
21cc2f3f
JX		 2242 * We need interrupts for the admin queue and each non-polled I/O queue,
2243 * but some Apple controllers require all queues to use the first
2244 * vector.
66341331 2245 */
21cc2f3f
JX		 2246 irq_queues = 1;
2247 if (!(dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR))
2248 irq_queues += (nr_io_queues - poll_queues);
612b7286
ML		 2249 return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues,
2250 PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd);
3b6592f7
JA		 2251}
2252
8fae268b
KB		 2253static void nvme_disable_io_queues(struct nvme_dev *dev)
2254{
2255 if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq))
2256 __nvme_disable_io_queues(dev, nvme_admin_delete_cq);
2257}
2258
2a5bcfdd
WZ		 2259static unsigned int nvme_max_io_queues(struct nvme_dev *dev)
2260{
e3aef095
NS		 2261 /*
2262 * If tags are shared with admin queue (Apple bug), then
2263 * make sure we only use one IO queue.
2264 */
2265 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2266 return 1;
2a5bcfdd
WZ		 2267 return num_possible_cpus() + dev->nr_write_queues + dev->nr_poll_queues;
2268}
2269
8d85fce7 2270static int nvme_setup_io_queues(struct nvme_dev *dev)
b60503ba 2271{
147b27e4 2272 struct nvme_queue *adminq = &dev->queues[0];
e75ec752 2273 struct pci_dev *pdev = to_pci_dev(dev->dev);
2a5bcfdd 2274 unsigned int nr_io_queues;
97f6ef64 2275 unsigned long size;
2a5bcfdd 2276 int result;
b60503ba 2277
2a5bcfdd
WZ		 2278 /*
2279 * Sample the module parameters once at reset time so that we have
2280 * stable values to work with.
2281 */
2282 dev->nr_write_queues = write_queues;
2283 dev->nr_poll_queues = poll_queues;
d38e9f04 2284
e3aef095 2285 nr_io_queues = dev->nr_allocated_queues - 1;
9a0be7ab
CH		 2286 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
2287 if (result < 0)
1b23484b 2288 return result;
9a0be7ab 2289
f5fa90dc 2290 if (nr_io_queues == 0)
a5229050 2291 return 0;
53dc180e 2292
e4b9852a
CC		 2293 /*
2294 * Free IRQ resources as soon as NVMEQ_ENABLED bit transitions
2295 * from set to unset. If there is a window to it is truely freed,
2296 * pci_free_irq_vectors() jumping into this window will crash.
2297 * And take lock to avoid racing with pci_free_irq_vectors() in
2298 * nvme_dev_disable() path.
2299 */
2300 result = nvme_setup_io_queues_trylock(dev);
2301 if (result)
2302 return result;
2303 if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags))
2304 pci_free_irq(pdev, 0, adminq);
b60503ba 2305
0f238ff5 2306 if (dev->cmb_use_sqes) {
8ffaadf7
JD		 2307 result = nvme_cmb_qdepth(dev, nr_io_queues,
2308 sizeof(struct nvme_command));
2309 if (result > 0)
2310 dev->q_depth = result;
2311 else
0f238ff5 2312 dev->cmb_use_sqes = false;
8ffaadf7
JD		 2313 }
2314
97f6ef64
XY		 2315 do {
2316 size = db_bar_size(dev, nr_io_queues);
2317 result = nvme_remap_bar(dev, size);
2318 if (!result)
2319 break;
e4b9852a
CC		 2320 if (!--nr_io_queues) {
2321 result = -ENOMEM;
2322 goto out_unlock;
2323 }
97f6ef64
XY		 2324 } while (1);
2325 adminq->q_db = dev->dbs;
f1938f6e 2326
8fae268b 2327 retry:
9d713c2b 2328 /* Deregister the admin queue's interrupt */
e4b9852a
CC		 2329 if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags))
2330 pci_free_irq(pdev, 0, adminq);
9d713c2b 2331
e32efbfc
JA		 2332 /*
2333 * If we enable msix early due to not intx, disable it again before
2334 * setting up the full range we need.
2335 */
dca51e78 2336 pci_free_irq_vectors(pdev);
3b6592f7
JA		 2337
2338 result = nvme_setup_irqs(dev, nr_io_queues);
e4b9852a
CC		 2339 if (result <= 0) {
2340 result = -EIO;
2341 goto out_unlock;
2342 }
3b6592f7 2343
22b55601 2344 dev->num_vecs = result;
4b04cc6a 2345 result = max(result - 1, 1);
e20ba6e1 2346 dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL];
fa08a396 2347
063a8096
MW		 2348 /*
2349 * Should investigate if there's a performance win from allocating
2350 * more queues than interrupt vectors; it might allow the submission
2351 * path to scale better, even if the receive path is limited by the
2352 * number of interrupts.
2353 */
dca51e78 2354 result = queue_request_irq(adminq);
7c349dde 2355 if (result)
e4b9852a 2356 goto out_unlock;
4e224106 2357 set_bit(NVMEQ_ENABLED, &adminq->flags);
e4b9852a 2358 mutex_unlock(&dev->shutdown_lock);
8fae268b
KB		 2359
2360 result = nvme_create_io_queues(dev);
2361 if (result || dev->online_queues < 2)
2362 return result;
2363
2364 if (dev->online_queues - 1 < dev->max_qid) {
2365 nr_io_queues = dev->online_queues - 1;
2366 nvme_disable_io_queues(dev);
e4b9852a
CC		 2367 result = nvme_setup_io_queues_trylock(dev);
2368 if (result)
2369 return result;
8fae268b
KB		 2370 nvme_suspend_io_queues(dev);
2371 goto retry;
2372 }
2373 dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n",
2374 dev->io_queues[HCTX_TYPE_DEFAULT],
2375 dev->io_queues[HCTX_TYPE_READ],
2376 dev->io_queues[HCTX_TYPE_POLL]);
2377 return 0;
e4b9852a
CC		 2378out_unlock:
2379 mutex_unlock(&dev->shutdown_lock);
2380 return result;
b60503ba
MW		 2381}
2382
2a842aca 2383static void nvme_del_queue_end(struct request *req, blk_status_t error)
a5768aa8 2384{
db3cbfff 2385 struct nvme_queue *nvmeq = req->end_io_data;
b5875222 2386
db3cbfff 2387 blk_mq_free_request(req);
d1ed6aa1 2388 complete(&nvmeq->delete_done);
a5768aa8
KB		 2389}
2390
2a842aca 2391static void nvme_del_cq_end(struct request *req, blk_status_t error)
a5768aa8 2392{
db3cbfff 2393 struct nvme_queue *nvmeq = req->end_io_data;
a5768aa8 2394
d1ed6aa1
CH		 2395 if (error)
2396 set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
db3cbfff
KB		 2397
2398 nvme_del_queue_end(req, error);
a5768aa8
KB		 2399}
2400
db3cbfff 2401static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
bda4e0fb 2402{
db3cbfff
KB		 2403 struct request_queue *q = nvmeq->dev->ctrl.admin_q;
2404 struct request *req;
f66e2804 2405 struct nvme_command cmd = { };
bda4e0fb 2406
db3cbfff
KB		 2407 cmd.delete_queue.opcode = opcode;
2408 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
bda4e0fb 2409
39dfe844 2410 req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT);
db3cbfff
KB		 2411 if (IS_ERR(req))
2412 return PTR_ERR(req);
bda4e0fb 2413
db3cbfff
KB		 2414 req->end_io_data = nvmeq;
2415
d1ed6aa1 2416 init_completion(&nvmeq->delete_done);
b84ba30b
CH		 2417 blk_execute_rq_nowait(req, false, opcode == nvme_admin_delete_cq ?
2418 nvme_del_cq_end : nvme_del_queue_end);
db3cbfff 2419 return 0;
bda4e0fb
KB		 2420}
2421
8fae268b 2422static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode)
a5768aa8 2423{
5271edd4 2424 int nr_queues = dev->online_queues - 1, sent = 0;
db3cbfff 2425 unsigned long timeout;
a5768aa8 2426
db3cbfff 2427 retry:
dc96f938 2428 timeout = NVME_ADMIN_TIMEOUT;
5271edd4
CH		 2429 while (nr_queues > 0) {
2430 if (nvme_delete_queue(&dev->queues[nr_queues], opcode))
2431 break;
2432 nr_queues--;
2433 sent++;
db3cbfff 2434 }
d1ed6aa1
CH		 2435 while (sent) {
2436 struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent];
2437
2438 timeout = wait_for_completion_io_timeout(&nvmeq->delete_done,
5271edd4
CH		 2439 timeout);
2440 if (timeout == 0)
2441 return false;
d1ed6aa1 2442
d1ed6aa1 2443 sent--;
5271edd4
CH		 2444 if (nr_queues)
2445 goto retry;
2446 }
2447 return true;
a5768aa8
KB		 2448}
2449
5d02a5c1 2450static void nvme_dev_add(struct nvme_dev *dev)
b60503ba 2451{
2b1b7e78
JW		 2452 int ret;
2453
5bae7f73 2454 if (!dev->ctrl.tagset) {
376f7ef8 2455 dev->tagset.ops = &nvme_mq_ops;
ffe7704d 2456 dev->tagset.nr_hw_queues = dev->online_queues - 1;
8fe34be1 2457 dev->tagset.nr_maps = 2; /* default + read */
ed92ad37
CH		 2458 if (dev->io_queues[HCTX_TYPE_POLL])
2459 dev->tagset.nr_maps++;
ffe7704d 2460 dev->tagset.timeout = NVME_IO_TIMEOUT;
d4ec47f1 2461 dev->tagset.numa_node = dev->ctrl.numa_node;
61f3b896
CK		 2462 dev->tagset.queue_depth = min_t(unsigned int, dev->q_depth,
2463 BLK_MQ_MAX_DEPTH) - 1;
d43f1ccf 2464 dev->tagset.cmd_size = sizeof(struct nvme_iod);
ffe7704d
KB		 2465 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2466 dev->tagset.driver_data = dev;
b60503ba 2467
d38e9f04
BH		 2468 /*
2469 * Some Apple controllers requires tags to be unique
2470 * across admin and IO queue, so reserve the first 32
2471 * tags of the IO queue.
2472 */
2473 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2474 dev->tagset.reserved_tags = NVME_AQ_DEPTH;
2475
2b1b7e78
JW		 2476 ret = blk_mq_alloc_tag_set(&dev->tagset);
2477 if (ret) {
2478 dev_warn(dev->ctrl.device,
2479 "IO queues tagset allocation failed %d\n", ret);
5d02a5c1 2480 return;
2b1b7e78 2481 }
5bae7f73 2482 dev->ctrl.tagset = &dev->tagset;
949928c1
KB		 2483 } else {
2484 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2485
2486 /* Free previously allocated queues that are no longer usable */
2487 nvme_free_queues(dev, dev->online_queues);
ffe7704d 2488 }
949928c1 2489
e8fd41bb 2490 nvme_dbbuf_set(dev);
b60503ba
MW		 2491}
2492
b00a726a 2493static int nvme_pci_enable(struct nvme_dev *dev)
0877cb0d 2494{
b00a726a 2495 int result = -ENOMEM;
e75ec752 2496 struct pci_dev *pdev = to_pci_dev(dev->dev);
4bdf2603 2497 int dma_address_bits = 64;
0877cb0d
KB		 2498
2499 if (pci_enable_device_mem(pdev))
2500 return result;
2501
0877cb0d 2502 pci_set_master(pdev);
0877cb0d 2503
4bdf2603
FS		 2504 if (dev->ctrl.quirks & NVME_QUIRK_DMA_ADDRESS_BITS_48)
2505 dma_address_bits = 48;
2506 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(dma_address_bits)))
052d0efa 2507 goto disable;
0877cb0d 2508
7a67cbea 2509 if (readl(dev->bar + NVME_REG_CSTS) == -1) {
0e53d180 2510 result = -ENODEV;
b00a726a 2511 goto disable;
0e53d180 2512 }
e32efbfc
JA		 2513
2514 /*
a5229050
KB		 2515 * Some devices and/or platforms don't advertise or work with INTx
2516 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2517 * adjust this later.
e32efbfc 2518 */
dca51e78
CH		 2519 result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
2520 if (result < 0)
2521 return result;
e32efbfc 2522
20d0dfe6 2523 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
7a67cbea 2524
7442ddce 2525 dev->q_depth = min_t(u32, NVME_CAP_MQES(dev->ctrl.cap) + 1,
b27c1e68 2526 io_queue_depth);
aa22c8e6 2527 dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */
20d0dfe6 2528 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
7a67cbea 2529 dev->dbs = dev->bar + 4096;
1f390c1f 2530
66341331
BH		 2531 /*
2532 * Some Apple controllers require a non-standard SQE size.
2533 * Interestingly they also seem to ignore the CC:IOSQES register
2534 * so we don't bother updating it here.
2535 */
2536 if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES)
2537 dev->io_sqes = 7;
2538 else
2539 dev->io_sqes = NVME_NVM_IOSQES;
1f390c1f
SG		 2540
2541 /*
2542 * Temporary fix for the Apple controller found in the MacBook8,1 and
2543 * some MacBook7,1 to avoid controller resets and data loss.
2544 */
2545 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
2546 dev->q_depth = 2;
9bdcfb10
CH		 2547 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
2548 "set queue depth=%u to work around controller resets\n",
1f390c1f 2549 dev->q_depth);
d554b5e1
MP		 2550 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2551 (pdev->device == 0xa821 || pdev->device == 0xa822) &&
20d0dfe6 2552 NVME_CAP_MQES(dev->ctrl.cap) == 0) {
d554b5e1
MP		 2553 dev->q_depth = 64;
2554 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2555 "set queue depth=%u\n", dev->q_depth);
1f390c1f
SG		 2556 }
2557
d38e9f04
BH		 2558 /*
2559 * Controllers with the shared tags quirk need the IO queue to be
2560 * big enough so that we get 32 tags for the admin queue
2561 */
2562 if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) &&
2563 (dev->q_depth < (NVME_AQ_DEPTH + 2))) {
2564 dev->q_depth = NVME_AQ_DEPTH + 2;
2565 dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n",
2566 dev->q_depth);
2567 }
2568
2569
f65efd6d 2570 nvme_map_cmb(dev);
202021c1 2571
a0a3408e
KB		 2572 pci_enable_pcie_error_reporting(pdev);
2573 pci_save_state(pdev);
0877cb0d
KB		 2574 return 0;
2575
2576 disable:
0877cb0d
KB		 2577 pci_disable_device(pdev);
2578 return result;
2579}
2580
2581static void nvme_dev_unmap(struct nvme_dev *dev)
b00a726a
KB		 2582{
2583 if (dev->bar)
2584 iounmap(dev->bar);
a1f447b3 2585 pci_release_mem_regions(to_pci_dev(dev->dev));
b00a726a
KB		 2586}
2587
2588static void nvme_pci_disable(struct nvme_dev *dev)
0877cb0d 2589{
e75ec752
CH		 2590 struct pci_dev *pdev = to_pci_dev(dev->dev);
2591
dca51e78 2592 pci_free_irq_vectors(pdev);
0877cb0d 2593
a0a3408e
KB		 2594 if (pci_is_enabled(pdev)) {
2595 pci_disable_pcie_error_reporting(pdev);
e75ec752 2596 pci_disable_device(pdev);
4d115420 2597 }
4d115420
KB		 2598}
2599
a5cdb68c 2600static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
b60503ba 2601{
e43269e6 2602 bool dead = true, freeze = false;
302ad8cc 2603 struct pci_dev *pdev = to_pci_dev(dev->dev);
22404274 2604
77bf25ea 2605 mutex_lock(&dev->shutdown_lock);
302ad8cc
KB		 2606 if (pci_is_enabled(pdev)) {
2607 u32 csts = readl(dev->bar + NVME_REG_CSTS);
2608
ebef7368 2609 if (dev->ctrl.state == NVME_CTRL_LIVE ||
e43269e6
KB		 2610 dev->ctrl.state == NVME_CTRL_RESETTING) {
2611 freeze = true;
302ad8cc 2612 nvme_start_freeze(&dev->ctrl);
e43269e6 2613 }
302ad8cc
KB		 2614 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
2615 pdev->error_state != pci_channel_io_normal);
c9d3bf88 2616 }
c21377f8 2617
302ad8cc
KB		 2618 /*
2619 * Give the controller a chance to complete all entered requests if
2620 * doing a safe shutdown.
2621 */
e43269e6
KB		 2622 if (!dead && shutdown && freeze)
2623 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
9a915a5b
JW		 2624
2625 nvme_stop_queues(&dev->ctrl);
87ad72a5 2626
64ee0ac0 2627 if (!dead && dev->ctrl.queue_count > 0) {
8fae268b 2628 nvme_disable_io_queues(dev);
a5cdb68c 2629 nvme_disable_admin_queue(dev, shutdown);
4d115420 2630 }
8fae268b
KB		 2631 nvme_suspend_io_queues(dev);
2632 nvme_suspend_queue(&dev->queues[0]);
b00a726a 2633 nvme_pci_disable(dev);
fa46c6fb 2634 nvme_reap_pending_cqes(dev);
07836e65 2635
e1958e65
ML		 2636 blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
2637 blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
622b8b68
ML		 2638 blk_mq_tagset_wait_completed_request(&dev->tagset);
2639 blk_mq_tagset_wait_completed_request(&dev->admin_tagset);
302ad8cc
KB		 2640
2641 /*
2642 * The driver will not be starting up queues again if shutting down so
2643 * must flush all entered requests to their failed completion to avoid
2644 * deadlocking blk-mq hot-cpu notifier.
2645 */
c8e9e9b7 2646 if (shutdown) {
302ad8cc 2647 nvme_start_queues(&dev->ctrl);
c8e9e9b7 2648 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q))
6ca1d902 2649 nvme_start_admin_queue(&dev->ctrl);
c8e9e9b7 2650 }
77bf25ea 2651 mutex_unlock(&dev->shutdown_lock);
b60503ba
MW		 2652}
2653
c1ac9a4b
KB		 2654static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown)
2655{
2656 if (!nvme_wait_reset(&dev->ctrl))
2657 return -EBUSY;
2658 nvme_dev_disable(dev, shutdown);
2659 return 0;
2660}
2661
091b6092
MW		 2662static int nvme_setup_prp_pools(struct nvme_dev *dev)
2663{
e75ec752 2664 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
c61b82c7
CH		 2665 NVME_CTRL_PAGE_SIZE,
2666 NVME_CTRL_PAGE_SIZE, 0);
091b6092
MW		 2667 if (!dev->prp_page_pool)
2668 return -ENOMEM;
2669
99802a7a 2670 /* Optimisation for I/Os between 4k and 128k */
e75ec752 2671 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
99802a7a
MW		 2672 256, 256, 0);
2673 if (!dev->prp_small_pool) {
2674 dma_pool_destroy(dev->prp_page_pool);
2675 return -ENOMEM;
2676 }
091b6092
MW		 2677 return 0;
2678}
2679
2680static void nvme_release_prp_pools(struct nvme_dev *dev)
2681{
2682 dma_pool_destroy(dev->prp_page_pool);
99802a7a 2683 dma_pool_destroy(dev->prp_small_pool);
091b6092
MW		 2684}
2685
770597ec
KB		 2686static void nvme_free_tagset(struct nvme_dev *dev)
2687{
2688 if (dev->tagset.tags)
2689 blk_mq_free_tag_set(&dev->tagset);
2690 dev->ctrl.tagset = NULL;
2691}
2692
1673f1f0 2693static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
5e82e952 2694{
1673f1f0 2695 struct nvme_dev *dev = to_nvme_dev(ctrl);
9ac27090 2696
f9f38e33 2697 nvme_dbbuf_dma_free(dev);
770597ec 2698 nvme_free_tagset(dev);
1c63dc66
CH		 2699 if (dev->ctrl.admin_q)
2700 blk_put_queue(dev->ctrl.admin_q);
e286bcfc 2701 free_opal_dev(dev->ctrl.opal_dev);
943e942e 2702 mempool_destroy(dev->iod_mempool);
253fd4ac
IR		 2703 put_device(dev->dev);
2704 kfree(dev->queues);
5e82e952
KB		 2705 kfree(dev);
2706}
2707
7c1ce408 2708static void nvme_remove_dead_ctrl(struct nvme_dev *dev)
f58944e2 2709{
c1ac9a4b
KB		 2710 /*
2711 * Set state to deleting now to avoid blocking nvme_wait_reset(), which
2712 * may be holding this pci_dev's device lock.
2713 */
2714 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
d22524a4 2715 nvme_get_ctrl(&dev->ctrl);
69d9a99c 2716 nvme_dev_disable(dev, false);
9f9cafc1 2717 nvme_kill_queues(&dev->ctrl);
03e0f3a6 2718 if (!queue_work(nvme_wq, &dev->remove_work))
f58944e2
KB		 2719 nvme_put_ctrl(&dev->ctrl);
2720}
2721
fd634f41 2722static void nvme_reset_work(struct work_struct *work)
5e82e952 2723{
d86c4d8e
CH		 2724 struct nvme_dev *dev =
2725 container_of(work, struct nvme_dev, ctrl.reset_work);
a98e58e5 2726 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
e71afda4 2727 int result;
5e82e952 2728
7764656b
ZC		 2729 if (dev->ctrl.state != NVME_CTRL_RESETTING) {
2730 dev_warn(dev->ctrl.device, "ctrl state %d is not RESETTING\n",
2731 dev->ctrl.state);
e71afda4 2732 result = -ENODEV;
fd634f41 2733 goto out;
e71afda4 2734 }
5e82e952 2735
fd634f41
CH		 2736 /*
2737 * If we're called to reset a live controller first shut it down before
2738 * moving on.
2739 */
b00a726a 2740 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
a5cdb68c 2741 nvme_dev_disable(dev, false);
d6135c3a 2742 nvme_sync_queues(&dev->ctrl);
5e82e952 2743
5c959d73 2744 mutex_lock(&dev->shutdown_lock);
b00a726a 2745 result = nvme_pci_enable(dev);
f0b50732 2746 if (result)
4726bcf3 2747 goto out_unlock;
f0b50732 2748
01ad0990 2749 result = nvme_pci_configure_admin_queue(dev);
f0b50732 2750 if (result)
4726bcf3 2751 goto out_unlock;
f0b50732 2752
0fb59cbc
KB		 2753 result = nvme_alloc_admin_tags(dev);
2754 if (result)
4726bcf3 2755 goto out_unlock;
b9afca3e 2756
943e942e
JA		 2757 /*
2758 * Limit the max command size to prevent iod->sg allocations going
2759 * over a single page.
2760 */
7637de31
CH		 2761 dev->ctrl.max_hw_sectors = min_t(u32,
2762 NVME_MAX_KB_SZ << 1, dma_max_mapping_size(dev->dev) >> 9);
943e942e 2763 dev->ctrl.max_segments = NVME_MAX_SEGS;
a48bc520
CH		 2764
2765 /*
2766 * Don't limit the IOMMU merged segment size.
2767 */
2768 dma_set_max_seg_size(dev->dev, 0xffffffff);
3d2d861e 2769 dma_set_min_align_mask(dev->dev, NVME_CTRL_PAGE_SIZE - 1);
a48bc520 2770
5c959d73
KB		 2771 mutex_unlock(&dev->shutdown_lock);
2772
2773 /*
2774 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
2775 * initializing procedure here.
2776 */
2777 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
2778 dev_warn(dev->ctrl.device,
2779 "failed to mark controller CONNECTING\n");
cee6c269 2780 result = -EBUSY;
5c959d73
KB		 2781 goto out;
2782 }
943e942e 2783
95093350
MG		 2784 /*
2785 * We do not support an SGL for metadata (yet), so we are limited to a
2786 * single integrity segment for the separate metadata pointer.
2787 */
2788 dev->ctrl.max_integrity_segments = 1;
2789
f21c4769 2790 result = nvme_init_ctrl_finish(&dev->ctrl);
ce4541f4 2791 if (result)
f58944e2 2792 goto out;
ce4541f4 2793
e286bcfc
SB		 2794 if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
2795 if (!dev->ctrl.opal_dev)
2796 dev->ctrl.opal_dev =
2797 init_opal_dev(&dev->ctrl, &nvme_sec_submit);
2798 else if (was_suspend)
2799 opal_unlock_from_suspend(dev->ctrl.opal_dev);
2800 } else {
2801 free_opal_dev(dev->ctrl.opal_dev);
2802 dev->ctrl.opal_dev = NULL;
4f1244c8 2803 }
a98e58e5 2804
f9f38e33
HK		 2805 if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) {
2806 result = nvme_dbbuf_dma_alloc(dev);
2807 if (result)
2808 dev_warn(dev->dev,
2809 "unable to allocate dma for dbbuf\n");
2810 }
2811
9620cfba
CH		 2812 if (dev->ctrl.hmpre) {
2813 result = nvme_setup_host_mem(dev);
2814 if (result < 0)
2815 goto out;
2816 }
87ad72a5 2817
f0b50732 2818 result = nvme_setup_io_queues(dev);
badc34d4 2819 if (result)
f58944e2 2820 goto out;
f0b50732 2821
2659e57b
CH		 2822 /*
2823 * Keep the controller around but remove all namespaces if we don't have
2824 * any working I/O queue.
2825 */
3cf519b5 2826 if (dev->online_queues < 2) {
1b3c47c1 2827 dev_warn(dev->ctrl.device, "IO queues not created\n");
3b24774e 2828 nvme_kill_queues(&dev->ctrl);
5bae7f73 2829 nvme_remove_namespaces(&dev->ctrl);
770597ec 2830 nvme_free_tagset(dev);
3cf519b5 2831 } else {
25646264 2832 nvme_start_queues(&dev->ctrl);
302ad8cc 2833 nvme_wait_freeze(&dev->ctrl);
5d02a5c1 2834 nvme_dev_add(dev);
302ad8cc 2835 nvme_unfreeze(&dev->ctrl);
3cf519b5
CH		 2836 }
2837
2b1b7e78
JW		 2838 /*
2839 * If only admin queue live, keep it to do further investigation or
2840 * recovery.
2841 */
5d02a5c1 2842 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
2b1b7e78 2843 dev_warn(dev->ctrl.device,
5d02a5c1 2844 "failed to mark controller live state\n");
e71afda4 2845 result = -ENODEV;
bb8d261e
CH		 2846 goto out;
2847 }
92911a55 2848
0521905e
KB		 2849 if (!dev->attrs_added && !sysfs_create_group(&dev->ctrl.device->kobj,
2850 &nvme_pci_attr_group))
2851 dev->attrs_added = true;
2852
d09f2b45 2853 nvme_start_ctrl(&dev->ctrl);
3cf519b5 2854 return;
f0b50732 2855
4726bcf3
KB		 2856 out_unlock:
2857 mutex_unlock(&dev->shutdown_lock);
3cf519b5 2858 out:
7c1ce408
CK		 2859 if (result)
2860 dev_warn(dev->ctrl.device,
2861 "Removing after probe failure status: %d\n", result);
2862 nvme_remove_dead_ctrl(dev);
f0b50732
KB		 2863}
2864
5c8809e6 2865static void nvme_remove_dead_ctrl_work(struct work_struct *work)
9a6b9458 2866{
5c8809e6 2867 struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
e75ec752 2868 struct pci_dev *pdev = to_pci_dev(dev->dev);
9a6b9458
KB		 2869
2870 if (pci_get_drvdata(pdev))
921920ab 2871 device_release_driver(&pdev->dev);
1673f1f0 2872 nvme_put_ctrl(&dev->ctrl);
9a6b9458
KB		 2873}
2874
1c63dc66 2875static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
9ca97374 2876{
1c63dc66 2877 *val = readl(to_nvme_dev(ctrl)->bar + off);
90667892 2878 return 0;
9ca97374
TH		 2879}
2880
5fd4ce1b 2881static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
4cc06521 2882{
5fd4ce1b
CH		 2883 writel(val, to_nvme_dev(ctrl)->bar + off);
2884 return 0;
2885}
4cc06521 2886
7fd8930f
CH		 2887static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2888{
3a8ecc93 2889 *val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off);
7fd8930f 2890 return 0;
4cc06521
KB		 2891}
2892
97c12223
KB		 2893static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
2894{
2895 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2896
2db24e4a 2897 return snprintf(buf, size, "%s\n", dev_name(&pdev->dev));
97c12223
KB		 2898}
2899
1c63dc66 2900static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
1a353d85 2901 .name = "pcie",
e439bb12 2902 .module = THIS_MODULE,
e0596ab2
LG		 2903 .flags = NVME_F_METADATA_SUPPORTED |
2904 NVME_F_PCI_P2PDMA,
1c63dc66 2905 .reg_read32 = nvme_pci_reg_read32,
5fd4ce1b 2906 .reg_write32 = nvme_pci_reg_write32,
7fd8930f 2907 .reg_read64 = nvme_pci_reg_read64,
1673f1f0 2908 .free_ctrl = nvme_pci_free_ctrl,
f866fc42 2909 .submit_async_event = nvme_pci_submit_async_event,
97c12223 2910 .get_address = nvme_pci_get_address,
1c63dc66 2911};
4cc06521 2912
b00a726a
KB		 2913static int nvme_dev_map(struct nvme_dev *dev)
2914{
b00a726a
KB		 2915 struct pci_dev *pdev = to_pci_dev(dev->dev);
2916
a1f447b3 2917 if (pci_request_mem_regions(pdev, "nvme"))
b00a726a
KB		 2918 return -ENODEV;
2919
97f6ef64 2920 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
b00a726a
KB		 2921 goto release;
2922
9fa196e7 2923 return 0;
b00a726a 2924 release:
9fa196e7
MG		 2925 pci_release_mem_regions(pdev);
2926 return -ENODEV;
b00a726a
KB		 2927}
2928
8427bbc2 2929static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
ff5350a8
AL		 2930{
2931 if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
2932 /*
2933 * Several Samsung devices seem to drop off the PCIe bus
2934 * randomly when APST is on and uses the deepest sleep state.
2935 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2936 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2937 * 950 PRO 256GB", but it seems to be restricted to two Dell
2938 * laptops.
2939 */
2940 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
2941 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
2942 dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
2943 return NVME_QUIRK_NO_DEEPEST_PS;
8427bbc2
KHF		 2944 } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
2945 /*
2946 * Samsung SSD 960 EVO drops off the PCIe bus after system
467c77d4
JJ		 2947 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
2948 * within few minutes after bootup on a Coffee Lake board -
2949 * ASUS PRIME Z370-A
8427bbc2
KHF		 2950 */
2951 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
467c77d4
JJ		 2952 (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") ||
2953 dmi_match(DMI_BOARD_NAME, "PRIME Z370-A")))
8427bbc2 2954 return NVME_QUIRK_NO_APST;
1fae37ac
S		 2955 } else if ((pdev->vendor == 0x144d && (pdev->device == 0xa801 ||
2956 pdev->device == 0xa808 || pdev->device == 0xa809)) ||
2957 (pdev->vendor == 0x1e0f && pdev->device == 0x0001)) {
2958 /*
2959 * Forcing to use host managed nvme power settings for
2960 * lowest idle power with quick resume latency on
2961 * Samsung and Toshiba SSDs based on suspend behavior
2962 * on Coffee Lake board for LENOVO C640
2963 */
2964 if ((dmi_match(DMI_BOARD_VENDOR, "LENOVO")) &&
2965 dmi_match(DMI_BOARD_NAME, "LNVNB161216"))
2966 return NVME_QUIRK_SIMPLE_SUSPEND;
ff5350a8
AL		 2967 }
2968
2969 return 0;
2970}
2971
18119775
KB		 2972static void nvme_async_probe(void *data, async_cookie_t cookie)
2973{
2974 struct nvme_dev *dev = data;
80f513b5 2975
bd46a906 2976 flush_work(&dev->ctrl.reset_work);
18119775 2977 flush_work(&dev->ctrl.scan_work);
80f513b5 2978 nvme_put_ctrl(&dev->ctrl);
18119775
KB		 2979}
2980
8d85fce7 2981static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
b60503ba 2982{
a4aea562 2983 int node, result = -ENOMEM;
b60503ba 2984 struct nvme_dev *dev;
ff5350a8 2985 unsigned long quirks = id->driver_data;
943e942e 2986 size_t alloc_size;
b60503ba 2987
a4aea562
MB		 2988 node = dev_to_node(&pdev->dev);
2989 if (node == NUMA_NO_NODE)
2fa84351 2990 set_dev_node(&pdev->dev, first_memory_node);
a4aea562
MB		 2991
2992 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
b60503ba
MW		 2993 if (!dev)
2994 return -ENOMEM;
147b27e4 2995
2a5bcfdd
WZ		 2996 dev->nr_write_queues = write_queues;
2997 dev->nr_poll_queues = poll_queues;
2998 dev->nr_allocated_queues = nvme_max_io_queues(dev) + 1;
2999 dev->queues = kcalloc_node(dev->nr_allocated_queues,
3000 sizeof(struct nvme_queue), GFP_KERNEL, node);
b60503ba
MW		 3001 if (!dev->queues)
3002 goto free;
3003
e75ec752 3004 dev->dev = get_device(&pdev->dev);
9a6b9458 3005 pci_set_drvdata(pdev, dev);
1c63dc66 3006
b00a726a
KB		 3007 result = nvme_dev_map(dev);
3008 if (result)
b00c9b7a 3009 goto put_pci;
b00a726a 3010
d86c4d8e 3011 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
5c8809e6 3012 INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
77bf25ea 3013 mutex_init(&dev->shutdown_lock);
b60503ba 3014
091b6092
MW		 3015 result = nvme_setup_prp_pools(dev);
3016 if (result)
b00c9b7a 3017 goto unmap;
4cc06521 3018
8427bbc2 3019 quirks |= check_vendor_combination_bug(pdev);
ff5350a8 3020
2744d7a0 3021 if (!noacpi && acpi_storage_d3(&pdev->dev)) {
df4f9bc4
DB		 3022 /*
3023 * Some systems use a bios work around to ask for D3 on
3024 * platforms that support kernel managed suspend.
3025 */
3026 dev_info(&pdev->dev,
3027 "platform quirk: setting simple suspend\n");
3028 quirks |= NVME_QUIRK_SIMPLE_SUSPEND;
3029 }
3030
943e942e
JA		 3031 /*
3032 * Double check that our mempool alloc size will cover the biggest
3033 * command we support.
3034 */
b13c6393 3035 alloc_size = nvme_pci_iod_alloc_size();
943e942e
JA		 3036 WARN_ON_ONCE(alloc_size > PAGE_SIZE);
3037
3038 dev->iod_mempool = mempool_create_node(1, mempool_kmalloc,
3039 mempool_kfree,
3040 (void *) alloc_size,
3041 GFP_KERNEL, node);
3042 if (!dev->iod_mempool) {
3043 result = -ENOMEM;
3044 goto release_pools;
3045 }
3046
b6e44b4c
KB		 3047 result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
3048 quirks);
3049 if (result)
3050 goto release_mempool;
3051
1b3c47c1
SG		 3052 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
3053
bd46a906 3054 nvme_reset_ctrl(&dev->ctrl);
18119775 3055 async_schedule(nvme_async_probe, dev);
4caff8fc 3056
b60503ba
MW		 3057 return 0;
3058
b6e44b4c
KB		 3059 release_mempool:
3060 mempool_destroy(dev->iod_mempool);
0877cb0d 3061 release_pools:
091b6092 3062 nvme_release_prp_pools(dev);
b00c9b7a
CJ		 3063 unmap:
3064 nvme_dev_unmap(dev);
a96d4f5c 3065 put_pci:
e75ec752 3066 put_device(dev->dev);
b60503ba
MW		 3067 free:
3068 kfree(dev->queues);
b60503ba
MW		 3069 kfree(dev);
3070 return result;
3071}
3072
775755ed 3073static void nvme_reset_prepare(struct pci_dev *pdev)
f0d54a54 3074{
a6739479 3075 struct nvme_dev *dev = pci_get_drvdata(pdev);
c1ac9a4b
KB		 3076
3077 /*
3078 * We don't need to check the return value from waiting for the reset
3079 * state as pci_dev device lock is held, making it impossible to race
3080 * with ->remove().
3081 */
3082 nvme_disable_prepare_reset(dev, false);
3083 nvme_sync_queues(&dev->ctrl);
775755ed 3084}
f0d54a54 3085
775755ed
CH		 3086static void nvme_reset_done(struct pci_dev *pdev)
3087{
f263fbb8 3088 struct nvme_dev *dev = pci_get_drvdata(pdev);
c1ac9a4b
KB		 3089
3090 if (!nvme_try_sched_reset(&dev->ctrl))
3091 flush_work(&dev->ctrl.reset_work);
f0d54a54
KB		 3092}
3093
09ece142
KB		 3094static void nvme_shutdown(struct pci_dev *pdev)
3095{
3096 struct nvme_dev *dev = pci_get_drvdata(pdev);
4e523547 3097
c1ac9a4b 3098 nvme_disable_prepare_reset(dev, true);
09ece142
KB		 3099}
3100
0521905e
KB		 3101static void nvme_remove_attrs(struct nvme_dev *dev)
3102{
3103 if (dev->attrs_added)
3104 sysfs_remove_group(&dev->ctrl.device->kobj,
3105 &nvme_pci_attr_group);
3106}
3107
f58944e2
KB		 3108/*
3109 * The driver's remove may be called on a device in a partially initialized
3110 * state. This function must not have any dependencies on the device state in
3111 * order to proceed.
3112 */
8d85fce7 3113static void nvme_remove(struct pci_dev *pdev)
b60503ba
MW		 3114{
3115 struct nvme_dev *dev = pci_get_drvdata(pdev);
9a6b9458 3116
bb8d261e 3117 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
9a6b9458 3118 pci_set_drvdata(pdev, NULL);
0ff9d4e1 3119
6db28eda 3120 if (!pci_device_is_present(pdev)) {
0ff9d4e1 3121 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
1d39e692 3122 nvme_dev_disable(dev, true);
6db28eda 3123 }
0ff9d4e1 3124
d86c4d8e 3125 flush_work(&dev->ctrl.reset_work);
d09f2b45
SG		 3126 nvme_stop_ctrl(&dev->ctrl);
3127 nvme_remove_namespaces(&dev->ctrl);
a5cdb68c 3128 nvme_dev_disable(dev, true);
0521905e 3129 nvme_remove_attrs(dev);
87ad72a5 3130 nvme_free_host_mem(dev);
a4aea562 3131 nvme_dev_remove_admin(dev);
a1a5ef99 3132 nvme_free_queues(dev, 0);
9a6b9458 3133 nvme_release_prp_pools(dev);
b00a726a 3134 nvme_dev_unmap(dev);
726612b6 3135 nvme_uninit_ctrl(&dev->ctrl);
b60503ba
MW		 3136}
3137
671a6018 3138#ifdef CONFIG_PM_SLEEP
d916b1be
KB		 3139static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps)
3140{
3141 return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps);
3142}
3143
3144static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps)
3145{
3146 return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL);
3147}
3148
3149static int nvme_resume(struct device *dev)
3150{
3151 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
3152 struct nvme_ctrl *ctrl = &ndev->ctrl;
3153
4eaefe8c 3154 if (ndev->last_ps == U32_MAX ||
d916b1be 3155 nvme_set_power_state(ctrl, ndev->last_ps) != 0)
e5ad96f3
KB		 3156 goto reset;
3157 if (ctrl->hmpre && nvme_setup_host_mem(ndev))
3158 goto reset;
3159
d916b1be 3160 return 0;
e5ad96f3
KB		 3161reset:
3162 return nvme_try_sched_reset(ctrl);
d916b1be
KB		 3163}
3164
cd638946
KB		 3165static int nvme_suspend(struct device *dev)
3166{
3167 struct pci_dev *pdev = to_pci_dev(dev);
3168 struct nvme_dev *ndev = pci_get_drvdata(pdev);
d916b1be
KB		 3169 struct nvme_ctrl *ctrl = &ndev->ctrl;
3170 int ret = -EBUSY;
3171
4eaefe8c
RW		 3172 ndev->last_ps = U32_MAX;
3173
d916b1be
KB		 3174 /*
3175 * The platform does not remove power for a kernel managed suspend so
3176 * use host managed nvme power settings for lowest idle power if
3177 * possible. This should have quicker resume latency than a full device
3178 * shutdown. But if the firmware is involved after the suspend or the
3179 * device does not support any non-default power states, shut down the
3180 * device fully.
4eaefe8c
RW		 3181 *
3182 * If ASPM is not enabled for the device, shut down the device and allow
3183 * the PCI bus layer to put it into D3 in order to take the PCIe link
3184 * down, so as to allow the platform to achieve its minimum low-power
3185 * state (which may not be possible if the link is up).
d916b1be 3186 */
4eaefe8c 3187 if (pm_suspend_via_firmware() || !ctrl->npss ||
cb32de1b 3188 !pcie_aspm_enabled(pdev) ||
c1ac9a4b
KB		 3189 (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND))
3190 return nvme_disable_prepare_reset(ndev, true);
d916b1be
KB		 3191
3192 nvme_start_freeze(ctrl);
3193 nvme_wait_freeze(ctrl);
3194 nvme_sync_queues(ctrl);
3195
5d02a5c1 3196 if (ctrl->state != NVME_CTRL_LIVE)
d916b1be
KB		 3197 goto unfreeze;
3198
e5ad96f3
KB		 3199 /*
3200 * Host memory access may not be successful in a system suspend state,
3201 * but the specification allows the controller to access memory in a
3202 * non-operational power state.
3203 */
3204 if (ndev->hmb) {
3205 ret = nvme_set_host_mem(ndev, 0);
3206 if (ret < 0)
3207 goto unfreeze;
3208 }
3209
d916b1be
KB		 3210 ret = nvme_get_power_state(ctrl, &ndev->last_ps);
3211 if (ret < 0)
3212 goto unfreeze;
3213
7cbb5c6f
ML		 3214 /*
3215 * A saved state prevents pci pm from generically controlling the
3216 * device's power. If we're using protocol specific settings, we don't
3217 * want pci interfering.
3218 */
3219 pci_save_state(pdev);
3220
d916b1be
KB		 3221 ret = nvme_set_power_state(ctrl, ctrl->npss);
3222 if (ret < 0)
3223 goto unfreeze;
3224
3225 if (ret) {
7cbb5c6f
ML		 3226 /* discard the saved state */
3227 pci_load_saved_state(pdev, NULL);
3228
d916b1be
KB		 3229 /*
3230 * Clearing npss forces a controller reset on resume. The
05d3046f 3231 * correct value will be rediscovered then.
d916b1be 3232 */
c1ac9a4b 3233 ret = nvme_disable_prepare_reset(ndev, true);
d916b1be 3234 ctrl->npss = 0;
d916b1be 3235 }
d916b1be
KB		 3236unfreeze:
3237 nvme_unfreeze(ctrl);
3238 return ret;
3239}
3240
3241static int nvme_simple_suspend(struct device *dev)
3242{
3243 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
4e523547 3244
c1ac9a4b 3245 return nvme_disable_prepare_reset(ndev, true);
cd638946
KB		 3246}
3247
d916b1be 3248static int nvme_simple_resume(struct device *dev)
cd638946
KB		 3249{
3250 struct pci_dev *pdev = to_pci_dev(dev);
3251 struct nvme_dev *ndev = pci_get_drvdata(pdev);
cd638946 3252
c1ac9a4b 3253 return nvme_try_sched_reset(&ndev->ctrl);
cd638946
KB		 3254}
3255
21774222 3256static const struct dev_pm_ops nvme_dev_pm_ops = {
d916b1be
KB		 3257 .suspend = nvme_suspend,
3258 .resume = nvme_resume,
3259 .freeze = nvme_simple_suspend,
3260 .thaw = nvme_simple_resume,
3261 .poweroff = nvme_simple_suspend,
3262 .restore = nvme_simple_resume,
3263};
3264#endif /* CONFIG_PM_SLEEP */
b60503ba 3265
a0a3408e
KB		 3266static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
3267 pci_channel_state_t state)
3268{
3269 struct nvme_dev *dev = pci_get_drvdata(pdev);
3270
3271 /*
3272 * A frozen channel requires a reset. When detected, this method will
3273 * shutdown the controller to quiesce. The controller will be restarted
3274 * after the slot reset through driver's slot_reset callback.
3275 */
a0a3408e
KB		 3276 switch (state) {
3277 case pci_channel_io_normal:
3278 return PCI_ERS_RESULT_CAN_RECOVER;
3279 case pci_channel_io_frozen:
d011fb31
KB		 3280 dev_warn(dev->ctrl.device,
3281 "frozen state error detected, reset controller\n");
a5cdb68c 3282 nvme_dev_disable(dev, false);
a0a3408e
KB		 3283 return PCI_ERS_RESULT_NEED_RESET;
3284 case pci_channel_io_perm_failure:
d011fb31
KB		 3285 dev_warn(dev->ctrl.device,
3286 "failure state error detected, request disconnect\n");
a0a3408e
KB		 3287 return PCI_ERS_RESULT_DISCONNECT;
3288 }
3289 return PCI_ERS_RESULT_NEED_RESET;
3290}
3291
3292static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
3293{
3294 struct nvme_dev *dev = pci_get_drvdata(pdev);
3295
1b3c47c1 3296 dev_info(dev->ctrl.device, "restart after slot reset\n");
a0a3408e 3297 pci_restore_state(pdev);
d86c4d8e 3298 nvme_reset_ctrl(&dev->ctrl);
a0a3408e
KB		 3299 return PCI_ERS_RESULT_RECOVERED;
3300}
3301
3302static void nvme_error_resume(struct pci_dev *pdev)
3303{
72cd4cc2
KB		 3304 struct nvme_dev *dev = pci_get_drvdata(pdev);
3305
3306 flush_work(&dev->ctrl.reset_work);
a0a3408e
KB		 3307}
3308
1d352035 3309static const struct pci_error_handlers nvme_err_handler = {
b60503ba 3310 .error_detected = nvme_error_detected,
b60503ba
MW		 3311 .slot_reset = nvme_slot_reset,
3312 .resume = nvme_error_resume,
775755ed
CH		 3313 .reset_prepare = nvme_reset_prepare,
3314 .reset_done = nvme_reset_done,
b60503ba
MW		 3315};
3316
6eb0d698 3317static const struct pci_device_id nvme_id_table[] = {
972b13e2 3318 { PCI_VDEVICE(INTEL, 0x0953), /* Intel 750/P3500/P3600/P3700 */
08095e70 3319 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 3320 NVME_QUIRK_DEALLOCATE_ZEROES, },
972b13e2 3321 { PCI_VDEVICE(INTEL, 0x0a53), /* Intel P3520 */
99466e70 3322 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 3323 NVME_QUIRK_DEALLOCATE_ZEROES, },
972b13e2 3324 { PCI_VDEVICE(INTEL, 0x0a54), /* Intel P4500/P4600 */
99466e70 3325 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 3326 NVME_QUIRK_DEALLOCATE_ZEROES, },
972b13e2 3327 { PCI_VDEVICE(INTEL, 0x0a55), /* Dell Express Flash P4600 */
f99cb7af
DWF		 3328 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3329 NVME_QUIRK_DEALLOCATE_ZEROES, },
50af47d0 3330 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */
9abd68ef 3331 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
6c6aa2f2 3332 NVME_QUIRK_MEDIUM_PRIO_SQ |
ce4cc313
DM		 3333 NVME_QUIRK_NO_TEMP_THRESH_CHANGE |
3334 NVME_QUIRK_DISABLE_WRITE_ZEROES, },
6299358d
JD		 3335 { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */
3336 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
540c801c 3337 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */
7b210e4e
CH		 3338 .driver_data = NVME_QUIRK_IDENTIFY_CNS |
3339 NVME_QUIRK_DISABLE_WRITE_ZEROES, },
5bedd3af
CH		 3340 { PCI_DEVICE(0x126f, 0x2263), /* Silicon Motion unidentified */
3341 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST, },
0302ae60 3342 { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */
5e112d3f
JE		 3343 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
3344 NVME_QUIRK_NO_NS_DESC_LIST, },
54adc010
GP		 3345 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
3346 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
8c97eecc
JL		 3347 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */
3348 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
015282c9
WW		 3349 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
3350 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
d554b5e1
MP		 3351 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */
3352 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3353 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */
7ee5c78c 3354 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
abbb5f59 3355 NVME_QUIRK_DISABLE_WRITE_ZEROES|
7ee5c78c 3356 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
c9e95c39
CS		 3357 { PCI_DEVICE(0x1987, 0x5016), /* Phison E16 */
3358 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
6e6a6828
PT		 3359 { PCI_DEVICE(0x1b4b, 0x1092), /* Lexar 256 GB SSD */
3360 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST |
3361 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
08b903b5
MN		 3362 { PCI_DEVICE(0x10ec, 0x5762), /* ADATA SX6000LNP */
3363 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
f03e42c6
GC		 3364 { PCI_DEVICE(0x1cc1, 0x8201), /* ADATA SX8200PNP 512GB */
3365 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3366 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
5611ec2b
KHF		 3367 { PCI_DEVICE(0x1c5c, 0x1504), /* SK Hynix PC400 */
3368 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
02ca079c
KHF		 3369 { PCI_DEVICE(0x15b7, 0x2001), /* Sandisk Skyhawk */
3370 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
89919929
CK		 3371 { PCI_DEVICE(0x1d97, 0x2263), /* SPCC */
3372 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
dc22c1c0
ZB		 3373 { PCI_DEVICE(0x2646, 0x2262), /* KINGSTON SKC2000 NVMe SSD */
3374 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
538e4a8c
TL		 3375 { PCI_DEVICE(0x2646, 0x2263), /* KINGSTON A2000 NVMe SSD */
3376 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
4bdf2603
FS		 3377 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0061),
3378 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3379 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0065),
3380 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3381 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x8061),
3382 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3383 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd00),
3384 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3385 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd01),
3386 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3387 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd02),
3388 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
98f7b86a
AS		 3389 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001),
3390 .driver_data = NVME_QUIRK_SINGLE_VECTOR },
124298bd 3391 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
66341331
BH		 3392 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005),
3393 .driver_data = NVME_QUIRK_SINGLE_VECTOR |
d38e9f04 3394 NVME_QUIRK_128_BYTES_SQES |
a2941f6a
KB		 3395 NVME_QUIRK_SHARED_TAGS |
3396 NVME_QUIRK_SKIP_CID_GEN },
0b85f59d
AS		 3397
3398 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
b60503ba
MW		 3399 { 0, }
3400};
3401MODULE_DEVICE_TABLE(pci, nvme_id_table);
3402
3403static struct pci_driver nvme_driver = {
3404 .name = "nvme",
3405 .id_table = nvme_id_table,
3406 .probe = nvme_probe,
8d85fce7 3407 .remove = nvme_remove,
09ece142 3408 .shutdown = nvme_shutdown,
d916b1be 3409#ifdef CONFIG_PM_SLEEP
cd638946
KB		 3410 .driver = {
3411 .pm = &nvme_dev_pm_ops,
3412 },
d916b1be 3413#endif
74d986ab 3414 .sriov_configure = pci_sriov_configure_simple,
b60503ba
MW		 3415 .err_handler = &nvme_err_handler,
3416};
3417
3418static int __init nvme_init(void)
3419{
81101540
CH		 3420 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
3421 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
3422 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
612b7286 3423 BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2);
17c33167 3424
9a6327d2 3425 return pci_register_driver(&nvme_driver);
b60503ba
MW		 3426}
3427
3428static void __exit nvme_exit(void)
3429{
3430 pci_unregister_driver(&nvme_driver);
03e0f3a6 3431 flush_workqueue(nvme_wq);
b60503ba
MW		 3432}
3433
3434MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3435MODULE_LICENSE("GPL");
c78b4713 3436MODULE_VERSION("1.0");
b60503ba
MW		 3437module_init(nvme_init);
3438module_exit(nvme_exit);
Linux 6.x block layer and io_uring tree(s)