Commit | Line | Data |
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5f37396d | 1 | // SPDX-License-Identifier: GPL-2.0 |
b60503ba MW |
2 | /* |
3 | * NVM Express device driver | |
6eb0d698 | 4 | * Copyright (c) 2011-2014, Intel Corporation. |
b60503ba MW |
5 | */ |
6 | ||
df4f9bc4 | 7 | #include <linux/acpi.h> |
a0a3408e | 8 | #include <linux/aer.h> |
18119775 | 9 | #include <linux/async.h> |
b60503ba | 10 | #include <linux/blkdev.h> |
a4aea562 | 11 | #include <linux/blk-mq.h> |
dca51e78 | 12 | #include <linux/blk-mq-pci.h> |
fe45e630 | 13 | #include <linux/blk-integrity.h> |
ff5350a8 | 14 | #include <linux/dmi.h> |
b60503ba MW |
15 | #include <linux/init.h> |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/io.h> | |
dc90f084 | 18 | #include <linux/memremap.h> |
b60503ba MW |
19 | #include <linux/mm.h> |
20 | #include <linux/module.h> | |
77bf25ea | 21 | #include <linux/mutex.h> |
d0877473 | 22 | #include <linux/once.h> |
b60503ba | 23 | #include <linux/pci.h> |
d916b1be | 24 | #include <linux/suspend.h> |
e1e5e564 | 25 | #include <linux/t10-pi.h> |
b60503ba | 26 | #include <linux/types.h> |
2f8e2c87 | 27 | #include <linux/io-64-nonatomic-lo-hi.h> |
20d3bb92 | 28 | #include <linux/io-64-nonatomic-hi-lo.h> |
a98e58e5 | 29 | #include <linux/sed-opal.h> |
0f238ff5 | 30 | #include <linux/pci-p2pdma.h> |
797a796a | 31 | |
604c01d5 | 32 | #include "trace.h" |
f11bb3e2 CH |
33 | #include "nvme.h" |
34 | ||
c1e0cc7e | 35 | #define SQ_SIZE(q) ((q)->q_depth << (q)->sqes) |
8a1d09a6 | 36 | #define CQ_SIZE(q) ((q)->q_depth * sizeof(struct nvme_completion)) |
c965809c | 37 | |
a7a7cbe3 | 38 | #define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc)) |
9d43cf64 | 39 | |
943e942e JA |
40 | /* |
41 | * These can be higher, but we need to ensure that any command doesn't | |
42 | * require an sg allocation that needs more than a page of data. | |
43 | */ | |
44 | #define NVME_MAX_KB_SZ 4096 | |
45 | #define NVME_MAX_SEGS 127 | |
46 | ||
58ffacb5 | 47 | static int use_threaded_interrupts; |
2e21e445 | 48 | module_param(use_threaded_interrupts, int, 0444); |
58ffacb5 | 49 | |
8ffaadf7 | 50 | static bool use_cmb_sqes = true; |
69f4eb9f | 51 | module_param(use_cmb_sqes, bool, 0444); |
8ffaadf7 JD |
52 | MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes"); |
53 | ||
87ad72a5 CH |
54 | static unsigned int max_host_mem_size_mb = 128; |
55 | module_param(max_host_mem_size_mb, uint, 0444); | |
56 | MODULE_PARM_DESC(max_host_mem_size_mb, | |
57 | "Maximum Host Memory Buffer (HMB) size per controller (in MiB)"); | |
1fa6aead | 58 | |
a7a7cbe3 CK |
59 | static unsigned int sgl_threshold = SZ_32K; |
60 | module_param(sgl_threshold, uint, 0644); | |
61 | MODULE_PARM_DESC(sgl_threshold, | |
62 | "Use SGLs when average request segment size is larger or equal to " | |
63 | "this size. Use 0 to disable SGLs."); | |
64 | ||
27453b45 SG |
65 | #define NVME_PCI_MIN_QUEUE_SIZE 2 |
66 | #define NVME_PCI_MAX_QUEUE_SIZE 4095 | |
b27c1e68 | 67 | static int io_queue_depth_set(const char *val, const struct kernel_param *kp); |
68 | static const struct kernel_param_ops io_queue_depth_ops = { | |
69 | .set = io_queue_depth_set, | |
61f3b896 | 70 | .get = param_get_uint, |
b27c1e68 | 71 | }; |
72 | ||
61f3b896 | 73 | static unsigned int io_queue_depth = 1024; |
b27c1e68 | 74 | module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644); |
27453b45 | 75 | MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2 and < 4096"); |
b27c1e68 | 76 | |
9c9e76d5 WZ |
77 | static int io_queue_count_set(const char *val, const struct kernel_param *kp) |
78 | { | |
79 | unsigned int n; | |
80 | int ret; | |
81 | ||
82 | ret = kstrtouint(val, 10, &n); | |
83 | if (ret != 0 || n > num_possible_cpus()) | |
84 | return -EINVAL; | |
85 | return param_set_uint(val, kp); | |
86 | } | |
87 | ||
88 | static const struct kernel_param_ops io_queue_count_ops = { | |
89 | .set = io_queue_count_set, | |
90 | .get = param_get_uint, | |
91 | }; | |
92 | ||
3f68baf7 | 93 | static unsigned int write_queues; |
9c9e76d5 | 94 | module_param_cb(write_queues, &io_queue_count_ops, &write_queues, 0644); |
3b6592f7 JA |
95 | MODULE_PARM_DESC(write_queues, |
96 | "Number of queues to use for writes. If not set, reads and writes " | |
97 | "will share a queue set."); | |
98 | ||
3f68baf7 | 99 | static unsigned int poll_queues; |
9c9e76d5 | 100 | module_param_cb(poll_queues, &io_queue_count_ops, &poll_queues, 0644); |
4b04cc6a JA |
101 | MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO."); |
102 | ||
df4f9bc4 DB |
103 | static bool noacpi; |
104 | module_param(noacpi, bool, 0444); | |
105 | MODULE_PARM_DESC(noacpi, "disable acpi bios quirks"); | |
106 | ||
1c63dc66 CH |
107 | struct nvme_dev; |
108 | struct nvme_queue; | |
b3fffdef | 109 | |
a5cdb68c | 110 | static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown); |
8fae268b | 111 | static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode); |
d4b4ff8e | 112 | |
1c63dc66 CH |
113 | /* |
114 | * Represents an NVM Express device. Each nvme_dev is a PCI function. | |
115 | */ | |
116 | struct nvme_dev { | |
147b27e4 | 117 | struct nvme_queue *queues; |
1c63dc66 CH |
118 | struct blk_mq_tag_set tagset; |
119 | struct blk_mq_tag_set admin_tagset; | |
120 | u32 __iomem *dbs; | |
121 | struct device *dev; | |
122 | struct dma_pool *prp_page_pool; | |
123 | struct dma_pool *prp_small_pool; | |
1c63dc66 CH |
124 | unsigned online_queues; |
125 | unsigned max_qid; | |
e20ba6e1 | 126 | unsigned io_queues[HCTX_MAX_TYPES]; |
22b55601 | 127 | unsigned int num_vecs; |
7442ddce | 128 | u32 q_depth; |
c1e0cc7e | 129 | int io_sqes; |
1c63dc66 | 130 | u32 db_stride; |
1c63dc66 | 131 | void __iomem *bar; |
97f6ef64 | 132 | unsigned long bar_mapped_size; |
5c8809e6 | 133 | struct work_struct remove_work; |
77bf25ea | 134 | struct mutex shutdown_lock; |
1c63dc66 | 135 | bool subsystem; |
1c63dc66 | 136 | u64 cmb_size; |
0f238ff5 | 137 | bool cmb_use_sqes; |
1c63dc66 | 138 | u32 cmbsz; |
202021c1 | 139 | u32 cmbloc; |
1c63dc66 | 140 | struct nvme_ctrl ctrl; |
d916b1be | 141 | u32 last_ps; |
a5df5e79 | 142 | bool hmb; |
87ad72a5 | 143 | |
943e942e JA |
144 | mempool_t *iod_mempool; |
145 | ||
87ad72a5 | 146 | /* shadow doorbell buffer support: */ |
f9f38e33 HK |
147 | u32 *dbbuf_dbs; |
148 | dma_addr_t dbbuf_dbs_dma_addr; | |
149 | u32 *dbbuf_eis; | |
150 | dma_addr_t dbbuf_eis_dma_addr; | |
87ad72a5 CH |
151 | |
152 | /* host memory buffer support: */ | |
153 | u64 host_mem_size; | |
154 | u32 nr_host_mem_descs; | |
4033f35d | 155 | dma_addr_t host_mem_descs_dma; |
87ad72a5 CH |
156 | struct nvme_host_mem_buf_desc *host_mem_descs; |
157 | void **host_mem_desc_bufs; | |
2a5bcfdd WZ |
158 | unsigned int nr_allocated_queues; |
159 | unsigned int nr_write_queues; | |
160 | unsigned int nr_poll_queues; | |
4d115420 | 161 | }; |
1fa6aead | 162 | |
b27c1e68 | 163 | static int io_queue_depth_set(const char *val, const struct kernel_param *kp) |
164 | { | |
27453b45 SG |
165 | return param_set_uint_minmax(val, kp, NVME_PCI_MIN_QUEUE_SIZE, |
166 | NVME_PCI_MAX_QUEUE_SIZE); | |
b27c1e68 | 167 | } |
168 | ||
f9f38e33 HK |
169 | static inline unsigned int sq_idx(unsigned int qid, u32 stride) |
170 | { | |
171 | return qid * 2 * stride; | |
172 | } | |
173 | ||
174 | static inline unsigned int cq_idx(unsigned int qid, u32 stride) | |
175 | { | |
176 | return (qid * 2 + 1) * stride; | |
177 | } | |
178 | ||
1c63dc66 CH |
179 | static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl) |
180 | { | |
181 | return container_of(ctrl, struct nvme_dev, ctrl); | |
182 | } | |
183 | ||
b60503ba MW |
184 | /* |
185 | * An NVM Express queue. Each device has at least two (one for admin | |
186 | * commands and one for I/O commands). | |
187 | */ | |
188 | struct nvme_queue { | |
091b6092 | 189 | struct nvme_dev *dev; |
1ab0cd69 | 190 | spinlock_t sq_lock; |
c1e0cc7e | 191 | void *sq_cmds; |
3a7afd8e CH |
192 | /* only used for poll queues: */ |
193 | spinlock_t cq_poll_lock ____cacheline_aligned_in_smp; | |
74943d45 | 194 | struct nvme_completion *cqes; |
b60503ba MW |
195 | dma_addr_t sq_dma_addr; |
196 | dma_addr_t cq_dma_addr; | |
b60503ba | 197 | u32 __iomem *q_db; |
7442ddce | 198 | u32 q_depth; |
7c349dde | 199 | u16 cq_vector; |
b60503ba | 200 | u16 sq_tail; |
38210800 | 201 | u16 last_sq_tail; |
b60503ba | 202 | u16 cq_head; |
c30341dc | 203 | u16 qid; |
e9539f47 | 204 | u8 cq_phase; |
c1e0cc7e | 205 | u8 sqes; |
4e224106 CH |
206 | unsigned long flags; |
207 | #define NVMEQ_ENABLED 0 | |
63223078 | 208 | #define NVMEQ_SQ_CMB 1 |
d1ed6aa1 | 209 | #define NVMEQ_DELETE_ERROR 2 |
7c349dde | 210 | #define NVMEQ_POLLED 3 |
f9f38e33 HK |
211 | u32 *dbbuf_sq_db; |
212 | u32 *dbbuf_cq_db; | |
213 | u32 *dbbuf_sq_ei; | |
214 | u32 *dbbuf_cq_ei; | |
d1ed6aa1 | 215 | struct completion delete_done; |
b60503ba MW |
216 | }; |
217 | ||
71bd150c | 218 | /* |
9b048119 CH |
219 | * The nvme_iod describes the data in an I/O. |
220 | * | |
221 | * The sg pointer contains the list of PRP/SGL chunk allocations in addition | |
222 | * to the actual struct scatterlist. | |
71bd150c CH |
223 | */ |
224 | struct nvme_iod { | |
d49187e9 | 225 | struct nvme_request req; |
af7fae85 | 226 | struct nvme_command cmd; |
a7a7cbe3 | 227 | bool use_sgl; |
52da4f3f | 228 | bool aborted; |
c372cdd1 KB |
229 | s8 nr_allocations; /* PRP list pool allocations. 0 means small |
230 | pool in use */ | |
dff824b2 | 231 | unsigned int dma_len; /* length of single DMA segment mapping */ |
c4c22c52 | 232 | dma_addr_t first_dma; |
783b94bd | 233 | dma_addr_t meta_dma; |
91fb2b60 | 234 | struct sg_table sgt; |
b60503ba MW |
235 | }; |
236 | ||
2a5bcfdd | 237 | static inline unsigned int nvme_dbbuf_size(struct nvme_dev *dev) |
3b6592f7 | 238 | { |
2a5bcfdd | 239 | return dev->nr_allocated_queues * 8 * dev->db_stride; |
f9f38e33 HK |
240 | } |
241 | ||
242 | static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev) | |
243 | { | |
2a5bcfdd | 244 | unsigned int mem_size = nvme_dbbuf_size(dev); |
f9f38e33 | 245 | |
58847f12 KB |
246 | if (dev->dbbuf_dbs) { |
247 | /* | |
248 | * Clear the dbbuf memory so the driver doesn't observe stale | |
249 | * values from the previous instantiation. | |
250 | */ | |
251 | memset(dev->dbbuf_dbs, 0, mem_size); | |
252 | memset(dev->dbbuf_eis, 0, mem_size); | |
f9f38e33 | 253 | return 0; |
58847f12 | 254 | } |
f9f38e33 HK |
255 | |
256 | dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size, | |
257 | &dev->dbbuf_dbs_dma_addr, | |
258 | GFP_KERNEL); | |
259 | if (!dev->dbbuf_dbs) | |
260 | return -ENOMEM; | |
261 | dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size, | |
262 | &dev->dbbuf_eis_dma_addr, | |
263 | GFP_KERNEL); | |
264 | if (!dev->dbbuf_eis) { | |
265 | dma_free_coherent(dev->dev, mem_size, | |
266 | dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); | |
267 | dev->dbbuf_dbs = NULL; | |
268 | return -ENOMEM; | |
269 | } | |
270 | ||
271 | return 0; | |
272 | } | |
273 | ||
274 | static void nvme_dbbuf_dma_free(struct nvme_dev *dev) | |
275 | { | |
2a5bcfdd | 276 | unsigned int mem_size = nvme_dbbuf_size(dev); |
f9f38e33 HK |
277 | |
278 | if (dev->dbbuf_dbs) { | |
279 | dma_free_coherent(dev->dev, mem_size, | |
280 | dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); | |
281 | dev->dbbuf_dbs = NULL; | |
282 | } | |
283 | if (dev->dbbuf_eis) { | |
284 | dma_free_coherent(dev->dev, mem_size, | |
285 | dev->dbbuf_eis, dev->dbbuf_eis_dma_addr); | |
286 | dev->dbbuf_eis = NULL; | |
287 | } | |
288 | } | |
289 | ||
290 | static void nvme_dbbuf_init(struct nvme_dev *dev, | |
291 | struct nvme_queue *nvmeq, int qid) | |
292 | { | |
293 | if (!dev->dbbuf_dbs || !qid) | |
294 | return; | |
295 | ||
296 | nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)]; | |
297 | nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)]; | |
298 | nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)]; | |
299 | nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)]; | |
300 | } | |
301 | ||
0f0d2c87 MI |
302 | static void nvme_dbbuf_free(struct nvme_queue *nvmeq) |
303 | { | |
304 | if (!nvmeq->qid) | |
305 | return; | |
306 | ||
307 | nvmeq->dbbuf_sq_db = NULL; | |
308 | nvmeq->dbbuf_cq_db = NULL; | |
309 | nvmeq->dbbuf_sq_ei = NULL; | |
310 | nvmeq->dbbuf_cq_ei = NULL; | |
311 | } | |
312 | ||
f9f38e33 HK |
313 | static void nvme_dbbuf_set(struct nvme_dev *dev) |
314 | { | |
f66e2804 | 315 | struct nvme_command c = { }; |
0f0d2c87 | 316 | unsigned int i; |
f9f38e33 HK |
317 | |
318 | if (!dev->dbbuf_dbs) | |
319 | return; | |
320 | ||
f9f38e33 HK |
321 | c.dbbuf.opcode = nvme_admin_dbbuf; |
322 | c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr); | |
323 | c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr); | |
324 | ||
325 | if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) { | |
9bdcfb10 | 326 | dev_warn(dev->ctrl.device, "unable to set dbbuf\n"); |
f9f38e33 HK |
327 | /* Free memory and continue on */ |
328 | nvme_dbbuf_dma_free(dev); | |
0f0d2c87 MI |
329 | |
330 | for (i = 1; i <= dev->online_queues; i++) | |
331 | nvme_dbbuf_free(&dev->queues[i]); | |
f9f38e33 HK |
332 | } |
333 | } | |
334 | ||
335 | static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old) | |
336 | { | |
337 | return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old); | |
338 | } | |
339 | ||
340 | /* Update dbbuf and return true if an MMIO is required */ | |
341 | static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db, | |
342 | volatile u32 *dbbuf_ei) | |
343 | { | |
344 | if (dbbuf_db) { | |
345 | u16 old_value; | |
346 | ||
347 | /* | |
348 | * Ensure that the queue is written before updating | |
349 | * the doorbell in memory | |
350 | */ | |
351 | wmb(); | |
352 | ||
353 | old_value = *dbbuf_db; | |
354 | *dbbuf_db = value; | |
355 | ||
f1ed3df2 MW |
356 | /* |
357 | * Ensure that the doorbell is updated before reading the event | |
358 | * index from memory. The controller needs to provide similar | |
359 | * ordering to ensure the envent index is updated before reading | |
360 | * the doorbell. | |
361 | */ | |
362 | mb(); | |
363 | ||
f9f38e33 HK |
364 | if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value)) |
365 | return false; | |
366 | } | |
367 | ||
368 | return true; | |
b60503ba MW |
369 | } |
370 | ||
ac3dd5bd JA |
371 | /* |
372 | * Will slightly overestimate the number of pages needed. This is OK | |
373 | * as it only leads to a small amount of wasted memory for the lifetime of | |
374 | * the I/O. | |
375 | */ | |
b13c6393 | 376 | static int nvme_pci_npages_prp(void) |
ac3dd5bd | 377 | { |
b13c6393 | 378 | unsigned nprps = DIV_ROUND_UP(NVME_MAX_KB_SZ + NVME_CTRL_PAGE_SIZE, |
6c3c05b0 | 379 | NVME_CTRL_PAGE_SIZE); |
ac3dd5bd JA |
380 | return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); |
381 | } | |
382 | ||
a7a7cbe3 CK |
383 | /* |
384 | * Calculates the number of pages needed for the SGL segments. For example a 4k | |
385 | * page can accommodate 256 SGL descriptors. | |
386 | */ | |
b13c6393 | 387 | static int nvme_pci_npages_sgl(void) |
ac3dd5bd | 388 | { |
b13c6393 CK |
389 | return DIV_ROUND_UP(NVME_MAX_SEGS * sizeof(struct nvme_sgl_desc), |
390 | PAGE_SIZE); | |
f4800d6d | 391 | } |
ac3dd5bd | 392 | |
a4aea562 MB |
393 | static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, |
394 | unsigned int hctx_idx) | |
e85248e5 | 395 | { |
a4aea562 | 396 | struct nvme_dev *dev = data; |
147b27e4 | 397 | struct nvme_queue *nvmeq = &dev->queues[0]; |
a4aea562 | 398 | |
42483228 KB |
399 | WARN_ON(hctx_idx != 0); |
400 | WARN_ON(dev->admin_tagset.tags[0] != hctx->tags); | |
42483228 | 401 | |
a4aea562 MB |
402 | hctx->driver_data = nvmeq; |
403 | return 0; | |
e85248e5 MW |
404 | } |
405 | ||
a4aea562 MB |
406 | static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, |
407 | unsigned int hctx_idx) | |
b60503ba | 408 | { |
a4aea562 | 409 | struct nvme_dev *dev = data; |
147b27e4 | 410 | struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1]; |
a4aea562 | 411 | |
42483228 | 412 | WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags); |
a4aea562 MB |
413 | hctx->driver_data = nvmeq; |
414 | return 0; | |
b60503ba MW |
415 | } |
416 | ||
e559398f CH |
417 | static int nvme_pci_init_request(struct blk_mq_tag_set *set, |
418 | struct request *req, unsigned int hctx_idx, | |
419 | unsigned int numa_node) | |
b60503ba | 420 | { |
d6296d39 | 421 | struct nvme_dev *dev = set->driver_data; |
f4800d6d | 422 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
59e29ce6 SG |
423 | |
424 | nvme_req(req)->ctrl = &dev->ctrl; | |
f4b9e6c9 | 425 | nvme_req(req)->cmd = &iod->cmd; |
a4aea562 MB |
426 | return 0; |
427 | } | |
428 | ||
3b6592f7 JA |
429 | static int queue_irq_offset(struct nvme_dev *dev) |
430 | { | |
431 | /* if we have more than 1 vec, admin queue offsets us by 1 */ | |
432 | if (dev->num_vecs > 1) | |
433 | return 1; | |
434 | ||
435 | return 0; | |
436 | } | |
437 | ||
a4e1d0b7 | 438 | static void nvme_pci_map_queues(struct blk_mq_tag_set *set) |
dca51e78 CH |
439 | { |
440 | struct nvme_dev *dev = set->driver_data; | |
3b6592f7 JA |
441 | int i, qoff, offset; |
442 | ||
443 | offset = queue_irq_offset(dev); | |
444 | for (i = 0, qoff = 0; i < set->nr_maps; i++) { | |
445 | struct blk_mq_queue_map *map = &set->map[i]; | |
446 | ||
447 | map->nr_queues = dev->io_queues[i]; | |
448 | if (!map->nr_queues) { | |
e20ba6e1 | 449 | BUG_ON(i == HCTX_TYPE_DEFAULT); |
7e849dd9 | 450 | continue; |
3b6592f7 JA |
451 | } |
452 | ||
4b04cc6a JA |
453 | /* |
454 | * The poll queue(s) doesn't have an IRQ (and hence IRQ | |
455 | * affinity), so use the regular blk-mq cpu mapping | |
456 | */ | |
3b6592f7 | 457 | map->queue_offset = qoff; |
cb9e0e50 | 458 | if (i != HCTX_TYPE_POLL && offset) |
4b04cc6a JA |
459 | blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset); |
460 | else | |
461 | blk_mq_map_queues(map); | |
3b6592f7 JA |
462 | qoff += map->nr_queues; |
463 | offset += map->nr_queues; | |
464 | } | |
dca51e78 CH |
465 | } |
466 | ||
38210800 KB |
467 | /* |
468 | * Write sq tail if we are asked to, or if the next command would wrap. | |
469 | */ | |
470 | static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq) | |
04f3eafd | 471 | { |
38210800 KB |
472 | if (!write_sq) { |
473 | u16 next_tail = nvmeq->sq_tail + 1; | |
474 | ||
475 | if (next_tail == nvmeq->q_depth) | |
476 | next_tail = 0; | |
477 | if (next_tail != nvmeq->last_sq_tail) | |
478 | return; | |
479 | } | |
480 | ||
04f3eafd JA |
481 | if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail, |
482 | nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei)) | |
483 | writel(nvmeq->sq_tail, nvmeq->q_db); | |
38210800 | 484 | nvmeq->last_sq_tail = nvmeq->sq_tail; |
04f3eafd JA |
485 | } |
486 | ||
3233b94c JA |
487 | static inline void nvme_sq_copy_cmd(struct nvme_queue *nvmeq, |
488 | struct nvme_command *cmd) | |
b60503ba | 489 | { |
c1e0cc7e | 490 | memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes), |
3233b94c | 491 | absolute_pointer(cmd), sizeof(*cmd)); |
90ea5ca4 CH |
492 | if (++nvmeq->sq_tail == nvmeq->q_depth) |
493 | nvmeq->sq_tail = 0; | |
04f3eafd JA |
494 | } |
495 | ||
496 | static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx) | |
497 | { | |
498 | struct nvme_queue *nvmeq = hctx->driver_data; | |
499 | ||
500 | spin_lock(&nvmeq->sq_lock); | |
38210800 KB |
501 | if (nvmeq->sq_tail != nvmeq->last_sq_tail) |
502 | nvme_write_sq_db(nvmeq, true); | |
90ea5ca4 | 503 | spin_unlock(&nvmeq->sq_lock); |
b60503ba MW |
504 | } |
505 | ||
a7a7cbe3 | 506 | static void **nvme_pci_iod_list(struct request *req) |
b60503ba | 507 | { |
f4800d6d | 508 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
91fb2b60 | 509 | return (void **)(iod->sgt.sgl + blk_rq_nr_phys_segments(req)); |
b60503ba MW |
510 | } |
511 | ||
955b1b5a MI |
512 | static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req) |
513 | { | |
a53232cb | 514 | struct nvme_queue *nvmeq = req->mq_hctx->driver_data; |
20469a37 | 515 | int nseg = blk_rq_nr_phys_segments(req); |
955b1b5a MI |
516 | unsigned int avg_seg_size; |
517 | ||
20469a37 | 518 | avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg); |
955b1b5a | 519 | |
253a0b76 | 520 | if (!nvme_ctrl_sgl_supported(&dev->ctrl)) |
955b1b5a | 521 | return false; |
a53232cb | 522 | if (!nvmeq->qid) |
955b1b5a MI |
523 | return false; |
524 | if (!sgl_threshold || avg_seg_size < sgl_threshold) | |
525 | return false; | |
526 | return true; | |
527 | } | |
528 | ||
9275c206 | 529 | static void nvme_free_prps(struct nvme_dev *dev, struct request *req) |
b60503ba | 530 | { |
6c3c05b0 | 531 | const int last_prp = NVME_CTRL_PAGE_SIZE / sizeof(__le64) - 1; |
9275c206 CH |
532 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
533 | dma_addr_t dma_addr = iod->first_dma; | |
eca18b23 | 534 | int i; |
eca18b23 | 535 | |
c372cdd1 | 536 | for (i = 0; i < iod->nr_allocations; i++) { |
9275c206 CH |
537 | __le64 *prp_list = nvme_pci_iod_list(req)[i]; |
538 | dma_addr_t next_dma_addr = le64_to_cpu(prp_list[last_prp]); | |
539 | ||
540 | dma_pool_free(dev->prp_page_pool, prp_list, dma_addr); | |
541 | dma_addr = next_dma_addr; | |
7fe07d14 | 542 | } |
9275c206 | 543 | } |
dff824b2 | 544 | |
9275c206 CH |
545 | static void nvme_free_sgls(struct nvme_dev *dev, struct request *req) |
546 | { | |
547 | const int last_sg = SGES_PER_PAGE - 1; | |
548 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); | |
549 | dma_addr_t dma_addr = iod->first_dma; | |
550 | int i; | |
dff824b2 | 551 | |
c372cdd1 | 552 | for (i = 0; i < iod->nr_allocations; i++) { |
9275c206 CH |
553 | struct nvme_sgl_desc *sg_list = nvme_pci_iod_list(req)[i]; |
554 | dma_addr_t next_dma_addr = le64_to_cpu((sg_list[last_sg]).addr); | |
dff824b2 | 555 | |
9275c206 CH |
556 | dma_pool_free(dev->prp_page_pool, sg_list, dma_addr); |
557 | dma_addr = next_dma_addr; | |
558 | } | |
9275c206 | 559 | } |
a7a7cbe3 | 560 | |
9275c206 CH |
561 | static void nvme_unmap_data(struct nvme_dev *dev, struct request *req) |
562 | { | |
563 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); | |
a7a7cbe3 | 564 | |
9275c206 CH |
565 | if (iod->dma_len) { |
566 | dma_unmap_page(dev->dev, iod->first_dma, iod->dma_len, | |
567 | rq_dma_dir(req)); | |
568 | return; | |
eca18b23 | 569 | } |
ac3dd5bd | 570 | |
91fb2b60 LG |
571 | WARN_ON_ONCE(!iod->sgt.nents); |
572 | ||
573 | dma_unmap_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req), 0); | |
9275c206 | 574 | |
c372cdd1 | 575 | if (iod->nr_allocations == 0) |
9275c206 CH |
576 | dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0], |
577 | iod->first_dma); | |
578 | else if (iod->use_sgl) | |
579 | nvme_free_sgls(dev, req); | |
580 | else | |
581 | nvme_free_prps(dev, req); | |
91fb2b60 | 582 | mempool_free(iod->sgt.sgl, dev->iod_mempool); |
b4ff9c8d KB |
583 | } |
584 | ||
d0877473 KB |
585 | static void nvme_print_sgl(struct scatterlist *sgl, int nents) |
586 | { | |
587 | int i; | |
588 | struct scatterlist *sg; | |
589 | ||
590 | for_each_sg(sgl, sg, nents, i) { | |
591 | dma_addr_t phys = sg_phys(sg); | |
592 | pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d " | |
593 | "dma_address:%pad dma_length:%d\n", | |
594 | i, &phys, sg->offset, sg->length, &sg_dma_address(sg), | |
595 | sg_dma_len(sg)); | |
596 | } | |
597 | } | |
598 | ||
a7a7cbe3 CK |
599 | static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev, |
600 | struct request *req, struct nvme_rw_command *cmnd) | |
ff22b54f | 601 | { |
f4800d6d | 602 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
99802a7a | 603 | struct dma_pool *pool; |
b131c61d | 604 | int length = blk_rq_payload_bytes(req); |
91fb2b60 | 605 | struct scatterlist *sg = iod->sgt.sgl; |
ff22b54f MW |
606 | int dma_len = sg_dma_len(sg); |
607 | u64 dma_addr = sg_dma_address(sg); | |
6c3c05b0 | 608 | int offset = dma_addr & (NVME_CTRL_PAGE_SIZE - 1); |
e025344c | 609 | __le64 *prp_list; |
a7a7cbe3 | 610 | void **list = nvme_pci_iod_list(req); |
e025344c | 611 | dma_addr_t prp_dma; |
eca18b23 | 612 | int nprps, i; |
ff22b54f | 613 | |
6c3c05b0 | 614 | length -= (NVME_CTRL_PAGE_SIZE - offset); |
5228b328 JS |
615 | if (length <= 0) { |
616 | iod->first_dma = 0; | |
a7a7cbe3 | 617 | goto done; |
5228b328 | 618 | } |
ff22b54f | 619 | |
6c3c05b0 | 620 | dma_len -= (NVME_CTRL_PAGE_SIZE - offset); |
ff22b54f | 621 | if (dma_len) { |
6c3c05b0 | 622 | dma_addr += (NVME_CTRL_PAGE_SIZE - offset); |
ff22b54f MW |
623 | } else { |
624 | sg = sg_next(sg); | |
625 | dma_addr = sg_dma_address(sg); | |
626 | dma_len = sg_dma_len(sg); | |
627 | } | |
628 | ||
6c3c05b0 | 629 | if (length <= NVME_CTRL_PAGE_SIZE) { |
edd10d33 | 630 | iod->first_dma = dma_addr; |
a7a7cbe3 | 631 | goto done; |
e025344c SMM |
632 | } |
633 | ||
6c3c05b0 | 634 | nprps = DIV_ROUND_UP(length, NVME_CTRL_PAGE_SIZE); |
99802a7a MW |
635 | if (nprps <= (256 / 8)) { |
636 | pool = dev->prp_small_pool; | |
c372cdd1 | 637 | iod->nr_allocations = 0; |
99802a7a MW |
638 | } else { |
639 | pool = dev->prp_page_pool; | |
c372cdd1 | 640 | iod->nr_allocations = 1; |
99802a7a MW |
641 | } |
642 | ||
69d2b571 | 643 | prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); |
b77954cb | 644 | if (!prp_list) { |
c372cdd1 | 645 | iod->nr_allocations = -1; |
86eea289 | 646 | return BLK_STS_RESOURCE; |
b77954cb | 647 | } |
eca18b23 MW |
648 | list[0] = prp_list; |
649 | iod->first_dma = prp_dma; | |
e025344c SMM |
650 | i = 0; |
651 | for (;;) { | |
6c3c05b0 | 652 | if (i == NVME_CTRL_PAGE_SIZE >> 3) { |
e025344c | 653 | __le64 *old_prp_list = prp_list; |
69d2b571 | 654 | prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); |
eca18b23 | 655 | if (!prp_list) |
fa073216 | 656 | goto free_prps; |
c372cdd1 | 657 | list[iod->nr_allocations++] = prp_list; |
7523d834 MW |
658 | prp_list[0] = old_prp_list[i - 1]; |
659 | old_prp_list[i - 1] = cpu_to_le64(prp_dma); | |
660 | i = 1; | |
e025344c SMM |
661 | } |
662 | prp_list[i++] = cpu_to_le64(dma_addr); | |
6c3c05b0 CK |
663 | dma_len -= NVME_CTRL_PAGE_SIZE; |
664 | dma_addr += NVME_CTRL_PAGE_SIZE; | |
665 | length -= NVME_CTRL_PAGE_SIZE; | |
e025344c SMM |
666 | if (length <= 0) |
667 | break; | |
668 | if (dma_len > 0) | |
669 | continue; | |
86eea289 KB |
670 | if (unlikely(dma_len < 0)) |
671 | goto bad_sgl; | |
e025344c SMM |
672 | sg = sg_next(sg); |
673 | dma_addr = sg_dma_address(sg); | |
674 | dma_len = sg_dma_len(sg); | |
ff22b54f | 675 | } |
a7a7cbe3 | 676 | done: |
91fb2b60 | 677 | cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sgt.sgl)); |
a7a7cbe3 | 678 | cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma); |
86eea289 | 679 | return BLK_STS_OK; |
fa073216 CH |
680 | free_prps: |
681 | nvme_free_prps(dev, req); | |
682 | return BLK_STS_RESOURCE; | |
683 | bad_sgl: | |
91fb2b60 | 684 | WARN(DO_ONCE(nvme_print_sgl, iod->sgt.sgl, iod->sgt.nents), |
d0877473 | 685 | "Invalid SGL for payload:%d nents:%d\n", |
91fb2b60 | 686 | blk_rq_payload_bytes(req), iod->sgt.nents); |
86eea289 | 687 | return BLK_STS_IOERR; |
ff22b54f MW |
688 | } |
689 | ||
a7a7cbe3 CK |
690 | static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge, |
691 | struct scatterlist *sg) | |
692 | { | |
693 | sge->addr = cpu_to_le64(sg_dma_address(sg)); | |
694 | sge->length = cpu_to_le32(sg_dma_len(sg)); | |
695 | sge->type = NVME_SGL_FMT_DATA_DESC << 4; | |
696 | } | |
697 | ||
698 | static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge, | |
699 | dma_addr_t dma_addr, int entries) | |
700 | { | |
701 | sge->addr = cpu_to_le64(dma_addr); | |
702 | if (entries < SGES_PER_PAGE) { | |
703 | sge->length = cpu_to_le32(entries * sizeof(*sge)); | |
704 | sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4; | |
705 | } else { | |
706 | sge->length = cpu_to_le32(PAGE_SIZE); | |
707 | sge->type = NVME_SGL_FMT_SEG_DESC << 4; | |
708 | } | |
709 | } | |
710 | ||
711 | static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev, | |
91fb2b60 | 712 | struct request *req, struct nvme_rw_command *cmd) |
a7a7cbe3 CK |
713 | { |
714 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); | |
a7a7cbe3 CK |
715 | struct dma_pool *pool; |
716 | struct nvme_sgl_desc *sg_list; | |
91fb2b60 LG |
717 | struct scatterlist *sg = iod->sgt.sgl; |
718 | unsigned int entries = iod->sgt.nents; | |
a7a7cbe3 | 719 | dma_addr_t sgl_dma; |
b0f2853b | 720 | int i = 0; |
a7a7cbe3 | 721 | |
a7a7cbe3 CK |
722 | /* setting the transfer type as SGL */ |
723 | cmd->flags = NVME_CMD_SGL_METABUF; | |
724 | ||
b0f2853b | 725 | if (entries == 1) { |
a7a7cbe3 CK |
726 | nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg); |
727 | return BLK_STS_OK; | |
728 | } | |
729 | ||
730 | if (entries <= (256 / sizeof(struct nvme_sgl_desc))) { | |
731 | pool = dev->prp_small_pool; | |
c372cdd1 | 732 | iod->nr_allocations = 0; |
a7a7cbe3 CK |
733 | } else { |
734 | pool = dev->prp_page_pool; | |
c372cdd1 | 735 | iod->nr_allocations = 1; |
a7a7cbe3 CK |
736 | } |
737 | ||
738 | sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); | |
739 | if (!sg_list) { | |
c372cdd1 | 740 | iod->nr_allocations = -1; |
a7a7cbe3 CK |
741 | return BLK_STS_RESOURCE; |
742 | } | |
743 | ||
744 | nvme_pci_iod_list(req)[0] = sg_list; | |
745 | iod->first_dma = sgl_dma; | |
746 | ||
747 | nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries); | |
748 | ||
749 | do { | |
750 | if (i == SGES_PER_PAGE) { | |
751 | struct nvme_sgl_desc *old_sg_desc = sg_list; | |
752 | struct nvme_sgl_desc *link = &old_sg_desc[i - 1]; | |
753 | ||
754 | sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); | |
755 | if (!sg_list) | |
fa073216 | 756 | goto free_sgls; |
a7a7cbe3 CK |
757 | |
758 | i = 0; | |
c372cdd1 | 759 | nvme_pci_iod_list(req)[iod->nr_allocations++] = sg_list; |
a7a7cbe3 CK |
760 | sg_list[i++] = *link; |
761 | nvme_pci_sgl_set_seg(link, sgl_dma, entries); | |
762 | } | |
763 | ||
764 | nvme_pci_sgl_set_data(&sg_list[i++], sg); | |
a7a7cbe3 | 765 | sg = sg_next(sg); |
b0f2853b | 766 | } while (--entries > 0); |
a7a7cbe3 | 767 | |
a7a7cbe3 | 768 | return BLK_STS_OK; |
fa073216 CH |
769 | free_sgls: |
770 | nvme_free_sgls(dev, req); | |
771 | return BLK_STS_RESOURCE; | |
a7a7cbe3 CK |
772 | } |
773 | ||
dff824b2 CH |
774 | static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev, |
775 | struct request *req, struct nvme_rw_command *cmnd, | |
776 | struct bio_vec *bv) | |
777 | { | |
778 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); | |
6c3c05b0 CK |
779 | unsigned int offset = bv->bv_offset & (NVME_CTRL_PAGE_SIZE - 1); |
780 | unsigned int first_prp_len = NVME_CTRL_PAGE_SIZE - offset; | |
dff824b2 CH |
781 | |
782 | iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0); | |
783 | if (dma_mapping_error(dev->dev, iod->first_dma)) | |
784 | return BLK_STS_RESOURCE; | |
785 | iod->dma_len = bv->bv_len; | |
786 | ||
787 | cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma); | |
788 | if (bv->bv_len > first_prp_len) | |
789 | cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len); | |
359c1f88 | 790 | return BLK_STS_OK; |
dff824b2 CH |
791 | } |
792 | ||
29791057 CH |
793 | static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev, |
794 | struct request *req, struct nvme_rw_command *cmnd, | |
795 | struct bio_vec *bv) | |
796 | { | |
797 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); | |
798 | ||
799 | iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0); | |
800 | if (dma_mapping_error(dev->dev, iod->first_dma)) | |
801 | return BLK_STS_RESOURCE; | |
802 | iod->dma_len = bv->bv_len; | |
803 | ||
049bf372 | 804 | cmnd->flags = NVME_CMD_SGL_METABUF; |
29791057 CH |
805 | cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma); |
806 | cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len); | |
807 | cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4; | |
359c1f88 | 808 | return BLK_STS_OK; |
29791057 CH |
809 | } |
810 | ||
fc17b653 | 811 | static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req, |
b131c61d | 812 | struct nvme_command *cmnd) |
d29ec824 | 813 | { |
f4800d6d | 814 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
70479b71 | 815 | blk_status_t ret = BLK_STS_RESOURCE; |
91fb2b60 | 816 | int rc; |
d29ec824 | 817 | |
dff824b2 | 818 | if (blk_rq_nr_phys_segments(req) == 1) { |
a53232cb | 819 | struct nvme_queue *nvmeq = req->mq_hctx->driver_data; |
dff824b2 CH |
820 | struct bio_vec bv = req_bvec(req); |
821 | ||
822 | if (!is_pci_p2pdma_page(bv.bv_page)) { | |
6c3c05b0 | 823 | if (bv.bv_offset + bv.bv_len <= NVME_CTRL_PAGE_SIZE * 2) |
dff824b2 CH |
824 | return nvme_setup_prp_simple(dev, req, |
825 | &cmnd->rw, &bv); | |
29791057 | 826 | |
a53232cb | 827 | if (nvmeq->qid && sgl_threshold && |
253a0b76 | 828 | nvme_ctrl_sgl_supported(&dev->ctrl)) |
29791057 CH |
829 | return nvme_setup_sgl_simple(dev, req, |
830 | &cmnd->rw, &bv); | |
dff824b2 CH |
831 | } |
832 | } | |
833 | ||
834 | iod->dma_len = 0; | |
91fb2b60 LG |
835 | iod->sgt.sgl = mempool_alloc(dev->iod_mempool, GFP_ATOMIC); |
836 | if (!iod->sgt.sgl) | |
d43f1ccf | 837 | return BLK_STS_RESOURCE; |
91fb2b60 LG |
838 | sg_init_table(iod->sgt.sgl, blk_rq_nr_phys_segments(req)); |
839 | iod->sgt.orig_nents = blk_rq_map_sg(req->q, req, iod->sgt.sgl); | |
840 | if (!iod->sgt.orig_nents) | |
fa073216 | 841 | goto out_free_sg; |
d29ec824 | 842 | |
91fb2b60 LG |
843 | rc = dma_map_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req), |
844 | DMA_ATTR_NO_WARN); | |
845 | if (rc) { | |
846 | if (rc == -EREMOTEIO) | |
847 | ret = BLK_STS_TARGET; | |
fa073216 | 848 | goto out_free_sg; |
91fb2b60 | 849 | } |
d29ec824 | 850 | |
70479b71 | 851 | iod->use_sgl = nvme_pci_use_sgls(dev, req); |
955b1b5a | 852 | if (iod->use_sgl) |
91fb2b60 | 853 | ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw); |
a7a7cbe3 CK |
854 | else |
855 | ret = nvme_pci_setup_prps(dev, req, &cmnd->rw); | |
86eea289 | 856 | if (ret != BLK_STS_OK) |
fa073216 CH |
857 | goto out_unmap_sg; |
858 | return BLK_STS_OK; | |
859 | ||
860 | out_unmap_sg: | |
91fb2b60 | 861 | dma_unmap_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req), 0); |
fa073216 | 862 | out_free_sg: |
91fb2b60 | 863 | mempool_free(iod->sgt.sgl, dev->iod_mempool); |
4aedb705 CH |
864 | return ret; |
865 | } | |
3045c0d0 | 866 | |
4aedb705 CH |
867 | static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req, |
868 | struct nvme_command *cmnd) | |
869 | { | |
870 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); | |
00df5cb4 | 871 | |
4aedb705 CH |
872 | iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req), |
873 | rq_dma_dir(req), 0); | |
874 | if (dma_mapping_error(dev->dev, iod->meta_dma)) | |
875 | return BLK_STS_IOERR; | |
876 | cmnd->rw.metadata = cpu_to_le64(iod->meta_dma); | |
359c1f88 | 877 | return BLK_STS_OK; |
00df5cb4 MW |
878 | } |
879 | ||
62451a2b | 880 | static blk_status_t nvme_prep_rq(struct nvme_dev *dev, struct request *req) |
edd10d33 | 881 | { |
9b048119 | 882 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
ebe6d874 | 883 | blk_status_t ret; |
e1e5e564 | 884 | |
52da4f3f | 885 | iod->aborted = false; |
c372cdd1 | 886 | iod->nr_allocations = -1; |
91fb2b60 | 887 | iod->sgt.nents = 0; |
9b048119 | 888 | |
62451a2b | 889 | ret = nvme_setup_cmd(req->q->queuedata, req); |
fc17b653 | 890 | if (ret) |
f4800d6d | 891 | return ret; |
a4aea562 | 892 | |
fc17b653 | 893 | if (blk_rq_nr_phys_segments(req)) { |
62451a2b | 894 | ret = nvme_map_data(dev, req, &iod->cmd); |
fc17b653 | 895 | if (ret) |
9b048119 | 896 | goto out_free_cmd; |
fc17b653 | 897 | } |
a4aea562 | 898 | |
4aedb705 | 899 | if (blk_integrity_rq(req)) { |
62451a2b | 900 | ret = nvme_map_metadata(dev, req, &iod->cmd); |
4aedb705 CH |
901 | if (ret) |
902 | goto out_unmap_data; | |
903 | } | |
904 | ||
aae239e1 | 905 | blk_mq_start_request(req); |
fc17b653 | 906 | return BLK_STS_OK; |
4aedb705 CH |
907 | out_unmap_data: |
908 | nvme_unmap_data(dev, req); | |
f9d03f96 CH |
909 | out_free_cmd: |
910 | nvme_cleanup_cmd(req); | |
ba1ca37e | 911 | return ret; |
b60503ba | 912 | } |
e1e5e564 | 913 | |
62451a2b JA |
914 | /* |
915 | * NOTE: ns is NULL when called on the admin queue. | |
916 | */ | |
917 | static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx, | |
918 | const struct blk_mq_queue_data *bd) | |
919 | { | |
920 | struct nvme_queue *nvmeq = hctx->driver_data; | |
921 | struct nvme_dev *dev = nvmeq->dev; | |
922 | struct request *req = bd->rq; | |
923 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); | |
924 | blk_status_t ret; | |
925 | ||
926 | /* | |
927 | * We should not need to do this, but we're still using this to | |
928 | * ensure we can drain requests on a dying queue. | |
929 | */ | |
930 | if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags))) | |
931 | return BLK_STS_IOERR; | |
932 | ||
933 | if (unlikely(!nvme_check_ready(&dev->ctrl, req, true))) | |
934 | return nvme_fail_nonready_command(&dev->ctrl, req); | |
935 | ||
936 | ret = nvme_prep_rq(dev, req); | |
937 | if (unlikely(ret)) | |
938 | return ret; | |
939 | spin_lock(&nvmeq->sq_lock); | |
940 | nvme_sq_copy_cmd(nvmeq, &iod->cmd); | |
941 | nvme_write_sq_db(nvmeq, bd->last); | |
942 | spin_unlock(&nvmeq->sq_lock); | |
943 | return BLK_STS_OK; | |
944 | } | |
945 | ||
d62cbcf6 JA |
946 | static void nvme_submit_cmds(struct nvme_queue *nvmeq, struct request **rqlist) |
947 | { | |
948 | spin_lock(&nvmeq->sq_lock); | |
949 | while (!rq_list_empty(*rqlist)) { | |
950 | struct request *req = rq_list_pop(rqlist); | |
951 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); | |
952 | ||
953 | nvme_sq_copy_cmd(nvmeq, &iod->cmd); | |
954 | } | |
955 | nvme_write_sq_db(nvmeq, true); | |
956 | spin_unlock(&nvmeq->sq_lock); | |
957 | } | |
958 | ||
959 | static bool nvme_prep_rq_batch(struct nvme_queue *nvmeq, struct request *req) | |
960 | { | |
961 | /* | |
962 | * We should not need to do this, but we're still using this to | |
963 | * ensure we can drain requests on a dying queue. | |
964 | */ | |
965 | if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags))) | |
966 | return false; | |
967 | if (unlikely(!nvme_check_ready(&nvmeq->dev->ctrl, req, true))) | |
968 | return false; | |
969 | ||
970 | req->mq_hctx->tags->rqs[req->tag] = req; | |
971 | return nvme_prep_rq(nvmeq->dev, req) == BLK_STS_OK; | |
972 | } | |
973 | ||
974 | static void nvme_queue_rqs(struct request **rqlist) | |
975 | { | |
6bfec799 | 976 | struct request *req, *next, *prev = NULL; |
d62cbcf6 JA |
977 | struct request *requeue_list = NULL; |
978 | ||
6bfec799 | 979 | rq_list_for_each_safe(rqlist, req, next) { |
d62cbcf6 JA |
980 | struct nvme_queue *nvmeq = req->mq_hctx->driver_data; |
981 | ||
982 | if (!nvme_prep_rq_batch(nvmeq, req)) { | |
983 | /* detach 'req' and add to remainder list */ | |
6bfec799 KB |
984 | rq_list_move(rqlist, &requeue_list, req, prev); |
985 | ||
986 | req = prev; | |
987 | if (!req) | |
988 | continue; | |
d62cbcf6 JA |
989 | } |
990 | ||
6bfec799 | 991 | if (!next || req->mq_hctx != next->mq_hctx) { |
d62cbcf6 | 992 | /* detach rest of list, and submit */ |
6bfec799 | 993 | req->rq_next = NULL; |
d62cbcf6 | 994 | nvme_submit_cmds(nvmeq, rqlist); |
6bfec799 KB |
995 | *rqlist = next; |
996 | prev = NULL; | |
997 | } else | |
998 | prev = req; | |
999 | } | |
d62cbcf6 JA |
1000 | |
1001 | *rqlist = requeue_list; | |
1002 | } | |
1003 | ||
c234a653 | 1004 | static __always_inline void nvme_pci_unmap_rq(struct request *req) |
eee417b0 | 1005 | { |
a53232cb KB |
1006 | struct nvme_queue *nvmeq = req->mq_hctx->driver_data; |
1007 | struct nvme_dev *dev = nvmeq->dev; | |
1008 | ||
1009 | if (blk_integrity_rq(req)) { | |
1010 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); | |
a4aea562 | 1011 | |
4aedb705 CH |
1012 | dma_unmap_page(dev->dev, iod->meta_dma, |
1013 | rq_integrity_vec(req)->bv_len, rq_data_dir(req)); | |
a53232cb KB |
1014 | } |
1015 | ||
b15c592d | 1016 | if (blk_rq_nr_phys_segments(req)) |
4aedb705 | 1017 | nvme_unmap_data(dev, req); |
c234a653 JA |
1018 | } |
1019 | ||
1020 | static void nvme_pci_complete_rq(struct request *req) | |
1021 | { | |
1022 | nvme_pci_unmap_rq(req); | |
77f02a7a | 1023 | nvme_complete_rq(req); |
b60503ba MW |
1024 | } |
1025 | ||
c234a653 JA |
1026 | static void nvme_pci_complete_batch(struct io_comp_batch *iob) |
1027 | { | |
1028 | nvme_complete_batch(iob, nvme_pci_unmap_rq); | |
1029 | } | |
1030 | ||
d783e0bd | 1031 | /* We read the CQE phase first to check if the rest of the entry is valid */ |
750dde44 | 1032 | static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq) |
d783e0bd | 1033 | { |
74943d45 KB |
1034 | struct nvme_completion *hcqe = &nvmeq->cqes[nvmeq->cq_head]; |
1035 | ||
1036 | return (le16_to_cpu(READ_ONCE(hcqe->status)) & 1) == nvmeq->cq_phase; | |
d783e0bd MR |
1037 | } |
1038 | ||
eb281c82 | 1039 | static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq) |
b60503ba | 1040 | { |
eb281c82 | 1041 | u16 head = nvmeq->cq_head; |
adf68f21 | 1042 | |
397c699f KB |
1043 | if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db, |
1044 | nvmeq->dbbuf_cq_ei)) | |
1045 | writel(head, nvmeq->q_db + nvmeq->dev->db_stride); | |
eb281c82 | 1046 | } |
aae239e1 | 1047 | |
cfa27356 CH |
1048 | static inline struct blk_mq_tags *nvme_queue_tagset(struct nvme_queue *nvmeq) |
1049 | { | |
1050 | if (!nvmeq->qid) | |
1051 | return nvmeq->dev->admin_tagset.tags[0]; | |
1052 | return nvmeq->dev->tagset.tags[nvmeq->qid - 1]; | |
1053 | } | |
1054 | ||
c234a653 JA |
1055 | static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, |
1056 | struct io_comp_batch *iob, u16 idx) | |
83a12fb7 | 1057 | { |
74943d45 | 1058 | struct nvme_completion *cqe = &nvmeq->cqes[idx]; |
62df8016 | 1059 | __u16 command_id = READ_ONCE(cqe->command_id); |
83a12fb7 | 1060 | struct request *req; |
adf68f21 | 1061 | |
83a12fb7 SG |
1062 | /* |
1063 | * AEN requests are special as they don't time out and can | |
1064 | * survive any kind of queue freeze and often don't respond to | |
1065 | * aborts. We don't even bother to allocate a struct request | |
1066 | * for them but rather special case them here. | |
1067 | */ | |
62df8016 | 1068 | if (unlikely(nvme_is_aen_req(nvmeq->qid, command_id))) { |
83a12fb7 SG |
1069 | nvme_complete_async_event(&nvmeq->dev->ctrl, |
1070 | cqe->status, &cqe->result); | |
a0fa9647 | 1071 | return; |
83a12fb7 | 1072 | } |
b60503ba | 1073 | |
e7006de6 | 1074 | req = nvme_find_rq(nvme_queue_tagset(nvmeq), command_id); |
50b7c243 XT |
1075 | if (unlikely(!req)) { |
1076 | dev_warn(nvmeq->dev->ctrl.device, | |
1077 | "invalid id %d completed on queue %d\n", | |
62df8016 | 1078 | command_id, le16_to_cpu(cqe->sq_id)); |
50b7c243 XT |
1079 | return; |
1080 | } | |
1081 | ||
604c01d5 | 1082 | trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail); |
c234a653 JA |
1083 | if (!nvme_try_complete_req(req, cqe->status, cqe->result) && |
1084 | !blk_mq_add_to_batch(req, iob, nvme_req(req)->status, | |
1085 | nvme_pci_complete_batch)) | |
ff029451 | 1086 | nvme_pci_complete_rq(req); |
83a12fb7 | 1087 | } |
b60503ba | 1088 | |
5cb525c8 JA |
1089 | static inline void nvme_update_cq_head(struct nvme_queue *nvmeq) |
1090 | { | |
a0aac973 | 1091 | u32 tmp = nvmeq->cq_head + 1; |
a8de6639 AD |
1092 | |
1093 | if (tmp == nvmeq->q_depth) { | |
5cb525c8 | 1094 | nvmeq->cq_head = 0; |
e2a366a4 | 1095 | nvmeq->cq_phase ^= 1; |
a8de6639 AD |
1096 | } else { |
1097 | nvmeq->cq_head = tmp; | |
b60503ba | 1098 | } |
a0fa9647 JA |
1099 | } |
1100 | ||
c234a653 JA |
1101 | static inline int nvme_poll_cq(struct nvme_queue *nvmeq, |
1102 | struct io_comp_batch *iob) | |
a0fa9647 | 1103 | { |
1052b8ac | 1104 | int found = 0; |
b60503ba | 1105 | |
1052b8ac | 1106 | while (nvme_cqe_pending(nvmeq)) { |
bf392a5d | 1107 | found++; |
b69e2ef2 KB |
1108 | /* |
1109 | * load-load control dependency between phase and the rest of | |
1110 | * the cqe requires a full read memory barrier | |
1111 | */ | |
1112 | dma_rmb(); | |
c234a653 | 1113 | nvme_handle_cqe(nvmeq, iob, nvmeq->cq_head); |
5cb525c8 | 1114 | nvme_update_cq_head(nvmeq); |
920d13a8 | 1115 | } |
eb281c82 | 1116 | |
324b494c | 1117 | if (found) |
920d13a8 | 1118 | nvme_ring_cq_doorbell(nvmeq); |
5cb525c8 | 1119 | return found; |
b60503ba MW |
1120 | } |
1121 | ||
1122 | static irqreturn_t nvme_irq(int irq, void *data) | |
58ffacb5 | 1123 | { |
58ffacb5 | 1124 | struct nvme_queue *nvmeq = data; |
4f502245 | 1125 | DEFINE_IO_COMP_BATCH(iob); |
5cb525c8 | 1126 | |
4f502245 JA |
1127 | if (nvme_poll_cq(nvmeq, &iob)) { |
1128 | if (!rq_list_empty(iob.req_list)) | |
1129 | nvme_pci_complete_batch(&iob); | |
05fae499 | 1130 | return IRQ_HANDLED; |
4f502245 | 1131 | } |
05fae499 | 1132 | return IRQ_NONE; |
58ffacb5 MW |
1133 | } |
1134 | ||
1135 | static irqreturn_t nvme_irq_check(int irq, void *data) | |
1136 | { | |
1137 | struct nvme_queue *nvmeq = data; | |
4e523547 | 1138 | |
750dde44 | 1139 | if (nvme_cqe_pending(nvmeq)) |
d783e0bd MR |
1140 | return IRQ_WAKE_THREAD; |
1141 | return IRQ_NONE; | |
58ffacb5 MW |
1142 | } |
1143 | ||
0b2a8a9f | 1144 | /* |
fa059b85 | 1145 | * Poll for completions for any interrupt driven queue |
0b2a8a9f CH |
1146 | * Can be called from any context. |
1147 | */ | |
fa059b85 | 1148 | static void nvme_poll_irqdisable(struct nvme_queue *nvmeq) |
a0fa9647 | 1149 | { |
3a7afd8e | 1150 | struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); |
a0fa9647 | 1151 | |
fa059b85 | 1152 | WARN_ON_ONCE(test_bit(NVMEQ_POLLED, &nvmeq->flags)); |
442e19b7 | 1153 | |
fa059b85 | 1154 | disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); |
c234a653 | 1155 | nvme_poll_cq(nvmeq, NULL); |
fa059b85 | 1156 | enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); |
a0fa9647 JA |
1157 | } |
1158 | ||
5a72e899 | 1159 | static int nvme_poll(struct blk_mq_hw_ctx *hctx, struct io_comp_batch *iob) |
dabcefab JA |
1160 | { |
1161 | struct nvme_queue *nvmeq = hctx->driver_data; | |
dabcefab JA |
1162 | bool found; |
1163 | ||
1164 | if (!nvme_cqe_pending(nvmeq)) | |
1165 | return 0; | |
1166 | ||
3a7afd8e | 1167 | spin_lock(&nvmeq->cq_poll_lock); |
c234a653 | 1168 | found = nvme_poll_cq(nvmeq, iob); |
3a7afd8e | 1169 | spin_unlock(&nvmeq->cq_poll_lock); |
dabcefab | 1170 | |
dabcefab JA |
1171 | return found; |
1172 | } | |
1173 | ||
ad22c355 | 1174 | static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl) |
b60503ba | 1175 | { |
f866fc42 | 1176 | struct nvme_dev *dev = to_nvme_dev(ctrl); |
147b27e4 | 1177 | struct nvme_queue *nvmeq = &dev->queues[0]; |
f66e2804 | 1178 | struct nvme_command c = { }; |
b60503ba | 1179 | |
a4aea562 | 1180 | c.common.opcode = nvme_admin_async_event; |
ad22c355 | 1181 | c.common.command_id = NVME_AQ_BLK_MQ_DEPTH; |
3233b94c JA |
1182 | |
1183 | spin_lock(&nvmeq->sq_lock); | |
1184 | nvme_sq_copy_cmd(nvmeq, &c); | |
1185 | nvme_write_sq_db(nvmeq, true); | |
1186 | spin_unlock(&nvmeq->sq_lock); | |
f705f837 CH |
1187 | } |
1188 | ||
b60503ba | 1189 | static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) |
f705f837 | 1190 | { |
f66e2804 | 1191 | struct nvme_command c = { }; |
b60503ba | 1192 | |
b60503ba MW |
1193 | c.delete_queue.opcode = opcode; |
1194 | c.delete_queue.qid = cpu_to_le16(id); | |
1195 | ||
1c63dc66 | 1196 | return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); |
b60503ba MW |
1197 | } |
1198 | ||
b60503ba | 1199 | static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, |
a8e3e0bb | 1200 | struct nvme_queue *nvmeq, s16 vector) |
b60503ba | 1201 | { |
f66e2804 | 1202 | struct nvme_command c = { }; |
4b04cc6a JA |
1203 | int flags = NVME_QUEUE_PHYS_CONTIG; |
1204 | ||
7c349dde | 1205 | if (!test_bit(NVMEQ_POLLED, &nvmeq->flags)) |
4b04cc6a | 1206 | flags |= NVME_CQ_IRQ_ENABLED; |
b60503ba | 1207 | |
d29ec824 | 1208 | /* |
16772ae6 | 1209 | * Note: we (ab)use the fact that the prp fields survive if no data |
d29ec824 CH |
1210 | * is attached to the request. |
1211 | */ | |
b60503ba MW |
1212 | c.create_cq.opcode = nvme_admin_create_cq; |
1213 | c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); | |
1214 | c.create_cq.cqid = cpu_to_le16(qid); | |
1215 | c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); | |
1216 | c.create_cq.cq_flags = cpu_to_le16(flags); | |
7c349dde | 1217 | c.create_cq.irq_vector = cpu_to_le16(vector); |
b60503ba | 1218 | |
1c63dc66 | 1219 | return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); |
b60503ba MW |
1220 | } |
1221 | ||
1222 | static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, | |
1223 | struct nvme_queue *nvmeq) | |
1224 | { | |
9abd68ef | 1225 | struct nvme_ctrl *ctrl = &dev->ctrl; |
f66e2804 | 1226 | struct nvme_command c = { }; |
81c1cd98 | 1227 | int flags = NVME_QUEUE_PHYS_CONTIG; |
b60503ba | 1228 | |
9abd68ef JA |
1229 | /* |
1230 | * Some drives have a bug that auto-enables WRRU if MEDIUM isn't | |
1231 | * set. Since URGENT priority is zeroes, it makes all queues | |
1232 | * URGENT. | |
1233 | */ | |
1234 | if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ) | |
1235 | flags |= NVME_SQ_PRIO_MEDIUM; | |
1236 | ||
d29ec824 | 1237 | /* |
16772ae6 | 1238 | * Note: we (ab)use the fact that the prp fields survive if no data |
d29ec824 CH |
1239 | * is attached to the request. |
1240 | */ | |
b60503ba MW |
1241 | c.create_sq.opcode = nvme_admin_create_sq; |
1242 | c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); | |
1243 | c.create_sq.sqid = cpu_to_le16(qid); | |
1244 | c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); | |
1245 | c.create_sq.sq_flags = cpu_to_le16(flags); | |
1246 | c.create_sq.cqid = cpu_to_le16(qid); | |
1247 | ||
1c63dc66 | 1248 | return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); |
b60503ba MW |
1249 | } |
1250 | ||
1251 | static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) | |
1252 | { | |
1253 | return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); | |
1254 | } | |
1255 | ||
1256 | static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) | |
1257 | { | |
1258 | return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); | |
1259 | } | |
1260 | ||
de671d61 | 1261 | static enum rq_end_io_ret abort_endio(struct request *req, blk_status_t error) |
bc5fc7e4 | 1262 | { |
a53232cb | 1263 | struct nvme_queue *nvmeq = req->mq_hctx->driver_data; |
e44ac588 | 1264 | |
27fa9bc5 CH |
1265 | dev_warn(nvmeq->dev->ctrl.device, |
1266 | "Abort status: 0x%x", nvme_req(req)->status); | |
e7a2a87d | 1267 | atomic_inc(&nvmeq->dev->ctrl.abort_limit); |
e7a2a87d | 1268 | blk_mq_free_request(req); |
de671d61 | 1269 | return RQ_END_IO_NONE; |
bc5fc7e4 MW |
1270 | } |
1271 | ||
b2a0eb1a KB |
1272 | static bool nvme_should_reset(struct nvme_dev *dev, u32 csts) |
1273 | { | |
b2a0eb1a KB |
1274 | /* If true, indicates loss of adapter communication, possibly by a |
1275 | * NVMe Subsystem reset. | |
1276 | */ | |
1277 | bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO); | |
1278 | ||
ad70062c JW |
1279 | /* If there is a reset/reinit ongoing, we shouldn't reset again. */ |
1280 | switch (dev->ctrl.state) { | |
1281 | case NVME_CTRL_RESETTING: | |
ad6a0a52 | 1282 | case NVME_CTRL_CONNECTING: |
b2a0eb1a | 1283 | return false; |
ad70062c JW |
1284 | default: |
1285 | break; | |
1286 | } | |
b2a0eb1a KB |
1287 | |
1288 | /* We shouldn't reset unless the controller is on fatal error state | |
1289 | * _or_ if we lost the communication with it. | |
1290 | */ | |
1291 | if (!(csts & NVME_CSTS_CFS) && !nssro) | |
1292 | return false; | |
1293 | ||
b2a0eb1a KB |
1294 | return true; |
1295 | } | |
1296 | ||
1297 | static void nvme_warn_reset(struct nvme_dev *dev, u32 csts) | |
1298 | { | |
1299 | /* Read a config register to help see what died. */ | |
1300 | u16 pci_status; | |
1301 | int result; | |
1302 | ||
1303 | result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS, | |
1304 | &pci_status); | |
1305 | if (result == PCIBIOS_SUCCESSFUL) | |
1306 | dev_warn(dev->ctrl.device, | |
1307 | "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n", | |
1308 | csts, pci_status); | |
1309 | else | |
1310 | dev_warn(dev->ctrl.device, | |
1311 | "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n", | |
1312 | csts, result); | |
4641a8e6 KB |
1313 | |
1314 | if (csts != ~0) | |
1315 | return; | |
1316 | ||
1317 | dev_warn(dev->ctrl.device, | |
1318 | "Does your device have a faulty power saving mode enabled?\n"); | |
1319 | dev_warn(dev->ctrl.device, | |
1320 | "Try \"nvme_core.default_ps_max_latency_us=0 pcie_aspm=off\" and report a bug\n"); | |
b2a0eb1a KB |
1321 | } |
1322 | ||
9bdb4833 | 1323 | static enum blk_eh_timer_return nvme_timeout(struct request *req) |
c30341dc | 1324 | { |
f4800d6d | 1325 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
a53232cb | 1326 | struct nvme_queue *nvmeq = req->mq_hctx->driver_data; |
c30341dc | 1327 | struct nvme_dev *dev = nvmeq->dev; |
a4aea562 | 1328 | struct request *abort_req; |
f66e2804 | 1329 | struct nvme_command cmd = { }; |
b2a0eb1a KB |
1330 | u32 csts = readl(dev->bar + NVME_REG_CSTS); |
1331 | ||
651438bb WX |
1332 | /* If PCI error recovery process is happening, we cannot reset or |
1333 | * the recovery mechanism will surely fail. | |
1334 | */ | |
1335 | mb(); | |
1336 | if (pci_channel_offline(to_pci_dev(dev->dev))) | |
1337 | return BLK_EH_RESET_TIMER; | |
1338 | ||
b2a0eb1a KB |
1339 | /* |
1340 | * Reset immediately if the controller is failed | |
1341 | */ | |
1342 | if (nvme_should_reset(dev, csts)) { | |
1343 | nvme_warn_reset(dev, csts); | |
1344 | nvme_dev_disable(dev, false); | |
d86c4d8e | 1345 | nvme_reset_ctrl(&dev->ctrl); |
db8c48e4 | 1346 | return BLK_EH_DONE; |
b2a0eb1a | 1347 | } |
c30341dc | 1348 | |
7776db1c KB |
1349 | /* |
1350 | * Did we miss an interrupt? | |
1351 | */ | |
fa059b85 | 1352 | if (test_bit(NVMEQ_POLLED, &nvmeq->flags)) |
5a72e899 | 1353 | nvme_poll(req->mq_hctx, NULL); |
fa059b85 KB |
1354 | else |
1355 | nvme_poll_irqdisable(nvmeq); | |
1356 | ||
bf392a5d | 1357 | if (blk_mq_request_completed(req)) { |
7776db1c KB |
1358 | dev_warn(dev->ctrl.device, |
1359 | "I/O %d QID %d timeout, completion polled\n", | |
1360 | req->tag, nvmeq->qid); | |
db8c48e4 | 1361 | return BLK_EH_DONE; |
7776db1c KB |
1362 | } |
1363 | ||
31c7c7d2 | 1364 | /* |
fd634f41 CH |
1365 | * Shutdown immediately if controller times out while starting. The |
1366 | * reset work will see the pci device disabled when it gets the forced | |
1367 | * cancellation error. All outstanding requests are completed on | |
db8c48e4 | 1368 | * shutdown, so we return BLK_EH_DONE. |
fd634f41 | 1369 | */ |
4244140d KB |
1370 | switch (dev->ctrl.state) { |
1371 | case NVME_CTRL_CONNECTING: | |
2036f726 | 1372 | nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); |
df561f66 | 1373 | fallthrough; |
2036f726 | 1374 | case NVME_CTRL_DELETING: |
b9cac43c | 1375 | dev_warn_ratelimited(dev->ctrl.device, |
fd634f41 CH |
1376 | "I/O %d QID %d timeout, disable controller\n", |
1377 | req->tag, nvmeq->qid); | |
27fa9bc5 | 1378 | nvme_req(req)->flags |= NVME_REQ_CANCELLED; |
7ad92f65 | 1379 | nvme_dev_disable(dev, true); |
db8c48e4 | 1380 | return BLK_EH_DONE; |
39a9dd81 KB |
1381 | case NVME_CTRL_RESETTING: |
1382 | return BLK_EH_RESET_TIMER; | |
4244140d KB |
1383 | default: |
1384 | break; | |
c30341dc KB |
1385 | } |
1386 | ||
fd634f41 | 1387 | /* |
ee0d96d3 BW |
1388 | * Shutdown the controller immediately and schedule a reset if the |
1389 | * command was already aborted once before and still hasn't been | |
1390 | * returned to the driver, or if this is the admin queue. | |
31c7c7d2 | 1391 | */ |
f4800d6d | 1392 | if (!nvmeq->qid || iod->aborted) { |
1b3c47c1 | 1393 | dev_warn(dev->ctrl.device, |
e1569a16 KB |
1394 | "I/O %d QID %d timeout, reset controller\n", |
1395 | req->tag, nvmeq->qid); | |
7ad92f65 | 1396 | nvme_req(req)->flags |= NVME_REQ_CANCELLED; |
a5cdb68c | 1397 | nvme_dev_disable(dev, false); |
d86c4d8e | 1398 | nvme_reset_ctrl(&dev->ctrl); |
c30341dc | 1399 | |
db8c48e4 | 1400 | return BLK_EH_DONE; |
c30341dc | 1401 | } |
c30341dc | 1402 | |
e7a2a87d | 1403 | if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) { |
6bf25d16 | 1404 | atomic_inc(&dev->ctrl.abort_limit); |
31c7c7d2 | 1405 | return BLK_EH_RESET_TIMER; |
6bf25d16 | 1406 | } |
52da4f3f | 1407 | iod->aborted = true; |
a4aea562 | 1408 | |
c30341dc | 1409 | cmd.abort.opcode = nvme_admin_abort_cmd; |
85f74acf | 1410 | cmd.abort.cid = nvme_cid(req); |
c30341dc | 1411 | cmd.abort.sqid = cpu_to_le16(nvmeq->qid); |
c30341dc | 1412 | |
1b3c47c1 | 1413 | dev_warn(nvmeq->dev->ctrl.device, |
86141440 CH |
1414 | "I/O %d (%s) QID %d timeout, aborting\n", |
1415 | req->tag, | |
1416 | nvme_get_opcode_str(nvme_req(req)->cmd->common.opcode), | |
1417 | nvmeq->qid); | |
e7a2a87d | 1418 | |
e559398f CH |
1419 | abort_req = blk_mq_alloc_request(dev->ctrl.admin_q, nvme_req_op(&cmd), |
1420 | BLK_MQ_REQ_NOWAIT); | |
e7a2a87d CH |
1421 | if (IS_ERR(abort_req)) { |
1422 | atomic_inc(&dev->ctrl.abort_limit); | |
1423 | return BLK_EH_RESET_TIMER; | |
1424 | } | |
e559398f | 1425 | nvme_init_request(abort_req, &cmd); |
e7a2a87d | 1426 | |
e2e53086 | 1427 | abort_req->end_io = abort_endio; |
e7a2a87d | 1428 | abort_req->end_io_data = NULL; |
128126a7 | 1429 | abort_req->rq_flags |= RQF_QUIET; |
e2e53086 | 1430 | blk_execute_rq_nowait(abort_req, false); |
c30341dc | 1431 | |
31c7c7d2 CH |
1432 | /* |
1433 | * The aborted req will be completed on receiving the abort req. | |
1434 | * We enable the timer again. If hit twice, it'll cause a device reset, | |
1435 | * as the device then is in a faulty state. | |
1436 | */ | |
1437 | return BLK_EH_RESET_TIMER; | |
c30341dc KB |
1438 | } |
1439 | ||
a4aea562 MB |
1440 | static void nvme_free_queue(struct nvme_queue *nvmeq) |
1441 | { | |
8a1d09a6 | 1442 | dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq), |
9e866774 | 1443 | (void *)nvmeq->cqes, nvmeq->cq_dma_addr); |
63223078 CH |
1444 | if (!nvmeq->sq_cmds) |
1445 | return; | |
0f238ff5 | 1446 | |
63223078 | 1447 | if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) { |
88a041f4 | 1448 | pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev), |
8a1d09a6 | 1449 | nvmeq->sq_cmds, SQ_SIZE(nvmeq)); |
63223078 | 1450 | } else { |
8a1d09a6 | 1451 | dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq), |
63223078 | 1452 | nvmeq->sq_cmds, nvmeq->sq_dma_addr); |
0f238ff5 | 1453 | } |
9e866774 MW |
1454 | } |
1455 | ||
a1a5ef99 | 1456 | static void nvme_free_queues(struct nvme_dev *dev, int lowest) |
22404274 KB |
1457 | { |
1458 | int i; | |
1459 | ||
d858e5f0 | 1460 | for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) { |
d858e5f0 | 1461 | dev->ctrl.queue_count--; |
147b27e4 | 1462 | nvme_free_queue(&dev->queues[i]); |
121c7ad4 | 1463 | } |
22404274 KB |
1464 | } |
1465 | ||
4d115420 KB |
1466 | /** |
1467 | * nvme_suspend_queue - put queue into suspended state | |
40581d1a | 1468 | * @nvmeq: queue to suspend |
4d115420 KB |
1469 | */ |
1470 | static int nvme_suspend_queue(struct nvme_queue *nvmeq) | |
b60503ba | 1471 | { |
4e224106 | 1472 | if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags)) |
2b25d981 | 1473 | return 1; |
a09115b2 | 1474 | |
4e224106 | 1475 | /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */ |
d1f06f4a | 1476 | mb(); |
a09115b2 | 1477 | |
4e224106 | 1478 | nvmeq->dev->online_queues--; |
1c63dc66 | 1479 | if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q) |
6ca1d902 | 1480 | nvme_stop_admin_queue(&nvmeq->dev->ctrl); |
7c349dde KB |
1481 | if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags)) |
1482 | pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq); | |
4d115420 KB |
1483 | return 0; |
1484 | } | |
b60503ba | 1485 | |
8fae268b KB |
1486 | static void nvme_suspend_io_queues(struct nvme_dev *dev) |
1487 | { | |
1488 | int i; | |
1489 | ||
1490 | for (i = dev->ctrl.queue_count - 1; i > 0; i--) | |
1491 | nvme_suspend_queue(&dev->queues[i]); | |
1492 | } | |
1493 | ||
a5cdb68c | 1494 | static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown) |
4d115420 | 1495 | { |
147b27e4 | 1496 | struct nvme_queue *nvmeq = &dev->queues[0]; |
4d115420 | 1497 | |
a5cdb68c KB |
1498 | if (shutdown) |
1499 | nvme_shutdown_ctrl(&dev->ctrl); | |
1500 | else | |
b5b05048 | 1501 | nvme_disable_ctrl(&dev->ctrl); |
07836e65 | 1502 | |
bf392a5d | 1503 | nvme_poll_irqdisable(nvmeq); |
b60503ba MW |
1504 | } |
1505 | ||
fa46c6fb KB |
1506 | /* |
1507 | * Called only on a device that has been disabled and after all other threads | |
9210c075 DZ |
1508 | * that can check this device's completion queues have synced, except |
1509 | * nvme_poll(). This is the last chance for the driver to see a natural | |
1510 | * completion before nvme_cancel_request() terminates all incomplete requests. | |
fa46c6fb KB |
1511 | */ |
1512 | static void nvme_reap_pending_cqes(struct nvme_dev *dev) | |
1513 | { | |
fa46c6fb KB |
1514 | int i; |
1515 | ||
9210c075 DZ |
1516 | for (i = dev->ctrl.queue_count - 1; i > 0; i--) { |
1517 | spin_lock(&dev->queues[i].cq_poll_lock); | |
c234a653 | 1518 | nvme_poll_cq(&dev->queues[i], NULL); |
9210c075 DZ |
1519 | spin_unlock(&dev->queues[i].cq_poll_lock); |
1520 | } | |
fa46c6fb KB |
1521 | } |
1522 | ||
8ffaadf7 JD |
1523 | static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues, |
1524 | int entry_size) | |
1525 | { | |
1526 | int q_depth = dev->q_depth; | |
5fd4ce1b | 1527 | unsigned q_size_aligned = roundup(q_depth * entry_size, |
6c3c05b0 | 1528 | NVME_CTRL_PAGE_SIZE); |
8ffaadf7 JD |
1529 | |
1530 | if (q_size_aligned * nr_io_queues > dev->cmb_size) { | |
c45f5c99 | 1531 | u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues); |
4e523547 | 1532 | |
6c3c05b0 | 1533 | mem_per_q = round_down(mem_per_q, NVME_CTRL_PAGE_SIZE); |
c45f5c99 | 1534 | q_depth = div_u64(mem_per_q, entry_size); |
8ffaadf7 JD |
1535 | |
1536 | /* | |
1537 | * Ensure the reduced q_depth is above some threshold where it | |
1538 | * would be better to map queues in system memory with the | |
1539 | * original depth | |
1540 | */ | |
1541 | if (q_depth < 64) | |
1542 | return -ENOMEM; | |
1543 | } | |
1544 | ||
1545 | return q_depth; | |
1546 | } | |
1547 | ||
1548 | static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq, | |
8a1d09a6 | 1549 | int qid) |
8ffaadf7 | 1550 | { |
0f238ff5 LG |
1551 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
1552 | ||
1553 | if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) { | |
8a1d09a6 | 1554 | nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq)); |
bfac8e9f AM |
1555 | if (nvmeq->sq_cmds) { |
1556 | nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev, | |
1557 | nvmeq->sq_cmds); | |
1558 | if (nvmeq->sq_dma_addr) { | |
1559 | set_bit(NVMEQ_SQ_CMB, &nvmeq->flags); | |
1560 | return 0; | |
1561 | } | |
1562 | ||
8a1d09a6 | 1563 | pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq)); |
63223078 | 1564 | } |
0f238ff5 | 1565 | } |
8ffaadf7 | 1566 | |
8a1d09a6 | 1567 | nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq), |
63223078 | 1568 | &nvmeq->sq_dma_addr, GFP_KERNEL); |
815c6704 KB |
1569 | if (!nvmeq->sq_cmds) |
1570 | return -ENOMEM; | |
8ffaadf7 JD |
1571 | return 0; |
1572 | } | |
1573 | ||
a6ff7262 | 1574 | static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth) |
b60503ba | 1575 | { |
147b27e4 | 1576 | struct nvme_queue *nvmeq = &dev->queues[qid]; |
b60503ba | 1577 | |
62314e40 KB |
1578 | if (dev->ctrl.queue_count > qid) |
1579 | return 0; | |
b60503ba | 1580 | |
c1e0cc7e | 1581 | nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES; |
8a1d09a6 BH |
1582 | nvmeq->q_depth = depth; |
1583 | nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq), | |
750afb08 | 1584 | &nvmeq->cq_dma_addr, GFP_KERNEL); |
b60503ba MW |
1585 | if (!nvmeq->cqes) |
1586 | goto free_nvmeq; | |
b60503ba | 1587 | |
8a1d09a6 | 1588 | if (nvme_alloc_sq_cmds(dev, nvmeq, qid)) |
b60503ba MW |
1589 | goto free_cqdma; |
1590 | ||
091b6092 | 1591 | nvmeq->dev = dev; |
1ab0cd69 | 1592 | spin_lock_init(&nvmeq->sq_lock); |
3a7afd8e | 1593 | spin_lock_init(&nvmeq->cq_poll_lock); |
b60503ba | 1594 | nvmeq->cq_head = 0; |
82123460 | 1595 | nvmeq->cq_phase = 1; |
b80d5ccc | 1596 | nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; |
c30341dc | 1597 | nvmeq->qid = qid; |
d858e5f0 | 1598 | dev->ctrl.queue_count++; |
36a7e993 | 1599 | |
147b27e4 | 1600 | return 0; |
b60503ba MW |
1601 | |
1602 | free_cqdma: | |
8a1d09a6 BH |
1603 | dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes, |
1604 | nvmeq->cq_dma_addr); | |
b60503ba | 1605 | free_nvmeq: |
147b27e4 | 1606 | return -ENOMEM; |
b60503ba MW |
1607 | } |
1608 | ||
dca51e78 | 1609 | static int queue_request_irq(struct nvme_queue *nvmeq) |
3001082c | 1610 | { |
0ff199cb CH |
1611 | struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); |
1612 | int nr = nvmeq->dev->ctrl.instance; | |
1613 | ||
1614 | if (use_threaded_interrupts) { | |
1615 | return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check, | |
1616 | nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid); | |
1617 | } else { | |
1618 | return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq, | |
1619 | NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid); | |
1620 | } | |
3001082c MW |
1621 | } |
1622 | ||
22404274 | 1623 | static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) |
b60503ba | 1624 | { |
22404274 | 1625 | struct nvme_dev *dev = nvmeq->dev; |
b60503ba | 1626 | |
22404274 | 1627 | nvmeq->sq_tail = 0; |
38210800 | 1628 | nvmeq->last_sq_tail = 0; |
22404274 KB |
1629 | nvmeq->cq_head = 0; |
1630 | nvmeq->cq_phase = 1; | |
b80d5ccc | 1631 | nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; |
8a1d09a6 | 1632 | memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq)); |
f9f38e33 | 1633 | nvme_dbbuf_init(dev, nvmeq, qid); |
42f61420 | 1634 | dev->online_queues++; |
3a7afd8e | 1635 | wmb(); /* ensure the first interrupt sees the initialization */ |
22404274 KB |
1636 | } |
1637 | ||
e4b9852a CC |
1638 | /* |
1639 | * Try getting shutdown_lock while setting up IO queues. | |
1640 | */ | |
1641 | static int nvme_setup_io_queues_trylock(struct nvme_dev *dev) | |
1642 | { | |
1643 | /* | |
1644 | * Give up if the lock is being held by nvme_dev_disable. | |
1645 | */ | |
1646 | if (!mutex_trylock(&dev->shutdown_lock)) | |
1647 | return -ENODEV; | |
1648 | ||
1649 | /* | |
1650 | * Controller is in wrong state, fail early. | |
1651 | */ | |
1652 | if (dev->ctrl.state != NVME_CTRL_CONNECTING) { | |
1653 | mutex_unlock(&dev->shutdown_lock); | |
1654 | return -ENODEV; | |
1655 | } | |
1656 | ||
1657 | return 0; | |
1658 | } | |
1659 | ||
4b04cc6a | 1660 | static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled) |
22404274 KB |
1661 | { |
1662 | struct nvme_dev *dev = nvmeq->dev; | |
1663 | int result; | |
7c349dde | 1664 | u16 vector = 0; |
3f85d50b | 1665 | |
d1ed6aa1 CH |
1666 | clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); |
1667 | ||
22b55601 KB |
1668 | /* |
1669 | * A queue's vector matches the queue identifier unless the controller | |
1670 | * has only one vector available. | |
1671 | */ | |
4b04cc6a JA |
1672 | if (!polled) |
1673 | vector = dev->num_vecs == 1 ? 0 : qid; | |
1674 | else | |
7c349dde | 1675 | set_bit(NVMEQ_POLLED, &nvmeq->flags); |
4b04cc6a | 1676 | |
a8e3e0bb | 1677 | result = adapter_alloc_cq(dev, qid, nvmeq, vector); |
ded45505 KB |
1678 | if (result) |
1679 | return result; | |
b60503ba MW |
1680 | |
1681 | result = adapter_alloc_sq(dev, qid, nvmeq); | |
1682 | if (result < 0) | |
ded45505 | 1683 | return result; |
c80b36cd | 1684 | if (result) |
b60503ba MW |
1685 | goto release_cq; |
1686 | ||
a8e3e0bb | 1687 | nvmeq->cq_vector = vector; |
4b04cc6a | 1688 | |
e4b9852a CC |
1689 | result = nvme_setup_io_queues_trylock(dev); |
1690 | if (result) | |
1691 | return result; | |
1692 | nvme_init_queue(nvmeq, qid); | |
7c349dde | 1693 | if (!polled) { |
4b04cc6a JA |
1694 | result = queue_request_irq(nvmeq); |
1695 | if (result < 0) | |
1696 | goto release_sq; | |
1697 | } | |
b60503ba | 1698 | |
4e224106 | 1699 | set_bit(NVMEQ_ENABLED, &nvmeq->flags); |
e4b9852a | 1700 | mutex_unlock(&dev->shutdown_lock); |
22404274 | 1701 | return result; |
b60503ba | 1702 | |
a8e3e0bb | 1703 | release_sq: |
f25a2dfc | 1704 | dev->online_queues--; |
e4b9852a | 1705 | mutex_unlock(&dev->shutdown_lock); |
b60503ba | 1706 | adapter_delete_sq(dev, qid); |
a8e3e0bb | 1707 | release_cq: |
b60503ba | 1708 | adapter_delete_cq(dev, qid); |
22404274 | 1709 | return result; |
b60503ba MW |
1710 | } |
1711 | ||
f363b089 | 1712 | static const struct blk_mq_ops nvme_mq_admin_ops = { |
d29ec824 | 1713 | .queue_rq = nvme_queue_rq, |
77f02a7a | 1714 | .complete = nvme_pci_complete_rq, |
a4aea562 | 1715 | .init_hctx = nvme_admin_init_hctx, |
e559398f | 1716 | .init_request = nvme_pci_init_request, |
a4aea562 MB |
1717 | .timeout = nvme_timeout, |
1718 | }; | |
1719 | ||
f363b089 | 1720 | static const struct blk_mq_ops nvme_mq_ops = { |
376f7ef8 | 1721 | .queue_rq = nvme_queue_rq, |
d62cbcf6 | 1722 | .queue_rqs = nvme_queue_rqs, |
376f7ef8 CH |
1723 | .complete = nvme_pci_complete_rq, |
1724 | .commit_rqs = nvme_commit_rqs, | |
1725 | .init_hctx = nvme_init_hctx, | |
e559398f | 1726 | .init_request = nvme_pci_init_request, |
376f7ef8 CH |
1727 | .map_queues = nvme_pci_map_queues, |
1728 | .timeout = nvme_timeout, | |
1729 | .poll = nvme_poll, | |
dabcefab JA |
1730 | }; |
1731 | ||
ea191d2f KB |
1732 | static void nvme_dev_remove_admin(struct nvme_dev *dev) |
1733 | { | |
1c63dc66 | 1734 | if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) { |
69d9a99c KB |
1735 | /* |
1736 | * If the controller was reset during removal, it's possible | |
1737 | * user requests may be waiting on a stopped queue. Start the | |
1738 | * queue to flush these to completion. | |
1739 | */ | |
6ca1d902 | 1740 | nvme_start_admin_queue(&dev->ctrl); |
6f8191fd | 1741 | blk_mq_destroy_queue(dev->ctrl.admin_q); |
96ef1be5 | 1742 | blk_put_queue(dev->ctrl.admin_q); |
ea191d2f KB |
1743 | blk_mq_free_tag_set(&dev->admin_tagset); |
1744 | } | |
1745 | } | |
1746 | ||
f91b727c | 1747 | static int nvme_pci_alloc_admin_tag_set(struct nvme_dev *dev) |
a4aea562 | 1748 | { |
f91b727c | 1749 | struct blk_mq_tag_set *set = &dev->admin_tagset; |
e3e9d50c | 1750 | |
f91b727c CH |
1751 | set->ops = &nvme_mq_admin_ops; |
1752 | set->nr_hw_queues = 1; | |
a4aea562 | 1753 | |
f91b727c CH |
1754 | set->queue_depth = NVME_AQ_MQ_TAG_DEPTH; |
1755 | set->timeout = NVME_ADMIN_TIMEOUT; | |
1756 | set->numa_node = dev->ctrl.numa_node; | |
1757 | set->cmd_size = sizeof(struct nvme_iod); | |
1758 | set->flags = BLK_MQ_F_NO_SCHED; | |
1759 | set->driver_data = dev; | |
a4aea562 | 1760 | |
f91b727c CH |
1761 | if (blk_mq_alloc_tag_set(set)) |
1762 | return -ENOMEM; | |
1763 | dev->ctrl.admin_tagset = set; | |
a4aea562 | 1764 | |
f91b727c CH |
1765 | dev->ctrl.admin_q = blk_mq_init_queue(set); |
1766 | if (IS_ERR(dev->ctrl.admin_q)) { | |
1767 | blk_mq_free_tag_set(set); | |
1768 | dev->ctrl.admin_q = NULL; | |
1769 | return -ENOMEM; | |
1770 | } | |
a4aea562 MB |
1771 | return 0; |
1772 | } | |
1773 | ||
97f6ef64 XY |
1774 | static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) |
1775 | { | |
1776 | return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride); | |
1777 | } | |
1778 | ||
1779 | static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size) | |
1780 | { | |
1781 | struct pci_dev *pdev = to_pci_dev(dev->dev); | |
1782 | ||
1783 | if (size <= dev->bar_mapped_size) | |
1784 | return 0; | |
1785 | if (size > pci_resource_len(pdev, 0)) | |
1786 | return -ENOMEM; | |
1787 | if (dev->bar) | |
1788 | iounmap(dev->bar); | |
1789 | dev->bar = ioremap(pci_resource_start(pdev, 0), size); | |
1790 | if (!dev->bar) { | |
1791 | dev->bar_mapped_size = 0; | |
1792 | return -ENOMEM; | |
1793 | } | |
1794 | dev->bar_mapped_size = size; | |
1795 | dev->dbs = dev->bar + NVME_REG_DBS; | |
1796 | ||
1797 | return 0; | |
1798 | } | |
1799 | ||
01ad0990 | 1800 | static int nvme_pci_configure_admin_queue(struct nvme_dev *dev) |
b60503ba | 1801 | { |
ba47e386 | 1802 | int result; |
b60503ba MW |
1803 | u32 aqa; |
1804 | struct nvme_queue *nvmeq; | |
1805 | ||
97f6ef64 XY |
1806 | result = nvme_remap_bar(dev, db_bar_size(dev, 0)); |
1807 | if (result < 0) | |
1808 | return result; | |
1809 | ||
8ef2074d | 1810 | dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ? |
20d0dfe6 | 1811 | NVME_CAP_NSSRC(dev->ctrl.cap) : 0; |
dfbac8c7 | 1812 | |
7a67cbea CH |
1813 | if (dev->subsystem && |
1814 | (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO)) | |
1815 | writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS); | |
dfbac8c7 | 1816 | |
b5b05048 | 1817 | result = nvme_disable_ctrl(&dev->ctrl); |
ba47e386 MW |
1818 | if (result < 0) |
1819 | return result; | |
b60503ba | 1820 | |
a6ff7262 | 1821 | result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH); |
147b27e4 SG |
1822 | if (result) |
1823 | return result; | |
b60503ba | 1824 | |
635333e4 MG |
1825 | dev->ctrl.numa_node = dev_to_node(dev->dev); |
1826 | ||
147b27e4 | 1827 | nvmeq = &dev->queues[0]; |
b60503ba MW |
1828 | aqa = nvmeq->q_depth - 1; |
1829 | aqa |= aqa << 16; | |
1830 | ||
7a67cbea CH |
1831 | writel(aqa, dev->bar + NVME_REG_AQA); |
1832 | lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ); | |
1833 | lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ); | |
b60503ba | 1834 | |
c0f2f45b | 1835 | result = nvme_enable_ctrl(&dev->ctrl); |
025c557a | 1836 | if (result) |
d4875622 | 1837 | return result; |
a4aea562 | 1838 | |
2b25d981 | 1839 | nvmeq->cq_vector = 0; |
161b8be2 | 1840 | nvme_init_queue(nvmeq, 0); |
dca51e78 | 1841 | result = queue_request_irq(nvmeq); |
758dd7fd | 1842 | if (result) { |
7c349dde | 1843 | dev->online_queues--; |
d4875622 | 1844 | return result; |
758dd7fd | 1845 | } |
025c557a | 1846 | |
4e224106 | 1847 | set_bit(NVMEQ_ENABLED, &nvmeq->flags); |
b60503ba MW |
1848 | return result; |
1849 | } | |
1850 | ||
749941f2 | 1851 | static int nvme_create_io_queues(struct nvme_dev *dev) |
42f61420 | 1852 | { |
4b04cc6a | 1853 | unsigned i, max, rw_queues; |
749941f2 | 1854 | int ret = 0; |
42f61420 | 1855 | |
d858e5f0 | 1856 | for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) { |
a6ff7262 | 1857 | if (nvme_alloc_queue(dev, i, dev->q_depth)) { |
749941f2 | 1858 | ret = -ENOMEM; |
42f61420 | 1859 | break; |
749941f2 CH |
1860 | } |
1861 | } | |
42f61420 | 1862 | |
d858e5f0 | 1863 | max = min(dev->max_qid, dev->ctrl.queue_count - 1); |
e20ba6e1 CH |
1864 | if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) { |
1865 | rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] + | |
1866 | dev->io_queues[HCTX_TYPE_READ]; | |
4b04cc6a JA |
1867 | } else { |
1868 | rw_queues = max; | |
1869 | } | |
1870 | ||
949928c1 | 1871 | for (i = dev->online_queues; i <= max; i++) { |
4b04cc6a JA |
1872 | bool polled = i > rw_queues; |
1873 | ||
1874 | ret = nvme_create_queue(&dev->queues[i], i, polled); | |
d4875622 | 1875 | if (ret) |
42f61420 | 1876 | break; |
27e8166c | 1877 | } |
749941f2 CH |
1878 | |
1879 | /* | |
1880 | * Ignore failing Create SQ/CQ commands, we can continue with less | |
8adb8c14 MI |
1881 | * than the desired amount of queues, and even a controller without |
1882 | * I/O queues can still be used to issue admin commands. This might | |
749941f2 CH |
1883 | * be useful to upgrade a buggy firmware for example. |
1884 | */ | |
1885 | return ret >= 0 ? 0 : ret; | |
b60503ba MW |
1886 | } |
1887 | ||
88de4598 | 1888 | static u64 nvme_cmb_size_unit(struct nvme_dev *dev) |
8ffaadf7 | 1889 | { |
88de4598 CH |
1890 | u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK; |
1891 | ||
1892 | return 1ULL << (12 + 4 * szu); | |
1893 | } | |
1894 | ||
1895 | static u32 nvme_cmb_size(struct nvme_dev *dev) | |
1896 | { | |
1897 | return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK; | |
1898 | } | |
1899 | ||
f65efd6d | 1900 | static void nvme_map_cmb(struct nvme_dev *dev) |
8ffaadf7 | 1901 | { |
88de4598 | 1902 | u64 size, offset; |
8ffaadf7 JD |
1903 | resource_size_t bar_size; |
1904 | struct pci_dev *pdev = to_pci_dev(dev->dev); | |
8969f1f8 | 1905 | int bar; |
8ffaadf7 | 1906 | |
9fe5c59f KB |
1907 | if (dev->cmb_size) |
1908 | return; | |
1909 | ||
20d3bb92 KJ |
1910 | if (NVME_CAP_CMBS(dev->ctrl.cap)) |
1911 | writel(NVME_CMBMSC_CRE, dev->bar + NVME_REG_CMBMSC); | |
1912 | ||
7a67cbea | 1913 | dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ); |
f65efd6d CH |
1914 | if (!dev->cmbsz) |
1915 | return; | |
202021c1 | 1916 | dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC); |
8ffaadf7 | 1917 | |
88de4598 CH |
1918 | size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev); |
1919 | offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc); | |
8969f1f8 CH |
1920 | bar = NVME_CMB_BIR(dev->cmbloc); |
1921 | bar_size = pci_resource_len(pdev, bar); | |
8ffaadf7 JD |
1922 | |
1923 | if (offset > bar_size) | |
f65efd6d | 1924 | return; |
8ffaadf7 | 1925 | |
20d3bb92 KJ |
1926 | /* |
1927 | * Tell the controller about the host side address mapping the CMB, | |
1928 | * and enable CMB decoding for the NVMe 1.4+ scheme: | |
1929 | */ | |
1930 | if (NVME_CAP_CMBS(dev->ctrl.cap)) { | |
1931 | hi_lo_writeq(NVME_CMBMSC_CRE | NVME_CMBMSC_CMSE | | |
1932 | (pci_bus_address(pdev, bar) + offset), | |
1933 | dev->bar + NVME_REG_CMBMSC); | |
1934 | } | |
1935 | ||
8ffaadf7 JD |
1936 | /* |
1937 | * Controllers may support a CMB size larger than their BAR, | |
1938 | * for example, due to being behind a bridge. Reduce the CMB to | |
1939 | * the reported size of the BAR | |
1940 | */ | |
1941 | if (size > bar_size - offset) | |
1942 | size = bar_size - offset; | |
1943 | ||
0f238ff5 LG |
1944 | if (pci_p2pdma_add_resource(pdev, bar, size, offset)) { |
1945 | dev_warn(dev->ctrl.device, | |
1946 | "failed to register the CMB\n"); | |
f65efd6d | 1947 | return; |
0f238ff5 LG |
1948 | } |
1949 | ||
8ffaadf7 | 1950 | dev->cmb_size = size; |
0f238ff5 LG |
1951 | dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS); |
1952 | ||
1953 | if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) == | |
1954 | (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) | |
1955 | pci_p2pmem_publish(pdev, true); | |
8ffaadf7 JD |
1956 | } |
1957 | ||
87ad72a5 CH |
1958 | static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits) |
1959 | { | |
6c3c05b0 | 1960 | u32 host_mem_size = dev->host_mem_size >> NVME_CTRL_PAGE_SHIFT; |
4033f35d | 1961 | u64 dma_addr = dev->host_mem_descs_dma; |
f66e2804 | 1962 | struct nvme_command c = { }; |
87ad72a5 CH |
1963 | int ret; |
1964 | ||
87ad72a5 CH |
1965 | c.features.opcode = nvme_admin_set_features; |
1966 | c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF); | |
1967 | c.features.dword11 = cpu_to_le32(bits); | |
6c3c05b0 | 1968 | c.features.dword12 = cpu_to_le32(host_mem_size); |
87ad72a5 CH |
1969 | c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr)); |
1970 | c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr)); | |
1971 | c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs); | |
1972 | ||
1973 | ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); | |
1974 | if (ret) { | |
1975 | dev_warn(dev->ctrl.device, | |
1976 | "failed to set host mem (err %d, flags %#x).\n", | |
1977 | ret, bits); | |
a5df5e79 KB |
1978 | } else |
1979 | dev->hmb = bits & NVME_HOST_MEM_ENABLE; | |
1980 | ||
87ad72a5 CH |
1981 | return ret; |
1982 | } | |
1983 | ||
1984 | static void nvme_free_host_mem(struct nvme_dev *dev) | |
1985 | { | |
1986 | int i; | |
1987 | ||
1988 | for (i = 0; i < dev->nr_host_mem_descs; i++) { | |
1989 | struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i]; | |
6c3c05b0 | 1990 | size_t size = le32_to_cpu(desc->size) * NVME_CTRL_PAGE_SIZE; |
87ad72a5 | 1991 | |
cc667f6d LD |
1992 | dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i], |
1993 | le64_to_cpu(desc->addr), | |
1994 | DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); | |
87ad72a5 CH |
1995 | } |
1996 | ||
1997 | kfree(dev->host_mem_desc_bufs); | |
1998 | dev->host_mem_desc_bufs = NULL; | |
4033f35d CH |
1999 | dma_free_coherent(dev->dev, |
2000 | dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs), | |
2001 | dev->host_mem_descs, dev->host_mem_descs_dma); | |
87ad72a5 | 2002 | dev->host_mem_descs = NULL; |
7e5dd57e | 2003 | dev->nr_host_mem_descs = 0; |
87ad72a5 CH |
2004 | } |
2005 | ||
92dc6895 CH |
2006 | static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred, |
2007 | u32 chunk_size) | |
9d713c2b | 2008 | { |
87ad72a5 | 2009 | struct nvme_host_mem_buf_desc *descs; |
92dc6895 | 2010 | u32 max_entries, len; |
4033f35d | 2011 | dma_addr_t descs_dma; |
2ee0e4ed | 2012 | int i = 0; |
87ad72a5 | 2013 | void **bufs; |
6fbcde66 | 2014 | u64 size, tmp; |
87ad72a5 | 2015 | |
87ad72a5 CH |
2016 | tmp = (preferred + chunk_size - 1); |
2017 | do_div(tmp, chunk_size); | |
2018 | max_entries = tmp; | |
044a9df1 CH |
2019 | |
2020 | if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries) | |
2021 | max_entries = dev->ctrl.hmmaxd; | |
2022 | ||
750afb08 LC |
2023 | descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs), |
2024 | &descs_dma, GFP_KERNEL); | |
87ad72a5 CH |
2025 | if (!descs) |
2026 | goto out; | |
2027 | ||
2028 | bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL); | |
2029 | if (!bufs) | |
2030 | goto out_free_descs; | |
2031 | ||
244a8fe4 | 2032 | for (size = 0; size < preferred && i < max_entries; size += len) { |
87ad72a5 CH |
2033 | dma_addr_t dma_addr; |
2034 | ||
50cdb7c6 | 2035 | len = min_t(u64, chunk_size, preferred - size); |
87ad72a5 CH |
2036 | bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL, |
2037 | DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); | |
2038 | if (!bufs[i]) | |
2039 | break; | |
2040 | ||
2041 | descs[i].addr = cpu_to_le64(dma_addr); | |
6c3c05b0 | 2042 | descs[i].size = cpu_to_le32(len / NVME_CTRL_PAGE_SIZE); |
87ad72a5 CH |
2043 | i++; |
2044 | } | |
2045 | ||
92dc6895 | 2046 | if (!size) |
87ad72a5 | 2047 | goto out_free_bufs; |
87ad72a5 | 2048 | |
87ad72a5 CH |
2049 | dev->nr_host_mem_descs = i; |
2050 | dev->host_mem_size = size; | |
2051 | dev->host_mem_descs = descs; | |
4033f35d | 2052 | dev->host_mem_descs_dma = descs_dma; |
87ad72a5 CH |
2053 | dev->host_mem_desc_bufs = bufs; |
2054 | return 0; | |
2055 | ||
2056 | out_free_bufs: | |
2057 | while (--i >= 0) { | |
6c3c05b0 | 2058 | size_t size = le32_to_cpu(descs[i].size) * NVME_CTRL_PAGE_SIZE; |
87ad72a5 | 2059 | |
cc667f6d LD |
2060 | dma_free_attrs(dev->dev, size, bufs[i], |
2061 | le64_to_cpu(descs[i].addr), | |
2062 | DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); | |
87ad72a5 CH |
2063 | } |
2064 | ||
2065 | kfree(bufs); | |
2066 | out_free_descs: | |
4033f35d CH |
2067 | dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs, |
2068 | descs_dma); | |
87ad72a5 | 2069 | out: |
87ad72a5 CH |
2070 | dev->host_mem_descs = NULL; |
2071 | return -ENOMEM; | |
2072 | } | |
2073 | ||
92dc6895 CH |
2074 | static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred) |
2075 | { | |
9dc54a0d CK |
2076 | u64 min_chunk = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES); |
2077 | u64 hmminds = max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2); | |
2078 | u64 chunk_size; | |
92dc6895 CH |
2079 | |
2080 | /* start big and work our way down */ | |
9dc54a0d | 2081 | for (chunk_size = min_chunk; chunk_size >= hmminds; chunk_size /= 2) { |
92dc6895 CH |
2082 | if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) { |
2083 | if (!min || dev->host_mem_size >= min) | |
2084 | return 0; | |
2085 | nvme_free_host_mem(dev); | |
2086 | } | |
2087 | } | |
2088 | ||
2089 | return -ENOMEM; | |
2090 | } | |
2091 | ||
9620cfba | 2092 | static int nvme_setup_host_mem(struct nvme_dev *dev) |
87ad72a5 CH |
2093 | { |
2094 | u64 max = (u64)max_host_mem_size_mb * SZ_1M; | |
2095 | u64 preferred = (u64)dev->ctrl.hmpre * 4096; | |
2096 | u64 min = (u64)dev->ctrl.hmmin * 4096; | |
2097 | u32 enable_bits = NVME_HOST_MEM_ENABLE; | |
6fbcde66 | 2098 | int ret; |
87ad72a5 CH |
2099 | |
2100 | preferred = min(preferred, max); | |
2101 | if (min > max) { | |
2102 | dev_warn(dev->ctrl.device, | |
2103 | "min host memory (%lld MiB) above limit (%d MiB).\n", | |
2104 | min >> ilog2(SZ_1M), max_host_mem_size_mb); | |
2105 | nvme_free_host_mem(dev); | |
9620cfba | 2106 | return 0; |
87ad72a5 CH |
2107 | } |
2108 | ||
2109 | /* | |
2110 | * If we already have a buffer allocated check if we can reuse it. | |
2111 | */ | |
2112 | if (dev->host_mem_descs) { | |
2113 | if (dev->host_mem_size >= min) | |
2114 | enable_bits |= NVME_HOST_MEM_RETURN; | |
2115 | else | |
2116 | nvme_free_host_mem(dev); | |
2117 | } | |
2118 | ||
2119 | if (!dev->host_mem_descs) { | |
92dc6895 CH |
2120 | if (nvme_alloc_host_mem(dev, min, preferred)) { |
2121 | dev_warn(dev->ctrl.device, | |
2122 | "failed to allocate host memory buffer.\n"); | |
9620cfba | 2123 | return 0; /* controller must work without HMB */ |
92dc6895 CH |
2124 | } |
2125 | ||
2126 | dev_info(dev->ctrl.device, | |
2127 | "allocated %lld MiB host memory buffer.\n", | |
2128 | dev->host_mem_size >> ilog2(SZ_1M)); | |
87ad72a5 CH |
2129 | } |
2130 | ||
9620cfba CH |
2131 | ret = nvme_set_host_mem(dev, enable_bits); |
2132 | if (ret) | |
87ad72a5 | 2133 | nvme_free_host_mem(dev); |
9620cfba | 2134 | return ret; |
9d713c2b KB |
2135 | } |
2136 | ||
0521905e KB |
2137 | static ssize_t cmb_show(struct device *dev, struct device_attribute *attr, |
2138 | char *buf) | |
2139 | { | |
2140 | struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); | |
2141 | ||
2142 | return sysfs_emit(buf, "cmbloc : x%08x\ncmbsz : x%08x\n", | |
2143 | ndev->cmbloc, ndev->cmbsz); | |
2144 | } | |
2145 | static DEVICE_ATTR_RO(cmb); | |
2146 | ||
1751e97a KB |
2147 | static ssize_t cmbloc_show(struct device *dev, struct device_attribute *attr, |
2148 | char *buf) | |
2149 | { | |
2150 | struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); | |
2151 | ||
2152 | return sysfs_emit(buf, "%u\n", ndev->cmbloc); | |
2153 | } | |
2154 | static DEVICE_ATTR_RO(cmbloc); | |
2155 | ||
2156 | static ssize_t cmbsz_show(struct device *dev, struct device_attribute *attr, | |
2157 | char *buf) | |
2158 | { | |
2159 | struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); | |
2160 | ||
2161 | return sysfs_emit(buf, "%u\n", ndev->cmbsz); | |
2162 | } | |
2163 | static DEVICE_ATTR_RO(cmbsz); | |
2164 | ||
a5df5e79 KB |
2165 | static ssize_t hmb_show(struct device *dev, struct device_attribute *attr, |
2166 | char *buf) | |
2167 | { | |
2168 | struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); | |
2169 | ||
2170 | return sysfs_emit(buf, "%d\n", ndev->hmb); | |
2171 | } | |
2172 | ||
2173 | static ssize_t hmb_store(struct device *dev, struct device_attribute *attr, | |
2174 | const char *buf, size_t count) | |
2175 | { | |
2176 | struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); | |
2177 | bool new; | |
2178 | int ret; | |
2179 | ||
2180 | if (strtobool(buf, &new) < 0) | |
2181 | return -EINVAL; | |
2182 | ||
2183 | if (new == ndev->hmb) | |
2184 | return count; | |
2185 | ||
2186 | if (new) { | |
2187 | ret = nvme_setup_host_mem(ndev); | |
2188 | } else { | |
2189 | ret = nvme_set_host_mem(ndev, 0); | |
2190 | if (!ret) | |
2191 | nvme_free_host_mem(ndev); | |
2192 | } | |
2193 | ||
2194 | if (ret < 0) | |
2195 | return ret; | |
2196 | ||
2197 | return count; | |
2198 | } | |
2199 | static DEVICE_ATTR_RW(hmb); | |
2200 | ||
0521905e KB |
2201 | static umode_t nvme_pci_attrs_are_visible(struct kobject *kobj, |
2202 | struct attribute *a, int n) | |
2203 | { | |
2204 | struct nvme_ctrl *ctrl = | |
2205 | dev_get_drvdata(container_of(kobj, struct device, kobj)); | |
2206 | struct nvme_dev *dev = to_nvme_dev(ctrl); | |
2207 | ||
1751e97a KB |
2208 | if (a == &dev_attr_cmb.attr || |
2209 | a == &dev_attr_cmbloc.attr || | |
2210 | a == &dev_attr_cmbsz.attr) { | |
2211 | if (!dev->cmbsz) | |
2212 | return 0; | |
2213 | } | |
a5df5e79 KB |
2214 | if (a == &dev_attr_hmb.attr && !ctrl->hmpre) |
2215 | return 0; | |
2216 | ||
0521905e KB |
2217 | return a->mode; |
2218 | } | |
2219 | ||
2220 | static struct attribute *nvme_pci_attrs[] = { | |
2221 | &dev_attr_cmb.attr, | |
1751e97a KB |
2222 | &dev_attr_cmbloc.attr, |
2223 | &dev_attr_cmbsz.attr, | |
a5df5e79 | 2224 | &dev_attr_hmb.attr, |
0521905e KB |
2225 | NULL, |
2226 | }; | |
2227 | ||
86adbf0c | 2228 | static const struct attribute_group nvme_pci_dev_attrs_group = { |
0521905e KB |
2229 | .attrs = nvme_pci_attrs, |
2230 | .is_visible = nvme_pci_attrs_are_visible, | |
2231 | }; | |
2232 | ||
86adbf0c CH |
2233 | static const struct attribute_group *nvme_pci_dev_attr_groups[] = { |
2234 | &nvme_dev_attrs_group, | |
2235 | &nvme_pci_dev_attrs_group, | |
2236 | NULL, | |
2237 | }; | |
2238 | ||
612b7286 ML |
2239 | /* |
2240 | * nirqs is the number of interrupts available for write and read | |
2241 | * queues. The core already reserved an interrupt for the admin queue. | |
2242 | */ | |
2243 | static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs) | |
3b6592f7 | 2244 | { |
612b7286 | 2245 | struct nvme_dev *dev = affd->priv; |
2a5bcfdd | 2246 | unsigned int nr_read_queues, nr_write_queues = dev->nr_write_queues; |
3b6592f7 JA |
2247 | |
2248 | /* | |
ee0d96d3 | 2249 | * If there is no interrupt available for queues, ensure that |
612b7286 ML |
2250 | * the default queue is set to 1. The affinity set size is |
2251 | * also set to one, but the irq core ignores it for this case. | |
2252 | * | |
2253 | * If only one interrupt is available or 'write_queue' == 0, combine | |
2254 | * write and read queues. | |
2255 | * | |
2256 | * If 'write_queues' > 0, ensure it leaves room for at least one read | |
2257 | * queue. | |
3b6592f7 | 2258 | */ |
612b7286 ML |
2259 | if (!nrirqs) { |
2260 | nrirqs = 1; | |
2261 | nr_read_queues = 0; | |
2a5bcfdd | 2262 | } else if (nrirqs == 1 || !nr_write_queues) { |
612b7286 | 2263 | nr_read_queues = 0; |
2a5bcfdd | 2264 | } else if (nr_write_queues >= nrirqs) { |
612b7286 | 2265 | nr_read_queues = 1; |
3b6592f7 | 2266 | } else { |
2a5bcfdd | 2267 | nr_read_queues = nrirqs - nr_write_queues; |
3b6592f7 | 2268 | } |
612b7286 ML |
2269 | |
2270 | dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues; | |
2271 | affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues; | |
2272 | dev->io_queues[HCTX_TYPE_READ] = nr_read_queues; | |
2273 | affd->set_size[HCTX_TYPE_READ] = nr_read_queues; | |
2274 | affd->nr_sets = nr_read_queues ? 2 : 1; | |
3b6592f7 JA |
2275 | } |
2276 | ||
6451fe73 | 2277 | static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues) |
3b6592f7 JA |
2278 | { |
2279 | struct pci_dev *pdev = to_pci_dev(dev->dev); | |
3b6592f7 | 2280 | struct irq_affinity affd = { |
9cfef55b | 2281 | .pre_vectors = 1, |
612b7286 ML |
2282 | .calc_sets = nvme_calc_irq_sets, |
2283 | .priv = dev, | |
3b6592f7 | 2284 | }; |
21cc2f3f | 2285 | unsigned int irq_queues, poll_queues; |
6451fe73 JA |
2286 | |
2287 | /* | |
21cc2f3f JX |
2288 | * Poll queues don't need interrupts, but we need at least one I/O queue |
2289 | * left over for non-polled I/O. | |
6451fe73 | 2290 | */ |
21cc2f3f JX |
2291 | poll_queues = min(dev->nr_poll_queues, nr_io_queues - 1); |
2292 | dev->io_queues[HCTX_TYPE_POLL] = poll_queues; | |
3b6592f7 | 2293 | |
21cc2f3f JX |
2294 | /* |
2295 | * Initialize for the single interrupt case, will be updated in | |
2296 | * nvme_calc_irq_sets(). | |
2297 | */ | |
612b7286 ML |
2298 | dev->io_queues[HCTX_TYPE_DEFAULT] = 1; |
2299 | dev->io_queues[HCTX_TYPE_READ] = 0; | |
3b6592f7 | 2300 | |
66341331 | 2301 | /* |
21cc2f3f JX |
2302 | * We need interrupts for the admin queue and each non-polled I/O queue, |
2303 | * but some Apple controllers require all queues to use the first | |
2304 | * vector. | |
66341331 | 2305 | */ |
21cc2f3f JX |
2306 | irq_queues = 1; |
2307 | if (!(dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR)) | |
2308 | irq_queues += (nr_io_queues - poll_queues); | |
612b7286 ML |
2309 | return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues, |
2310 | PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd); | |
3b6592f7 JA |
2311 | } |
2312 | ||
8fae268b KB |
2313 | static void nvme_disable_io_queues(struct nvme_dev *dev) |
2314 | { | |
2315 | if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq)) | |
2316 | __nvme_disable_io_queues(dev, nvme_admin_delete_cq); | |
2317 | } | |
2318 | ||
2a5bcfdd WZ |
2319 | static unsigned int nvme_max_io_queues(struct nvme_dev *dev) |
2320 | { | |
e3aef095 NS |
2321 | /* |
2322 | * If tags are shared with admin queue (Apple bug), then | |
2323 | * make sure we only use one IO queue. | |
2324 | */ | |
2325 | if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) | |
2326 | return 1; | |
2a5bcfdd WZ |
2327 | return num_possible_cpus() + dev->nr_write_queues + dev->nr_poll_queues; |
2328 | } | |
2329 | ||
8d85fce7 | 2330 | static int nvme_setup_io_queues(struct nvme_dev *dev) |
b60503ba | 2331 | { |
147b27e4 | 2332 | struct nvme_queue *adminq = &dev->queues[0]; |
e75ec752 | 2333 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
2a5bcfdd | 2334 | unsigned int nr_io_queues; |
97f6ef64 | 2335 | unsigned long size; |
2a5bcfdd | 2336 | int result; |
b60503ba | 2337 | |
2a5bcfdd WZ |
2338 | /* |
2339 | * Sample the module parameters once at reset time so that we have | |
2340 | * stable values to work with. | |
2341 | */ | |
2342 | dev->nr_write_queues = write_queues; | |
2343 | dev->nr_poll_queues = poll_queues; | |
d38e9f04 | 2344 | |
e3aef095 | 2345 | nr_io_queues = dev->nr_allocated_queues - 1; |
9a0be7ab CH |
2346 | result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues); |
2347 | if (result < 0) | |
1b23484b | 2348 | return result; |
9a0be7ab | 2349 | |
f5fa90dc | 2350 | if (nr_io_queues == 0) |
a5229050 | 2351 | return 0; |
53dc180e | 2352 | |
e4b9852a CC |
2353 | /* |
2354 | * Free IRQ resources as soon as NVMEQ_ENABLED bit transitions | |
2355 | * from set to unset. If there is a window to it is truely freed, | |
2356 | * pci_free_irq_vectors() jumping into this window will crash. | |
2357 | * And take lock to avoid racing with pci_free_irq_vectors() in | |
2358 | * nvme_dev_disable() path. | |
2359 | */ | |
2360 | result = nvme_setup_io_queues_trylock(dev); | |
2361 | if (result) | |
2362 | return result; | |
2363 | if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags)) | |
2364 | pci_free_irq(pdev, 0, adminq); | |
b60503ba | 2365 | |
0f238ff5 | 2366 | if (dev->cmb_use_sqes) { |
8ffaadf7 JD |
2367 | result = nvme_cmb_qdepth(dev, nr_io_queues, |
2368 | sizeof(struct nvme_command)); | |
2369 | if (result > 0) | |
2370 | dev->q_depth = result; | |
2371 | else | |
0f238ff5 | 2372 | dev->cmb_use_sqes = false; |
8ffaadf7 JD |
2373 | } |
2374 | ||
97f6ef64 XY |
2375 | do { |
2376 | size = db_bar_size(dev, nr_io_queues); | |
2377 | result = nvme_remap_bar(dev, size); | |
2378 | if (!result) | |
2379 | break; | |
e4b9852a CC |
2380 | if (!--nr_io_queues) { |
2381 | result = -ENOMEM; | |
2382 | goto out_unlock; | |
2383 | } | |
97f6ef64 XY |
2384 | } while (1); |
2385 | adminq->q_db = dev->dbs; | |
f1938f6e | 2386 | |
8fae268b | 2387 | retry: |
9d713c2b | 2388 | /* Deregister the admin queue's interrupt */ |
e4b9852a CC |
2389 | if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags)) |
2390 | pci_free_irq(pdev, 0, adminq); | |
9d713c2b | 2391 | |
e32efbfc JA |
2392 | /* |
2393 | * If we enable msix early due to not intx, disable it again before | |
2394 | * setting up the full range we need. | |
2395 | */ | |
dca51e78 | 2396 | pci_free_irq_vectors(pdev); |
3b6592f7 JA |
2397 | |
2398 | result = nvme_setup_irqs(dev, nr_io_queues); | |
e4b9852a CC |
2399 | if (result <= 0) { |
2400 | result = -EIO; | |
2401 | goto out_unlock; | |
2402 | } | |
3b6592f7 | 2403 | |
22b55601 | 2404 | dev->num_vecs = result; |
4b04cc6a | 2405 | result = max(result - 1, 1); |
e20ba6e1 | 2406 | dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL]; |
fa08a396 | 2407 | |
063a8096 MW |
2408 | /* |
2409 | * Should investigate if there's a performance win from allocating | |
2410 | * more queues than interrupt vectors; it might allow the submission | |
2411 | * path to scale better, even if the receive path is limited by the | |
2412 | * number of interrupts. | |
2413 | */ | |
dca51e78 | 2414 | result = queue_request_irq(adminq); |
7c349dde | 2415 | if (result) |
e4b9852a | 2416 | goto out_unlock; |
4e224106 | 2417 | set_bit(NVMEQ_ENABLED, &adminq->flags); |
e4b9852a | 2418 | mutex_unlock(&dev->shutdown_lock); |
8fae268b KB |
2419 | |
2420 | result = nvme_create_io_queues(dev); | |
2421 | if (result || dev->online_queues < 2) | |
2422 | return result; | |
2423 | ||
2424 | if (dev->online_queues - 1 < dev->max_qid) { | |
2425 | nr_io_queues = dev->online_queues - 1; | |
2426 | nvme_disable_io_queues(dev); | |
e4b9852a CC |
2427 | result = nvme_setup_io_queues_trylock(dev); |
2428 | if (result) | |
2429 | return result; | |
8fae268b KB |
2430 | nvme_suspend_io_queues(dev); |
2431 | goto retry; | |
2432 | } | |
2433 | dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n", | |
2434 | dev->io_queues[HCTX_TYPE_DEFAULT], | |
2435 | dev->io_queues[HCTX_TYPE_READ], | |
2436 | dev->io_queues[HCTX_TYPE_POLL]); | |
2437 | return 0; | |
e4b9852a CC |
2438 | out_unlock: |
2439 | mutex_unlock(&dev->shutdown_lock); | |
2440 | return result; | |
b60503ba MW |
2441 | } |
2442 | ||
de671d61 JA |
2443 | static enum rq_end_io_ret nvme_del_queue_end(struct request *req, |
2444 | blk_status_t error) | |
a5768aa8 | 2445 | { |
db3cbfff | 2446 | struct nvme_queue *nvmeq = req->end_io_data; |
b5875222 | 2447 | |
db3cbfff | 2448 | blk_mq_free_request(req); |
d1ed6aa1 | 2449 | complete(&nvmeq->delete_done); |
de671d61 | 2450 | return RQ_END_IO_NONE; |
a5768aa8 KB |
2451 | } |
2452 | ||
de671d61 JA |
2453 | static enum rq_end_io_ret nvme_del_cq_end(struct request *req, |
2454 | blk_status_t error) | |
a5768aa8 | 2455 | { |
db3cbfff | 2456 | struct nvme_queue *nvmeq = req->end_io_data; |
a5768aa8 | 2457 | |
d1ed6aa1 CH |
2458 | if (error) |
2459 | set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); | |
db3cbfff | 2460 | |
de671d61 | 2461 | return nvme_del_queue_end(req, error); |
a5768aa8 KB |
2462 | } |
2463 | ||
db3cbfff | 2464 | static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode) |
bda4e0fb | 2465 | { |
db3cbfff KB |
2466 | struct request_queue *q = nvmeq->dev->ctrl.admin_q; |
2467 | struct request *req; | |
f66e2804 | 2468 | struct nvme_command cmd = { }; |
bda4e0fb | 2469 | |
db3cbfff KB |
2470 | cmd.delete_queue.opcode = opcode; |
2471 | cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid); | |
bda4e0fb | 2472 | |
e559398f | 2473 | req = blk_mq_alloc_request(q, nvme_req_op(&cmd), BLK_MQ_REQ_NOWAIT); |
db3cbfff KB |
2474 | if (IS_ERR(req)) |
2475 | return PTR_ERR(req); | |
e559398f | 2476 | nvme_init_request(req, &cmd); |
bda4e0fb | 2477 | |
e2e53086 CH |
2478 | if (opcode == nvme_admin_delete_cq) |
2479 | req->end_io = nvme_del_cq_end; | |
2480 | else | |
2481 | req->end_io = nvme_del_queue_end; | |
db3cbfff KB |
2482 | req->end_io_data = nvmeq; |
2483 | ||
d1ed6aa1 | 2484 | init_completion(&nvmeq->delete_done); |
128126a7 | 2485 | req->rq_flags |= RQF_QUIET; |
e2e53086 | 2486 | blk_execute_rq_nowait(req, false); |
db3cbfff | 2487 | return 0; |
bda4e0fb KB |
2488 | } |
2489 | ||
8fae268b | 2490 | static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode) |
a5768aa8 | 2491 | { |
5271edd4 | 2492 | int nr_queues = dev->online_queues - 1, sent = 0; |
db3cbfff | 2493 | unsigned long timeout; |
a5768aa8 | 2494 | |
db3cbfff | 2495 | retry: |
dc96f938 | 2496 | timeout = NVME_ADMIN_TIMEOUT; |
5271edd4 CH |
2497 | while (nr_queues > 0) { |
2498 | if (nvme_delete_queue(&dev->queues[nr_queues], opcode)) | |
2499 | break; | |
2500 | nr_queues--; | |
2501 | sent++; | |
db3cbfff | 2502 | } |
d1ed6aa1 CH |
2503 | while (sent) { |
2504 | struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent]; | |
2505 | ||
2506 | timeout = wait_for_completion_io_timeout(&nvmeq->delete_done, | |
5271edd4 CH |
2507 | timeout); |
2508 | if (timeout == 0) | |
2509 | return false; | |
d1ed6aa1 | 2510 | |
d1ed6aa1 | 2511 | sent--; |
5271edd4 CH |
2512 | if (nr_queues) |
2513 | goto retry; | |
2514 | } | |
2515 | return true; | |
a5768aa8 KB |
2516 | } |
2517 | ||
2455a4b7 | 2518 | static void nvme_pci_alloc_tag_set(struct nvme_dev *dev) |
b60503ba | 2519 | { |
2455a4b7 | 2520 | struct blk_mq_tag_set * set = &dev->tagset; |
2b1b7e78 JW |
2521 | int ret; |
2522 | ||
2455a4b7 CH |
2523 | set->ops = &nvme_mq_ops; |
2524 | set->nr_hw_queues = dev->online_queues - 1; | |
6ee742fa KB |
2525 | set->nr_maps = 1; |
2526 | if (dev->io_queues[HCTX_TYPE_READ]) | |
2527 | set->nr_maps = 2; | |
2455a4b7 | 2528 | if (dev->io_queues[HCTX_TYPE_POLL]) |
6ee742fa | 2529 | set->nr_maps = 3; |
2455a4b7 CH |
2530 | set->timeout = NVME_IO_TIMEOUT; |
2531 | set->numa_node = dev->ctrl.numa_node; | |
2532 | set->queue_depth = min_t(unsigned, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1; | |
2533 | set->cmd_size = sizeof(struct nvme_iod); | |
2534 | set->flags = BLK_MQ_F_SHOULD_MERGE; | |
2535 | set->driver_data = dev; | |
d38e9f04 | 2536 | |
2455a4b7 CH |
2537 | /* |
2538 | * Some Apple controllers requires tags to be unique | |
2539 | * across admin and IO queue, so reserve the first 32 | |
2540 | * tags of the IO queue. | |
2541 | */ | |
2542 | if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) | |
2543 | set->reserved_tags = NVME_AQ_DEPTH; | |
949928c1 | 2544 | |
2455a4b7 CH |
2545 | ret = blk_mq_alloc_tag_set(set); |
2546 | if (ret) { | |
2547 | dev_warn(dev->ctrl.device, | |
2548 | "IO queues tagset allocation failed %d\n", ret); | |
2549 | return; | |
ffe7704d | 2550 | } |
2455a4b7 CH |
2551 | dev->ctrl.tagset = set; |
2552 | } | |
949928c1 | 2553 | |
2455a4b7 CH |
2554 | static void nvme_pci_update_nr_queues(struct nvme_dev *dev) |
2555 | { | |
2556 | blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1); | |
2557 | /* free previously allocated queues that are no longer usable */ | |
2558 | nvme_free_queues(dev, dev->online_queues); | |
b60503ba MW |
2559 | } |
2560 | ||
b00a726a | 2561 | static int nvme_pci_enable(struct nvme_dev *dev) |
0877cb0d | 2562 | { |
b00a726a | 2563 | int result = -ENOMEM; |
e75ec752 | 2564 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
4bdf2603 | 2565 | int dma_address_bits = 64; |
0877cb0d KB |
2566 | |
2567 | if (pci_enable_device_mem(pdev)) | |
2568 | return result; | |
2569 | ||
0877cb0d | 2570 | pci_set_master(pdev); |
0877cb0d | 2571 | |
4bdf2603 FS |
2572 | if (dev->ctrl.quirks & NVME_QUIRK_DMA_ADDRESS_BITS_48) |
2573 | dma_address_bits = 48; | |
2574 | if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(dma_address_bits))) | |
052d0efa | 2575 | goto disable; |
0877cb0d | 2576 | |
7a67cbea | 2577 | if (readl(dev->bar + NVME_REG_CSTS) == -1) { |
0e53d180 | 2578 | result = -ENODEV; |
b00a726a | 2579 | goto disable; |
0e53d180 | 2580 | } |
e32efbfc JA |
2581 | |
2582 | /* | |
a5229050 KB |
2583 | * Some devices and/or platforms don't advertise or work with INTx |
2584 | * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll | |
2585 | * adjust this later. | |
e32efbfc | 2586 | */ |
dca51e78 CH |
2587 | result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); |
2588 | if (result < 0) | |
2589 | return result; | |
e32efbfc | 2590 | |
20d0dfe6 | 2591 | dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP); |
7a67cbea | 2592 | |
7442ddce | 2593 | dev->q_depth = min_t(u32, NVME_CAP_MQES(dev->ctrl.cap) + 1, |
b27c1e68 | 2594 | io_queue_depth); |
aa22c8e6 | 2595 | dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */ |
20d0dfe6 | 2596 | dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap); |
7a67cbea | 2597 | dev->dbs = dev->bar + 4096; |
1f390c1f | 2598 | |
66341331 BH |
2599 | /* |
2600 | * Some Apple controllers require a non-standard SQE size. | |
2601 | * Interestingly they also seem to ignore the CC:IOSQES register | |
2602 | * so we don't bother updating it here. | |
2603 | */ | |
2604 | if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES) | |
2605 | dev->io_sqes = 7; | |
2606 | else | |
2607 | dev->io_sqes = NVME_NVM_IOSQES; | |
1f390c1f SG |
2608 | |
2609 | /* | |
2610 | * Temporary fix for the Apple controller found in the MacBook8,1 and | |
2611 | * some MacBook7,1 to avoid controller resets and data loss. | |
2612 | */ | |
2613 | if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) { | |
2614 | dev->q_depth = 2; | |
9bdcfb10 CH |
2615 | dev_warn(dev->ctrl.device, "detected Apple NVMe controller, " |
2616 | "set queue depth=%u to work around controller resets\n", | |
1f390c1f | 2617 | dev->q_depth); |
d554b5e1 MP |
2618 | } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG && |
2619 | (pdev->device == 0xa821 || pdev->device == 0xa822) && | |
20d0dfe6 | 2620 | NVME_CAP_MQES(dev->ctrl.cap) == 0) { |
d554b5e1 MP |
2621 | dev->q_depth = 64; |
2622 | dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, " | |
2623 | "set queue depth=%u\n", dev->q_depth); | |
1f390c1f SG |
2624 | } |
2625 | ||
d38e9f04 BH |
2626 | /* |
2627 | * Controllers with the shared tags quirk need the IO queue to be | |
2628 | * big enough so that we get 32 tags for the admin queue | |
2629 | */ | |
2630 | if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) && | |
2631 | (dev->q_depth < (NVME_AQ_DEPTH + 2))) { | |
2632 | dev->q_depth = NVME_AQ_DEPTH + 2; | |
2633 | dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n", | |
2634 | dev->q_depth); | |
2635 | } | |
2636 | ||
2637 | ||
f65efd6d | 2638 | nvme_map_cmb(dev); |
202021c1 | 2639 | |
a0a3408e KB |
2640 | pci_enable_pcie_error_reporting(pdev); |
2641 | pci_save_state(pdev); | |
0877cb0d KB |
2642 | return 0; |
2643 | ||
2644 | disable: | |
0877cb0d KB |
2645 | pci_disable_device(pdev); |
2646 | return result; | |
2647 | } | |
2648 | ||
2649 | static void nvme_dev_unmap(struct nvme_dev *dev) | |
b00a726a KB |
2650 | { |
2651 | if (dev->bar) | |
2652 | iounmap(dev->bar); | |
a1f447b3 | 2653 | pci_release_mem_regions(to_pci_dev(dev->dev)); |
b00a726a KB |
2654 | } |
2655 | ||
2656 | static void nvme_pci_disable(struct nvme_dev *dev) | |
0877cb0d | 2657 | { |
e75ec752 CH |
2658 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
2659 | ||
dca51e78 | 2660 | pci_free_irq_vectors(pdev); |
0877cb0d | 2661 | |
a0a3408e KB |
2662 | if (pci_is_enabled(pdev)) { |
2663 | pci_disable_pcie_error_reporting(pdev); | |
e75ec752 | 2664 | pci_disable_device(pdev); |
4d115420 | 2665 | } |
4d115420 KB |
2666 | } |
2667 | ||
a5cdb68c | 2668 | static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown) |
b60503ba | 2669 | { |
e43269e6 | 2670 | bool dead = true, freeze = false; |
302ad8cc | 2671 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
22404274 | 2672 | |
77bf25ea | 2673 | mutex_lock(&dev->shutdown_lock); |
081f5e75 KB |
2674 | if (pci_is_enabled(pdev)) { |
2675 | u32 csts; | |
2676 | ||
2677 | if (pci_device_is_present(pdev)) | |
2678 | csts = readl(dev->bar + NVME_REG_CSTS); | |
2679 | else | |
2680 | csts = ~0; | |
302ad8cc | 2681 | |
ebef7368 | 2682 | if (dev->ctrl.state == NVME_CTRL_LIVE || |
e43269e6 KB |
2683 | dev->ctrl.state == NVME_CTRL_RESETTING) { |
2684 | freeze = true; | |
302ad8cc | 2685 | nvme_start_freeze(&dev->ctrl); |
e43269e6 | 2686 | } |
302ad8cc KB |
2687 | dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) || |
2688 | pdev->error_state != pci_channel_io_normal); | |
c9d3bf88 | 2689 | } |
c21377f8 | 2690 | |
302ad8cc KB |
2691 | /* |
2692 | * Give the controller a chance to complete all entered requests if | |
2693 | * doing a safe shutdown. | |
2694 | */ | |
e43269e6 KB |
2695 | if (!dead && shutdown && freeze) |
2696 | nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT); | |
9a915a5b JW |
2697 | |
2698 | nvme_stop_queues(&dev->ctrl); | |
87ad72a5 | 2699 | |
64ee0ac0 | 2700 | if (!dead && dev->ctrl.queue_count > 0) { |
8fae268b | 2701 | nvme_disable_io_queues(dev); |
a5cdb68c | 2702 | nvme_disable_admin_queue(dev, shutdown); |
4d115420 | 2703 | } |
8fae268b KB |
2704 | nvme_suspend_io_queues(dev); |
2705 | nvme_suspend_queue(&dev->queues[0]); | |
b00a726a | 2706 | nvme_pci_disable(dev); |
fa46c6fb | 2707 | nvme_reap_pending_cqes(dev); |
07836e65 | 2708 | |
1fcfca78 GL |
2709 | nvme_cancel_tagset(&dev->ctrl); |
2710 | nvme_cancel_admin_tagset(&dev->ctrl); | |
302ad8cc KB |
2711 | |
2712 | /* | |
2713 | * The driver will not be starting up queues again if shutting down so | |
2714 | * must flush all entered requests to their failed completion to avoid | |
2715 | * deadlocking blk-mq hot-cpu notifier. | |
2716 | */ | |
c8e9e9b7 | 2717 | if (shutdown) { |
302ad8cc | 2718 | nvme_start_queues(&dev->ctrl); |
c8e9e9b7 | 2719 | if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) |
6ca1d902 | 2720 | nvme_start_admin_queue(&dev->ctrl); |
c8e9e9b7 | 2721 | } |
77bf25ea | 2722 | mutex_unlock(&dev->shutdown_lock); |
b60503ba MW |
2723 | } |
2724 | ||
c1ac9a4b KB |
2725 | static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown) |
2726 | { | |
2727 | if (!nvme_wait_reset(&dev->ctrl)) | |
2728 | return -EBUSY; | |
2729 | nvme_dev_disable(dev, shutdown); | |
2730 | return 0; | |
2731 | } | |
2732 | ||
091b6092 MW |
2733 | static int nvme_setup_prp_pools(struct nvme_dev *dev) |
2734 | { | |
e75ec752 | 2735 | dev->prp_page_pool = dma_pool_create("prp list page", dev->dev, |
c61b82c7 CH |
2736 | NVME_CTRL_PAGE_SIZE, |
2737 | NVME_CTRL_PAGE_SIZE, 0); | |
091b6092 MW |
2738 | if (!dev->prp_page_pool) |
2739 | return -ENOMEM; | |
2740 | ||
99802a7a | 2741 | /* Optimisation for I/Os between 4k and 128k */ |
e75ec752 | 2742 | dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev, |
99802a7a MW |
2743 | 256, 256, 0); |
2744 | if (!dev->prp_small_pool) { | |
2745 | dma_pool_destroy(dev->prp_page_pool); | |
2746 | return -ENOMEM; | |
2747 | } | |
091b6092 MW |
2748 | return 0; |
2749 | } | |
2750 | ||
2751 | static void nvme_release_prp_pools(struct nvme_dev *dev) | |
2752 | { | |
2753 | dma_pool_destroy(dev->prp_page_pool); | |
99802a7a | 2754 | dma_pool_destroy(dev->prp_small_pool); |
091b6092 MW |
2755 | } |
2756 | ||
081a7d95 CH |
2757 | static int nvme_pci_alloc_iod_mempool(struct nvme_dev *dev) |
2758 | { | |
2759 | size_t npages = max(nvme_pci_npages_prp(), nvme_pci_npages_sgl()); | |
2760 | size_t alloc_size = sizeof(__le64 *) * npages + | |
2761 | sizeof(struct scatterlist) * NVME_MAX_SEGS; | |
2762 | ||
2763 | WARN_ON_ONCE(alloc_size > PAGE_SIZE); | |
2764 | dev->iod_mempool = mempool_create_node(1, | |
2765 | mempool_kmalloc, mempool_kfree, | |
2766 | (void *)alloc_size, GFP_KERNEL, | |
2767 | dev_to_node(dev->dev)); | |
2768 | if (!dev->iod_mempool) | |
2769 | return -ENOMEM; | |
2770 | return 0; | |
2771 | } | |
2772 | ||
770597ec KB |
2773 | static void nvme_free_tagset(struct nvme_dev *dev) |
2774 | { | |
2775 | if (dev->tagset.tags) | |
2776 | blk_mq_free_tag_set(&dev->tagset); | |
2777 | dev->ctrl.tagset = NULL; | |
2778 | } | |
2779 | ||
2e87570b | 2780 | /* pairs with nvme_pci_alloc_dev */ |
1673f1f0 | 2781 | static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl) |
5e82e952 | 2782 | { |
1673f1f0 | 2783 | struct nvme_dev *dev = to_nvme_dev(ctrl); |
9ac27090 | 2784 | |
770597ec | 2785 | nvme_free_tagset(dev); |
253fd4ac IR |
2786 | put_device(dev->dev); |
2787 | kfree(dev->queues); | |
5e82e952 KB |
2788 | kfree(dev); |
2789 | } | |
2790 | ||
7c1ce408 | 2791 | static void nvme_remove_dead_ctrl(struct nvme_dev *dev) |
f58944e2 | 2792 | { |
c1ac9a4b KB |
2793 | /* |
2794 | * Set state to deleting now to avoid blocking nvme_wait_reset(), which | |
2795 | * may be holding this pci_dev's device lock. | |
2796 | */ | |
2797 | nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); | |
d22524a4 | 2798 | nvme_get_ctrl(&dev->ctrl); |
69d9a99c | 2799 | nvme_dev_disable(dev, false); |
cd50f9b2 | 2800 | nvme_mark_namespaces_dead(&dev->ctrl); |
03e0f3a6 | 2801 | if (!queue_work(nvme_wq, &dev->remove_work)) |
f58944e2 KB |
2802 | nvme_put_ctrl(&dev->ctrl); |
2803 | } | |
2804 | ||
fd634f41 | 2805 | static void nvme_reset_work(struct work_struct *work) |
5e82e952 | 2806 | { |
d86c4d8e CH |
2807 | struct nvme_dev *dev = |
2808 | container_of(work, struct nvme_dev, ctrl.reset_work); | |
a98e58e5 | 2809 | bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL); |
e71afda4 | 2810 | int result; |
5e82e952 | 2811 | |
7764656b ZC |
2812 | if (dev->ctrl.state != NVME_CTRL_RESETTING) { |
2813 | dev_warn(dev->ctrl.device, "ctrl state %d is not RESETTING\n", | |
2814 | dev->ctrl.state); | |
e71afda4 | 2815 | result = -ENODEV; |
fd634f41 | 2816 | goto out; |
e71afda4 | 2817 | } |
5e82e952 | 2818 | |
fd634f41 CH |
2819 | /* |
2820 | * If we're called to reset a live controller first shut it down before | |
2821 | * moving on. | |
2822 | */ | |
b00a726a | 2823 | if (dev->ctrl.ctrl_config & NVME_CC_ENABLE) |
a5cdb68c | 2824 | nvme_dev_disable(dev, false); |
d6135c3a | 2825 | nvme_sync_queues(&dev->ctrl); |
5e82e952 | 2826 | |
5c959d73 | 2827 | mutex_lock(&dev->shutdown_lock); |
b00a726a | 2828 | result = nvme_pci_enable(dev); |
f0b50732 | 2829 | if (result) |
4726bcf3 | 2830 | goto out_unlock; |
f0b50732 | 2831 | |
01ad0990 | 2832 | result = nvme_pci_configure_admin_queue(dev); |
f0b50732 | 2833 | if (result) |
4726bcf3 | 2834 | goto out_unlock; |
f0b50732 | 2835 | |
f91b727c CH |
2836 | if (!dev->ctrl.admin_q) { |
2837 | result = nvme_pci_alloc_admin_tag_set(dev); | |
2838 | if (result) | |
2839 | goto out_unlock; | |
2840 | } else { | |
2841 | nvme_start_admin_queue(&dev->ctrl); | |
2842 | } | |
b9afca3e | 2843 | |
61ce339f RB |
2844 | dma_set_min_align_mask(dev->dev, NVME_CTRL_PAGE_SIZE - 1); |
2845 | ||
943e942e JA |
2846 | /* |
2847 | * Limit the max command size to prevent iod->sg allocations going | |
2848 | * over a single page. | |
2849 | */ | |
7637de31 CH |
2850 | dev->ctrl.max_hw_sectors = min_t(u32, |
2851 | NVME_MAX_KB_SZ << 1, dma_max_mapping_size(dev->dev) >> 9); | |
943e942e | 2852 | dev->ctrl.max_segments = NVME_MAX_SEGS; |
a48bc520 CH |
2853 | |
2854 | /* | |
2855 | * Don't limit the IOMMU merged segment size. | |
2856 | */ | |
2857 | dma_set_max_seg_size(dev->dev, 0xffffffff); | |
2858 | ||
5c959d73 KB |
2859 | mutex_unlock(&dev->shutdown_lock); |
2860 | ||
2861 | /* | |
2862 | * Introduce CONNECTING state from nvme-fc/rdma transports to mark the | |
2863 | * initializing procedure here. | |
2864 | */ | |
2865 | if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) { | |
2866 | dev_warn(dev->ctrl.device, | |
2867 | "failed to mark controller CONNECTING\n"); | |
cee6c269 | 2868 | result = -EBUSY; |
5c959d73 KB |
2869 | goto out; |
2870 | } | |
943e942e | 2871 | |
95093350 MG |
2872 | /* |
2873 | * We do not support an SGL for metadata (yet), so we are limited to a | |
2874 | * single integrity segment for the separate metadata pointer. | |
2875 | */ | |
2876 | dev->ctrl.max_integrity_segments = 1; | |
2877 | ||
94cc781f | 2878 | result = nvme_init_ctrl_finish(&dev->ctrl, was_suspend); |
ce4541f4 | 2879 | if (result) |
f58944e2 | 2880 | goto out; |
ce4541f4 | 2881 | |
f9f38e33 HK |
2882 | if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) { |
2883 | result = nvme_dbbuf_dma_alloc(dev); | |
2884 | if (result) | |
2885 | dev_warn(dev->dev, | |
2886 | "unable to allocate dma for dbbuf\n"); | |
2887 | } | |
2888 | ||
9620cfba CH |
2889 | if (dev->ctrl.hmpre) { |
2890 | result = nvme_setup_host_mem(dev); | |
2891 | if (result < 0) | |
2892 | goto out; | |
2893 | } | |
87ad72a5 | 2894 | |
f0b50732 | 2895 | result = nvme_setup_io_queues(dev); |
badc34d4 | 2896 | if (result) |
f58944e2 | 2897 | goto out; |
f0b50732 | 2898 | |
0ffc7e98 CH |
2899 | if (dev->ctrl.tagset) { |
2900 | /* | |
2901 | * This is a controller reset and we already have a tagset. | |
2902 | * Freeze and update the number of I/O queues as thos might have | |
2903 | * changed. If there are no I/O queues left after this reset, | |
2904 | * keep the controller around but remove all namespaces. | |
2905 | */ | |
2906 | if (dev->online_queues > 1) { | |
2907 | nvme_start_queues(&dev->ctrl); | |
2908 | nvme_wait_freeze(&dev->ctrl); | |
2909 | nvme_pci_update_nr_queues(dev); | |
2910 | nvme_dbbuf_set(dev); | |
2911 | nvme_unfreeze(&dev->ctrl); | |
2912 | } else { | |
2913 | dev_warn(dev->ctrl.device, "IO queues lost\n"); | |
cd50f9b2 CH |
2914 | nvme_mark_namespaces_dead(&dev->ctrl); |
2915 | nvme_start_queues(&dev->ctrl); | |
0ffc7e98 CH |
2916 | nvme_remove_namespaces(&dev->ctrl); |
2917 | nvme_free_tagset(dev); | |
2918 | } | |
3cf519b5 | 2919 | } else { |
0ffc7e98 CH |
2920 | /* |
2921 | * First probe. Still allow the controller to show up even if | |
2922 | * there are no namespaces. | |
2923 | */ | |
2924 | if (dev->online_queues > 1) { | |
2455a4b7 | 2925 | nvme_pci_alloc_tag_set(dev); |
0ffc7e98 CH |
2926 | nvme_dbbuf_set(dev); |
2927 | } else { | |
2928 | dev_warn(dev->ctrl.device, "IO queues not created\n"); | |
2929 | } | |
3cf519b5 CH |
2930 | } |
2931 | ||
2b1b7e78 JW |
2932 | /* |
2933 | * If only admin queue live, keep it to do further investigation or | |
2934 | * recovery. | |
2935 | */ | |
5d02a5c1 | 2936 | if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) { |
2b1b7e78 | 2937 | dev_warn(dev->ctrl.device, |
5d02a5c1 | 2938 | "failed to mark controller live state\n"); |
e71afda4 | 2939 | result = -ENODEV; |
bb8d261e CH |
2940 | goto out; |
2941 | } | |
92911a55 | 2942 | |
d09f2b45 | 2943 | nvme_start_ctrl(&dev->ctrl); |
3cf519b5 | 2944 | return; |
f0b50732 | 2945 | |
4726bcf3 KB |
2946 | out_unlock: |
2947 | mutex_unlock(&dev->shutdown_lock); | |
3cf519b5 | 2948 | out: |
7c1ce408 CK |
2949 | if (result) |
2950 | dev_warn(dev->ctrl.device, | |
2951 | "Removing after probe failure status: %d\n", result); | |
2952 | nvme_remove_dead_ctrl(dev); | |
f0b50732 KB |
2953 | } |
2954 | ||
5c8809e6 | 2955 | static void nvme_remove_dead_ctrl_work(struct work_struct *work) |
9a6b9458 | 2956 | { |
5c8809e6 | 2957 | struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work); |
e75ec752 | 2958 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
9a6b9458 KB |
2959 | |
2960 | if (pci_get_drvdata(pdev)) | |
921920ab | 2961 | device_release_driver(&pdev->dev); |
1673f1f0 | 2962 | nvme_put_ctrl(&dev->ctrl); |
9a6b9458 KB |
2963 | } |
2964 | ||
1c63dc66 | 2965 | static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val) |
9ca97374 | 2966 | { |
1c63dc66 | 2967 | *val = readl(to_nvme_dev(ctrl)->bar + off); |
90667892 | 2968 | return 0; |
9ca97374 TH |
2969 | } |
2970 | ||
5fd4ce1b | 2971 | static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val) |
4cc06521 | 2972 | { |
5fd4ce1b CH |
2973 | writel(val, to_nvme_dev(ctrl)->bar + off); |
2974 | return 0; | |
2975 | } | |
4cc06521 | 2976 | |
7fd8930f CH |
2977 | static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val) |
2978 | { | |
3a8ecc93 | 2979 | *val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off); |
7fd8930f | 2980 | return 0; |
4cc06521 KB |
2981 | } |
2982 | ||
97c12223 KB |
2983 | static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size) |
2984 | { | |
2985 | struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev); | |
2986 | ||
2db24e4a | 2987 | return snprintf(buf, size, "%s\n", dev_name(&pdev->dev)); |
97c12223 KB |
2988 | } |
2989 | ||
2f0dad17 KB |
2990 | static void nvme_pci_print_device_info(struct nvme_ctrl *ctrl) |
2991 | { | |
2992 | struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev); | |
2993 | struct nvme_subsystem *subsys = ctrl->subsys; | |
2994 | ||
2995 | dev_err(ctrl->device, | |
2996 | "VID:DID %04x:%04x model:%.*s firmware:%.*s\n", | |
2997 | pdev->vendor, pdev->device, | |
2998 | nvme_strlen(subsys->model, sizeof(subsys->model)), | |
2999 | subsys->model, nvme_strlen(subsys->firmware_rev, | |
3000 | sizeof(subsys->firmware_rev)), | |
3001 | subsys->firmware_rev); | |
3002 | } | |
3003 | ||
2f859441 LG |
3004 | static bool nvme_pci_supports_pci_p2pdma(struct nvme_ctrl *ctrl) |
3005 | { | |
3006 | struct nvme_dev *dev = to_nvme_dev(ctrl); | |
3007 | ||
3008 | return dma_pci_p2pdma_supported(dev->dev); | |
3009 | } | |
3010 | ||
1c63dc66 | 3011 | static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = { |
1a353d85 | 3012 | .name = "pcie", |
e439bb12 | 3013 | .module = THIS_MODULE, |
2f859441 | 3014 | .flags = NVME_F_METADATA_SUPPORTED, |
86adbf0c | 3015 | .dev_attr_groups = nvme_pci_dev_attr_groups, |
1c63dc66 | 3016 | .reg_read32 = nvme_pci_reg_read32, |
5fd4ce1b | 3017 | .reg_write32 = nvme_pci_reg_write32, |
7fd8930f | 3018 | .reg_read64 = nvme_pci_reg_read64, |
1673f1f0 | 3019 | .free_ctrl = nvme_pci_free_ctrl, |
f866fc42 | 3020 | .submit_async_event = nvme_pci_submit_async_event, |
97c12223 | 3021 | .get_address = nvme_pci_get_address, |
2f0dad17 | 3022 | .print_device_info = nvme_pci_print_device_info, |
2f859441 | 3023 | .supports_pci_p2pdma = nvme_pci_supports_pci_p2pdma, |
1c63dc66 | 3024 | }; |
4cc06521 | 3025 | |
b00a726a KB |
3026 | static int nvme_dev_map(struct nvme_dev *dev) |
3027 | { | |
b00a726a KB |
3028 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
3029 | ||
a1f447b3 | 3030 | if (pci_request_mem_regions(pdev, "nvme")) |
b00a726a KB |
3031 | return -ENODEV; |
3032 | ||
97f6ef64 | 3033 | if (nvme_remap_bar(dev, NVME_REG_DBS + 4096)) |
b00a726a KB |
3034 | goto release; |
3035 | ||
9fa196e7 | 3036 | return 0; |
b00a726a | 3037 | release: |
9fa196e7 MG |
3038 | pci_release_mem_regions(pdev); |
3039 | return -ENODEV; | |
b00a726a KB |
3040 | } |
3041 | ||
8427bbc2 | 3042 | static unsigned long check_vendor_combination_bug(struct pci_dev *pdev) |
ff5350a8 AL |
3043 | { |
3044 | if (pdev->vendor == 0x144d && pdev->device == 0xa802) { | |
3045 | /* | |
3046 | * Several Samsung devices seem to drop off the PCIe bus | |
3047 | * randomly when APST is on and uses the deepest sleep state. | |
3048 | * This has been observed on a Samsung "SM951 NVMe SAMSUNG | |
3049 | * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD | |
3050 | * 950 PRO 256GB", but it seems to be restricted to two Dell | |
3051 | * laptops. | |
3052 | */ | |
3053 | if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") && | |
3054 | (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") || | |
3055 | dmi_match(DMI_PRODUCT_NAME, "Precision 5510"))) | |
3056 | return NVME_QUIRK_NO_DEEPEST_PS; | |
8427bbc2 KHF |
3057 | } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) { |
3058 | /* | |
3059 | * Samsung SSD 960 EVO drops off the PCIe bus after system | |
467c77d4 JJ |
3060 | * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as |
3061 | * within few minutes after bootup on a Coffee Lake board - | |
3062 | * ASUS PRIME Z370-A | |
8427bbc2 KHF |
3063 | */ |
3064 | if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") && | |
467c77d4 JJ |
3065 | (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") || |
3066 | dmi_match(DMI_BOARD_NAME, "PRIME Z370-A"))) | |
8427bbc2 | 3067 | return NVME_QUIRK_NO_APST; |
1fae37ac S |
3068 | } else if ((pdev->vendor == 0x144d && (pdev->device == 0xa801 || |
3069 | pdev->device == 0xa808 || pdev->device == 0xa809)) || | |
3070 | (pdev->vendor == 0x1e0f && pdev->device == 0x0001)) { | |
3071 | /* | |
3072 | * Forcing to use host managed nvme power settings for | |
3073 | * lowest idle power with quick resume latency on | |
3074 | * Samsung and Toshiba SSDs based on suspend behavior | |
3075 | * on Coffee Lake board for LENOVO C640 | |
3076 | */ | |
3077 | if ((dmi_match(DMI_BOARD_VENDOR, "LENOVO")) && | |
3078 | dmi_match(DMI_BOARD_NAME, "LNVNB161216")) | |
3079 | return NVME_QUIRK_SIMPLE_SUSPEND; | |
ff5350a8 AL |
3080 | } |
3081 | ||
3082 | return 0; | |
3083 | } | |
3084 | ||
18119775 KB |
3085 | static void nvme_async_probe(void *data, async_cookie_t cookie) |
3086 | { | |
3087 | struct nvme_dev *dev = data; | |
80f513b5 | 3088 | |
bd46a906 | 3089 | flush_work(&dev->ctrl.reset_work); |
18119775 | 3090 | flush_work(&dev->ctrl.scan_work); |
80f513b5 | 3091 | nvme_put_ctrl(&dev->ctrl); |
18119775 KB |
3092 | } |
3093 | ||
2e87570b CH |
3094 | static struct nvme_dev *nvme_pci_alloc_dev(struct pci_dev *pdev, |
3095 | const struct pci_device_id *id) | |
b60503ba | 3096 | { |
ff5350a8 | 3097 | unsigned long quirks = id->driver_data; |
2e87570b CH |
3098 | int node = dev_to_node(&pdev->dev); |
3099 | struct nvme_dev *dev; | |
3100 | int ret = -ENOMEM; | |
b60503ba | 3101 | |
a4aea562 | 3102 | if (node == NUMA_NO_NODE) |
2fa84351 | 3103 | set_dev_node(&pdev->dev, first_memory_node); |
a4aea562 MB |
3104 | |
3105 | dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); | |
b60503ba | 3106 | if (!dev) |
2e87570b CH |
3107 | return NULL; |
3108 | INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work); | |
3109 | INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work); | |
3110 | mutex_init(&dev->shutdown_lock); | |
147b27e4 | 3111 | |
2a5bcfdd WZ |
3112 | dev->nr_write_queues = write_queues; |
3113 | dev->nr_poll_queues = poll_queues; | |
3114 | dev->nr_allocated_queues = nvme_max_io_queues(dev) + 1; | |
3115 | dev->queues = kcalloc_node(dev->nr_allocated_queues, | |
3116 | sizeof(struct nvme_queue), GFP_KERNEL, node); | |
b60503ba | 3117 | if (!dev->queues) |
2e87570b | 3118 | goto out_free_dev; |
b60503ba | 3119 | |
e75ec752 | 3120 | dev->dev = get_device(&pdev->dev); |
4cc06521 | 3121 | |
8427bbc2 | 3122 | quirks |= check_vendor_combination_bug(pdev); |
2744d7a0 | 3123 | if (!noacpi && acpi_storage_d3(&pdev->dev)) { |
df4f9bc4 DB |
3124 | /* |
3125 | * Some systems use a bios work around to ask for D3 on | |
3126 | * platforms that support kernel managed suspend. | |
3127 | */ | |
3128 | dev_info(&pdev->dev, | |
3129 | "platform quirk: setting simple suspend\n"); | |
3130 | quirks |= NVME_QUIRK_SIMPLE_SUSPEND; | |
3131 | } | |
2e87570b CH |
3132 | ret = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops, |
3133 | quirks); | |
3134 | if (ret) | |
3135 | goto out_put_device; | |
3136 | return dev; | |
df4f9bc4 | 3137 | |
2e87570b CH |
3138 | out_put_device: |
3139 | put_device(dev->dev); | |
3140 | kfree(dev->queues); | |
3141 | out_free_dev: | |
3142 | kfree(dev); | |
3143 | return ERR_PTR(ret); | |
3144 | } | |
3145 | ||
3146 | static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) | |
3147 | { | |
3148 | struct nvme_dev *dev; | |
3149 | int result = -ENOMEM; | |
3150 | ||
3151 | dev = nvme_pci_alloc_dev(pdev, id); | |
3152 | if (!dev) | |
3153 | return -ENOMEM; | |
3154 | ||
3155 | result = nvme_dev_map(dev); | |
3156 | if (result) | |
3157 | goto out_uninit_ctrl; | |
3158 | ||
3159 | result = nvme_setup_prp_pools(dev); | |
081a7d95 | 3160 | if (result) |
2e87570b | 3161 | goto out_dev_unmap; |
943e942e | 3162 | |
2e87570b | 3163 | result = nvme_pci_alloc_iod_mempool(dev); |
b6e44b4c | 3164 | if (result) |
2e87570b | 3165 | goto out_release_prp_pools; |
b6e44b4c | 3166 | |
1b3c47c1 | 3167 | dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev)); |
2e87570b | 3168 | pci_set_drvdata(pdev, dev); |
1b3c47c1 | 3169 | |
bd46a906 | 3170 | nvme_reset_ctrl(&dev->ctrl); |
18119775 | 3171 | async_schedule(nvme_async_probe, dev); |
b60503ba MW |
3172 | return 0; |
3173 | ||
2e87570b | 3174 | out_release_prp_pools: |
091b6092 | 3175 | nvme_release_prp_pools(dev); |
2e87570b | 3176 | out_dev_unmap: |
b00c9b7a | 3177 | nvme_dev_unmap(dev); |
2e87570b CH |
3178 | out_uninit_ctrl: |
3179 | nvme_uninit_ctrl(&dev->ctrl); | |
b60503ba MW |
3180 | return result; |
3181 | } | |
3182 | ||
775755ed | 3183 | static void nvme_reset_prepare(struct pci_dev *pdev) |
f0d54a54 | 3184 | { |
a6739479 | 3185 | struct nvme_dev *dev = pci_get_drvdata(pdev); |
c1ac9a4b KB |
3186 | |
3187 | /* | |
3188 | * We don't need to check the return value from waiting for the reset | |
3189 | * state as pci_dev device lock is held, making it impossible to race | |
3190 | * with ->remove(). | |
3191 | */ | |
3192 | nvme_disable_prepare_reset(dev, false); | |
3193 | nvme_sync_queues(&dev->ctrl); | |
775755ed | 3194 | } |
f0d54a54 | 3195 | |
775755ed CH |
3196 | static void nvme_reset_done(struct pci_dev *pdev) |
3197 | { | |
f263fbb8 | 3198 | struct nvme_dev *dev = pci_get_drvdata(pdev); |
c1ac9a4b KB |
3199 | |
3200 | if (!nvme_try_sched_reset(&dev->ctrl)) | |
3201 | flush_work(&dev->ctrl.reset_work); | |
f0d54a54 KB |
3202 | } |
3203 | ||
09ece142 KB |
3204 | static void nvme_shutdown(struct pci_dev *pdev) |
3205 | { | |
3206 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
4e523547 | 3207 | |
c1ac9a4b | 3208 | nvme_disable_prepare_reset(dev, true); |
09ece142 KB |
3209 | } |
3210 | ||
f58944e2 KB |
3211 | /* |
3212 | * The driver's remove may be called on a device in a partially initialized | |
3213 | * state. This function must not have any dependencies on the device state in | |
3214 | * order to proceed. | |
3215 | */ | |
8d85fce7 | 3216 | static void nvme_remove(struct pci_dev *pdev) |
b60503ba MW |
3217 | { |
3218 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
9a6b9458 | 3219 | |
bb8d261e | 3220 | nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); |
9a6b9458 | 3221 | pci_set_drvdata(pdev, NULL); |
0ff9d4e1 | 3222 | |
6db28eda | 3223 | if (!pci_device_is_present(pdev)) { |
0ff9d4e1 | 3224 | nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD); |
1d39e692 | 3225 | nvme_dev_disable(dev, true); |
6db28eda | 3226 | } |
0ff9d4e1 | 3227 | |
d86c4d8e | 3228 | flush_work(&dev->ctrl.reset_work); |
d09f2b45 SG |
3229 | nvme_stop_ctrl(&dev->ctrl); |
3230 | nvme_remove_namespaces(&dev->ctrl); | |
a5cdb68c | 3231 | nvme_dev_disable(dev, true); |
87ad72a5 | 3232 | nvme_free_host_mem(dev); |
a4aea562 | 3233 | nvme_dev_remove_admin(dev); |
c11b7716 | 3234 | nvme_dbbuf_dma_free(dev); |
a1a5ef99 | 3235 | nvme_free_queues(dev, 0); |
c11b7716 | 3236 | mempool_destroy(dev->iod_mempool); |
9a6b9458 | 3237 | nvme_release_prp_pools(dev); |
b00a726a | 3238 | nvme_dev_unmap(dev); |
726612b6 | 3239 | nvme_uninit_ctrl(&dev->ctrl); |
b60503ba MW |
3240 | } |
3241 | ||
671a6018 | 3242 | #ifdef CONFIG_PM_SLEEP |
d916b1be KB |
3243 | static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps) |
3244 | { | |
3245 | return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps); | |
3246 | } | |
3247 | ||
3248 | static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps) | |
3249 | { | |
3250 | return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL); | |
3251 | } | |
3252 | ||
3253 | static int nvme_resume(struct device *dev) | |
3254 | { | |
3255 | struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev)); | |
3256 | struct nvme_ctrl *ctrl = &ndev->ctrl; | |
3257 | ||
4eaefe8c | 3258 | if (ndev->last_ps == U32_MAX || |
d916b1be | 3259 | nvme_set_power_state(ctrl, ndev->last_ps) != 0) |
e5ad96f3 KB |
3260 | goto reset; |
3261 | if (ctrl->hmpre && nvme_setup_host_mem(ndev)) | |
3262 | goto reset; | |
3263 | ||
d916b1be | 3264 | return 0; |
e5ad96f3 KB |
3265 | reset: |
3266 | return nvme_try_sched_reset(ctrl); | |
d916b1be KB |
3267 | } |
3268 | ||
cd638946 KB |
3269 | static int nvme_suspend(struct device *dev) |
3270 | { | |
3271 | struct pci_dev *pdev = to_pci_dev(dev); | |
3272 | struct nvme_dev *ndev = pci_get_drvdata(pdev); | |
d916b1be KB |
3273 | struct nvme_ctrl *ctrl = &ndev->ctrl; |
3274 | int ret = -EBUSY; | |
3275 | ||
4eaefe8c RW |
3276 | ndev->last_ps = U32_MAX; |
3277 | ||
d916b1be KB |
3278 | /* |
3279 | * The platform does not remove power for a kernel managed suspend so | |
3280 | * use host managed nvme power settings for lowest idle power if | |
3281 | * possible. This should have quicker resume latency than a full device | |
3282 | * shutdown. But if the firmware is involved after the suspend or the | |
3283 | * device does not support any non-default power states, shut down the | |
3284 | * device fully. | |
4eaefe8c RW |
3285 | * |
3286 | * If ASPM is not enabled for the device, shut down the device and allow | |
3287 | * the PCI bus layer to put it into D3 in order to take the PCIe link | |
3288 | * down, so as to allow the platform to achieve its minimum low-power | |
3289 | * state (which may not be possible if the link is up). | |
d916b1be | 3290 | */ |
4eaefe8c | 3291 | if (pm_suspend_via_firmware() || !ctrl->npss || |
cb32de1b | 3292 | !pcie_aspm_enabled(pdev) || |
c1ac9a4b KB |
3293 | (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND)) |
3294 | return nvme_disable_prepare_reset(ndev, true); | |
d916b1be KB |
3295 | |
3296 | nvme_start_freeze(ctrl); | |
3297 | nvme_wait_freeze(ctrl); | |
3298 | nvme_sync_queues(ctrl); | |
3299 | ||
5d02a5c1 | 3300 | if (ctrl->state != NVME_CTRL_LIVE) |
d916b1be KB |
3301 | goto unfreeze; |
3302 | ||
e5ad96f3 KB |
3303 | /* |
3304 | * Host memory access may not be successful in a system suspend state, | |
3305 | * but the specification allows the controller to access memory in a | |
3306 | * non-operational power state. | |
3307 | */ | |
3308 | if (ndev->hmb) { | |
3309 | ret = nvme_set_host_mem(ndev, 0); | |
3310 | if (ret < 0) | |
3311 | goto unfreeze; | |
3312 | } | |
3313 | ||
d916b1be KB |
3314 | ret = nvme_get_power_state(ctrl, &ndev->last_ps); |
3315 | if (ret < 0) | |
3316 | goto unfreeze; | |
3317 | ||
7cbb5c6f ML |
3318 | /* |
3319 | * A saved state prevents pci pm from generically controlling the | |
3320 | * device's power. If we're using protocol specific settings, we don't | |
3321 | * want pci interfering. | |
3322 | */ | |
3323 | pci_save_state(pdev); | |
3324 | ||
d916b1be KB |
3325 | ret = nvme_set_power_state(ctrl, ctrl->npss); |
3326 | if (ret < 0) | |
3327 | goto unfreeze; | |
3328 | ||
3329 | if (ret) { | |
7cbb5c6f ML |
3330 | /* discard the saved state */ |
3331 | pci_load_saved_state(pdev, NULL); | |
3332 | ||
d916b1be KB |
3333 | /* |
3334 | * Clearing npss forces a controller reset on resume. The | |
05d3046f | 3335 | * correct value will be rediscovered then. |
d916b1be | 3336 | */ |
c1ac9a4b | 3337 | ret = nvme_disable_prepare_reset(ndev, true); |
d916b1be | 3338 | ctrl->npss = 0; |
d916b1be | 3339 | } |
d916b1be KB |
3340 | unfreeze: |
3341 | nvme_unfreeze(ctrl); | |
3342 | return ret; | |
3343 | } | |
3344 | ||
3345 | static int nvme_simple_suspend(struct device *dev) | |
3346 | { | |
3347 | struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev)); | |
4e523547 | 3348 | |
c1ac9a4b | 3349 | return nvme_disable_prepare_reset(ndev, true); |
cd638946 KB |
3350 | } |
3351 | ||
d916b1be | 3352 | static int nvme_simple_resume(struct device *dev) |
cd638946 KB |
3353 | { |
3354 | struct pci_dev *pdev = to_pci_dev(dev); | |
3355 | struct nvme_dev *ndev = pci_get_drvdata(pdev); | |
cd638946 | 3356 | |
c1ac9a4b | 3357 | return nvme_try_sched_reset(&ndev->ctrl); |
cd638946 KB |
3358 | } |
3359 | ||
21774222 | 3360 | static const struct dev_pm_ops nvme_dev_pm_ops = { |
d916b1be KB |
3361 | .suspend = nvme_suspend, |
3362 | .resume = nvme_resume, | |
3363 | .freeze = nvme_simple_suspend, | |
3364 | .thaw = nvme_simple_resume, | |
3365 | .poweroff = nvme_simple_suspend, | |
3366 | .restore = nvme_simple_resume, | |
3367 | }; | |
3368 | #endif /* CONFIG_PM_SLEEP */ | |
b60503ba | 3369 | |
a0a3408e KB |
3370 | static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev, |
3371 | pci_channel_state_t state) | |
3372 | { | |
3373 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
3374 | ||
3375 | /* | |
3376 | * A frozen channel requires a reset. When detected, this method will | |
3377 | * shutdown the controller to quiesce. The controller will be restarted | |
3378 | * after the slot reset through driver's slot_reset callback. | |
3379 | */ | |
a0a3408e KB |
3380 | switch (state) { |
3381 | case pci_channel_io_normal: | |
3382 | return PCI_ERS_RESULT_CAN_RECOVER; | |
3383 | case pci_channel_io_frozen: | |
d011fb31 KB |
3384 | dev_warn(dev->ctrl.device, |
3385 | "frozen state error detected, reset controller\n"); | |
a5cdb68c | 3386 | nvme_dev_disable(dev, false); |
a0a3408e KB |
3387 | return PCI_ERS_RESULT_NEED_RESET; |
3388 | case pci_channel_io_perm_failure: | |
d011fb31 KB |
3389 | dev_warn(dev->ctrl.device, |
3390 | "failure state error detected, request disconnect\n"); | |
a0a3408e KB |
3391 | return PCI_ERS_RESULT_DISCONNECT; |
3392 | } | |
3393 | return PCI_ERS_RESULT_NEED_RESET; | |
3394 | } | |
3395 | ||
3396 | static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev) | |
3397 | { | |
3398 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
3399 | ||
1b3c47c1 | 3400 | dev_info(dev->ctrl.device, "restart after slot reset\n"); |
a0a3408e | 3401 | pci_restore_state(pdev); |
d86c4d8e | 3402 | nvme_reset_ctrl(&dev->ctrl); |
a0a3408e KB |
3403 | return PCI_ERS_RESULT_RECOVERED; |
3404 | } | |
3405 | ||
3406 | static void nvme_error_resume(struct pci_dev *pdev) | |
3407 | { | |
72cd4cc2 KB |
3408 | struct nvme_dev *dev = pci_get_drvdata(pdev); |
3409 | ||
3410 | flush_work(&dev->ctrl.reset_work); | |
a0a3408e KB |
3411 | } |
3412 | ||
1d352035 | 3413 | static const struct pci_error_handlers nvme_err_handler = { |
b60503ba | 3414 | .error_detected = nvme_error_detected, |
b60503ba MW |
3415 | .slot_reset = nvme_slot_reset, |
3416 | .resume = nvme_error_resume, | |
775755ed CH |
3417 | .reset_prepare = nvme_reset_prepare, |
3418 | .reset_done = nvme_reset_done, | |
b60503ba MW |
3419 | }; |
3420 | ||
6eb0d698 | 3421 | static const struct pci_device_id nvme_id_table[] = { |
972b13e2 | 3422 | { PCI_VDEVICE(INTEL, 0x0953), /* Intel 750/P3500/P3600/P3700 */ |
08095e70 | 3423 | .driver_data = NVME_QUIRK_STRIPE_SIZE | |
e850fd16 | 3424 | NVME_QUIRK_DEALLOCATE_ZEROES, }, |
972b13e2 | 3425 | { PCI_VDEVICE(INTEL, 0x0a53), /* Intel P3520 */ |
99466e70 | 3426 | .driver_data = NVME_QUIRK_STRIPE_SIZE | |
e850fd16 | 3427 | NVME_QUIRK_DEALLOCATE_ZEROES, }, |
972b13e2 | 3428 | { PCI_VDEVICE(INTEL, 0x0a54), /* Intel P4500/P4600 */ |
99466e70 | 3429 | .driver_data = NVME_QUIRK_STRIPE_SIZE | |
25e58af4 WZ |
3430 | NVME_QUIRK_DEALLOCATE_ZEROES | |
3431 | NVME_QUIRK_IGNORE_DEV_SUBNQN, }, | |
972b13e2 | 3432 | { PCI_VDEVICE(INTEL, 0x0a55), /* Dell Express Flash P4600 */ |
f99cb7af DWF |
3433 | .driver_data = NVME_QUIRK_STRIPE_SIZE | |
3434 | NVME_QUIRK_DEALLOCATE_ZEROES, }, | |
50af47d0 | 3435 | { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */ |
9abd68ef | 3436 | .driver_data = NVME_QUIRK_NO_DEEPEST_PS | |
6c6aa2f2 | 3437 | NVME_QUIRK_MEDIUM_PRIO_SQ | |
ce4cc313 DM |
3438 | NVME_QUIRK_NO_TEMP_THRESH_CHANGE | |
3439 | NVME_QUIRK_DISABLE_WRITE_ZEROES, }, | |
6299358d JD |
3440 | { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */ |
3441 | .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, }, | |
540c801c | 3442 | { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */ |
7b210e4e | 3443 | .driver_data = NVME_QUIRK_IDENTIFY_CNS | |
66dd346b CH |
3444 | NVME_QUIRK_DISABLE_WRITE_ZEROES | |
3445 | NVME_QUIRK_BOGUS_NID, }, | |
3446 | { PCI_VDEVICE(REDHAT, 0x0010), /* Qemu emulated controller */ | |
3447 | .driver_data = NVME_QUIRK_BOGUS_NID, }, | |
5bedd3af | 3448 | { PCI_DEVICE(0x126f, 0x2263), /* Silicon Motion unidentified */ |
c98a8793 KB |
3449 | .driver_data = NVME_QUIRK_NO_NS_DESC_LIST | |
3450 | NVME_QUIRK_BOGUS_NID, }, | |
0302ae60 | 3451 | { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */ |
5e112d3f JE |
3452 | .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY | |
3453 | NVME_QUIRK_NO_NS_DESC_LIST, }, | |
54adc010 GP |
3454 | { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */ |
3455 | .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, | |
8c97eecc JL |
3456 | { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */ |
3457 | .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, | |
015282c9 WW |
3458 | { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */ |
3459 | .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, | |
d554b5e1 MP |
3460 | { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */ |
3461 | .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, | |
3462 | { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */ | |
7ee5c78c | 3463 | .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY | |
abbb5f59 | 3464 | NVME_QUIRK_DISABLE_WRITE_ZEROES| |
7ee5c78c | 3465 | NVME_QUIRK_IGNORE_DEV_SUBNQN, }, |
2cf7a77e KB |
3466 | { PCI_DEVICE(0x1987, 0x5012), /* Phison E12 */ |
3467 | .driver_data = NVME_QUIRK_BOGUS_NID, }, | |
c9e95c39 | 3468 | { PCI_DEVICE(0x1987, 0x5016), /* Phison E16 */ |
73029c9b KB |
3469 | .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN | |
3470 | NVME_QUIRK_BOGUS_NID, }, | |
d14c2731 TH |
3471 | { PCI_DEVICE(0x1987, 0x5019), /* phison E19 */ |
3472 | .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, | |
3473 | { PCI_DEVICE(0x1987, 0x5021), /* Phison E21 */ | |
3474 | .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, | |
6e6a6828 PT |
3475 | { PCI_DEVICE(0x1b4b, 0x1092), /* Lexar 256 GB SSD */ |
3476 | .driver_data = NVME_QUIRK_NO_NS_DESC_LIST | | |
3477 | NVME_QUIRK_IGNORE_DEV_SUBNQN, }, | |
e1c70d79 LVS |
3478 | { PCI_DEVICE(0x1cc1, 0x33f8), /* ADATA IM2P33F8ABR1 1 TB */ |
3479 | .driver_data = NVME_QUIRK_BOGUS_NID, }, | |
08b903b5 | 3480 | { PCI_DEVICE(0x10ec, 0x5762), /* ADATA SX6000LNP */ |
1629de0e PG |
3481 | .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN | |
3482 | NVME_QUIRK_BOGUS_NID, }, | |
f03e42c6 GC |
3483 | { PCI_DEVICE(0x1cc1, 0x8201), /* ADATA SX8200PNP 512GB */ |
3484 | .driver_data = NVME_QUIRK_NO_DEEPEST_PS | | |
3485 | NVME_QUIRK_IGNORE_DEV_SUBNQN, }, | |
41f38043 LS |
3486 | { PCI_DEVICE(0x1344, 0x5407), /* Micron Technology Inc NVMe SSD */ |
3487 | .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN }, | |
5611ec2b KHF |
3488 | { PCI_DEVICE(0x1c5c, 0x1504), /* SK Hynix PC400 */ |
3489 | .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, | |
c4f01a77 KB |
3490 | { PCI_DEVICE(0x1c5c, 0x174a), /* SK Hynix P31 SSD */ |
3491 | .driver_data = NVME_QUIRK_BOGUS_NID, }, | |
02ca079c KHF |
3492 | { PCI_DEVICE(0x15b7, 0x2001), /* Sandisk Skyhawk */ |
3493 | .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, | |
89919929 CK |
3494 | { PCI_DEVICE(0x1d97, 0x2263), /* SPCC */ |
3495 | .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, | |
43047e08 | 3496 | { PCI_DEVICE(0x144d, 0xa80b), /* Samsung PM9B1 256G and 512G */ |
3497 | .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, | |
3498 | { PCI_DEVICE(0x144d, 0xa809), /* Samsung MZALQ256HBJD 256G */ | |
3499 | .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, | |
3500 | { PCI_DEVICE(0x1cc4, 0x6303), /* UMIS RPJTJ512MGE1QDY 512G */ | |
3501 | .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, | |
3502 | { PCI_DEVICE(0x1cc4, 0x6302), /* UMIS RPJTJ256MGE1QDY 256G */ | |
3503 | .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, | |
dc22c1c0 ZB |
3504 | { PCI_DEVICE(0x2646, 0x2262), /* KINGSTON SKC2000 NVMe SSD */ |
3505 | .driver_data = NVME_QUIRK_NO_DEEPEST_PS, }, | |
538e4a8c TL |
3506 | { PCI_DEVICE(0x2646, 0x2263), /* KINGSTON A2000 NVMe SSD */ |
3507 | .driver_data = NVME_QUIRK_NO_DEEPEST_PS, }, | |
ac9b57d4 XL |
3508 | { PCI_DEVICE(0x2646, 0x5018), /* KINGSTON OM8SFP4xxxxP OS21012 NVMe SSD */ |
3509 | .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, | |
3510 | { PCI_DEVICE(0x2646, 0x5016), /* KINGSTON OM3PGP4xxxxP OS21011 NVMe SSD */ | |
3511 | .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, | |
3512 | { PCI_DEVICE(0x2646, 0x501A), /* KINGSTON OM8PGP4xxxxP OS21005 NVMe SSD */ | |
3513 | .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, | |
3514 | { PCI_DEVICE(0x2646, 0x501B), /* KINGSTON OM8PGP4xxxxQ OS21005 NVMe SSD */ | |
3515 | .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, | |
3516 | { PCI_DEVICE(0x2646, 0x501E), /* KINGSTON OM3PGP4xxxxQ OS21011 NVMe SSD */ | |
3517 | .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, | |
70ce3455 CH |
3518 | { PCI_DEVICE(0x1e4B, 0x1001), /* MAXIO MAP1001 */ |
3519 | .driver_data = NVME_QUIRK_BOGUS_NID, }, | |
a98a945b CH |
3520 | { PCI_DEVICE(0x1e4B, 0x1002), /* MAXIO MAP1002 */ |
3521 | .driver_data = NVME_QUIRK_BOGUS_NID, }, | |
3522 | { PCI_DEVICE(0x1e4B, 0x1202), /* MAXIO MAP1202 */ | |
3523 | .driver_data = NVME_QUIRK_BOGUS_NID, }, | |
3765fad5 SR |
3524 | { PCI_DEVICE(0x1cc1, 0x5350), /* ADATA XPG GAMMIX S50 */ |
3525 | .driver_data = NVME_QUIRK_BOGUS_NID, }, | |
f37527a0 DK |
3526 | { PCI_DEVICE(0x1dbe, 0x5236), /* ADATA XPG GAMMIX S70 */ |
3527 | .driver_data = NVME_QUIRK_BOGUS_NID, }, | |
d5d3c100 XR |
3528 | { PCI_DEVICE(0x1e49, 0x0021), /* ZHITAI TiPro5000 NVMe SSD */ |
3529 | .driver_data = NVME_QUIRK_NO_DEEPEST_PS, }, | |
6b961bce NW |
3530 | { PCI_DEVICE(0x1e49, 0x0041), /* ZHITAI TiPro7000 NVMe SSD */ |
3531 | .driver_data = NVME_QUIRK_NO_DEEPEST_PS, }, | |
d6c52fa3 TG |
3532 | { PCI_DEVICE(0xc0a9, 0x540a), /* Crucial P2 */ |
3533 | .driver_data = NVME_QUIRK_BOGUS_NID, }, | |
200dccd0 SA |
3534 | { PCI_DEVICE(0x1d97, 0x2263), /* Lexar NM610 */ |
3535 | .driver_data = NVME_QUIRK_BOGUS_NID, }, | |
80b26240 A |
3536 | { PCI_DEVICE(0x1d97, 0x2269), /* Lexar NM760 */ |
3537 | .driver_data = NVME_QUIRK_BOGUS_NID, }, | |
4bdf2603 FS |
3538 | { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0061), |
3539 | .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, | |
3540 | { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0065), | |
3541 | .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, | |
3542 | { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x8061), | |
3543 | .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, | |
3544 | { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd00), | |
3545 | .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, | |
3546 | { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd01), | |
3547 | .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, | |
3548 | { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd02), | |
3549 | .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, | |
98f7b86a AS |
3550 | { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001), |
3551 | .driver_data = NVME_QUIRK_SINGLE_VECTOR }, | |
124298bd | 3552 | { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) }, |
66341331 BH |
3553 | { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005), |
3554 | .driver_data = NVME_QUIRK_SINGLE_VECTOR | | |
d38e9f04 | 3555 | NVME_QUIRK_128_BYTES_SQES | |
a2941f6a KB |
3556 | NVME_QUIRK_SHARED_TAGS | |
3557 | NVME_QUIRK_SKIP_CID_GEN }, | |
0b85f59d | 3558 | { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, |
b60503ba MW |
3559 | { 0, } |
3560 | }; | |
3561 | MODULE_DEVICE_TABLE(pci, nvme_id_table); | |
3562 | ||
3563 | static struct pci_driver nvme_driver = { | |
3564 | .name = "nvme", | |
3565 | .id_table = nvme_id_table, | |
3566 | .probe = nvme_probe, | |
8d85fce7 | 3567 | .remove = nvme_remove, |
09ece142 | 3568 | .shutdown = nvme_shutdown, |
d916b1be | 3569 | #ifdef CONFIG_PM_SLEEP |
cd638946 KB |
3570 | .driver = { |
3571 | .pm = &nvme_dev_pm_ops, | |
3572 | }, | |
d916b1be | 3573 | #endif |
74d986ab | 3574 | .sriov_configure = pci_sriov_configure_simple, |
b60503ba MW |
3575 | .err_handler = &nvme_err_handler, |
3576 | }; | |
3577 | ||
3578 | static int __init nvme_init(void) | |
3579 | { | |
81101540 CH |
3580 | BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); |
3581 | BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); | |
3582 | BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); | |
612b7286 | 3583 | BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2); |
c372cdd1 KB |
3584 | BUILD_BUG_ON(DIV_ROUND_UP(nvme_pci_npages_prp(), NVME_CTRL_PAGE_SIZE) > |
3585 | S8_MAX); | |
17c33167 | 3586 | |
9a6327d2 | 3587 | return pci_register_driver(&nvme_driver); |
b60503ba MW |
3588 | } |
3589 | ||
3590 | static void __exit nvme_exit(void) | |
3591 | { | |
3592 | pci_unregister_driver(&nvme_driver); | |
03e0f3a6 | 3593 | flush_workqueue(nvme_wq); |
b60503ba MW |
3594 | } |
3595 | ||
3596 | MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); | |
3597 | MODULE_LICENSE("GPL"); | |
c78b4713 | 3598 | MODULE_VERSION("1.0"); |
b60503ba MW |
3599 | module_init(nvme_init); |
3600 | module_exit(nvme_exit); |