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nvme-rdma: fix potential unbalanced freeze & unfreeze
[linux-2.6-block.git] / drivers / nvme / host / pci.c
CommitLineData
5f37396d 1// SPDX-License-Identifier: GPL-2.0
b60503ba
MW		 2/*
3 * NVM Express device driver
6eb0d698 4 * Copyright (c) 2011-2014, Intel Corporation.
b60503ba
MW		 5 */
6
df4f9bc4 7#include <linux/acpi.h>
18119775 8#include <linux/async.h>
b60503ba 9#include <linux/blkdev.h>
a4aea562 10#include <linux/blk-mq.h>
dca51e78 11#include <linux/blk-mq-pci.h>
fe45e630 12#include <linux/blk-integrity.h>
ff5350a8 13#include <linux/dmi.h>
b60503ba
MW		 14#include <linux/init.h>
15#include <linux/interrupt.h>
16#include <linux/io.h>
99722c8a 17#include <linux/kstrtox.h>
dc90f084 18#include <linux/memremap.h>
b60503ba
MW		 19#include <linux/mm.h>
20#include <linux/module.h>
77bf25ea 21#include <linux/mutex.h>
d0877473 22#include <linux/once.h>
b60503ba 23#include <linux/pci.h>
d916b1be 24#include <linux/suspend.h>
e1e5e564 25#include <linux/t10-pi.h>
b60503ba 26#include <linux/types.h>
2f8e2c87 27#include <linux/io-64-nonatomic-lo-hi.h>
20d3bb92 28#include <linux/io-64-nonatomic-hi-lo.h>
a98e58e5 29#include <linux/sed-opal.h>
0f238ff5 30#include <linux/pci-p2pdma.h>
797a796a 31
604c01d5 32#include "trace.h"
f11bb3e2
CH		 33#include "nvme.h"
34
c1e0cc7e 35#define SQ_SIZE(q) ((q)->q_depth << (q)->sqes)
8a1d09a6 36#define CQ_SIZE(q) ((q)->q_depth * sizeof(struct nvme_completion))
c965809c 37
84173423 38#define SGES_PER_PAGE (NVME_CTRL_PAGE_SIZE / sizeof(struct nvme_sgl_desc))
9d43cf64 39
943e942e
JA		 40/*
41 * These can be higher, but we need to ensure that any command doesn't
42 * require an sg allocation that needs more than a page of data.
43 */
7846c1b5
KB		 44#define NVME_MAX_KB_SZ 8192
45#define NVME_MAX_SEGS 128
46#define NVME_MAX_NR_ALLOCATIONS 5
943e942e 47
58ffacb5 48static int use_threaded_interrupts;
2e21e445 49module_param(use_threaded_interrupts, int, 0444);
58ffacb5 50
8ffaadf7 51static bool use_cmb_sqes = true;
69f4eb9f 52module_param(use_cmb_sqes, bool, 0444);
8ffaadf7
JD		 53MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
54
87ad72a5
CH		 55static unsigned int max_host_mem_size_mb = 128;
56module_param(max_host_mem_size_mb, uint, 0444);
57MODULE_PARM_DESC(max_host_mem_size_mb,
58 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
1fa6aead 59
a7a7cbe3
CK		 60static unsigned int sgl_threshold = SZ_32K;
61module_param(sgl_threshold, uint, 0644);
62MODULE_PARM_DESC(sgl_threshold,
63 "Use SGLs when average request segment size is larger or equal to "
64 "this size. Use 0 to disable SGLs.");
65
27453b45
SG		 66#define NVME_PCI_MIN_QUEUE_SIZE 2
67#define NVME_PCI_MAX_QUEUE_SIZE 4095
b27c1e68 68static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
69static const struct kernel_param_ops io_queue_depth_ops = {
70 .set = io_queue_depth_set,
61f3b896 71 .get = param_get_uint,
b27c1e68 72};
73
61f3b896 74static unsigned int io_queue_depth = 1024;
b27c1e68 75module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
27453b45 76MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2 and < 4096");
b27c1e68 77
9c9e76d5
WZ		 78static int io_queue_count_set(const char *val, const struct kernel_param *kp)
79{
80 unsigned int n;
81 int ret;
82
83 ret = kstrtouint(val, 10, &n);
84 if (ret != 0 || n > num_possible_cpus())
85 return -EINVAL;
86 return param_set_uint(val, kp);
87}
88
89static const struct kernel_param_ops io_queue_count_ops = {
90 .set = io_queue_count_set,
91 .get = param_get_uint,
92};
93
3f68baf7 94static unsigned int write_queues;
9c9e76d5 95module_param_cb(write_queues, &io_queue_count_ops, &write_queues, 0644);
3b6592f7
JA		 96MODULE_PARM_DESC(write_queues,
97 "Number of queues to use for writes. If not set, reads and writes "
98 "will share a queue set.");
99
3f68baf7 100static unsigned int poll_queues;
9c9e76d5 101module_param_cb(poll_queues, &io_queue_count_ops, &poll_queues, 0644);
4b04cc6a
JA		 102MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO.");
103
df4f9bc4
DB		 104static bool noacpi;
105module_param(noacpi, bool, 0444);
106MODULE_PARM_DESC(noacpi, "disable acpi bios quirks");
107
1c63dc66
CH		 108struct nvme_dev;
109struct nvme_queue;
b3fffdef 110
a5cdb68c 111static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
7d879c90 112static void nvme_delete_io_queues(struct nvme_dev *dev);
e917a849 113static void nvme_update_attrs(struct nvme_dev *dev);
d4b4ff8e 114
1c63dc66
CH		 115/*
116 * Represents an NVM Express device. Each nvme_dev is a PCI function.
117 */
118struct nvme_dev {
147b27e4 119 struct nvme_queue *queues;
1c63dc66
CH		 120 struct blk_mq_tag_set tagset;
121 struct blk_mq_tag_set admin_tagset;
122 u32 __iomem *dbs;
123 struct device *dev;
124 struct dma_pool *prp_page_pool;
125 struct dma_pool *prp_small_pool;
1c63dc66
CH		 126 unsigned online_queues;
127 unsigned max_qid;
e20ba6e1 128 unsigned io_queues[HCTX_MAX_TYPES];
22b55601 129 unsigned int num_vecs;
7442ddce 130 u32 q_depth;
c1e0cc7e 131 int io_sqes;
1c63dc66 132 u32 db_stride;
1c63dc66 133 void __iomem *bar;
97f6ef64 134 unsigned long bar_mapped_size;
77bf25ea 135 struct mutex shutdown_lock;
1c63dc66 136 bool subsystem;
1c63dc66 137 u64 cmb_size;
0f238ff5 138 bool cmb_use_sqes;
1c63dc66 139 u32 cmbsz;
202021c1 140 u32 cmbloc;
1c63dc66 141 struct nvme_ctrl ctrl;
d916b1be 142 u32 last_ps;
a5df5e79 143 bool hmb;
87ad72a5 144
943e942e
JA		 145 mempool_t *iod_mempool;
146
87ad72a5 147 /* shadow doorbell buffer support: */
b5f96cb7 148 __le32 *dbbuf_dbs;
f9f38e33 149 dma_addr_t dbbuf_dbs_dma_addr;
b5f96cb7 150 __le32 *dbbuf_eis;
f9f38e33 151 dma_addr_t dbbuf_eis_dma_addr;
87ad72a5
CH		 152
153 /* host memory buffer support: */
154 u64 host_mem_size;
155 u32 nr_host_mem_descs;
4033f35d 156 dma_addr_t host_mem_descs_dma;
87ad72a5
CH		 157 struct nvme_host_mem_buf_desc *host_mem_descs;
158 void **host_mem_desc_bufs;
2a5bcfdd
WZ		 159 unsigned int nr_allocated_queues;
160 unsigned int nr_write_queues;
161 unsigned int nr_poll_queues;
4d115420 162};
1fa6aead 163
b27c1e68 164static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
165{
27453b45
SG		 166 return param_set_uint_minmax(val, kp, NVME_PCI_MIN_QUEUE_SIZE,
167 NVME_PCI_MAX_QUEUE_SIZE);
b27c1e68 168}
169
f9f38e33
HK		 170static inline unsigned int sq_idx(unsigned int qid, u32 stride)
171{
172 return qid * 2 * stride;
173}
174
175static inline unsigned int cq_idx(unsigned int qid, u32 stride)
176{
177 return (qid * 2 + 1) * stride;
178}
179
1c63dc66
CH		 180static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
181{
182 return container_of(ctrl, struct nvme_dev, ctrl);
183}
184
b60503ba
MW		 185/*
186 * An NVM Express queue. Each device has at least two (one for admin
187 * commands and one for I/O commands).
188 */
189struct nvme_queue {
091b6092 190 struct nvme_dev *dev;
1ab0cd69 191 spinlock_t sq_lock;
c1e0cc7e 192 void *sq_cmds;
3a7afd8e
CH		 193 /* only used for poll queues: */
194 spinlock_t cq_poll_lock ____cacheline_aligned_in_smp;
74943d45 195 struct nvme_completion *cqes;
b60503ba
MW		 196 dma_addr_t sq_dma_addr;
197 dma_addr_t cq_dma_addr;
b60503ba 198 u32 __iomem *q_db;
7442ddce 199 u32 q_depth;
7c349dde 200 u16 cq_vector;
b60503ba 201 u16 sq_tail;
38210800 202 u16 last_sq_tail;
b60503ba 203 u16 cq_head;
c30341dc 204 u16 qid;
e9539f47 205 u8 cq_phase;
c1e0cc7e 206 u8 sqes;
4e224106
CH		 207 unsigned long flags;
208#define NVMEQ_ENABLED 0
63223078 209#define NVMEQ_SQ_CMB 1
d1ed6aa1 210#define NVMEQ_DELETE_ERROR 2
7c349dde 211#define NVMEQ_POLLED 3
b5f96cb7
KJ		 212 __le32 *dbbuf_sq_db;
213 __le32 *dbbuf_cq_db;
214 __le32 *dbbuf_sq_ei;
215 __le32 *dbbuf_cq_ei;
d1ed6aa1 216 struct completion delete_done;
b60503ba
MW		 217};
218
7846c1b5
KB		 219union nvme_descriptor {
220 struct nvme_sgl_desc *sg_list;
221 __le64 *prp_list;
222};
223
71bd150c 224/*
9b048119
CH		 225 * The nvme_iod describes the data in an I/O.
226 *
227 * The sg pointer contains the list of PRP/SGL chunk allocations in addition
228 * to the actual struct scatterlist.
71bd150c
CH		 229 */
230struct nvme_iod {
d49187e9 231 struct nvme_request req;
af7fae85 232 struct nvme_command cmd;
52da4f3f 233 bool aborted;
c372cdd1
KB		 234 s8 nr_allocations; /* PRP list pool allocations. 0 means small
235 pool in use */
dff824b2 236 unsigned int dma_len; /* length of single DMA segment mapping */
c4c22c52 237 dma_addr_t first_dma;
783b94bd 238 dma_addr_t meta_dma;
91fb2b60 239 struct sg_table sgt;
7846c1b5 240 union nvme_descriptor list[NVME_MAX_NR_ALLOCATIONS];
b60503ba
MW		 241};
242
2a5bcfdd 243static inline unsigned int nvme_dbbuf_size(struct nvme_dev *dev)
3b6592f7 244{
2a5bcfdd 245 return dev->nr_allocated_queues * 8 * dev->db_stride;
f9f38e33
HK		 246}
247
65a54646 248static void nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
f9f38e33 249{
2a5bcfdd 250 unsigned int mem_size = nvme_dbbuf_size(dev);
f9f38e33 251
65a54646
CH		 252 if (!(dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP))
253 return;
254
58847f12
KB		 255 if (dev->dbbuf_dbs) {
256 /*
257 * Clear the dbbuf memory so the driver doesn't observe stale
258 * values from the previous instantiation.
259 */
260 memset(dev->dbbuf_dbs, 0, mem_size);
261 memset(dev->dbbuf_eis, 0, mem_size);
65a54646 262 return;
58847f12 263 }
f9f38e33
HK		 264
265 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
266 &dev->dbbuf_dbs_dma_addr,
267 GFP_KERNEL);
268 if (!dev->dbbuf_dbs)
65a54646 269 goto fail;
f9f38e33
HK		 270 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
271 &dev->dbbuf_eis_dma_addr,
272 GFP_KERNEL);
65a54646
CH		 273 if (!dev->dbbuf_eis)
274 goto fail_free_dbbuf_dbs;
275 return;
f9f38e33 276
65a54646
CH		 277fail_free_dbbuf_dbs:
278 dma_free_coherent(dev->dev, mem_size, dev->dbbuf_dbs,
279 dev->dbbuf_dbs_dma_addr);
280 dev->dbbuf_dbs = NULL;
281fail:
282 dev_warn(dev->dev, "unable to allocate dma for dbbuf\n");
f9f38e33
HK		 283}
284
285static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
286{
2a5bcfdd 287 unsigned int mem_size = nvme_dbbuf_size(dev);
f9f38e33
HK		 288
289 if (dev->dbbuf_dbs) {
290 dma_free_coherent(dev->dev, mem_size,
291 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
292 dev->dbbuf_dbs = NULL;
293 }
294 if (dev->dbbuf_eis) {
295 dma_free_coherent(dev->dev, mem_size,
296 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
297 dev->dbbuf_eis = NULL;
298 }
299}
300
301static void nvme_dbbuf_init(struct nvme_dev *dev,
302 struct nvme_queue *nvmeq, int qid)
303{
304 if (!dev->dbbuf_dbs || !qid)
305 return;
306
307 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
308 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
309 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
310 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
311}
312
0f0d2c87
MI		 313static void nvme_dbbuf_free(struct nvme_queue *nvmeq)
314{
315 if (!nvmeq->qid)
316 return;
317
318 nvmeq->dbbuf_sq_db = NULL;
319 nvmeq->dbbuf_cq_db = NULL;
320 nvmeq->dbbuf_sq_ei = NULL;
321 nvmeq->dbbuf_cq_ei = NULL;
322}
323
f9f38e33
HK		 324static void nvme_dbbuf_set(struct nvme_dev *dev)
325{
f66e2804 326 struct nvme_command c = { };
0f0d2c87 327 unsigned int i;
f9f38e33
HK		 328
329 if (!dev->dbbuf_dbs)
330 return;
331
f9f38e33
HK		 332 c.dbbuf.opcode = nvme_admin_dbbuf;
333 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
334 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
335
336 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
9bdcfb10 337 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
f9f38e33
HK		 338 /* Free memory and continue on */
339 nvme_dbbuf_dma_free(dev);
0f0d2c87
MI		 340
341 for (i = 1; i <= dev->online_queues; i++)
342 nvme_dbbuf_free(&dev->queues[i]);
f9f38e33
HK		 343 }
344}
345
346static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
347{
348 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
349}
350
351/* Update dbbuf and return true if an MMIO is required */
b5f96cb7
KJ		 352static bool nvme_dbbuf_update_and_check_event(u16 value, __le32 *dbbuf_db,
353 volatile __le32 *dbbuf_ei)
f9f38e33
HK		 354{
355 if (dbbuf_db) {
b5f96cb7 356 u16 old_value, event_idx;
f9f38e33
HK		 357
358 /*
359 * Ensure that the queue is written before updating
360 * the doorbell in memory
361 */
362 wmb();
363
b5f96cb7
KJ		 364 old_value = le32_to_cpu(*dbbuf_db);
365 *dbbuf_db = cpu_to_le32(value);
f9f38e33 366
f1ed3df2
MW		 367 /*
368 * Ensure that the doorbell is updated before reading the event
369 * index from memory. The controller needs to provide similar
370 * ordering to ensure the envent index is updated before reading
371 * the doorbell.
372 */
373 mb();
374
b5f96cb7
KJ		 375 event_idx = le32_to_cpu(*dbbuf_ei);
376 if (!nvme_dbbuf_need_event(event_idx, value, old_value))
f9f38e33
HK		 377 return false;
378 }
379
380 return true;
b60503ba
MW		 381}
382
ac3dd5bd
JA		 383/*
384 * Will slightly overestimate the number of pages needed. This is OK
385 * as it only leads to a small amount of wasted memory for the lifetime of
386 * the I/O.
387 */
b13c6393 388static int nvme_pci_npages_prp(void)
ac3dd5bd 389{
c89a529e
KB		 390 unsigned max_bytes = (NVME_MAX_KB_SZ * 1024) + NVME_CTRL_PAGE_SIZE;
391 unsigned nprps = DIV_ROUND_UP(max_bytes, NVME_CTRL_PAGE_SIZE);
84173423 392 return DIV_ROUND_UP(8 * nprps, NVME_CTRL_PAGE_SIZE - 8);
ac3dd5bd
JA		 393}
394
a4aea562
MB		 395static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
396 unsigned int hctx_idx)
e85248e5 397{
0da7feaa 398 struct nvme_dev *dev = to_nvme_dev(data);
147b27e4 399 struct nvme_queue *nvmeq = &dev->queues[0];
a4aea562 400
42483228
KB		 401 WARN_ON(hctx_idx != 0);
402 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
42483228 403
a4aea562
MB		 404 hctx->driver_data = nvmeq;
405 return 0;
e85248e5
MW		 406}
407
a4aea562
MB		 408static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
409 unsigned int hctx_idx)
b60503ba 410{
0da7feaa 411 struct nvme_dev *dev = to_nvme_dev(data);
147b27e4 412 struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
a4aea562 413
42483228 414 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
a4aea562
MB		 415 hctx->driver_data = nvmeq;
416 return 0;
b60503ba
MW		 417}
418
e559398f
CH		 419static int nvme_pci_init_request(struct blk_mq_tag_set *set,
420 struct request *req, unsigned int hctx_idx,
421 unsigned int numa_node)
b60503ba 422{
f4800d6d 423 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
59e29ce6 424
4a4d9bc0 425 nvme_req(req)->ctrl = set->driver_data;
f4b9e6c9 426 nvme_req(req)->cmd = &iod->cmd;
a4aea562
MB		 427 return 0;
428}
429
3b6592f7
JA		 430static int queue_irq_offset(struct nvme_dev *dev)
431{
432 /* if we have more than 1 vec, admin queue offsets us by 1 */
433 if (dev->num_vecs > 1)
434 return 1;
435
436 return 0;
437}
438
a4e1d0b7 439static void nvme_pci_map_queues(struct blk_mq_tag_set *set)
dca51e78 440{
0da7feaa 441 struct nvme_dev *dev = to_nvme_dev(set->driver_data);
3b6592f7
JA		 442 int i, qoff, offset;
443
444 offset = queue_irq_offset(dev);
445 for (i = 0, qoff = 0; i < set->nr_maps; i++) {
446 struct blk_mq_queue_map *map = &set->map[i];
447
448 map->nr_queues = dev->io_queues[i];
449 if (!map->nr_queues) {
e20ba6e1 450 BUG_ON(i == HCTX_TYPE_DEFAULT);
7e849dd9 451 continue;
3b6592f7
JA		 452 }
453
4b04cc6a
JA		 454 /*
455 * The poll queue(s) doesn't have an IRQ (and hence IRQ
456 * affinity), so use the regular blk-mq cpu mapping
457 */
3b6592f7 458 map->queue_offset = qoff;
cb9e0e50 459 if (i != HCTX_TYPE_POLL && offset)
4b04cc6a
JA		 460 blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset);
461 else
462 blk_mq_map_queues(map);
3b6592f7
JA		 463 qoff += map->nr_queues;
464 offset += map->nr_queues;
465 }
dca51e78
CH		 466}
467
38210800
KB		 468/*
469 * Write sq tail if we are asked to, or if the next command would wrap.
470 */
471static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq)
04f3eafd 472{
38210800
KB		 473 if (!write_sq) {
474 u16 next_tail = nvmeq->sq_tail + 1;
475
476 if (next_tail == nvmeq->q_depth)
477 next_tail = 0;
478 if (next_tail != nvmeq->last_sq_tail)
479 return;
480 }
481
04f3eafd
JA		 482 if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail,
483 nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei))
484 writel(nvmeq->sq_tail, nvmeq->q_db);
38210800 485 nvmeq->last_sq_tail = nvmeq->sq_tail;
04f3eafd
JA		 486}
487
3233b94c
JA		 488static inline void nvme_sq_copy_cmd(struct nvme_queue *nvmeq,
489 struct nvme_command *cmd)
b60503ba 490{
c1e0cc7e 491 memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes),
3233b94c 492 absolute_pointer(cmd), sizeof(*cmd));
90ea5ca4
CH		 493 if (++nvmeq->sq_tail == nvmeq->q_depth)
494 nvmeq->sq_tail = 0;
04f3eafd
JA		 495}
496
497static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx)
498{
499 struct nvme_queue *nvmeq = hctx->driver_data;
500
501 spin_lock(&nvmeq->sq_lock);
38210800
KB		 502 if (nvmeq->sq_tail != nvmeq->last_sq_tail)
503 nvme_write_sq_db(nvmeq, true);
90ea5ca4 504 spin_unlock(&nvmeq->sq_lock);
b60503ba
MW		 505}
506
ae582935
KB		 507static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req,
508 int nseg)
955b1b5a 509{
a53232cb 510 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
955b1b5a
MI		 511 unsigned int avg_seg_size;
512
20469a37 513 avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
955b1b5a 514
253a0b76 515 if (!nvme_ctrl_sgl_supported(&dev->ctrl))
955b1b5a 516 return false;
a53232cb 517 if (!nvmeq->qid)
955b1b5a
MI		 518 return false;
519 if (!sgl_threshold || avg_seg_size < sgl_threshold)
520 return false;
521 return true;
522}
523
9275c206 524static void nvme_free_prps(struct nvme_dev *dev, struct request *req)
b60503ba 525{
6c3c05b0 526 const int last_prp = NVME_CTRL_PAGE_SIZE / sizeof(__le64) - 1;
9275c206
CH		 527 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
528 dma_addr_t dma_addr = iod->first_dma;
eca18b23 529 int i;
eca18b23 530
c372cdd1 531 for (i = 0; i < iod->nr_allocations; i++) {
7846c1b5 532 __le64 *prp_list = iod->list[i].prp_list;
9275c206
CH		 533 dma_addr_t next_dma_addr = le64_to_cpu(prp_list[last_prp]);
534
535 dma_pool_free(dev->prp_page_pool, prp_list, dma_addr);
536 dma_addr = next_dma_addr;
7fe07d14 537 }
9275c206 538}
dff824b2 539
9275c206
CH		 540static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
541{
542 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3 543
9275c206
CH		 544 if (iod->dma_len) {
545 dma_unmap_page(dev->dev, iod->first_dma, iod->dma_len,
546 rq_dma_dir(req));
547 return;
eca18b23 548 }
ac3dd5bd 549
91fb2b60
LG		 550 WARN_ON_ONCE(!iod->sgt.nents);
551
552 dma_unmap_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req), 0);
9275c206 553
c372cdd1 554 if (iod->nr_allocations == 0)
7846c1b5 555 dma_pool_free(dev->prp_small_pool, iod->list[0].sg_list,
9275c206 556 iod->first_dma);
8f0edf45 557 else if (iod->nr_allocations == 1)
7846c1b5 558 dma_pool_free(dev->prp_page_pool, iod->list[0].sg_list,
9275c206 559 iod->first_dma);
9275c206
CH		 560 else
561 nvme_free_prps(dev, req);
91fb2b60 562 mempool_free(iod->sgt.sgl, dev->iod_mempool);
b4ff9c8d
KB		 563}
564
d0877473
KB		 565static void nvme_print_sgl(struct scatterlist *sgl, int nents)
566{
567 int i;
568 struct scatterlist *sg;
569
570 for_each_sg(sgl, sg, nents, i) {
571 dma_addr_t phys = sg_phys(sg);
572 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
573 "dma_address:%pad dma_length:%d\n",
574 i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
575 sg_dma_len(sg));
576 }
577}
578
a7a7cbe3
CK		 579static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
580 struct request *req, struct nvme_rw_command *cmnd)
ff22b54f 581{
f4800d6d 582 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
99802a7a 583 struct dma_pool *pool;
b131c61d 584 int length = blk_rq_payload_bytes(req);
91fb2b60 585 struct scatterlist *sg = iod->sgt.sgl;
ff22b54f
MW		 586 int dma_len = sg_dma_len(sg);
587 u64 dma_addr = sg_dma_address(sg);
6c3c05b0 588 int offset = dma_addr & (NVME_CTRL_PAGE_SIZE - 1);
e025344c
SMM		 589 __le64 *prp_list;
590 dma_addr_t prp_dma;
eca18b23 591 int nprps, i;
ff22b54f 592
6c3c05b0 593 length -= (NVME_CTRL_PAGE_SIZE - offset);
5228b328
JS		 594 if (length <= 0) {
595 iod->first_dma = 0;
a7a7cbe3 596 goto done;
5228b328 597 }
ff22b54f 598
6c3c05b0 599 dma_len -= (NVME_CTRL_PAGE_SIZE - offset);
ff22b54f 600 if (dma_len) {
6c3c05b0 601 dma_addr += (NVME_CTRL_PAGE_SIZE - offset);
ff22b54f
MW		 602 } else {
603 sg = sg_next(sg);
604 dma_addr = sg_dma_address(sg);
605 dma_len = sg_dma_len(sg);
606 }
607
6c3c05b0 608 if (length <= NVME_CTRL_PAGE_SIZE) {
edd10d33 609 iod->first_dma = dma_addr;
a7a7cbe3 610 goto done;
e025344c
SMM		 611 }
612
6c3c05b0 613 nprps = DIV_ROUND_UP(length, NVME_CTRL_PAGE_SIZE);
99802a7a
MW		 614 if (nprps <= (256 / 8)) {
615 pool = dev->prp_small_pool;
c372cdd1 616 iod->nr_allocations = 0;
99802a7a
MW		 617 } else {
618 pool = dev->prp_page_pool;
c372cdd1 619 iod->nr_allocations = 1;
99802a7a
MW		 620 }
621
69d2b571 622 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
b77954cb 623 if (!prp_list) {
c372cdd1 624 iod->nr_allocations = -1;
86eea289 625 return BLK_STS_RESOURCE;
b77954cb 626 }
7846c1b5 627 iod->list[0].prp_list = prp_list;
eca18b23 628 iod->first_dma = prp_dma;
e025344c
SMM		 629 i = 0;
630 for (;;) {
6c3c05b0 631 if (i == NVME_CTRL_PAGE_SIZE >> 3) {
e025344c 632 __le64 *old_prp_list = prp_list;
69d2b571 633 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
eca18b23 634 if (!prp_list)
fa073216 635 goto free_prps;
7846c1b5 636 iod->list[iod->nr_allocations++].prp_list = prp_list;
7523d834
MW		 637 prp_list[0] = old_prp_list[i - 1];
638 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
639 i = 1;
e025344c
SMM		 640 }
641 prp_list[i++] = cpu_to_le64(dma_addr);
6c3c05b0
CK		 642 dma_len -= NVME_CTRL_PAGE_SIZE;
643 dma_addr += NVME_CTRL_PAGE_SIZE;
644 length -= NVME_CTRL_PAGE_SIZE;
e025344c
SMM		 645 if (length <= 0)
646 break;
647 if (dma_len > 0)
648 continue;
86eea289
KB		 649 if (unlikely(dma_len < 0))
650 goto bad_sgl;
e025344c
SMM		 651 sg = sg_next(sg);
652 dma_addr = sg_dma_address(sg);
653 dma_len = sg_dma_len(sg);
ff22b54f 654 }
a7a7cbe3 655done:
91fb2b60 656 cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sgt.sgl));
a7a7cbe3 657 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
86eea289 658 return BLK_STS_OK;
fa073216
CH		 659free_prps:
660 nvme_free_prps(dev, req);
661 return BLK_STS_RESOURCE;
662bad_sgl:
91fb2b60 663 WARN(DO_ONCE(nvme_print_sgl, iod->sgt.sgl, iod->sgt.nents),
d0877473 664 "Invalid SGL for payload:%d nents:%d\n",
91fb2b60 665 blk_rq_payload_bytes(req), iod->sgt.nents);
86eea289 666 return BLK_STS_IOERR;
ff22b54f
MW		 667}
668
a7a7cbe3
CK		 669static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
670 struct scatterlist *sg)
671{
672 sge->addr = cpu_to_le64(sg_dma_address(sg));
673 sge->length = cpu_to_le32(sg_dma_len(sg));
674 sge->type = NVME_SGL_FMT_DATA_DESC << 4;
675}
676
677static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
678 dma_addr_t dma_addr, int entries)
679{
680 sge->addr = cpu_to_le64(dma_addr);
01df742d
KB		 681 sge->length = cpu_to_le32(entries * sizeof(*sge));
682 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
a7a7cbe3
CK		 683}
684
685static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
91fb2b60 686 struct request *req, struct nvme_rw_command *cmd)
a7a7cbe3
CK		 687{
688 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3
CK		 689 struct dma_pool *pool;
690 struct nvme_sgl_desc *sg_list;
91fb2b60
LG		 691 struct scatterlist *sg = iod->sgt.sgl;
692 unsigned int entries = iod->sgt.nents;
a7a7cbe3 693 dma_addr_t sgl_dma;
b0f2853b 694 int i = 0;
a7a7cbe3 695
a7a7cbe3
CK		 696 /* setting the transfer type as SGL */
697 cmd->flags = NVME_CMD_SGL_METABUF;
698
b0f2853b 699 if (entries == 1) {
a7a7cbe3
CK		 700 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
701 return BLK_STS_OK;
702 }
703
704 if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
705 pool = dev->prp_small_pool;
c372cdd1 706 iod->nr_allocations = 0;
a7a7cbe3
CK		 707 } else {
708 pool = dev->prp_page_pool;
c372cdd1 709 iod->nr_allocations = 1;
a7a7cbe3
CK		 710 }
711
712 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
713 if (!sg_list) {
c372cdd1 714 iod->nr_allocations = -1;
a7a7cbe3
CK		 715 return BLK_STS_RESOURCE;
716 }
717
7846c1b5 718 iod->list[0].sg_list = sg_list;
a7a7cbe3
CK		 719 iod->first_dma = sgl_dma;
720
721 nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
a7a7cbe3 722 do {
a7a7cbe3 723 nvme_pci_sgl_set_data(&sg_list[i++], sg);
a7a7cbe3 724 sg = sg_next(sg);
b0f2853b 725 } while (--entries > 0);
a7a7cbe3 726
a7a7cbe3
CK		 727 return BLK_STS_OK;
728}
729
dff824b2
CH		 730static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev,
731 struct request *req, struct nvme_rw_command *cmnd,
732 struct bio_vec *bv)
733{
734 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
6c3c05b0
CK		 735 unsigned int offset = bv->bv_offset & (NVME_CTRL_PAGE_SIZE - 1);
736 unsigned int first_prp_len = NVME_CTRL_PAGE_SIZE - offset;
dff824b2
CH		 737
738 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
739 if (dma_mapping_error(dev->dev, iod->first_dma))
740 return BLK_STS_RESOURCE;
741 iod->dma_len = bv->bv_len;
742
743 cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma);
744 if (bv->bv_len > first_prp_len)
745 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len);
a56ea614
LR		 746 else
747 cmnd->dptr.prp2 = 0;
359c1f88 748 return BLK_STS_OK;
dff824b2
CH		 749}
750
29791057
CH		 751static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev,
752 struct request *req, struct nvme_rw_command *cmnd,
753 struct bio_vec *bv)
754{
755 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
756
757 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
758 if (dma_mapping_error(dev->dev, iod->first_dma))
759 return BLK_STS_RESOURCE;
760 iod->dma_len = bv->bv_len;
761
049bf372 762 cmnd->flags = NVME_CMD_SGL_METABUF;
29791057
CH		 763 cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma);
764 cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len);
765 cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4;
359c1f88 766 return BLK_STS_OK;
29791057
CH		 767}
768
fc17b653 769static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
b131c61d 770 struct nvme_command *cmnd)
d29ec824 771{
f4800d6d 772 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
70479b71 773 blk_status_t ret = BLK_STS_RESOURCE;
91fb2b60 774 int rc;
d29ec824 775
dff824b2 776 if (blk_rq_nr_phys_segments(req) == 1) {
a53232cb 777 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
dff824b2
CH		 778 struct bio_vec bv = req_bvec(req);
779
780 if (!is_pci_p2pdma_page(bv.bv_page)) {
6c3c05b0 781 if (bv.bv_offset + bv.bv_len <= NVME_CTRL_PAGE_SIZE * 2)
dff824b2
CH		 782 return nvme_setup_prp_simple(dev, req,
783 &cmnd->rw, &bv);
29791057 784
a53232cb 785 if (nvmeq->qid && sgl_threshold &&
253a0b76 786 nvme_ctrl_sgl_supported(&dev->ctrl))
29791057
CH		 787 return nvme_setup_sgl_simple(dev, req,
788 &cmnd->rw, &bv);
dff824b2
CH		 789 }
790 }
791
792 iod->dma_len = 0;
91fb2b60
LG		 793 iod->sgt.sgl = mempool_alloc(dev->iod_mempool, GFP_ATOMIC);
794 if (!iod->sgt.sgl)
d43f1ccf 795 return BLK_STS_RESOURCE;
91fb2b60
LG		 796 sg_init_table(iod->sgt.sgl, blk_rq_nr_phys_segments(req));
797 iod->sgt.orig_nents = blk_rq_map_sg(req->q, req, iod->sgt.sgl);
798 if (!iod->sgt.orig_nents)
fa073216 799 goto out_free_sg;
d29ec824 800
91fb2b60
LG		 801 rc = dma_map_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req),
802 DMA_ATTR_NO_WARN);
803 if (rc) {
804 if (rc == -EREMOTEIO)
805 ret = BLK_STS_TARGET;
fa073216 806 goto out_free_sg;
91fb2b60 807 }
d29ec824 808
b6c0c237 809 if (nvme_pci_use_sgls(dev, req, iod->sgt.nents))
91fb2b60 810 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw);
a7a7cbe3
CK		 811 else
812 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
86eea289 813 if (ret != BLK_STS_OK)
fa073216
CH		 814 goto out_unmap_sg;
815 return BLK_STS_OK;
816
817out_unmap_sg:
91fb2b60 818 dma_unmap_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req), 0);
fa073216 819out_free_sg:
91fb2b60 820 mempool_free(iod->sgt.sgl, dev->iod_mempool);
4aedb705
CH		 821 return ret;
822}
3045c0d0 823
4aedb705
CH		 824static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req,
825 struct nvme_command *cmnd)
826{
827 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
00df5cb4 828
4aedb705
CH		 829 iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req),
830 rq_dma_dir(req), 0);
831 if (dma_mapping_error(dev->dev, iod->meta_dma))
832 return BLK_STS_IOERR;
833 cmnd->rw.metadata = cpu_to_le64(iod->meta_dma);
359c1f88 834 return BLK_STS_OK;
00df5cb4
MW		 835}
836
62451a2b 837static blk_status_t nvme_prep_rq(struct nvme_dev *dev, struct request *req)
edd10d33 838{
9b048119 839 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
ebe6d874 840 blk_status_t ret;
e1e5e564 841
52da4f3f 842 iod->aborted = false;
c372cdd1 843 iod->nr_allocations = -1;
91fb2b60 844 iod->sgt.nents = 0;
9b048119 845
62451a2b 846 ret = nvme_setup_cmd(req->q->queuedata, req);
fc17b653 847 if (ret)
f4800d6d 848 return ret;
a4aea562 849
fc17b653 850 if (blk_rq_nr_phys_segments(req)) {
62451a2b 851 ret = nvme_map_data(dev, req, &iod->cmd);
fc17b653 852 if (ret)
9b048119 853 goto out_free_cmd;
fc17b653 854 }
a4aea562 855
4aedb705 856 if (blk_integrity_rq(req)) {
62451a2b 857 ret = nvme_map_metadata(dev, req, &iod->cmd);
4aedb705
CH		 858 if (ret)
859 goto out_unmap_data;
860 }
861
6887fc64 862 nvme_start_request(req);
fc17b653 863 return BLK_STS_OK;
4aedb705
CH		 864out_unmap_data:
865 nvme_unmap_data(dev, req);
f9d03f96
CH		 866out_free_cmd:
867 nvme_cleanup_cmd(req);
ba1ca37e 868 return ret;
b60503ba 869}
e1e5e564 870
62451a2b
JA		 871/*
872 * NOTE: ns is NULL when called on the admin queue.
873 */
874static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
875 const struct blk_mq_queue_data *bd)
876{
877 struct nvme_queue *nvmeq = hctx->driver_data;
878 struct nvme_dev *dev = nvmeq->dev;
879 struct request *req = bd->rq;
880 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
881 blk_status_t ret;
882
883 /*
884 * We should not need to do this, but we're still using this to
885 * ensure we can drain requests on a dying queue.
886 */
887 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
888 return BLK_STS_IOERR;
889
890 if (unlikely(!nvme_check_ready(&dev->ctrl, req, true)))
891 return nvme_fail_nonready_command(&dev->ctrl, req);
892
893 ret = nvme_prep_rq(dev, req);
894 if (unlikely(ret))
895 return ret;
896 spin_lock(&nvmeq->sq_lock);
897 nvme_sq_copy_cmd(nvmeq, &iod->cmd);
898 nvme_write_sq_db(nvmeq, bd->last);
899 spin_unlock(&nvmeq->sq_lock);
900 return BLK_STS_OK;
901}
902
d62cbcf6
JA		 903static void nvme_submit_cmds(struct nvme_queue *nvmeq, struct request **rqlist)
904{
905 spin_lock(&nvmeq->sq_lock);
906 while (!rq_list_empty(*rqlist)) {
907 struct request *req = rq_list_pop(rqlist);
908 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
909
910 nvme_sq_copy_cmd(nvmeq, &iod->cmd);
911 }
912 nvme_write_sq_db(nvmeq, true);
913 spin_unlock(&nvmeq->sq_lock);
914}
915
916static bool nvme_prep_rq_batch(struct nvme_queue *nvmeq, struct request *req)
917{
918 /*
919 * We should not need to do this, but we're still using this to
920 * ensure we can drain requests on a dying queue.
921 */
922 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
923 return false;
924 if (unlikely(!nvme_check_ready(&nvmeq->dev->ctrl, req, true)))
925 return false;
926
927 req->mq_hctx->tags->rqs[req->tag] = req;
928 return nvme_prep_rq(nvmeq->dev, req) == BLK_STS_OK;
929}
930
931static void nvme_queue_rqs(struct request **rqlist)
932{
6bfec799 933 struct request *req, *next, *prev = NULL;
d62cbcf6
JA		 934 struct request *requeue_list = NULL;
935
6bfec799 936 rq_list_for_each_safe(rqlist, req, next) {
d62cbcf6
JA		 937 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
938
939 if (!nvme_prep_rq_batch(nvmeq, req)) {
940 /* detach 'req' and add to remainder list */
6bfec799
KB		 941 rq_list_move(rqlist, &requeue_list, req, prev);
942
943 req = prev;
944 if (!req)
945 continue;
d62cbcf6
JA		 946 }
947
6bfec799 948 if (!next || req->mq_hctx != next->mq_hctx) {
d62cbcf6 949 /* detach rest of list, and submit */
6bfec799 950 req->rq_next = NULL;
d62cbcf6 951 nvme_submit_cmds(nvmeq, rqlist);
6bfec799
KB		 952 *rqlist = next;
953 prev = NULL;
954 } else
955 prev = req;
956 }
d62cbcf6
JA		 957
958 *rqlist = requeue_list;
959}
960
c234a653 961static __always_inline void nvme_pci_unmap_rq(struct request *req)
eee417b0 962{
a53232cb
KB		 963 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
964 struct nvme_dev *dev = nvmeq->dev;
965
966 if (blk_integrity_rq(req)) {
967 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a4aea562 968
4aedb705 969 dma_unmap_page(dev->dev, iod->meta_dma,
b8f6446b 970 rq_integrity_vec(req)->bv_len, rq_dma_dir(req));
a53232cb
KB		 971 }
972
b15c592d 973 if (blk_rq_nr_phys_segments(req))
4aedb705 974 nvme_unmap_data(dev, req);
c234a653
JA		 975}
976
977static void nvme_pci_complete_rq(struct request *req)
978{
979 nvme_pci_unmap_rq(req);
77f02a7a 980 nvme_complete_rq(req);
b60503ba
MW		 981}
982
c234a653
JA		 983static void nvme_pci_complete_batch(struct io_comp_batch *iob)
984{
985 nvme_complete_batch(iob, nvme_pci_unmap_rq);
986}
987
d783e0bd 988/* We read the CQE phase first to check if the rest of the entry is valid */
750dde44 989static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq)
d783e0bd 990{
74943d45
KB		 991 struct nvme_completion *hcqe = &nvmeq->cqes[nvmeq->cq_head];
992
993 return (le16_to_cpu(READ_ONCE(hcqe->status)) & 1) == nvmeq->cq_phase;
d783e0bd
MR		 994}
995
eb281c82 996static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
b60503ba 997{
eb281c82 998 u16 head = nvmeq->cq_head;
adf68f21 999
397c699f
KB		 1000 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
1001 nvmeq->dbbuf_cq_ei))
1002 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
eb281c82 1003}
aae239e1 1004
cfa27356
CH		 1005static inline struct blk_mq_tags *nvme_queue_tagset(struct nvme_queue *nvmeq)
1006{
1007 if (!nvmeq->qid)
1008 return nvmeq->dev->admin_tagset.tags[0];
1009 return nvmeq->dev->tagset.tags[nvmeq->qid - 1];
1010}
1011
c234a653
JA		 1012static inline void nvme_handle_cqe(struct nvme_queue *nvmeq,
1013 struct io_comp_batch *iob, u16 idx)
83a12fb7 1014{
74943d45 1015 struct nvme_completion *cqe = &nvmeq->cqes[idx];
62df8016 1016 __u16 command_id = READ_ONCE(cqe->command_id);
83a12fb7 1017 struct request *req;
adf68f21 1018
83a12fb7
SG		 1019 /*
1020 * AEN requests are special as they don't time out and can
1021 * survive any kind of queue freeze and often don't respond to
1022 * aborts. We don't even bother to allocate a struct request
1023 * for them but rather special case them here.
1024 */
62df8016 1025 if (unlikely(nvme_is_aen_req(nvmeq->qid, command_id))) {
83a12fb7
SG		 1026 nvme_complete_async_event(&nvmeq->dev->ctrl,
1027 cqe->status, &cqe->result);
a0fa9647 1028 return;
83a12fb7 1029 }
b60503ba 1030
e7006de6 1031 req = nvme_find_rq(nvme_queue_tagset(nvmeq), command_id);
50b7c243
XT		 1032 if (unlikely(!req)) {
1033 dev_warn(nvmeq->dev->ctrl.device,
1034 "invalid id %d completed on queue %d\n",
62df8016 1035 command_id, le16_to_cpu(cqe->sq_id));
50b7c243
XT		 1036 return;
1037 }
1038
604c01d5 1039 trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail);
c234a653
JA		 1040 if (!nvme_try_complete_req(req, cqe->status, cqe->result) &&
1041 !blk_mq_add_to_batch(req, iob, nvme_req(req)->status,
1042 nvme_pci_complete_batch))
ff029451 1043 nvme_pci_complete_rq(req);
83a12fb7 1044}
b60503ba 1045
5cb525c8
JA		 1046static inline void nvme_update_cq_head(struct nvme_queue *nvmeq)
1047{
a0aac973 1048 u32 tmp = nvmeq->cq_head + 1;
a8de6639
AD		 1049
1050 if (tmp == nvmeq->q_depth) {
5cb525c8 1051 nvmeq->cq_head = 0;
e2a366a4 1052 nvmeq->cq_phase ^= 1;
a8de6639
AD		 1053 } else {
1054 nvmeq->cq_head = tmp;
b60503ba 1055 }
a0fa9647
JA		 1056}
1057
c234a653
JA		 1058static inline int nvme_poll_cq(struct nvme_queue *nvmeq,
1059 struct io_comp_batch *iob)
a0fa9647 1060{
1052b8ac 1061 int found = 0;
b60503ba 1062
1052b8ac 1063 while (nvme_cqe_pending(nvmeq)) {
bf392a5d 1064 found++;
b69e2ef2
KB		 1065 /*
1066 * load-load control dependency between phase and the rest of
1067 * the cqe requires a full read memory barrier
1068 */
1069 dma_rmb();
c234a653 1070 nvme_handle_cqe(nvmeq, iob, nvmeq->cq_head);
5cb525c8 1071 nvme_update_cq_head(nvmeq);
920d13a8 1072 }
eb281c82 1073
324b494c 1074 if (found)
920d13a8 1075 nvme_ring_cq_doorbell(nvmeq);
5cb525c8 1076 return found;
b60503ba
MW		 1077}
1078
1079static irqreturn_t nvme_irq(int irq, void *data)
58ffacb5 1080{
58ffacb5 1081 struct nvme_queue *nvmeq = data;
4f502245 1082 DEFINE_IO_COMP_BATCH(iob);
5cb525c8 1083
4f502245
JA		 1084 if (nvme_poll_cq(nvmeq, &iob)) {
1085 if (!rq_list_empty(iob.req_list))
1086 nvme_pci_complete_batch(&iob);
05fae499 1087 return IRQ_HANDLED;
4f502245 1088 }
05fae499 1089 return IRQ_NONE;
58ffacb5
MW		 1090}
1091
1092static irqreturn_t nvme_irq_check(int irq, void *data)
1093{
1094 struct nvme_queue *nvmeq = data;
4e523547 1095
750dde44 1096 if (nvme_cqe_pending(nvmeq))
d783e0bd
MR		 1097 return IRQ_WAKE_THREAD;
1098 return IRQ_NONE;
58ffacb5
MW		 1099}
1100
0b2a8a9f 1101/*
fa059b85 1102 * Poll for completions for any interrupt driven queue
0b2a8a9f
CH		 1103 * Can be called from any context.
1104 */
fa059b85 1105static void nvme_poll_irqdisable(struct nvme_queue *nvmeq)
a0fa9647 1106{
3a7afd8e 1107 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
a0fa9647 1108
fa059b85 1109 WARN_ON_ONCE(test_bit(NVMEQ_POLLED, &nvmeq->flags));
442e19b7 1110
fa059b85 1111 disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
c234a653 1112 nvme_poll_cq(nvmeq, NULL);
fa059b85 1113 enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
a0fa9647
JA		 1114}
1115
5a72e899 1116static int nvme_poll(struct blk_mq_hw_ctx *hctx, struct io_comp_batch *iob)
dabcefab
JA		 1117{
1118 struct nvme_queue *nvmeq = hctx->driver_data;
dabcefab
JA		 1119 bool found;
1120
1121 if (!nvme_cqe_pending(nvmeq))
1122 return 0;
1123
3a7afd8e 1124 spin_lock(&nvmeq->cq_poll_lock);
c234a653 1125 found = nvme_poll_cq(nvmeq, iob);
3a7afd8e 1126 spin_unlock(&nvmeq->cq_poll_lock);
dabcefab 1127
dabcefab
JA		 1128 return found;
1129}
1130
ad22c355 1131static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
b60503ba 1132{
f866fc42 1133 struct nvme_dev *dev = to_nvme_dev(ctrl);
147b27e4 1134 struct nvme_queue *nvmeq = &dev->queues[0];
f66e2804 1135 struct nvme_command c = { };
b60503ba 1136
a4aea562 1137 c.common.opcode = nvme_admin_async_event;
ad22c355 1138 c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
3233b94c
JA		 1139
1140 spin_lock(&nvmeq->sq_lock);
1141 nvme_sq_copy_cmd(nvmeq, &c);
1142 nvme_write_sq_db(nvmeq, true);
1143 spin_unlock(&nvmeq->sq_lock);
f705f837
CH		 1144}
1145
b60503ba 1146static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
f705f837 1147{
f66e2804 1148 struct nvme_command c = { };
b60503ba 1149
b60503ba
MW		 1150 c.delete_queue.opcode = opcode;
1151 c.delete_queue.qid = cpu_to_le16(id);
1152
1c63dc66 1153 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1154}
1155
b60503ba 1156static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
a8e3e0bb 1157 struct nvme_queue *nvmeq, s16 vector)
b60503ba 1158{
f66e2804 1159 struct nvme_command c = { };
4b04cc6a
JA		 1160 int flags = NVME_QUEUE_PHYS_CONTIG;
1161
7c349dde 1162 if (!test_bit(NVMEQ_POLLED, &nvmeq->flags))
4b04cc6a 1163 flags |= NVME_CQ_IRQ_ENABLED;
b60503ba 1164
d29ec824 1165 /*
16772ae6 1166 * Note: we (ab)use the fact that the prp fields survive if no data
d29ec824
CH		 1167 * is attached to the request.
1168 */
b60503ba
MW		 1169 c.create_cq.opcode = nvme_admin_create_cq;
1170 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1171 c.create_cq.cqid = cpu_to_le16(qid);
1172 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1173 c.create_cq.cq_flags = cpu_to_le16(flags);
7c349dde 1174 c.create_cq.irq_vector = cpu_to_le16(vector);
b60503ba 1175
1c63dc66 1176 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1177}
1178
1179static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1180 struct nvme_queue *nvmeq)
1181{
9abd68ef 1182 struct nvme_ctrl *ctrl = &dev->ctrl;
f66e2804 1183 struct nvme_command c = { };
81c1cd98 1184 int flags = NVME_QUEUE_PHYS_CONTIG;
b60503ba 1185
9abd68ef
JA		 1186 /*
1187 * Some drives have a bug that auto-enables WRRU if MEDIUM isn't
1188 * set. Since URGENT priority is zeroes, it makes all queues
1189 * URGENT.
1190 */
1191 if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ)
1192 flags |= NVME_SQ_PRIO_MEDIUM;
1193
d29ec824 1194 /*
16772ae6 1195 * Note: we (ab)use the fact that the prp fields survive if no data
d29ec824
CH		 1196 * is attached to the request.
1197 */
b60503ba
MW		 1198 c.create_sq.opcode = nvme_admin_create_sq;
1199 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1200 c.create_sq.sqid = cpu_to_le16(qid);
1201 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1202 c.create_sq.sq_flags = cpu_to_le16(flags);
1203 c.create_sq.cqid = cpu_to_le16(qid);
1204
1c63dc66 1205 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1206}
1207
1208static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1209{
1210 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1211}
1212
1213static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1214{
1215 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1216}
1217
de671d61 1218static enum rq_end_io_ret abort_endio(struct request *req, blk_status_t error)
bc5fc7e4 1219{
a53232cb 1220 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
e44ac588 1221
27fa9bc5
CH		 1222 dev_warn(nvmeq->dev->ctrl.device,
1223 "Abort status: 0x%x", nvme_req(req)->status);
e7a2a87d 1224 atomic_inc(&nvmeq->dev->ctrl.abort_limit);
e7a2a87d 1225 blk_mq_free_request(req);
de671d61 1226 return RQ_END_IO_NONE;
bc5fc7e4
MW		 1227}
1228
b2a0eb1a
KB		 1229static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1230{
b2a0eb1a
KB		 1231 /* If true, indicates loss of adapter communication, possibly by a
1232 * NVMe Subsystem reset.
1233 */
1234 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1235
ad70062c
JW		 1236 /* If there is a reset/reinit ongoing, we shouldn't reset again. */
1237 switch (dev->ctrl.state) {
1238 case NVME_CTRL_RESETTING:
ad6a0a52 1239 case NVME_CTRL_CONNECTING:
b2a0eb1a 1240 return false;
ad70062c
JW		 1241 default:
1242 break;
1243 }
b2a0eb1a
KB		 1244
1245 /* We shouldn't reset unless the controller is on fatal error state
1246 * _or_ if we lost the communication with it.
1247 */
1248 if (!(csts & NVME_CSTS_CFS) && !nssro)
1249 return false;
1250
b2a0eb1a
KB		 1251 return true;
1252}
1253
1254static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1255{
1256 /* Read a config register to help see what died. */
1257 u16 pci_status;
1258 int result;
1259
1260 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1261 &pci_status);
1262 if (result == PCIBIOS_SUCCESSFUL)
1263 dev_warn(dev->ctrl.device,
1264 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1265 csts, pci_status);
1266 else
1267 dev_warn(dev->ctrl.device,
1268 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1269 csts, result);
4641a8e6
KB		 1270
1271 if (csts != ~0)
1272 return;
1273
1274 dev_warn(dev->ctrl.device,
1275 "Does your device have a faulty power saving mode enabled?\n");
1276 dev_warn(dev->ctrl.device,
1277 "Try \"nvme_core.default_ps_max_latency_us=0 pcie_aspm=off\" and report a bug\n");
b2a0eb1a
KB		 1278}
1279
9bdb4833 1280static enum blk_eh_timer_return nvme_timeout(struct request *req)
c30341dc 1281{
f4800d6d 1282 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a53232cb 1283 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
c30341dc 1284 struct nvme_dev *dev = nvmeq->dev;
a4aea562 1285 struct request *abort_req;
f66e2804 1286 struct nvme_command cmd = { };
b2a0eb1a
KB		 1287 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1288
651438bb
WX		 1289 /* If PCI error recovery process is happening, we cannot reset or
1290 * the recovery mechanism will surely fail.
1291 */
1292 mb();
1293 if (pci_channel_offline(to_pci_dev(dev->dev)))
1294 return BLK_EH_RESET_TIMER;
1295
b2a0eb1a
KB		 1296 /*
1297 * Reset immediately if the controller is failed
1298 */
1299 if (nvme_should_reset(dev, csts)) {
1300 nvme_warn_reset(dev, csts);
71a5bb15 1301 goto disable;
b2a0eb1a 1302 }
c30341dc 1303
7776db1c
KB		 1304 /*
1305 * Did we miss an interrupt?
1306 */
fa059b85 1307 if (test_bit(NVMEQ_POLLED, &nvmeq->flags))
5a72e899 1308 nvme_poll(req->mq_hctx, NULL);
fa059b85
KB		 1309 else
1310 nvme_poll_irqdisable(nvmeq);
1311
1c584208 1312 if (blk_mq_rq_state(req) != MQ_RQ_IN_FLIGHT) {
7776db1c
KB		 1313 dev_warn(dev->ctrl.device,
1314 "I/O %d QID %d timeout, completion polled\n",
1315 req->tag, nvmeq->qid);
db8c48e4 1316 return BLK_EH_DONE;
7776db1c
KB		 1317 }
1318
31c7c7d2 1319 /*
fd634f41
CH		 1320 * Shutdown immediately if controller times out while starting. The
1321 * reset work will see the pci device disabled when it gets the forced
1322 * cancellation error. All outstanding requests are completed on
db8c48e4 1323 * shutdown, so we return BLK_EH_DONE.
fd634f41 1324 */
4244140d
KB		 1325 switch (dev->ctrl.state) {
1326 case NVME_CTRL_CONNECTING:
2036f726 1327 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
df561f66 1328 fallthrough;
2036f726 1329 case NVME_CTRL_DELETING:
b9cac43c 1330 dev_warn_ratelimited(dev->ctrl.device,
fd634f41
CH		 1331 "I/O %d QID %d timeout, disable controller\n",
1332 req->tag, nvmeq->qid);
27fa9bc5 1333 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
7ad92f65 1334 nvme_dev_disable(dev, true);
db8c48e4 1335 return BLK_EH_DONE;
39a9dd81
KB		 1336 case NVME_CTRL_RESETTING:
1337 return BLK_EH_RESET_TIMER;
4244140d
KB		 1338 default:
1339 break;
c30341dc
KB		 1340 }
1341
fd634f41 1342 /*
ee0d96d3
BW		 1343 * Shutdown the controller immediately and schedule a reset if the
1344 * command was already aborted once before and still hasn't been
1345 * returned to the driver, or if this is the admin queue.
31c7c7d2 1346 */
f4800d6d 1347 if (!nvmeq->qid || iod->aborted) {
1b3c47c1 1348 dev_warn(dev->ctrl.device,
e1569a16
KB		 1349 "I/O %d QID %d timeout, reset controller\n",
1350 req->tag, nvmeq->qid);
7ad92f65 1351 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
71a5bb15 1352 goto disable;
c30341dc 1353 }
c30341dc 1354
e7a2a87d 1355 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
6bf25d16 1356 atomic_inc(&dev->ctrl.abort_limit);
31c7c7d2 1357 return BLK_EH_RESET_TIMER;
6bf25d16 1358 }
52da4f3f 1359 iod->aborted = true;
a4aea562 1360
c30341dc 1361 cmd.abort.opcode = nvme_admin_abort_cmd;
85f74acf 1362 cmd.abort.cid = nvme_cid(req);
c30341dc 1363 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
c30341dc 1364
1b3c47c1 1365 dev_warn(nvmeq->dev->ctrl.device,
86141440
CH		 1366 "I/O %d (%s) QID %d timeout, aborting\n",
1367 req->tag,
1368 nvme_get_opcode_str(nvme_req(req)->cmd->common.opcode),
1369 nvmeq->qid);
e7a2a87d 1370
e559398f
CH		 1371 abort_req = blk_mq_alloc_request(dev->ctrl.admin_q, nvme_req_op(&cmd),
1372 BLK_MQ_REQ_NOWAIT);
e7a2a87d
CH		 1373 if (IS_ERR(abort_req)) {
1374 atomic_inc(&dev->ctrl.abort_limit);
1375 return BLK_EH_RESET_TIMER;
1376 }
e559398f 1377 nvme_init_request(abort_req, &cmd);
e7a2a87d 1378
e2e53086 1379 abort_req->end_io = abort_endio;
e7a2a87d 1380 abort_req->end_io_data = NULL;
e2e53086 1381 blk_execute_rq_nowait(abort_req, false);
c30341dc 1382
31c7c7d2
CH		 1383 /*
1384 * The aborted req will be completed on receiving the abort req.
1385 * We enable the timer again. If hit twice, it'll cause a device reset,
1386 * as the device then is in a faulty state.
1387 */
1388 return BLK_EH_RESET_TIMER;
71a5bb15
KB		 1389
1390disable:
1391 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_RESETTING))
1392 return BLK_EH_DONE;
1393
1394 nvme_dev_disable(dev, false);
1395 if (nvme_try_sched_reset(&dev->ctrl))
1396 nvme_unquiesce_io_queues(&dev->ctrl);
1397 return BLK_EH_DONE;
c30341dc
KB		 1398}
1399
a4aea562
MB		 1400static void nvme_free_queue(struct nvme_queue *nvmeq)
1401{
8a1d09a6 1402 dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq),
9e866774 1403 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
63223078
CH		 1404 if (!nvmeq->sq_cmds)
1405 return;
0f238ff5 1406
63223078 1407 if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) {
88a041f4 1408 pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev),
8a1d09a6 1409 nvmeq->sq_cmds, SQ_SIZE(nvmeq));
63223078 1410 } else {
8a1d09a6 1411 dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq),
63223078 1412 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
0f238ff5 1413 }
9e866774
MW		 1414}
1415
a1a5ef99 1416static void nvme_free_queues(struct nvme_dev *dev, int lowest)
22404274
KB		 1417{
1418 int i;
1419
d858e5f0 1420 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
d858e5f0 1421 dev->ctrl.queue_count--;
147b27e4 1422 nvme_free_queue(&dev->queues[i]);
121c7ad4 1423 }
22404274
KB		 1424}
1425
10981f23 1426static void nvme_suspend_queue(struct nvme_dev *dev, unsigned int qid)
b60503ba 1427{
10981f23
CH		 1428 struct nvme_queue *nvmeq = &dev->queues[qid];
1429
4e224106 1430 if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags))
10981f23 1431 return;
a09115b2 1432
4e224106 1433 /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */
d1f06f4a 1434 mb();
a09115b2 1435
4e224106 1436 nvmeq->dev->online_queues--;
1c63dc66 1437 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
9f27bd70 1438 nvme_quiesce_admin_queue(&nvmeq->dev->ctrl);
7c349dde 1439 if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags))
10981f23 1440 pci_free_irq(to_pci_dev(dev->dev), nvmeq->cq_vector, nvmeq);
4d115420 1441}
b60503ba 1442
8fae268b
KB		 1443static void nvme_suspend_io_queues(struct nvme_dev *dev)
1444{
1445 int i;
1446
1447 for (i = dev->ctrl.queue_count - 1; i > 0; i--)
10981f23 1448 nvme_suspend_queue(dev, i);
b60503ba
MW		 1449}
1450
fa46c6fb
KB		 1451/*
1452 * Called only on a device that has been disabled and after all other threads
9210c075
DZ		 1453 * that can check this device's completion queues have synced, except
1454 * nvme_poll(). This is the last chance for the driver to see a natural
1455 * completion before nvme_cancel_request() terminates all incomplete requests.
fa46c6fb
KB		 1456 */
1457static void nvme_reap_pending_cqes(struct nvme_dev *dev)
1458{
fa46c6fb
KB		 1459 int i;
1460
9210c075
DZ		 1461 for (i = dev->ctrl.queue_count - 1; i > 0; i--) {
1462 spin_lock(&dev->queues[i].cq_poll_lock);
c234a653 1463 nvme_poll_cq(&dev->queues[i], NULL);
9210c075
DZ		 1464 spin_unlock(&dev->queues[i].cq_poll_lock);
1465 }
fa46c6fb
KB		 1466}
1467
8ffaadf7
JD		 1468static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1469 int entry_size)
1470{
1471 int q_depth = dev->q_depth;
5fd4ce1b 1472 unsigned q_size_aligned = roundup(q_depth * entry_size,
6c3c05b0 1473 NVME_CTRL_PAGE_SIZE);
8ffaadf7
JD		 1474
1475 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
c45f5c99 1476 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
4e523547 1477
6c3c05b0 1478 mem_per_q = round_down(mem_per_q, NVME_CTRL_PAGE_SIZE);
c45f5c99 1479 q_depth = div_u64(mem_per_q, entry_size);
8ffaadf7
JD		 1480
1481 /*
1482 * Ensure the reduced q_depth is above some threshold where it
1483 * would be better to map queues in system memory with the
1484 * original depth
1485 */
1486 if (q_depth < 64)
1487 return -ENOMEM;
1488 }
1489
1490 return q_depth;
1491}
1492
1493static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
8a1d09a6 1494 int qid)
8ffaadf7 1495{
0f238ff5
LG		 1496 struct pci_dev *pdev = to_pci_dev(dev->dev);
1497
1498 if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
8a1d09a6 1499 nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq));
bfac8e9f
AM		 1500 if (nvmeq->sq_cmds) {
1501 nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev,
1502 nvmeq->sq_cmds);
1503 if (nvmeq->sq_dma_addr) {
1504 set_bit(NVMEQ_SQ_CMB, &nvmeq->flags);
1505 return 0;
1506 }
1507
8a1d09a6 1508 pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq));
63223078 1509 }
0f238ff5 1510 }
8ffaadf7 1511
8a1d09a6 1512 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq),
63223078 1513 &nvmeq->sq_dma_addr, GFP_KERNEL);
815c6704
KB		 1514 if (!nvmeq->sq_cmds)
1515 return -ENOMEM;
8ffaadf7
JD		 1516 return 0;
1517}
1518
a6ff7262 1519static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
b60503ba 1520{
147b27e4 1521 struct nvme_queue *nvmeq = &dev->queues[qid];
b60503ba 1522
62314e40
KB		 1523 if (dev->ctrl.queue_count > qid)
1524 return 0;
b60503ba 1525
c1e0cc7e 1526 nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES;
8a1d09a6
BH		 1527 nvmeq->q_depth = depth;
1528 nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq),
750afb08 1529 &nvmeq->cq_dma_addr, GFP_KERNEL);
b60503ba
MW		 1530 if (!nvmeq->cqes)
1531 goto free_nvmeq;
b60503ba 1532
8a1d09a6 1533 if (nvme_alloc_sq_cmds(dev, nvmeq, qid))
b60503ba
MW		 1534 goto free_cqdma;
1535
091b6092 1536 nvmeq->dev = dev;
1ab0cd69 1537 spin_lock_init(&nvmeq->sq_lock);
3a7afd8e 1538 spin_lock_init(&nvmeq->cq_poll_lock);
b60503ba 1539 nvmeq->cq_head = 0;
82123460 1540 nvmeq->cq_phase = 1;
b80d5ccc 1541 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
c30341dc 1542 nvmeq->qid = qid;
d858e5f0 1543 dev->ctrl.queue_count++;
36a7e993 1544
147b27e4 1545 return 0;
b60503ba
MW		 1546
1547 free_cqdma:
8a1d09a6
BH		 1548 dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes,
1549 nvmeq->cq_dma_addr);
b60503ba 1550 free_nvmeq:
147b27e4 1551 return -ENOMEM;
b60503ba
MW		 1552}
1553
dca51e78 1554static int queue_request_irq(struct nvme_queue *nvmeq)
3001082c 1555{
0ff199cb
CH		 1556 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1557 int nr = nvmeq->dev->ctrl.instance;
1558
1559 if (use_threaded_interrupts) {
1560 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1561 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1562 } else {
1563 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1564 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1565 }
3001082c
MW		 1566}
1567
22404274 1568static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
b60503ba 1569{
22404274 1570 struct nvme_dev *dev = nvmeq->dev;
b60503ba 1571
22404274 1572 nvmeq->sq_tail = 0;
38210800 1573 nvmeq->last_sq_tail = 0;
22404274
KB		 1574 nvmeq->cq_head = 0;
1575 nvmeq->cq_phase = 1;
b80d5ccc 1576 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
8a1d09a6 1577 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq));
f9f38e33 1578 nvme_dbbuf_init(dev, nvmeq, qid);
42f61420 1579 dev->online_queues++;
3a7afd8e 1580 wmb(); /* ensure the first interrupt sees the initialization */
22404274
KB		 1581}
1582
e4b9852a
CC		 1583/*
1584 * Try getting shutdown_lock while setting up IO queues.
1585 */
1586static int nvme_setup_io_queues_trylock(struct nvme_dev *dev)
1587{
1588 /*
1589 * Give up if the lock is being held by nvme_dev_disable.
1590 */
1591 if (!mutex_trylock(&dev->shutdown_lock))
1592 return -ENODEV;
1593
1594 /*
1595 * Controller is in wrong state, fail early.
1596 */
1597 if (dev->ctrl.state != NVME_CTRL_CONNECTING) {
1598 mutex_unlock(&dev->shutdown_lock);
1599 return -ENODEV;
1600 }
1601
1602 return 0;
1603}
1604
4b04cc6a 1605static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled)
22404274
KB		 1606{
1607 struct nvme_dev *dev = nvmeq->dev;
1608 int result;
7c349dde 1609 u16 vector = 0;
3f85d50b 1610
d1ed6aa1
CH		 1611 clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
1612
22b55601
KB		 1613 /*
1614 * A queue's vector matches the queue identifier unless the controller
1615 * has only one vector available.
1616 */
4b04cc6a
JA		 1617 if (!polled)
1618 vector = dev->num_vecs == 1 ? 0 : qid;
1619 else
7c349dde 1620 set_bit(NVMEQ_POLLED, &nvmeq->flags);
4b04cc6a 1621
a8e3e0bb 1622 result = adapter_alloc_cq(dev, qid, nvmeq, vector);
ded45505
KB		 1623 if (result)
1624 return result;
b60503ba
MW		 1625
1626 result = adapter_alloc_sq(dev, qid, nvmeq);
1627 if (result < 0)
ded45505 1628 return result;
c80b36cd 1629 if (result)
b60503ba
MW		 1630 goto release_cq;
1631
a8e3e0bb 1632 nvmeq->cq_vector = vector;
4b04cc6a 1633
e4b9852a
CC		 1634 result = nvme_setup_io_queues_trylock(dev);
1635 if (result)
1636 return result;
1637 nvme_init_queue(nvmeq, qid);
7c349dde 1638 if (!polled) {
4b04cc6a
JA		 1639 result = queue_request_irq(nvmeq);
1640 if (result < 0)
1641 goto release_sq;
1642 }
b60503ba 1643
4e224106 1644 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
e4b9852a 1645 mutex_unlock(&dev->shutdown_lock);
22404274 1646 return result;
b60503ba 1647
a8e3e0bb 1648release_sq:
f25a2dfc 1649 dev->online_queues--;
e4b9852a 1650 mutex_unlock(&dev->shutdown_lock);
b60503ba 1651 adapter_delete_sq(dev, qid);
a8e3e0bb 1652release_cq:
b60503ba 1653 adapter_delete_cq(dev, qid);
22404274 1654 return result;
b60503ba
MW		 1655}
1656
f363b089 1657static const struct blk_mq_ops nvme_mq_admin_ops = {
d29ec824 1658 .queue_rq = nvme_queue_rq,
77f02a7a 1659 .complete = nvme_pci_complete_rq,
a4aea562 1660 .init_hctx = nvme_admin_init_hctx,
e559398f 1661 .init_request = nvme_pci_init_request,
a4aea562
MB		 1662 .timeout = nvme_timeout,
1663};
1664
f363b089 1665static const struct blk_mq_ops nvme_mq_ops = {
376f7ef8 1666 .queue_rq = nvme_queue_rq,
d62cbcf6 1667 .queue_rqs = nvme_queue_rqs,
376f7ef8
CH		 1668 .complete = nvme_pci_complete_rq,
1669 .commit_rqs = nvme_commit_rqs,
1670 .init_hctx = nvme_init_hctx,
e559398f 1671 .init_request = nvme_pci_init_request,
376f7ef8
CH		 1672 .map_queues = nvme_pci_map_queues,
1673 .timeout = nvme_timeout,
1674 .poll = nvme_poll,
dabcefab
JA		 1675};
1676
ea191d2f
KB		 1677static void nvme_dev_remove_admin(struct nvme_dev *dev)
1678{
1c63dc66 1679 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
69d9a99c
KB		 1680 /*
1681 * If the controller was reset during removal, it's possible
1682 * user requests may be waiting on a stopped queue. Start the
1683 * queue to flush these to completion.
1684 */
9f27bd70 1685 nvme_unquiesce_admin_queue(&dev->ctrl);
0da7feaa 1686 nvme_remove_admin_tag_set(&dev->ctrl);
ea191d2f
KB		 1687 }
1688}
1689
97f6ef64
XY		 1690static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1691{
1692 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1693}
1694
1695static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1696{
1697 struct pci_dev *pdev = to_pci_dev(dev->dev);
1698
1699 if (size <= dev->bar_mapped_size)
1700 return 0;
1701 if (size > pci_resource_len(pdev, 0))
1702 return -ENOMEM;
1703 if (dev->bar)
1704 iounmap(dev->bar);
1705 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1706 if (!dev->bar) {
1707 dev->bar_mapped_size = 0;
1708 return -ENOMEM;
1709 }
1710 dev->bar_mapped_size = size;
1711 dev->dbs = dev->bar + NVME_REG_DBS;
1712
1713 return 0;
1714}
1715
01ad0990 1716static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
b60503ba 1717{
ba47e386 1718 int result;
b60503ba
MW		 1719 u32 aqa;
1720 struct nvme_queue *nvmeq;
1721
97f6ef64
XY		 1722 result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1723 if (result < 0)
1724 return result;
1725
8ef2074d 1726 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
20d0dfe6 1727 NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
dfbac8c7 1728
7a67cbea
CH		 1729 if (dev->subsystem &&
1730 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1731 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
dfbac8c7 1732
285b6e9b
CH		 1733 /*
1734 * If the device has been passed off to us in an enabled state, just
1735 * clear the enabled bit. The spec says we should set the 'shutdown
1736 * notification bits', but doing so may cause the device to complete
1737 * commands to the admin queue ... and we don't know what memory that
1738 * might be pointing at!
1739 */
1740 result = nvme_disable_ctrl(&dev->ctrl, false);
ba47e386
MW		 1741 if (result < 0)
1742 return result;
b60503ba 1743
a6ff7262 1744 result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
147b27e4
SG		 1745 if (result)
1746 return result;
b60503ba 1747
635333e4
MG		 1748 dev->ctrl.numa_node = dev_to_node(dev->dev);
1749
147b27e4 1750 nvmeq = &dev->queues[0];
b60503ba
MW		 1751 aqa = nvmeq->q_depth - 1;
1752 aqa |= aqa << 16;
1753
7a67cbea
CH		 1754 writel(aqa, dev->bar + NVME_REG_AQA);
1755 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1756 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
b60503ba 1757
c0f2f45b 1758 result = nvme_enable_ctrl(&dev->ctrl);
025c557a 1759 if (result)
d4875622 1760 return result;
a4aea562 1761
2b25d981 1762 nvmeq->cq_vector = 0;
161b8be2 1763 nvme_init_queue(nvmeq, 0);
dca51e78 1764 result = queue_request_irq(nvmeq);
758dd7fd 1765 if (result) {
7c349dde 1766 dev->online_queues--;
d4875622 1767 return result;
758dd7fd 1768 }
025c557a 1769
4e224106 1770 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
b60503ba
MW		 1771 return result;
1772}
1773
749941f2 1774static int nvme_create_io_queues(struct nvme_dev *dev)
42f61420 1775{
4b04cc6a 1776 unsigned i, max, rw_queues;
749941f2 1777 int ret = 0;
42f61420 1778
d858e5f0 1779 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
a6ff7262 1780 if (nvme_alloc_queue(dev, i, dev->q_depth)) {
749941f2 1781 ret = -ENOMEM;
42f61420 1782 break;
749941f2
CH		 1783 }
1784 }
42f61420 1785
d858e5f0 1786 max = min(dev->max_qid, dev->ctrl.queue_count - 1);
e20ba6e1
CH		 1787 if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) {
1788 rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] +
1789 dev->io_queues[HCTX_TYPE_READ];
4b04cc6a
JA		 1790 } else {
1791 rw_queues = max;
1792 }
1793
949928c1 1794 for (i = dev->online_queues; i <= max; i++) {
4b04cc6a
JA		 1795 bool polled = i > rw_queues;
1796
1797 ret = nvme_create_queue(&dev->queues[i], i, polled);
d4875622 1798 if (ret)
42f61420 1799 break;
27e8166c 1800 }
749941f2
CH		 1801
1802 /*
1803 * Ignore failing Create SQ/CQ commands, we can continue with less
8adb8c14
MI		 1804 * than the desired amount of queues, and even a controller without
1805 * I/O queues can still be used to issue admin commands. This might
749941f2
CH		 1806 * be useful to upgrade a buggy firmware for example.
1807 */
1808 return ret >= 0 ? 0 : ret;
b60503ba
MW		 1809}
1810
88de4598 1811static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
8ffaadf7 1812{
88de4598
CH		 1813 u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
1814
1815 return 1ULL << (12 + 4 * szu);
1816}
1817
1818static u32 nvme_cmb_size(struct nvme_dev *dev)
1819{
1820 return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
1821}
1822
f65efd6d 1823static void nvme_map_cmb(struct nvme_dev *dev)
8ffaadf7 1824{
88de4598 1825 u64 size, offset;
8ffaadf7
JD		 1826 resource_size_t bar_size;
1827 struct pci_dev *pdev = to_pci_dev(dev->dev);
8969f1f8 1828 int bar;
8ffaadf7 1829
9fe5c59f
KB		 1830 if (dev->cmb_size)
1831 return;
1832
20d3bb92
KJ		 1833 if (NVME_CAP_CMBS(dev->ctrl.cap))
1834 writel(NVME_CMBMSC_CRE, dev->bar + NVME_REG_CMBMSC);
1835
7a67cbea 1836 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
f65efd6d
CH		 1837 if (!dev->cmbsz)
1838 return;
202021c1 1839 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
8ffaadf7 1840
88de4598
CH		 1841 size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
1842 offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
8969f1f8
CH		 1843 bar = NVME_CMB_BIR(dev->cmbloc);
1844 bar_size = pci_resource_len(pdev, bar);
8ffaadf7
JD		 1845
1846 if (offset > bar_size)
f65efd6d 1847 return;
8ffaadf7 1848
20d3bb92
KJ		 1849 /*
1850 * Tell the controller about the host side address mapping the CMB,
1851 * and enable CMB decoding for the NVMe 1.4+ scheme:
1852 */
1853 if (NVME_CAP_CMBS(dev->ctrl.cap)) {
1854 hi_lo_writeq(NVME_CMBMSC_CRE | NVME_CMBMSC_CMSE |
1855 (pci_bus_address(pdev, bar) + offset),
1856 dev->bar + NVME_REG_CMBMSC);
1857 }
1858
8ffaadf7
JD		 1859 /*
1860 * Controllers may support a CMB size larger than their BAR,
1861 * for example, due to being behind a bridge. Reduce the CMB to
1862 * the reported size of the BAR
1863 */
1864 if (size > bar_size - offset)
1865 size = bar_size - offset;
1866
0f238ff5
LG		 1867 if (pci_p2pdma_add_resource(pdev, bar, size, offset)) {
1868 dev_warn(dev->ctrl.device,
1869 "failed to register the CMB\n");
f65efd6d 1870 return;
0f238ff5
LG		 1871 }
1872
8ffaadf7 1873 dev->cmb_size = size;
0f238ff5
LG		 1874 dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS);
1875
1876 if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) ==
1877 (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS))
1878 pci_p2pmem_publish(pdev, true);
e917a849
KB		 1879
1880 nvme_update_attrs(dev);
8ffaadf7
JD		 1881}
1882
87ad72a5
CH		 1883static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1884{
6c3c05b0 1885 u32 host_mem_size = dev->host_mem_size >> NVME_CTRL_PAGE_SHIFT;
4033f35d 1886 u64 dma_addr = dev->host_mem_descs_dma;
f66e2804 1887 struct nvme_command c = { };
87ad72a5
CH		 1888 int ret;
1889
87ad72a5
CH		 1890 c.features.opcode = nvme_admin_set_features;
1891 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1892 c.features.dword11 = cpu_to_le32(bits);
6c3c05b0 1893 c.features.dword12 = cpu_to_le32(host_mem_size);
87ad72a5
CH		 1894 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr));
1895 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr));
1896 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs);
1897
1898 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1899 if (ret) {
1900 dev_warn(dev->ctrl.device,
1901 "failed to set host mem (err %d, flags %#x).\n",
1902 ret, bits);
a5df5e79
KB		 1903 } else
1904 dev->hmb = bits & NVME_HOST_MEM_ENABLE;
1905
87ad72a5
CH		 1906 return ret;
1907}
1908
1909static void nvme_free_host_mem(struct nvme_dev *dev)
1910{
1911 int i;
1912
1913 for (i = 0; i < dev->nr_host_mem_descs; i++) {
1914 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
6c3c05b0 1915 size_t size = le32_to_cpu(desc->size) * NVME_CTRL_PAGE_SIZE;
87ad72a5 1916
cc667f6d
LD		 1917 dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i],
1918 le64_to_cpu(desc->addr),
1919 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
87ad72a5
CH		 1920 }
1921
1922 kfree(dev->host_mem_desc_bufs);
1923 dev->host_mem_desc_bufs = NULL;
4033f35d
CH		 1924 dma_free_coherent(dev->dev,
1925 dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
1926 dev->host_mem_descs, dev->host_mem_descs_dma);
87ad72a5 1927 dev->host_mem_descs = NULL;
7e5dd57e 1928 dev->nr_host_mem_descs = 0;
87ad72a5
CH		 1929}
1930
92dc6895
CH		 1931static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
1932 u32 chunk_size)
9d713c2b 1933{
87ad72a5 1934 struct nvme_host_mem_buf_desc *descs;
92dc6895 1935 u32 max_entries, len;
4033f35d 1936 dma_addr_t descs_dma;
2ee0e4ed 1937 int i = 0;
87ad72a5 1938 void **bufs;
6fbcde66 1939 u64 size, tmp;
87ad72a5 1940
87ad72a5
CH		 1941 tmp = (preferred + chunk_size - 1);
1942 do_div(tmp, chunk_size);
1943 max_entries = tmp;
044a9df1
CH		 1944
1945 if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
1946 max_entries = dev->ctrl.hmmaxd;
1947
750afb08
LC		 1948 descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs),
1949 &descs_dma, GFP_KERNEL);
87ad72a5
CH		 1950 if (!descs)
1951 goto out;
1952
1953 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
1954 if (!bufs)
1955 goto out_free_descs;
1956
244a8fe4 1957 for (size = 0; size < preferred && i < max_entries; size += len) {
87ad72a5
CH		 1958 dma_addr_t dma_addr;
1959
50cdb7c6 1960 len = min_t(u64, chunk_size, preferred - size);
87ad72a5
CH		 1961 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
1962 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1963 if (!bufs[i])
1964 break;
1965
1966 descs[i].addr = cpu_to_le64(dma_addr);
6c3c05b0 1967 descs[i].size = cpu_to_le32(len / NVME_CTRL_PAGE_SIZE);
87ad72a5
CH		 1968 i++;
1969 }
1970
92dc6895 1971 if (!size)
87ad72a5 1972 goto out_free_bufs;
87ad72a5 1973
87ad72a5
CH		 1974 dev->nr_host_mem_descs = i;
1975 dev->host_mem_size = size;
1976 dev->host_mem_descs = descs;
4033f35d 1977 dev->host_mem_descs_dma = descs_dma;
87ad72a5
CH		 1978 dev->host_mem_desc_bufs = bufs;
1979 return 0;
1980
1981out_free_bufs:
1982 while (--i >= 0) {
6c3c05b0 1983 size_t size = le32_to_cpu(descs[i].size) * NVME_CTRL_PAGE_SIZE;
87ad72a5 1984
cc667f6d
LD		 1985 dma_free_attrs(dev->dev, size, bufs[i],
1986 le64_to_cpu(descs[i].addr),
1987 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
87ad72a5
CH		 1988 }
1989
1990 kfree(bufs);
1991out_free_descs:
4033f35d
CH		 1992 dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
1993 descs_dma);
87ad72a5 1994out:
87ad72a5
CH		 1995 dev->host_mem_descs = NULL;
1996 return -ENOMEM;
1997}
1998
92dc6895
CH		 1999static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
2000{
9dc54a0d
CK		 2001 u64 min_chunk = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
2002 u64 hmminds = max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
2003 u64 chunk_size;
92dc6895
CH		 2004
2005 /* start big and work our way down */
9dc54a0d 2006 for (chunk_size = min_chunk; chunk_size >= hmminds; chunk_size /= 2) {
92dc6895
CH		 2007 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
2008 if (!min || dev->host_mem_size >= min)
2009 return 0;
2010 nvme_free_host_mem(dev);
2011 }
2012 }
2013
2014 return -ENOMEM;
2015}
2016
9620cfba 2017static int nvme_setup_host_mem(struct nvme_dev *dev)
87ad72a5
CH		 2018{
2019 u64 max = (u64)max_host_mem_size_mb * SZ_1M;
2020 u64 preferred = (u64)dev->ctrl.hmpre * 4096;
2021 u64 min = (u64)dev->ctrl.hmmin * 4096;
2022 u32 enable_bits = NVME_HOST_MEM_ENABLE;
6fbcde66 2023 int ret;
87ad72a5 2024
acb71e53
CH		 2025 if (!dev->ctrl.hmpre)
2026 return 0;
2027
87ad72a5
CH		 2028 preferred = min(preferred, max);
2029 if (min > max) {
2030 dev_warn(dev->ctrl.device,
2031 "min host memory (%lld MiB) above limit (%d MiB).\n",
2032 min >> ilog2(SZ_1M), max_host_mem_size_mb);
2033 nvme_free_host_mem(dev);
9620cfba 2034 return 0;
87ad72a5
CH		 2035 }
2036
2037 /*
2038 * If we already have a buffer allocated check if we can reuse it.
2039 */
2040 if (dev->host_mem_descs) {
2041 if (dev->host_mem_size >= min)
2042 enable_bits |= NVME_HOST_MEM_RETURN;
2043 else
2044 nvme_free_host_mem(dev);
2045 }
2046
2047 if (!dev->host_mem_descs) {
92dc6895
CH		 2048 if (nvme_alloc_host_mem(dev, min, preferred)) {
2049 dev_warn(dev->ctrl.device,
2050 "failed to allocate host memory buffer.\n");
9620cfba 2051 return 0; /* controller must work without HMB */
92dc6895
CH		 2052 }
2053
2054 dev_info(dev->ctrl.device,
2055 "allocated %lld MiB host memory buffer.\n",
2056 dev->host_mem_size >> ilog2(SZ_1M));
87ad72a5
CH		 2057 }
2058
9620cfba
CH		 2059 ret = nvme_set_host_mem(dev, enable_bits);
2060 if (ret)
87ad72a5 2061 nvme_free_host_mem(dev);
9620cfba 2062 return ret;
9d713c2b
KB		 2063}
2064
0521905e
KB		 2065static ssize_t cmb_show(struct device *dev, struct device_attribute *attr,
2066 char *buf)
2067{
2068 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2069
2070 return sysfs_emit(buf, "cmbloc : x%08x\ncmbsz : x%08x\n",
2071 ndev->cmbloc, ndev->cmbsz);
2072}
2073static DEVICE_ATTR_RO(cmb);
2074
1751e97a
KB		 2075static ssize_t cmbloc_show(struct device *dev, struct device_attribute *attr,
2076 char *buf)
2077{
2078 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2079
2080 return sysfs_emit(buf, "%u\n", ndev->cmbloc);
2081}
2082static DEVICE_ATTR_RO(cmbloc);
2083
2084static ssize_t cmbsz_show(struct device *dev, struct device_attribute *attr,
2085 char *buf)
2086{
2087 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2088
2089 return sysfs_emit(buf, "%u\n", ndev->cmbsz);
2090}
2091static DEVICE_ATTR_RO(cmbsz);
2092
a5df5e79
KB		 2093static ssize_t hmb_show(struct device *dev, struct device_attribute *attr,
2094 char *buf)
2095{
2096 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2097
2098 return sysfs_emit(buf, "%d\n", ndev->hmb);
2099}
2100
2101static ssize_t hmb_store(struct device *dev, struct device_attribute *attr,
2102 const char *buf, size_t count)
2103{
2104 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2105 bool new;
2106 int ret;
2107
99722c8a 2108 if (kstrtobool(buf, &new) < 0)
a5df5e79
KB		 2109 return -EINVAL;
2110
2111 if (new == ndev->hmb)
2112 return count;
2113
2114 if (new) {
2115 ret = nvme_setup_host_mem(ndev);
2116 } else {
2117 ret = nvme_set_host_mem(ndev, 0);
2118 if (!ret)
2119 nvme_free_host_mem(ndev);
2120 }
2121
2122 if (ret < 0)
2123 return ret;
2124
2125 return count;
2126}
2127static DEVICE_ATTR_RW(hmb);
2128
0521905e
KB		 2129static umode_t nvme_pci_attrs_are_visible(struct kobject *kobj,
2130 struct attribute *a, int n)
2131{
2132 struct nvme_ctrl *ctrl =
2133 dev_get_drvdata(container_of(kobj, struct device, kobj));
2134 struct nvme_dev *dev = to_nvme_dev(ctrl);
2135
1751e97a
KB		 2136 if (a == &dev_attr_cmb.attr ||
2137 a == &dev_attr_cmbloc.attr ||
2138 a == &dev_attr_cmbsz.attr) {
2139 if (!dev->cmbsz)
2140 return 0;
2141 }
a5df5e79
KB		 2142 if (a == &dev_attr_hmb.attr && !ctrl->hmpre)
2143 return 0;
2144
0521905e
KB		 2145 return a->mode;
2146}
2147
2148static struct attribute *nvme_pci_attrs[] = {
2149 &dev_attr_cmb.attr,
1751e97a
KB		 2150 &dev_attr_cmbloc.attr,
2151 &dev_attr_cmbsz.attr,
a5df5e79 2152 &dev_attr_hmb.attr,
0521905e
KB		 2153 NULL,
2154};
2155
86adbf0c 2156static const struct attribute_group nvme_pci_dev_attrs_group = {
0521905e
KB		 2157 .attrs = nvme_pci_attrs,
2158 .is_visible = nvme_pci_attrs_are_visible,
2159};
2160
86adbf0c
CH		 2161static const struct attribute_group *nvme_pci_dev_attr_groups[] = {
2162 &nvme_dev_attrs_group,
2163 &nvme_pci_dev_attrs_group,
2164 NULL,
2165};
2166
e917a849
KB		 2167static void nvme_update_attrs(struct nvme_dev *dev)
2168{
2169 sysfs_update_group(&dev->ctrl.device->kobj, &nvme_pci_dev_attrs_group);
2170}
2171
612b7286
ML		 2172/*
2173 * nirqs is the number of interrupts available for write and read
2174 * queues. The core already reserved an interrupt for the admin queue.
2175 */
2176static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs)
3b6592f7 2177{
612b7286 2178 struct nvme_dev *dev = affd->priv;
2a5bcfdd 2179 unsigned int nr_read_queues, nr_write_queues = dev->nr_write_queues;
3b6592f7
JA		 2180
2181 /*
ee0d96d3 2182 * If there is no interrupt available for queues, ensure that
612b7286
ML		 2183 * the default queue is set to 1. The affinity set size is
2184 * also set to one, but the irq core ignores it for this case.
2185 *
2186 * If only one interrupt is available or 'write_queue' == 0, combine
2187 * write and read queues.
2188 *
2189 * If 'write_queues' > 0, ensure it leaves room for at least one read
2190 * queue.
3b6592f7 2191 */
612b7286
ML		 2192 if (!nrirqs) {
2193 nrirqs = 1;
2194 nr_read_queues = 0;
2a5bcfdd 2195 } else if (nrirqs == 1 || !nr_write_queues) {
612b7286 2196 nr_read_queues = 0;
2a5bcfdd 2197 } else if (nr_write_queues >= nrirqs) {
612b7286 2198 nr_read_queues = 1;
3b6592f7 2199 } else {
2a5bcfdd 2200 nr_read_queues = nrirqs - nr_write_queues;
3b6592f7 2201 }
612b7286
ML		 2202
2203 dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2204 affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2205 dev->io_queues[HCTX_TYPE_READ] = nr_read_queues;
2206 affd->set_size[HCTX_TYPE_READ] = nr_read_queues;
2207 affd->nr_sets = nr_read_queues ? 2 : 1;
3b6592f7
JA		 2208}
2209
6451fe73 2210static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues)
3b6592f7
JA		 2211{
2212 struct pci_dev *pdev = to_pci_dev(dev->dev);
3b6592f7 2213 struct irq_affinity affd = {
9cfef55b 2214 .pre_vectors = 1,
612b7286
ML		 2215 .calc_sets = nvme_calc_irq_sets,
2216 .priv = dev,
3b6592f7 2217 };
21cc2f3f 2218 unsigned int irq_queues, poll_queues;
6451fe73
JA		 2219
2220 /*
21cc2f3f
JX		 2221 * Poll queues don't need interrupts, but we need at least one I/O queue
2222 * left over for non-polled I/O.
6451fe73 2223 */
21cc2f3f
JX		 2224 poll_queues = min(dev->nr_poll_queues, nr_io_queues - 1);
2225 dev->io_queues[HCTX_TYPE_POLL] = poll_queues;
3b6592f7 2226
21cc2f3f
JX		 2227 /*
2228 * Initialize for the single interrupt case, will be updated in
2229 * nvme_calc_irq_sets().
2230 */
612b7286
ML		 2231 dev->io_queues[HCTX_TYPE_DEFAULT] = 1;
2232 dev->io_queues[HCTX_TYPE_READ] = 0;
3b6592f7 2233
66341331 2234 /*
21cc2f3f
JX		 2235 * We need interrupts for the admin queue and each non-polled I/O queue,
2236 * but some Apple controllers require all queues to use the first
2237 * vector.
66341331 2238 */
21cc2f3f
JX		 2239 irq_queues = 1;
2240 if (!(dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR))
2241 irq_queues += (nr_io_queues - poll_queues);
612b7286
ML		 2242 return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues,
2243 PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd);
3b6592f7
JA		 2244}
2245
2a5bcfdd
WZ		 2246static unsigned int nvme_max_io_queues(struct nvme_dev *dev)
2247{
e3aef095
NS		 2248 /*
2249 * If tags are shared with admin queue (Apple bug), then
2250 * make sure we only use one IO queue.
2251 */
2252 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2253 return 1;
2a5bcfdd
WZ		 2254 return num_possible_cpus() + dev->nr_write_queues + dev->nr_poll_queues;
2255}
2256
8d85fce7 2257static int nvme_setup_io_queues(struct nvme_dev *dev)
b60503ba 2258{
147b27e4 2259 struct nvme_queue *adminq = &dev->queues[0];
e75ec752 2260 struct pci_dev *pdev = to_pci_dev(dev->dev);
2a5bcfdd 2261 unsigned int nr_io_queues;
97f6ef64 2262 unsigned long size;
2a5bcfdd 2263 int result;
b60503ba 2264
2a5bcfdd
WZ		 2265 /*
2266 * Sample the module parameters once at reset time so that we have
2267 * stable values to work with.
2268 */
2269 dev->nr_write_queues = write_queues;
2270 dev->nr_poll_queues = poll_queues;
d38e9f04 2271
e3aef095 2272 nr_io_queues = dev->nr_allocated_queues - 1;
9a0be7ab
CH		 2273 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
2274 if (result < 0)
1b23484b 2275 return result;
9a0be7ab 2276
f5fa90dc 2277 if (nr_io_queues == 0)
a5229050 2278 return 0;
53dc180e 2279
e4b9852a
CC		 2280 /*
2281 * Free IRQ resources as soon as NVMEQ_ENABLED bit transitions
2282 * from set to unset. If there is a window to it is truely freed,
2283 * pci_free_irq_vectors() jumping into this window will crash.
2284 * And take lock to avoid racing with pci_free_irq_vectors() in
2285 * nvme_dev_disable() path.
2286 */
2287 result = nvme_setup_io_queues_trylock(dev);
2288 if (result)
2289 return result;
2290 if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags))
2291 pci_free_irq(pdev, 0, adminq);
b60503ba 2292
0f238ff5 2293 if (dev->cmb_use_sqes) {
8ffaadf7
JD		 2294 result = nvme_cmb_qdepth(dev, nr_io_queues,
2295 sizeof(struct nvme_command));
88d356ca 2296 if (result > 0) {
8ffaadf7 2297 dev->q_depth = result;
88d356ca
CH		 2298 dev->ctrl.sqsize = result - 1;
2299 } else {
0f238ff5 2300 dev->cmb_use_sqes = false;
88d356ca 2301 }
8ffaadf7
JD		 2302 }
2303
97f6ef64
XY		 2304 do {
2305 size = db_bar_size(dev, nr_io_queues);
2306 result = nvme_remap_bar(dev, size);
2307 if (!result)
2308 break;
e4b9852a
CC		 2309 if (!--nr_io_queues) {
2310 result = -ENOMEM;
2311 goto out_unlock;
2312 }
97f6ef64
XY		 2313 } while (1);
2314 adminq->q_db = dev->dbs;
f1938f6e 2315
8fae268b 2316 retry:
9d713c2b 2317 /* Deregister the admin queue's interrupt */
e4b9852a
CC		 2318 if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags))
2319 pci_free_irq(pdev, 0, adminq);
9d713c2b 2320
e32efbfc
JA		 2321 /*
2322 * If we enable msix early due to not intx, disable it again before
2323 * setting up the full range we need.
2324 */
dca51e78 2325 pci_free_irq_vectors(pdev);
3b6592f7
JA		 2326
2327 result = nvme_setup_irqs(dev, nr_io_queues);
e4b9852a
CC		 2328 if (result <= 0) {
2329 result = -EIO;
2330 goto out_unlock;
2331 }
3b6592f7 2332
22b55601 2333 dev->num_vecs = result;
4b04cc6a 2334 result = max(result - 1, 1);
e20ba6e1 2335 dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL];
fa08a396 2336
063a8096
MW		 2337 /*
2338 * Should investigate if there's a performance win from allocating
2339 * more queues than interrupt vectors; it might allow the submission
2340 * path to scale better, even if the receive path is limited by the
2341 * number of interrupts.
2342 */
dca51e78 2343 result = queue_request_irq(adminq);
7c349dde 2344 if (result)
e4b9852a 2345 goto out_unlock;
4e224106 2346 set_bit(NVMEQ_ENABLED, &adminq->flags);
e4b9852a 2347 mutex_unlock(&dev->shutdown_lock);
8fae268b
KB		 2348
2349 result = nvme_create_io_queues(dev);
2350 if (result || dev->online_queues < 2)
2351 return result;
2352
2353 if (dev->online_queues - 1 < dev->max_qid) {
2354 nr_io_queues = dev->online_queues - 1;
7d879c90 2355 nvme_delete_io_queues(dev);
e4b9852a
CC		 2356 result = nvme_setup_io_queues_trylock(dev);
2357 if (result)
2358 return result;
8fae268b
KB		 2359 nvme_suspend_io_queues(dev);
2360 goto retry;
2361 }
2362 dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n",
2363 dev->io_queues[HCTX_TYPE_DEFAULT],
2364 dev->io_queues[HCTX_TYPE_READ],
2365 dev->io_queues[HCTX_TYPE_POLL]);
2366 return 0;
e4b9852a
CC		 2367out_unlock:
2368 mutex_unlock(&dev->shutdown_lock);
2369 return result;
b60503ba
MW		 2370}
2371
de671d61
JA		 2372static enum rq_end_io_ret nvme_del_queue_end(struct request *req,
2373 blk_status_t error)
a5768aa8 2374{
db3cbfff 2375 struct nvme_queue *nvmeq = req->end_io_data;
b5875222 2376
db3cbfff 2377 blk_mq_free_request(req);
d1ed6aa1 2378 complete(&nvmeq->delete_done);
de671d61 2379 return RQ_END_IO_NONE;
a5768aa8
KB		 2380}
2381
de671d61
JA		 2382static enum rq_end_io_ret nvme_del_cq_end(struct request *req,
2383 blk_status_t error)
a5768aa8 2384{
db3cbfff 2385 struct nvme_queue *nvmeq = req->end_io_data;
a5768aa8 2386
d1ed6aa1
CH		 2387 if (error)
2388 set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
db3cbfff 2389
de671d61 2390 return nvme_del_queue_end(req, error);
a5768aa8
KB		 2391}
2392
db3cbfff 2393static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
bda4e0fb 2394{
db3cbfff
KB		 2395 struct request_queue *q = nvmeq->dev->ctrl.admin_q;
2396 struct request *req;
f66e2804 2397 struct nvme_command cmd = { };
bda4e0fb 2398
db3cbfff
KB		 2399 cmd.delete_queue.opcode = opcode;
2400 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
bda4e0fb 2401
e559398f 2402 req = blk_mq_alloc_request(q, nvme_req_op(&cmd), BLK_MQ_REQ_NOWAIT);
db3cbfff
KB		 2403 if (IS_ERR(req))
2404 return PTR_ERR(req);
e559398f 2405 nvme_init_request(req, &cmd);
bda4e0fb 2406
e2e53086
CH		 2407 if (opcode == nvme_admin_delete_cq)
2408 req->end_io = nvme_del_cq_end;
2409 else
2410 req->end_io = nvme_del_queue_end;
db3cbfff
KB		 2411 req->end_io_data = nvmeq;
2412
d1ed6aa1 2413 init_completion(&nvmeq->delete_done);
e2e53086 2414 blk_execute_rq_nowait(req, false);
db3cbfff 2415 return 0;
bda4e0fb
KB		 2416}
2417
7d879c90 2418static bool __nvme_delete_io_queues(struct nvme_dev *dev, u8 opcode)
a5768aa8 2419{
5271edd4 2420 int nr_queues = dev->online_queues - 1, sent = 0;
db3cbfff 2421 unsigned long timeout;
a5768aa8 2422
db3cbfff 2423 retry:
dc96f938 2424 timeout = NVME_ADMIN_TIMEOUT;
5271edd4
CH		 2425 while (nr_queues > 0) {
2426 if (nvme_delete_queue(&dev->queues[nr_queues], opcode))
2427 break;
2428 nr_queues--;
2429 sent++;
db3cbfff 2430 }
d1ed6aa1
CH		 2431 while (sent) {
2432 struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent];
2433
2434 timeout = wait_for_completion_io_timeout(&nvmeq->delete_done,
5271edd4
CH		 2435 timeout);
2436 if (timeout == 0)
2437 return false;
d1ed6aa1 2438
d1ed6aa1 2439 sent--;
5271edd4
CH		 2440 if (nr_queues)
2441 goto retry;
2442 }
2443 return true;
a5768aa8
KB		 2444}
2445
7d879c90 2446static void nvme_delete_io_queues(struct nvme_dev *dev)
b60503ba 2447{
7d879c90
CH		 2448 if (__nvme_delete_io_queues(dev, nvme_admin_delete_sq))
2449 __nvme_delete_io_queues(dev, nvme_admin_delete_cq);
2450}
2b1b7e78 2451
0da7feaa 2452static unsigned int nvme_pci_nr_maps(struct nvme_dev *dev)
b60503ba 2453{
2455a4b7 2454 if (dev->io_queues[HCTX_TYPE_POLL])
0da7feaa
CH		 2455 return 3;
2456 if (dev->io_queues[HCTX_TYPE_READ])
2457 return 2;
2458 return 1;
2455a4b7 2459}
949928c1 2460
2455a4b7
CH		 2461static void nvme_pci_update_nr_queues(struct nvme_dev *dev)
2462{
2463 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2464 /* free previously allocated queues that are no longer usable */
2465 nvme_free_queues(dev, dev->online_queues);
b60503ba
MW		 2466}
2467
b00a726a 2468static int nvme_pci_enable(struct nvme_dev *dev)
0877cb0d 2469{
b00a726a 2470 int result = -ENOMEM;
e75ec752 2471 struct pci_dev *pdev = to_pci_dev(dev->dev);
0877cb0d
KB		 2472
2473 if (pci_enable_device_mem(pdev))
2474 return result;
2475
0877cb0d 2476 pci_set_master(pdev);
0877cb0d 2477
7a67cbea 2478 if (readl(dev->bar + NVME_REG_CSTS) == -1) {
0e53d180 2479 result = -ENODEV;
b00a726a 2480 goto disable;
0e53d180 2481 }
e32efbfc
JA		 2482
2483 /*
a5229050
KB		 2484 * Some devices and/or platforms don't advertise or work with INTx
2485 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2486 * adjust this later.
e32efbfc 2487 */
dca51e78
CH		 2488 result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
2489 if (result < 0)
09113abf 2490 goto disable;
e32efbfc 2491
20d0dfe6 2492 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
7a67cbea 2493
7442ddce 2494 dev->q_depth = min_t(u32, NVME_CAP_MQES(dev->ctrl.cap) + 1,
b27c1e68 2495 io_queue_depth);
20d0dfe6 2496 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
7a67cbea 2497 dev->dbs = dev->bar + 4096;
1f390c1f 2498
66341331
BH		 2499 /*
2500 * Some Apple controllers require a non-standard SQE size.
2501 * Interestingly they also seem to ignore the CC:IOSQES register
2502 * so we don't bother updating it here.
2503 */
2504 if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES)
2505 dev->io_sqes = 7;
2506 else
2507 dev->io_sqes = NVME_NVM_IOSQES;
1f390c1f
SG		 2508
2509 /*
2510 * Temporary fix for the Apple controller found in the MacBook8,1 and
2511 * some MacBook7,1 to avoid controller resets and data loss.
2512 */
2513 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
2514 dev->q_depth = 2;
9bdcfb10
CH		 2515 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
2516 "set queue depth=%u to work around controller resets\n",
1f390c1f 2517 dev->q_depth);
d554b5e1
MP		 2518 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2519 (pdev->device == 0xa821 || pdev->device == 0xa822) &&
20d0dfe6 2520 NVME_CAP_MQES(dev->ctrl.cap) == 0) {
d554b5e1
MP		 2521 dev->q_depth = 64;
2522 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2523 "set queue depth=%u\n", dev->q_depth);
1f390c1f
SG		 2524 }
2525
d38e9f04
BH		 2526 /*
2527 * Controllers with the shared tags quirk need the IO queue to be
2528 * big enough so that we get 32 tags for the admin queue
2529 */
2530 if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) &&
2531 (dev->q_depth < (NVME_AQ_DEPTH + 2))) {
2532 dev->q_depth = NVME_AQ_DEPTH + 2;
2533 dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n",
2534 dev->q_depth);
2535 }
88d356ca 2536 dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */
d38e9f04 2537
f65efd6d 2538 nvme_map_cmb(dev);
202021c1 2539
a0a3408e 2540 pci_save_state(pdev);
a6ee7f19 2541
09113abf
TZ		 2542 result = nvme_pci_configure_admin_queue(dev);
2543 if (result)
2544 goto free_irq;
2545 return result;
0877cb0d 2546
09113abf
TZ		 2547 free_irq:
2548 pci_free_irq_vectors(pdev);
0877cb0d 2549 disable:
0877cb0d
KB		 2550 pci_disable_device(pdev);
2551 return result;
2552}
2553
2554static void nvme_dev_unmap(struct nvme_dev *dev)
b00a726a
KB		 2555{
2556 if (dev->bar)
2557 iounmap(dev->bar);
a1f447b3 2558 pci_release_mem_regions(to_pci_dev(dev->dev));
b00a726a
KB		 2559}
2560
68e81eba 2561static bool nvme_pci_ctrl_is_dead(struct nvme_dev *dev)
0877cb0d 2562{
e75ec752 2563 struct pci_dev *pdev = to_pci_dev(dev->dev);
68e81eba 2564 u32 csts;
e75ec752 2565
68e81eba
CH		 2566 if (!pci_is_enabled(pdev) || !pci_device_is_present(pdev))
2567 return true;
2568 if (pdev->error_state != pci_channel_io_normal)
2569 return true;
0877cb0d 2570
68e81eba
CH		 2571 csts = readl(dev->bar + NVME_REG_CSTS);
2572 return (csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY);
4d115420
KB		 2573}
2574
a5cdb68c 2575static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
b60503ba 2576{
302ad8cc 2577 struct pci_dev *pdev = to_pci_dev(dev->dev);
68e81eba 2578 bool dead;
22404274 2579
77bf25ea 2580 mutex_lock(&dev->shutdown_lock);
68e81eba
CH		 2581 dead = nvme_pci_ctrl_is_dead(dev);
2582 if (dev->ctrl.state == NVME_CTRL_LIVE ||
2583 dev->ctrl.state == NVME_CTRL_RESETTING) {
2584 if (pci_is_enabled(pdev))
302ad8cc 2585 nvme_start_freeze(&dev->ctrl);
68e81eba
CH		 2586 /*
2587 * Give the controller a chance to complete all entered requests
2588 * if doing a safe shutdown.
2589 */
2590 if (!dead && shutdown)
2591 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
c9d3bf88 2592 }
c21377f8 2593
9f27bd70 2594 nvme_quiesce_io_queues(&dev->ctrl);
87ad72a5 2595
64ee0ac0 2596 if (!dead && dev->ctrl.queue_count > 0) {
7d879c90 2597 nvme_delete_io_queues(dev);
47d42d22
CH		 2598 nvme_disable_ctrl(&dev->ctrl, shutdown);
2599 nvme_poll_irqdisable(&dev->queues[0]);
4d115420 2600 }
8fae268b 2601 nvme_suspend_io_queues(dev);
10981f23 2602 nvme_suspend_queue(dev, 0);
c80767f7 2603 pci_free_irq_vectors(pdev);
1ad11eaf 2604 if (pci_is_enabled(pdev))
c80767f7 2605 pci_disable_device(pdev);
fa46c6fb 2606 nvme_reap_pending_cqes(dev);
07836e65 2607
1fcfca78
GL		 2608 nvme_cancel_tagset(&dev->ctrl);
2609 nvme_cancel_admin_tagset(&dev->ctrl);
302ad8cc
KB		 2610
2611 /*
2612 * The driver will not be starting up queues again if shutting down so
2613 * must flush all entered requests to their failed completion to avoid
2614 * deadlocking blk-mq hot-cpu notifier.
2615 */
c8e9e9b7 2616 if (shutdown) {
9f27bd70 2617 nvme_unquiesce_io_queues(&dev->ctrl);
c8e9e9b7 2618 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q))
9f27bd70 2619 nvme_unquiesce_admin_queue(&dev->ctrl);
c8e9e9b7 2620 }
77bf25ea 2621 mutex_unlock(&dev->shutdown_lock);
b60503ba
MW		 2622}
2623
c1ac9a4b
KB		 2624static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown)
2625{
2626 if (!nvme_wait_reset(&dev->ctrl))
2627 return -EBUSY;
2628 nvme_dev_disable(dev, shutdown);
2629 return 0;
2630}
2631
091b6092
MW		 2632static int nvme_setup_prp_pools(struct nvme_dev *dev)
2633{
e75ec752 2634 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
c61b82c7
CH		 2635 NVME_CTRL_PAGE_SIZE,
2636 NVME_CTRL_PAGE_SIZE, 0);
091b6092
MW		 2637 if (!dev->prp_page_pool)
2638 return -ENOMEM;
2639
99802a7a 2640 /* Optimisation for I/Os between 4k and 128k */
e75ec752 2641 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
99802a7a
MW		 2642 256, 256, 0);
2643 if (!dev->prp_small_pool) {
2644 dma_pool_destroy(dev->prp_page_pool);
2645 return -ENOMEM;
2646 }
091b6092
MW		 2647 return 0;
2648}
2649
2650static void nvme_release_prp_pools(struct nvme_dev *dev)
2651{
2652 dma_pool_destroy(dev->prp_page_pool);
99802a7a 2653 dma_pool_destroy(dev->prp_small_pool);
091b6092
MW		 2654}
2655
081a7d95
CH		 2656static int nvme_pci_alloc_iod_mempool(struct nvme_dev *dev)
2657{
7846c1b5 2658 size_t alloc_size = sizeof(struct scatterlist) * NVME_MAX_SEGS;
081a7d95 2659
081a7d95
CH		 2660 dev->iod_mempool = mempool_create_node(1,
2661 mempool_kmalloc, mempool_kfree,
2662 (void *)alloc_size, GFP_KERNEL,
2663 dev_to_node(dev->dev));
2664 if (!dev->iod_mempool)
2665 return -ENOMEM;
2666 return 0;
2667}
2668
770597ec
KB		 2669static void nvme_free_tagset(struct nvme_dev *dev)
2670{
2671 if (dev->tagset.tags)
0da7feaa 2672 nvme_remove_io_tag_set(&dev->ctrl);
770597ec
KB		 2673 dev->ctrl.tagset = NULL;
2674}
2675
2e87570b 2676/* pairs with nvme_pci_alloc_dev */
1673f1f0 2677static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
5e82e952 2678{
1673f1f0 2679 struct nvme_dev *dev = to_nvme_dev(ctrl);
9ac27090 2680
770597ec 2681 nvme_free_tagset(dev);
253fd4ac
IR		 2682 put_device(dev->dev);
2683 kfree(dev->queues);
5e82e952
KB		 2684 kfree(dev);
2685}
2686
fd634f41 2687static void nvme_reset_work(struct work_struct *work)
5e82e952 2688{
d86c4d8e
CH		 2689 struct nvme_dev *dev =
2690 container_of(work, struct nvme_dev, ctrl.reset_work);
a98e58e5 2691 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
e71afda4 2692 int result;
5e82e952 2693
7764656b
ZC		 2694 if (dev->ctrl.state != NVME_CTRL_RESETTING) {
2695 dev_warn(dev->ctrl.device, "ctrl state %d is not RESETTING\n",
2696 dev->ctrl.state);
4e69d4da
KB		 2697 result = -ENODEV;
2698 goto out;
e71afda4 2699 }
5e82e952 2700
fd634f41
CH		 2701 /*
2702 * If we're called to reset a live controller first shut it down before
2703 * moving on.
2704 */
b00a726a 2705 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
a5cdb68c 2706 nvme_dev_disable(dev, false);
d6135c3a 2707 nvme_sync_queues(&dev->ctrl);
5e82e952 2708
5c959d73 2709 mutex_lock(&dev->shutdown_lock);
b00a726a 2710 result = nvme_pci_enable(dev);
f0b50732 2711 if (result)
4726bcf3 2712 goto out_unlock;
9f27bd70 2713 nvme_unquiesce_admin_queue(&dev->ctrl);
5c959d73
KB		 2714 mutex_unlock(&dev->shutdown_lock);
2715
2716 /*
2717 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
2718 * initializing procedure here.
2719 */
2720 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
2721 dev_warn(dev->ctrl.device,
2722 "failed to mark controller CONNECTING\n");
cee6c269 2723 result = -EBUSY;
5c959d73
KB		 2724 goto out;
2725 }
943e942e 2726
94cc781f 2727 result = nvme_init_ctrl_finish(&dev->ctrl, was_suspend);
ce4541f4 2728 if (result)
f58944e2 2729 goto out;
ce4541f4 2730
65a54646 2731 nvme_dbbuf_dma_alloc(dev);
f9f38e33 2732
acb71e53
CH		 2733 result = nvme_setup_host_mem(dev);
2734 if (result < 0)
2735 goto out;
87ad72a5 2736
f0b50732 2737 result = nvme_setup_io_queues(dev);
badc34d4 2738 if (result)
f58944e2 2739 goto out;
f0b50732 2740
2659e57b 2741 /*
eac3ef26
CH		 2742 * Freeze and update the number of I/O queues as thos might have
2743 * changed. If there are no I/O queues left after this reset, keep the
2744 * controller around but remove all namespaces.
2659e57b 2745 */
eac3ef26 2746 if (dev->online_queues > 1) {
9f27bd70 2747 nvme_unquiesce_io_queues(&dev->ctrl);
302ad8cc 2748 nvme_wait_freeze(&dev->ctrl);
eac3ef26 2749 nvme_pci_update_nr_queues(dev);
2455a4b7 2750 nvme_dbbuf_set(dev);
302ad8cc 2751 nvme_unfreeze(&dev->ctrl);
3cf519b5 2752 } else {
eac3ef26
CH		 2753 dev_warn(dev->ctrl.device, "IO queues lost\n");
2754 nvme_mark_namespaces_dead(&dev->ctrl);
9f27bd70 2755 nvme_unquiesce_io_queues(&dev->ctrl);
eac3ef26
CH		 2756 nvme_remove_namespaces(&dev->ctrl);
2757 nvme_free_tagset(dev);
3cf519b5
CH		 2758 }
2759
2b1b7e78
JW		 2760 /*
2761 * If only admin queue live, keep it to do further investigation or
2762 * recovery.
2763 */
5d02a5c1 2764 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
2b1b7e78 2765 dev_warn(dev->ctrl.device,
5d02a5c1 2766 "failed to mark controller live state\n");
e71afda4 2767 result = -ENODEV;
bb8d261e
CH		 2768 goto out;
2769 }
92911a55 2770
d09f2b45 2771 nvme_start_ctrl(&dev->ctrl);
3cf519b5 2772 return;
f0b50732 2773
4726bcf3
KB		 2774 out_unlock:
2775 mutex_unlock(&dev->shutdown_lock);
3cf519b5 2776 out:
c7c16c5b
CH		 2777 /*
2778 * Set state to deleting now to avoid blocking nvme_wait_reset(), which
2779 * may be holding this pci_dev's device lock.
2780 */
2781 dev_warn(dev->ctrl.device, "Disabling device after reset failure: %d\n",
2782 result);
2783 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
2784 nvme_dev_disable(dev, true);
a2b5d544 2785 nvme_sync_queues(&dev->ctrl);
c7c16c5b 2786 nvme_mark_namespaces_dead(&dev->ctrl);
2ab4e5f4 2787 nvme_unquiesce_io_queues(&dev->ctrl);
c7c16c5b 2788 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
9a6b9458
KB		 2789}
2790
1c63dc66 2791static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
9ca97374 2792{
1c63dc66 2793 *val = readl(to_nvme_dev(ctrl)->bar + off);
90667892 2794 return 0;
9ca97374
TH		 2795}
2796
5fd4ce1b 2797static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
4cc06521 2798{
5fd4ce1b
CH		 2799 writel(val, to_nvme_dev(ctrl)->bar + off);
2800 return 0;
2801}
4cc06521 2802
7fd8930f
CH		 2803static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2804{
3a8ecc93 2805 *val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off);
7fd8930f 2806 return 0;
4cc06521
KB		 2807}
2808
97c12223
KB		 2809static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
2810{
2811 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2812
2db24e4a 2813 return snprintf(buf, size, "%s\n", dev_name(&pdev->dev));
97c12223
KB		 2814}
2815
2f0dad17
KB		 2816static void nvme_pci_print_device_info(struct nvme_ctrl *ctrl)
2817{
2818 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2819 struct nvme_subsystem *subsys = ctrl->subsys;
2820
2821 dev_err(ctrl->device,
2822 "VID:DID %04x:%04x model:%.*s firmware:%.*s\n",
2823 pdev->vendor, pdev->device,
2824 nvme_strlen(subsys->model, sizeof(subsys->model)),
2825 subsys->model, nvme_strlen(subsys->firmware_rev,
2826 sizeof(subsys->firmware_rev)),
2827 subsys->firmware_rev);
2828}
2829
2f859441
LG		 2830static bool nvme_pci_supports_pci_p2pdma(struct nvme_ctrl *ctrl)
2831{
2832 struct nvme_dev *dev = to_nvme_dev(ctrl);
2833
2834 return dma_pci_p2pdma_supported(dev->dev);
2835}
2836
1c63dc66 2837static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
1a353d85 2838 .name = "pcie",
e439bb12 2839 .module = THIS_MODULE,
2f859441 2840 .flags = NVME_F_METADATA_SUPPORTED,
86adbf0c 2841 .dev_attr_groups = nvme_pci_dev_attr_groups,
1c63dc66 2842 .reg_read32 = nvme_pci_reg_read32,
5fd4ce1b 2843 .reg_write32 = nvme_pci_reg_write32,
7fd8930f 2844 .reg_read64 = nvme_pci_reg_read64,
1673f1f0 2845 .free_ctrl = nvme_pci_free_ctrl,
f866fc42 2846 .submit_async_event = nvme_pci_submit_async_event,
97c12223 2847 .get_address = nvme_pci_get_address,
2f0dad17 2848 .print_device_info = nvme_pci_print_device_info,
2f859441 2849 .supports_pci_p2pdma = nvme_pci_supports_pci_p2pdma,
1c63dc66 2850};
4cc06521 2851
b00a726a
KB		 2852static int nvme_dev_map(struct nvme_dev *dev)
2853{
b00a726a
KB		 2854 struct pci_dev *pdev = to_pci_dev(dev->dev);
2855
a1f447b3 2856 if (pci_request_mem_regions(pdev, "nvme"))
b00a726a
KB		 2857 return -ENODEV;
2858
97f6ef64 2859 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
b00a726a
KB		 2860 goto release;
2861
9fa196e7 2862 return 0;
b00a726a 2863 release:
9fa196e7
MG		 2864 pci_release_mem_regions(pdev);
2865 return -ENODEV;
b00a726a
KB		 2866}
2867
8427bbc2 2868static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
ff5350a8
AL		 2869{
2870 if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
2871 /*
2872 * Several Samsung devices seem to drop off the PCIe bus
2873 * randomly when APST is on and uses the deepest sleep state.
2874 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2875 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2876 * 950 PRO 256GB", but it seems to be restricted to two Dell
2877 * laptops.
2878 */
2879 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
2880 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
2881 dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
2882 return NVME_QUIRK_NO_DEEPEST_PS;
8427bbc2
KHF		 2883 } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
2884 /*
2885 * Samsung SSD 960 EVO drops off the PCIe bus after system
467c77d4
JJ		 2886 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
2887 * within few minutes after bootup on a Coffee Lake board -
2888 * ASUS PRIME Z370-A
8427bbc2
KHF		 2889 */
2890 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
467c77d4
JJ		 2891 (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") ||
2892 dmi_match(DMI_BOARD_NAME, "PRIME Z370-A")))
8427bbc2 2893 return NVME_QUIRK_NO_APST;
1fae37ac
S		 2894 } else if ((pdev->vendor == 0x144d && (pdev->device == 0xa801 ||
2895 pdev->device == 0xa808 || pdev->device == 0xa809)) ||
2896 (pdev->vendor == 0x1e0f && pdev->device == 0x0001)) {
2897 /*
2898 * Forcing to use host managed nvme power settings for
2899 * lowest idle power with quick resume latency on
2900 * Samsung and Toshiba SSDs based on suspend behavior
2901 * on Coffee Lake board for LENOVO C640
2902 */
2903 if ((dmi_match(DMI_BOARD_VENDOR, "LENOVO")) &&
2904 dmi_match(DMI_BOARD_NAME, "LNVNB161216"))
2905 return NVME_QUIRK_SIMPLE_SUSPEND;
ff5350a8
AL		 2906 }
2907
2908 return 0;
2909}
2910
2e87570b
CH		 2911static struct nvme_dev *nvme_pci_alloc_dev(struct pci_dev *pdev,
2912 const struct pci_device_id *id)
18119775 2913{
ff5350a8 2914 unsigned long quirks = id->driver_data;
2e87570b
CH		 2915 int node = dev_to_node(&pdev->dev);
2916 struct nvme_dev *dev;
2917 int ret = -ENOMEM;
b60503ba 2918
a4aea562 2919 if (node == NUMA_NO_NODE)
2fa84351 2920 set_dev_node(&pdev->dev, first_memory_node);
a4aea562
MB		 2921
2922 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
b60503ba 2923 if (!dev)
dc785d69 2924 return ERR_PTR(-ENOMEM);
2e87570b 2925 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
2e87570b 2926 mutex_init(&dev->shutdown_lock);
147b27e4 2927
2a5bcfdd
WZ		 2928 dev->nr_write_queues = write_queues;
2929 dev->nr_poll_queues = poll_queues;
2930 dev->nr_allocated_queues = nvme_max_io_queues(dev) + 1;
2931 dev->queues = kcalloc_node(dev->nr_allocated_queues,
2932 sizeof(struct nvme_queue), GFP_KERNEL, node);
b60503ba 2933 if (!dev->queues)
2e87570b 2934 goto out_free_dev;
b60503ba 2935
e75ec752 2936 dev->dev = get_device(&pdev->dev);
4cc06521 2937
8427bbc2 2938 quirks |= check_vendor_combination_bug(pdev);
2744d7a0 2939 if (!noacpi && acpi_storage_d3(&pdev->dev)) {
df4f9bc4
DB		 2940 /*
2941 * Some systems use a bios work around to ask for D3 on
2942 * platforms that support kernel managed suspend.
2943 */
2944 dev_info(&pdev->dev,
2945 "platform quirk: setting simple suspend\n");
2946 quirks |= NVME_QUIRK_SIMPLE_SUSPEND;
2947 }
2e87570b
CH		 2948 ret = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
2949 quirks);
2950 if (ret)
2951 goto out_put_device;
924bd96e
CH		 2952
2953 if (dev->ctrl.quirks & NVME_QUIRK_DMA_ADDRESS_BITS_48)
2954 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(48));
2955 else
2956 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
3f30a79c
CH		 2957 dma_set_min_align_mask(&pdev->dev, NVME_CTRL_PAGE_SIZE - 1);
2958 dma_set_max_seg_size(&pdev->dev, 0xffffffff);
df4f9bc4 2959
943e942e 2960 /*
3f30a79c
CH		 2961 * Limit the max command size to prevent iod->sg allocations going
2962 * over a single page.
943e942e 2963 */
3f30a79c 2964 dev->ctrl.max_hw_sectors = min_t(u32,
3710e2b0 2965 NVME_MAX_KB_SZ << 1, dma_opt_mapping_size(&pdev->dev) >> 9);
3f30a79c 2966 dev->ctrl.max_segments = NVME_MAX_SEGS;
943e942e 2967
3f30a79c
CH		 2968 /*
2969 * There is no support for SGLs for metadata (yet), so we are limited to
2970 * a single integrity segment for the separate metadata pointer.
2971 */
2972 dev->ctrl.max_integrity_segments = 1;
2e87570b 2973 return dev;
df4f9bc4 2974
2e87570b
CH		 2975out_put_device:
2976 put_device(dev->dev);
2977 kfree(dev->queues);
2978out_free_dev:
2979 kfree(dev);
2980 return ERR_PTR(ret);
2981}
943e942e 2982
2e87570b
CH		 2983static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2984{
2985 struct nvme_dev *dev;
2986 int result = -ENOMEM;
2987
2988 dev = nvme_pci_alloc_dev(pdev, id);
dc785d69
IC		 2989 if (IS_ERR(dev))
2990 return PTR_ERR(dev);
2e87570b
CH		 2991
2992 result = nvme_dev_map(dev);
b6e44b4c 2993 if (result)
2e87570b
CH		 2994 goto out_uninit_ctrl;
2995
2996 result = nvme_setup_prp_pools(dev);
081a7d95 2997 if (result)
2e87570b 2998 goto out_dev_unmap;
943e942e 2999
2e87570b 3000 result = nvme_pci_alloc_iod_mempool(dev);
b6e44b4c 3001 if (result)
2e87570b 3002 goto out_release_prp_pools;
b6e44b4c 3003
1b3c47c1
SG		 3004 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
3005
eac3ef26
CH		 3006 result = nvme_pci_enable(dev);
3007 if (result)
3008 goto out_release_iod_mempool;
3009
0da7feaa
CH		 3010 result = nvme_alloc_admin_tag_set(&dev->ctrl, &dev->admin_tagset,
3011 &nvme_mq_admin_ops, sizeof(struct nvme_iod));
eac3ef26
CH		 3012 if (result)
3013 goto out_disable;
3014
3015 /*
3016 * Mark the controller as connecting before sending admin commands to
3017 * allow the timeout handler to do the right thing.
3018 */
3019 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
3020 dev_warn(dev->ctrl.device,
3021 "failed to mark controller CONNECTING\n");
3022 result = -EBUSY;
3023 goto out_disable;
3024 }
3025
3026 result = nvme_init_ctrl_finish(&dev->ctrl, false);
3027 if (result)
3028 goto out_disable;
3029
3030 nvme_dbbuf_dma_alloc(dev);
3031
3032 result = nvme_setup_host_mem(dev);
3033 if (result < 0)
3034 goto out_disable;
3035
3036 result = nvme_setup_io_queues(dev);
3037 if (result)
3038 goto out_disable;
4caff8fc 3039
eac3ef26 3040 if (dev->online_queues > 1) {
0da7feaa
CH		 3041 nvme_alloc_io_tag_set(&dev->ctrl, &dev->tagset, &nvme_mq_ops,
3042 nvme_pci_nr_maps(dev), sizeof(struct nvme_iod));
eac3ef26 3043 nvme_dbbuf_set(dev);
eac3ef26
CH		 3044 }
3045
0da7feaa
CH		 3046 if (!dev->ctrl.tagset)
3047 dev_warn(dev->ctrl.device, "IO queues not created\n");
3048
eac3ef26
CH		 3049 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
3050 dev_warn(dev->ctrl.device,
3051 "failed to mark controller live state\n");
3052 result = -ENODEV;
3053 goto out_disable;
3054 }
3055
2e87570b 3056 pci_set_drvdata(pdev, dev);
1b3c47c1 3057
eac3ef26
CH		 3058 nvme_start_ctrl(&dev->ctrl);
3059 nvme_put_ctrl(&dev->ctrl);
5a5754a4 3060 flush_work(&dev->ctrl.scan_work);
b60503ba
MW		 3061 return 0;
3062
eac3ef26
CH		 3063out_disable:
3064 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
3065 nvme_dev_disable(dev, true);
3066 nvme_free_host_mem(dev);
3067 nvme_dev_remove_admin(dev);
3068 nvme_dbbuf_dma_free(dev);
3069 nvme_free_queues(dev, 0);
3070out_release_iod_mempool:
b6e44b4c 3071 mempool_destroy(dev->iod_mempool);
2e87570b 3072out_release_prp_pools:
091b6092 3073 nvme_release_prp_pools(dev);
2e87570b 3074out_dev_unmap:
b00c9b7a 3075 nvme_dev_unmap(dev);
2e87570b
CH		 3076out_uninit_ctrl:
3077 nvme_uninit_ctrl(&dev->ctrl);
a61d2655 3078 nvme_put_ctrl(&dev->ctrl);
b60503ba
MW		 3079 return result;
3080}
3081
775755ed 3082static void nvme_reset_prepare(struct pci_dev *pdev)
f0d54a54 3083{
a6739479 3084 struct nvme_dev *dev = pci_get_drvdata(pdev);
c1ac9a4b
KB		 3085
3086 /*
3087 * We don't need to check the return value from waiting for the reset
3088 * state as pci_dev device lock is held, making it impossible to race
3089 * with ->remove().
3090 */
3091 nvme_disable_prepare_reset(dev, false);
3092 nvme_sync_queues(&dev->ctrl);
775755ed 3093}
f0d54a54 3094
775755ed
CH		 3095static void nvme_reset_done(struct pci_dev *pdev)
3096{
f263fbb8 3097 struct nvme_dev *dev = pci_get_drvdata(pdev);
c1ac9a4b
KB		 3098
3099 if (!nvme_try_sched_reset(&dev->ctrl))
3100 flush_work(&dev->ctrl.reset_work);
f0d54a54
KB		 3101}
3102
09ece142
KB		 3103static void nvme_shutdown(struct pci_dev *pdev)
3104{
3105 struct nvme_dev *dev = pci_get_drvdata(pdev);
4e523547 3106
c1ac9a4b 3107 nvme_disable_prepare_reset(dev, true);
09ece142
KB		 3108}
3109
f58944e2
KB		 3110/*
3111 * The driver's remove may be called on a device in a partially initialized
3112 * state. This function must not have any dependencies on the device state in
3113 * order to proceed.
3114 */
8d85fce7 3115static void nvme_remove(struct pci_dev *pdev)
b60503ba
MW		 3116{
3117 struct nvme_dev *dev = pci_get_drvdata(pdev);
9a6b9458 3118
bb8d261e 3119 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
9a6b9458 3120 pci_set_drvdata(pdev, NULL);
0ff9d4e1 3121
6db28eda 3122 if (!pci_device_is_present(pdev)) {
0ff9d4e1 3123 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
1d39e692 3124 nvme_dev_disable(dev, true);
6db28eda 3125 }
0ff9d4e1 3126
d86c4d8e 3127 flush_work(&dev->ctrl.reset_work);
d09f2b45
SG		 3128 nvme_stop_ctrl(&dev->ctrl);
3129 nvme_remove_namespaces(&dev->ctrl);
a5cdb68c 3130 nvme_dev_disable(dev, true);
87ad72a5 3131 nvme_free_host_mem(dev);
a4aea562 3132 nvme_dev_remove_admin(dev);
c11b7716 3133 nvme_dbbuf_dma_free(dev);
a1a5ef99 3134 nvme_free_queues(dev, 0);
c11b7716 3135 mempool_destroy(dev->iod_mempool);
9a6b9458 3136 nvme_release_prp_pools(dev);
b00a726a 3137 nvme_dev_unmap(dev);
726612b6 3138 nvme_uninit_ctrl(&dev->ctrl);
b60503ba
MW		 3139}
3140
671a6018 3141#ifdef CONFIG_PM_SLEEP
d916b1be
KB		 3142static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps)
3143{
3144 return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps);
3145}
3146
3147static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps)
3148{
3149 return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL);
3150}
3151
3152static int nvme_resume(struct device *dev)
3153{
3154 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
3155 struct nvme_ctrl *ctrl = &ndev->ctrl;
3156
4eaefe8c 3157 if (ndev->last_ps == U32_MAX ||
d916b1be 3158 nvme_set_power_state(ctrl, ndev->last_ps) != 0)
e5ad96f3
KB		 3159 goto reset;
3160 if (ctrl->hmpre && nvme_setup_host_mem(ndev))
3161 goto reset;
3162
d916b1be 3163 return 0;
e5ad96f3
KB		 3164reset:
3165 return nvme_try_sched_reset(ctrl);
d916b1be
KB		 3166}
3167
cd638946
KB		 3168static int nvme_suspend(struct device *dev)
3169{
3170 struct pci_dev *pdev = to_pci_dev(dev);
3171 struct nvme_dev *ndev = pci_get_drvdata(pdev);
d916b1be
KB		 3172 struct nvme_ctrl *ctrl = &ndev->ctrl;
3173 int ret = -EBUSY;
3174
4eaefe8c
RW		 3175 ndev->last_ps = U32_MAX;
3176
d916b1be
KB		 3177 /*
3178 * The platform does not remove power for a kernel managed suspend so
3179 * use host managed nvme power settings for lowest idle power if
3180 * possible. This should have quicker resume latency than a full device
3181 * shutdown. But if the firmware is involved after the suspend or the
3182 * device does not support any non-default power states, shut down the
3183 * device fully.
4eaefe8c
RW		 3184 *
3185 * If ASPM is not enabled for the device, shut down the device and allow
3186 * the PCI bus layer to put it into D3 in order to take the PCIe link
3187 * down, so as to allow the platform to achieve its minimum low-power
3188 * state (which may not be possible if the link is up).
d916b1be 3189 */
4eaefe8c 3190 if (pm_suspend_via_firmware() || !ctrl->npss ||
cb32de1b 3191 !pcie_aspm_enabled(pdev) ||
c1ac9a4b
KB		 3192 (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND))
3193 return nvme_disable_prepare_reset(ndev, true);
d916b1be
KB		 3194
3195 nvme_start_freeze(ctrl);
3196 nvme_wait_freeze(ctrl);
3197 nvme_sync_queues(ctrl);
3198
5d02a5c1 3199 if (ctrl->state != NVME_CTRL_LIVE)
d916b1be
KB		 3200 goto unfreeze;
3201
e5ad96f3
KB		 3202 /*
3203 * Host memory access may not be successful in a system suspend state,
3204 * but the specification allows the controller to access memory in a
3205 * non-operational power state.
3206 */
3207 if (ndev->hmb) {
3208 ret = nvme_set_host_mem(ndev, 0);
3209 if (ret < 0)
3210 goto unfreeze;
3211 }
3212
d916b1be
KB		 3213 ret = nvme_get_power_state(ctrl, &ndev->last_ps);
3214 if (ret < 0)
3215 goto unfreeze;
3216
7cbb5c6f
ML		 3217 /*
3218 * A saved state prevents pci pm from generically controlling the
3219 * device's power. If we're using protocol specific settings, we don't
3220 * want pci interfering.
3221 */
3222 pci_save_state(pdev);
3223
d916b1be
KB		 3224 ret = nvme_set_power_state(ctrl, ctrl->npss);
3225 if (ret < 0)
3226 goto unfreeze;
3227
3228 if (ret) {
7cbb5c6f
ML		 3229 /* discard the saved state */
3230 pci_load_saved_state(pdev, NULL);
3231
d916b1be
KB		 3232 /*
3233 * Clearing npss forces a controller reset on resume. The
05d3046f 3234 * correct value will be rediscovered then.
d916b1be 3235 */
c1ac9a4b 3236 ret = nvme_disable_prepare_reset(ndev, true);
d916b1be 3237 ctrl->npss = 0;
d916b1be 3238 }
d916b1be
KB		 3239unfreeze:
3240 nvme_unfreeze(ctrl);
3241 return ret;
3242}
3243
3244static int nvme_simple_suspend(struct device *dev)
3245{
3246 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
4e523547 3247
c1ac9a4b 3248 return nvme_disable_prepare_reset(ndev, true);
cd638946
KB		 3249}
3250
d916b1be 3251static int nvme_simple_resume(struct device *dev)
cd638946
KB		 3252{
3253 struct pci_dev *pdev = to_pci_dev(dev);
3254 struct nvme_dev *ndev = pci_get_drvdata(pdev);
cd638946 3255
c1ac9a4b 3256 return nvme_try_sched_reset(&ndev->ctrl);
cd638946
KB		 3257}
3258
21774222 3259static const struct dev_pm_ops nvme_dev_pm_ops = {
d916b1be
KB		 3260 .suspend = nvme_suspend,
3261 .resume = nvme_resume,
3262 .freeze = nvme_simple_suspend,
3263 .thaw = nvme_simple_resume,
3264 .poweroff = nvme_simple_suspend,
3265 .restore = nvme_simple_resume,
3266};
3267#endif /* CONFIG_PM_SLEEP */
b60503ba 3268
a0a3408e
KB		 3269static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
3270 pci_channel_state_t state)
3271{
3272 struct nvme_dev *dev = pci_get_drvdata(pdev);
3273
3274 /*
3275 * A frozen channel requires a reset. When detected, this method will
3276 * shutdown the controller to quiesce. The controller will be restarted
3277 * after the slot reset through driver's slot_reset callback.
3278 */
a0a3408e
KB		 3279 switch (state) {
3280 case pci_channel_io_normal:
3281 return PCI_ERS_RESULT_CAN_RECOVER;
3282 case pci_channel_io_frozen:
d011fb31
KB		 3283 dev_warn(dev->ctrl.device,
3284 "frozen state error detected, reset controller\n");
71a5bb15
KB		 3285 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_RESETTING)) {
3286 nvme_dev_disable(dev, true);
3287 return PCI_ERS_RESULT_DISCONNECT;
3288 }
a5cdb68c 3289 nvme_dev_disable(dev, false);
a0a3408e
KB		 3290 return PCI_ERS_RESULT_NEED_RESET;
3291 case pci_channel_io_perm_failure:
d011fb31
KB		 3292 dev_warn(dev->ctrl.device,
3293 "failure state error detected, request disconnect\n");
a0a3408e
KB		 3294 return PCI_ERS_RESULT_DISCONNECT;
3295 }
3296 return PCI_ERS_RESULT_NEED_RESET;
3297}
3298
3299static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
3300{
3301 struct nvme_dev *dev = pci_get_drvdata(pdev);
3302
1b3c47c1 3303 dev_info(dev->ctrl.device, "restart after slot reset\n");
a0a3408e 3304 pci_restore_state(pdev);
71a5bb15
KB		 3305 if (!nvme_try_sched_reset(&dev->ctrl))
3306 nvme_unquiesce_io_queues(&dev->ctrl);
a0a3408e
KB		 3307 return PCI_ERS_RESULT_RECOVERED;
3308}
3309
3310static void nvme_error_resume(struct pci_dev *pdev)
3311{
72cd4cc2
KB		 3312 struct nvme_dev *dev = pci_get_drvdata(pdev);
3313
3314 flush_work(&dev->ctrl.reset_work);
a0a3408e
KB		 3315}
3316
1d352035 3317static const struct pci_error_handlers nvme_err_handler = {
b60503ba 3318 .error_detected = nvme_error_detected,
b60503ba
MW		 3319 .slot_reset = nvme_slot_reset,
3320 .resume = nvme_error_resume,
775755ed
CH		 3321 .reset_prepare = nvme_reset_prepare,
3322 .reset_done = nvme_reset_done,
b60503ba
MW		 3323};
3324
6eb0d698 3325static const struct pci_device_id nvme_id_table[] = {
972b13e2 3326 { PCI_VDEVICE(INTEL, 0x0953), /* Intel 750/P3500/P3600/P3700 */
08095e70 3327 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 3328 NVME_QUIRK_DEALLOCATE_ZEROES, },
972b13e2 3329 { PCI_VDEVICE(INTEL, 0x0a53), /* Intel P3520 */
99466e70 3330 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 3331 NVME_QUIRK_DEALLOCATE_ZEROES, },
972b13e2 3332 { PCI_VDEVICE(INTEL, 0x0a54), /* Intel P4500/P4600 */
99466e70 3333 .driver_data = NVME_QUIRK_STRIPE_SIZE |
25e58af4
WZ		 3334 NVME_QUIRK_DEALLOCATE_ZEROES |
3335 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
972b13e2 3336 { PCI_VDEVICE(INTEL, 0x0a55), /* Dell Express Flash P4600 */
f99cb7af
DWF		 3337 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3338 NVME_QUIRK_DEALLOCATE_ZEROES, },
50af47d0 3339 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */
9abd68ef 3340 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
6c6aa2f2 3341 NVME_QUIRK_MEDIUM_PRIO_SQ |
ce4cc313
DM		 3342 NVME_QUIRK_NO_TEMP_THRESH_CHANGE |
3343 NVME_QUIRK_DISABLE_WRITE_ZEROES, },
6299358d
JD		 3344 { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */
3345 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
540c801c 3346 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */
7b210e4e 3347 .driver_data = NVME_QUIRK_IDENTIFY_CNS |
66dd346b
CH		 3348 NVME_QUIRK_DISABLE_WRITE_ZEROES |
3349 NVME_QUIRK_BOGUS_NID, },
3350 { PCI_VDEVICE(REDHAT, 0x0010), /* Qemu emulated controller */
3351 .driver_data = NVME_QUIRK_BOGUS_NID, },
5bedd3af 3352 { PCI_DEVICE(0x126f, 0x2263), /* Silicon Motion unidentified */
c98a8793
KB		 3353 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST |
3354 NVME_QUIRK_BOGUS_NID, },
0302ae60 3355 { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */
5e112d3f
JE		 3356 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
3357 NVME_QUIRK_NO_NS_DESC_LIST, },
54adc010
GP		 3358 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
3359 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
8c97eecc
JL		 3360 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */
3361 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
015282c9
WW		 3362 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
3363 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
d554b5e1
MP		 3364 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */
3365 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3366 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */
7ee5c78c 3367 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
abbb5f59 3368 NVME_QUIRK_DISABLE_WRITE_ZEROES|
7ee5c78c 3369 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
2cf7a77e
KB		 3370 { PCI_DEVICE(0x1987, 0x5012), /* Phison E12 */
3371 .driver_data = NVME_QUIRK_BOGUS_NID, },
c9e95c39 3372 { PCI_DEVICE(0x1987, 0x5016), /* Phison E16 */
73029c9b
KB		 3373 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN |
3374 NVME_QUIRK_BOGUS_NID, },
d14c2731
TH		 3375 { PCI_DEVICE(0x1987, 0x5019), /* phison E19 */
3376 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3377 { PCI_DEVICE(0x1987, 0x5021), /* Phison E21 */
3378 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
6e6a6828
PT		 3379 { PCI_DEVICE(0x1b4b, 0x1092), /* Lexar 256 GB SSD */
3380 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST |
3381 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
e1c70d79
LVS		 3382 { PCI_DEVICE(0x1cc1, 0x33f8), /* ADATA IM2P33F8ABR1 1 TB */
3383 .driver_data = NVME_QUIRK_BOGUS_NID, },
08b903b5 3384 { PCI_DEVICE(0x10ec, 0x5762), /* ADATA SX6000LNP */
1629de0e
PG		 3385 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN |
3386 NVME_QUIRK_BOGUS_NID, },
5f69f009
DW		 3387 { PCI_DEVICE(0x10ec, 0x5763), /* ADATA SX6000PNP */
3388 .driver_data = NVME_QUIRK_BOGUS_NID, },
f03e42c6
GC		 3389 { PCI_DEVICE(0x1cc1, 0x8201), /* ADATA SX8200PNP 512GB */
3390 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3391 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
41f38043
LS		 3392 { PCI_DEVICE(0x1344, 0x5407), /* Micron Technology Inc NVMe SSD */
3393 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN },
d5ceb4d1
BH		 3394 { PCI_DEVICE(0x1344, 0x6001), /* Micron Nitro NVMe */
3395 .driver_data = NVME_QUIRK_BOGUS_NID, },
5611ec2b
KHF		 3396 { PCI_DEVICE(0x1c5c, 0x1504), /* SK Hynix PC400 */
3397 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
c4f01a77
KB		 3398 { PCI_DEVICE(0x1c5c, 0x174a), /* SK Hynix P31 SSD */
3399 .driver_data = NVME_QUIRK_BOGUS_NID, },
02ca079c
KHF		 3400 { PCI_DEVICE(0x15b7, 0x2001), /* Sandisk Skyhawk */
3401 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
89919929
CK		 3402 { PCI_DEVICE(0x1d97, 0x2263), /* SPCC */
3403 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
43047e08 3404 { PCI_DEVICE(0x144d, 0xa80b), /* Samsung PM9B1 256G and 512G */
3405 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3406 { PCI_DEVICE(0x144d, 0xa809), /* Samsung MZALQ256HBJD 256G */
3407 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
e5bb0988
PR		 3408 { PCI_DEVICE(0x144d, 0xa802), /* Samsung SM953 */
3409 .driver_data = NVME_QUIRK_BOGUS_NID, },
43047e08 3410 { PCI_DEVICE(0x1cc4, 0x6303), /* UMIS RPJTJ512MGE1QDY 512G */
3411 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3412 { PCI_DEVICE(0x1cc4, 0x6302), /* UMIS RPJTJ256MGE1QDY 256G */
3413 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
dc22c1c0
ZB		 3414 { PCI_DEVICE(0x2646, 0x2262), /* KINGSTON SKC2000 NVMe SSD */
3415 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
538e4a8c
TL		 3416 { PCI_DEVICE(0x2646, 0x2263), /* KINGSTON A2000 NVMe SSD */
3417 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
bd375fee
HV		 3418 { PCI_DEVICE(0x2646, 0x5013), /* Kingston KC3000, Kingston FURY Renegade */
3419 .driver_data = NVME_QUIRK_NO_SECONDARY_TEMP_THRESH, },
ac9b57d4
XL		 3420 { PCI_DEVICE(0x2646, 0x5018), /* KINGSTON OM8SFP4xxxxP OS21012 NVMe SSD */
3421 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3422 { PCI_DEVICE(0x2646, 0x5016), /* KINGSTON OM3PGP4xxxxP OS21011 NVMe SSD */
3423 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3424 { PCI_DEVICE(0x2646, 0x501A), /* KINGSTON OM8PGP4xxxxP OS21005 NVMe SSD */
3425 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3426 { PCI_DEVICE(0x2646, 0x501B), /* KINGSTON OM8PGP4xxxxQ OS21005 NVMe SSD */
3427 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3428 { PCI_DEVICE(0x2646, 0x501E), /* KINGSTON OM3PGP4xxxxQ OS21011 NVMe SSD */
3429 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
9630d806
EMMG		 3430 { PCI_DEVICE(0x1f40, 0x1202), /* Netac Technologies Co. NV3000 NVMe SSD */
3431 .driver_data = NVME_QUIRK_BOGUS_NID, },
8d6e38f6
TDF		 3432 { PCI_DEVICE(0x1f40, 0x5236), /* Netac Technologies Co. NV7000 NVMe SSD */
3433 .driver_data = NVME_QUIRK_BOGUS_NID, },
70ce3455
CH		 3434 { PCI_DEVICE(0x1e4B, 0x1001), /* MAXIO MAP1001 */
3435 .driver_data = NVME_QUIRK_BOGUS_NID, },
a98a945b
CH		 3436 { PCI_DEVICE(0x1e4B, 0x1002), /* MAXIO MAP1002 */
3437 .driver_data = NVME_QUIRK_BOGUS_NID, },
3438 { PCI_DEVICE(0x1e4B, 0x1202), /* MAXIO MAP1202 */
3439 .driver_data = NVME_QUIRK_BOGUS_NID, },
a3a9d63d
TS		 3440 { PCI_DEVICE(0x1e4B, 0x1602), /* MAXIO MAP1602 */
3441 .driver_data = NVME_QUIRK_BOGUS_NID, },
3765fad5
SR		 3442 { PCI_DEVICE(0x1cc1, 0x5350), /* ADATA XPG GAMMIX S50 */
3443 .driver_data = NVME_QUIRK_BOGUS_NID, },
f37527a0
DK		 3444 { PCI_DEVICE(0x1dbe, 0x5236), /* ADATA XPG GAMMIX S70 */
3445 .driver_data = NVME_QUIRK_BOGUS_NID, },
d5d3c100
XR		 3446 { PCI_DEVICE(0x1e49, 0x0021), /* ZHITAI TiPro5000 NVMe SSD */
3447 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
6b961bce
NW		 3448 { PCI_DEVICE(0x1e49, 0x0041), /* ZHITAI TiPro7000 NVMe SSD */
3449 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
d6c52fa3
TG		 3450 { PCI_DEVICE(0xc0a9, 0x540a), /* Crucial P2 */
3451 .driver_data = NVME_QUIRK_BOGUS_NID, },
200dccd0
SA		 3452 { PCI_DEVICE(0x1d97, 0x2263), /* Lexar NM610 */
3453 .driver_data = NVME_QUIRK_BOGUS_NID, },
b65d44fa
PG		 3454 { PCI_DEVICE(0x1d97, 0x1d97), /* Lexar NM620 */
3455 .driver_data = NVME_QUIRK_BOGUS_NID, },
80b26240 3456 { PCI_DEVICE(0x1d97, 0x2269), /* Lexar NM760 */
1231363a
JP		 3457 .driver_data = NVME_QUIRK_BOGUS_NID |
3458 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
74391b3e
DT		 3459 { PCI_DEVICE(0x10ec, 0x5763), /* TEAMGROUP T-FORCE CARDEA ZERO Z330 SSD */
3460 .driver_data = NVME_QUIRK_BOGUS_NID, },
1616d6c3
SG		 3461 { PCI_DEVICE(0x1e4b, 0x1602), /* HS-SSD-FUTURE 2048G */
3462 .driver_data = NVME_QUIRK_BOGUS_NID, },
06497281
DS		 3463 { PCI_DEVICE(0x10ec, 0x5765), /* TEAMGROUP MP33 2TB SSD */
3464 .driver_data = NVME_QUIRK_BOGUS_NID, },
4bdf2603
FS		 3465 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0061),
3466 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3467 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0065),
3468 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3469 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x8061),
3470 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3471 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd00),
3472 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3473 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd01),
3474 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3475 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd02),
3476 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
98f7b86a
AS		 3477 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001),
3478 .driver_data = NVME_QUIRK_SINGLE_VECTOR },
124298bd 3479 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
66341331
BH		 3480 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005),
3481 .driver_data = NVME_QUIRK_SINGLE_VECTOR |
d38e9f04 3482 NVME_QUIRK_128_BYTES_SQES |
a2941f6a 3483 NVME_QUIRK_SHARED_TAGS |
453116a4
HM		 3484 NVME_QUIRK_SKIP_CID_GEN |
3485 NVME_QUIRK_IDENTIFY_CNS },
0b85f59d 3486 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
b60503ba
MW		 3487 { 0, }
3488};
3489MODULE_DEVICE_TABLE(pci, nvme_id_table);
3490
3491static struct pci_driver nvme_driver = {
3492 .name = "nvme",
3493 .id_table = nvme_id_table,
3494 .probe = nvme_probe,
8d85fce7 3495 .remove = nvme_remove,
09ece142 3496 .shutdown = nvme_shutdown,
cd638946 3497 .driver = {
eac3ef26
CH		 3498 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
3499#ifdef CONFIG_PM_SLEEP
3500 .pm = &nvme_dev_pm_ops,
d916b1be 3501#endif
eac3ef26 3502 },
74d986ab 3503 .sriov_configure = pci_sriov_configure_simple,
b60503ba
MW		 3504 .err_handler = &nvme_err_handler,
3505};
3506
3507static int __init nvme_init(void)
3508{
81101540
CH		 3509 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
3510 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
3511 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
612b7286 3512 BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2);
01df742d 3513 BUILD_BUG_ON(NVME_MAX_SEGS > SGES_PER_PAGE);
7846c1b5
KB		 3514 BUILD_BUG_ON(sizeof(struct scatterlist) * NVME_MAX_SEGS > PAGE_SIZE);
3515 BUILD_BUG_ON(nvme_pci_npages_prp() > NVME_MAX_NR_ALLOCATIONS);
17c33167 3516
9a6327d2 3517 return pci_register_driver(&nvme_driver);
b60503ba
MW		 3518}
3519
3520static void __exit nvme_exit(void)
3521{
3522 pci_unregister_driver(&nvme_driver);
03e0f3a6 3523 flush_workqueue(nvme_wq);
b60503ba
MW		 3524}
3525
3526MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3527MODULE_LICENSE("GPL");
c78b4713 3528MODULE_VERSION("1.0");
b60503ba
MW		 3529module_init(nvme_init);
3530module_exit(nvme_exit);
Linux 6.x block layer and io_uring tree(s)