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nvme: keep ctrl->namespaces ordered
[linux-2.6-block.git] / drivers / nvme / host / pci.c
CommitLineData
5f37396d 1// SPDX-License-Identifier: GPL-2.0
b60503ba
MW		 2/*
3 * NVM Express device driver
6eb0d698 4 * Copyright (c) 2011-2014, Intel Corporation.
b60503ba
MW		 5 */
6
df4f9bc4 7#include <linux/acpi.h>
a0a3408e 8#include <linux/aer.h>
18119775 9#include <linux/async.h>
b60503ba 10#include <linux/blkdev.h>
a4aea562 11#include <linux/blk-mq.h>
dca51e78 12#include <linux/blk-mq-pci.h>
ff5350a8 13#include <linux/dmi.h>
b60503ba
MW		 14#include <linux/init.h>
15#include <linux/interrupt.h>
16#include <linux/io.h>
b60503ba
MW		 17#include <linux/mm.h>
18#include <linux/module.h>
77bf25ea 19#include <linux/mutex.h>
d0877473 20#include <linux/once.h>
b60503ba 21#include <linux/pci.h>
d916b1be 22#include <linux/suspend.h>
e1e5e564 23#include <linux/t10-pi.h>
b60503ba 24#include <linux/types.h>
2f8e2c87 25#include <linux/io-64-nonatomic-lo-hi.h>
20d3bb92 26#include <linux/io-64-nonatomic-hi-lo.h>
a98e58e5 27#include <linux/sed-opal.h>
0f238ff5 28#include <linux/pci-p2pdma.h>
797a796a 29
604c01d5 30#include "trace.h"
f11bb3e2
CH		 31#include "nvme.h"
32
c1e0cc7e 33#define SQ_SIZE(q) ((q)->q_depth << (q)->sqes)
8a1d09a6 34#define CQ_SIZE(q) ((q)->q_depth * sizeof(struct nvme_completion))
c965809c 35
a7a7cbe3 36#define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc))
9d43cf64 37
943e942e
JA		 38/*
39 * These can be higher, but we need to ensure that any command doesn't
40 * require an sg allocation that needs more than a page of data.
41 */
42#define NVME_MAX_KB_SZ 4096
43#define NVME_MAX_SEGS 127
44
58ffacb5
MW		 45static int use_threaded_interrupts;
46module_param(use_threaded_interrupts, int, 0);
47
8ffaadf7 48static bool use_cmb_sqes = true;
69f4eb9f 49module_param(use_cmb_sqes, bool, 0444);
8ffaadf7
JD		 50MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
51
87ad72a5
CH		 52static unsigned int max_host_mem_size_mb = 128;
53module_param(max_host_mem_size_mb, uint, 0444);
54MODULE_PARM_DESC(max_host_mem_size_mb,
55 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
1fa6aead 56
a7a7cbe3
CK		 57static unsigned int sgl_threshold = SZ_32K;
58module_param(sgl_threshold, uint, 0644);
59MODULE_PARM_DESC(sgl_threshold,
60 "Use SGLs when average request segment size is larger or equal to "
61 "this size. Use 0 to disable SGLs.");
62
27453b45
SG		 63#define NVME_PCI_MIN_QUEUE_SIZE 2
64#define NVME_PCI_MAX_QUEUE_SIZE 4095
b27c1e68 65static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
66static const struct kernel_param_ops io_queue_depth_ops = {
67 .set = io_queue_depth_set,
61f3b896 68 .get = param_get_uint,
b27c1e68 69};
70
61f3b896 71static unsigned int io_queue_depth = 1024;
b27c1e68 72module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
27453b45 73MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2 and < 4096");
b27c1e68 74
9c9e76d5
WZ		 75static int io_queue_count_set(const char *val, const struct kernel_param *kp)
76{
77 unsigned int n;
78 int ret;
79
80 ret = kstrtouint(val, 10, &n);
81 if (ret != 0 || n > num_possible_cpus())
82 return -EINVAL;
83 return param_set_uint(val, kp);
84}
85
86static const struct kernel_param_ops io_queue_count_ops = {
87 .set = io_queue_count_set,
88 .get = param_get_uint,
89};
90
3f68baf7 91static unsigned int write_queues;
9c9e76d5 92module_param_cb(write_queues, &io_queue_count_ops, &write_queues, 0644);
3b6592f7
JA		 93MODULE_PARM_DESC(write_queues,
94 "Number of queues to use for writes. If not set, reads and writes "
95 "will share a queue set.");
96
3f68baf7 97static unsigned int poll_queues;
9c9e76d5 98module_param_cb(poll_queues, &io_queue_count_ops, &poll_queues, 0644);
4b04cc6a
JA		 99MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO.");
100
df4f9bc4
DB		 101static bool noacpi;
102module_param(noacpi, bool, 0444);
103MODULE_PARM_DESC(noacpi, "disable acpi bios quirks");
104
1c63dc66
CH		 105struct nvme_dev;
106struct nvme_queue;
b3fffdef 107
a5cdb68c 108static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
8fae268b 109static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode);
d4b4ff8e 110
1c63dc66
CH		 111/*
112 * Represents an NVM Express device. Each nvme_dev is a PCI function.
113 */
114struct nvme_dev {
147b27e4 115 struct nvme_queue *queues;
1c63dc66
CH		 116 struct blk_mq_tag_set tagset;
117 struct blk_mq_tag_set admin_tagset;
118 u32 __iomem *dbs;
119 struct device *dev;
120 struct dma_pool *prp_page_pool;
121 struct dma_pool *prp_small_pool;
1c63dc66
CH		 122 unsigned online_queues;
123 unsigned max_qid;
e20ba6e1 124 unsigned io_queues[HCTX_MAX_TYPES];
22b55601 125 unsigned int num_vecs;
7442ddce 126 u32 q_depth;
c1e0cc7e 127 int io_sqes;
1c63dc66 128 u32 db_stride;
1c63dc66 129 void __iomem *bar;
97f6ef64 130 unsigned long bar_mapped_size;
5c8809e6 131 struct work_struct remove_work;
77bf25ea 132 struct mutex shutdown_lock;
1c63dc66 133 bool subsystem;
1c63dc66 134 u64 cmb_size;
0f238ff5 135 bool cmb_use_sqes;
1c63dc66 136 u32 cmbsz;
202021c1 137 u32 cmbloc;
1c63dc66 138 struct nvme_ctrl ctrl;
d916b1be 139 u32 last_ps;
a5df5e79 140 bool hmb;
87ad72a5 141
943e942e
JA		 142 mempool_t *iod_mempool;
143
87ad72a5 144 /* shadow doorbell buffer support: */
f9f38e33
HK		 145 u32 *dbbuf_dbs;
146 dma_addr_t dbbuf_dbs_dma_addr;
147 u32 *dbbuf_eis;
148 dma_addr_t dbbuf_eis_dma_addr;
87ad72a5
CH		 149
150 /* host memory buffer support: */
151 u64 host_mem_size;
152 u32 nr_host_mem_descs;
4033f35d 153 dma_addr_t host_mem_descs_dma;
87ad72a5
CH		 154 struct nvme_host_mem_buf_desc *host_mem_descs;
155 void **host_mem_desc_bufs;
2a5bcfdd
WZ		 156 unsigned int nr_allocated_queues;
157 unsigned int nr_write_queues;
158 unsigned int nr_poll_queues;
0521905e
KB		 159
160 bool attrs_added;
4d115420 161};
1fa6aead 162
b27c1e68 163static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
164{
27453b45
SG		 165 return param_set_uint_minmax(val, kp, NVME_PCI_MIN_QUEUE_SIZE,
166 NVME_PCI_MAX_QUEUE_SIZE);
b27c1e68 167}
168
f9f38e33
HK		 169static inline unsigned int sq_idx(unsigned int qid, u32 stride)
170{
171 return qid * 2 * stride;
172}
173
174static inline unsigned int cq_idx(unsigned int qid, u32 stride)
175{
176 return (qid * 2 + 1) * stride;
177}
178
1c63dc66
CH		 179static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
180{
181 return container_of(ctrl, struct nvme_dev, ctrl);
182}
183
b60503ba
MW		 184/*
185 * An NVM Express queue. Each device has at least two (one for admin
186 * commands and one for I/O commands).
187 */
188struct nvme_queue {
091b6092 189 struct nvme_dev *dev;
1ab0cd69 190 spinlock_t sq_lock;
c1e0cc7e 191 void *sq_cmds;
3a7afd8e
CH		 192 /* only used for poll queues: */
193 spinlock_t cq_poll_lock ____cacheline_aligned_in_smp;
74943d45 194 struct nvme_completion *cqes;
b60503ba
MW		 195 dma_addr_t sq_dma_addr;
196 dma_addr_t cq_dma_addr;
b60503ba 197 u32 __iomem *q_db;
7442ddce 198 u32 q_depth;
7c349dde 199 u16 cq_vector;
b60503ba 200 u16 sq_tail;
38210800 201 u16 last_sq_tail;
b60503ba 202 u16 cq_head;
c30341dc 203 u16 qid;
e9539f47 204 u8 cq_phase;
c1e0cc7e 205 u8 sqes;
4e224106
CH		 206 unsigned long flags;
207#define NVMEQ_ENABLED 0
63223078 208#define NVMEQ_SQ_CMB 1
d1ed6aa1 209#define NVMEQ_DELETE_ERROR 2
7c349dde 210#define NVMEQ_POLLED 3
f9f38e33
HK		 211 u32 *dbbuf_sq_db;
212 u32 *dbbuf_cq_db;
213 u32 *dbbuf_sq_ei;
214 u32 *dbbuf_cq_ei;
d1ed6aa1 215 struct completion delete_done;
b60503ba
MW		 216};
217
71bd150c 218/*
9b048119
CH		 219 * The nvme_iod describes the data in an I/O.
220 *
221 * The sg pointer contains the list of PRP/SGL chunk allocations in addition
222 * to the actual struct scatterlist.
71bd150c
CH		 223 */
224struct nvme_iod {
d49187e9 225 struct nvme_request req;
af7fae85 226 struct nvme_command cmd;
f4800d6d 227 struct nvme_queue *nvmeq;
a7a7cbe3 228 bool use_sgl;
f4800d6d 229 int aborted;
71bd150c 230 int npages; /* In the PRP list. 0 means small pool in use */
71bd150c 231 int nents; /* Used in scatterlist */
71bd150c 232 dma_addr_t first_dma;
dff824b2 233 unsigned int dma_len; /* length of single DMA segment mapping */
783b94bd 234 dma_addr_t meta_dma;
f4800d6d 235 struct scatterlist *sg;
b60503ba
MW		 236};
237
2a5bcfdd 238static inline unsigned int nvme_dbbuf_size(struct nvme_dev *dev)
3b6592f7 239{
2a5bcfdd 240 return dev->nr_allocated_queues * 8 * dev->db_stride;
f9f38e33
HK		 241}
242
243static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
244{
2a5bcfdd 245 unsigned int mem_size = nvme_dbbuf_size(dev);
f9f38e33
HK		 246
247 if (dev->dbbuf_dbs)
248 return 0;
249
250 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
251 &dev->dbbuf_dbs_dma_addr,
252 GFP_KERNEL);
253 if (!dev->dbbuf_dbs)
254 return -ENOMEM;
255 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
256 &dev->dbbuf_eis_dma_addr,
257 GFP_KERNEL);
258 if (!dev->dbbuf_eis) {
259 dma_free_coherent(dev->dev, mem_size,
260 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
261 dev->dbbuf_dbs = NULL;
262 return -ENOMEM;
263 }
264
265 return 0;
266}
267
268static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
269{
2a5bcfdd 270 unsigned int mem_size = nvme_dbbuf_size(dev);
f9f38e33
HK		 271
272 if (dev->dbbuf_dbs) {
273 dma_free_coherent(dev->dev, mem_size,
274 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
275 dev->dbbuf_dbs = NULL;
276 }
277 if (dev->dbbuf_eis) {
278 dma_free_coherent(dev->dev, mem_size,
279 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
280 dev->dbbuf_eis = NULL;
281 }
282}
283
284static void nvme_dbbuf_init(struct nvme_dev *dev,
285 struct nvme_queue *nvmeq, int qid)
286{
287 if (!dev->dbbuf_dbs || !qid)
288 return;
289
290 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
291 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
292 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
293 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
294}
295
0f0d2c87
MI		 296static void nvme_dbbuf_free(struct nvme_queue *nvmeq)
297{
298 if (!nvmeq->qid)
299 return;
300
301 nvmeq->dbbuf_sq_db = NULL;
302 nvmeq->dbbuf_cq_db = NULL;
303 nvmeq->dbbuf_sq_ei = NULL;
304 nvmeq->dbbuf_cq_ei = NULL;
305}
306
f9f38e33
HK		 307static void nvme_dbbuf_set(struct nvme_dev *dev)
308{
f66e2804 309 struct nvme_command c = { };
0f0d2c87 310 unsigned int i;
f9f38e33
HK		 311
312 if (!dev->dbbuf_dbs)
313 return;
314
f9f38e33
HK		 315 c.dbbuf.opcode = nvme_admin_dbbuf;
316 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
317 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
318
319 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
9bdcfb10 320 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
f9f38e33
HK		 321 /* Free memory and continue on */
322 nvme_dbbuf_dma_free(dev);
0f0d2c87
MI		 323
324 for (i = 1; i <= dev->online_queues; i++)
325 nvme_dbbuf_free(&dev->queues[i]);
f9f38e33
HK		 326 }
327}
328
329static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
330{
331 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
332}
333
334/* Update dbbuf and return true if an MMIO is required */
335static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
336 volatile u32 *dbbuf_ei)
337{
338 if (dbbuf_db) {
339 u16 old_value;
340
341 /*
342 * Ensure that the queue is written before updating
343 * the doorbell in memory
344 */
345 wmb();
346
347 old_value = *dbbuf_db;
348 *dbbuf_db = value;
349
f1ed3df2
MW		 350 /*
351 * Ensure that the doorbell is updated before reading the event
352 * index from memory. The controller needs to provide similar
353 * ordering to ensure the envent index is updated before reading
354 * the doorbell.
355 */
356 mb();
357
f9f38e33
HK		 358 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value))
359 return false;
360 }
361
362 return true;
b60503ba
MW		 363}
364
ac3dd5bd
JA		 365/*
366 * Will slightly overestimate the number of pages needed. This is OK
367 * as it only leads to a small amount of wasted memory for the lifetime of
368 * the I/O.
369 */
b13c6393 370static int nvme_pci_npages_prp(void)
ac3dd5bd 371{
b13c6393 372 unsigned nprps = DIV_ROUND_UP(NVME_MAX_KB_SZ + NVME_CTRL_PAGE_SIZE,
6c3c05b0 373 NVME_CTRL_PAGE_SIZE);
ac3dd5bd
JA		 374 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
375}
376
a7a7cbe3
CK		 377/*
378 * Calculates the number of pages needed for the SGL segments. For example a 4k
379 * page can accommodate 256 SGL descriptors.
380 */
b13c6393 381static int nvme_pci_npages_sgl(void)
ac3dd5bd 382{
b13c6393
CK		 383 return DIV_ROUND_UP(NVME_MAX_SEGS * sizeof(struct nvme_sgl_desc),
384 PAGE_SIZE);
f4800d6d 385}
ac3dd5bd 386
b13c6393 387static size_t nvme_pci_iod_alloc_size(void)
f4800d6d 388{
b13c6393 389 size_t npages = max(nvme_pci_npages_prp(), nvme_pci_npages_sgl());
a7a7cbe3 390
b13c6393
CK		 391 return sizeof(__le64 *) * npages +
392 sizeof(struct scatterlist) * NVME_MAX_SEGS;
f4800d6d 393}
ac3dd5bd 394
a4aea562
MB		 395static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
396 unsigned int hctx_idx)
e85248e5 397{
a4aea562 398 struct nvme_dev *dev = data;
147b27e4 399 struct nvme_queue *nvmeq = &dev->queues[0];
a4aea562 400
42483228
KB		 401 WARN_ON(hctx_idx != 0);
402 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
42483228 403
a4aea562
MB		 404 hctx->driver_data = nvmeq;
405 return 0;
e85248e5
MW		 406}
407
a4aea562
MB		 408static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
409 unsigned int hctx_idx)
b60503ba 410{
a4aea562 411 struct nvme_dev *dev = data;
147b27e4 412 struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
a4aea562 413
42483228 414 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
a4aea562
MB		 415 hctx->driver_data = nvmeq;
416 return 0;
b60503ba
MW		 417}
418
d6296d39
CH		 419static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req,
420 unsigned int hctx_idx, unsigned int numa_node)
b60503ba 421{
d6296d39 422 struct nvme_dev *dev = set->driver_data;
f4800d6d 423 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
0350815a 424 int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0;
147b27e4 425 struct nvme_queue *nvmeq = &dev->queues[queue_idx];
a4aea562
MB		 426
427 BUG_ON(!nvmeq);
f4800d6d 428 iod->nvmeq = nvmeq;
59e29ce6
SG		 429
430 nvme_req(req)->ctrl = &dev->ctrl;
f4b9e6c9 431 nvme_req(req)->cmd = &iod->cmd;
a4aea562
MB		 432 return 0;
433}
434
3b6592f7
JA		 435static int queue_irq_offset(struct nvme_dev *dev)
436{
437 /* if we have more than 1 vec, admin queue offsets us by 1 */
438 if (dev->num_vecs > 1)
439 return 1;
440
441 return 0;
442}
443
dca51e78
CH		 444static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
445{
446 struct nvme_dev *dev = set->driver_data;
3b6592f7
JA		 447 int i, qoff, offset;
448
449 offset = queue_irq_offset(dev);
450 for (i = 0, qoff = 0; i < set->nr_maps; i++) {
451 struct blk_mq_queue_map *map = &set->map[i];
452
453 map->nr_queues = dev->io_queues[i];
454 if (!map->nr_queues) {
e20ba6e1 455 BUG_ON(i == HCTX_TYPE_DEFAULT);
7e849dd9 456 continue;
3b6592f7
JA		 457 }
458
4b04cc6a
JA		 459 /*
460 * The poll queue(s) doesn't have an IRQ (and hence IRQ
461 * affinity), so use the regular blk-mq cpu mapping
462 */
3b6592f7 463 map->queue_offset = qoff;
cb9e0e50 464 if (i != HCTX_TYPE_POLL && offset)
4b04cc6a
JA		 465 blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset);
466 else
467 blk_mq_map_queues(map);
3b6592f7
JA		 468 qoff += map->nr_queues;
469 offset += map->nr_queues;
470 }
471
472 return 0;
dca51e78
CH		 473}
474
38210800
KB		 475/*
476 * Write sq tail if we are asked to, or if the next command would wrap.
477 */
478static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq)
04f3eafd 479{
38210800
KB		 480 if (!write_sq) {
481 u16 next_tail = nvmeq->sq_tail + 1;
482
483 if (next_tail == nvmeq->q_depth)
484 next_tail = 0;
485 if (next_tail != nvmeq->last_sq_tail)
486 return;
487 }
488
04f3eafd
JA		 489 if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail,
490 nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei))
491 writel(nvmeq->sq_tail, nvmeq->q_db);
38210800 492 nvmeq->last_sq_tail = nvmeq->sq_tail;
04f3eafd
JA		 493}
494
b60503ba 495/**
90ea5ca4 496 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
b60503ba
MW		 497 * @nvmeq: The queue to use
498 * @cmd: The command to send
04f3eafd 499 * @write_sq: whether to write to the SQ doorbell
b60503ba 500 */
04f3eafd
JA		 501static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd,
502 bool write_sq)
b60503ba 503{
90ea5ca4 504 spin_lock(&nvmeq->sq_lock);
c1e0cc7e
BH		 505 memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes),
506 cmd, sizeof(*cmd));
90ea5ca4
CH		 507 if (++nvmeq->sq_tail == nvmeq->q_depth)
508 nvmeq->sq_tail = 0;
38210800 509 nvme_write_sq_db(nvmeq, write_sq);
04f3eafd
JA		 510 spin_unlock(&nvmeq->sq_lock);
511}
512
513static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx)
514{
515 struct nvme_queue *nvmeq = hctx->driver_data;
516
517 spin_lock(&nvmeq->sq_lock);
38210800
KB		 518 if (nvmeq->sq_tail != nvmeq->last_sq_tail)
519 nvme_write_sq_db(nvmeq, true);
90ea5ca4 520 spin_unlock(&nvmeq->sq_lock);
b60503ba
MW		 521}
522
a7a7cbe3 523static void **nvme_pci_iod_list(struct request *req)
b60503ba 524{
f4800d6d 525 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3 526 return (void **)(iod->sg + blk_rq_nr_phys_segments(req));
b60503ba
MW		 527}
528
955b1b5a
MI		 529static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req)
530{
531 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
20469a37 532 int nseg = blk_rq_nr_phys_segments(req);
955b1b5a
MI		 533 unsigned int avg_seg_size;
534
20469a37 535 avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
955b1b5a 536
253a0b76 537 if (!nvme_ctrl_sgl_supported(&dev->ctrl))
955b1b5a
MI		 538 return false;
539 if (!iod->nvmeq->qid)
540 return false;
541 if (!sgl_threshold || avg_seg_size < sgl_threshold)
542 return false;
543 return true;
544}
545
9275c206 546static void nvme_free_prps(struct nvme_dev *dev, struct request *req)
b60503ba 547{
6c3c05b0 548 const int last_prp = NVME_CTRL_PAGE_SIZE / sizeof(__le64) - 1;
9275c206
CH		 549 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
550 dma_addr_t dma_addr = iod->first_dma;
eca18b23 551 int i;
eca18b23 552
9275c206
CH		 553 for (i = 0; i < iod->npages; i++) {
554 __le64 *prp_list = nvme_pci_iod_list(req)[i];
555 dma_addr_t next_dma_addr = le64_to_cpu(prp_list[last_prp]);
556
557 dma_pool_free(dev->prp_page_pool, prp_list, dma_addr);
558 dma_addr = next_dma_addr;
7fe07d14 559 }
9275c206 560}
dff824b2 561
9275c206
CH		 562static void nvme_free_sgls(struct nvme_dev *dev, struct request *req)
563{
564 const int last_sg = SGES_PER_PAGE - 1;
565 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
566 dma_addr_t dma_addr = iod->first_dma;
567 int i;
dff824b2 568
9275c206
CH		 569 for (i = 0; i < iod->npages; i++) {
570 struct nvme_sgl_desc *sg_list = nvme_pci_iod_list(req)[i];
571 dma_addr_t next_dma_addr = le64_to_cpu((sg_list[last_sg]).addr);
dff824b2 572
9275c206
CH		 573 dma_pool_free(dev->prp_page_pool, sg_list, dma_addr);
574 dma_addr = next_dma_addr;
575 }
9275c206 576}
a7a7cbe3 577
9275c206
CH		 578static void nvme_unmap_sg(struct nvme_dev *dev, struct request *req)
579{
580 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3 581
9275c206
CH		 582 if (is_pci_p2pdma_page(sg_page(iod->sg)))
583 pci_p2pdma_unmap_sg(dev->dev, iod->sg, iod->nents,
584 rq_dma_dir(req));
585 else
586 dma_unmap_sg(dev->dev, iod->sg, iod->nents, rq_dma_dir(req));
587}
a7a7cbe3 588
9275c206
CH		 589static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
590{
591 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3 592
9275c206
CH		 593 if (iod->dma_len) {
594 dma_unmap_page(dev->dev, iod->first_dma, iod->dma_len,
595 rq_dma_dir(req));
596 return;
eca18b23 597 }
ac3dd5bd 598
9275c206
CH		 599 WARN_ON_ONCE(!iod->nents);
600
601 nvme_unmap_sg(dev, req);
602 if (iod->npages == 0)
603 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0],
604 iod->first_dma);
605 else if (iod->use_sgl)
606 nvme_free_sgls(dev, req);
607 else
608 nvme_free_prps(dev, req);
d43f1ccf 609 mempool_free(iod->sg, dev->iod_mempool);
b4ff9c8d
KB		 610}
611
d0877473
KB		 612static void nvme_print_sgl(struct scatterlist *sgl, int nents)
613{
614 int i;
615 struct scatterlist *sg;
616
617 for_each_sg(sgl, sg, nents, i) {
618 dma_addr_t phys = sg_phys(sg);
619 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
620 "dma_address:%pad dma_length:%d\n",
621 i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
622 sg_dma_len(sg));
623 }
624}
625
a7a7cbe3
CK		 626static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
627 struct request *req, struct nvme_rw_command *cmnd)
ff22b54f 628{
f4800d6d 629 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
99802a7a 630 struct dma_pool *pool;
b131c61d 631 int length = blk_rq_payload_bytes(req);
eca18b23 632 struct scatterlist *sg = iod->sg;
ff22b54f
MW		 633 int dma_len = sg_dma_len(sg);
634 u64 dma_addr = sg_dma_address(sg);
6c3c05b0 635 int offset = dma_addr & (NVME_CTRL_PAGE_SIZE - 1);
e025344c 636 __le64 *prp_list;
a7a7cbe3 637 void **list = nvme_pci_iod_list(req);
e025344c 638 dma_addr_t prp_dma;
eca18b23 639 int nprps, i;
ff22b54f 640
6c3c05b0 641 length -= (NVME_CTRL_PAGE_SIZE - offset);
5228b328
JS		 642 if (length <= 0) {
643 iod->first_dma = 0;
a7a7cbe3 644 goto done;
5228b328 645 }
ff22b54f 646
6c3c05b0 647 dma_len -= (NVME_CTRL_PAGE_SIZE - offset);
ff22b54f 648 if (dma_len) {
6c3c05b0 649 dma_addr += (NVME_CTRL_PAGE_SIZE - offset);
ff22b54f
MW		 650 } else {
651 sg = sg_next(sg);
652 dma_addr = sg_dma_address(sg);
653 dma_len = sg_dma_len(sg);
654 }
655
6c3c05b0 656 if (length <= NVME_CTRL_PAGE_SIZE) {
edd10d33 657 iod->first_dma = dma_addr;
a7a7cbe3 658 goto done;
e025344c
SMM		 659 }
660
6c3c05b0 661 nprps = DIV_ROUND_UP(length, NVME_CTRL_PAGE_SIZE);
99802a7a
MW		 662 if (nprps <= (256 / 8)) {
663 pool = dev->prp_small_pool;
eca18b23 664 iod->npages = 0;
99802a7a
MW		 665 } else {
666 pool = dev->prp_page_pool;
eca18b23 667 iod->npages = 1;
99802a7a
MW		 668 }
669
69d2b571 670 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
b77954cb 671 if (!prp_list) {
edd10d33 672 iod->first_dma = dma_addr;
eca18b23 673 iod->npages = -1;
86eea289 674 return BLK_STS_RESOURCE;
b77954cb 675 }
eca18b23
MW		 676 list[0] = prp_list;
677 iod->first_dma = prp_dma;
e025344c
SMM		 678 i = 0;
679 for (;;) {
6c3c05b0 680 if (i == NVME_CTRL_PAGE_SIZE >> 3) {
e025344c 681 __le64 *old_prp_list = prp_list;
69d2b571 682 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
eca18b23 683 if (!prp_list)
fa073216 684 goto free_prps;
eca18b23 685 list[iod->npages++] = prp_list;
7523d834
MW		 686 prp_list[0] = old_prp_list[i - 1];
687 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
688 i = 1;
e025344c
SMM		 689 }
690 prp_list[i++] = cpu_to_le64(dma_addr);
6c3c05b0
CK		 691 dma_len -= NVME_CTRL_PAGE_SIZE;
692 dma_addr += NVME_CTRL_PAGE_SIZE;
693 length -= NVME_CTRL_PAGE_SIZE;
e025344c
SMM		 694 if (length <= 0)
695 break;
696 if (dma_len > 0)
697 continue;
86eea289
KB		 698 if (unlikely(dma_len < 0))
699 goto bad_sgl;
e025344c
SMM		 700 sg = sg_next(sg);
701 dma_addr = sg_dma_address(sg);
702 dma_len = sg_dma_len(sg);
ff22b54f 703 }
a7a7cbe3
CK		 704done:
705 cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
706 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
86eea289 707 return BLK_STS_OK;
fa073216
CH		 708free_prps:
709 nvme_free_prps(dev, req);
710 return BLK_STS_RESOURCE;
711bad_sgl:
d0877473
KB		 712 WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents),
713 "Invalid SGL for payload:%d nents:%d\n",
714 blk_rq_payload_bytes(req), iod->nents);
86eea289 715 return BLK_STS_IOERR;
ff22b54f
MW		 716}
717
a7a7cbe3
CK		 718static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
719 struct scatterlist *sg)
720{
721 sge->addr = cpu_to_le64(sg_dma_address(sg));
722 sge->length = cpu_to_le32(sg_dma_len(sg));
723 sge->type = NVME_SGL_FMT_DATA_DESC << 4;
724}
725
726static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
727 dma_addr_t dma_addr, int entries)
728{
729 sge->addr = cpu_to_le64(dma_addr);
730 if (entries < SGES_PER_PAGE) {
731 sge->length = cpu_to_le32(entries * sizeof(*sge));
732 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
733 } else {
734 sge->length = cpu_to_le32(PAGE_SIZE);
735 sge->type = NVME_SGL_FMT_SEG_DESC << 4;
736 }
737}
738
739static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
b0f2853b 740 struct request *req, struct nvme_rw_command *cmd, int entries)
a7a7cbe3
CK		 741{
742 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3
CK		 743 struct dma_pool *pool;
744 struct nvme_sgl_desc *sg_list;
745 struct scatterlist *sg = iod->sg;
a7a7cbe3 746 dma_addr_t sgl_dma;
b0f2853b 747 int i = 0;
a7a7cbe3 748
a7a7cbe3
CK		 749 /* setting the transfer type as SGL */
750 cmd->flags = NVME_CMD_SGL_METABUF;
751
b0f2853b 752 if (entries == 1) {
a7a7cbe3
CK		 753 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
754 return BLK_STS_OK;
755 }
756
757 if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
758 pool = dev->prp_small_pool;
759 iod->npages = 0;
760 } else {
761 pool = dev->prp_page_pool;
762 iod->npages = 1;
763 }
764
765 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
766 if (!sg_list) {
767 iod->npages = -1;
768 return BLK_STS_RESOURCE;
769 }
770
771 nvme_pci_iod_list(req)[0] = sg_list;
772 iod->first_dma = sgl_dma;
773
774 nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
775
776 do {
777 if (i == SGES_PER_PAGE) {
778 struct nvme_sgl_desc *old_sg_desc = sg_list;
779 struct nvme_sgl_desc *link = &old_sg_desc[i - 1];
780
781 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
782 if (!sg_list)
fa073216 783 goto free_sgls;
a7a7cbe3
CK		 784
785 i = 0;
786 nvme_pci_iod_list(req)[iod->npages++] = sg_list;
787 sg_list[i++] = *link;
788 nvme_pci_sgl_set_seg(link, sgl_dma, entries);
789 }
790
791 nvme_pci_sgl_set_data(&sg_list[i++], sg);
a7a7cbe3 792 sg = sg_next(sg);
b0f2853b 793 } while (--entries > 0);
a7a7cbe3 794
a7a7cbe3 795 return BLK_STS_OK;
fa073216
CH		 796free_sgls:
797 nvme_free_sgls(dev, req);
798 return BLK_STS_RESOURCE;
a7a7cbe3
CK		 799}
800
dff824b2
CH		 801static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev,
802 struct request *req, struct nvme_rw_command *cmnd,
803 struct bio_vec *bv)
804{
805 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
6c3c05b0
CK		 806 unsigned int offset = bv->bv_offset & (NVME_CTRL_PAGE_SIZE - 1);
807 unsigned int first_prp_len = NVME_CTRL_PAGE_SIZE - offset;
dff824b2
CH		 808
809 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
810 if (dma_mapping_error(dev->dev, iod->first_dma))
811 return BLK_STS_RESOURCE;
812 iod->dma_len = bv->bv_len;
813
814 cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma);
815 if (bv->bv_len > first_prp_len)
816 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len);
359c1f88 817 return BLK_STS_OK;
dff824b2
CH		 818}
819
29791057
CH		 820static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev,
821 struct request *req, struct nvme_rw_command *cmnd,
822 struct bio_vec *bv)
823{
824 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
825
826 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
827 if (dma_mapping_error(dev->dev, iod->first_dma))
828 return BLK_STS_RESOURCE;
829 iod->dma_len = bv->bv_len;
830
049bf372 831 cmnd->flags = NVME_CMD_SGL_METABUF;
29791057
CH		 832 cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma);
833 cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len);
834 cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4;
359c1f88 835 return BLK_STS_OK;
29791057
CH		 836}
837
fc17b653 838static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
b131c61d 839 struct nvme_command *cmnd)
d29ec824 840{
f4800d6d 841 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
70479b71 842 blk_status_t ret = BLK_STS_RESOURCE;
b0f2853b 843 int nr_mapped;
d29ec824 844
dff824b2
CH		 845 if (blk_rq_nr_phys_segments(req) == 1) {
846 struct bio_vec bv = req_bvec(req);
847
848 if (!is_pci_p2pdma_page(bv.bv_page)) {
6c3c05b0 849 if (bv.bv_offset + bv.bv_len <= NVME_CTRL_PAGE_SIZE * 2)
dff824b2
CH		 850 return nvme_setup_prp_simple(dev, req,
851 &cmnd->rw, &bv);
29791057 852
e51183be 853 if (iod->nvmeq->qid && sgl_threshold &&
253a0b76 854 nvme_ctrl_sgl_supported(&dev->ctrl))
29791057
CH		 855 return nvme_setup_sgl_simple(dev, req,
856 &cmnd->rw, &bv);
dff824b2
CH		 857 }
858 }
859
860 iod->dma_len = 0;
d43f1ccf
CH		 861 iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC);
862 if (!iod->sg)
863 return BLK_STS_RESOURCE;
f9d03f96 864 sg_init_table(iod->sg, blk_rq_nr_phys_segments(req));
70479b71 865 iod->nents = blk_rq_map_sg(req->q, req, iod->sg);
ba1ca37e 866 if (!iod->nents)
fa073216 867 goto out_free_sg;
d29ec824 868
e0596ab2 869 if (is_pci_p2pdma_page(sg_page(iod->sg)))
2b9f4bb2
LG		 870 nr_mapped = pci_p2pdma_map_sg_attrs(dev->dev, iod->sg,
871 iod->nents, rq_dma_dir(req), DMA_ATTR_NO_WARN);
e0596ab2
LG		 872 else
873 nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents,
70479b71 874 rq_dma_dir(req), DMA_ATTR_NO_WARN);
b0f2853b 875 if (!nr_mapped)
fa073216 876 goto out_free_sg;
d29ec824 877
70479b71 878 iod->use_sgl = nvme_pci_use_sgls(dev, req);
955b1b5a 879 if (iod->use_sgl)
b0f2853b 880 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped);
a7a7cbe3
CK		 881 else
882 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
86eea289 883 if (ret != BLK_STS_OK)
fa073216
CH		 884 goto out_unmap_sg;
885 return BLK_STS_OK;
886
887out_unmap_sg:
888 nvme_unmap_sg(dev, req);
889out_free_sg:
890 mempool_free(iod->sg, dev->iod_mempool);
4aedb705
CH		 891 return ret;
892}
3045c0d0 893
4aedb705
CH		 894static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req,
895 struct nvme_command *cmnd)
896{
897 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
00df5cb4 898
4aedb705
CH		 899 iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req),
900 rq_dma_dir(req), 0);
901 if (dma_mapping_error(dev->dev, iod->meta_dma))
902 return BLK_STS_IOERR;
903 cmnd->rw.metadata = cpu_to_le64(iod->meta_dma);
359c1f88 904 return BLK_STS_OK;
00df5cb4
MW		 905}
906
d29ec824
CH		 907/*
908 * NOTE: ns is NULL when called on the admin queue.
909 */
fc17b653 910static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
a4aea562 911 const struct blk_mq_queue_data *bd)
edd10d33 912{
a4aea562
MB		 913 struct nvme_ns *ns = hctx->queue->queuedata;
914 struct nvme_queue *nvmeq = hctx->driver_data;
d29ec824 915 struct nvme_dev *dev = nvmeq->dev;
a4aea562 916 struct request *req = bd->rq;
9b048119 917 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
af7fae85 918 struct nvme_command *cmnd = &iod->cmd;
ebe6d874 919 blk_status_t ret;
e1e5e564 920
9b048119
CH		 921 iod->aborted = 0;
922 iod->npages = -1;
923 iod->nents = 0;
924
d1f06f4a
JA		 925 /*
926 * We should not need to do this, but we're still using this to
927 * ensure we can drain requests on a dying queue.
928 */
4e224106 929 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
d1f06f4a
JA		 930 return BLK_STS_IOERR;
931
d4060d2b
TC		 932 if (!nvme_check_ready(&dev->ctrl, req, true))
933 return nvme_fail_nonready_command(&dev->ctrl, req);
934
f4b9e6c9 935 ret = nvme_setup_cmd(ns, req);
fc17b653 936 if (ret)
f4800d6d 937 return ret;
a4aea562 938
fc17b653 939 if (blk_rq_nr_phys_segments(req)) {
af7fae85 940 ret = nvme_map_data(dev, req, cmnd);
fc17b653 941 if (ret)
9b048119 942 goto out_free_cmd;
fc17b653 943 }
a4aea562 944
4aedb705 945 if (blk_integrity_rq(req)) {
af7fae85 946 ret = nvme_map_metadata(dev, req, cmnd);
4aedb705
CH		 947 if (ret)
948 goto out_unmap_data;
949 }
950
aae239e1 951 blk_mq_start_request(req);
af7fae85 952 nvme_submit_cmd(nvmeq, cmnd, bd->last);
fc17b653 953 return BLK_STS_OK;
4aedb705
CH		 954out_unmap_data:
955 nvme_unmap_data(dev, req);
f9d03f96
CH		 956out_free_cmd:
957 nvme_cleanup_cmd(req);
ba1ca37e 958 return ret;
b60503ba 959}
e1e5e564 960
77f02a7a 961static void nvme_pci_complete_rq(struct request *req)
eee417b0 962{
f4800d6d 963 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
4aedb705 964 struct nvme_dev *dev = iod->nvmeq->dev;
a4aea562 965
4aedb705
CH		 966 if (blk_integrity_rq(req))
967 dma_unmap_page(dev->dev, iod->meta_dma,
968 rq_integrity_vec(req)->bv_len, rq_data_dir(req));
b15c592d 969 if (blk_rq_nr_phys_segments(req))
4aedb705 970 nvme_unmap_data(dev, req);
77f02a7a 971 nvme_complete_rq(req);
b60503ba
MW		 972}
973
d783e0bd 974/* We read the CQE phase first to check if the rest of the entry is valid */
750dde44 975static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq)
d783e0bd 976{
74943d45
KB		 977 struct nvme_completion *hcqe = &nvmeq->cqes[nvmeq->cq_head];
978
979 return (le16_to_cpu(READ_ONCE(hcqe->status)) & 1) == nvmeq->cq_phase;
d783e0bd
MR		 980}
981
eb281c82 982static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
b60503ba 983{
eb281c82 984 u16 head = nvmeq->cq_head;
adf68f21 985
397c699f
KB		 986 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
987 nvmeq->dbbuf_cq_ei))
988 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
eb281c82 989}
aae239e1 990
cfa27356
CH		 991static inline struct blk_mq_tags *nvme_queue_tagset(struct nvme_queue *nvmeq)
992{
993 if (!nvmeq->qid)
994 return nvmeq->dev->admin_tagset.tags[0];
995 return nvmeq->dev->tagset.tags[nvmeq->qid - 1];
996}
997
5cb525c8 998static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx)
83a12fb7 999{
74943d45 1000 struct nvme_completion *cqe = &nvmeq->cqes[idx];
62df8016 1001 __u16 command_id = READ_ONCE(cqe->command_id);
83a12fb7 1002 struct request *req;
adf68f21 1003
83a12fb7
SG		 1004 /*
1005 * AEN requests are special as they don't time out and can
1006 * survive any kind of queue freeze and often don't respond to
1007 * aborts. We don't even bother to allocate a struct request
1008 * for them but rather special case them here.
1009 */
62df8016 1010 if (unlikely(nvme_is_aen_req(nvmeq->qid, command_id))) {
83a12fb7
SG		 1011 nvme_complete_async_event(&nvmeq->dev->ctrl,
1012 cqe->status, &cqe->result);
a0fa9647 1013 return;
83a12fb7 1014 }
b60503ba 1015
e7006de6 1016 req = nvme_find_rq(nvme_queue_tagset(nvmeq), command_id);
50b7c243
XT		 1017 if (unlikely(!req)) {
1018 dev_warn(nvmeq->dev->ctrl.device,
1019 "invalid id %d completed on queue %d\n",
62df8016 1020 command_id, le16_to_cpu(cqe->sq_id));
50b7c243
XT		 1021 return;
1022 }
1023
604c01d5 1024 trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail);
2eb81a33 1025 if (!nvme_try_complete_req(req, cqe->status, cqe->result))
ff029451 1026 nvme_pci_complete_rq(req);
83a12fb7 1027}
b60503ba 1028
5cb525c8
JA		 1029static inline void nvme_update_cq_head(struct nvme_queue *nvmeq)
1030{
a0aac973 1031 u32 tmp = nvmeq->cq_head + 1;
a8de6639
AD		 1032
1033 if (tmp == nvmeq->q_depth) {
5cb525c8 1034 nvmeq->cq_head = 0;
e2a366a4 1035 nvmeq->cq_phase ^= 1;
a8de6639
AD		 1036 } else {
1037 nvmeq->cq_head = tmp;
b60503ba 1038 }
a0fa9647
JA		 1039}
1040
324b494c 1041static inline int nvme_process_cq(struct nvme_queue *nvmeq)
a0fa9647 1042{
1052b8ac 1043 int found = 0;
b60503ba 1044
1052b8ac 1045 while (nvme_cqe_pending(nvmeq)) {
bf392a5d 1046 found++;
b69e2ef2
KB		 1047 /*
1048 * load-load control dependency between phase and the rest of
1049 * the cqe requires a full read memory barrier
1050 */
1051 dma_rmb();
324b494c 1052 nvme_handle_cqe(nvmeq, nvmeq->cq_head);
5cb525c8 1053 nvme_update_cq_head(nvmeq);
920d13a8 1054 }
eb281c82 1055
324b494c 1056 if (found)
920d13a8 1057 nvme_ring_cq_doorbell(nvmeq);
5cb525c8 1058 return found;
b60503ba
MW		 1059}
1060
1061static irqreturn_t nvme_irq(int irq, void *data)
58ffacb5 1062{
58ffacb5 1063 struct nvme_queue *nvmeq = data;
5cb525c8 1064
324b494c 1065 if (nvme_process_cq(nvmeq))
05fae499
CK		 1066 return IRQ_HANDLED;
1067 return IRQ_NONE;
58ffacb5
MW		 1068}
1069
1070static irqreturn_t nvme_irq_check(int irq, void *data)
1071{
1072 struct nvme_queue *nvmeq = data;
4e523547 1073
750dde44 1074 if (nvme_cqe_pending(nvmeq))
d783e0bd
MR		 1075 return IRQ_WAKE_THREAD;
1076 return IRQ_NONE;
58ffacb5
MW		 1077}
1078
0b2a8a9f 1079/*
fa059b85 1080 * Poll for completions for any interrupt driven queue
0b2a8a9f
CH		 1081 * Can be called from any context.
1082 */
fa059b85 1083static void nvme_poll_irqdisable(struct nvme_queue *nvmeq)
a0fa9647 1084{
3a7afd8e 1085 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
a0fa9647 1086
fa059b85 1087 WARN_ON_ONCE(test_bit(NVMEQ_POLLED, &nvmeq->flags));
442e19b7 1088
fa059b85
KB		 1089 disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1090 nvme_process_cq(nvmeq);
1091 enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
a0fa9647
JA		 1092}
1093
9743139c 1094static int nvme_poll(struct blk_mq_hw_ctx *hctx)
dabcefab
JA		 1095{
1096 struct nvme_queue *nvmeq = hctx->driver_data;
dabcefab
JA		 1097 bool found;
1098
1099 if (!nvme_cqe_pending(nvmeq))
1100 return 0;
1101
3a7afd8e 1102 spin_lock(&nvmeq->cq_poll_lock);
324b494c 1103 found = nvme_process_cq(nvmeq);
3a7afd8e 1104 spin_unlock(&nvmeq->cq_poll_lock);
dabcefab 1105
dabcefab
JA		 1106 return found;
1107}
1108
ad22c355 1109static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
b60503ba 1110{
f866fc42 1111 struct nvme_dev *dev = to_nvme_dev(ctrl);
147b27e4 1112 struct nvme_queue *nvmeq = &dev->queues[0];
f66e2804 1113 struct nvme_command c = { };
b60503ba 1114
a4aea562 1115 c.common.opcode = nvme_admin_async_event;
ad22c355 1116 c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
04f3eafd 1117 nvme_submit_cmd(nvmeq, &c, true);
f705f837
CH		 1118}
1119
b60503ba 1120static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
f705f837 1121{
f66e2804 1122 struct nvme_command c = { };
b60503ba 1123
b60503ba
MW		 1124 c.delete_queue.opcode = opcode;
1125 c.delete_queue.qid = cpu_to_le16(id);
1126
1c63dc66 1127 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1128}
1129
b60503ba 1130static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
a8e3e0bb 1131 struct nvme_queue *nvmeq, s16 vector)
b60503ba 1132{
f66e2804 1133 struct nvme_command c = { };
4b04cc6a
JA		 1134 int flags = NVME_QUEUE_PHYS_CONTIG;
1135
7c349dde 1136 if (!test_bit(NVMEQ_POLLED, &nvmeq->flags))
4b04cc6a 1137 flags |= NVME_CQ_IRQ_ENABLED;
b60503ba 1138
d29ec824 1139 /*
16772ae6 1140 * Note: we (ab)use the fact that the prp fields survive if no data
d29ec824
CH		 1141 * is attached to the request.
1142 */
b60503ba
MW		 1143 c.create_cq.opcode = nvme_admin_create_cq;
1144 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1145 c.create_cq.cqid = cpu_to_le16(qid);
1146 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1147 c.create_cq.cq_flags = cpu_to_le16(flags);
7c349dde 1148 c.create_cq.irq_vector = cpu_to_le16(vector);
b60503ba 1149
1c63dc66 1150 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1151}
1152
1153static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1154 struct nvme_queue *nvmeq)
1155{
9abd68ef 1156 struct nvme_ctrl *ctrl = &dev->ctrl;
f66e2804 1157 struct nvme_command c = { };
81c1cd98 1158 int flags = NVME_QUEUE_PHYS_CONTIG;
b60503ba 1159
9abd68ef
JA		 1160 /*
1161 * Some drives have a bug that auto-enables WRRU if MEDIUM isn't
1162 * set. Since URGENT priority is zeroes, it makes all queues
1163 * URGENT.
1164 */
1165 if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ)
1166 flags |= NVME_SQ_PRIO_MEDIUM;
1167
d29ec824 1168 /*
16772ae6 1169 * Note: we (ab)use the fact that the prp fields survive if no data
d29ec824
CH		 1170 * is attached to the request.
1171 */
b60503ba
MW		 1172 c.create_sq.opcode = nvme_admin_create_sq;
1173 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1174 c.create_sq.sqid = cpu_to_le16(qid);
1175 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1176 c.create_sq.sq_flags = cpu_to_le16(flags);
1177 c.create_sq.cqid = cpu_to_le16(qid);
1178
1c63dc66 1179 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1180}
1181
1182static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1183{
1184 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1185}
1186
1187static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1188{
1189 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1190}
1191
2a842aca 1192static void abort_endio(struct request *req, blk_status_t error)
bc5fc7e4 1193{
f4800d6d
CH		 1194 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1195 struct nvme_queue *nvmeq = iod->nvmeq;
e44ac588 1196
27fa9bc5
CH		 1197 dev_warn(nvmeq->dev->ctrl.device,
1198 "Abort status: 0x%x", nvme_req(req)->status);
e7a2a87d 1199 atomic_inc(&nvmeq->dev->ctrl.abort_limit);
e7a2a87d 1200 blk_mq_free_request(req);
bc5fc7e4
MW		 1201}
1202
b2a0eb1a
KB		 1203static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1204{
b2a0eb1a
KB		 1205 /* If true, indicates loss of adapter communication, possibly by a
1206 * NVMe Subsystem reset.
1207 */
1208 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1209
ad70062c
JW		 1210 /* If there is a reset/reinit ongoing, we shouldn't reset again. */
1211 switch (dev->ctrl.state) {
1212 case NVME_CTRL_RESETTING:
ad6a0a52 1213 case NVME_CTRL_CONNECTING:
b2a0eb1a 1214 return false;
ad70062c
JW		 1215 default:
1216 break;
1217 }
b2a0eb1a
KB		 1218
1219 /* We shouldn't reset unless the controller is on fatal error state
1220 * _or_ if we lost the communication with it.
1221 */
1222 if (!(csts & NVME_CSTS_CFS) && !nssro)
1223 return false;
1224
b2a0eb1a
KB		 1225 return true;
1226}
1227
1228static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1229{
1230 /* Read a config register to help see what died. */
1231 u16 pci_status;
1232 int result;
1233
1234 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1235 &pci_status);
1236 if (result == PCIBIOS_SUCCESSFUL)
1237 dev_warn(dev->ctrl.device,
1238 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1239 csts, pci_status);
1240 else
1241 dev_warn(dev->ctrl.device,
1242 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1243 csts, result);
1244}
1245
31c7c7d2 1246static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
c30341dc 1247{
f4800d6d
CH		 1248 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1249 struct nvme_queue *nvmeq = iod->nvmeq;
c30341dc 1250 struct nvme_dev *dev = nvmeq->dev;
a4aea562 1251 struct request *abort_req;
f66e2804 1252 struct nvme_command cmd = { };
b2a0eb1a
KB		 1253 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1254
651438bb
WX		 1255 /* If PCI error recovery process is happening, we cannot reset or
1256 * the recovery mechanism will surely fail.
1257 */
1258 mb();
1259 if (pci_channel_offline(to_pci_dev(dev->dev)))
1260 return BLK_EH_RESET_TIMER;
1261
b2a0eb1a
KB		 1262 /*
1263 * Reset immediately if the controller is failed
1264 */
1265 if (nvme_should_reset(dev, csts)) {
1266 nvme_warn_reset(dev, csts);
1267 nvme_dev_disable(dev, false);
d86c4d8e 1268 nvme_reset_ctrl(&dev->ctrl);
db8c48e4 1269 return BLK_EH_DONE;
b2a0eb1a 1270 }
c30341dc 1271
7776db1c
KB		 1272 /*
1273 * Did we miss an interrupt?
1274 */
fa059b85
KB		 1275 if (test_bit(NVMEQ_POLLED, &nvmeq->flags))
1276 nvme_poll(req->mq_hctx);
1277 else
1278 nvme_poll_irqdisable(nvmeq);
1279
bf392a5d 1280 if (blk_mq_request_completed(req)) {
7776db1c
KB		 1281 dev_warn(dev->ctrl.device,
1282 "I/O %d QID %d timeout, completion polled\n",
1283 req->tag, nvmeq->qid);
db8c48e4 1284 return BLK_EH_DONE;
7776db1c
KB		 1285 }
1286
31c7c7d2 1287 /*
fd634f41
CH		 1288 * Shutdown immediately if controller times out while starting. The
1289 * reset work will see the pci device disabled when it gets the forced
1290 * cancellation error. All outstanding requests are completed on
db8c48e4 1291 * shutdown, so we return BLK_EH_DONE.
fd634f41 1292 */
4244140d
KB		 1293 switch (dev->ctrl.state) {
1294 case NVME_CTRL_CONNECTING:
2036f726 1295 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
df561f66 1296 fallthrough;
2036f726 1297 case NVME_CTRL_DELETING:
b9cac43c 1298 dev_warn_ratelimited(dev->ctrl.device,
fd634f41
CH		 1299 "I/O %d QID %d timeout, disable controller\n",
1300 req->tag, nvmeq->qid);
27fa9bc5 1301 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
7ad92f65 1302 nvme_dev_disable(dev, true);
db8c48e4 1303 return BLK_EH_DONE;
39a9dd81
KB		 1304 case NVME_CTRL_RESETTING:
1305 return BLK_EH_RESET_TIMER;
4244140d
KB		 1306 default:
1307 break;
c30341dc
KB		 1308 }
1309
fd634f41 1310 /*
ee0d96d3
BW		 1311 * Shutdown the controller immediately and schedule a reset if the
1312 * command was already aborted once before and still hasn't been
1313 * returned to the driver, or if this is the admin queue.
31c7c7d2 1314 */
f4800d6d 1315 if (!nvmeq->qid || iod->aborted) {
1b3c47c1 1316 dev_warn(dev->ctrl.device,
e1569a16
KB		 1317 "I/O %d QID %d timeout, reset controller\n",
1318 req->tag, nvmeq->qid);
7ad92f65 1319 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
a5cdb68c 1320 nvme_dev_disable(dev, false);
d86c4d8e 1321 nvme_reset_ctrl(&dev->ctrl);
c30341dc 1322
db8c48e4 1323 return BLK_EH_DONE;
c30341dc 1324 }
c30341dc 1325
e7a2a87d 1326 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
6bf25d16 1327 atomic_inc(&dev->ctrl.abort_limit);
31c7c7d2 1328 return BLK_EH_RESET_TIMER;
6bf25d16 1329 }
7bf7d778 1330 iod->aborted = 1;
a4aea562 1331
c30341dc 1332 cmd.abort.opcode = nvme_admin_abort_cmd;
a4aea562 1333 cmd.abort.cid = req->tag;
c30341dc 1334 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
c30341dc 1335
1b3c47c1
SG		 1336 dev_warn(nvmeq->dev->ctrl.device,
1337 "I/O %d QID %d timeout, aborting\n",
1338 req->tag, nvmeq->qid);
e7a2a87d
CH		 1339
1340 abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
39dfe844 1341 BLK_MQ_REQ_NOWAIT);
e7a2a87d
CH		 1342 if (IS_ERR(abort_req)) {
1343 atomic_inc(&dev->ctrl.abort_limit);
1344 return BLK_EH_RESET_TIMER;
1345 }
1346
e7a2a87d 1347 abort_req->end_io_data = NULL;
8eeed0b5 1348 blk_execute_rq_nowait(NULL, abort_req, 0, abort_endio);
c30341dc 1349
31c7c7d2
CH		 1350 /*
1351 * The aborted req will be completed on receiving the abort req.
1352 * We enable the timer again. If hit twice, it'll cause a device reset,
1353 * as the device then is in a faulty state.
1354 */
1355 return BLK_EH_RESET_TIMER;
c30341dc
KB		 1356}
1357
a4aea562
MB		 1358static void nvme_free_queue(struct nvme_queue *nvmeq)
1359{
8a1d09a6 1360 dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq),
9e866774 1361 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
63223078
CH		 1362 if (!nvmeq->sq_cmds)
1363 return;
0f238ff5 1364
63223078 1365 if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) {
88a041f4 1366 pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev),
8a1d09a6 1367 nvmeq->sq_cmds, SQ_SIZE(nvmeq));
63223078 1368 } else {
8a1d09a6 1369 dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq),
63223078 1370 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
0f238ff5 1371 }
9e866774
MW		 1372}
1373
a1a5ef99 1374static void nvme_free_queues(struct nvme_dev *dev, int lowest)
22404274
KB		 1375{
1376 int i;
1377
d858e5f0 1378 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
d858e5f0 1379 dev->ctrl.queue_count--;
147b27e4 1380 nvme_free_queue(&dev->queues[i]);
121c7ad4 1381 }
22404274
KB		 1382}
1383
4d115420
KB		 1384/**
1385 * nvme_suspend_queue - put queue into suspended state
40581d1a 1386 * @nvmeq: queue to suspend
4d115420
KB		 1387 */
1388static int nvme_suspend_queue(struct nvme_queue *nvmeq)
b60503ba 1389{
4e224106 1390 if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags))
2b25d981 1391 return 1;
a09115b2 1392
4e224106 1393 /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */
d1f06f4a 1394 mb();
a09115b2 1395
4e224106 1396 nvmeq->dev->online_queues--;
1c63dc66 1397 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
c81545f9 1398 blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q);
7c349dde
KB		 1399 if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags))
1400 pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq);
4d115420
KB		 1401 return 0;
1402}
b60503ba 1403
8fae268b
KB		 1404static void nvme_suspend_io_queues(struct nvme_dev *dev)
1405{
1406 int i;
1407
1408 for (i = dev->ctrl.queue_count - 1; i > 0; i--)
1409 nvme_suspend_queue(&dev->queues[i]);
1410}
1411
a5cdb68c 1412static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
4d115420 1413{
147b27e4 1414 struct nvme_queue *nvmeq = &dev->queues[0];
4d115420 1415
a5cdb68c
KB		 1416 if (shutdown)
1417 nvme_shutdown_ctrl(&dev->ctrl);
1418 else
b5b05048 1419 nvme_disable_ctrl(&dev->ctrl);
07836e65 1420
bf392a5d 1421 nvme_poll_irqdisable(nvmeq);
b60503ba
MW		 1422}
1423
fa46c6fb
KB		 1424/*
1425 * Called only on a device that has been disabled and after all other threads
9210c075
DZ		 1426 * that can check this device's completion queues have synced, except
1427 * nvme_poll(). This is the last chance for the driver to see a natural
1428 * completion before nvme_cancel_request() terminates all incomplete requests.
fa46c6fb
KB		 1429 */
1430static void nvme_reap_pending_cqes(struct nvme_dev *dev)
1431{
fa46c6fb
KB		 1432 int i;
1433
9210c075
DZ		 1434 for (i = dev->ctrl.queue_count - 1; i > 0; i--) {
1435 spin_lock(&dev->queues[i].cq_poll_lock);
324b494c 1436 nvme_process_cq(&dev->queues[i]);
9210c075
DZ		 1437 spin_unlock(&dev->queues[i].cq_poll_lock);
1438 }
fa46c6fb
KB		 1439}
1440
8ffaadf7
JD		 1441static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1442 int entry_size)
1443{
1444 int q_depth = dev->q_depth;
5fd4ce1b 1445 unsigned q_size_aligned = roundup(q_depth * entry_size,
6c3c05b0 1446 NVME_CTRL_PAGE_SIZE);
8ffaadf7
JD		 1447
1448 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
c45f5c99 1449 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
4e523547 1450
6c3c05b0 1451 mem_per_q = round_down(mem_per_q, NVME_CTRL_PAGE_SIZE);
c45f5c99 1452 q_depth = div_u64(mem_per_q, entry_size);
8ffaadf7
JD		 1453
1454 /*
1455 * Ensure the reduced q_depth is above some threshold where it
1456 * would be better to map queues in system memory with the
1457 * original depth
1458 */
1459 if (q_depth < 64)
1460 return -ENOMEM;
1461 }
1462
1463 return q_depth;
1464}
1465
1466static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
8a1d09a6 1467 int qid)
8ffaadf7 1468{
0f238ff5
LG		 1469 struct pci_dev *pdev = to_pci_dev(dev->dev);
1470
1471 if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
8a1d09a6 1472 nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq));
bfac8e9f
AM		 1473 if (nvmeq->sq_cmds) {
1474 nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev,
1475 nvmeq->sq_cmds);
1476 if (nvmeq->sq_dma_addr) {
1477 set_bit(NVMEQ_SQ_CMB, &nvmeq->flags);
1478 return 0;
1479 }
1480
8a1d09a6 1481 pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq));
63223078 1482 }
0f238ff5 1483 }
8ffaadf7 1484
8a1d09a6 1485 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq),
63223078 1486 &nvmeq->sq_dma_addr, GFP_KERNEL);
815c6704
KB		 1487 if (!nvmeq->sq_cmds)
1488 return -ENOMEM;
8ffaadf7
JD		 1489 return 0;
1490}
1491
a6ff7262 1492static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
b60503ba 1493{
147b27e4 1494 struct nvme_queue *nvmeq = &dev->queues[qid];
b60503ba 1495
62314e40
KB		 1496 if (dev->ctrl.queue_count > qid)
1497 return 0;
b60503ba 1498
c1e0cc7e 1499 nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES;
8a1d09a6
BH		 1500 nvmeq->q_depth = depth;
1501 nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq),
750afb08 1502 &nvmeq->cq_dma_addr, GFP_KERNEL);
b60503ba
MW		 1503 if (!nvmeq->cqes)
1504 goto free_nvmeq;
b60503ba 1505
8a1d09a6 1506 if (nvme_alloc_sq_cmds(dev, nvmeq, qid))
b60503ba
MW		 1507 goto free_cqdma;
1508
091b6092 1509 nvmeq->dev = dev;
1ab0cd69 1510 spin_lock_init(&nvmeq->sq_lock);
3a7afd8e 1511 spin_lock_init(&nvmeq->cq_poll_lock);
b60503ba 1512 nvmeq->cq_head = 0;
82123460 1513 nvmeq->cq_phase = 1;
b80d5ccc 1514 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
c30341dc 1515 nvmeq->qid = qid;
d858e5f0 1516 dev->ctrl.queue_count++;
36a7e993 1517
147b27e4 1518 return 0;
b60503ba
MW		 1519
1520 free_cqdma:
8a1d09a6
BH		 1521 dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes,
1522 nvmeq->cq_dma_addr);
b60503ba 1523 free_nvmeq:
147b27e4 1524 return -ENOMEM;
b60503ba
MW		 1525}
1526
dca51e78 1527static int queue_request_irq(struct nvme_queue *nvmeq)
3001082c 1528{
0ff199cb
CH		 1529 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1530 int nr = nvmeq->dev->ctrl.instance;
1531
1532 if (use_threaded_interrupts) {
1533 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1534 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1535 } else {
1536 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1537 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1538 }
3001082c
MW		 1539}
1540
22404274 1541static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
b60503ba 1542{
22404274 1543 struct nvme_dev *dev = nvmeq->dev;
b60503ba 1544
22404274 1545 nvmeq->sq_tail = 0;
38210800 1546 nvmeq->last_sq_tail = 0;
22404274
KB		 1547 nvmeq->cq_head = 0;
1548 nvmeq->cq_phase = 1;
b80d5ccc 1549 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
8a1d09a6 1550 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq));
f9f38e33 1551 nvme_dbbuf_init(dev, nvmeq, qid);
42f61420 1552 dev->online_queues++;
3a7afd8e 1553 wmb(); /* ensure the first interrupt sees the initialization */
22404274
KB		 1554}
1555
e4b9852a
CC		 1556/*
1557 * Try getting shutdown_lock while setting up IO queues.
1558 */
1559static int nvme_setup_io_queues_trylock(struct nvme_dev *dev)
1560{
1561 /*
1562 * Give up if the lock is being held by nvme_dev_disable.
1563 */
1564 if (!mutex_trylock(&dev->shutdown_lock))
1565 return -ENODEV;
1566
1567 /*
1568 * Controller is in wrong state, fail early.
1569 */
1570 if (dev->ctrl.state != NVME_CTRL_CONNECTING) {
1571 mutex_unlock(&dev->shutdown_lock);
1572 return -ENODEV;
1573 }
1574
1575 return 0;
1576}
1577
4b04cc6a 1578static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled)
22404274
KB		 1579{
1580 struct nvme_dev *dev = nvmeq->dev;
1581 int result;
7c349dde 1582 u16 vector = 0;
3f85d50b 1583
d1ed6aa1
CH		 1584 clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
1585
22b55601
KB		 1586 /*
1587 * A queue's vector matches the queue identifier unless the controller
1588 * has only one vector available.
1589 */
4b04cc6a
JA		 1590 if (!polled)
1591 vector = dev->num_vecs == 1 ? 0 : qid;
1592 else
7c349dde 1593 set_bit(NVMEQ_POLLED, &nvmeq->flags);
4b04cc6a 1594
a8e3e0bb 1595 result = adapter_alloc_cq(dev, qid, nvmeq, vector);
ded45505
KB		 1596 if (result)
1597 return result;
b60503ba
MW		 1598
1599 result = adapter_alloc_sq(dev, qid, nvmeq);
1600 if (result < 0)
ded45505 1601 return result;
c80b36cd 1602 if (result)
b60503ba
MW		 1603 goto release_cq;
1604
a8e3e0bb 1605 nvmeq->cq_vector = vector;
4b04cc6a 1606
e4b9852a
CC		 1607 result = nvme_setup_io_queues_trylock(dev);
1608 if (result)
1609 return result;
1610 nvme_init_queue(nvmeq, qid);
7c349dde 1611 if (!polled) {
4b04cc6a
JA		 1612 result = queue_request_irq(nvmeq);
1613 if (result < 0)
1614 goto release_sq;
1615 }
b60503ba 1616
4e224106 1617 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
e4b9852a 1618 mutex_unlock(&dev->shutdown_lock);
22404274 1619 return result;
b60503ba 1620
a8e3e0bb 1621release_sq:
f25a2dfc 1622 dev->online_queues--;
e4b9852a 1623 mutex_unlock(&dev->shutdown_lock);
b60503ba 1624 adapter_delete_sq(dev, qid);
a8e3e0bb 1625release_cq:
b60503ba 1626 adapter_delete_cq(dev, qid);
22404274 1627 return result;
b60503ba
MW		 1628}
1629
f363b089 1630static const struct blk_mq_ops nvme_mq_admin_ops = {
d29ec824 1631 .queue_rq = nvme_queue_rq,
77f02a7a 1632 .complete = nvme_pci_complete_rq,
a4aea562 1633 .init_hctx = nvme_admin_init_hctx,
0350815a 1634 .init_request = nvme_init_request,
a4aea562
MB		 1635 .timeout = nvme_timeout,
1636};
1637
f363b089 1638static const struct blk_mq_ops nvme_mq_ops = {
376f7ef8
CH		 1639 .queue_rq = nvme_queue_rq,
1640 .complete = nvme_pci_complete_rq,
1641 .commit_rqs = nvme_commit_rqs,
1642 .init_hctx = nvme_init_hctx,
1643 .init_request = nvme_init_request,
1644 .map_queues = nvme_pci_map_queues,
1645 .timeout = nvme_timeout,
1646 .poll = nvme_poll,
dabcefab
JA		 1647};
1648
ea191d2f
KB		 1649static void nvme_dev_remove_admin(struct nvme_dev *dev)
1650{
1c63dc66 1651 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
69d9a99c
KB		 1652 /*
1653 * If the controller was reset during removal, it's possible
1654 * user requests may be waiting on a stopped queue. Start the
1655 * queue to flush these to completion.
1656 */
c81545f9 1657 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1c63dc66 1658 blk_cleanup_queue(dev->ctrl.admin_q);
ea191d2f
KB		 1659 blk_mq_free_tag_set(&dev->admin_tagset);
1660 }
1661}
1662
a4aea562
MB		 1663static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1664{
1c63dc66 1665 if (!dev->ctrl.admin_q) {
a4aea562
MB		 1666 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1667 dev->admin_tagset.nr_hw_queues = 1;
e3e9d50c 1668
38dabe21 1669 dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH;
dc96f938 1670 dev->admin_tagset.timeout = NVME_ADMIN_TIMEOUT;
d4ec47f1 1671 dev->admin_tagset.numa_node = dev->ctrl.numa_node;
d43f1ccf 1672 dev->admin_tagset.cmd_size = sizeof(struct nvme_iod);
d3484991 1673 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED;
a4aea562
MB		 1674 dev->admin_tagset.driver_data = dev;
1675
1676 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1677 return -ENOMEM;
34b6c231 1678 dev->ctrl.admin_tagset = &dev->admin_tagset;
a4aea562 1679
1c63dc66
CH		 1680 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1681 if (IS_ERR(dev->ctrl.admin_q)) {
a4aea562
MB		 1682 blk_mq_free_tag_set(&dev->admin_tagset);
1683 return -ENOMEM;
1684 }
1c63dc66 1685 if (!blk_get_queue(dev->ctrl.admin_q)) {
ea191d2f 1686 nvme_dev_remove_admin(dev);
1c63dc66 1687 dev->ctrl.admin_q = NULL;
ea191d2f
KB		 1688 return -ENODEV;
1689 }
0fb59cbc 1690 } else
c81545f9 1691 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
a4aea562
MB		 1692
1693 return 0;
1694}
1695
97f6ef64
XY		 1696static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1697{
1698 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1699}
1700
1701static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1702{
1703 struct pci_dev *pdev = to_pci_dev(dev->dev);
1704
1705 if (size <= dev->bar_mapped_size)
1706 return 0;
1707 if (size > pci_resource_len(pdev, 0))
1708 return -ENOMEM;
1709 if (dev->bar)
1710 iounmap(dev->bar);
1711 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1712 if (!dev->bar) {
1713 dev->bar_mapped_size = 0;
1714 return -ENOMEM;
1715 }
1716 dev->bar_mapped_size = size;
1717 dev->dbs = dev->bar + NVME_REG_DBS;
1718
1719 return 0;
1720}
1721
01ad0990 1722static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
b60503ba 1723{
ba47e386 1724 int result;
b60503ba
MW		 1725 u32 aqa;
1726 struct nvme_queue *nvmeq;
1727
97f6ef64
XY		 1728 result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1729 if (result < 0)
1730 return result;
1731
8ef2074d 1732 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
20d0dfe6 1733 NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
dfbac8c7 1734
7a67cbea
CH		 1735 if (dev->subsystem &&
1736 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1737 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
dfbac8c7 1738
b5b05048 1739 result = nvme_disable_ctrl(&dev->ctrl);
ba47e386
MW		 1740 if (result < 0)
1741 return result;
b60503ba 1742
a6ff7262 1743 result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
147b27e4
SG		 1744 if (result)
1745 return result;
b60503ba 1746
635333e4
MG		 1747 dev->ctrl.numa_node = dev_to_node(dev->dev);
1748
147b27e4 1749 nvmeq = &dev->queues[0];
b60503ba
MW		 1750 aqa = nvmeq->q_depth - 1;
1751 aqa |= aqa << 16;
1752
7a67cbea
CH		 1753 writel(aqa, dev->bar + NVME_REG_AQA);
1754 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1755 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
b60503ba 1756
c0f2f45b 1757 result = nvme_enable_ctrl(&dev->ctrl);
025c557a 1758 if (result)
d4875622 1759 return result;
a4aea562 1760
2b25d981 1761 nvmeq->cq_vector = 0;
161b8be2 1762 nvme_init_queue(nvmeq, 0);
dca51e78 1763 result = queue_request_irq(nvmeq);
758dd7fd 1764 if (result) {
7c349dde 1765 dev->online_queues--;
d4875622 1766 return result;
758dd7fd 1767 }
025c557a 1768
4e224106 1769 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
b60503ba
MW		 1770 return result;
1771}
1772
749941f2 1773static int nvme_create_io_queues(struct nvme_dev *dev)
42f61420 1774{
4b04cc6a 1775 unsigned i, max, rw_queues;
749941f2 1776 int ret = 0;
42f61420 1777
d858e5f0 1778 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
a6ff7262 1779 if (nvme_alloc_queue(dev, i, dev->q_depth)) {
749941f2 1780 ret = -ENOMEM;
42f61420 1781 break;
749941f2
CH		 1782 }
1783 }
42f61420 1784
d858e5f0 1785 max = min(dev->max_qid, dev->ctrl.queue_count - 1);
e20ba6e1
CH		 1786 if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) {
1787 rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] +
1788 dev->io_queues[HCTX_TYPE_READ];
4b04cc6a
JA		 1789 } else {
1790 rw_queues = max;
1791 }
1792
949928c1 1793 for (i = dev->online_queues; i <= max; i++) {
4b04cc6a
JA		 1794 bool polled = i > rw_queues;
1795
1796 ret = nvme_create_queue(&dev->queues[i], i, polled);
d4875622 1797 if (ret)
42f61420 1798 break;
27e8166c 1799 }
749941f2
CH		 1800
1801 /*
1802 * Ignore failing Create SQ/CQ commands, we can continue with less
8adb8c14
MI		 1803 * than the desired amount of queues, and even a controller without
1804 * I/O queues can still be used to issue admin commands. This might
749941f2
CH		 1805 * be useful to upgrade a buggy firmware for example.
1806 */
1807 return ret >= 0 ? 0 : ret;
b60503ba
MW		 1808}
1809
88de4598 1810static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
8ffaadf7 1811{
88de4598
CH		 1812 u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
1813
1814 return 1ULL << (12 + 4 * szu);
1815}
1816
1817static u32 nvme_cmb_size(struct nvme_dev *dev)
1818{
1819 return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
1820}
1821
f65efd6d 1822static void nvme_map_cmb(struct nvme_dev *dev)
8ffaadf7 1823{
88de4598 1824 u64 size, offset;
8ffaadf7
JD		 1825 resource_size_t bar_size;
1826 struct pci_dev *pdev = to_pci_dev(dev->dev);
8969f1f8 1827 int bar;
8ffaadf7 1828
9fe5c59f
KB		 1829 if (dev->cmb_size)
1830 return;
1831
20d3bb92
KJ		 1832 if (NVME_CAP_CMBS(dev->ctrl.cap))
1833 writel(NVME_CMBMSC_CRE, dev->bar + NVME_REG_CMBMSC);
1834
7a67cbea 1835 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
f65efd6d
CH		 1836 if (!dev->cmbsz)
1837 return;
202021c1 1838 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
8ffaadf7 1839
88de4598
CH		 1840 size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
1841 offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
8969f1f8
CH		 1842 bar = NVME_CMB_BIR(dev->cmbloc);
1843 bar_size = pci_resource_len(pdev, bar);
8ffaadf7
JD		 1844
1845 if (offset > bar_size)
f65efd6d 1846 return;
8ffaadf7 1847
20d3bb92
KJ		 1848 /*
1849 * Tell the controller about the host side address mapping the CMB,
1850 * and enable CMB decoding for the NVMe 1.4+ scheme:
1851 */
1852 if (NVME_CAP_CMBS(dev->ctrl.cap)) {
1853 hi_lo_writeq(NVME_CMBMSC_CRE | NVME_CMBMSC_CMSE |
1854 (pci_bus_address(pdev, bar) + offset),
1855 dev->bar + NVME_REG_CMBMSC);
1856 }
1857
8ffaadf7
JD		 1858 /*
1859 * Controllers may support a CMB size larger than their BAR,
1860 * for example, due to being behind a bridge. Reduce the CMB to
1861 * the reported size of the BAR
1862 */
1863 if (size > bar_size - offset)
1864 size = bar_size - offset;
1865
0f238ff5
LG		 1866 if (pci_p2pdma_add_resource(pdev, bar, size, offset)) {
1867 dev_warn(dev->ctrl.device,
1868 "failed to register the CMB\n");
f65efd6d 1869 return;
0f238ff5
LG		 1870 }
1871
8ffaadf7 1872 dev->cmb_size = size;
0f238ff5
LG		 1873 dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS);
1874
1875 if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) ==
1876 (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS))
1877 pci_p2pmem_publish(pdev, true);
8ffaadf7
JD		 1878}
1879
87ad72a5
CH		 1880static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1881{
6c3c05b0 1882 u32 host_mem_size = dev->host_mem_size >> NVME_CTRL_PAGE_SHIFT;
4033f35d 1883 u64 dma_addr = dev->host_mem_descs_dma;
f66e2804 1884 struct nvme_command c = { };
87ad72a5
CH		 1885 int ret;
1886
87ad72a5
CH		 1887 c.features.opcode = nvme_admin_set_features;
1888 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1889 c.features.dword11 = cpu_to_le32(bits);
6c3c05b0 1890 c.features.dword12 = cpu_to_le32(host_mem_size);
87ad72a5
CH		 1891 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr));
1892 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr));
1893 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs);
1894
1895 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1896 if (ret) {
1897 dev_warn(dev->ctrl.device,
1898 "failed to set host mem (err %d, flags %#x).\n",
1899 ret, bits);
a5df5e79
KB		 1900 } else
1901 dev->hmb = bits & NVME_HOST_MEM_ENABLE;
1902
87ad72a5
CH		 1903 return ret;
1904}
1905
1906static void nvme_free_host_mem(struct nvme_dev *dev)
1907{
1908 int i;
1909
1910 for (i = 0; i < dev->nr_host_mem_descs; i++) {
1911 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
6c3c05b0 1912 size_t size = le32_to_cpu(desc->size) * NVME_CTRL_PAGE_SIZE;
87ad72a5 1913
cc667f6d
LD		 1914 dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i],
1915 le64_to_cpu(desc->addr),
1916 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
87ad72a5
CH		 1917 }
1918
1919 kfree(dev->host_mem_desc_bufs);
1920 dev->host_mem_desc_bufs = NULL;
4033f35d
CH		 1921 dma_free_coherent(dev->dev,
1922 dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
1923 dev->host_mem_descs, dev->host_mem_descs_dma);
87ad72a5 1924 dev->host_mem_descs = NULL;
7e5dd57e 1925 dev->nr_host_mem_descs = 0;
87ad72a5
CH		 1926}
1927
92dc6895
CH		 1928static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
1929 u32 chunk_size)
9d713c2b 1930{
87ad72a5 1931 struct nvme_host_mem_buf_desc *descs;
92dc6895 1932 u32 max_entries, len;
4033f35d 1933 dma_addr_t descs_dma;
2ee0e4ed 1934 int i = 0;
87ad72a5 1935 void **bufs;
6fbcde66 1936 u64 size, tmp;
87ad72a5 1937
87ad72a5
CH		 1938 tmp = (preferred + chunk_size - 1);
1939 do_div(tmp, chunk_size);
1940 max_entries = tmp;
044a9df1
CH		 1941
1942 if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
1943 max_entries = dev->ctrl.hmmaxd;
1944
750afb08
LC		 1945 descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs),
1946 &descs_dma, GFP_KERNEL);
87ad72a5
CH		 1947 if (!descs)
1948 goto out;
1949
1950 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
1951 if (!bufs)
1952 goto out_free_descs;
1953
244a8fe4 1954 for (size = 0; size < preferred && i < max_entries; size += len) {
87ad72a5
CH		 1955 dma_addr_t dma_addr;
1956
50cdb7c6 1957 len = min_t(u64, chunk_size, preferred - size);
87ad72a5
CH		 1958 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
1959 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1960 if (!bufs[i])
1961 break;
1962
1963 descs[i].addr = cpu_to_le64(dma_addr);
6c3c05b0 1964 descs[i].size = cpu_to_le32(len / NVME_CTRL_PAGE_SIZE);
87ad72a5
CH		 1965 i++;
1966 }
1967
92dc6895 1968 if (!size)
87ad72a5 1969 goto out_free_bufs;
87ad72a5 1970
87ad72a5
CH		 1971 dev->nr_host_mem_descs = i;
1972 dev->host_mem_size = size;
1973 dev->host_mem_descs = descs;
4033f35d 1974 dev->host_mem_descs_dma = descs_dma;
87ad72a5
CH		 1975 dev->host_mem_desc_bufs = bufs;
1976 return 0;
1977
1978out_free_bufs:
1979 while (--i >= 0) {
6c3c05b0 1980 size_t size = le32_to_cpu(descs[i].size) * NVME_CTRL_PAGE_SIZE;
87ad72a5 1981
cc667f6d
LD		 1982 dma_free_attrs(dev->dev, size, bufs[i],
1983 le64_to_cpu(descs[i].addr),
1984 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
87ad72a5
CH		 1985 }
1986
1987 kfree(bufs);
1988out_free_descs:
4033f35d
CH		 1989 dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
1990 descs_dma);
87ad72a5 1991out:
87ad72a5
CH		 1992 dev->host_mem_descs = NULL;
1993 return -ENOMEM;
1994}
1995
92dc6895
CH		 1996static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
1997{
9dc54a0d
CK		 1998 u64 min_chunk = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
1999 u64 hmminds = max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
2000 u64 chunk_size;
92dc6895
CH		 2001
2002 /* start big and work our way down */
9dc54a0d 2003 for (chunk_size = min_chunk; chunk_size >= hmminds; chunk_size /= 2) {
92dc6895
CH		 2004 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
2005 if (!min || dev->host_mem_size >= min)
2006 return 0;
2007 nvme_free_host_mem(dev);
2008 }
2009 }
2010
2011 return -ENOMEM;
2012}
2013
9620cfba 2014static int nvme_setup_host_mem(struct nvme_dev *dev)
87ad72a5
CH		 2015{
2016 u64 max = (u64)max_host_mem_size_mb * SZ_1M;
2017 u64 preferred = (u64)dev->ctrl.hmpre * 4096;
2018 u64 min = (u64)dev->ctrl.hmmin * 4096;
2019 u32 enable_bits = NVME_HOST_MEM_ENABLE;
6fbcde66 2020 int ret;
87ad72a5
CH		 2021
2022 preferred = min(preferred, max);
2023 if (min > max) {
2024 dev_warn(dev->ctrl.device,
2025 "min host memory (%lld MiB) above limit (%d MiB).\n",
2026 min >> ilog2(SZ_1M), max_host_mem_size_mb);
2027 nvme_free_host_mem(dev);
9620cfba 2028 return 0;
87ad72a5
CH		 2029 }
2030
2031 /*
2032 * If we already have a buffer allocated check if we can reuse it.
2033 */
2034 if (dev->host_mem_descs) {
2035 if (dev->host_mem_size >= min)
2036 enable_bits |= NVME_HOST_MEM_RETURN;
2037 else
2038 nvme_free_host_mem(dev);
2039 }
2040
2041 if (!dev->host_mem_descs) {
92dc6895
CH		 2042 if (nvme_alloc_host_mem(dev, min, preferred)) {
2043 dev_warn(dev->ctrl.device,
2044 "failed to allocate host memory buffer.\n");
9620cfba 2045 return 0; /* controller must work without HMB */
92dc6895
CH		 2046 }
2047
2048 dev_info(dev->ctrl.device,
2049 "allocated %lld MiB host memory buffer.\n",
2050 dev->host_mem_size >> ilog2(SZ_1M));
87ad72a5
CH		 2051 }
2052
9620cfba
CH		 2053 ret = nvme_set_host_mem(dev, enable_bits);
2054 if (ret)
87ad72a5 2055 nvme_free_host_mem(dev);
9620cfba 2056 return ret;
9d713c2b
KB		 2057}
2058
0521905e
KB		 2059static ssize_t cmb_show(struct device *dev, struct device_attribute *attr,
2060 char *buf)
2061{
2062 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2063
2064 return sysfs_emit(buf, "cmbloc : x%08x\ncmbsz : x%08x\n",
2065 ndev->cmbloc, ndev->cmbsz);
2066}
2067static DEVICE_ATTR_RO(cmb);
2068
1751e97a
KB		 2069static ssize_t cmbloc_show(struct device *dev, struct device_attribute *attr,
2070 char *buf)
2071{
2072 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2073
2074 return sysfs_emit(buf, "%u\n", ndev->cmbloc);
2075}
2076static DEVICE_ATTR_RO(cmbloc);
2077
2078static ssize_t cmbsz_show(struct device *dev, struct device_attribute *attr,
2079 char *buf)
2080{
2081 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2082
2083 return sysfs_emit(buf, "%u\n", ndev->cmbsz);
2084}
2085static DEVICE_ATTR_RO(cmbsz);
2086
a5df5e79
KB		 2087static ssize_t hmb_show(struct device *dev, struct device_attribute *attr,
2088 char *buf)
2089{
2090 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2091
2092 return sysfs_emit(buf, "%d\n", ndev->hmb);
2093}
2094
2095static ssize_t hmb_store(struct device *dev, struct device_attribute *attr,
2096 const char *buf, size_t count)
2097{
2098 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2099 bool new;
2100 int ret;
2101
2102 if (strtobool(buf, &new) < 0)
2103 return -EINVAL;
2104
2105 if (new == ndev->hmb)
2106 return count;
2107
2108 if (new) {
2109 ret = nvme_setup_host_mem(ndev);
2110 } else {
2111 ret = nvme_set_host_mem(ndev, 0);
2112 if (!ret)
2113 nvme_free_host_mem(ndev);
2114 }
2115
2116 if (ret < 0)
2117 return ret;
2118
2119 return count;
2120}
2121static DEVICE_ATTR_RW(hmb);
2122
0521905e
KB		 2123static umode_t nvme_pci_attrs_are_visible(struct kobject *kobj,
2124 struct attribute *a, int n)
2125{
2126 struct nvme_ctrl *ctrl =
2127 dev_get_drvdata(container_of(kobj, struct device, kobj));
2128 struct nvme_dev *dev = to_nvme_dev(ctrl);
2129
1751e97a
KB		 2130 if (a == &dev_attr_cmb.attr ||
2131 a == &dev_attr_cmbloc.attr ||
2132 a == &dev_attr_cmbsz.attr) {
2133 if (!dev->cmbsz)
2134 return 0;
2135 }
a5df5e79
KB		 2136 if (a == &dev_attr_hmb.attr && !ctrl->hmpre)
2137 return 0;
2138
0521905e
KB		 2139 return a->mode;
2140}
2141
2142static struct attribute *nvme_pci_attrs[] = {
2143 &dev_attr_cmb.attr,
1751e97a
KB		 2144 &dev_attr_cmbloc.attr,
2145 &dev_attr_cmbsz.attr,
a5df5e79 2146 &dev_attr_hmb.attr,
0521905e
KB		 2147 NULL,
2148};
2149
2150static const struct attribute_group nvme_pci_attr_group = {
2151 .attrs = nvme_pci_attrs,
2152 .is_visible = nvme_pci_attrs_are_visible,
2153};
2154
612b7286
ML		 2155/*
2156 * nirqs is the number of interrupts available for write and read
2157 * queues. The core already reserved an interrupt for the admin queue.
2158 */
2159static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs)
3b6592f7 2160{
612b7286 2161 struct nvme_dev *dev = affd->priv;
2a5bcfdd 2162 unsigned int nr_read_queues, nr_write_queues = dev->nr_write_queues;
3b6592f7
JA		 2163
2164 /*
ee0d96d3 2165 * If there is no interrupt available for queues, ensure that
612b7286
ML		 2166 * the default queue is set to 1. The affinity set size is
2167 * also set to one, but the irq core ignores it for this case.
2168 *
2169 * If only one interrupt is available or 'write_queue' == 0, combine
2170 * write and read queues.
2171 *
2172 * If 'write_queues' > 0, ensure it leaves room for at least one read
2173 * queue.
3b6592f7 2174 */
612b7286
ML		 2175 if (!nrirqs) {
2176 nrirqs = 1;
2177 nr_read_queues = 0;
2a5bcfdd 2178 } else if (nrirqs == 1 || !nr_write_queues) {
612b7286 2179 nr_read_queues = 0;
2a5bcfdd 2180 } else if (nr_write_queues >= nrirqs) {
612b7286 2181 nr_read_queues = 1;
3b6592f7 2182 } else {
2a5bcfdd 2183 nr_read_queues = nrirqs - nr_write_queues;
3b6592f7 2184 }
612b7286
ML		 2185
2186 dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2187 affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2188 dev->io_queues[HCTX_TYPE_READ] = nr_read_queues;
2189 affd->set_size[HCTX_TYPE_READ] = nr_read_queues;
2190 affd->nr_sets = nr_read_queues ? 2 : 1;
3b6592f7
JA		 2191}
2192
6451fe73 2193static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues)
3b6592f7
JA		 2194{
2195 struct pci_dev *pdev = to_pci_dev(dev->dev);
3b6592f7 2196 struct irq_affinity affd = {
9cfef55b 2197 .pre_vectors = 1,
612b7286
ML		 2198 .calc_sets = nvme_calc_irq_sets,
2199 .priv = dev,
3b6592f7 2200 };
21cc2f3f 2201 unsigned int irq_queues, poll_queues;
6451fe73
JA		 2202
2203 /*
21cc2f3f
JX		 2204 * Poll queues don't need interrupts, but we need at least one I/O queue
2205 * left over for non-polled I/O.
6451fe73 2206 */
21cc2f3f
JX		 2207 poll_queues = min(dev->nr_poll_queues, nr_io_queues - 1);
2208 dev->io_queues[HCTX_TYPE_POLL] = poll_queues;
3b6592f7 2209
21cc2f3f
JX		 2210 /*
2211 * Initialize for the single interrupt case, will be updated in
2212 * nvme_calc_irq_sets().
2213 */
612b7286
ML		 2214 dev->io_queues[HCTX_TYPE_DEFAULT] = 1;
2215 dev->io_queues[HCTX_TYPE_READ] = 0;
3b6592f7 2216
66341331 2217 /*
21cc2f3f
JX		 2218 * We need interrupts for the admin queue and each non-polled I/O queue,
2219 * but some Apple controllers require all queues to use the first
2220 * vector.
66341331 2221 */
21cc2f3f
JX		 2222 irq_queues = 1;
2223 if (!(dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR))
2224 irq_queues += (nr_io_queues - poll_queues);
612b7286
ML		 2225 return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues,
2226 PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd);
3b6592f7
JA		 2227}
2228
8fae268b
KB		 2229static void nvme_disable_io_queues(struct nvme_dev *dev)
2230{
2231 if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq))
2232 __nvme_disable_io_queues(dev, nvme_admin_delete_cq);
2233}
2234
2a5bcfdd
WZ		 2235static unsigned int nvme_max_io_queues(struct nvme_dev *dev)
2236{
e3aef095
NS		 2237 /*
2238 * If tags are shared with admin queue (Apple bug), then
2239 * make sure we only use one IO queue.
2240 */
2241 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2242 return 1;
2a5bcfdd
WZ		 2243 return num_possible_cpus() + dev->nr_write_queues + dev->nr_poll_queues;
2244}
2245
8d85fce7 2246static int nvme_setup_io_queues(struct nvme_dev *dev)
b60503ba 2247{
147b27e4 2248 struct nvme_queue *adminq = &dev->queues[0];
e75ec752 2249 struct pci_dev *pdev = to_pci_dev(dev->dev);
2a5bcfdd 2250 unsigned int nr_io_queues;
97f6ef64 2251 unsigned long size;
2a5bcfdd 2252 int result;
b60503ba 2253
2a5bcfdd
WZ		 2254 /*
2255 * Sample the module parameters once at reset time so that we have
2256 * stable values to work with.
2257 */
2258 dev->nr_write_queues = write_queues;
2259 dev->nr_poll_queues = poll_queues;
d38e9f04 2260
e3aef095 2261 nr_io_queues = dev->nr_allocated_queues - 1;
9a0be7ab
CH		 2262 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
2263 if (result < 0)
1b23484b 2264 return result;
9a0be7ab 2265
f5fa90dc 2266 if (nr_io_queues == 0)
a5229050 2267 return 0;
53dc180e 2268
e4b9852a
CC		 2269 /*
2270 * Free IRQ resources as soon as NVMEQ_ENABLED bit transitions
2271 * from set to unset. If there is a window to it is truely freed,
2272 * pci_free_irq_vectors() jumping into this window will crash.
2273 * And take lock to avoid racing with pci_free_irq_vectors() in
2274 * nvme_dev_disable() path.
2275 */
2276 result = nvme_setup_io_queues_trylock(dev);
2277 if (result)
2278 return result;
2279 if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags))
2280 pci_free_irq(pdev, 0, adminq);
b60503ba 2281
0f238ff5 2282 if (dev->cmb_use_sqes) {
8ffaadf7
JD		 2283 result = nvme_cmb_qdepth(dev, nr_io_queues,
2284 sizeof(struct nvme_command));
2285 if (result > 0)
2286 dev->q_depth = result;
2287 else
0f238ff5 2288 dev->cmb_use_sqes = false;
8ffaadf7
JD		 2289 }
2290
97f6ef64
XY		 2291 do {
2292 size = db_bar_size(dev, nr_io_queues);
2293 result = nvme_remap_bar(dev, size);
2294 if (!result)
2295 break;
e4b9852a
CC		 2296 if (!--nr_io_queues) {
2297 result = -ENOMEM;
2298 goto out_unlock;
2299 }
97f6ef64
XY		 2300 } while (1);
2301 adminq->q_db = dev->dbs;
f1938f6e 2302
8fae268b 2303 retry:
9d713c2b 2304 /* Deregister the admin queue's interrupt */
e4b9852a
CC		 2305 if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags))
2306 pci_free_irq(pdev, 0, adminq);
9d713c2b 2307
e32efbfc
JA		 2308 /*
2309 * If we enable msix early due to not intx, disable it again before
2310 * setting up the full range we need.
2311 */
dca51e78 2312 pci_free_irq_vectors(pdev);
3b6592f7
JA		 2313
2314 result = nvme_setup_irqs(dev, nr_io_queues);
e4b9852a
CC		 2315 if (result <= 0) {
2316 result = -EIO;
2317 goto out_unlock;
2318 }
3b6592f7 2319
22b55601 2320 dev->num_vecs = result;
4b04cc6a 2321 result = max(result - 1, 1);
e20ba6e1 2322 dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL];
fa08a396 2323
063a8096
MW		 2324 /*
2325 * Should investigate if there's a performance win from allocating
2326 * more queues than interrupt vectors; it might allow the submission
2327 * path to scale better, even if the receive path is limited by the
2328 * number of interrupts.
2329 */
dca51e78 2330 result = queue_request_irq(adminq);
7c349dde 2331 if (result)
e4b9852a 2332 goto out_unlock;
4e224106 2333 set_bit(NVMEQ_ENABLED, &adminq->flags);
e4b9852a 2334 mutex_unlock(&dev->shutdown_lock);
8fae268b
KB		 2335
2336 result = nvme_create_io_queues(dev);
2337 if (result || dev->online_queues < 2)
2338 return result;
2339
2340 if (dev->online_queues - 1 < dev->max_qid) {
2341 nr_io_queues = dev->online_queues - 1;
2342 nvme_disable_io_queues(dev);
e4b9852a
CC		 2343 result = nvme_setup_io_queues_trylock(dev);
2344 if (result)
2345 return result;
8fae268b
KB		 2346 nvme_suspend_io_queues(dev);
2347 goto retry;
2348 }
2349 dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n",
2350 dev->io_queues[HCTX_TYPE_DEFAULT],
2351 dev->io_queues[HCTX_TYPE_READ],
2352 dev->io_queues[HCTX_TYPE_POLL]);
2353 return 0;
e4b9852a
CC		 2354out_unlock:
2355 mutex_unlock(&dev->shutdown_lock);
2356 return result;
b60503ba
MW		 2357}
2358
2a842aca 2359static void nvme_del_queue_end(struct request *req, blk_status_t error)
a5768aa8 2360{
db3cbfff 2361 struct nvme_queue *nvmeq = req->end_io_data;
b5875222 2362
db3cbfff 2363 blk_mq_free_request(req);
d1ed6aa1 2364 complete(&nvmeq->delete_done);
a5768aa8
KB		 2365}
2366
2a842aca 2367static void nvme_del_cq_end(struct request *req, blk_status_t error)
a5768aa8 2368{
db3cbfff 2369 struct nvme_queue *nvmeq = req->end_io_data;
a5768aa8 2370
d1ed6aa1
CH		 2371 if (error)
2372 set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
db3cbfff
KB		 2373
2374 nvme_del_queue_end(req, error);
a5768aa8
KB		 2375}
2376
db3cbfff 2377static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
bda4e0fb 2378{
db3cbfff
KB		 2379 struct request_queue *q = nvmeq->dev->ctrl.admin_q;
2380 struct request *req;
f66e2804 2381 struct nvme_command cmd = { };
bda4e0fb 2382
db3cbfff
KB		 2383 cmd.delete_queue.opcode = opcode;
2384 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
bda4e0fb 2385
39dfe844 2386 req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT);
db3cbfff
KB		 2387 if (IS_ERR(req))
2388 return PTR_ERR(req);
bda4e0fb 2389
db3cbfff
KB		 2390 req->end_io_data = nvmeq;
2391
d1ed6aa1 2392 init_completion(&nvmeq->delete_done);
8eeed0b5 2393 blk_execute_rq_nowait(NULL, req, false,
db3cbfff
KB		 2394 opcode == nvme_admin_delete_cq ?
2395 nvme_del_cq_end : nvme_del_queue_end);
2396 return 0;
bda4e0fb
KB		 2397}
2398
8fae268b 2399static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode)
a5768aa8 2400{
5271edd4 2401 int nr_queues = dev->online_queues - 1, sent = 0;
db3cbfff 2402 unsigned long timeout;
a5768aa8 2403
db3cbfff 2404 retry:
dc96f938 2405 timeout = NVME_ADMIN_TIMEOUT;
5271edd4
CH		 2406 while (nr_queues > 0) {
2407 if (nvme_delete_queue(&dev->queues[nr_queues], opcode))
2408 break;
2409 nr_queues--;
2410 sent++;
db3cbfff 2411 }
d1ed6aa1
CH		 2412 while (sent) {
2413 struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent];
2414
2415 timeout = wait_for_completion_io_timeout(&nvmeq->delete_done,
5271edd4
CH		 2416 timeout);
2417 if (timeout == 0)
2418 return false;
d1ed6aa1 2419
d1ed6aa1 2420 sent--;
5271edd4
CH		 2421 if (nr_queues)
2422 goto retry;
2423 }
2424 return true;
a5768aa8
KB		 2425}
2426
5d02a5c1 2427static void nvme_dev_add(struct nvme_dev *dev)
b60503ba 2428{
2b1b7e78
JW		 2429 int ret;
2430
5bae7f73 2431 if (!dev->ctrl.tagset) {
376f7ef8 2432 dev->tagset.ops = &nvme_mq_ops;
ffe7704d 2433 dev->tagset.nr_hw_queues = dev->online_queues - 1;
8fe34be1 2434 dev->tagset.nr_maps = 2; /* default + read */
ed92ad37
CH		 2435 if (dev->io_queues[HCTX_TYPE_POLL])
2436 dev->tagset.nr_maps++;
ffe7704d 2437 dev->tagset.timeout = NVME_IO_TIMEOUT;
d4ec47f1 2438 dev->tagset.numa_node = dev->ctrl.numa_node;
61f3b896
CK		 2439 dev->tagset.queue_depth = min_t(unsigned int, dev->q_depth,
2440 BLK_MQ_MAX_DEPTH) - 1;
d43f1ccf 2441 dev->tagset.cmd_size = sizeof(struct nvme_iod);
ffe7704d
KB		 2442 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2443 dev->tagset.driver_data = dev;
b60503ba 2444
d38e9f04
BH		 2445 /*
2446 * Some Apple controllers requires tags to be unique
2447 * across admin and IO queue, so reserve the first 32
2448 * tags of the IO queue.
2449 */
2450 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2451 dev->tagset.reserved_tags = NVME_AQ_DEPTH;
2452
2b1b7e78
JW		 2453 ret = blk_mq_alloc_tag_set(&dev->tagset);
2454 if (ret) {
2455 dev_warn(dev->ctrl.device,
2456 "IO queues tagset allocation failed %d\n", ret);
5d02a5c1 2457 return;
2b1b7e78 2458 }
5bae7f73 2459 dev->ctrl.tagset = &dev->tagset;
949928c1
KB		 2460 } else {
2461 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2462
2463 /* Free previously allocated queues that are no longer usable */
2464 nvme_free_queues(dev, dev->online_queues);
ffe7704d 2465 }
949928c1 2466
e8fd41bb 2467 nvme_dbbuf_set(dev);
b60503ba
MW		 2468}
2469
b00a726a 2470static int nvme_pci_enable(struct nvme_dev *dev)
0877cb0d 2471{
b00a726a 2472 int result = -ENOMEM;
e75ec752 2473 struct pci_dev *pdev = to_pci_dev(dev->dev);
4bdf2603 2474 int dma_address_bits = 64;
0877cb0d
KB		 2475
2476 if (pci_enable_device_mem(pdev))
2477 return result;
2478
0877cb0d 2479 pci_set_master(pdev);
0877cb0d 2480
4bdf2603
FS		 2481 if (dev->ctrl.quirks & NVME_QUIRK_DMA_ADDRESS_BITS_48)
2482 dma_address_bits = 48;
2483 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(dma_address_bits)))
052d0efa 2484 goto disable;
0877cb0d 2485
7a67cbea 2486 if (readl(dev->bar + NVME_REG_CSTS) == -1) {
0e53d180 2487 result = -ENODEV;
b00a726a 2488 goto disable;
0e53d180 2489 }
e32efbfc
JA		 2490
2491 /*
a5229050
KB		 2492 * Some devices and/or platforms don't advertise or work with INTx
2493 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2494 * adjust this later.
e32efbfc 2495 */
dca51e78
CH		 2496 result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
2497 if (result < 0)
2498 return result;
e32efbfc 2499
20d0dfe6 2500 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
7a67cbea 2501
7442ddce 2502 dev->q_depth = min_t(u32, NVME_CAP_MQES(dev->ctrl.cap) + 1,
b27c1e68 2503 io_queue_depth);
aa22c8e6 2504 dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */
20d0dfe6 2505 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
7a67cbea 2506 dev->dbs = dev->bar + 4096;
1f390c1f 2507
66341331
BH		 2508 /*
2509 * Some Apple controllers require a non-standard SQE size.
2510 * Interestingly they also seem to ignore the CC:IOSQES register
2511 * so we don't bother updating it here.
2512 */
2513 if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES)
2514 dev->io_sqes = 7;
2515 else
2516 dev->io_sqes = NVME_NVM_IOSQES;
1f390c1f
SG		 2517
2518 /*
2519 * Temporary fix for the Apple controller found in the MacBook8,1 and
2520 * some MacBook7,1 to avoid controller resets and data loss.
2521 */
2522 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
2523 dev->q_depth = 2;
9bdcfb10
CH		 2524 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
2525 "set queue depth=%u to work around controller resets\n",
1f390c1f 2526 dev->q_depth);
d554b5e1
MP		 2527 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2528 (pdev->device == 0xa821 || pdev->device == 0xa822) &&
20d0dfe6 2529 NVME_CAP_MQES(dev->ctrl.cap) == 0) {
d554b5e1
MP		 2530 dev->q_depth = 64;
2531 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2532 "set queue depth=%u\n", dev->q_depth);
1f390c1f
SG		 2533 }
2534
d38e9f04
BH		 2535 /*
2536 * Controllers with the shared tags quirk need the IO queue to be
2537 * big enough so that we get 32 tags for the admin queue
2538 */
2539 if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) &&
2540 (dev->q_depth < (NVME_AQ_DEPTH + 2))) {
2541 dev->q_depth = NVME_AQ_DEPTH + 2;
2542 dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n",
2543 dev->q_depth);
2544 }
2545
2546
f65efd6d 2547 nvme_map_cmb(dev);
202021c1 2548
a0a3408e
KB		 2549 pci_enable_pcie_error_reporting(pdev);
2550 pci_save_state(pdev);
0877cb0d
KB		 2551 return 0;
2552
2553 disable:
0877cb0d
KB		 2554 pci_disable_device(pdev);
2555 return result;
2556}
2557
2558static void nvme_dev_unmap(struct nvme_dev *dev)
b00a726a
KB		 2559{
2560 if (dev->bar)
2561 iounmap(dev->bar);
a1f447b3 2562 pci_release_mem_regions(to_pci_dev(dev->dev));
b00a726a
KB		 2563}
2564
2565static void nvme_pci_disable(struct nvme_dev *dev)
0877cb0d 2566{
e75ec752
CH		 2567 struct pci_dev *pdev = to_pci_dev(dev->dev);
2568
dca51e78 2569 pci_free_irq_vectors(pdev);
0877cb0d 2570
a0a3408e
KB		 2571 if (pci_is_enabled(pdev)) {
2572 pci_disable_pcie_error_reporting(pdev);
e75ec752 2573 pci_disable_device(pdev);
4d115420 2574 }
4d115420
KB		 2575}
2576
a5cdb68c 2577static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
b60503ba 2578{
e43269e6 2579 bool dead = true, freeze = false;
302ad8cc 2580 struct pci_dev *pdev = to_pci_dev(dev->dev);
22404274 2581
77bf25ea 2582 mutex_lock(&dev->shutdown_lock);
302ad8cc
KB		 2583 if (pci_is_enabled(pdev)) {
2584 u32 csts = readl(dev->bar + NVME_REG_CSTS);
2585
ebef7368 2586 if (dev->ctrl.state == NVME_CTRL_LIVE ||
e43269e6
KB		 2587 dev->ctrl.state == NVME_CTRL_RESETTING) {
2588 freeze = true;
302ad8cc 2589 nvme_start_freeze(&dev->ctrl);
e43269e6 2590 }
302ad8cc
KB		 2591 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
2592 pdev->error_state != pci_channel_io_normal);
c9d3bf88 2593 }
c21377f8 2594
302ad8cc
KB		 2595 /*
2596 * Give the controller a chance to complete all entered requests if
2597 * doing a safe shutdown.
2598 */
e43269e6
KB		 2599 if (!dead && shutdown && freeze)
2600 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
9a915a5b
JW		 2601
2602 nvme_stop_queues(&dev->ctrl);
87ad72a5 2603
64ee0ac0 2604 if (!dead && dev->ctrl.queue_count > 0) {
8fae268b 2605 nvme_disable_io_queues(dev);
a5cdb68c 2606 nvme_disable_admin_queue(dev, shutdown);
4d115420 2607 }
8fae268b
KB		 2608 nvme_suspend_io_queues(dev);
2609 nvme_suspend_queue(&dev->queues[0]);
b00a726a 2610 nvme_pci_disable(dev);
fa46c6fb 2611 nvme_reap_pending_cqes(dev);
07836e65 2612
e1958e65
ML		 2613 blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
2614 blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
622b8b68
ML		 2615 blk_mq_tagset_wait_completed_request(&dev->tagset);
2616 blk_mq_tagset_wait_completed_request(&dev->admin_tagset);
302ad8cc
KB		 2617
2618 /*
2619 * The driver will not be starting up queues again if shutting down so
2620 * must flush all entered requests to their failed completion to avoid
2621 * deadlocking blk-mq hot-cpu notifier.
2622 */
c8e9e9b7 2623 if (shutdown) {
302ad8cc 2624 nvme_start_queues(&dev->ctrl);
c8e9e9b7
KB		 2625 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q))
2626 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
2627 }
77bf25ea 2628 mutex_unlock(&dev->shutdown_lock);
b60503ba
MW		 2629}
2630
c1ac9a4b
KB		 2631static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown)
2632{
2633 if (!nvme_wait_reset(&dev->ctrl))
2634 return -EBUSY;
2635 nvme_dev_disable(dev, shutdown);
2636 return 0;
2637}
2638
091b6092
MW		 2639static int nvme_setup_prp_pools(struct nvme_dev *dev)
2640{
e75ec752 2641 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
c61b82c7
CH		 2642 NVME_CTRL_PAGE_SIZE,
2643 NVME_CTRL_PAGE_SIZE, 0);
091b6092
MW		 2644 if (!dev->prp_page_pool)
2645 return -ENOMEM;
2646
99802a7a 2647 /* Optimisation for I/Os between 4k and 128k */
e75ec752 2648 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
99802a7a
MW		 2649 256, 256, 0);
2650 if (!dev->prp_small_pool) {
2651 dma_pool_destroy(dev->prp_page_pool);
2652 return -ENOMEM;
2653 }
091b6092
MW		 2654 return 0;
2655}
2656
2657static void nvme_release_prp_pools(struct nvme_dev *dev)
2658{
2659 dma_pool_destroy(dev->prp_page_pool);
99802a7a 2660 dma_pool_destroy(dev->prp_small_pool);
091b6092
MW		 2661}
2662
770597ec
KB		 2663static void nvme_free_tagset(struct nvme_dev *dev)
2664{
2665 if (dev->tagset.tags)
2666 blk_mq_free_tag_set(&dev->tagset);
2667 dev->ctrl.tagset = NULL;
2668}
2669
1673f1f0 2670static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
5e82e952 2671{
1673f1f0 2672 struct nvme_dev *dev = to_nvme_dev(ctrl);
9ac27090 2673
f9f38e33 2674 nvme_dbbuf_dma_free(dev);
770597ec 2675 nvme_free_tagset(dev);
1c63dc66
CH		 2676 if (dev->ctrl.admin_q)
2677 blk_put_queue(dev->ctrl.admin_q);
e286bcfc 2678 free_opal_dev(dev->ctrl.opal_dev);
943e942e 2679 mempool_destroy(dev->iod_mempool);
253fd4ac
IR		 2680 put_device(dev->dev);
2681 kfree(dev->queues);
5e82e952
KB		 2682 kfree(dev);
2683}
2684
7c1ce408 2685static void nvme_remove_dead_ctrl(struct nvme_dev *dev)
f58944e2 2686{
c1ac9a4b
KB		 2687 /*
2688 * Set state to deleting now to avoid blocking nvme_wait_reset(), which
2689 * may be holding this pci_dev's device lock.
2690 */
2691 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
d22524a4 2692 nvme_get_ctrl(&dev->ctrl);
69d9a99c 2693 nvme_dev_disable(dev, false);
9f9cafc1 2694 nvme_kill_queues(&dev->ctrl);
03e0f3a6 2695 if (!queue_work(nvme_wq, &dev->remove_work))
f58944e2
KB		 2696 nvme_put_ctrl(&dev->ctrl);
2697}
2698
fd634f41 2699static void nvme_reset_work(struct work_struct *work)
5e82e952 2700{
d86c4d8e
CH		 2701 struct nvme_dev *dev =
2702 container_of(work, struct nvme_dev, ctrl.reset_work);
a98e58e5 2703 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
e71afda4 2704 int result;
5e82e952 2705
7764656b
ZC		 2706 if (dev->ctrl.state != NVME_CTRL_RESETTING) {
2707 dev_warn(dev->ctrl.device, "ctrl state %d is not RESETTING\n",
2708 dev->ctrl.state);
e71afda4 2709 result = -ENODEV;
fd634f41 2710 goto out;
e71afda4 2711 }
5e82e952 2712
fd634f41
CH		 2713 /*
2714 * If we're called to reset a live controller first shut it down before
2715 * moving on.
2716 */
b00a726a 2717 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
a5cdb68c 2718 nvme_dev_disable(dev, false);
d6135c3a 2719 nvme_sync_queues(&dev->ctrl);
5e82e952 2720
5c959d73 2721 mutex_lock(&dev->shutdown_lock);
b00a726a 2722 result = nvme_pci_enable(dev);
f0b50732 2723 if (result)
4726bcf3 2724 goto out_unlock;
f0b50732 2725
01ad0990 2726 result = nvme_pci_configure_admin_queue(dev);
f0b50732 2727 if (result)
4726bcf3 2728 goto out_unlock;
f0b50732 2729
0fb59cbc
KB		 2730 result = nvme_alloc_admin_tags(dev);
2731 if (result)
4726bcf3 2732 goto out_unlock;
b9afca3e 2733
943e942e
JA		 2734 /*
2735 * Limit the max command size to prevent iod->sg allocations going
2736 * over a single page.
2737 */
7637de31
CH		 2738 dev->ctrl.max_hw_sectors = min_t(u32,
2739 NVME_MAX_KB_SZ << 1, dma_max_mapping_size(dev->dev) >> 9);
943e942e 2740 dev->ctrl.max_segments = NVME_MAX_SEGS;
a48bc520
CH		 2741
2742 /*
2743 * Don't limit the IOMMU merged segment size.
2744 */
2745 dma_set_max_seg_size(dev->dev, 0xffffffff);
3d2d861e 2746 dma_set_min_align_mask(dev->dev, NVME_CTRL_PAGE_SIZE - 1);
a48bc520 2747
5c959d73
KB		 2748 mutex_unlock(&dev->shutdown_lock);
2749
2750 /*
2751 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
2752 * initializing procedure here.
2753 */
2754 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
2755 dev_warn(dev->ctrl.device,
2756 "failed to mark controller CONNECTING\n");
cee6c269 2757 result = -EBUSY;
5c959d73
KB		 2758 goto out;
2759 }
943e942e 2760
95093350
MG		 2761 /*
2762 * We do not support an SGL for metadata (yet), so we are limited to a
2763 * single integrity segment for the separate metadata pointer.
2764 */
2765 dev->ctrl.max_integrity_segments = 1;
2766
f21c4769 2767 result = nvme_init_ctrl_finish(&dev->ctrl);
ce4541f4 2768 if (result)
f58944e2 2769 goto out;
ce4541f4 2770
e286bcfc
SB		 2771 if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
2772 if (!dev->ctrl.opal_dev)
2773 dev->ctrl.opal_dev =
2774 init_opal_dev(&dev->ctrl, &nvme_sec_submit);
2775 else if (was_suspend)
2776 opal_unlock_from_suspend(dev->ctrl.opal_dev);
2777 } else {
2778 free_opal_dev(dev->ctrl.opal_dev);
2779 dev->ctrl.opal_dev = NULL;
4f1244c8 2780 }
a98e58e5 2781
f9f38e33
HK		 2782 if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) {
2783 result = nvme_dbbuf_dma_alloc(dev);
2784 if (result)
2785 dev_warn(dev->dev,
2786 "unable to allocate dma for dbbuf\n");
2787 }
2788
9620cfba
CH		 2789 if (dev->ctrl.hmpre) {
2790 result = nvme_setup_host_mem(dev);
2791 if (result < 0)
2792 goto out;
2793 }
87ad72a5 2794
f0b50732 2795 result = nvme_setup_io_queues(dev);
badc34d4 2796 if (result)
f58944e2 2797 goto out;
f0b50732 2798
2659e57b
CH		 2799 /*
2800 * Keep the controller around but remove all namespaces if we don't have
2801 * any working I/O queue.
2802 */
3cf519b5 2803 if (dev->online_queues < 2) {
1b3c47c1 2804 dev_warn(dev->ctrl.device, "IO queues not created\n");
3b24774e 2805 nvme_kill_queues(&dev->ctrl);
5bae7f73 2806 nvme_remove_namespaces(&dev->ctrl);
770597ec 2807 nvme_free_tagset(dev);
3cf519b5 2808 } else {
25646264 2809 nvme_start_queues(&dev->ctrl);
302ad8cc 2810 nvme_wait_freeze(&dev->ctrl);
5d02a5c1 2811 nvme_dev_add(dev);
302ad8cc 2812 nvme_unfreeze(&dev->ctrl);
3cf519b5
CH		 2813 }
2814
2b1b7e78
JW		 2815 /*
2816 * If only admin queue live, keep it to do further investigation or
2817 * recovery.
2818 */
5d02a5c1 2819 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
2b1b7e78 2820 dev_warn(dev->ctrl.device,
5d02a5c1 2821 "failed to mark controller live state\n");
e71afda4 2822 result = -ENODEV;
bb8d261e
CH		 2823 goto out;
2824 }
92911a55 2825
0521905e
KB		 2826 if (!dev->attrs_added && !sysfs_create_group(&dev->ctrl.device->kobj,
2827 &nvme_pci_attr_group))
2828 dev->attrs_added = true;
2829
d09f2b45 2830 nvme_start_ctrl(&dev->ctrl);
3cf519b5 2831 return;
f0b50732 2832
4726bcf3
KB		 2833 out_unlock:
2834 mutex_unlock(&dev->shutdown_lock);
3cf519b5 2835 out:
7c1ce408
CK		 2836 if (result)
2837 dev_warn(dev->ctrl.device,
2838 "Removing after probe failure status: %d\n", result);
2839 nvme_remove_dead_ctrl(dev);
f0b50732
KB		 2840}
2841
5c8809e6 2842static void nvme_remove_dead_ctrl_work(struct work_struct *work)
9a6b9458 2843{
5c8809e6 2844 struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
e75ec752 2845 struct pci_dev *pdev = to_pci_dev(dev->dev);
9a6b9458
KB		 2846
2847 if (pci_get_drvdata(pdev))
921920ab 2848 device_release_driver(&pdev->dev);
1673f1f0 2849 nvme_put_ctrl(&dev->ctrl);
9a6b9458
KB		 2850}
2851
1c63dc66 2852static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
9ca97374 2853{
1c63dc66 2854 *val = readl(to_nvme_dev(ctrl)->bar + off);
90667892 2855 return 0;
9ca97374
TH		 2856}
2857
5fd4ce1b 2858static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
4cc06521 2859{
5fd4ce1b
CH		 2860 writel(val, to_nvme_dev(ctrl)->bar + off);
2861 return 0;
2862}
4cc06521 2863
7fd8930f
CH		 2864static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2865{
3a8ecc93 2866 *val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off);
7fd8930f 2867 return 0;
4cc06521
KB		 2868}
2869
97c12223
KB		 2870static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
2871{
2872 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2873
2db24e4a 2874 return snprintf(buf, size, "%s\n", dev_name(&pdev->dev));
97c12223
KB		 2875}
2876
1c63dc66 2877static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
1a353d85 2878 .name = "pcie",
e439bb12 2879 .module = THIS_MODULE,
e0596ab2
LG		 2880 .flags = NVME_F_METADATA_SUPPORTED |
2881 NVME_F_PCI_P2PDMA,
1c63dc66 2882 .reg_read32 = nvme_pci_reg_read32,
5fd4ce1b 2883 .reg_write32 = nvme_pci_reg_write32,
7fd8930f 2884 .reg_read64 = nvme_pci_reg_read64,
1673f1f0 2885 .free_ctrl = nvme_pci_free_ctrl,
f866fc42 2886 .submit_async_event = nvme_pci_submit_async_event,
97c12223 2887 .get_address = nvme_pci_get_address,
1c63dc66 2888};
4cc06521 2889
b00a726a
KB		 2890static int nvme_dev_map(struct nvme_dev *dev)
2891{
b00a726a
KB		 2892 struct pci_dev *pdev = to_pci_dev(dev->dev);
2893
a1f447b3 2894 if (pci_request_mem_regions(pdev, "nvme"))
b00a726a
KB		 2895 return -ENODEV;
2896
97f6ef64 2897 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
b00a726a
KB		 2898 goto release;
2899
9fa196e7 2900 return 0;
b00a726a 2901 release:
9fa196e7
MG		 2902 pci_release_mem_regions(pdev);
2903 return -ENODEV;
b00a726a
KB		 2904}
2905
8427bbc2 2906static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
ff5350a8
AL		 2907{
2908 if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
2909 /*
2910 * Several Samsung devices seem to drop off the PCIe bus
2911 * randomly when APST is on and uses the deepest sleep state.
2912 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2913 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2914 * 950 PRO 256GB", but it seems to be restricted to two Dell
2915 * laptops.
2916 */
2917 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
2918 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
2919 dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
2920 return NVME_QUIRK_NO_DEEPEST_PS;
8427bbc2
KHF		 2921 } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
2922 /*
2923 * Samsung SSD 960 EVO drops off the PCIe bus after system
467c77d4
JJ		 2924 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
2925 * within few minutes after bootup on a Coffee Lake board -
2926 * ASUS PRIME Z370-A
8427bbc2
KHF		 2927 */
2928 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
467c77d4
JJ		 2929 (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") ||
2930 dmi_match(DMI_BOARD_NAME, "PRIME Z370-A")))
8427bbc2 2931 return NVME_QUIRK_NO_APST;
1fae37ac
S		 2932 } else if ((pdev->vendor == 0x144d && (pdev->device == 0xa801 ||
2933 pdev->device == 0xa808 || pdev->device == 0xa809)) ||
2934 (pdev->vendor == 0x1e0f && pdev->device == 0x0001)) {
2935 /*
2936 * Forcing to use host managed nvme power settings for
2937 * lowest idle power with quick resume latency on
2938 * Samsung and Toshiba SSDs based on suspend behavior
2939 * on Coffee Lake board for LENOVO C640
2940 */
2941 if ((dmi_match(DMI_BOARD_VENDOR, "LENOVO")) &&
2942 dmi_match(DMI_BOARD_NAME, "LNVNB161216"))
2943 return NVME_QUIRK_SIMPLE_SUSPEND;
ff5350a8
AL		 2944 }
2945
2946 return 0;
2947}
2948
18119775
KB		 2949static void nvme_async_probe(void *data, async_cookie_t cookie)
2950{
2951 struct nvme_dev *dev = data;
80f513b5 2952
bd46a906 2953 flush_work(&dev->ctrl.reset_work);
18119775 2954 flush_work(&dev->ctrl.scan_work);
80f513b5 2955 nvme_put_ctrl(&dev->ctrl);
18119775
KB		 2956}
2957
8d85fce7 2958static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
b60503ba 2959{
a4aea562 2960 int node, result = -ENOMEM;
b60503ba 2961 struct nvme_dev *dev;
ff5350a8 2962 unsigned long quirks = id->driver_data;
943e942e 2963 size_t alloc_size;
b60503ba 2964
a4aea562
MB		 2965 node = dev_to_node(&pdev->dev);
2966 if (node == NUMA_NO_NODE)
2fa84351 2967 set_dev_node(&pdev->dev, first_memory_node);
a4aea562
MB		 2968
2969 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
b60503ba
MW		 2970 if (!dev)
2971 return -ENOMEM;
147b27e4 2972
2a5bcfdd
WZ		 2973 dev->nr_write_queues = write_queues;
2974 dev->nr_poll_queues = poll_queues;
2975 dev->nr_allocated_queues = nvme_max_io_queues(dev) + 1;
2976 dev->queues = kcalloc_node(dev->nr_allocated_queues,
2977 sizeof(struct nvme_queue), GFP_KERNEL, node);
b60503ba
MW		 2978 if (!dev->queues)
2979 goto free;
2980
e75ec752 2981 dev->dev = get_device(&pdev->dev);
9a6b9458 2982 pci_set_drvdata(pdev, dev);
1c63dc66 2983
b00a726a
KB		 2984 result = nvme_dev_map(dev);
2985 if (result)
b00c9b7a 2986 goto put_pci;
b00a726a 2987
d86c4d8e 2988 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
5c8809e6 2989 INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
77bf25ea 2990 mutex_init(&dev->shutdown_lock);
b60503ba 2991
091b6092
MW		 2992 result = nvme_setup_prp_pools(dev);
2993 if (result)
b00c9b7a 2994 goto unmap;
4cc06521 2995
8427bbc2 2996 quirks |= check_vendor_combination_bug(pdev);
ff5350a8 2997
2744d7a0 2998 if (!noacpi && acpi_storage_d3(&pdev->dev)) {
df4f9bc4
DB		 2999 /*
3000 * Some systems use a bios work around to ask for D3 on
3001 * platforms that support kernel managed suspend.
3002 */
3003 dev_info(&pdev->dev,
3004 "platform quirk: setting simple suspend\n");
3005 quirks |= NVME_QUIRK_SIMPLE_SUSPEND;
3006 }
3007
943e942e
JA		 3008 /*
3009 * Double check that our mempool alloc size will cover the biggest
3010 * command we support.
3011 */
b13c6393 3012 alloc_size = nvme_pci_iod_alloc_size();
943e942e
JA		 3013 WARN_ON_ONCE(alloc_size > PAGE_SIZE);
3014
3015 dev->iod_mempool = mempool_create_node(1, mempool_kmalloc,
3016 mempool_kfree,
3017 (void *) alloc_size,
3018 GFP_KERNEL, node);
3019 if (!dev->iod_mempool) {
3020 result = -ENOMEM;
3021 goto release_pools;
3022 }
3023
b6e44b4c
KB		 3024 result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
3025 quirks);
3026 if (result)
3027 goto release_mempool;
3028
1b3c47c1
SG		 3029 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
3030
bd46a906 3031 nvme_reset_ctrl(&dev->ctrl);
18119775 3032 async_schedule(nvme_async_probe, dev);
4caff8fc 3033
b60503ba
MW		 3034 return 0;
3035
b6e44b4c
KB		 3036 release_mempool:
3037 mempool_destroy(dev->iod_mempool);
0877cb0d 3038 release_pools:
091b6092 3039 nvme_release_prp_pools(dev);
b00c9b7a
CJ		 3040 unmap:
3041 nvme_dev_unmap(dev);
a96d4f5c 3042 put_pci:
e75ec752 3043 put_device(dev->dev);
b60503ba
MW		 3044 free:
3045 kfree(dev->queues);
b60503ba
MW		 3046 kfree(dev);
3047 return result;
3048}
3049
775755ed 3050static void nvme_reset_prepare(struct pci_dev *pdev)
f0d54a54 3051{
a6739479 3052 struct nvme_dev *dev = pci_get_drvdata(pdev);
c1ac9a4b
KB		 3053
3054 /*
3055 * We don't need to check the return value from waiting for the reset
3056 * state as pci_dev device lock is held, making it impossible to race
3057 * with ->remove().
3058 */
3059 nvme_disable_prepare_reset(dev, false);
3060 nvme_sync_queues(&dev->ctrl);
775755ed 3061}
f0d54a54 3062
775755ed
CH		 3063static void nvme_reset_done(struct pci_dev *pdev)
3064{
f263fbb8 3065 struct nvme_dev *dev = pci_get_drvdata(pdev);
c1ac9a4b
KB		 3066
3067 if (!nvme_try_sched_reset(&dev->ctrl))
3068 flush_work(&dev->ctrl.reset_work);
f0d54a54
KB		 3069}
3070
09ece142
KB		 3071static void nvme_shutdown(struct pci_dev *pdev)
3072{
3073 struct nvme_dev *dev = pci_get_drvdata(pdev);
4e523547 3074
c1ac9a4b 3075 nvme_disable_prepare_reset(dev, true);
09ece142
KB		 3076}
3077
0521905e
KB		 3078static void nvme_remove_attrs(struct nvme_dev *dev)
3079{
3080 if (dev->attrs_added)
3081 sysfs_remove_group(&dev->ctrl.device->kobj,
3082 &nvme_pci_attr_group);
3083}
3084
f58944e2
KB		 3085/*
3086 * The driver's remove may be called on a device in a partially initialized
3087 * state. This function must not have any dependencies on the device state in
3088 * order to proceed.
3089 */
8d85fce7 3090static void nvme_remove(struct pci_dev *pdev)
b60503ba
MW		 3091{
3092 struct nvme_dev *dev = pci_get_drvdata(pdev);
9a6b9458 3093
bb8d261e 3094 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
9a6b9458 3095 pci_set_drvdata(pdev, NULL);
0ff9d4e1 3096
6db28eda 3097 if (!pci_device_is_present(pdev)) {
0ff9d4e1 3098 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
1d39e692 3099 nvme_dev_disable(dev, true);
6db28eda 3100 }
0ff9d4e1 3101
d86c4d8e 3102 flush_work(&dev->ctrl.reset_work);
d09f2b45
SG		 3103 nvme_stop_ctrl(&dev->ctrl);
3104 nvme_remove_namespaces(&dev->ctrl);
a5cdb68c 3105 nvme_dev_disable(dev, true);
0521905e 3106 nvme_remove_attrs(dev);
87ad72a5 3107 nvme_free_host_mem(dev);
a4aea562 3108 nvme_dev_remove_admin(dev);
a1a5ef99 3109 nvme_free_queues(dev, 0);
9a6b9458 3110 nvme_release_prp_pools(dev);
b00a726a 3111 nvme_dev_unmap(dev);
726612b6 3112 nvme_uninit_ctrl(&dev->ctrl);
b60503ba
MW		 3113}
3114
671a6018 3115#ifdef CONFIG_PM_SLEEP
d916b1be
KB		 3116static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps)
3117{
3118 return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps);
3119}
3120
3121static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps)
3122{
3123 return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL);
3124}
3125
3126static int nvme_resume(struct device *dev)
3127{
3128 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
3129 struct nvme_ctrl *ctrl = &ndev->ctrl;
3130
4eaefe8c 3131 if (ndev->last_ps == U32_MAX ||
d916b1be 3132 nvme_set_power_state(ctrl, ndev->last_ps) != 0)
e5ad96f3
KB		 3133 goto reset;
3134 if (ctrl->hmpre && nvme_setup_host_mem(ndev))
3135 goto reset;
3136
d916b1be 3137 return 0;
e5ad96f3
KB		 3138reset:
3139 return nvme_try_sched_reset(ctrl);
d916b1be
KB		 3140}
3141
cd638946
KB		 3142static int nvme_suspend(struct device *dev)
3143{
3144 struct pci_dev *pdev = to_pci_dev(dev);
3145 struct nvme_dev *ndev = pci_get_drvdata(pdev);
d916b1be
KB		 3146 struct nvme_ctrl *ctrl = &ndev->ctrl;
3147 int ret = -EBUSY;
3148
4eaefe8c
RW		 3149 ndev->last_ps = U32_MAX;
3150
d916b1be
KB		 3151 /*
3152 * The platform does not remove power for a kernel managed suspend so
3153 * use host managed nvme power settings for lowest idle power if
3154 * possible. This should have quicker resume latency than a full device
3155 * shutdown. But if the firmware is involved after the suspend or the
3156 * device does not support any non-default power states, shut down the
3157 * device fully.
4eaefe8c
RW		 3158 *
3159 * If ASPM is not enabled for the device, shut down the device and allow
3160 * the PCI bus layer to put it into D3 in order to take the PCIe link
3161 * down, so as to allow the platform to achieve its minimum low-power
3162 * state (which may not be possible if the link is up).
d916b1be 3163 */
4eaefe8c 3164 if (pm_suspend_via_firmware() || !ctrl->npss ||
cb32de1b 3165 !pcie_aspm_enabled(pdev) ||
c1ac9a4b
KB		 3166 (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND))
3167 return nvme_disable_prepare_reset(ndev, true);
d916b1be
KB		 3168
3169 nvme_start_freeze(ctrl);
3170 nvme_wait_freeze(ctrl);
3171 nvme_sync_queues(ctrl);
3172
5d02a5c1 3173 if (ctrl->state != NVME_CTRL_LIVE)
d916b1be
KB		 3174 goto unfreeze;
3175
e5ad96f3
KB		 3176 /*
3177 * Host memory access may not be successful in a system suspend state,
3178 * but the specification allows the controller to access memory in a
3179 * non-operational power state.
3180 */
3181 if (ndev->hmb) {
3182 ret = nvme_set_host_mem(ndev, 0);
3183 if (ret < 0)
3184 goto unfreeze;
3185 }
3186
d916b1be
KB		 3187 ret = nvme_get_power_state(ctrl, &ndev->last_ps);
3188 if (ret < 0)
3189 goto unfreeze;
3190
7cbb5c6f
ML		 3191 /*
3192 * A saved state prevents pci pm from generically controlling the
3193 * device's power. If we're using protocol specific settings, we don't
3194 * want pci interfering.
3195 */
3196 pci_save_state(pdev);
3197
d916b1be
KB		 3198 ret = nvme_set_power_state(ctrl, ctrl->npss);
3199 if (ret < 0)
3200 goto unfreeze;
3201
3202 if (ret) {
7cbb5c6f
ML		 3203 /* discard the saved state */
3204 pci_load_saved_state(pdev, NULL);
3205
d916b1be
KB		 3206 /*
3207 * Clearing npss forces a controller reset on resume. The
05d3046f 3208 * correct value will be rediscovered then.
d916b1be 3209 */
c1ac9a4b 3210 ret = nvme_disable_prepare_reset(ndev, true);
d916b1be 3211 ctrl->npss = 0;
d916b1be 3212 }
d916b1be
KB		 3213unfreeze:
3214 nvme_unfreeze(ctrl);
3215 return ret;
3216}
3217
3218static int nvme_simple_suspend(struct device *dev)
3219{
3220 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
4e523547 3221
c1ac9a4b 3222 return nvme_disable_prepare_reset(ndev, true);
cd638946
KB		 3223}
3224
d916b1be 3225static int nvme_simple_resume(struct device *dev)
cd638946
KB		 3226{
3227 struct pci_dev *pdev = to_pci_dev(dev);
3228 struct nvme_dev *ndev = pci_get_drvdata(pdev);
cd638946 3229
c1ac9a4b 3230 return nvme_try_sched_reset(&ndev->ctrl);
cd638946
KB		 3231}
3232
21774222 3233static const struct dev_pm_ops nvme_dev_pm_ops = {
d916b1be
KB		 3234 .suspend = nvme_suspend,
3235 .resume = nvme_resume,
3236 .freeze = nvme_simple_suspend,
3237 .thaw = nvme_simple_resume,
3238 .poweroff = nvme_simple_suspend,
3239 .restore = nvme_simple_resume,
3240};
3241#endif /* CONFIG_PM_SLEEP */
b60503ba 3242
a0a3408e
KB		 3243static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
3244 pci_channel_state_t state)
3245{
3246 struct nvme_dev *dev = pci_get_drvdata(pdev);
3247
3248 /*
3249 * A frozen channel requires a reset. When detected, this method will
3250 * shutdown the controller to quiesce. The controller will be restarted
3251 * after the slot reset through driver's slot_reset callback.
3252 */
a0a3408e
KB		 3253 switch (state) {
3254 case pci_channel_io_normal:
3255 return PCI_ERS_RESULT_CAN_RECOVER;
3256 case pci_channel_io_frozen:
d011fb31
KB		 3257 dev_warn(dev->ctrl.device,
3258 "frozen state error detected, reset controller\n");
a5cdb68c 3259 nvme_dev_disable(dev, false);
a0a3408e
KB		 3260 return PCI_ERS_RESULT_NEED_RESET;
3261 case pci_channel_io_perm_failure:
d011fb31
KB		 3262 dev_warn(dev->ctrl.device,
3263 "failure state error detected, request disconnect\n");
a0a3408e
KB		 3264 return PCI_ERS_RESULT_DISCONNECT;
3265 }
3266 return PCI_ERS_RESULT_NEED_RESET;
3267}
3268
3269static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
3270{
3271 struct nvme_dev *dev = pci_get_drvdata(pdev);
3272
1b3c47c1 3273 dev_info(dev->ctrl.device, "restart after slot reset\n");
a0a3408e 3274 pci_restore_state(pdev);
d86c4d8e 3275 nvme_reset_ctrl(&dev->ctrl);
a0a3408e
KB		 3276 return PCI_ERS_RESULT_RECOVERED;
3277}
3278
3279static void nvme_error_resume(struct pci_dev *pdev)
3280{
72cd4cc2
KB		 3281 struct nvme_dev *dev = pci_get_drvdata(pdev);
3282
3283 flush_work(&dev->ctrl.reset_work);
a0a3408e
KB		 3284}
3285
1d352035 3286static const struct pci_error_handlers nvme_err_handler = {
b60503ba 3287 .error_detected = nvme_error_detected,
b60503ba
MW		 3288 .slot_reset = nvme_slot_reset,
3289 .resume = nvme_error_resume,
775755ed
CH		 3290 .reset_prepare = nvme_reset_prepare,
3291 .reset_done = nvme_reset_done,
b60503ba
MW		 3292};
3293
6eb0d698 3294static const struct pci_device_id nvme_id_table[] = {
972b13e2 3295 { PCI_VDEVICE(INTEL, 0x0953), /* Intel 750/P3500/P3600/P3700 */
08095e70 3296 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 3297 NVME_QUIRK_DEALLOCATE_ZEROES, },
972b13e2 3298 { PCI_VDEVICE(INTEL, 0x0a53), /* Intel P3520 */
99466e70 3299 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 3300 NVME_QUIRK_DEALLOCATE_ZEROES, },
972b13e2 3301 { PCI_VDEVICE(INTEL, 0x0a54), /* Intel P4500/P4600 */
99466e70 3302 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 3303 NVME_QUIRK_DEALLOCATE_ZEROES, },
972b13e2 3304 { PCI_VDEVICE(INTEL, 0x0a55), /* Dell Express Flash P4600 */
f99cb7af
DWF		 3305 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3306 NVME_QUIRK_DEALLOCATE_ZEROES, },
50af47d0 3307 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */
9abd68ef 3308 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
6c6aa2f2 3309 NVME_QUIRK_MEDIUM_PRIO_SQ |
ce4cc313
DM		 3310 NVME_QUIRK_NO_TEMP_THRESH_CHANGE |
3311 NVME_QUIRK_DISABLE_WRITE_ZEROES, },
6299358d
JD		 3312 { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */
3313 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
540c801c 3314 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */
7b210e4e
CH		 3315 .driver_data = NVME_QUIRK_IDENTIFY_CNS |
3316 NVME_QUIRK_DISABLE_WRITE_ZEROES, },
5bedd3af
CH		 3317 { PCI_DEVICE(0x126f, 0x2263), /* Silicon Motion unidentified */
3318 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST, },
0302ae60 3319 { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */
5e112d3f
JE		 3320 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
3321 NVME_QUIRK_NO_NS_DESC_LIST, },
54adc010
GP		 3322 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
3323 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
8c97eecc
JL		 3324 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */
3325 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
015282c9
WW		 3326 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
3327 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
d554b5e1
MP		 3328 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */
3329 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3330 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */
7ee5c78c 3331 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
abbb5f59 3332 NVME_QUIRK_DISABLE_WRITE_ZEROES|
7ee5c78c 3333 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
c9e95c39
CS		 3334 { PCI_DEVICE(0x1987, 0x5016), /* Phison E16 */
3335 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
6e6a6828
PT		 3336 { PCI_DEVICE(0x1b4b, 0x1092), /* Lexar 256 GB SSD */
3337 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST |
3338 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
08b903b5
MN		 3339 { PCI_DEVICE(0x10ec, 0x5762), /* ADATA SX6000LNP */
3340 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
f03e42c6
GC		 3341 { PCI_DEVICE(0x1cc1, 0x8201), /* ADATA SX8200PNP 512GB */
3342 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3343 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
5611ec2b
KHF		 3344 { PCI_DEVICE(0x1c5c, 0x1504), /* SK Hynix PC400 */
3345 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
02ca079c
KHF		 3346 { PCI_DEVICE(0x15b7, 0x2001), /* Sandisk Skyhawk */
3347 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
89919929
CK		 3348 { PCI_DEVICE(0x1d97, 0x2263), /* SPCC */
3349 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
dc22c1c0
ZB		 3350 { PCI_DEVICE(0x2646, 0x2262), /* KINGSTON SKC2000 NVMe SSD */
3351 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
538e4a8c
TL		 3352 { PCI_DEVICE(0x2646, 0x2263), /* KINGSTON A2000 NVMe SSD */
3353 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
4bdf2603
FS		 3354 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0061),
3355 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3356 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0065),
3357 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3358 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x8061),
3359 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3360 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd00),
3361 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3362 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd01),
3363 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3364 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd02),
3365 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
98f7b86a
AS		 3366 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001),
3367 .driver_data = NVME_QUIRK_SINGLE_VECTOR },
124298bd 3368 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
66341331
BH		 3369 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005),
3370 .driver_data = NVME_QUIRK_SINGLE_VECTOR |
d38e9f04
BH		 3371 NVME_QUIRK_128_BYTES_SQES |
3372 NVME_QUIRK_SHARED_TAGS },
0b85f59d
AS		 3373
3374 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
b60503ba
MW		 3375 { 0, }
3376};
3377MODULE_DEVICE_TABLE(pci, nvme_id_table);
3378
3379static struct pci_driver nvme_driver = {
3380 .name = "nvme",
3381 .id_table = nvme_id_table,
3382 .probe = nvme_probe,
8d85fce7 3383 .remove = nvme_remove,
09ece142 3384 .shutdown = nvme_shutdown,
d916b1be 3385#ifdef CONFIG_PM_SLEEP
cd638946
KB		 3386 .driver = {
3387 .pm = &nvme_dev_pm_ops,
3388 },
d916b1be 3389#endif
74d986ab 3390 .sriov_configure = pci_sriov_configure_simple,
b60503ba
MW		 3391 .err_handler = &nvme_err_handler,
3392};
3393
3394static int __init nvme_init(void)
3395{
81101540
CH		 3396 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
3397 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
3398 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
612b7286 3399 BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2);
17c33167 3400
9a6327d2 3401 return pci_register_driver(&nvme_driver);
b60503ba
MW		 3402}
3403
3404static void __exit nvme_exit(void)
3405{
3406 pci_unregister_driver(&nvme_driver);
03e0f3a6 3407 flush_workqueue(nvme_wq);
b60503ba
MW		 3408}
3409
3410MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3411MODULE_LICENSE("GPL");
c78b4713 3412MODULE_VERSION("1.0");
b60503ba
MW		 3413module_init(nvme_init);
3414module_exit(nvme_exit);
Linux 6.x block layer and io_uring tree(s)