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nvme-pci: optimize mapping single segment requests using SGLs
[linux-2.6-block.git] / drivers / nvme / host / pci.c
CommitLineData
5f37396d 1// SPDX-License-Identifier: GPL-2.0
b60503ba
MW		 2/*
3 * NVM Express device driver
6eb0d698 4 * Copyright (c) 2011-2014, Intel Corporation.
b60503ba
MW		 5 */
6
a0a3408e 7#include <linux/aer.h>
18119775 8#include <linux/async.h>
b60503ba 9#include <linux/blkdev.h>
a4aea562 10#include <linux/blk-mq.h>
dca51e78 11#include <linux/blk-mq-pci.h>
ff5350a8 12#include <linux/dmi.h>
b60503ba
MW		 13#include <linux/init.h>
14#include <linux/interrupt.h>
15#include <linux/io.h>
b60503ba
MW		 16#include <linux/mm.h>
17#include <linux/module.h>
77bf25ea 18#include <linux/mutex.h>
d0877473 19#include <linux/once.h>
b60503ba 20#include <linux/pci.h>
e1e5e564 21#include <linux/t10-pi.h>
b60503ba 22#include <linux/types.h>
2f8e2c87 23#include <linux/io-64-nonatomic-lo-hi.h>
a98e58e5 24#include <linux/sed-opal.h>
0f238ff5 25#include <linux/pci-p2pdma.h>
797a796a 26
604c01d5 27#include "trace.h"
f11bb3e2
CH		 28#include "nvme.h"
29
b60503ba
MW		 30#define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
31#define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
c965809c 32
a7a7cbe3 33#define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc))
9d43cf64 34
943e942e
JA		 35/*
36 * These can be higher, but we need to ensure that any command doesn't
37 * require an sg allocation that needs more than a page of data.
38 */
39#define NVME_MAX_KB_SZ 4096
40#define NVME_MAX_SEGS 127
41
58ffacb5
MW		 42static int use_threaded_interrupts;
43module_param(use_threaded_interrupts, int, 0);
44
8ffaadf7 45static bool use_cmb_sqes = true;
69f4eb9f 46module_param(use_cmb_sqes, bool, 0444);
8ffaadf7
JD		 47MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
48
87ad72a5
CH		 49static unsigned int max_host_mem_size_mb = 128;
50module_param(max_host_mem_size_mb, uint, 0444);
51MODULE_PARM_DESC(max_host_mem_size_mb,
52 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
1fa6aead 53
a7a7cbe3
CK		 54static unsigned int sgl_threshold = SZ_32K;
55module_param(sgl_threshold, uint, 0644);
56MODULE_PARM_DESC(sgl_threshold,
57 "Use SGLs when average request segment size is larger or equal to "
58 "this size. Use 0 to disable SGLs.");
59
b27c1e68 60static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
61static const struct kernel_param_ops io_queue_depth_ops = {
62 .set = io_queue_depth_set,
63 .get = param_get_int,
64};
65
66static int io_queue_depth = 1024;
67module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
68MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2");
69
3b6592f7
JA		 70static int queue_count_set(const char *val, const struct kernel_param *kp);
71static const struct kernel_param_ops queue_count_ops = {
72 .set = queue_count_set,
73 .get = param_get_int,
74};
75
76static int write_queues;
77module_param_cb(write_queues, &queue_count_ops, &write_queues, 0644);
78MODULE_PARM_DESC(write_queues,
79 "Number of queues to use for writes. If not set, reads and writes "
80 "will share a queue set.");
81
a4668d9b 82static int poll_queues = 0;
4b04cc6a
JA		 83module_param_cb(poll_queues, &queue_count_ops, &poll_queues, 0644);
84MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO.");
85
1c63dc66
CH		 86struct nvme_dev;
87struct nvme_queue;
b3fffdef 88
a5cdb68c 89static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
8fae268b 90static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode);
d4b4ff8e 91
1c63dc66
CH		 92/*
93 * Represents an NVM Express device. Each nvme_dev is a PCI function.
94 */
95struct nvme_dev {
147b27e4 96 struct nvme_queue *queues;
1c63dc66
CH		 97 struct blk_mq_tag_set tagset;
98 struct blk_mq_tag_set admin_tagset;
99 u32 __iomem *dbs;
100 struct device *dev;
101 struct dma_pool *prp_page_pool;
102 struct dma_pool *prp_small_pool;
1c63dc66
CH		 103 unsigned online_queues;
104 unsigned max_qid;
e20ba6e1 105 unsigned io_queues[HCTX_MAX_TYPES];
22b55601 106 unsigned int num_vecs;
1c63dc66
CH		 107 int q_depth;
108 u32 db_stride;
1c63dc66 109 void __iomem *bar;
97f6ef64 110 unsigned long bar_mapped_size;
5c8809e6 111 struct work_struct remove_work;
77bf25ea 112 struct mutex shutdown_lock;
1c63dc66 113 bool subsystem;
1c63dc66 114 u64 cmb_size;
0f238ff5 115 bool cmb_use_sqes;
1c63dc66 116 u32 cmbsz;
202021c1 117 u32 cmbloc;
1c63dc66 118 struct nvme_ctrl ctrl;
87ad72a5 119
943e942e
JA		 120 mempool_t *iod_mempool;
121
87ad72a5 122 /* shadow doorbell buffer support: */
f9f38e33
HK		 123 u32 *dbbuf_dbs;
124 dma_addr_t dbbuf_dbs_dma_addr;
125 u32 *dbbuf_eis;
126 dma_addr_t dbbuf_eis_dma_addr;
87ad72a5
CH		 127
128 /* host memory buffer support: */
129 u64 host_mem_size;
130 u32 nr_host_mem_descs;
4033f35d 131 dma_addr_t host_mem_descs_dma;
87ad72a5
CH		 132 struct nvme_host_mem_buf_desc *host_mem_descs;
133 void **host_mem_desc_bufs;
4d115420 134};
1fa6aead 135
b27c1e68 136static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
137{
138 int n = 0, ret;
139
140 ret = kstrtoint(val, 10, &n);
141 if (ret != 0 || n < 2)
142 return -EINVAL;
143
144 return param_set_int(val, kp);
145}
146
3b6592f7
JA		 147static int queue_count_set(const char *val, const struct kernel_param *kp)
148{
149 int n = 0, ret;
150
151 ret = kstrtoint(val, 10, &n);
e895fedf
BVA		 152 if (ret)
153 return ret;
3b6592f7
JA		 154 if (n > num_possible_cpus())
155 n = num_possible_cpus();
156
157 return param_set_int(val, kp);
158}
159
f9f38e33
HK		 160static inline unsigned int sq_idx(unsigned int qid, u32 stride)
161{
162 return qid * 2 * stride;
163}
164
165static inline unsigned int cq_idx(unsigned int qid, u32 stride)
166{
167 return (qid * 2 + 1) * stride;
168}
169
1c63dc66
CH		 170static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
171{
172 return container_of(ctrl, struct nvme_dev, ctrl);
173}
174
b60503ba
MW		 175/*
176 * An NVM Express queue. Each device has at least two (one for admin
177 * commands and one for I/O commands).
178 */
179struct nvme_queue {
091b6092 180 struct nvme_dev *dev;
1ab0cd69 181 spinlock_t sq_lock;
b60503ba 182 struct nvme_command *sq_cmds;
3a7afd8e
CH		 183 /* only used for poll queues: */
184 spinlock_t cq_poll_lock ____cacheline_aligned_in_smp;
b60503ba 185 volatile struct nvme_completion *cqes;
42483228 186 struct blk_mq_tags **tags;
b60503ba
MW		 187 dma_addr_t sq_dma_addr;
188 dma_addr_t cq_dma_addr;
b60503ba
MW		 189 u32 __iomem *q_db;
190 u16 q_depth;
7c349dde 191 u16 cq_vector;
b60503ba 192 u16 sq_tail;
04f3eafd 193 u16 last_sq_tail;
b60503ba 194 u16 cq_head;
68fa9dbe 195 u16 last_cq_head;
c30341dc 196 u16 qid;
e9539f47 197 u8 cq_phase;
4e224106
CH		 198 unsigned long flags;
199#define NVMEQ_ENABLED 0
63223078 200#define NVMEQ_SQ_CMB 1
d1ed6aa1 201#define NVMEQ_DELETE_ERROR 2
7c349dde 202#define NVMEQ_POLLED 3
f9f38e33
HK		 203 u32 *dbbuf_sq_db;
204 u32 *dbbuf_cq_db;
205 u32 *dbbuf_sq_ei;
206 u32 *dbbuf_cq_ei;
d1ed6aa1 207 struct completion delete_done;
b60503ba
MW		 208};
209
71bd150c 210/*
9b048119
CH		 211 * The nvme_iod describes the data in an I/O.
212 *
213 * The sg pointer contains the list of PRP/SGL chunk allocations in addition
214 * to the actual struct scatterlist.
71bd150c
CH		 215 */
216struct nvme_iod {
d49187e9 217 struct nvme_request req;
f4800d6d 218 struct nvme_queue *nvmeq;
a7a7cbe3 219 bool use_sgl;
f4800d6d 220 int aborted;
71bd150c 221 int npages; /* In the PRP list. 0 means small pool in use */
71bd150c 222 int nents; /* Used in scatterlist */
71bd150c 223 dma_addr_t first_dma;
dff824b2 224 unsigned int dma_len; /* length of single DMA segment mapping */
783b94bd 225 dma_addr_t meta_dma;
f4800d6d 226 struct scatterlist *sg;
b60503ba
MW		 227};
228
229/*
230 * Check we didin't inadvertently grow the command struct
231 */
232static inline void _nvme_check_size(void)
233{
234 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
235 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
236 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
237 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
238 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
f8ebf840 239 BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
c30341dc 240 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
b60503ba 241 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
0add5e8e
JT		 242 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != NVME_IDENTIFY_DATA_SIZE);
243 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != NVME_IDENTIFY_DATA_SIZE);
b60503ba 244 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
6ecec745 245 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
f9f38e33
HK		 246 BUILD_BUG_ON(sizeof(struct nvme_dbbuf) != 64);
247}
248
3b6592f7
JA		 249static unsigned int max_io_queues(void)
250{
4b04cc6a 251 return num_possible_cpus() + write_queues + poll_queues;
3b6592f7
JA		 252}
253
254static unsigned int max_queue_count(void)
255{
256 /* IO queues + admin queue */
257 return 1 + max_io_queues();
258}
259
f9f38e33
HK		 260static inline unsigned int nvme_dbbuf_size(u32 stride)
261{
3b6592f7 262 return (max_queue_count() * 8 * stride);
f9f38e33
HK		 263}
264
265static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
266{
267 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
268
269 if (dev->dbbuf_dbs)
270 return 0;
271
272 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
273 &dev->dbbuf_dbs_dma_addr,
274 GFP_KERNEL);
275 if (!dev->dbbuf_dbs)
276 return -ENOMEM;
277 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
278 &dev->dbbuf_eis_dma_addr,
279 GFP_KERNEL);
280 if (!dev->dbbuf_eis) {
281 dma_free_coherent(dev->dev, mem_size,
282 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
283 dev->dbbuf_dbs = NULL;
284 return -ENOMEM;
285 }
286
287 return 0;
288}
289
290static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
291{
292 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
293
294 if (dev->dbbuf_dbs) {
295 dma_free_coherent(dev->dev, mem_size,
296 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
297 dev->dbbuf_dbs = NULL;
298 }
299 if (dev->dbbuf_eis) {
300 dma_free_coherent(dev->dev, mem_size,
301 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
302 dev->dbbuf_eis = NULL;
303 }
304}
305
306static void nvme_dbbuf_init(struct nvme_dev *dev,
307 struct nvme_queue *nvmeq, int qid)
308{
309 if (!dev->dbbuf_dbs || !qid)
310 return;
311
312 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
313 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
314 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
315 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
316}
317
318static void nvme_dbbuf_set(struct nvme_dev *dev)
319{
320 struct nvme_command c;
321
322 if (!dev->dbbuf_dbs)
323 return;
324
325 memset(&c, 0, sizeof(c));
326 c.dbbuf.opcode = nvme_admin_dbbuf;
327 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
328 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
329
330 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
9bdcfb10 331 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
f9f38e33
HK		 332 /* Free memory and continue on */
333 nvme_dbbuf_dma_free(dev);
334 }
335}
336
337static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
338{
339 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
340}
341
342/* Update dbbuf and return true if an MMIO is required */
343static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
344 volatile u32 *dbbuf_ei)
345{
346 if (dbbuf_db) {
347 u16 old_value;
348
349 /*
350 * Ensure that the queue is written before updating
351 * the doorbell in memory
352 */
353 wmb();
354
355 old_value = *dbbuf_db;
356 *dbbuf_db = value;
357
f1ed3df2
MW		 358 /*
359 * Ensure that the doorbell is updated before reading the event
360 * index from memory. The controller needs to provide similar
361 * ordering to ensure the envent index is updated before reading
362 * the doorbell.
363 */
364 mb();
365
f9f38e33
HK		 366 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value))
367 return false;
368 }
369
370 return true;
b60503ba
MW		 371}
372
ac3dd5bd
JA		 373/*
374 * Will slightly overestimate the number of pages needed. This is OK
375 * as it only leads to a small amount of wasted memory for the lifetime of
376 * the I/O.
377 */
378static int nvme_npages(unsigned size, struct nvme_dev *dev)
379{
5fd4ce1b
CH		 380 unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size,
381 dev->ctrl.page_size);
ac3dd5bd
JA		 382 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
383}
384
a7a7cbe3
CK		 385/*
386 * Calculates the number of pages needed for the SGL segments. For example a 4k
387 * page can accommodate 256 SGL descriptors.
388 */
389static int nvme_pci_npages_sgl(unsigned int num_seg)
ac3dd5bd 390{
a7a7cbe3 391 return DIV_ROUND_UP(num_seg * sizeof(struct nvme_sgl_desc), PAGE_SIZE);
f4800d6d 392}
ac3dd5bd 393
a7a7cbe3
CK		 394static unsigned int nvme_pci_iod_alloc_size(struct nvme_dev *dev,
395 unsigned int size, unsigned int nseg, bool use_sgl)
f4800d6d 396{
a7a7cbe3
CK		 397 size_t alloc_size;
398
399 if (use_sgl)
400 alloc_size = sizeof(__le64 *) * nvme_pci_npages_sgl(nseg);
401 else
402 alloc_size = sizeof(__le64 *) * nvme_npages(size, dev);
403
404 return alloc_size + sizeof(struct scatterlist) * nseg;
f4800d6d 405}
ac3dd5bd 406
a4aea562
MB		 407static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
408 unsigned int hctx_idx)
e85248e5 409{
a4aea562 410 struct nvme_dev *dev = data;
147b27e4 411 struct nvme_queue *nvmeq = &dev->queues[0];
a4aea562 412
42483228
KB		 413 WARN_ON(hctx_idx != 0);
414 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
415 WARN_ON(nvmeq->tags);
416
a4aea562 417 hctx->driver_data = nvmeq;
42483228 418 nvmeq->tags = &dev->admin_tagset.tags[0];
a4aea562 419 return 0;
e85248e5
MW		 420}
421
4af0e21c
KB		 422static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
423{
424 struct nvme_queue *nvmeq = hctx->driver_data;
425
426 nvmeq->tags = NULL;
427}
428
a4aea562
MB		 429static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
430 unsigned int hctx_idx)
b60503ba 431{
a4aea562 432 struct nvme_dev *dev = data;
147b27e4 433 struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
a4aea562 434
42483228
KB		 435 if (!nvmeq->tags)
436 nvmeq->tags = &dev->tagset.tags[hctx_idx];
b60503ba 437
42483228 438 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
a4aea562
MB		 439 hctx->driver_data = nvmeq;
440 return 0;
b60503ba
MW		 441}
442
d6296d39
CH		 443static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req,
444 unsigned int hctx_idx, unsigned int numa_node)
b60503ba 445{
d6296d39 446 struct nvme_dev *dev = set->driver_data;
f4800d6d 447 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
0350815a 448 int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0;
147b27e4 449 struct nvme_queue *nvmeq = &dev->queues[queue_idx];
a4aea562
MB		 450
451 BUG_ON(!nvmeq);
f4800d6d 452 iod->nvmeq = nvmeq;
59e29ce6
SG		 453
454 nvme_req(req)->ctrl = &dev->ctrl;
a4aea562
MB		 455 return 0;
456}
457
3b6592f7
JA		 458static int queue_irq_offset(struct nvme_dev *dev)
459{
460 /* if we have more than 1 vec, admin queue offsets us by 1 */
461 if (dev->num_vecs > 1)
462 return 1;
463
464 return 0;
465}
466
dca51e78
CH		 467static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
468{
469 struct nvme_dev *dev = set->driver_data;
3b6592f7
JA		 470 int i, qoff, offset;
471
472 offset = queue_irq_offset(dev);
473 for (i = 0, qoff = 0; i < set->nr_maps; i++) {
474 struct blk_mq_queue_map *map = &set->map[i];
475
476 map->nr_queues = dev->io_queues[i];
477 if (!map->nr_queues) {
e20ba6e1 478 BUG_ON(i == HCTX_TYPE_DEFAULT);
7e849dd9 479 continue;
3b6592f7
JA		 480 }
481
4b04cc6a
JA		 482 /*
483 * The poll queue(s) doesn't have an IRQ (and hence IRQ
484 * affinity), so use the regular blk-mq cpu mapping
485 */
3b6592f7 486 map->queue_offset = qoff;
e20ba6e1 487 if (i != HCTX_TYPE_POLL)
4b04cc6a
JA		 488 blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset);
489 else
490 blk_mq_map_queues(map);
3b6592f7
JA		 491 qoff += map->nr_queues;
492 offset += map->nr_queues;
493 }
494
495 return 0;
dca51e78
CH		 496}
497
04f3eafd
JA		 498/*
499 * Write sq tail if we are asked to, or if the next command would wrap.
500 */
501static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq)
502{
503 if (!write_sq) {
504 u16 next_tail = nvmeq->sq_tail + 1;
505
506 if (next_tail == nvmeq->q_depth)
507 next_tail = 0;
508 if (next_tail != nvmeq->last_sq_tail)
509 return;
510 }
511
512 if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail,
513 nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei))
514 writel(nvmeq->sq_tail, nvmeq->q_db);
515 nvmeq->last_sq_tail = nvmeq->sq_tail;
516}
517
b60503ba 518/**
90ea5ca4 519 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
b60503ba
MW		 520 * @nvmeq: The queue to use
521 * @cmd: The command to send
04f3eafd 522 * @write_sq: whether to write to the SQ doorbell
b60503ba 523 */
04f3eafd
JA		 524static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd,
525 bool write_sq)
b60503ba 526{
90ea5ca4 527 spin_lock(&nvmeq->sq_lock);
0f238ff5 528 memcpy(&nvmeq->sq_cmds[nvmeq->sq_tail], cmd, sizeof(*cmd));
90ea5ca4
CH		 529 if (++nvmeq->sq_tail == nvmeq->q_depth)
530 nvmeq->sq_tail = 0;
04f3eafd
JA		 531 nvme_write_sq_db(nvmeq, write_sq);
532 spin_unlock(&nvmeq->sq_lock);
533}
534
535static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx)
536{
537 struct nvme_queue *nvmeq = hctx->driver_data;
538
539 spin_lock(&nvmeq->sq_lock);
540 if (nvmeq->sq_tail != nvmeq->last_sq_tail)
541 nvme_write_sq_db(nvmeq, true);
90ea5ca4 542 spin_unlock(&nvmeq->sq_lock);
b60503ba
MW		 543}
544
a7a7cbe3 545static void **nvme_pci_iod_list(struct request *req)
b60503ba 546{
f4800d6d 547 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3 548 return (void **)(iod->sg + blk_rq_nr_phys_segments(req));
b60503ba
MW		 549}
550
955b1b5a
MI		 551static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req)
552{
553 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
20469a37 554 int nseg = blk_rq_nr_phys_segments(req);
955b1b5a
MI		 555 unsigned int avg_seg_size;
556
20469a37
KB		 557 if (nseg == 0)
558 return false;
559
560 avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
955b1b5a
MI		 561
562 if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1))))
563 return false;
564 if (!iod->nvmeq->qid)
565 return false;
566 if (!sgl_threshold || avg_seg_size < sgl_threshold)
567 return false;
568 return true;
569}
570
7fe07d14 571static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
b60503ba 572{
f4800d6d 573 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
7fe07d14
CH		 574 enum dma_data_direction dma_dir = rq_data_dir(req) ?
575 DMA_TO_DEVICE : DMA_FROM_DEVICE;
a7a7cbe3
CK		 576 const int last_prp = dev->ctrl.page_size / sizeof(__le64) - 1;
577 dma_addr_t dma_addr = iod->first_dma, next_dma_addr;
eca18b23 578 int i;
eca18b23 579
dff824b2
CH		 580 if (iod->dma_len) {
581 dma_unmap_page(dev->dev, dma_addr, iod->dma_len, dma_dir);
582 return;
7fe07d14
CH		 583 }
584
dff824b2
CH		 585 WARN_ON_ONCE(!iod->nents);
586
587 /* P2PDMA requests do not need to be unmapped */
588 if (!is_pci_p2pdma_page(sg_page(iod->sg)))
589 dma_unmap_sg(dev->dev, iod->sg, iod->nents, rq_dma_dir(req));
590
591
eca18b23 592 if (iod->npages == 0)
a7a7cbe3
CK		 593 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0],
594 dma_addr);
595
eca18b23 596 for (i = 0; i < iod->npages; i++) {
a7a7cbe3
CK		 597 void *addr = nvme_pci_iod_list(req)[i];
598
599 if (iod->use_sgl) {
600 struct nvme_sgl_desc *sg_list = addr;
601
602 next_dma_addr =
603 le64_to_cpu((sg_list[SGES_PER_PAGE - 1]).addr);
604 } else {
605 __le64 *prp_list = addr;
606
607 next_dma_addr = le64_to_cpu(prp_list[last_prp]);
608 }
609
610 dma_pool_free(dev->prp_page_pool, addr, dma_addr);
611 dma_addr = next_dma_addr;
eca18b23 612 }
ac3dd5bd 613
d43f1ccf 614 mempool_free(iod->sg, dev->iod_mempool);
b4ff9c8d
KB		 615}
616
d0877473
KB		 617static void nvme_print_sgl(struct scatterlist *sgl, int nents)
618{
619 int i;
620 struct scatterlist *sg;
621
622 for_each_sg(sgl, sg, nents, i) {
623 dma_addr_t phys = sg_phys(sg);
624 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
625 "dma_address:%pad dma_length:%d\n",
626 i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
627 sg_dma_len(sg));
628 }
629}
630
a7a7cbe3
CK		 631static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
632 struct request *req, struct nvme_rw_command *cmnd)
ff22b54f 633{
f4800d6d 634 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
99802a7a 635 struct dma_pool *pool;
b131c61d 636 int length = blk_rq_payload_bytes(req);
eca18b23 637 struct scatterlist *sg = iod->sg;
ff22b54f
MW		 638 int dma_len = sg_dma_len(sg);
639 u64 dma_addr = sg_dma_address(sg);
5fd4ce1b 640 u32 page_size = dev->ctrl.page_size;
f137e0f1 641 int offset = dma_addr & (page_size - 1);
e025344c 642 __le64 *prp_list;
a7a7cbe3 643 void **list = nvme_pci_iod_list(req);
e025344c 644 dma_addr_t prp_dma;
eca18b23 645 int nprps, i;
ff22b54f 646
1d090624 647 length -= (page_size - offset);
5228b328
JS		 648 if (length <= 0) {
649 iod->first_dma = 0;
a7a7cbe3 650 goto done;
5228b328 651 }
ff22b54f 652
1d090624 653 dma_len -= (page_size - offset);
ff22b54f 654 if (dma_len) {
1d090624 655 dma_addr += (page_size - offset);
ff22b54f
MW		 656 } else {
657 sg = sg_next(sg);
658 dma_addr = sg_dma_address(sg);
659 dma_len = sg_dma_len(sg);
660 }
661
1d090624 662 if (length <= page_size) {
edd10d33 663 iod->first_dma = dma_addr;
a7a7cbe3 664 goto done;
e025344c
SMM		 665 }
666
1d090624 667 nprps = DIV_ROUND_UP(length, page_size);
99802a7a
MW		 668 if (nprps <= (256 / 8)) {
669 pool = dev->prp_small_pool;
eca18b23 670 iod->npages = 0;
99802a7a
MW		 671 } else {
672 pool = dev->prp_page_pool;
eca18b23 673 iod->npages = 1;
99802a7a
MW		 674 }
675
69d2b571 676 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
b77954cb 677 if (!prp_list) {
edd10d33 678 iod->first_dma = dma_addr;
eca18b23 679 iod->npages = -1;
86eea289 680 return BLK_STS_RESOURCE;
b77954cb 681 }
eca18b23
MW		 682 list[0] = prp_list;
683 iod->first_dma = prp_dma;
e025344c
SMM		 684 i = 0;
685 for (;;) {
1d090624 686 if (i == page_size >> 3) {
e025344c 687 __le64 *old_prp_list = prp_list;
69d2b571 688 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
eca18b23 689 if (!prp_list)
86eea289 690 return BLK_STS_RESOURCE;
eca18b23 691 list[iod->npages++] = prp_list;
7523d834
MW		 692 prp_list[0] = old_prp_list[i - 1];
693 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
694 i = 1;
e025344c
SMM		 695 }
696 prp_list[i++] = cpu_to_le64(dma_addr);
1d090624
KB		 697 dma_len -= page_size;
698 dma_addr += page_size;
699 length -= page_size;
e025344c
SMM		 700 if (length <= 0)
701 break;
702 if (dma_len > 0)
703 continue;
86eea289
KB		 704 if (unlikely(dma_len < 0))
705 goto bad_sgl;
e025344c
SMM		 706 sg = sg_next(sg);
707 dma_addr = sg_dma_address(sg);
708 dma_len = sg_dma_len(sg);
ff22b54f
MW		 709 }
710
a7a7cbe3
CK		 711done:
712 cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
713 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
714
86eea289
KB		 715 return BLK_STS_OK;
716
717 bad_sgl:
d0877473
KB		 718 WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents),
719 "Invalid SGL for payload:%d nents:%d\n",
720 blk_rq_payload_bytes(req), iod->nents);
86eea289 721 return BLK_STS_IOERR;
ff22b54f
MW		 722}
723
a7a7cbe3
CK		 724static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
725 struct scatterlist *sg)
726{
727 sge->addr = cpu_to_le64(sg_dma_address(sg));
728 sge->length = cpu_to_le32(sg_dma_len(sg));
729 sge->type = NVME_SGL_FMT_DATA_DESC << 4;
730}
731
732static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
733 dma_addr_t dma_addr, int entries)
734{
735 sge->addr = cpu_to_le64(dma_addr);
736 if (entries < SGES_PER_PAGE) {
737 sge->length = cpu_to_le32(entries * sizeof(*sge));
738 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
739 } else {
740 sge->length = cpu_to_le32(PAGE_SIZE);
741 sge->type = NVME_SGL_FMT_SEG_DESC << 4;
742 }
743}
744
745static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
b0f2853b 746 struct request *req, struct nvme_rw_command *cmd, int entries)
a7a7cbe3
CK		 747{
748 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3
CK		 749 struct dma_pool *pool;
750 struct nvme_sgl_desc *sg_list;
751 struct scatterlist *sg = iod->sg;
a7a7cbe3 752 dma_addr_t sgl_dma;
b0f2853b 753 int i = 0;
a7a7cbe3 754
a7a7cbe3
CK		 755 /* setting the transfer type as SGL */
756 cmd->flags = NVME_CMD_SGL_METABUF;
757
b0f2853b 758 if (entries == 1) {
a7a7cbe3
CK		 759 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
760 return BLK_STS_OK;
761 }
762
763 if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
764 pool = dev->prp_small_pool;
765 iod->npages = 0;
766 } else {
767 pool = dev->prp_page_pool;
768 iod->npages = 1;
769 }
770
771 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
772 if (!sg_list) {
773 iod->npages = -1;
774 return BLK_STS_RESOURCE;
775 }
776
777 nvme_pci_iod_list(req)[0] = sg_list;
778 iod->first_dma = sgl_dma;
779
780 nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
781
782 do {
783 if (i == SGES_PER_PAGE) {
784 struct nvme_sgl_desc *old_sg_desc = sg_list;
785 struct nvme_sgl_desc *link = &old_sg_desc[i - 1];
786
787 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
788 if (!sg_list)
789 return BLK_STS_RESOURCE;
790
791 i = 0;
792 nvme_pci_iod_list(req)[iod->npages++] = sg_list;
793 sg_list[i++] = *link;
794 nvme_pci_sgl_set_seg(link, sgl_dma, entries);
795 }
796
797 nvme_pci_sgl_set_data(&sg_list[i++], sg);
a7a7cbe3 798 sg = sg_next(sg);
b0f2853b 799 } while (--entries > 0);
a7a7cbe3 800
a7a7cbe3
CK		 801 return BLK_STS_OK;
802}
803
dff824b2
CH		 804static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev,
805 struct request *req, struct nvme_rw_command *cmnd,
806 struct bio_vec *bv)
807{
808 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
809 unsigned int first_prp_len = dev->ctrl.page_size - bv->bv_offset;
810
811 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
812 if (dma_mapping_error(dev->dev, iod->first_dma))
813 return BLK_STS_RESOURCE;
814 iod->dma_len = bv->bv_len;
815
816 cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma);
817 if (bv->bv_len > first_prp_len)
818 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len);
819 return 0;
820}
821
29791057
CH		 822static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev,
823 struct request *req, struct nvme_rw_command *cmnd,
824 struct bio_vec *bv)
825{
826 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
827
828 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
829 if (dma_mapping_error(dev->dev, iod->first_dma))
830 return BLK_STS_RESOURCE;
831 iod->dma_len = bv->bv_len;
832
833 cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma);
834 cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len);
835 cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4;
836 return 0;
837}
838
fc17b653 839static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
b131c61d 840 struct nvme_command *cmnd)
d29ec824 841{
f4800d6d 842 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
ba1ca37e
CH		 843 struct request_queue *q = req->q;
844 enum dma_data_direction dma_dir = rq_data_dir(req) ?
845 DMA_TO_DEVICE : DMA_FROM_DEVICE;
fc17b653 846 blk_status_t ret = BLK_STS_IOERR;
b0f2853b 847 int nr_mapped;
d29ec824 848
dff824b2
CH		 849 if (blk_rq_nr_phys_segments(req) == 1) {
850 struct bio_vec bv = req_bvec(req);
851
852 if (!is_pci_p2pdma_page(bv.bv_page)) {
853 if (bv.bv_offset + bv.bv_len <= dev->ctrl.page_size * 2)
854 return nvme_setup_prp_simple(dev, req,
855 &cmnd->rw, &bv);
29791057
CH		 856
857 if (iod->nvmeq->qid &&
858 dev->ctrl.sgls & ((1 << 0) | (1 << 1)))
859 return nvme_setup_sgl_simple(dev, req,
860 &cmnd->rw, &bv);
dff824b2
CH		 861 }
862 }
863
864 iod->dma_len = 0;
d43f1ccf
CH		 865 iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC);
866 if (!iod->sg)
867 return BLK_STS_RESOURCE;
9b048119
CH		 868
869 iod->use_sgl = nvme_pci_use_sgls(dev, req);
870
f9d03f96 871 sg_init_table(iod->sg, blk_rq_nr_phys_segments(req));
ba1ca37e
CH		 872 iod->nents = blk_rq_map_sg(q, req, iod->sg);
873 if (!iod->nents)
874 goto out;
d29ec824 875
fc17b653 876 ret = BLK_STS_RESOURCE;
e0596ab2
LG		 877
878 if (is_pci_p2pdma_page(sg_page(iod->sg)))
879 nr_mapped = pci_p2pdma_map_sg(dev->dev, iod->sg, iod->nents,
880 dma_dir);
881 else
882 nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents,
883 dma_dir, DMA_ATTR_NO_WARN);
b0f2853b 884 if (!nr_mapped)
ba1ca37e 885 goto out;
d29ec824 886
955b1b5a 887 if (iod->use_sgl)
b0f2853b 888 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped);
a7a7cbe3
CK		 889 else
890 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
4aedb705 891out:
86eea289 892 if (ret != BLK_STS_OK)
4aedb705
CH		 893 nvme_unmap_data(dev, req);
894 return ret;
895}
3045c0d0 896
4aedb705
CH		 897static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req,
898 struct nvme_command *cmnd)
899{
900 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
00df5cb4 901
4aedb705
CH		 902 iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req),
903 rq_dma_dir(req), 0);
904 if (dma_mapping_error(dev->dev, iod->meta_dma))
905 return BLK_STS_IOERR;
906 cmnd->rw.metadata = cpu_to_le64(iod->meta_dma);
907 return 0;
00df5cb4
MW		 908}
909
d29ec824
CH		 910/*
911 * NOTE: ns is NULL when called on the admin queue.
912 */
fc17b653 913static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
a4aea562 914 const struct blk_mq_queue_data *bd)
edd10d33 915{
a4aea562
MB		 916 struct nvme_ns *ns = hctx->queue->queuedata;
917 struct nvme_queue *nvmeq = hctx->driver_data;
d29ec824 918 struct nvme_dev *dev = nvmeq->dev;
a4aea562 919 struct request *req = bd->rq;
9b048119 920 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
ba1ca37e 921 struct nvme_command cmnd;
ebe6d874 922 blk_status_t ret;
e1e5e564 923
9b048119
CH		 924 iod->aborted = 0;
925 iod->npages = -1;
926 iod->nents = 0;
927
d1f06f4a
JA		 928 /*
929 * We should not need to do this, but we're still using this to
930 * ensure we can drain requests on a dying queue.
931 */
4e224106 932 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
d1f06f4a
JA		 933 return BLK_STS_IOERR;
934
f9d03f96 935 ret = nvme_setup_cmd(ns, req, &cmnd);
fc17b653 936 if (ret)
f4800d6d 937 return ret;
a4aea562 938
fc17b653 939 if (blk_rq_nr_phys_segments(req)) {
b131c61d 940 ret = nvme_map_data(dev, req, &cmnd);
fc17b653 941 if (ret)
9b048119 942 goto out_free_cmd;
fc17b653 943 }
a4aea562 944
4aedb705
CH		 945 if (blk_integrity_rq(req)) {
946 ret = nvme_map_metadata(dev, req, &cmnd);
947 if (ret)
948 goto out_unmap_data;
949 }
950
aae239e1 951 blk_mq_start_request(req);
04f3eafd 952 nvme_submit_cmd(nvmeq, &cmnd, bd->last);
fc17b653 953 return BLK_STS_OK;
4aedb705
CH		 954out_unmap_data:
955 nvme_unmap_data(dev, req);
f9d03f96
CH		 956out_free_cmd:
957 nvme_cleanup_cmd(req);
ba1ca37e 958 return ret;
b60503ba 959}
e1e5e564 960
77f02a7a 961static void nvme_pci_complete_rq(struct request *req)
eee417b0 962{
f4800d6d 963 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
4aedb705 964 struct nvme_dev *dev = iod->nvmeq->dev;
a4aea562 965
915f04c9 966 nvme_cleanup_cmd(req);
4aedb705
CH		 967 if (blk_integrity_rq(req))
968 dma_unmap_page(dev->dev, iod->meta_dma,
969 rq_integrity_vec(req)->bv_len, rq_data_dir(req));
b15c592d 970 if (blk_rq_nr_phys_segments(req))
4aedb705 971 nvme_unmap_data(dev, req);
77f02a7a 972 nvme_complete_rq(req);
b60503ba
MW		 973}
974
d783e0bd 975/* We read the CQE phase first to check if the rest of the entry is valid */
750dde44 976static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq)
d783e0bd 977{
750dde44
CH		 978 return (le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) ==
979 nvmeq->cq_phase;
d783e0bd
MR		 980}
981
eb281c82 982static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
b60503ba 983{
eb281c82 984 u16 head = nvmeq->cq_head;
adf68f21 985
397c699f
KB		 986 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
987 nvmeq->dbbuf_cq_ei))
988 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
eb281c82 989}
aae239e1 990
5cb525c8 991static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx)
83a12fb7 992{
5cb525c8 993 volatile struct nvme_completion *cqe = &nvmeq->cqes[idx];
83a12fb7 994 struct request *req;
adf68f21 995
83a12fb7
SG		 996 if (unlikely(cqe->command_id >= nvmeq->q_depth)) {
997 dev_warn(nvmeq->dev->ctrl.device,
998 "invalid id %d completed on queue %d\n",
999 cqe->command_id, le16_to_cpu(cqe->sq_id));
1000 return;
b60503ba
MW		 1001 }
1002
83a12fb7
SG		 1003 /*
1004 * AEN requests are special as they don't time out and can
1005 * survive any kind of queue freeze and often don't respond to
1006 * aborts. We don't even bother to allocate a struct request
1007 * for them but rather special case them here.
1008 */
1009 if (unlikely(nvmeq->qid == 0 &&
38dabe21 1010 cqe->command_id >= NVME_AQ_BLK_MQ_DEPTH)) {
83a12fb7
SG		 1011 nvme_complete_async_event(&nvmeq->dev->ctrl,
1012 cqe->status, &cqe->result);
a0fa9647 1013 return;
83a12fb7 1014 }
b60503ba 1015
83a12fb7 1016 req = blk_mq_tag_to_rq(*nvmeq->tags, cqe->command_id);
604c01d5 1017 trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail);
83a12fb7
SG		 1018 nvme_end_request(req, cqe->status, cqe->result);
1019}
b60503ba 1020
5cb525c8 1021static void nvme_complete_cqes(struct nvme_queue *nvmeq, u16 start, u16 end)
b60503ba 1022{
5cb525c8
JA		 1023 while (start != end) {
1024 nvme_handle_cqe(nvmeq, start);
1025 if (++start == nvmeq->q_depth)
1026 start = 0;
1027 }
1028}
adf68f21 1029
5cb525c8
JA		 1030static inline void nvme_update_cq_head(struct nvme_queue *nvmeq)
1031{
dcca1662 1032 if (nvmeq->cq_head == nvmeq->q_depth - 1) {
5cb525c8
JA		 1033 nvmeq->cq_head = 0;
1034 nvmeq->cq_phase = !nvmeq->cq_phase;
dcca1662
HY		 1035 } else {
1036 nvmeq->cq_head++;
b60503ba 1037 }
a0fa9647
JA		 1038}
1039
1052b8ac
JA		 1040static inline int nvme_process_cq(struct nvme_queue *nvmeq, u16 *start,
1041 u16 *end, unsigned int tag)
a0fa9647 1042{
1052b8ac 1043 int found = 0;
b60503ba 1044
5cb525c8 1045 *start = nvmeq->cq_head;
1052b8ac
JA		 1046 while (nvme_cqe_pending(nvmeq)) {
1047 if (tag == -1U || nvmeq->cqes[nvmeq->cq_head].command_id == tag)
1048 found++;
5cb525c8 1049 nvme_update_cq_head(nvmeq);
920d13a8 1050 }
5cb525c8 1051 *end = nvmeq->cq_head;
eb281c82 1052
5cb525c8 1053 if (*start != *end)
920d13a8 1054 nvme_ring_cq_doorbell(nvmeq);
5cb525c8 1055 return found;
b60503ba
MW		 1056}
1057
1058static irqreturn_t nvme_irq(int irq, void *data)
58ffacb5 1059{
58ffacb5 1060 struct nvme_queue *nvmeq = data;
68fa9dbe 1061 irqreturn_t ret = IRQ_NONE;
5cb525c8
JA		 1062 u16 start, end;
1063
3a7afd8e
CH		 1064 /*
1065 * The rmb/wmb pair ensures we see all updates from a previous run of
1066 * the irq handler, even if that was on another CPU.
1067 */
1068 rmb();
68fa9dbe
JA		 1069 if (nvmeq->cq_head != nvmeq->last_cq_head)
1070 ret = IRQ_HANDLED;
5cb525c8 1071 nvme_process_cq(nvmeq, &start, &end, -1);
68fa9dbe 1072 nvmeq->last_cq_head = nvmeq->cq_head;
3a7afd8e 1073 wmb();
5cb525c8 1074
68fa9dbe
JA		 1075 if (start != end) {
1076 nvme_complete_cqes(nvmeq, start, end);
1077 return IRQ_HANDLED;
1078 }
1079
1080 return ret;
58ffacb5
MW		 1081}
1082
1083static irqreturn_t nvme_irq_check(int irq, void *data)
1084{
1085 struct nvme_queue *nvmeq = data;
750dde44 1086 if (nvme_cqe_pending(nvmeq))
d783e0bd
MR		 1087 return IRQ_WAKE_THREAD;
1088 return IRQ_NONE;
58ffacb5
MW		 1089}
1090
0b2a8a9f
CH		 1091/*
1092 * Poll for completions any queue, including those not dedicated to polling.
1093 * Can be called from any context.
1094 */
1095static int nvme_poll_irqdisable(struct nvme_queue *nvmeq, unsigned int tag)
a0fa9647 1096{
3a7afd8e 1097 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
5cb525c8 1098 u16 start, end;
1052b8ac 1099 int found;
a0fa9647 1100
3a7afd8e
CH		 1101 /*
1102 * For a poll queue we need to protect against the polling thread
1103 * using the CQ lock. For normal interrupt driven threads we have
1104 * to disable the interrupt to avoid racing with it.
1105 */
7c349dde 1106 if (test_bit(NVMEQ_POLLED, &nvmeq->flags)) {
3a7afd8e 1107 spin_lock(&nvmeq->cq_poll_lock);
91a509f8 1108 found = nvme_process_cq(nvmeq, &start, &end, tag);
3a7afd8e 1109 spin_unlock(&nvmeq->cq_poll_lock);
91a509f8
CH		 1110 } else {
1111 disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1112 found = nvme_process_cq(nvmeq, &start, &end, tag);
3a7afd8e 1113 enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
91a509f8 1114 }
442e19b7 1115
5cb525c8 1116 nvme_complete_cqes(nvmeq, start, end);
442e19b7 1117 return found;
a0fa9647
JA		 1118}
1119
9743139c 1120static int nvme_poll(struct blk_mq_hw_ctx *hctx)
dabcefab
JA		 1121{
1122 struct nvme_queue *nvmeq = hctx->driver_data;
1123 u16 start, end;
1124 bool found;
1125
1126 if (!nvme_cqe_pending(nvmeq))
1127 return 0;
1128
3a7afd8e 1129 spin_lock(&nvmeq->cq_poll_lock);
9743139c 1130 found = nvme_process_cq(nvmeq, &start, &end, -1);
3a7afd8e 1131 spin_unlock(&nvmeq->cq_poll_lock);
dabcefab
JA		 1132
1133 nvme_complete_cqes(nvmeq, start, end);
1134 return found;
1135}
1136
ad22c355 1137static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
b60503ba 1138{
f866fc42 1139 struct nvme_dev *dev = to_nvme_dev(ctrl);
147b27e4 1140 struct nvme_queue *nvmeq = &dev->queues[0];
a4aea562 1141 struct nvme_command c;
b60503ba 1142
a4aea562
MB		 1143 memset(&c, 0, sizeof(c));
1144 c.common.opcode = nvme_admin_async_event;
ad22c355 1145 c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
04f3eafd 1146 nvme_submit_cmd(nvmeq, &c, true);
f705f837
CH		 1147}
1148
b60503ba 1149static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
f705f837 1150{
b60503ba
MW		 1151 struct nvme_command c;
1152
1153 memset(&c, 0, sizeof(c));
1154 c.delete_queue.opcode = opcode;
1155 c.delete_queue.qid = cpu_to_le16(id);
1156
1c63dc66 1157 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1158}
1159
b60503ba 1160static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
a8e3e0bb 1161 struct nvme_queue *nvmeq, s16 vector)
b60503ba 1162{
b60503ba 1163 struct nvme_command c;
4b04cc6a
JA		 1164 int flags = NVME_QUEUE_PHYS_CONTIG;
1165
7c349dde 1166 if (!test_bit(NVMEQ_POLLED, &nvmeq->flags))
4b04cc6a 1167 flags |= NVME_CQ_IRQ_ENABLED;
b60503ba 1168
d29ec824 1169 /*
16772ae6 1170 * Note: we (ab)use the fact that the prp fields survive if no data
d29ec824
CH		 1171 * is attached to the request.
1172 */
b60503ba
MW		 1173 memset(&c, 0, sizeof(c));
1174 c.create_cq.opcode = nvme_admin_create_cq;
1175 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1176 c.create_cq.cqid = cpu_to_le16(qid);
1177 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1178 c.create_cq.cq_flags = cpu_to_le16(flags);
7c349dde 1179 c.create_cq.irq_vector = cpu_to_le16(vector);
b60503ba 1180
1c63dc66 1181 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1182}
1183
1184static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1185 struct nvme_queue *nvmeq)
1186{
9abd68ef 1187 struct nvme_ctrl *ctrl = &dev->ctrl;
b60503ba 1188 struct nvme_command c;
81c1cd98 1189 int flags = NVME_QUEUE_PHYS_CONTIG;
b60503ba 1190
9abd68ef
JA		 1191 /*
1192 * Some drives have a bug that auto-enables WRRU if MEDIUM isn't
1193 * set. Since URGENT priority is zeroes, it makes all queues
1194 * URGENT.
1195 */
1196 if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ)
1197 flags |= NVME_SQ_PRIO_MEDIUM;
1198
d29ec824 1199 /*
16772ae6 1200 * Note: we (ab)use the fact that the prp fields survive if no data
d29ec824
CH		 1201 * is attached to the request.
1202 */
b60503ba
MW		 1203 memset(&c, 0, sizeof(c));
1204 c.create_sq.opcode = nvme_admin_create_sq;
1205 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1206 c.create_sq.sqid = cpu_to_le16(qid);
1207 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1208 c.create_sq.sq_flags = cpu_to_le16(flags);
1209 c.create_sq.cqid = cpu_to_le16(qid);
1210
1c63dc66 1211 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1212}
1213
1214static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1215{
1216 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1217}
1218
1219static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1220{
1221 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1222}
1223
2a842aca 1224static void abort_endio(struct request *req, blk_status_t error)
bc5fc7e4 1225{
f4800d6d
CH		 1226 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1227 struct nvme_queue *nvmeq = iod->nvmeq;
e44ac588 1228
27fa9bc5
CH		 1229 dev_warn(nvmeq->dev->ctrl.device,
1230 "Abort status: 0x%x", nvme_req(req)->status);
e7a2a87d 1231 atomic_inc(&nvmeq->dev->ctrl.abort_limit);
e7a2a87d 1232 blk_mq_free_request(req);
bc5fc7e4
MW		 1233}
1234
b2a0eb1a
KB		 1235static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1236{
1237
1238 /* If true, indicates loss of adapter communication, possibly by a
1239 * NVMe Subsystem reset.
1240 */
1241 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1242
ad70062c
JW		 1243 /* If there is a reset/reinit ongoing, we shouldn't reset again. */
1244 switch (dev->ctrl.state) {
1245 case NVME_CTRL_RESETTING:
ad6a0a52 1246 case NVME_CTRL_CONNECTING:
b2a0eb1a 1247 return false;
ad70062c
JW		 1248 default:
1249 break;
1250 }
b2a0eb1a
KB		 1251
1252 /* We shouldn't reset unless the controller is on fatal error state
1253 * _or_ if we lost the communication with it.
1254 */
1255 if (!(csts & NVME_CSTS_CFS) && !nssro)
1256 return false;
1257
b2a0eb1a
KB		 1258 return true;
1259}
1260
1261static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1262{
1263 /* Read a config register to help see what died. */
1264 u16 pci_status;
1265 int result;
1266
1267 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1268 &pci_status);
1269 if (result == PCIBIOS_SUCCESSFUL)
1270 dev_warn(dev->ctrl.device,
1271 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1272 csts, pci_status);
1273 else
1274 dev_warn(dev->ctrl.device,
1275 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1276 csts, result);
1277}
1278
31c7c7d2 1279static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
c30341dc 1280{
f4800d6d
CH		 1281 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1282 struct nvme_queue *nvmeq = iod->nvmeq;
c30341dc 1283 struct nvme_dev *dev = nvmeq->dev;
a4aea562 1284 struct request *abort_req;
a4aea562 1285 struct nvme_command cmd;
b2a0eb1a
KB		 1286 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1287
651438bb
WX		 1288 /* If PCI error recovery process is happening, we cannot reset or
1289 * the recovery mechanism will surely fail.
1290 */
1291 mb();
1292 if (pci_channel_offline(to_pci_dev(dev->dev)))
1293 return BLK_EH_RESET_TIMER;
1294
b2a0eb1a
KB		 1295 /*
1296 * Reset immediately if the controller is failed
1297 */
1298 if (nvme_should_reset(dev, csts)) {
1299 nvme_warn_reset(dev, csts);
1300 nvme_dev_disable(dev, false);
d86c4d8e 1301 nvme_reset_ctrl(&dev->ctrl);
db8c48e4 1302 return BLK_EH_DONE;
b2a0eb1a 1303 }
c30341dc 1304
7776db1c
KB		 1305 /*
1306 * Did we miss an interrupt?
1307 */
0b2a8a9f 1308 if (nvme_poll_irqdisable(nvmeq, req->tag)) {
7776db1c
KB		 1309 dev_warn(dev->ctrl.device,
1310 "I/O %d QID %d timeout, completion polled\n",
1311 req->tag, nvmeq->qid);
db8c48e4 1312 return BLK_EH_DONE;
7776db1c
KB		 1313 }
1314
31c7c7d2 1315 /*
fd634f41
CH		 1316 * Shutdown immediately if controller times out while starting. The
1317 * reset work will see the pci device disabled when it gets the forced
1318 * cancellation error. All outstanding requests are completed on
db8c48e4 1319 * shutdown, so we return BLK_EH_DONE.
fd634f41 1320 */
4244140d
KB		 1321 switch (dev->ctrl.state) {
1322 case NVME_CTRL_CONNECTING:
1323 case NVME_CTRL_RESETTING:
b9cac43c 1324 dev_warn_ratelimited(dev->ctrl.device,
fd634f41
CH		 1325 "I/O %d QID %d timeout, disable controller\n",
1326 req->tag, nvmeq->qid);
a5cdb68c 1327 nvme_dev_disable(dev, false);
27fa9bc5 1328 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
db8c48e4 1329 return BLK_EH_DONE;
4244140d
KB		 1330 default:
1331 break;
c30341dc
KB		 1332 }
1333
fd634f41
CH		 1334 /*
1335 * Shutdown the controller immediately and schedule a reset if the
1336 * command was already aborted once before and still hasn't been
1337 * returned to the driver, or if this is the admin queue.
31c7c7d2 1338 */
f4800d6d 1339 if (!nvmeq->qid || iod->aborted) {
1b3c47c1 1340 dev_warn(dev->ctrl.device,
e1569a16
KB		 1341 "I/O %d QID %d timeout, reset controller\n",
1342 req->tag, nvmeq->qid);
a5cdb68c 1343 nvme_dev_disable(dev, false);
d86c4d8e 1344 nvme_reset_ctrl(&dev->ctrl);
c30341dc 1345
27fa9bc5 1346 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
db8c48e4 1347 return BLK_EH_DONE;
c30341dc 1348 }
c30341dc 1349
e7a2a87d 1350 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
6bf25d16 1351 atomic_inc(&dev->ctrl.abort_limit);
31c7c7d2 1352 return BLK_EH_RESET_TIMER;
6bf25d16 1353 }
7bf7d778 1354 iod->aborted = 1;
a4aea562 1355
c30341dc
KB		 1356 memset(&cmd, 0, sizeof(cmd));
1357 cmd.abort.opcode = nvme_admin_abort_cmd;
a4aea562 1358 cmd.abort.cid = req->tag;
c30341dc 1359 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
c30341dc 1360
1b3c47c1
SG		 1361 dev_warn(nvmeq->dev->ctrl.device,
1362 "I/O %d QID %d timeout, aborting\n",
1363 req->tag, nvmeq->qid);
e7a2a87d
CH		 1364
1365 abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
eb71f435 1366 BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
e7a2a87d
CH		 1367 if (IS_ERR(abort_req)) {
1368 atomic_inc(&dev->ctrl.abort_limit);
1369 return BLK_EH_RESET_TIMER;
1370 }
1371
1372 abort_req->timeout = ADMIN_TIMEOUT;
1373 abort_req->end_io_data = NULL;
1374 blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio);
c30341dc 1375
31c7c7d2
CH		 1376 /*
1377 * The aborted req will be completed on receiving the abort req.
1378 * We enable the timer again. If hit twice, it'll cause a device reset,
1379 * as the device then is in a faulty state.
1380 */
1381 return BLK_EH_RESET_TIMER;
c30341dc
KB		 1382}
1383
a4aea562
MB		 1384static void nvme_free_queue(struct nvme_queue *nvmeq)
1385{
88a041f4 1386 dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq->q_depth),
9e866774 1387 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
63223078
CH		 1388 if (!nvmeq->sq_cmds)
1389 return;
0f238ff5 1390
63223078 1391 if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) {
88a041f4 1392 pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev),
63223078
CH		 1393 nvmeq->sq_cmds, SQ_SIZE(nvmeq->q_depth));
1394 } else {
88a041f4 1395 dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq->q_depth),
63223078 1396 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
0f238ff5 1397 }
9e866774
MW		 1398}
1399
a1a5ef99 1400static void nvme_free_queues(struct nvme_dev *dev, int lowest)
22404274
KB		 1401{
1402 int i;
1403
d858e5f0 1404 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
d858e5f0 1405 dev->ctrl.queue_count--;
147b27e4 1406 nvme_free_queue(&dev->queues[i]);
121c7ad4 1407 }
22404274
KB		 1408}
1409
4d115420
KB		 1410/**
1411 * nvme_suspend_queue - put queue into suspended state
40581d1a 1412 * @nvmeq: queue to suspend
4d115420
KB		 1413 */
1414static int nvme_suspend_queue(struct nvme_queue *nvmeq)
b60503ba 1415{
4e224106 1416 if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags))
2b25d981 1417 return 1;
a09115b2 1418
4e224106 1419 /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */
d1f06f4a 1420 mb();
a09115b2 1421
4e224106 1422 nvmeq->dev->online_queues--;
1c63dc66 1423 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
c81545f9 1424 blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q);
7c349dde
KB		 1425 if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags))
1426 pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq);
4d115420
KB		 1427 return 0;
1428}
b60503ba 1429
8fae268b
KB		 1430static void nvme_suspend_io_queues(struct nvme_dev *dev)
1431{
1432 int i;
1433
1434 for (i = dev->ctrl.queue_count - 1; i > 0; i--)
1435 nvme_suspend_queue(&dev->queues[i]);
1436}
1437
a5cdb68c 1438static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
4d115420 1439{
147b27e4 1440 struct nvme_queue *nvmeq = &dev->queues[0];
4d115420 1441
a5cdb68c
KB		 1442 if (shutdown)
1443 nvme_shutdown_ctrl(&dev->ctrl);
1444 else
20d0dfe6 1445 nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap);
07836e65 1446
0b2a8a9f 1447 nvme_poll_irqdisable(nvmeq, -1);
b60503ba
MW		 1448}
1449
8ffaadf7
JD		 1450static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1451 int entry_size)
1452{
1453 int q_depth = dev->q_depth;
5fd4ce1b
CH		 1454 unsigned q_size_aligned = roundup(q_depth * entry_size,
1455 dev->ctrl.page_size);
8ffaadf7
JD		 1456
1457 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
c45f5c99 1458 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
5fd4ce1b 1459 mem_per_q = round_down(mem_per_q, dev->ctrl.page_size);
c45f5c99 1460 q_depth = div_u64(mem_per_q, entry_size);
8ffaadf7
JD		 1461
1462 /*
1463 * Ensure the reduced q_depth is above some threshold where it
1464 * would be better to map queues in system memory with the
1465 * original depth
1466 */
1467 if (q_depth < 64)
1468 return -ENOMEM;
1469 }
1470
1471 return q_depth;
1472}
1473
1474static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1475 int qid, int depth)
1476{
0f238ff5
LG		 1477 struct pci_dev *pdev = to_pci_dev(dev->dev);
1478
1479 if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
1480 nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(depth));
1481 nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev,
1482 nvmeq->sq_cmds);
63223078
CH		 1483 if (nvmeq->sq_dma_addr) {
1484 set_bit(NVMEQ_SQ_CMB, &nvmeq->flags);
1485 return 0;
1486 }
0f238ff5 1487 }
8ffaadf7 1488
63223078
CH		 1489 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
1490 &nvmeq->sq_dma_addr, GFP_KERNEL);
815c6704
KB		 1491 if (!nvmeq->sq_cmds)
1492 return -ENOMEM;
8ffaadf7
JD		 1493 return 0;
1494}
1495
a6ff7262 1496static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
b60503ba 1497{
147b27e4 1498 struct nvme_queue *nvmeq = &dev->queues[qid];
b60503ba 1499
62314e40
KB		 1500 if (dev->ctrl.queue_count > qid)
1501 return 0;
b60503ba 1502
750afb08
LC		 1503 nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(depth),
1504 &nvmeq->cq_dma_addr, GFP_KERNEL);
b60503ba
MW		 1505 if (!nvmeq->cqes)
1506 goto free_nvmeq;
b60503ba 1507
8ffaadf7 1508 if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth))
b60503ba
MW		 1509 goto free_cqdma;
1510
091b6092 1511 nvmeq->dev = dev;
1ab0cd69 1512 spin_lock_init(&nvmeq->sq_lock);
3a7afd8e 1513 spin_lock_init(&nvmeq->cq_poll_lock);
b60503ba 1514 nvmeq->cq_head = 0;
82123460 1515 nvmeq->cq_phase = 1;
b80d5ccc 1516 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
b60503ba 1517 nvmeq->q_depth = depth;
c30341dc 1518 nvmeq->qid = qid;
d858e5f0 1519 dev->ctrl.queue_count++;
36a7e993 1520
147b27e4 1521 return 0;
b60503ba
MW		 1522
1523 free_cqdma:
e75ec752 1524 dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes,
b60503ba
MW		 1525 nvmeq->cq_dma_addr);
1526 free_nvmeq:
147b27e4 1527 return -ENOMEM;
b60503ba
MW		 1528}
1529
dca51e78 1530static int queue_request_irq(struct nvme_queue *nvmeq)
3001082c 1531{
0ff199cb
CH		 1532 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1533 int nr = nvmeq->dev->ctrl.instance;
1534
1535 if (use_threaded_interrupts) {
1536 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1537 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1538 } else {
1539 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1540 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1541 }
3001082c
MW		 1542}
1543
22404274 1544static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
b60503ba 1545{
22404274 1546 struct nvme_dev *dev = nvmeq->dev;
b60503ba 1547
22404274 1548 nvmeq->sq_tail = 0;
04f3eafd 1549 nvmeq->last_sq_tail = 0;
22404274
KB		 1550 nvmeq->cq_head = 0;
1551 nvmeq->cq_phase = 1;
b80d5ccc 1552 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
22404274 1553 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
f9f38e33 1554 nvme_dbbuf_init(dev, nvmeq, qid);
42f61420 1555 dev->online_queues++;
3a7afd8e 1556 wmb(); /* ensure the first interrupt sees the initialization */
22404274
KB		 1557}
1558
4b04cc6a 1559static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled)
22404274
KB		 1560{
1561 struct nvme_dev *dev = nvmeq->dev;
1562 int result;
7c349dde 1563 u16 vector = 0;
3f85d50b 1564
d1ed6aa1
CH		 1565 clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
1566
22b55601
KB		 1567 /*
1568 * A queue's vector matches the queue identifier unless the controller
1569 * has only one vector available.
1570 */
4b04cc6a
JA		 1571 if (!polled)
1572 vector = dev->num_vecs == 1 ? 0 : qid;
1573 else
7c349dde 1574 set_bit(NVMEQ_POLLED, &nvmeq->flags);
4b04cc6a 1575
a8e3e0bb 1576 result = adapter_alloc_cq(dev, qid, nvmeq, vector);
ded45505
KB		 1577 if (result)
1578 return result;
b60503ba
MW		 1579
1580 result = adapter_alloc_sq(dev, qid, nvmeq);
1581 if (result < 0)
ded45505
KB		 1582 return result;
1583 else if (result)
b60503ba
MW		 1584 goto release_cq;
1585
a8e3e0bb 1586 nvmeq->cq_vector = vector;
161b8be2 1587 nvme_init_queue(nvmeq, qid);
4b04cc6a 1588
7c349dde
KB		 1589 if (!polled) {
1590 nvmeq->cq_vector = vector;
4b04cc6a
JA		 1591 result = queue_request_irq(nvmeq);
1592 if (result < 0)
1593 goto release_sq;
1594 }
b60503ba 1595
4e224106 1596 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
22404274 1597 return result;
b60503ba 1598
a8e3e0bb 1599release_sq:
f25a2dfc 1600 dev->online_queues--;
b60503ba 1601 adapter_delete_sq(dev, qid);
a8e3e0bb 1602release_cq:
b60503ba 1603 adapter_delete_cq(dev, qid);
22404274 1604 return result;
b60503ba
MW		 1605}
1606
f363b089 1607static const struct blk_mq_ops nvme_mq_admin_ops = {
d29ec824 1608 .queue_rq = nvme_queue_rq,
77f02a7a 1609 .complete = nvme_pci_complete_rq,
a4aea562 1610 .init_hctx = nvme_admin_init_hctx,
4af0e21c 1611 .exit_hctx = nvme_admin_exit_hctx,
0350815a 1612 .init_request = nvme_init_request,
a4aea562
MB		 1613 .timeout = nvme_timeout,
1614};
1615
f363b089 1616static const struct blk_mq_ops nvme_mq_ops = {
376f7ef8
CH		 1617 .queue_rq = nvme_queue_rq,
1618 .complete = nvme_pci_complete_rq,
1619 .commit_rqs = nvme_commit_rqs,
1620 .init_hctx = nvme_init_hctx,
1621 .init_request = nvme_init_request,
1622 .map_queues = nvme_pci_map_queues,
1623 .timeout = nvme_timeout,
1624 .poll = nvme_poll,
dabcefab
JA		 1625};
1626
ea191d2f
KB		 1627static void nvme_dev_remove_admin(struct nvme_dev *dev)
1628{
1c63dc66 1629 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
69d9a99c
KB		 1630 /*
1631 * If the controller was reset during removal, it's possible
1632 * user requests may be waiting on a stopped queue. Start the
1633 * queue to flush these to completion.
1634 */
c81545f9 1635 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1c63dc66 1636 blk_cleanup_queue(dev->ctrl.admin_q);
ea191d2f
KB		 1637 blk_mq_free_tag_set(&dev->admin_tagset);
1638 }
1639}
1640
a4aea562
MB		 1641static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1642{
1c63dc66 1643 if (!dev->ctrl.admin_q) {
a4aea562
MB		 1644 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1645 dev->admin_tagset.nr_hw_queues = 1;
e3e9d50c 1646
38dabe21 1647 dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH;
a4aea562 1648 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
e75ec752 1649 dev->admin_tagset.numa_node = dev_to_node(dev->dev);
d43f1ccf 1650 dev->admin_tagset.cmd_size = sizeof(struct nvme_iod);
d3484991 1651 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED;
a4aea562
MB		 1652 dev->admin_tagset.driver_data = dev;
1653
1654 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1655 return -ENOMEM;
34b6c231 1656 dev->ctrl.admin_tagset = &dev->admin_tagset;
a4aea562 1657
1c63dc66
CH		 1658 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1659 if (IS_ERR(dev->ctrl.admin_q)) {
a4aea562
MB		 1660 blk_mq_free_tag_set(&dev->admin_tagset);
1661 return -ENOMEM;
1662 }
1c63dc66 1663 if (!blk_get_queue(dev->ctrl.admin_q)) {
ea191d2f 1664 nvme_dev_remove_admin(dev);
1c63dc66 1665 dev->ctrl.admin_q = NULL;
ea191d2f
KB		 1666 return -ENODEV;
1667 }
0fb59cbc 1668 } else
c81545f9 1669 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
a4aea562
MB		 1670
1671 return 0;
1672}
1673
97f6ef64
XY		 1674static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1675{
1676 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1677}
1678
1679static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1680{
1681 struct pci_dev *pdev = to_pci_dev(dev->dev);
1682
1683 if (size <= dev->bar_mapped_size)
1684 return 0;
1685 if (size > pci_resource_len(pdev, 0))
1686 return -ENOMEM;
1687 if (dev->bar)
1688 iounmap(dev->bar);
1689 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1690 if (!dev->bar) {
1691 dev->bar_mapped_size = 0;
1692 return -ENOMEM;
1693 }
1694 dev->bar_mapped_size = size;
1695 dev->dbs = dev->bar + NVME_REG_DBS;
1696
1697 return 0;
1698}
1699
01ad0990 1700static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
b60503ba 1701{
ba47e386 1702 int result;
b60503ba
MW		 1703 u32 aqa;
1704 struct nvme_queue *nvmeq;
1705
97f6ef64
XY		 1706 result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1707 if (result < 0)
1708 return result;
1709
8ef2074d 1710 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
20d0dfe6 1711 NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
dfbac8c7 1712
7a67cbea
CH		 1713 if (dev->subsystem &&
1714 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1715 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
dfbac8c7 1716
20d0dfe6 1717 result = nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap);
ba47e386
MW		 1718 if (result < 0)
1719 return result;
b60503ba 1720
a6ff7262 1721 result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
147b27e4
SG		 1722 if (result)
1723 return result;
b60503ba 1724
147b27e4 1725 nvmeq = &dev->queues[0];
b60503ba
MW		 1726 aqa = nvmeq->q_depth - 1;
1727 aqa |= aqa << 16;
1728
7a67cbea
CH		 1729 writel(aqa, dev->bar + NVME_REG_AQA);
1730 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1731 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
b60503ba 1732
20d0dfe6 1733 result = nvme_enable_ctrl(&dev->ctrl, dev->ctrl.cap);
025c557a 1734 if (result)
d4875622 1735 return result;
a4aea562 1736
2b25d981 1737 nvmeq->cq_vector = 0;
161b8be2 1738 nvme_init_queue(nvmeq, 0);
dca51e78 1739 result = queue_request_irq(nvmeq);
758dd7fd 1740 if (result) {
7c349dde 1741 dev->online_queues--;
d4875622 1742 return result;
758dd7fd 1743 }
025c557a 1744
4e224106 1745 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
b60503ba
MW		 1746 return result;
1747}
1748
749941f2 1749static int nvme_create_io_queues(struct nvme_dev *dev)
42f61420 1750{
4b04cc6a 1751 unsigned i, max, rw_queues;
749941f2 1752 int ret = 0;
42f61420 1753
d858e5f0 1754 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
a6ff7262 1755 if (nvme_alloc_queue(dev, i, dev->q_depth)) {
749941f2 1756 ret = -ENOMEM;
42f61420 1757 break;
749941f2
CH		 1758 }
1759 }
42f61420 1760
d858e5f0 1761 max = min(dev->max_qid, dev->ctrl.queue_count - 1);
e20ba6e1
CH		 1762 if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) {
1763 rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] +
1764 dev->io_queues[HCTX_TYPE_READ];
4b04cc6a
JA		 1765 } else {
1766 rw_queues = max;
1767 }
1768
949928c1 1769 for (i = dev->online_queues; i <= max; i++) {
4b04cc6a
JA		 1770 bool polled = i > rw_queues;
1771
1772 ret = nvme_create_queue(&dev->queues[i], i, polled);
d4875622 1773 if (ret)
42f61420 1774 break;
27e8166c 1775 }
749941f2
CH		 1776
1777 /*
1778 * Ignore failing Create SQ/CQ commands, we can continue with less
8adb8c14
MI		 1779 * than the desired amount of queues, and even a controller without
1780 * I/O queues can still be used to issue admin commands. This might
749941f2
CH		 1781 * be useful to upgrade a buggy firmware for example.
1782 */
1783 return ret >= 0 ? 0 : ret;
b60503ba
MW		 1784}
1785
202021c1
SB		 1786static ssize_t nvme_cmb_show(struct device *dev,
1787 struct device_attribute *attr,
1788 char *buf)
1789{
1790 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
1791
c965809c 1792 return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n",
202021c1
SB		 1793 ndev->cmbloc, ndev->cmbsz);
1794}
1795static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL);
1796
88de4598 1797static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
8ffaadf7 1798{
88de4598
CH		 1799 u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
1800
1801 return 1ULL << (12 + 4 * szu);
1802}
1803
1804static u32 nvme_cmb_size(struct nvme_dev *dev)
1805{
1806 return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
1807}
1808
f65efd6d 1809static void nvme_map_cmb(struct nvme_dev *dev)
8ffaadf7 1810{
88de4598 1811 u64 size, offset;
8ffaadf7
JD		 1812 resource_size_t bar_size;
1813 struct pci_dev *pdev = to_pci_dev(dev->dev);
8969f1f8 1814 int bar;
8ffaadf7 1815
9fe5c59f
KB		 1816 if (dev->cmb_size)
1817 return;
1818
7a67cbea 1819 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
f65efd6d
CH		 1820 if (!dev->cmbsz)
1821 return;
202021c1 1822 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
8ffaadf7 1823
88de4598
CH		 1824 size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
1825 offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
8969f1f8
CH		 1826 bar = NVME_CMB_BIR(dev->cmbloc);
1827 bar_size = pci_resource_len(pdev, bar);
8ffaadf7
JD		 1828
1829 if (offset > bar_size)
f65efd6d 1830 return;
8ffaadf7
JD		 1831
1832 /*
1833 * Controllers may support a CMB size larger than their BAR,
1834 * for example, due to being behind a bridge. Reduce the CMB to
1835 * the reported size of the BAR
1836 */
1837 if (size > bar_size - offset)
1838 size = bar_size - offset;
1839
0f238ff5
LG		 1840 if (pci_p2pdma_add_resource(pdev, bar, size, offset)) {
1841 dev_warn(dev->ctrl.device,
1842 "failed to register the CMB\n");
f65efd6d 1843 return;
0f238ff5
LG		 1844 }
1845
8ffaadf7 1846 dev->cmb_size = size;
0f238ff5
LG		 1847 dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS);
1848
1849 if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) ==
1850 (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS))
1851 pci_p2pmem_publish(pdev, true);
f65efd6d
CH		 1852
1853 if (sysfs_add_file_to_group(&dev->ctrl.device->kobj,
1854 &dev_attr_cmb.attr, NULL))
1855 dev_warn(dev->ctrl.device,
1856 "failed to add sysfs attribute for CMB\n");
8ffaadf7
JD		 1857}
1858
1859static inline void nvme_release_cmb(struct nvme_dev *dev)
1860{
0f238ff5 1861 if (dev->cmb_size) {
1c78f773
MG		 1862 sysfs_remove_file_from_group(&dev->ctrl.device->kobj,
1863 &dev_attr_cmb.attr, NULL);
0f238ff5 1864 dev->cmb_size = 0;
8ffaadf7
JD		 1865 }
1866}
1867
87ad72a5
CH		 1868static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1869{
4033f35d 1870 u64 dma_addr = dev->host_mem_descs_dma;
87ad72a5 1871 struct nvme_command c;
87ad72a5
CH		 1872 int ret;
1873
87ad72a5
CH		 1874 memset(&c, 0, sizeof(c));
1875 c.features.opcode = nvme_admin_set_features;
1876 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1877 c.features.dword11 = cpu_to_le32(bits);
1878 c.features.dword12 = cpu_to_le32(dev->host_mem_size >>
1879 ilog2(dev->ctrl.page_size));
1880 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr));
1881 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr));
1882 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs);
1883
1884 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1885 if (ret) {
1886 dev_warn(dev->ctrl.device,
1887 "failed to set host mem (err %d, flags %#x).\n",
1888 ret, bits);
1889 }
87ad72a5
CH		 1890 return ret;
1891}
1892
1893static void nvme_free_host_mem(struct nvme_dev *dev)
1894{
1895 int i;
1896
1897 for (i = 0; i < dev->nr_host_mem_descs; i++) {
1898 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
1899 size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size;
1900
cc667f6d
LD		 1901 dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i],
1902 le64_to_cpu(desc->addr),
1903 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
87ad72a5
CH		 1904 }
1905
1906 kfree(dev->host_mem_desc_bufs);
1907 dev->host_mem_desc_bufs = NULL;
4033f35d
CH		 1908 dma_free_coherent(dev->dev,
1909 dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
1910 dev->host_mem_descs, dev->host_mem_descs_dma);
87ad72a5 1911 dev->host_mem_descs = NULL;
7e5dd57e 1912 dev->nr_host_mem_descs = 0;
87ad72a5
CH		 1913}
1914
92dc6895
CH		 1915static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
1916 u32 chunk_size)
9d713c2b 1917{
87ad72a5 1918 struct nvme_host_mem_buf_desc *descs;
92dc6895 1919 u32 max_entries, len;
4033f35d 1920 dma_addr_t descs_dma;
2ee0e4ed 1921 int i = 0;
87ad72a5 1922 void **bufs;
6fbcde66 1923 u64 size, tmp;
87ad72a5 1924
87ad72a5
CH		 1925 tmp = (preferred + chunk_size - 1);
1926 do_div(tmp, chunk_size);
1927 max_entries = tmp;
044a9df1
CH		 1928
1929 if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
1930 max_entries = dev->ctrl.hmmaxd;
1931
750afb08
LC		 1932 descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs),
1933 &descs_dma, GFP_KERNEL);
87ad72a5
CH		 1934 if (!descs)
1935 goto out;
1936
1937 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
1938 if (!bufs)
1939 goto out_free_descs;
1940
244a8fe4 1941 for (size = 0; size < preferred && i < max_entries; size += len) {
87ad72a5
CH		 1942 dma_addr_t dma_addr;
1943
50cdb7c6 1944 len = min_t(u64, chunk_size, preferred - size);
87ad72a5
CH		 1945 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
1946 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1947 if (!bufs[i])
1948 break;
1949
1950 descs[i].addr = cpu_to_le64(dma_addr);
1951 descs[i].size = cpu_to_le32(len / dev->ctrl.page_size);
1952 i++;
1953 }
1954
92dc6895 1955 if (!size)
87ad72a5 1956 goto out_free_bufs;
87ad72a5 1957
87ad72a5
CH		 1958 dev->nr_host_mem_descs = i;
1959 dev->host_mem_size = size;
1960 dev->host_mem_descs = descs;
4033f35d 1961 dev->host_mem_descs_dma = descs_dma;
87ad72a5
CH		 1962 dev->host_mem_desc_bufs = bufs;
1963 return 0;
1964
1965out_free_bufs:
1966 while (--i >= 0) {
1967 size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size;
1968
cc667f6d
LD		 1969 dma_free_attrs(dev->dev, size, bufs[i],
1970 le64_to_cpu(descs[i].addr),
1971 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
87ad72a5
CH		 1972 }
1973
1974 kfree(bufs);
1975out_free_descs:
4033f35d
CH		 1976 dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
1977 descs_dma);
87ad72a5 1978out:
87ad72a5
CH		 1979 dev->host_mem_descs = NULL;
1980 return -ENOMEM;
1981}
1982
92dc6895
CH		 1983static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
1984{
1985 u32 chunk_size;
1986
1987 /* start big and work our way down */
30f92d62 1988 for (chunk_size = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
044a9df1 1989 chunk_size >= max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
92dc6895
CH		 1990 chunk_size /= 2) {
1991 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
1992 if (!min || dev->host_mem_size >= min)
1993 return 0;
1994 nvme_free_host_mem(dev);
1995 }
1996 }
1997
1998 return -ENOMEM;
1999}
2000
9620cfba 2001static int nvme_setup_host_mem(struct nvme_dev *dev)
87ad72a5
CH		 2002{
2003 u64 max = (u64)max_host_mem_size_mb * SZ_1M;
2004 u64 preferred = (u64)dev->ctrl.hmpre * 4096;
2005 u64 min = (u64)dev->ctrl.hmmin * 4096;
2006 u32 enable_bits = NVME_HOST_MEM_ENABLE;
6fbcde66 2007 int ret;
87ad72a5
CH		 2008
2009 preferred = min(preferred, max);
2010 if (min > max) {
2011 dev_warn(dev->ctrl.device,
2012 "min host memory (%lld MiB) above limit (%d MiB).\n",
2013 min >> ilog2(SZ_1M), max_host_mem_size_mb);
2014 nvme_free_host_mem(dev);
9620cfba 2015 return 0;
87ad72a5
CH		 2016 }
2017
2018 /*
2019 * If we already have a buffer allocated check if we can reuse it.
2020 */
2021 if (dev->host_mem_descs) {
2022 if (dev->host_mem_size >= min)
2023 enable_bits |= NVME_HOST_MEM_RETURN;
2024 else
2025 nvme_free_host_mem(dev);
2026 }
2027
2028 if (!dev->host_mem_descs) {
92dc6895
CH		 2029 if (nvme_alloc_host_mem(dev, min, preferred)) {
2030 dev_warn(dev->ctrl.device,
2031 "failed to allocate host memory buffer.\n");
9620cfba 2032 return 0; /* controller must work without HMB */
92dc6895
CH		 2033 }
2034
2035 dev_info(dev->ctrl.device,
2036 "allocated %lld MiB host memory buffer.\n",
2037 dev->host_mem_size >> ilog2(SZ_1M));
87ad72a5
CH		 2038 }
2039
9620cfba
CH		 2040 ret = nvme_set_host_mem(dev, enable_bits);
2041 if (ret)
87ad72a5 2042 nvme_free_host_mem(dev);
9620cfba 2043 return ret;
9d713c2b
KB		 2044}
2045
612b7286
ML		 2046/*
2047 * nirqs is the number of interrupts available for write and read
2048 * queues. The core already reserved an interrupt for the admin queue.
2049 */
2050static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs)
3b6592f7 2051{
612b7286
ML		 2052 struct nvme_dev *dev = affd->priv;
2053 unsigned int nr_read_queues;
3b6592f7
JA		 2054
2055 /*
612b7286
ML		 2056 * If there is no interupt available for queues, ensure that
2057 * the default queue is set to 1. The affinity set size is
2058 * also set to one, but the irq core ignores it for this case.
2059 *
2060 * If only one interrupt is available or 'write_queue' == 0, combine
2061 * write and read queues.
2062 *
2063 * If 'write_queues' > 0, ensure it leaves room for at least one read
2064 * queue.
3b6592f7 2065 */
612b7286
ML		 2066 if (!nrirqs) {
2067 nrirqs = 1;
2068 nr_read_queues = 0;
2069 } else if (nrirqs == 1 || !write_queues) {
2070 nr_read_queues = 0;
2071 } else if (write_queues >= nrirqs) {
2072 nr_read_queues = 1;
3b6592f7 2073 } else {
612b7286 2074 nr_read_queues = nrirqs - write_queues;
3b6592f7 2075 }
612b7286
ML		 2076
2077 dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2078 affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2079 dev->io_queues[HCTX_TYPE_READ] = nr_read_queues;
2080 affd->set_size[HCTX_TYPE_READ] = nr_read_queues;
2081 affd->nr_sets = nr_read_queues ? 2 : 1;
3b6592f7
JA		 2082}
2083
6451fe73 2084static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues)
3b6592f7
JA		 2085{
2086 struct pci_dev *pdev = to_pci_dev(dev->dev);
3b6592f7 2087 struct irq_affinity affd = {
9cfef55b 2088 .pre_vectors = 1,
612b7286
ML		 2089 .calc_sets = nvme_calc_irq_sets,
2090 .priv = dev,
3b6592f7 2091 };
6451fe73
JA		 2092 unsigned int irq_queues, this_p_queues;
2093
2094 /*
2095 * Poll queues don't need interrupts, but we need at least one IO
2096 * queue left over for non-polled IO.
2097 */
2098 this_p_queues = poll_queues;
2099 if (this_p_queues >= nr_io_queues) {
2100 this_p_queues = nr_io_queues - 1;
2101 irq_queues = 1;
2102 } else {
c45b1fa2 2103 irq_queues = nr_io_queues - this_p_queues + 1;
6451fe73
JA		 2104 }
2105 dev->io_queues[HCTX_TYPE_POLL] = this_p_queues;
3b6592f7 2106
612b7286
ML		 2107 /* Initialize for the single interrupt case */
2108 dev->io_queues[HCTX_TYPE_DEFAULT] = 1;
2109 dev->io_queues[HCTX_TYPE_READ] = 0;
3b6592f7 2110
612b7286
ML		 2111 return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues,
2112 PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd);
3b6592f7
JA		 2113}
2114
8fae268b
KB		 2115static void nvme_disable_io_queues(struct nvme_dev *dev)
2116{
2117 if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq))
2118 __nvme_disable_io_queues(dev, nvme_admin_delete_cq);
2119}
2120
8d85fce7 2121static int nvme_setup_io_queues(struct nvme_dev *dev)
b60503ba 2122{
147b27e4 2123 struct nvme_queue *adminq = &dev->queues[0];
e75ec752 2124 struct pci_dev *pdev = to_pci_dev(dev->dev);
97f6ef64
XY		 2125 int result, nr_io_queues;
2126 unsigned long size;
b60503ba 2127
3b6592f7 2128 nr_io_queues = max_io_queues();
9a0be7ab
CH		 2129 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
2130 if (result < 0)
1b23484b 2131 return result;
9a0be7ab 2132
f5fa90dc 2133 if (nr_io_queues == 0)
a5229050 2134 return 0;
4e224106
CH		 2135
2136 clear_bit(NVMEQ_ENABLED, &adminq->flags);
b60503ba 2137
0f238ff5 2138 if (dev->cmb_use_sqes) {
8ffaadf7
JD		 2139 result = nvme_cmb_qdepth(dev, nr_io_queues,
2140 sizeof(struct nvme_command));
2141 if (result > 0)
2142 dev->q_depth = result;
2143 else
0f238ff5 2144 dev->cmb_use_sqes = false;
8ffaadf7
JD		 2145 }
2146
97f6ef64
XY		 2147 do {
2148 size = db_bar_size(dev, nr_io_queues);
2149 result = nvme_remap_bar(dev, size);
2150 if (!result)
2151 break;
2152 if (!--nr_io_queues)
2153 return -ENOMEM;
2154 } while (1);
2155 adminq->q_db = dev->dbs;
f1938f6e 2156
8fae268b 2157 retry:
9d713c2b 2158 /* Deregister the admin queue's interrupt */
0ff199cb 2159 pci_free_irq(pdev, 0, adminq);
9d713c2b 2160
e32efbfc
JA		 2161 /*
2162 * If we enable msix early due to not intx, disable it again before
2163 * setting up the full range we need.
2164 */
dca51e78 2165 pci_free_irq_vectors(pdev);
3b6592f7
JA		 2166
2167 result = nvme_setup_irqs(dev, nr_io_queues);
22b55601 2168 if (result <= 0)
dca51e78 2169 return -EIO;
3b6592f7 2170
22b55601 2171 dev->num_vecs = result;
4b04cc6a 2172 result = max(result - 1, 1);
e20ba6e1 2173 dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL];
fa08a396 2174
063a8096
MW		 2175 /*
2176 * Should investigate if there's a performance win from allocating
2177 * more queues than interrupt vectors; it might allow the submission
2178 * path to scale better, even if the receive path is limited by the
2179 * number of interrupts.
2180 */
dca51e78 2181 result = queue_request_irq(adminq);
7c349dde 2182 if (result)
d4875622 2183 return result;
4e224106 2184 set_bit(NVMEQ_ENABLED, &adminq->flags);
8fae268b
KB		 2185
2186 result = nvme_create_io_queues(dev);
2187 if (result || dev->online_queues < 2)
2188 return result;
2189
2190 if (dev->online_queues - 1 < dev->max_qid) {
2191 nr_io_queues = dev->online_queues - 1;
2192 nvme_disable_io_queues(dev);
2193 nvme_suspend_io_queues(dev);
2194 goto retry;
2195 }
2196 dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n",
2197 dev->io_queues[HCTX_TYPE_DEFAULT],
2198 dev->io_queues[HCTX_TYPE_READ],
2199 dev->io_queues[HCTX_TYPE_POLL]);
2200 return 0;
b60503ba
MW		 2201}
2202
2a842aca 2203static void nvme_del_queue_end(struct request *req, blk_status_t error)
a5768aa8 2204{
db3cbfff 2205 struct nvme_queue *nvmeq = req->end_io_data;
b5875222 2206
db3cbfff 2207 blk_mq_free_request(req);
d1ed6aa1 2208 complete(&nvmeq->delete_done);
a5768aa8
KB		 2209}
2210
2a842aca 2211static void nvme_del_cq_end(struct request *req, blk_status_t error)
a5768aa8 2212{
db3cbfff 2213 struct nvme_queue *nvmeq = req->end_io_data;
a5768aa8 2214
d1ed6aa1
CH		 2215 if (error)
2216 set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
db3cbfff
KB		 2217
2218 nvme_del_queue_end(req, error);
a5768aa8
KB		 2219}
2220
db3cbfff 2221static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
bda4e0fb 2222{
db3cbfff
KB		 2223 struct request_queue *q = nvmeq->dev->ctrl.admin_q;
2224 struct request *req;
2225 struct nvme_command cmd;
bda4e0fb 2226
db3cbfff
KB		 2227 memset(&cmd, 0, sizeof(cmd));
2228 cmd.delete_queue.opcode = opcode;
2229 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
bda4e0fb 2230
eb71f435 2231 req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
db3cbfff
KB		 2232 if (IS_ERR(req))
2233 return PTR_ERR(req);
bda4e0fb 2234
db3cbfff
KB		 2235 req->timeout = ADMIN_TIMEOUT;
2236 req->end_io_data = nvmeq;
2237
d1ed6aa1 2238 init_completion(&nvmeq->delete_done);
db3cbfff
KB		 2239 blk_execute_rq_nowait(q, NULL, req, false,
2240 opcode == nvme_admin_delete_cq ?
2241 nvme_del_cq_end : nvme_del_queue_end);
2242 return 0;
bda4e0fb
KB		 2243}
2244
8fae268b 2245static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode)
a5768aa8 2246{
5271edd4 2247 int nr_queues = dev->online_queues - 1, sent = 0;
db3cbfff 2248 unsigned long timeout;
a5768aa8 2249
db3cbfff 2250 retry:
5271edd4
CH		 2251 timeout = ADMIN_TIMEOUT;
2252 while (nr_queues > 0) {
2253 if (nvme_delete_queue(&dev->queues[nr_queues], opcode))
2254 break;
2255 nr_queues--;
2256 sent++;
db3cbfff 2257 }
d1ed6aa1
CH		 2258 while (sent) {
2259 struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent];
2260
2261 timeout = wait_for_completion_io_timeout(&nvmeq->delete_done,
5271edd4
CH		 2262 timeout);
2263 if (timeout == 0)
2264 return false;
d1ed6aa1
CH		 2265
2266 /* handle any remaining CQEs */
2267 if (opcode == nvme_admin_delete_cq &&
2268 !test_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags))
2269 nvme_poll_irqdisable(nvmeq, -1);
2270
2271 sent--;
5271edd4
CH		 2272 if (nr_queues)
2273 goto retry;
2274 }
2275 return true;
a5768aa8
KB		 2276}
2277
422ef0c7 2278/*
2b1b7e78 2279 * return error value only when tagset allocation failed
422ef0c7 2280 */
8d85fce7 2281static int nvme_dev_add(struct nvme_dev *dev)
b60503ba 2282{
2b1b7e78
JW		 2283 int ret;
2284
5bae7f73 2285 if (!dev->ctrl.tagset) {
376f7ef8 2286 dev->tagset.ops = &nvme_mq_ops;
ffe7704d 2287 dev->tagset.nr_hw_queues = dev->online_queues - 1;
ed92ad37
CH		 2288 dev->tagset.nr_maps = 2; /* default + read */
2289 if (dev->io_queues[HCTX_TYPE_POLL])
2290 dev->tagset.nr_maps++;
ffe7704d
KB		 2291 dev->tagset.timeout = NVME_IO_TIMEOUT;
2292 dev->tagset.numa_node = dev_to_node(dev->dev);
2293 dev->tagset.queue_depth =
a4aea562 2294 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
d43f1ccf 2295 dev->tagset.cmd_size = sizeof(struct nvme_iod);
ffe7704d
KB		 2296 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2297 dev->tagset.driver_data = dev;
b60503ba 2298
2b1b7e78
JW		 2299 ret = blk_mq_alloc_tag_set(&dev->tagset);
2300 if (ret) {
2301 dev_warn(dev->ctrl.device,
2302 "IO queues tagset allocation failed %d\n", ret);
2303 return ret;
2304 }
5bae7f73 2305 dev->ctrl.tagset = &dev->tagset;
f9f38e33
HK		 2306
2307 nvme_dbbuf_set(dev);
949928c1
KB		 2308 } else {
2309 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2310
2311 /* Free previously allocated queues that are no longer usable */
2312 nvme_free_queues(dev, dev->online_queues);
ffe7704d 2313 }
949928c1 2314
e1e5e564 2315 return 0;
b60503ba
MW		 2316}
2317
b00a726a 2318static int nvme_pci_enable(struct nvme_dev *dev)
0877cb0d 2319{
b00a726a 2320 int result = -ENOMEM;
e75ec752 2321 struct pci_dev *pdev = to_pci_dev(dev->dev);
0877cb0d
KB		 2322
2323 if (pci_enable_device_mem(pdev))
2324 return result;
2325
0877cb0d 2326 pci_set_master(pdev);
0877cb0d 2327
e75ec752
CH		 2328 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) &&
2329 dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32)))
052d0efa 2330 goto disable;
0877cb0d 2331
7a67cbea 2332 if (readl(dev->bar + NVME_REG_CSTS) == -1) {
0e53d180 2333 result = -ENODEV;
b00a726a 2334 goto disable;
0e53d180 2335 }
e32efbfc
JA		 2336
2337 /*
a5229050
KB		 2338 * Some devices and/or platforms don't advertise or work with INTx
2339 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2340 * adjust this later.
e32efbfc 2341 */
dca51e78
CH		 2342 result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
2343 if (result < 0)
2344 return result;
e32efbfc 2345
20d0dfe6 2346 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
7a67cbea 2347
20d0dfe6 2348 dev->q_depth = min_t(int, NVME_CAP_MQES(dev->ctrl.cap) + 1,
b27c1e68 2349 io_queue_depth);
20d0dfe6 2350 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
7a67cbea 2351 dev->dbs = dev->bar + 4096;
1f390c1f
SG		 2352
2353 /*
2354 * Temporary fix for the Apple controller found in the MacBook8,1 and
2355 * some MacBook7,1 to avoid controller resets and data loss.
2356 */
2357 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
2358 dev->q_depth = 2;
9bdcfb10
CH		 2359 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
2360 "set queue depth=%u to work around controller resets\n",
1f390c1f 2361 dev->q_depth);
d554b5e1
MP		 2362 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2363 (pdev->device == 0xa821 || pdev->device == 0xa822) &&
20d0dfe6 2364 NVME_CAP_MQES(dev->ctrl.cap) == 0) {
d554b5e1
MP		 2365 dev->q_depth = 64;
2366 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2367 "set queue depth=%u\n", dev->q_depth);
1f390c1f
SG		 2368 }
2369
f65efd6d 2370 nvme_map_cmb(dev);
202021c1 2371
a0a3408e
KB		 2372 pci_enable_pcie_error_reporting(pdev);
2373 pci_save_state(pdev);
0877cb0d
KB		 2374 return 0;
2375
2376 disable:
0877cb0d
KB		 2377 pci_disable_device(pdev);
2378 return result;
2379}
2380
2381static void nvme_dev_unmap(struct nvme_dev *dev)
b00a726a
KB		 2382{
2383 if (dev->bar)
2384 iounmap(dev->bar);
a1f447b3 2385 pci_release_mem_regions(to_pci_dev(dev->dev));
b00a726a
KB		 2386}
2387
2388static void nvme_pci_disable(struct nvme_dev *dev)
0877cb0d 2389{
e75ec752
CH		 2390 struct pci_dev *pdev = to_pci_dev(dev->dev);
2391
dca51e78 2392 pci_free_irq_vectors(pdev);
0877cb0d 2393
a0a3408e
KB		 2394 if (pci_is_enabled(pdev)) {
2395 pci_disable_pcie_error_reporting(pdev);
e75ec752 2396 pci_disable_device(pdev);
4d115420 2397 }
4d115420
KB		 2398}
2399
a5cdb68c 2400static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
b60503ba 2401{
302ad8cc
KB		 2402 bool dead = true;
2403 struct pci_dev *pdev = to_pci_dev(dev->dev);
22404274 2404
77bf25ea 2405 mutex_lock(&dev->shutdown_lock);
302ad8cc
KB		 2406 if (pci_is_enabled(pdev)) {
2407 u32 csts = readl(dev->bar + NVME_REG_CSTS);
2408
ebef7368
KB		 2409 if (dev->ctrl.state == NVME_CTRL_LIVE ||
2410 dev->ctrl.state == NVME_CTRL_RESETTING)
302ad8cc
KB		 2411 nvme_start_freeze(&dev->ctrl);
2412 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
2413 pdev->error_state != pci_channel_io_normal);
c9d3bf88 2414 }
c21377f8 2415
302ad8cc
KB		 2416 /*
2417 * Give the controller a chance to complete all entered requests if
2418 * doing a safe shutdown.
2419 */
87ad72a5
CH		 2420 if (!dead) {
2421 if (shutdown)
2422 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
9a915a5b
JW		 2423 }
2424
2425 nvme_stop_queues(&dev->ctrl);
87ad72a5 2426
64ee0ac0 2427 if (!dead && dev->ctrl.queue_count > 0) {
8fae268b 2428 nvme_disable_io_queues(dev);
a5cdb68c 2429 nvme_disable_admin_queue(dev, shutdown);
4d115420 2430 }
8fae268b
KB		 2431 nvme_suspend_io_queues(dev);
2432 nvme_suspend_queue(&dev->queues[0]);
b00a726a 2433 nvme_pci_disable(dev);
07836e65 2434
e1958e65
ML		 2435 blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
2436 blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
302ad8cc
KB		 2437
2438 /*
2439 * The driver will not be starting up queues again if shutting down so
2440 * must flush all entered requests to their failed completion to avoid
2441 * deadlocking blk-mq hot-cpu notifier.
2442 */
2443 if (shutdown)
2444 nvme_start_queues(&dev->ctrl);
77bf25ea 2445 mutex_unlock(&dev->shutdown_lock);
b60503ba
MW		 2446}
2447
091b6092
MW		 2448static int nvme_setup_prp_pools(struct nvme_dev *dev)
2449{
e75ec752 2450 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
091b6092
MW		 2451 PAGE_SIZE, PAGE_SIZE, 0);
2452 if (!dev->prp_page_pool)
2453 return -ENOMEM;
2454
99802a7a 2455 /* Optimisation for I/Os between 4k and 128k */
e75ec752 2456 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
99802a7a
MW		 2457 256, 256, 0);
2458 if (!dev->prp_small_pool) {
2459 dma_pool_destroy(dev->prp_page_pool);
2460 return -ENOMEM;
2461 }
091b6092
MW		 2462 return 0;
2463}
2464
2465static void nvme_release_prp_pools(struct nvme_dev *dev)
2466{
2467 dma_pool_destroy(dev->prp_page_pool);
99802a7a 2468 dma_pool_destroy(dev->prp_small_pool);
091b6092
MW		 2469}
2470
1673f1f0 2471static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
5e82e952 2472{
1673f1f0 2473 struct nvme_dev *dev = to_nvme_dev(ctrl);
9ac27090 2474
f9f38e33 2475 nvme_dbbuf_dma_free(dev);
e75ec752 2476 put_device(dev->dev);
4af0e21c
KB		 2477 if (dev->tagset.tags)
2478 blk_mq_free_tag_set(&dev->tagset);
1c63dc66
CH		 2479 if (dev->ctrl.admin_q)
2480 blk_put_queue(dev->ctrl.admin_q);
5e82e952 2481 kfree(dev->queues);
e286bcfc 2482 free_opal_dev(dev->ctrl.opal_dev);
943e942e 2483 mempool_destroy(dev->iod_mempool);
5e82e952
KB		 2484 kfree(dev);
2485}
2486
f58944e2
KB		 2487static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status)
2488{
237045fc 2489 dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status);
f58944e2 2490
d22524a4 2491 nvme_get_ctrl(&dev->ctrl);
69d9a99c 2492 nvme_dev_disable(dev, false);
9f9cafc1 2493 nvme_kill_queues(&dev->ctrl);
03e0f3a6 2494 if (!queue_work(nvme_wq, &dev->remove_work))
f58944e2
KB		 2495 nvme_put_ctrl(&dev->ctrl);
2496}
2497
fd634f41 2498static void nvme_reset_work(struct work_struct *work)
5e82e952 2499{
d86c4d8e
CH		 2500 struct nvme_dev *dev =
2501 container_of(work, struct nvme_dev, ctrl.reset_work);
a98e58e5 2502 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
f58944e2 2503 int result = -ENODEV;
2b1b7e78 2504 enum nvme_ctrl_state new_state = NVME_CTRL_LIVE;
5e82e952 2505
82b057ca 2506 if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING))
fd634f41 2507 goto out;
5e82e952 2508
fd634f41
CH		 2509 /*
2510 * If we're called to reset a live controller first shut it down before
2511 * moving on.
2512 */
b00a726a 2513 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
a5cdb68c 2514 nvme_dev_disable(dev, false);
5e82e952 2515
5c959d73 2516 mutex_lock(&dev->shutdown_lock);
b00a726a 2517 result = nvme_pci_enable(dev);
f0b50732 2518 if (result)
4726bcf3 2519 goto out_unlock;
f0b50732 2520
01ad0990 2521 result = nvme_pci_configure_admin_queue(dev);
f0b50732 2522 if (result)
4726bcf3 2523 goto out_unlock;
f0b50732 2524
0fb59cbc
KB		 2525 result = nvme_alloc_admin_tags(dev);
2526 if (result)
4726bcf3 2527 goto out_unlock;
b9afca3e 2528
943e942e
JA		 2529 /*
2530 * Limit the max command size to prevent iod->sg allocations going
2531 * over a single page.
2532 */
2533 dev->ctrl.max_hw_sectors = NVME_MAX_KB_SZ << 1;
2534 dev->ctrl.max_segments = NVME_MAX_SEGS;
5c959d73
KB		 2535 mutex_unlock(&dev->shutdown_lock);
2536
2537 /*
2538 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
2539 * initializing procedure here.
2540 */
2541 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
2542 dev_warn(dev->ctrl.device,
2543 "failed to mark controller CONNECTING\n");
2544 goto out;
2545 }
943e942e 2546
ce4541f4
CH		 2547 result = nvme_init_identify(&dev->ctrl);
2548 if (result)
f58944e2 2549 goto out;
ce4541f4 2550
e286bcfc
SB		 2551 if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
2552 if (!dev->ctrl.opal_dev)
2553 dev->ctrl.opal_dev =
2554 init_opal_dev(&dev->ctrl, &nvme_sec_submit);
2555 else if (was_suspend)
2556 opal_unlock_from_suspend(dev->ctrl.opal_dev);
2557 } else {
2558 free_opal_dev(dev->ctrl.opal_dev);
2559 dev->ctrl.opal_dev = NULL;
4f1244c8 2560 }
a98e58e5 2561
f9f38e33
HK		 2562 if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) {
2563 result = nvme_dbbuf_dma_alloc(dev);
2564 if (result)
2565 dev_warn(dev->dev,
2566 "unable to allocate dma for dbbuf\n");
2567 }
2568
9620cfba
CH		 2569 if (dev->ctrl.hmpre) {
2570 result = nvme_setup_host_mem(dev);
2571 if (result < 0)
2572 goto out;
2573 }
87ad72a5 2574
f0b50732 2575 result = nvme_setup_io_queues(dev);
badc34d4 2576 if (result)
f58944e2 2577 goto out;
f0b50732 2578
2659e57b
CH		 2579 /*
2580 * Keep the controller around but remove all namespaces if we don't have
2581 * any working I/O queue.
2582 */
3cf519b5 2583 if (dev->online_queues < 2) {
1b3c47c1 2584 dev_warn(dev->ctrl.device, "IO queues not created\n");
3b24774e 2585 nvme_kill_queues(&dev->ctrl);
5bae7f73 2586 nvme_remove_namespaces(&dev->ctrl);
2b1b7e78 2587 new_state = NVME_CTRL_ADMIN_ONLY;
3cf519b5 2588 } else {
25646264 2589 nvme_start_queues(&dev->ctrl);
302ad8cc 2590 nvme_wait_freeze(&dev->ctrl);
2b1b7e78
JW		 2591 /* hit this only when allocate tagset fails */
2592 if (nvme_dev_add(dev))
2593 new_state = NVME_CTRL_ADMIN_ONLY;
302ad8cc 2594 nvme_unfreeze(&dev->ctrl);
3cf519b5
CH		 2595 }
2596
2b1b7e78
JW		 2597 /*
2598 * If only admin queue live, keep it to do further investigation or
2599 * recovery.
2600 */
2601 if (!nvme_change_ctrl_state(&dev->ctrl, new_state)) {
2602 dev_warn(dev->ctrl.device,
2603 "failed to mark controller state %d\n", new_state);
bb8d261e
CH		 2604 goto out;
2605 }
92911a55 2606
d09f2b45 2607 nvme_start_ctrl(&dev->ctrl);
3cf519b5 2608 return;
f0b50732 2609
4726bcf3
KB		 2610 out_unlock:
2611 mutex_unlock(&dev->shutdown_lock);
3cf519b5 2612 out:
f58944e2 2613 nvme_remove_dead_ctrl(dev, result);
f0b50732
KB		 2614}
2615
5c8809e6 2616static void nvme_remove_dead_ctrl_work(struct work_struct *work)
9a6b9458 2617{
5c8809e6 2618 struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
e75ec752 2619 struct pci_dev *pdev = to_pci_dev(dev->dev);
9a6b9458
KB		 2620
2621 if (pci_get_drvdata(pdev))
921920ab 2622 device_release_driver(&pdev->dev);
1673f1f0 2623 nvme_put_ctrl(&dev->ctrl);
9a6b9458
KB		 2624}
2625
1c63dc66 2626static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
9ca97374 2627{
1c63dc66 2628 *val = readl(to_nvme_dev(ctrl)->bar + off);
90667892 2629 return 0;
9ca97374
TH		 2630}
2631
5fd4ce1b 2632static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
4cc06521 2633{
5fd4ce1b
CH		 2634 writel(val, to_nvme_dev(ctrl)->bar + off);
2635 return 0;
2636}
4cc06521 2637
7fd8930f
CH		 2638static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2639{
2640 *val = readq(to_nvme_dev(ctrl)->bar + off);
2641 return 0;
4cc06521
KB		 2642}
2643
97c12223
KB		 2644static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
2645{
2646 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2647
2648 return snprintf(buf, size, "%s", dev_name(&pdev->dev));
2649}
2650
1c63dc66 2651static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
1a353d85 2652 .name = "pcie",
e439bb12 2653 .module = THIS_MODULE,
e0596ab2
LG		 2654 .flags = NVME_F_METADATA_SUPPORTED |
2655 NVME_F_PCI_P2PDMA,
1c63dc66 2656 .reg_read32 = nvme_pci_reg_read32,
5fd4ce1b 2657 .reg_write32 = nvme_pci_reg_write32,
7fd8930f 2658 .reg_read64 = nvme_pci_reg_read64,
1673f1f0 2659 .free_ctrl = nvme_pci_free_ctrl,
f866fc42 2660 .submit_async_event = nvme_pci_submit_async_event,
97c12223 2661 .get_address = nvme_pci_get_address,
1c63dc66 2662};
4cc06521 2663
b00a726a
KB		 2664static int nvme_dev_map(struct nvme_dev *dev)
2665{
b00a726a
KB		 2666 struct pci_dev *pdev = to_pci_dev(dev->dev);
2667
a1f447b3 2668 if (pci_request_mem_regions(pdev, "nvme"))
b00a726a
KB		 2669 return -ENODEV;
2670
97f6ef64 2671 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
b00a726a
KB		 2672 goto release;
2673
9fa196e7 2674 return 0;
b00a726a 2675 release:
9fa196e7
MG		 2676 pci_release_mem_regions(pdev);
2677 return -ENODEV;
b00a726a
KB		 2678}
2679
8427bbc2 2680static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
ff5350a8
AL		 2681{
2682 if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
2683 /*
2684 * Several Samsung devices seem to drop off the PCIe bus
2685 * randomly when APST is on and uses the deepest sleep state.
2686 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2687 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2688 * 950 PRO 256GB", but it seems to be restricted to two Dell
2689 * laptops.
2690 */
2691 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
2692 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
2693 dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
2694 return NVME_QUIRK_NO_DEEPEST_PS;
8427bbc2
KHF		 2695 } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
2696 /*
2697 * Samsung SSD 960 EVO drops off the PCIe bus after system
467c77d4
JJ		 2698 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
2699 * within few minutes after bootup on a Coffee Lake board -
2700 * ASUS PRIME Z370-A
8427bbc2
KHF		 2701 */
2702 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
467c77d4
JJ		 2703 (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") ||
2704 dmi_match(DMI_BOARD_NAME, "PRIME Z370-A")))
8427bbc2 2705 return NVME_QUIRK_NO_APST;
ff5350a8
AL		 2706 }
2707
2708 return 0;
2709}
2710
18119775
KB		 2711static void nvme_async_probe(void *data, async_cookie_t cookie)
2712{
2713 struct nvme_dev *dev = data;
80f513b5 2714
18119775
KB		 2715 nvme_reset_ctrl_sync(&dev->ctrl);
2716 flush_work(&dev->ctrl.scan_work);
80f513b5 2717 nvme_put_ctrl(&dev->ctrl);
18119775
KB		 2718}
2719
8d85fce7 2720static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
b60503ba 2721{
a4aea562 2722 int node, result = -ENOMEM;
b60503ba 2723 struct nvme_dev *dev;
ff5350a8 2724 unsigned long quirks = id->driver_data;
943e942e 2725 size_t alloc_size;
b60503ba 2726
a4aea562
MB		 2727 node = dev_to_node(&pdev->dev);
2728 if (node == NUMA_NO_NODE)
2fa84351 2729 set_dev_node(&pdev->dev, first_memory_node);
a4aea562
MB		 2730
2731 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
b60503ba
MW		 2732 if (!dev)
2733 return -ENOMEM;
147b27e4 2734
3b6592f7
JA		 2735 dev->queues = kcalloc_node(max_queue_count(), sizeof(struct nvme_queue),
2736 GFP_KERNEL, node);
b60503ba
MW		 2737 if (!dev->queues)
2738 goto free;
2739
e75ec752 2740 dev->dev = get_device(&pdev->dev);
9a6b9458 2741 pci_set_drvdata(pdev, dev);
1c63dc66 2742
b00a726a
KB		 2743 result = nvme_dev_map(dev);
2744 if (result)
b00c9b7a 2745 goto put_pci;
b00a726a 2746
d86c4d8e 2747 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
5c8809e6 2748 INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
77bf25ea 2749 mutex_init(&dev->shutdown_lock);
b60503ba 2750
091b6092
MW		 2751 result = nvme_setup_prp_pools(dev);
2752 if (result)
b00c9b7a 2753 goto unmap;
4cc06521 2754
8427bbc2 2755 quirks |= check_vendor_combination_bug(pdev);
ff5350a8 2756
943e942e
JA		 2757 /*
2758 * Double check that our mempool alloc size will cover the biggest
2759 * command we support.
2760 */
2761 alloc_size = nvme_pci_iod_alloc_size(dev, NVME_MAX_KB_SZ,
2762 NVME_MAX_SEGS, true);
2763 WARN_ON_ONCE(alloc_size > PAGE_SIZE);
2764
2765 dev->iod_mempool = mempool_create_node(1, mempool_kmalloc,
2766 mempool_kfree,
2767 (void *) alloc_size,
2768 GFP_KERNEL, node);
2769 if (!dev->iod_mempool) {
2770 result = -ENOMEM;
2771 goto release_pools;
2772 }
2773
b6e44b4c
KB		 2774 result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
2775 quirks);
2776 if (result)
2777 goto release_mempool;
2778
1b3c47c1
SG		 2779 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
2780
80f513b5 2781 nvme_get_ctrl(&dev->ctrl);
18119775 2782 async_schedule(nvme_async_probe, dev);
4caff8fc 2783
b60503ba
MW		 2784 return 0;
2785
b6e44b4c
KB		 2786 release_mempool:
2787 mempool_destroy(dev->iod_mempool);
0877cb0d 2788 release_pools:
091b6092 2789 nvme_release_prp_pools(dev);
b00c9b7a
CJ		 2790 unmap:
2791 nvme_dev_unmap(dev);
a96d4f5c 2792 put_pci:
e75ec752 2793 put_device(dev->dev);
b60503ba
MW		 2794 free:
2795 kfree(dev->queues);
b60503ba
MW		 2796 kfree(dev);
2797 return result;
2798}
2799
775755ed 2800static void nvme_reset_prepare(struct pci_dev *pdev)
f0d54a54 2801{
a6739479 2802 struct nvme_dev *dev = pci_get_drvdata(pdev);
f263fbb8 2803 nvme_dev_disable(dev, false);
775755ed 2804}
f0d54a54 2805
775755ed
CH		 2806static void nvme_reset_done(struct pci_dev *pdev)
2807{
f263fbb8 2808 struct nvme_dev *dev = pci_get_drvdata(pdev);
79c48ccf 2809 nvme_reset_ctrl_sync(&dev->ctrl);
f0d54a54
KB		 2810}
2811
09ece142
KB		 2812static void nvme_shutdown(struct pci_dev *pdev)
2813{
2814 struct nvme_dev *dev = pci_get_drvdata(pdev);
a5cdb68c 2815 nvme_dev_disable(dev, true);
09ece142
KB		 2816}
2817
f58944e2
KB		 2818/*
2819 * The driver's remove may be called on a device in a partially initialized
2820 * state. This function must not have any dependencies on the device state in
2821 * order to proceed.
2822 */
8d85fce7 2823static void nvme_remove(struct pci_dev *pdev)
b60503ba
MW		 2824{
2825 struct nvme_dev *dev = pci_get_drvdata(pdev);
9a6b9458 2826
bb8d261e 2827 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
9a6b9458 2828 pci_set_drvdata(pdev, NULL);
0ff9d4e1 2829
6db28eda 2830 if (!pci_device_is_present(pdev)) {
0ff9d4e1 2831 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
1d39e692 2832 nvme_dev_disable(dev, true);
cb4bfda6 2833 nvme_dev_remove_admin(dev);
6db28eda 2834 }
0ff9d4e1 2835
d86c4d8e 2836 flush_work(&dev->ctrl.reset_work);
d09f2b45
SG		 2837 nvme_stop_ctrl(&dev->ctrl);
2838 nvme_remove_namespaces(&dev->ctrl);
a5cdb68c 2839 nvme_dev_disable(dev, true);
9fe5c59f 2840 nvme_release_cmb(dev);
87ad72a5 2841 nvme_free_host_mem(dev);
a4aea562 2842 nvme_dev_remove_admin(dev);
a1a5ef99 2843 nvme_free_queues(dev, 0);
d09f2b45 2844 nvme_uninit_ctrl(&dev->ctrl);
9a6b9458 2845 nvme_release_prp_pools(dev);
b00a726a 2846 nvme_dev_unmap(dev);
1673f1f0 2847 nvme_put_ctrl(&dev->ctrl);
b60503ba
MW		 2848}
2849
671a6018 2850#ifdef CONFIG_PM_SLEEP
cd638946
KB		 2851static int nvme_suspend(struct device *dev)
2852{
2853 struct pci_dev *pdev = to_pci_dev(dev);
2854 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2855
a5cdb68c 2856 nvme_dev_disable(ndev, true);
cd638946
KB		 2857 return 0;
2858}
2859
2860static int nvme_resume(struct device *dev)
2861{
2862 struct pci_dev *pdev = to_pci_dev(dev);
2863 struct nvme_dev *ndev = pci_get_drvdata(pdev);
cd638946 2864
d86c4d8e 2865 nvme_reset_ctrl(&ndev->ctrl);
9a6b9458 2866 return 0;
cd638946 2867}
671a6018 2868#endif
cd638946
KB		 2869
2870static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
b60503ba 2871
a0a3408e
KB		 2872static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
2873 pci_channel_state_t state)
2874{
2875 struct nvme_dev *dev = pci_get_drvdata(pdev);
2876
2877 /*
2878 * A frozen channel requires a reset. When detected, this method will
2879 * shutdown the controller to quiesce. The controller will be restarted
2880 * after the slot reset through driver's slot_reset callback.
2881 */
a0a3408e
KB		 2882 switch (state) {
2883 case pci_channel_io_normal:
2884 return PCI_ERS_RESULT_CAN_RECOVER;
2885 case pci_channel_io_frozen:
d011fb31
KB		 2886 dev_warn(dev->ctrl.device,
2887 "frozen state error detected, reset controller\n");
a5cdb68c 2888 nvme_dev_disable(dev, false);
a0a3408e
KB		 2889 return PCI_ERS_RESULT_NEED_RESET;
2890 case pci_channel_io_perm_failure:
d011fb31
KB		 2891 dev_warn(dev->ctrl.device,
2892 "failure state error detected, request disconnect\n");
a0a3408e
KB		 2893 return PCI_ERS_RESULT_DISCONNECT;
2894 }
2895 return PCI_ERS_RESULT_NEED_RESET;
2896}
2897
2898static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
2899{
2900 struct nvme_dev *dev = pci_get_drvdata(pdev);
2901
1b3c47c1 2902 dev_info(dev->ctrl.device, "restart after slot reset\n");
a0a3408e 2903 pci_restore_state(pdev);
d86c4d8e 2904 nvme_reset_ctrl(&dev->ctrl);
a0a3408e
KB		 2905 return PCI_ERS_RESULT_RECOVERED;
2906}
2907
2908static void nvme_error_resume(struct pci_dev *pdev)
2909{
72cd4cc2
KB		 2910 struct nvme_dev *dev = pci_get_drvdata(pdev);
2911
2912 flush_work(&dev->ctrl.reset_work);
a0a3408e
KB		 2913}
2914
1d352035 2915static const struct pci_error_handlers nvme_err_handler = {
b60503ba 2916 .error_detected = nvme_error_detected,
b60503ba
MW		 2917 .slot_reset = nvme_slot_reset,
2918 .resume = nvme_error_resume,
775755ed
CH		 2919 .reset_prepare = nvme_reset_prepare,
2920 .reset_done = nvme_reset_done,
b60503ba
MW		 2921};
2922
6eb0d698 2923static const struct pci_device_id nvme_id_table[] = {
106198ed 2924 { PCI_VDEVICE(INTEL, 0x0953),
08095e70 2925 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 2926 NVME_QUIRK_DEALLOCATE_ZEROES, },
99466e70
KB		 2927 { PCI_VDEVICE(INTEL, 0x0a53),
2928 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 2929 NVME_QUIRK_DEALLOCATE_ZEROES, },
99466e70
KB		 2930 { PCI_VDEVICE(INTEL, 0x0a54),
2931 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 2932 NVME_QUIRK_DEALLOCATE_ZEROES, },
f99cb7af
DWF		 2933 { PCI_VDEVICE(INTEL, 0x0a55),
2934 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2935 NVME_QUIRK_DEALLOCATE_ZEROES, },
50af47d0 2936 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */
9abd68ef
JA		 2937 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
2938 NVME_QUIRK_MEDIUM_PRIO_SQ },
6299358d
JD		 2939 { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */
2940 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
540c801c 2941 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */
7b210e4e
CH		 2942 .driver_data = NVME_QUIRK_IDENTIFY_CNS |
2943 NVME_QUIRK_DISABLE_WRITE_ZEROES, },
0302ae60
MP		 2944 { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */
2945 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
54adc010
GP		 2946 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
2947 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
8c97eecc
JL		 2948 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */
2949 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
015282c9
WW		 2950 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
2951 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
d554b5e1
MP		 2952 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */
2953 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2954 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */
2955 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
608cc4b1
CH		 2956 { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */
2957 .driver_data = NVME_QUIRK_LIGHTNVM, },
2958 { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */
2959 .driver_data = NVME_QUIRK_LIGHTNVM, },
ea48e877
WX		 2960 { PCI_DEVICE(0x1d1d, 0x2601), /* CNEX Granby */
2961 .driver_data = NVME_QUIRK_LIGHTNVM, },
b60503ba 2962 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
c74dc780 2963 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) },
124298bd 2964 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
b60503ba
MW		 2965 { 0, }
2966};
2967MODULE_DEVICE_TABLE(pci, nvme_id_table);
2968
2969static struct pci_driver nvme_driver = {
2970 .name = "nvme",
2971 .id_table = nvme_id_table,
2972 .probe = nvme_probe,
8d85fce7 2973 .remove = nvme_remove,
09ece142 2974 .shutdown = nvme_shutdown,
cd638946
KB		 2975 .driver = {
2976 .pm = &nvme_dev_pm_ops,
2977 },
74d986ab 2978 .sriov_configure = pci_sriov_configure_simple,
b60503ba
MW		 2979 .err_handler = &nvme_err_handler,
2980};
2981
2982static int __init nvme_init(void)
2983{
612b7286 2984 BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2);
9a6327d2 2985 return pci_register_driver(&nvme_driver);
b60503ba
MW		 2986}
2987
2988static void __exit nvme_exit(void)
2989{
2990 pci_unregister_driver(&nvme_driver);
03e0f3a6 2991 flush_workqueue(nvme_wq);
21bd78bc 2992 _nvme_check_size();
b60503ba
MW		 2993}
2994
2995MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2996MODULE_LICENSE("GPL");
c78b4713 2997MODULE_VERSION("1.0");
b60503ba
MW		 2998module_init(nvme_init);
2999module_exit(nvme_exit);
Linux 6.x block layer and io_uring tree(s)