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nvme-pci: check segement valid for SGL use
[linux-2.6-block.git] / drivers / nvme / host / pci.c
CommitLineData
b60503ba
MW		 1/*
2 * NVM Express device driver
6eb0d698 3 * Copyright (c) 2011-2014, Intel Corporation.
b60503ba
MW		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
b60503ba
MW		 13 */
14
a0a3408e 15#include <linux/aer.h>
b60503ba 16#include <linux/blkdev.h>
a4aea562 17#include <linux/blk-mq.h>
dca51e78 18#include <linux/blk-mq-pci.h>
ff5350a8 19#include <linux/dmi.h>
b60503ba
MW		 20#include <linux/init.h>
21#include <linux/interrupt.h>
22#include <linux/io.h>
b60503ba
MW		 23#include <linux/mm.h>
24#include <linux/module.h>
77bf25ea 25#include <linux/mutex.h>
d0877473 26#include <linux/once.h>
b60503ba 27#include <linux/pci.h>
e1e5e564 28#include <linux/t10-pi.h>
b60503ba 29#include <linux/types.h>
2f8e2c87 30#include <linux/io-64-nonatomic-lo-hi.h>
a98e58e5 31#include <linux/sed-opal.h>
797a796a 32
f11bb3e2
CH		 33#include "nvme.h"
34
b60503ba
MW		 35#define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
36#define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
c965809c 37
a7a7cbe3 38#define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc))
9d43cf64 39
58ffacb5
MW		 40static int use_threaded_interrupts;
41module_param(use_threaded_interrupts, int, 0);
42
8ffaadf7
JD		 43static bool use_cmb_sqes = true;
44module_param(use_cmb_sqes, bool, 0644);
45MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
46
87ad72a5
CH		 47static unsigned int max_host_mem_size_mb = 128;
48module_param(max_host_mem_size_mb, uint, 0444);
49MODULE_PARM_DESC(max_host_mem_size_mb,
50 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
1fa6aead 51
a7a7cbe3
CK		 52static unsigned int sgl_threshold = SZ_32K;
53module_param(sgl_threshold, uint, 0644);
54MODULE_PARM_DESC(sgl_threshold,
55 "Use SGLs when average request segment size is larger or equal to "
56 "this size. Use 0 to disable SGLs.");
57
b27c1e68 58static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
59static const struct kernel_param_ops io_queue_depth_ops = {
60 .set = io_queue_depth_set,
61 .get = param_get_int,
62};
63
64static int io_queue_depth = 1024;
65module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
66MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2");
67
1c63dc66
CH		 68struct nvme_dev;
69struct nvme_queue;
b3fffdef 70
a0fa9647 71static void nvme_process_cq(struct nvme_queue *nvmeq);
a5cdb68c 72static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
d4b4ff8e 73
1c63dc66
CH		 74/*
75 * Represents an NVM Express device. Each nvme_dev is a PCI function.
76 */
77struct nvme_dev {
1c63dc66
CH		 78 struct nvme_queue **queues;
79 struct blk_mq_tag_set tagset;
80 struct blk_mq_tag_set admin_tagset;
81 u32 __iomem *dbs;
82 struct device *dev;
83 struct dma_pool *prp_page_pool;
84 struct dma_pool *prp_small_pool;
1c63dc66
CH		 85 unsigned online_queues;
86 unsigned max_qid;
87 int q_depth;
88 u32 db_stride;
1c63dc66 89 void __iomem *bar;
97f6ef64 90 unsigned long bar_mapped_size;
5c8809e6 91 struct work_struct remove_work;
77bf25ea 92 struct mutex shutdown_lock;
1c63dc66 93 bool subsystem;
1c63dc66 94 void __iomem *cmb;
8969f1f8 95 pci_bus_addr_t cmb_bus_addr;
1c63dc66
CH		 96 u64 cmb_size;
97 u32 cmbsz;
202021c1 98 u32 cmbloc;
1c63dc66 99 struct nvme_ctrl ctrl;
db3cbfff 100 struct completion ioq_wait;
87ad72a5
CH		 101
102 /* shadow doorbell buffer support: */
f9f38e33
HK		 103 u32 *dbbuf_dbs;
104 dma_addr_t dbbuf_dbs_dma_addr;
105 u32 *dbbuf_eis;
106 dma_addr_t dbbuf_eis_dma_addr;
87ad72a5
CH		 107
108 /* host memory buffer support: */
109 u64 host_mem_size;
110 u32 nr_host_mem_descs;
4033f35d 111 dma_addr_t host_mem_descs_dma;
87ad72a5
CH		 112 struct nvme_host_mem_buf_desc *host_mem_descs;
113 void **host_mem_desc_bufs;
4d115420 114};
1fa6aead 115
b27c1e68 116static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
117{
118 int n = 0, ret;
119
120 ret = kstrtoint(val, 10, &n);
121 if (ret != 0 || n < 2)
122 return -EINVAL;
123
124 return param_set_int(val, kp);
125}
126
f9f38e33
HK		 127static inline unsigned int sq_idx(unsigned int qid, u32 stride)
128{
129 return qid * 2 * stride;
130}
131
132static inline unsigned int cq_idx(unsigned int qid, u32 stride)
133{
134 return (qid * 2 + 1) * stride;
135}
136
1c63dc66
CH		 137static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
138{
139 return container_of(ctrl, struct nvme_dev, ctrl);
140}
141
b60503ba
MW		 142/*
143 * An NVM Express queue. Each device has at least two (one for admin
144 * commands and one for I/O commands).
145 */
146struct nvme_queue {
147 struct device *q_dmadev;
091b6092 148 struct nvme_dev *dev;
b60503ba
MW		 149 spinlock_t q_lock;
150 struct nvme_command *sq_cmds;
8ffaadf7 151 struct nvme_command __iomem *sq_cmds_io;
b60503ba 152 volatile struct nvme_completion *cqes;
42483228 153 struct blk_mq_tags **tags;
b60503ba
MW		 154 dma_addr_t sq_dma_addr;
155 dma_addr_t cq_dma_addr;
b60503ba
MW		 156 u32 __iomem *q_db;
157 u16 q_depth;
6222d172 158 s16 cq_vector;
b60503ba
MW		 159 u16 sq_tail;
160 u16 cq_head;
c30341dc 161 u16 qid;
e9539f47
MW		 162 u8 cq_phase;
163 u8 cqe_seen;
f9f38e33
HK		 164 u32 *dbbuf_sq_db;
165 u32 *dbbuf_cq_db;
166 u32 *dbbuf_sq_ei;
167 u32 *dbbuf_cq_ei;
b60503ba
MW		 168};
169
71bd150c
CH		 170/*
171 * The nvme_iod describes the data in an I/O, including the list of PRP
172 * entries. You can't see it in this data structure because C doesn't let
f4800d6d 173 * me express that. Use nvme_init_iod to ensure there's enough space
71bd150c
CH		 174 * allocated to store the PRP list.
175 */
176struct nvme_iod {
d49187e9 177 struct nvme_request req;
f4800d6d 178 struct nvme_queue *nvmeq;
a7a7cbe3 179 bool use_sgl;
f4800d6d 180 int aborted;
71bd150c 181 int npages; /* In the PRP list. 0 means small pool in use */
71bd150c
CH		 182 int nents; /* Used in scatterlist */
183 int length; /* Of data, in bytes */
184 dma_addr_t first_dma;
bf684057 185 struct scatterlist meta_sg; /* metadata requires single contiguous buffer */
f4800d6d
CH		 186 struct scatterlist *sg;
187 struct scatterlist inline_sg[0];
b60503ba
MW		 188};
189
190/*
191 * Check we didin't inadvertently grow the command struct
192 */
193static inline void _nvme_check_size(void)
194{
195 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
196 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
197 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
198 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
199 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
f8ebf840 200 BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
c30341dc 201 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
b60503ba 202 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
0add5e8e
JT		 203 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != NVME_IDENTIFY_DATA_SIZE);
204 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != NVME_IDENTIFY_DATA_SIZE);
b60503ba 205 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
6ecec745 206 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
f9f38e33
HK		 207 BUILD_BUG_ON(sizeof(struct nvme_dbbuf) != 64);
208}
209
210static inline unsigned int nvme_dbbuf_size(u32 stride)
211{
212 return ((num_possible_cpus() + 1) * 8 * stride);
213}
214
215static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
216{
217 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
218
219 if (dev->dbbuf_dbs)
220 return 0;
221
222 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
223 &dev->dbbuf_dbs_dma_addr,
224 GFP_KERNEL);
225 if (!dev->dbbuf_dbs)
226 return -ENOMEM;
227 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
228 &dev->dbbuf_eis_dma_addr,
229 GFP_KERNEL);
230 if (!dev->dbbuf_eis) {
231 dma_free_coherent(dev->dev, mem_size,
232 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
233 dev->dbbuf_dbs = NULL;
234 return -ENOMEM;
235 }
236
237 return 0;
238}
239
240static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
241{
242 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
243
244 if (dev->dbbuf_dbs) {
245 dma_free_coherent(dev->dev, mem_size,
246 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
247 dev->dbbuf_dbs = NULL;
248 }
249 if (dev->dbbuf_eis) {
250 dma_free_coherent(dev->dev, mem_size,
251 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
252 dev->dbbuf_eis = NULL;
253 }
254}
255
256static void nvme_dbbuf_init(struct nvme_dev *dev,
257 struct nvme_queue *nvmeq, int qid)
258{
259 if (!dev->dbbuf_dbs || !qid)
260 return;
261
262 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
263 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
264 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
265 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
266}
267
268static void nvme_dbbuf_set(struct nvme_dev *dev)
269{
270 struct nvme_command c;
271
272 if (!dev->dbbuf_dbs)
273 return;
274
275 memset(&c, 0, sizeof(c));
276 c.dbbuf.opcode = nvme_admin_dbbuf;
277 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
278 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
279
280 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
9bdcfb10 281 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
f9f38e33
HK		 282 /* Free memory and continue on */
283 nvme_dbbuf_dma_free(dev);
284 }
285}
286
287static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
288{
289 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
290}
291
292/* Update dbbuf and return true if an MMIO is required */
293static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
294 volatile u32 *dbbuf_ei)
295{
296 if (dbbuf_db) {
297 u16 old_value;
298
299 /*
300 * Ensure that the queue is written before updating
301 * the doorbell in memory
302 */
303 wmb();
304
305 old_value = *dbbuf_db;
306 *dbbuf_db = value;
307
308 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value))
309 return false;
310 }
311
312 return true;
b60503ba
MW		 313}
314
ac3dd5bd
JA		 315/*
316 * Max size of iod being embedded in the request payload
317 */
318#define NVME_INT_PAGES 2
5fd4ce1b 319#define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size)
ac3dd5bd
JA		 320
321/*
322 * Will slightly overestimate the number of pages needed. This is OK
323 * as it only leads to a small amount of wasted memory for the lifetime of
324 * the I/O.
325 */
326static int nvme_npages(unsigned size, struct nvme_dev *dev)
327{
5fd4ce1b
CH		 328 unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size,
329 dev->ctrl.page_size);
ac3dd5bd
JA		 330 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
331}
332
a7a7cbe3
CK		 333/*
334 * Calculates the number of pages needed for the SGL segments. For example a 4k
335 * page can accommodate 256 SGL descriptors.
336 */
337static int nvme_pci_npages_sgl(unsigned int num_seg)
ac3dd5bd 338{
a7a7cbe3 339 return DIV_ROUND_UP(num_seg * sizeof(struct nvme_sgl_desc), PAGE_SIZE);
f4800d6d 340}
ac3dd5bd 341
a7a7cbe3
CK		 342static unsigned int nvme_pci_iod_alloc_size(struct nvme_dev *dev,
343 unsigned int size, unsigned int nseg, bool use_sgl)
f4800d6d 344{
a7a7cbe3
CK		 345 size_t alloc_size;
346
347 if (use_sgl)
348 alloc_size = sizeof(__le64 *) * nvme_pci_npages_sgl(nseg);
349 else
350 alloc_size = sizeof(__le64 *) * nvme_npages(size, dev);
351
352 return alloc_size + sizeof(struct scatterlist) * nseg;
f4800d6d 353}
ac3dd5bd 354
a7a7cbe3 355static unsigned int nvme_pci_cmd_size(struct nvme_dev *dev, bool use_sgl)
f4800d6d 356{
a7a7cbe3
CK		 357 unsigned int alloc_size = nvme_pci_iod_alloc_size(dev,
358 NVME_INT_BYTES(dev), NVME_INT_PAGES,
359 use_sgl);
360
361 return sizeof(struct nvme_iod) + alloc_size;
ac3dd5bd
JA		 362}
363
a4aea562
MB		 364static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
365 unsigned int hctx_idx)
e85248e5 366{
a4aea562
MB		 367 struct nvme_dev *dev = data;
368 struct nvme_queue *nvmeq = dev->queues[0];
369
42483228
KB		 370 WARN_ON(hctx_idx != 0);
371 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
372 WARN_ON(nvmeq->tags);
373
a4aea562 374 hctx->driver_data = nvmeq;
42483228 375 nvmeq->tags = &dev->admin_tagset.tags[0];
a4aea562 376 return 0;
e85248e5
MW		 377}
378
4af0e21c
KB		 379static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
380{
381 struct nvme_queue *nvmeq = hctx->driver_data;
382
383 nvmeq->tags = NULL;
384}
385
a4aea562
MB		 386static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
387 unsigned int hctx_idx)
b60503ba 388{
a4aea562 389 struct nvme_dev *dev = data;
42483228 390 struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
a4aea562 391
42483228
KB		 392 if (!nvmeq->tags)
393 nvmeq->tags = &dev->tagset.tags[hctx_idx];
b60503ba 394
42483228 395 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
a4aea562
MB		 396 hctx->driver_data = nvmeq;
397 return 0;
b60503ba
MW		 398}
399
d6296d39
CH		 400static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req,
401 unsigned int hctx_idx, unsigned int numa_node)
b60503ba 402{
d6296d39 403 struct nvme_dev *dev = set->driver_data;
f4800d6d 404 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
0350815a
CH		 405 int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0;
406 struct nvme_queue *nvmeq = dev->queues[queue_idx];
a4aea562
MB		 407
408 BUG_ON(!nvmeq);
f4800d6d 409 iod->nvmeq = nvmeq;
a4aea562
MB		 410 return 0;
411}
412
dca51e78
CH		 413static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
414{
415 struct nvme_dev *dev = set->driver_data;
416
417 return blk_mq_pci_map_queues(set, to_pci_dev(dev->dev));
418}
419
b60503ba 420/**
adf68f21 421 * __nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
b60503ba
MW		 422 * @nvmeq: The queue to use
423 * @cmd: The command to send
424 *
425 * Safe to use from interrupt context
426 */
e3f879bf
SB		 427static void __nvme_submit_cmd(struct nvme_queue *nvmeq,
428 struct nvme_command *cmd)
b60503ba 429{
a4aea562
MB		 430 u16 tail = nvmeq->sq_tail;
431
8ffaadf7
JD		 432 if (nvmeq->sq_cmds_io)
433 memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd));
434 else
435 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
436
b60503ba
MW		 437 if (++tail == nvmeq->q_depth)
438 tail = 0;
f9f38e33
HK		 439 if (nvme_dbbuf_update_and_check_event(tail, nvmeq->dbbuf_sq_db,
440 nvmeq->dbbuf_sq_ei))
441 writel(tail, nvmeq->q_db);
b60503ba 442 nvmeq->sq_tail = tail;
b60503ba
MW		 443}
444
a7a7cbe3 445static void **nvme_pci_iod_list(struct request *req)
b60503ba 446{
f4800d6d 447 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3 448 return (void **)(iod->sg + blk_rq_nr_phys_segments(req));
b60503ba
MW		 449}
450
955b1b5a
MI		 451static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req)
452{
453 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
20469a37 454 int nseg = blk_rq_nr_phys_segments(req);
955b1b5a
MI		 455 unsigned int avg_seg_size;
456
20469a37
KB		 457 if (nseg == 0)
458 return false;
459
460 avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
955b1b5a
MI		 461
462 if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1))))
463 return false;
464 if (!iod->nvmeq->qid)
465 return false;
466 if (!sgl_threshold || avg_seg_size < sgl_threshold)
467 return false;
468 return true;
469}
470
fc17b653 471static blk_status_t nvme_init_iod(struct request *rq, struct nvme_dev *dev)
ac3dd5bd 472{
f4800d6d 473 struct nvme_iod *iod = blk_mq_rq_to_pdu(rq);
f9d03f96 474 int nseg = blk_rq_nr_phys_segments(rq);
b131c61d 475 unsigned int size = blk_rq_payload_bytes(rq);
ac3dd5bd 476
955b1b5a
MI		 477 iod->use_sgl = nvme_pci_use_sgls(dev, rq);
478
f4800d6d 479 if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) {
a7a7cbe3
CK		 480 size_t alloc_size = nvme_pci_iod_alloc_size(dev, size, nseg,
481 iod->use_sgl);
482
483 iod->sg = kmalloc(alloc_size, GFP_ATOMIC);
f4800d6d 484 if (!iod->sg)
fc17b653 485 return BLK_STS_RESOURCE;
f4800d6d
CH		 486 } else {
487 iod->sg = iod->inline_sg;
ac3dd5bd
JA		 488 }
489
f4800d6d
CH		 490 iod->aborted = 0;
491 iod->npages = -1;
492 iod->nents = 0;
493 iod->length = size;
f80ec966 494
fc17b653 495 return BLK_STS_OK;
ac3dd5bd
JA		 496}
497
f4800d6d 498static void nvme_free_iod(struct nvme_dev *dev, struct request *req)
b60503ba 499{
f4800d6d 500 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3
CK		 501 const int last_prp = dev->ctrl.page_size / sizeof(__le64) - 1;
502 dma_addr_t dma_addr = iod->first_dma, next_dma_addr;
503
eca18b23 504 int i;
eca18b23
MW		 505
506 if (iod->npages == 0)
a7a7cbe3
CK		 507 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0],
508 dma_addr);
509
eca18b23 510 for (i = 0; i < iod->npages; i++) {
a7a7cbe3
CK		 511 void *addr = nvme_pci_iod_list(req)[i];
512
513 if (iod->use_sgl) {
514 struct nvme_sgl_desc *sg_list = addr;
515
516 next_dma_addr =
517 le64_to_cpu((sg_list[SGES_PER_PAGE - 1]).addr);
518 } else {
519 __le64 *prp_list = addr;
520
521 next_dma_addr = le64_to_cpu(prp_list[last_prp]);
522 }
523
524 dma_pool_free(dev->prp_page_pool, addr, dma_addr);
525 dma_addr = next_dma_addr;
eca18b23 526 }
ac3dd5bd 527
f4800d6d
CH		 528 if (iod->sg != iod->inline_sg)
529 kfree(iod->sg);
b4ff9c8d
KB		 530}
531
52b68d7e 532#ifdef CONFIG_BLK_DEV_INTEGRITY
e1e5e564
KB		 533static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
534{
535 if (be32_to_cpu(pi->ref_tag) == v)
536 pi->ref_tag = cpu_to_be32(p);
537}
538
539static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
540{
541 if (be32_to_cpu(pi->ref_tag) == p)
542 pi->ref_tag = cpu_to_be32(v);
543}
544
545/**
546 * nvme_dif_remap - remaps ref tags to bip seed and physical lba
547 *
548 * The virtual start sector is the one that was originally submitted by the
549 * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical
550 * start sector may be different. Remap protection information to match the
551 * physical LBA on writes, and back to the original seed on reads.
552 *
553 * Type 0 and 3 do not have a ref tag, so no remapping required.
554 */
555static void nvme_dif_remap(struct request *req,
556 void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
557{
558 struct nvme_ns *ns = req->rq_disk->private_data;
559 struct bio_integrity_payload *bip;
560 struct t10_pi_tuple *pi;
561 void *p, *pmap;
562 u32 i, nlb, ts, phys, virt;
563
564 if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3)
565 return;
566
567 bip = bio_integrity(req->bio);
568 if (!bip)
569 return;
570
571 pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset;
e1e5e564
KB		 572
573 p = pmap;
574 virt = bip_get_seed(bip);
575 phys = nvme_block_nr(ns, blk_rq_pos(req));
576 nlb = (blk_rq_bytes(req) >> ns->lba_shift);
ac6fc48c 577 ts = ns->disk->queue->integrity.tuple_size;
e1e5e564
KB		 578
579 for (i = 0; i < nlb; i++, virt++, phys++) {
580 pi = (struct t10_pi_tuple *)p;
581 dif_swap(phys, virt, pi);
582 p += ts;
583 }
584 kunmap_atomic(pmap);
585}
52b68d7e
KB		 586#else /* CONFIG_BLK_DEV_INTEGRITY */
587static void nvme_dif_remap(struct request *req,
588 void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
589{
590}
591static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
592{
593}
594static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
595{
596}
52b68d7e
KB		 597#endif
598
d0877473
KB		 599static void nvme_print_sgl(struct scatterlist *sgl, int nents)
600{
601 int i;
602 struct scatterlist *sg;
603
604 for_each_sg(sgl, sg, nents, i) {
605 dma_addr_t phys = sg_phys(sg);
606 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
607 "dma_address:%pad dma_length:%d\n",
608 i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
609 sg_dma_len(sg));
610 }
611}
612
a7a7cbe3
CK		 613static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
614 struct request *req, struct nvme_rw_command *cmnd)
ff22b54f 615{
f4800d6d 616 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
99802a7a 617 struct dma_pool *pool;
b131c61d 618 int length = blk_rq_payload_bytes(req);
eca18b23 619 struct scatterlist *sg = iod->sg;
ff22b54f
MW		 620 int dma_len = sg_dma_len(sg);
621 u64 dma_addr = sg_dma_address(sg);
5fd4ce1b 622 u32 page_size = dev->ctrl.page_size;
f137e0f1 623 int offset = dma_addr & (page_size - 1);
e025344c 624 __le64 *prp_list;
a7a7cbe3 625 void **list = nvme_pci_iod_list(req);
e025344c 626 dma_addr_t prp_dma;
eca18b23 627 int nprps, i;
ff22b54f 628
1d090624 629 length -= (page_size - offset);
5228b328
JS		 630 if (length <= 0) {
631 iod->first_dma = 0;
a7a7cbe3 632 goto done;
5228b328 633 }
ff22b54f 634
1d090624 635 dma_len -= (page_size - offset);
ff22b54f 636 if (dma_len) {
1d090624 637 dma_addr += (page_size - offset);
ff22b54f
MW		 638 } else {
639 sg = sg_next(sg);
640 dma_addr = sg_dma_address(sg);
641 dma_len = sg_dma_len(sg);
642 }
643
1d090624 644 if (length <= page_size) {
edd10d33 645 iod->first_dma = dma_addr;
a7a7cbe3 646 goto done;
e025344c
SMM		 647 }
648
1d090624 649 nprps = DIV_ROUND_UP(length, page_size);
99802a7a
MW		 650 if (nprps <= (256 / 8)) {
651 pool = dev->prp_small_pool;
eca18b23 652 iod->npages = 0;
99802a7a
MW		 653 } else {
654 pool = dev->prp_page_pool;
eca18b23 655 iod->npages = 1;
99802a7a
MW		 656 }
657
69d2b571 658 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
b77954cb 659 if (!prp_list) {
edd10d33 660 iod->first_dma = dma_addr;
eca18b23 661 iod->npages = -1;
86eea289 662 return BLK_STS_RESOURCE;
b77954cb 663 }
eca18b23
MW		 664 list[0] = prp_list;
665 iod->first_dma = prp_dma;
e025344c
SMM		 666 i = 0;
667 for (;;) {
1d090624 668 if (i == page_size >> 3) {
e025344c 669 __le64 *old_prp_list = prp_list;
69d2b571 670 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
eca18b23 671 if (!prp_list)
86eea289 672 return BLK_STS_RESOURCE;
eca18b23 673 list[iod->npages++] = prp_list;
7523d834
MW		 674 prp_list[0] = old_prp_list[i - 1];
675 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
676 i = 1;
e025344c
SMM		 677 }
678 prp_list[i++] = cpu_to_le64(dma_addr);
1d090624
KB		 679 dma_len -= page_size;
680 dma_addr += page_size;
681 length -= page_size;
e025344c
SMM		 682 if (length <= 0)
683 break;
684 if (dma_len > 0)
685 continue;
86eea289
KB		 686 if (unlikely(dma_len < 0))
687 goto bad_sgl;
e025344c
SMM		 688 sg = sg_next(sg);
689 dma_addr = sg_dma_address(sg);
690 dma_len = sg_dma_len(sg);
ff22b54f
MW		 691 }
692
a7a7cbe3
CK		 693done:
694 cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
695 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
696
86eea289
KB		 697 return BLK_STS_OK;
698
699 bad_sgl:
d0877473
KB		 700 WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents),
701 "Invalid SGL for payload:%d nents:%d\n",
702 blk_rq_payload_bytes(req), iod->nents);
86eea289 703 return BLK_STS_IOERR;
ff22b54f
MW		 704}
705
a7a7cbe3
CK		 706static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
707 struct scatterlist *sg)
708{
709 sge->addr = cpu_to_le64(sg_dma_address(sg));
710 sge->length = cpu_to_le32(sg_dma_len(sg));
711 sge->type = NVME_SGL_FMT_DATA_DESC << 4;
712}
713
714static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
715 dma_addr_t dma_addr, int entries)
716{
717 sge->addr = cpu_to_le64(dma_addr);
718 if (entries < SGES_PER_PAGE) {
719 sge->length = cpu_to_le32(entries * sizeof(*sge));
720 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
721 } else {
722 sge->length = cpu_to_le32(PAGE_SIZE);
723 sge->type = NVME_SGL_FMT_SEG_DESC << 4;
724 }
725}
726
727static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
728 struct request *req, struct nvme_rw_command *cmd)
729{
730 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
731 int length = blk_rq_payload_bytes(req);
732 struct dma_pool *pool;
733 struct nvme_sgl_desc *sg_list;
734 struct scatterlist *sg = iod->sg;
735 int entries = iod->nents, i = 0;
736 dma_addr_t sgl_dma;
737
a7a7cbe3
CK		 738 /* setting the transfer type as SGL */
739 cmd->flags = NVME_CMD_SGL_METABUF;
740
741 if (length == sg_dma_len(sg)) {
742 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
743 return BLK_STS_OK;
744 }
745
746 if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
747 pool = dev->prp_small_pool;
748 iod->npages = 0;
749 } else {
750 pool = dev->prp_page_pool;
751 iod->npages = 1;
752 }
753
754 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
755 if (!sg_list) {
756 iod->npages = -1;
757 return BLK_STS_RESOURCE;
758 }
759
760 nvme_pci_iod_list(req)[0] = sg_list;
761 iod->first_dma = sgl_dma;
762
763 nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
764
765 do {
766 if (i == SGES_PER_PAGE) {
767 struct nvme_sgl_desc *old_sg_desc = sg_list;
768 struct nvme_sgl_desc *link = &old_sg_desc[i - 1];
769
770 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
771 if (!sg_list)
772 return BLK_STS_RESOURCE;
773
774 i = 0;
775 nvme_pci_iod_list(req)[iod->npages++] = sg_list;
776 sg_list[i++] = *link;
777 nvme_pci_sgl_set_seg(link, sgl_dma, entries);
778 }
779
780 nvme_pci_sgl_set_data(&sg_list[i++], sg);
781
782 length -= sg_dma_len(sg);
783 sg = sg_next(sg);
784 entries--;
785 } while (length > 0);
786
787 WARN_ON(entries > 0);
788 return BLK_STS_OK;
789}
790
fc17b653 791static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
b131c61d 792 struct nvme_command *cmnd)
d29ec824 793{
f4800d6d 794 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
ba1ca37e
CH		 795 struct request_queue *q = req->q;
796 enum dma_data_direction dma_dir = rq_data_dir(req) ?
797 DMA_TO_DEVICE : DMA_FROM_DEVICE;
fc17b653 798 blk_status_t ret = BLK_STS_IOERR;
d29ec824 799
f9d03f96 800 sg_init_table(iod->sg, blk_rq_nr_phys_segments(req));
ba1ca37e
CH		 801 iod->nents = blk_rq_map_sg(q, req, iod->sg);
802 if (!iod->nents)
803 goto out;
d29ec824 804
fc17b653 805 ret = BLK_STS_RESOURCE;
2b6b535d
MFO		 806 if (!dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, dma_dir,
807 DMA_ATTR_NO_WARN))
ba1ca37e 808 goto out;
d29ec824 809
955b1b5a 810 if (iod->use_sgl)
a7a7cbe3
CK		 811 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw);
812 else
813 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
814
86eea289 815 if (ret != BLK_STS_OK)
ba1ca37e 816 goto out_unmap;
0e5e4f0e 817
fc17b653 818 ret = BLK_STS_IOERR;
ba1ca37e
CH		 819 if (blk_integrity_rq(req)) {
820 if (blk_rq_count_integrity_sg(q, req->bio) != 1)
821 goto out_unmap;
0e5e4f0e 822
bf684057
CH		 823 sg_init_table(&iod->meta_sg, 1);
824 if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1)
ba1ca37e 825 goto out_unmap;
0e5e4f0e 826
b5d8af5b 827 if (req_op(req) == REQ_OP_WRITE)
ba1ca37e 828 nvme_dif_remap(req, nvme_dif_prep);
0e5e4f0e 829
bf684057 830 if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir))
ba1ca37e 831 goto out_unmap;
d29ec824 832 }
00df5cb4 833
ba1ca37e 834 if (blk_integrity_rq(req))
bf684057 835 cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg));
fc17b653 836 return BLK_STS_OK;
00df5cb4 837
ba1ca37e
CH		 838out_unmap:
839 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
840out:
841 return ret;
00df5cb4
MW		 842}
843
f4800d6d 844static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
b60503ba 845{
f4800d6d 846 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
d4f6c3ab
CH		 847 enum dma_data_direction dma_dir = rq_data_dir(req) ?
848 DMA_TO_DEVICE : DMA_FROM_DEVICE;
849
850 if (iod->nents) {
851 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
852 if (blk_integrity_rq(req)) {
b5d8af5b 853 if (req_op(req) == REQ_OP_READ)
d4f6c3ab 854 nvme_dif_remap(req, nvme_dif_complete);
bf684057 855 dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir);
e1e5e564 856 }
e19b127f 857 }
e1e5e564 858
f9d03f96 859 nvme_cleanup_cmd(req);
f4800d6d 860 nvme_free_iod(dev, req);
d4f6c3ab 861}
b60503ba 862
d29ec824
CH		 863/*
864 * NOTE: ns is NULL when called on the admin queue.
865 */
fc17b653 866static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
a4aea562 867 const struct blk_mq_queue_data *bd)
edd10d33 868{
a4aea562
MB		 869 struct nvme_ns *ns = hctx->queue->queuedata;
870 struct nvme_queue *nvmeq = hctx->driver_data;
d29ec824 871 struct nvme_dev *dev = nvmeq->dev;
a4aea562 872 struct request *req = bd->rq;
ba1ca37e 873 struct nvme_command cmnd;
ebe6d874 874 blk_status_t ret;
e1e5e564 875
f9d03f96 876 ret = nvme_setup_cmd(ns, req, &cmnd);
fc17b653 877 if (ret)
f4800d6d 878 return ret;
a4aea562 879
b131c61d 880 ret = nvme_init_iod(req, dev);
fc17b653 881 if (ret)
f9d03f96 882 goto out_free_cmd;
a4aea562 883
fc17b653 884 if (blk_rq_nr_phys_segments(req)) {
b131c61d 885 ret = nvme_map_data(dev, req, &cmnd);
fc17b653
CH		 886 if (ret)
887 goto out_cleanup_iod;
888 }
a4aea562 889
aae239e1 890 blk_mq_start_request(req);
a4aea562 891
ba1ca37e 892 spin_lock_irq(&nvmeq->q_lock);
ae1fba20 893 if (unlikely(nvmeq->cq_vector < 0)) {
fc17b653 894 ret = BLK_STS_IOERR;
ae1fba20 895 spin_unlock_irq(&nvmeq->q_lock);
f9d03f96 896 goto out_cleanup_iod;
ae1fba20 897 }
ba1ca37e 898 __nvme_submit_cmd(nvmeq, &cmnd);
a4aea562
MB		 899 nvme_process_cq(nvmeq);
900 spin_unlock_irq(&nvmeq->q_lock);
fc17b653 901 return BLK_STS_OK;
f9d03f96 902out_cleanup_iod:
f4800d6d 903 nvme_free_iod(dev, req);
f9d03f96
CH		 904out_free_cmd:
905 nvme_cleanup_cmd(req);
ba1ca37e 906 return ret;
b60503ba 907}
e1e5e564 908
77f02a7a 909static void nvme_pci_complete_rq(struct request *req)
eee417b0 910{
f4800d6d 911 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a4aea562 912
77f02a7a
CH		 913 nvme_unmap_data(iod->nvmeq->dev, req);
914 nvme_complete_rq(req);
b60503ba
MW		 915}
916
d783e0bd
MR		 917/* We read the CQE phase first to check if the rest of the entry is valid */
918static inline bool nvme_cqe_valid(struct nvme_queue *nvmeq, u16 head,
919 u16 phase)
920{
921 return (le16_to_cpu(nvmeq->cqes[head].status) & 1) == phase;
922}
923
eb281c82 924static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
b60503ba 925{
eb281c82 926 u16 head = nvmeq->cq_head;
adf68f21 927
eb281c82
SG		 928 if (likely(nvmeq->cq_vector >= 0)) {
929 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
930 nvmeq->dbbuf_cq_ei))
931 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
932 }
933}
aae239e1 934
83a12fb7
SG		 935static inline void nvme_handle_cqe(struct nvme_queue *nvmeq,
936 struct nvme_completion *cqe)
937{
938 struct request *req;
adf68f21 939
83a12fb7
SG		 940 if (unlikely(cqe->command_id >= nvmeq->q_depth)) {
941 dev_warn(nvmeq->dev->ctrl.device,
942 "invalid id %d completed on queue %d\n",
943 cqe->command_id, le16_to_cpu(cqe->sq_id));
944 return;
b60503ba
MW		 945 }
946
83a12fb7
SG		 947 /*
948 * AEN requests are special as they don't time out and can
949 * survive any kind of queue freeze and often don't respond to
950 * aborts. We don't even bother to allocate a struct request
951 * for them but rather special case them here.
952 */
953 if (unlikely(nvmeq->qid == 0 &&
38dabe21 954 cqe->command_id >= NVME_AQ_BLK_MQ_DEPTH)) {
83a12fb7
SG		 955 nvme_complete_async_event(&nvmeq->dev->ctrl,
956 cqe->status, &cqe->result);
a0fa9647 957 return;
83a12fb7 958 }
b60503ba 959
e9d8a0fd 960 nvmeq->cqe_seen = 1;
83a12fb7
SG		 961 req = blk_mq_tag_to_rq(*nvmeq->tags, cqe->command_id);
962 nvme_end_request(req, cqe->status, cqe->result);
963}
b60503ba 964
920d13a8
SG		 965static inline bool nvme_read_cqe(struct nvme_queue *nvmeq,
966 struct nvme_completion *cqe)
b60503ba 967{
920d13a8
SG		 968 if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase)) {
969 *cqe = nvmeq->cqes[nvmeq->cq_head];
adf68f21 970
920d13a8
SG		 971 if (++nvmeq->cq_head == nvmeq->q_depth) {
972 nvmeq->cq_head = 0;
973 nvmeq->cq_phase = !nvmeq->cq_phase;
b60503ba 974 }
920d13a8 975 return true;
b60503ba 976 }
920d13a8 977 return false;
a0fa9647
JA		 978}
979
980static void nvme_process_cq(struct nvme_queue *nvmeq)
981{
920d13a8
SG		 982 struct nvme_completion cqe;
983 int consumed = 0;
b60503ba 984
920d13a8
SG		 985 while (nvme_read_cqe(nvmeq, &cqe)) {
986 nvme_handle_cqe(nvmeq, &cqe);
987 consumed++;
920d13a8 988 }
eb281c82 989
e9d8a0fd 990 if (consumed)
920d13a8 991 nvme_ring_cq_doorbell(nvmeq);
b60503ba
MW		 992}
993
994static irqreturn_t nvme_irq(int irq, void *data)
58ffacb5
MW		 995{
996 irqreturn_t result;
997 struct nvme_queue *nvmeq = data;
998 spin_lock(&nvmeq->q_lock);
e9539f47
MW		 999 nvme_process_cq(nvmeq);
1000 result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE;
1001 nvmeq->cqe_seen = 0;
58ffacb5
MW		 1002 spin_unlock(&nvmeq->q_lock);
1003 return result;
1004}
1005
1006static irqreturn_t nvme_irq_check(int irq, void *data)
1007{
1008 struct nvme_queue *nvmeq = data;
d783e0bd
MR		 1009 if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase))
1010 return IRQ_WAKE_THREAD;
1011 return IRQ_NONE;
58ffacb5
MW		 1012}
1013
7776db1c 1014static int __nvme_poll(struct nvme_queue *nvmeq, unsigned int tag)
a0fa9647 1015{
442e19b7
SG		 1016 struct nvme_completion cqe;
1017 int found = 0, consumed = 0;
a0fa9647 1018
442e19b7
SG		 1019 if (!nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase))
1020 return 0;
a0fa9647 1021
442e19b7
SG		 1022 spin_lock_irq(&nvmeq->q_lock);
1023 while (nvme_read_cqe(nvmeq, &cqe)) {
1024 nvme_handle_cqe(nvmeq, &cqe);
1025 consumed++;
1026
1027 if (tag == cqe.command_id) {
1028 found = 1;
1029 break;
1030 }
1031 }
1032
1033 if (consumed)
1034 nvme_ring_cq_doorbell(nvmeq);
1035 spin_unlock_irq(&nvmeq->q_lock);
1036
1037 return found;
a0fa9647
JA		 1038}
1039
7776db1c
KB		 1040static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag)
1041{
1042 struct nvme_queue *nvmeq = hctx->driver_data;
1043
1044 return __nvme_poll(nvmeq, tag);
1045}
1046
ad22c355 1047static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
b60503ba 1048{
f866fc42 1049 struct nvme_dev *dev = to_nvme_dev(ctrl);
9396dec9 1050 struct nvme_queue *nvmeq = dev->queues[0];
a4aea562 1051 struct nvme_command c;
b60503ba 1052
a4aea562
MB		 1053 memset(&c, 0, sizeof(c));
1054 c.common.opcode = nvme_admin_async_event;
ad22c355 1055 c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
3c0cf138 1056
9396dec9 1057 spin_lock_irq(&nvmeq->q_lock);
f866fc42 1058 __nvme_submit_cmd(nvmeq, &c);
9396dec9 1059 spin_unlock_irq(&nvmeq->q_lock);
f705f837
CH		 1060}
1061
b60503ba 1062static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
f705f837 1063{
b60503ba
MW		 1064 struct nvme_command c;
1065
1066 memset(&c, 0, sizeof(c));
1067 c.delete_queue.opcode = opcode;
1068 c.delete_queue.qid = cpu_to_le16(id);
1069
1c63dc66 1070 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1071}
1072
b60503ba
MW		 1073static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
1074 struct nvme_queue *nvmeq)
1075{
b60503ba
MW		 1076 struct nvme_command c;
1077 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
1078
d29ec824 1079 /*
16772ae6 1080 * Note: we (ab)use the fact that the prp fields survive if no data
d29ec824
CH		 1081 * is attached to the request.
1082 */
b60503ba
MW		 1083 memset(&c, 0, sizeof(c));
1084 c.create_cq.opcode = nvme_admin_create_cq;
1085 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1086 c.create_cq.cqid = cpu_to_le16(qid);
1087 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1088 c.create_cq.cq_flags = cpu_to_le16(flags);
1089 c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
1090
1c63dc66 1091 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1092}
1093
1094static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1095 struct nvme_queue *nvmeq)
1096{
b60503ba 1097 struct nvme_command c;
81c1cd98 1098 int flags = NVME_QUEUE_PHYS_CONTIG;
b60503ba 1099
d29ec824 1100 /*
16772ae6 1101 * Note: we (ab)use the fact that the prp fields survive if no data
d29ec824
CH		 1102 * is attached to the request.
1103 */
b60503ba
MW		 1104 memset(&c, 0, sizeof(c));
1105 c.create_sq.opcode = nvme_admin_create_sq;
1106 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1107 c.create_sq.sqid = cpu_to_le16(qid);
1108 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1109 c.create_sq.sq_flags = cpu_to_le16(flags);
1110 c.create_sq.cqid = cpu_to_le16(qid);
1111
1c63dc66 1112 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1113}
1114
1115static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1116{
1117 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1118}
1119
1120static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1121{
1122 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1123}
1124
2a842aca 1125static void abort_endio(struct request *req, blk_status_t error)
bc5fc7e4 1126{
f4800d6d
CH		 1127 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1128 struct nvme_queue *nvmeq = iod->nvmeq;
e44ac588 1129
27fa9bc5
CH		 1130 dev_warn(nvmeq->dev->ctrl.device,
1131 "Abort status: 0x%x", nvme_req(req)->status);
e7a2a87d 1132 atomic_inc(&nvmeq->dev->ctrl.abort_limit);
e7a2a87d 1133 blk_mq_free_request(req);
bc5fc7e4
MW		 1134}
1135
b2a0eb1a
KB		 1136static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1137{
1138
1139 /* If true, indicates loss of adapter communication, possibly by a
1140 * NVMe Subsystem reset.
1141 */
1142 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1143
1144 /* If there is a reset ongoing, we shouldn't reset again. */
1145 if (dev->ctrl.state == NVME_CTRL_RESETTING)
1146 return false;
1147
1148 /* We shouldn't reset unless the controller is on fatal error state
1149 * _or_ if we lost the communication with it.
1150 */
1151 if (!(csts & NVME_CSTS_CFS) && !nssro)
1152 return false;
1153
1154 /* If PCI error recovery process is happening, we cannot reset or
1155 * the recovery mechanism will surely fail.
1156 */
1157 if (pci_channel_offline(to_pci_dev(dev->dev)))
1158 return false;
1159
1160 return true;
1161}
1162
1163static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1164{
1165 /* Read a config register to help see what died. */
1166 u16 pci_status;
1167 int result;
1168
1169 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1170 &pci_status);
1171 if (result == PCIBIOS_SUCCESSFUL)
1172 dev_warn(dev->ctrl.device,
1173 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1174 csts, pci_status);
1175 else
1176 dev_warn(dev->ctrl.device,
1177 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1178 csts, result);
1179}
1180
31c7c7d2 1181static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
c30341dc 1182{
f4800d6d
CH		 1183 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1184 struct nvme_queue *nvmeq = iod->nvmeq;
c30341dc 1185 struct nvme_dev *dev = nvmeq->dev;
a4aea562 1186 struct request *abort_req;
a4aea562 1187 struct nvme_command cmd;
b2a0eb1a
KB		 1188 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1189
1190 /*
1191 * Reset immediately if the controller is failed
1192 */
1193 if (nvme_should_reset(dev, csts)) {
1194 nvme_warn_reset(dev, csts);
1195 nvme_dev_disable(dev, false);
d86c4d8e 1196 nvme_reset_ctrl(&dev->ctrl);
b2a0eb1a
KB		 1197 return BLK_EH_HANDLED;
1198 }
c30341dc 1199
7776db1c
KB		 1200 /*
1201 * Did we miss an interrupt?
1202 */
1203 if (__nvme_poll(nvmeq, req->tag)) {
1204 dev_warn(dev->ctrl.device,
1205 "I/O %d QID %d timeout, completion polled\n",
1206 req->tag, nvmeq->qid);
1207 return BLK_EH_HANDLED;
1208 }
1209
31c7c7d2 1210 /*
fd634f41
CH		 1211 * Shutdown immediately if controller times out while starting. The
1212 * reset work will see the pci device disabled when it gets the forced
1213 * cancellation error. All outstanding requests are completed on
1214 * shutdown, so we return BLK_EH_HANDLED.
1215 */
bb8d261e 1216 if (dev->ctrl.state == NVME_CTRL_RESETTING) {
1b3c47c1 1217 dev_warn(dev->ctrl.device,
fd634f41
CH		 1218 "I/O %d QID %d timeout, disable controller\n",
1219 req->tag, nvmeq->qid);
a5cdb68c 1220 nvme_dev_disable(dev, false);
27fa9bc5 1221 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
fd634f41 1222 return BLK_EH_HANDLED;
c30341dc
KB		 1223 }
1224
fd634f41
CH		 1225 /*
1226 * Shutdown the controller immediately and schedule a reset if the
1227 * command was already aborted once before and still hasn't been
1228 * returned to the driver, or if this is the admin queue.
31c7c7d2 1229 */
f4800d6d 1230 if (!nvmeq->qid || iod->aborted) {
1b3c47c1 1231 dev_warn(dev->ctrl.device,
e1569a16
KB		 1232 "I/O %d QID %d timeout, reset controller\n",
1233 req->tag, nvmeq->qid);
a5cdb68c 1234 nvme_dev_disable(dev, false);
d86c4d8e 1235 nvme_reset_ctrl(&dev->ctrl);
c30341dc 1236
e1569a16
KB		 1237 /*
1238 * Mark the request as handled, since the inline shutdown
1239 * forces all outstanding requests to complete.
1240 */
27fa9bc5 1241 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
e1569a16 1242 return BLK_EH_HANDLED;
c30341dc 1243 }
c30341dc 1244
e7a2a87d 1245 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
6bf25d16 1246 atomic_inc(&dev->ctrl.abort_limit);
31c7c7d2 1247 return BLK_EH_RESET_TIMER;
6bf25d16 1248 }
7bf7d778 1249 iod->aborted = 1;
a4aea562 1250
c30341dc
KB		 1251 memset(&cmd, 0, sizeof(cmd));
1252 cmd.abort.opcode = nvme_admin_abort_cmd;
a4aea562 1253 cmd.abort.cid = req->tag;
c30341dc 1254 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
c30341dc 1255
1b3c47c1
SG		 1256 dev_warn(nvmeq->dev->ctrl.device,
1257 "I/O %d QID %d timeout, aborting\n",
1258 req->tag, nvmeq->qid);
e7a2a87d
CH		 1259
1260 abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
eb71f435 1261 BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
e7a2a87d
CH		 1262 if (IS_ERR(abort_req)) {
1263 atomic_inc(&dev->ctrl.abort_limit);
1264 return BLK_EH_RESET_TIMER;
1265 }
1266
1267 abort_req->timeout = ADMIN_TIMEOUT;
1268 abort_req->end_io_data = NULL;
1269 blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio);
c30341dc 1270
31c7c7d2
CH		 1271 /*
1272 * The aborted req will be completed on receiving the abort req.
1273 * We enable the timer again. If hit twice, it'll cause a device reset,
1274 * as the device then is in a faulty state.
1275 */
1276 return BLK_EH_RESET_TIMER;
c30341dc
KB		 1277}
1278
a4aea562
MB		 1279static void nvme_free_queue(struct nvme_queue *nvmeq)
1280{
9e866774
MW		 1281 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1282 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
8ffaadf7
JD		 1283 if (nvmeq->sq_cmds)
1284 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
9e866774
MW		 1285 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1286 kfree(nvmeq);
1287}
1288
a1a5ef99 1289static void nvme_free_queues(struct nvme_dev *dev, int lowest)
22404274
KB		 1290{
1291 int i;
1292
d858e5f0 1293 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
a4aea562 1294 struct nvme_queue *nvmeq = dev->queues[i];
d858e5f0 1295 dev->ctrl.queue_count--;
a4aea562 1296 dev->queues[i] = NULL;
f435c282 1297 nvme_free_queue(nvmeq);
121c7ad4 1298 }
22404274
KB		 1299}
1300
4d115420
KB		 1301/**
1302 * nvme_suspend_queue - put queue into suspended state
1303 * @nvmeq - queue to suspend
4d115420
KB		 1304 */
1305static int nvme_suspend_queue(struct nvme_queue *nvmeq)
b60503ba 1306{
2b25d981 1307 int vector;
b60503ba 1308
a09115b2 1309 spin_lock_irq(&nvmeq->q_lock);
2b25d981
KB		 1310 if (nvmeq->cq_vector == -1) {
1311 spin_unlock_irq(&nvmeq->q_lock);
1312 return 1;
1313 }
0ff199cb 1314 vector = nvmeq->cq_vector;
42f61420 1315 nvmeq->dev->online_queues--;
2b25d981 1316 nvmeq->cq_vector = -1;
a09115b2
MW		 1317 spin_unlock_irq(&nvmeq->q_lock);
1318
1c63dc66 1319 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
c81545f9 1320 blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q);
6df3dbc8 1321
0ff199cb 1322 pci_free_irq(to_pci_dev(nvmeq->dev->dev), vector, nvmeq);
b60503ba 1323
4d115420
KB		 1324 return 0;
1325}
b60503ba 1326
a5cdb68c 1327static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
4d115420 1328{
a5cdb68c 1329 struct nvme_queue *nvmeq = dev->queues[0];
4d115420
KB		 1330
1331 if (!nvmeq)
1332 return;
1333 if (nvme_suspend_queue(nvmeq))
1334 return;
1335
a5cdb68c
KB		 1336 if (shutdown)
1337 nvme_shutdown_ctrl(&dev->ctrl);
1338 else
20d0dfe6 1339 nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap);
07836e65
KB		 1340
1341 spin_lock_irq(&nvmeq->q_lock);
1342 nvme_process_cq(nvmeq);
1343 spin_unlock_irq(&nvmeq->q_lock);
b60503ba
MW		 1344}
1345
8ffaadf7
JD		 1346static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1347 int entry_size)
1348{
1349 int q_depth = dev->q_depth;
5fd4ce1b
CH		 1350 unsigned q_size_aligned = roundup(q_depth * entry_size,
1351 dev->ctrl.page_size);
8ffaadf7
JD		 1352
1353 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
c45f5c99 1354 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
5fd4ce1b 1355 mem_per_q = round_down(mem_per_q, dev->ctrl.page_size);
c45f5c99 1356 q_depth = div_u64(mem_per_q, entry_size);
8ffaadf7
JD		 1357
1358 /*
1359 * Ensure the reduced q_depth is above some threshold where it
1360 * would be better to map queues in system memory with the
1361 * original depth
1362 */
1363 if (q_depth < 64)
1364 return -ENOMEM;
1365 }
1366
1367 return q_depth;
1368}
1369
1370static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1371 int qid, int depth)
1372{
1373 if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz)) {
5fd4ce1b
CH		 1374 unsigned offset = (qid - 1) * roundup(SQ_SIZE(depth),
1375 dev->ctrl.page_size);
8969f1f8 1376 nvmeq->sq_dma_addr = dev->cmb_bus_addr + offset;
8ffaadf7
JD		 1377 nvmeq->sq_cmds_io = dev->cmb + offset;
1378 } else {
1379 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
1380 &nvmeq->sq_dma_addr, GFP_KERNEL);
1381 if (!nvmeq->sq_cmds)
1382 return -ENOMEM;
1383 }
1384
1385 return 0;
1386}
1387
b60503ba 1388static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
d3af3ecd 1389 int depth, int node)
b60503ba 1390{
d3af3ecd
SL		 1391 struct nvme_queue *nvmeq = kzalloc_node(sizeof(*nvmeq), GFP_KERNEL,
1392 node);
b60503ba
MW		 1393 if (!nvmeq)
1394 return NULL;
1395
e75ec752 1396 nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth),
4d51abf9 1397 &nvmeq->cq_dma_addr, GFP_KERNEL);
b60503ba
MW		 1398 if (!nvmeq->cqes)
1399 goto free_nvmeq;
b60503ba 1400
8ffaadf7 1401 if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth))
b60503ba
MW		 1402 goto free_cqdma;
1403
e75ec752 1404 nvmeq->q_dmadev = dev->dev;
091b6092 1405 nvmeq->dev = dev;
b60503ba
MW		 1406 spin_lock_init(&nvmeq->q_lock);
1407 nvmeq->cq_head = 0;
82123460 1408 nvmeq->cq_phase = 1;
b80d5ccc 1409 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
b60503ba 1410 nvmeq->q_depth = depth;
c30341dc 1411 nvmeq->qid = qid;
758dd7fd 1412 nvmeq->cq_vector = -1;
a4aea562 1413 dev->queues[qid] = nvmeq;
d858e5f0 1414 dev->ctrl.queue_count++;
36a7e993 1415
b60503ba
MW		 1416 return nvmeq;
1417
1418 free_cqdma:
e75ec752 1419 dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes,
b60503ba
MW		 1420 nvmeq->cq_dma_addr);
1421 free_nvmeq:
1422 kfree(nvmeq);
1423 return NULL;
1424}
1425
dca51e78 1426static int queue_request_irq(struct nvme_queue *nvmeq)
3001082c 1427{
0ff199cb
CH		 1428 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1429 int nr = nvmeq->dev->ctrl.instance;
1430
1431 if (use_threaded_interrupts) {
1432 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1433 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1434 } else {
1435 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1436 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1437 }
3001082c
MW		 1438}
1439
22404274 1440static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
b60503ba 1441{
22404274 1442 struct nvme_dev *dev = nvmeq->dev;
b60503ba 1443
7be50e93 1444 spin_lock_irq(&nvmeq->q_lock);
22404274
KB		 1445 nvmeq->sq_tail = 0;
1446 nvmeq->cq_head = 0;
1447 nvmeq->cq_phase = 1;
b80d5ccc 1448 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
22404274 1449 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
f9f38e33 1450 nvme_dbbuf_init(dev, nvmeq, qid);
42f61420 1451 dev->online_queues++;
7be50e93 1452 spin_unlock_irq(&nvmeq->q_lock);
22404274
KB		 1453}
1454
1455static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1456{
1457 struct nvme_dev *dev = nvmeq->dev;
1458 int result;
3f85d50b 1459
2b25d981 1460 nvmeq->cq_vector = qid - 1;
b60503ba
MW		 1461 result = adapter_alloc_cq(dev, qid, nvmeq);
1462 if (result < 0)
22404274 1463 return result;
b60503ba
MW		 1464
1465 result = adapter_alloc_sq(dev, qid, nvmeq);
1466 if (result < 0)
1467 goto release_cq;
1468
161b8be2 1469 nvme_init_queue(nvmeq, qid);
dca51e78 1470 result = queue_request_irq(nvmeq);
b60503ba
MW		 1471 if (result < 0)
1472 goto release_sq;
1473
22404274 1474 return result;
b60503ba
MW		 1475
1476 release_sq:
1477 adapter_delete_sq(dev, qid);
1478 release_cq:
1479 adapter_delete_cq(dev, qid);
22404274 1480 return result;
b60503ba
MW		 1481}
1482
f363b089 1483static const struct blk_mq_ops nvme_mq_admin_ops = {
d29ec824 1484 .queue_rq = nvme_queue_rq,
77f02a7a 1485 .complete = nvme_pci_complete_rq,
a4aea562 1486 .init_hctx = nvme_admin_init_hctx,
4af0e21c 1487 .exit_hctx = nvme_admin_exit_hctx,
0350815a 1488 .init_request = nvme_init_request,
a4aea562
MB		 1489 .timeout = nvme_timeout,
1490};
1491
f363b089 1492static const struct blk_mq_ops nvme_mq_ops = {
a4aea562 1493 .queue_rq = nvme_queue_rq,
77f02a7a 1494 .complete = nvme_pci_complete_rq,
a4aea562
MB		 1495 .init_hctx = nvme_init_hctx,
1496 .init_request = nvme_init_request,
dca51e78 1497 .map_queues = nvme_pci_map_queues,
a4aea562 1498 .timeout = nvme_timeout,
a0fa9647 1499 .poll = nvme_poll,
a4aea562
MB		 1500};
1501
ea191d2f
KB		 1502static void nvme_dev_remove_admin(struct nvme_dev *dev)
1503{
1c63dc66 1504 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
69d9a99c
KB		 1505 /*
1506 * If the controller was reset during removal, it's possible
1507 * user requests may be waiting on a stopped queue. Start the
1508 * queue to flush these to completion.
1509 */
c81545f9 1510 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1c63dc66 1511 blk_cleanup_queue(dev->ctrl.admin_q);
ea191d2f
KB		 1512 blk_mq_free_tag_set(&dev->admin_tagset);
1513 }
1514}
1515
a4aea562
MB		 1516static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1517{
1c63dc66 1518 if (!dev->ctrl.admin_q) {
a4aea562
MB		 1519 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1520 dev->admin_tagset.nr_hw_queues = 1;
e3e9d50c 1521
38dabe21 1522 dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH;
a4aea562 1523 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
e75ec752 1524 dev->admin_tagset.numa_node = dev_to_node(dev->dev);
a7a7cbe3 1525 dev->admin_tagset.cmd_size = nvme_pci_cmd_size(dev, false);
d3484991 1526 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED;
a4aea562
MB		 1527 dev->admin_tagset.driver_data = dev;
1528
1529 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1530 return -ENOMEM;
34b6c231 1531 dev->ctrl.admin_tagset = &dev->admin_tagset;
a4aea562 1532
1c63dc66
CH		 1533 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1534 if (IS_ERR(dev->ctrl.admin_q)) {
a4aea562
MB		 1535 blk_mq_free_tag_set(&dev->admin_tagset);
1536 return -ENOMEM;
1537 }
1c63dc66 1538 if (!blk_get_queue(dev->ctrl.admin_q)) {
ea191d2f 1539 nvme_dev_remove_admin(dev);
1c63dc66 1540 dev->ctrl.admin_q = NULL;
ea191d2f
KB		 1541 return -ENODEV;
1542 }
0fb59cbc 1543 } else
c81545f9 1544 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
a4aea562
MB		 1545
1546 return 0;
1547}
1548
97f6ef64
XY		 1549static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1550{
1551 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1552}
1553
1554static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1555{
1556 struct pci_dev *pdev = to_pci_dev(dev->dev);
1557
1558 if (size <= dev->bar_mapped_size)
1559 return 0;
1560 if (size > pci_resource_len(pdev, 0))
1561 return -ENOMEM;
1562 if (dev->bar)
1563 iounmap(dev->bar);
1564 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1565 if (!dev->bar) {
1566 dev->bar_mapped_size = 0;
1567 return -ENOMEM;
1568 }
1569 dev->bar_mapped_size = size;
1570 dev->dbs = dev->bar + NVME_REG_DBS;
1571
1572 return 0;
1573}
1574
01ad0990 1575static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
b60503ba 1576{
ba47e386 1577 int result;
b60503ba
MW		 1578 u32 aqa;
1579 struct nvme_queue *nvmeq;
1580
97f6ef64
XY		 1581 result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1582 if (result < 0)
1583 return result;
1584
8ef2074d 1585 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
20d0dfe6 1586 NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
dfbac8c7 1587
7a67cbea
CH		 1588 if (dev->subsystem &&
1589 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1590 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
dfbac8c7 1591
20d0dfe6 1592 result = nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap);
ba47e386
MW		 1593 if (result < 0)
1594 return result;
b60503ba 1595
a4aea562 1596 nvmeq = dev->queues[0];
cd638946 1597 if (!nvmeq) {
d3af3ecd
SL		 1598 nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH,
1599 dev_to_node(dev->dev));
cd638946
KB		 1600 if (!nvmeq)
1601 return -ENOMEM;
cd638946 1602 }
b60503ba
MW		 1603
1604 aqa = nvmeq->q_depth - 1;
1605 aqa |= aqa << 16;
1606
7a67cbea
CH		 1607 writel(aqa, dev->bar + NVME_REG_AQA);
1608 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1609 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
b60503ba 1610
20d0dfe6 1611 result = nvme_enable_ctrl(&dev->ctrl, dev->ctrl.cap);
025c557a 1612 if (result)
d4875622 1613 return result;
a4aea562 1614
2b25d981 1615 nvmeq->cq_vector = 0;
161b8be2 1616 nvme_init_queue(nvmeq, 0);
dca51e78 1617 result = queue_request_irq(nvmeq);
758dd7fd
JD		 1618 if (result) {
1619 nvmeq->cq_vector = -1;
d4875622 1620 return result;
758dd7fd 1621 }
025c557a 1622
b60503ba
MW		 1623 return result;
1624}
1625
749941f2 1626static int nvme_create_io_queues(struct nvme_dev *dev)
42f61420 1627{
949928c1 1628 unsigned i, max;
749941f2 1629 int ret = 0;
42f61420 1630
d858e5f0 1631 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
d3af3ecd
SL		 1632 /* vector == qid - 1, match nvme_create_queue */
1633 if (!nvme_alloc_queue(dev, i, dev->q_depth,
1634 pci_irq_get_node(to_pci_dev(dev->dev), i - 1))) {
749941f2 1635 ret = -ENOMEM;
42f61420 1636 break;
749941f2
CH		 1637 }
1638 }
42f61420 1639
d858e5f0 1640 max = min(dev->max_qid, dev->ctrl.queue_count - 1);
949928c1 1641 for (i = dev->online_queues; i <= max; i++) {
749941f2 1642 ret = nvme_create_queue(dev->queues[i], i);
d4875622 1643 if (ret)
42f61420 1644 break;
27e8166c 1645 }
749941f2
CH		 1646
1647 /*
1648 * Ignore failing Create SQ/CQ commands, we can continue with less
1649 * than the desired aount of queues, and even a controller without
1650 * I/O queues an still be used to issue admin commands. This might
1651 * be useful to upgrade a buggy firmware for example.
1652 */
1653 return ret >= 0 ? 0 : ret;
b60503ba
MW		 1654}
1655
202021c1
SB		 1656static ssize_t nvme_cmb_show(struct device *dev,
1657 struct device_attribute *attr,
1658 char *buf)
1659{
1660 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
1661
c965809c 1662 return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n",
202021c1
SB		 1663 ndev->cmbloc, ndev->cmbsz);
1664}
1665static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL);
1666
8ffaadf7
JD		 1667static void __iomem *nvme_map_cmb(struct nvme_dev *dev)
1668{
1669 u64 szu, size, offset;
8ffaadf7
JD		 1670 resource_size_t bar_size;
1671 struct pci_dev *pdev = to_pci_dev(dev->dev);
1672 void __iomem *cmb;
8969f1f8 1673 int bar;
8ffaadf7 1674
7a67cbea 1675 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
8ffaadf7
JD		 1676 if (!(NVME_CMB_SZ(dev->cmbsz)))
1677 return NULL;
202021c1 1678 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
8ffaadf7 1679
202021c1
SB		 1680 if (!use_cmb_sqes)
1681 return NULL;
8ffaadf7
JD		 1682
1683 szu = (u64)1 << (12 + 4 * NVME_CMB_SZU(dev->cmbsz));
1684 size = szu * NVME_CMB_SZ(dev->cmbsz);
202021c1 1685 offset = szu * NVME_CMB_OFST(dev->cmbloc);
8969f1f8
CH		 1686 bar = NVME_CMB_BIR(dev->cmbloc);
1687 bar_size = pci_resource_len(pdev, bar);
8ffaadf7
JD		 1688
1689 if (offset > bar_size)
1690 return NULL;
1691
1692 /*
1693 * Controllers may support a CMB size larger than their BAR,
1694 * for example, due to being behind a bridge. Reduce the CMB to
1695 * the reported size of the BAR
1696 */
1697 if (size > bar_size - offset)
1698 size = bar_size - offset;
1699
8969f1f8 1700 cmb = ioremap_wc(pci_resource_start(pdev, bar) + offset, size);
8ffaadf7
JD		 1701 if (!cmb)
1702 return NULL;
1703
8969f1f8 1704 dev->cmb_bus_addr = pci_bus_address(pdev, bar) + offset;
8ffaadf7
JD		 1705 dev->cmb_size = size;
1706 return cmb;
1707}
1708
1709static inline void nvme_release_cmb(struct nvme_dev *dev)
1710{
1711 if (dev->cmb) {
1712 iounmap(dev->cmb);
1713 dev->cmb = NULL;
1c78f773
MG		 1714 sysfs_remove_file_from_group(&dev->ctrl.device->kobj,
1715 &dev_attr_cmb.attr, NULL);
1716 dev->cmbsz = 0;
8ffaadf7
JD		 1717 }
1718}
1719
87ad72a5
CH		 1720static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1721{
4033f35d 1722 u64 dma_addr = dev->host_mem_descs_dma;
87ad72a5 1723 struct nvme_command c;
87ad72a5
CH		 1724 int ret;
1725
87ad72a5
CH		 1726 memset(&c, 0, sizeof(c));
1727 c.features.opcode = nvme_admin_set_features;
1728 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1729 c.features.dword11 = cpu_to_le32(bits);
1730 c.features.dword12 = cpu_to_le32(dev->host_mem_size >>
1731 ilog2(dev->ctrl.page_size));
1732 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr));
1733 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr));
1734 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs);
1735
1736 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1737 if (ret) {
1738 dev_warn(dev->ctrl.device,
1739 "failed to set host mem (err %d, flags %#x).\n",
1740 ret, bits);
1741 }
87ad72a5
CH		 1742 return ret;
1743}
1744
1745static void nvme_free_host_mem(struct nvme_dev *dev)
1746{
1747 int i;
1748
1749 for (i = 0; i < dev->nr_host_mem_descs; i++) {
1750 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
1751 size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size;
1752
1753 dma_free_coherent(dev->dev, size, dev->host_mem_desc_bufs[i],
1754 le64_to_cpu(desc->addr));
1755 }
1756
1757 kfree(dev->host_mem_desc_bufs);
1758 dev->host_mem_desc_bufs = NULL;
4033f35d
CH		 1759 dma_free_coherent(dev->dev,
1760 dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
1761 dev->host_mem_descs, dev->host_mem_descs_dma);
87ad72a5 1762 dev->host_mem_descs = NULL;
7e5dd57e 1763 dev->nr_host_mem_descs = 0;
87ad72a5
CH		 1764}
1765
92dc6895
CH		 1766static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
1767 u32 chunk_size)
9d713c2b 1768{
87ad72a5 1769 struct nvme_host_mem_buf_desc *descs;
92dc6895 1770 u32 max_entries, len;
4033f35d 1771 dma_addr_t descs_dma;
2ee0e4ed 1772 int i = 0;
87ad72a5 1773 void **bufs;
2ee0e4ed 1774 u64 size = 0, tmp;
87ad72a5 1775
87ad72a5
CH		 1776 tmp = (preferred + chunk_size - 1);
1777 do_div(tmp, chunk_size);
1778 max_entries = tmp;
044a9df1
CH		 1779
1780 if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
1781 max_entries = dev->ctrl.hmmaxd;
1782
4033f35d
CH		 1783 descs = dma_zalloc_coherent(dev->dev, max_entries * sizeof(*descs),
1784 &descs_dma, GFP_KERNEL);
87ad72a5
CH		 1785 if (!descs)
1786 goto out;
1787
1788 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
1789 if (!bufs)
1790 goto out_free_descs;
1791
244a8fe4 1792 for (size = 0; size < preferred && i < max_entries; size += len) {
87ad72a5
CH		 1793 dma_addr_t dma_addr;
1794
50cdb7c6 1795 len = min_t(u64, chunk_size, preferred - size);
87ad72a5
CH		 1796 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
1797 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1798 if (!bufs[i])
1799 break;
1800
1801 descs[i].addr = cpu_to_le64(dma_addr);
1802 descs[i].size = cpu_to_le32(len / dev->ctrl.page_size);
1803 i++;
1804 }
1805
92dc6895 1806 if (!size)
87ad72a5 1807 goto out_free_bufs;
87ad72a5 1808
87ad72a5
CH		 1809 dev->nr_host_mem_descs = i;
1810 dev->host_mem_size = size;
1811 dev->host_mem_descs = descs;
4033f35d 1812 dev->host_mem_descs_dma = descs_dma;
87ad72a5
CH		 1813 dev->host_mem_desc_bufs = bufs;
1814 return 0;
1815
1816out_free_bufs:
1817 while (--i >= 0) {
1818 size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size;
1819
1820 dma_free_coherent(dev->dev, size, bufs[i],
1821 le64_to_cpu(descs[i].addr));
1822 }
1823
1824 kfree(bufs);
1825out_free_descs:
4033f35d
CH		 1826 dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
1827 descs_dma);
87ad72a5 1828out:
87ad72a5
CH		 1829 dev->host_mem_descs = NULL;
1830 return -ENOMEM;
1831}
1832
92dc6895
CH		 1833static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
1834{
1835 u32 chunk_size;
1836
1837 /* start big and work our way down */
30f92d62 1838 for (chunk_size = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
044a9df1 1839 chunk_size >= max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
92dc6895
CH		 1840 chunk_size /= 2) {
1841 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
1842 if (!min || dev->host_mem_size >= min)
1843 return 0;
1844 nvme_free_host_mem(dev);
1845 }
1846 }
1847
1848 return -ENOMEM;
1849}
1850
9620cfba 1851static int nvme_setup_host_mem(struct nvme_dev *dev)
87ad72a5
CH		 1852{
1853 u64 max = (u64)max_host_mem_size_mb * SZ_1M;
1854 u64 preferred = (u64)dev->ctrl.hmpre * 4096;
1855 u64 min = (u64)dev->ctrl.hmmin * 4096;
1856 u32 enable_bits = NVME_HOST_MEM_ENABLE;
9620cfba 1857 int ret = 0;
87ad72a5
CH		 1858
1859 preferred = min(preferred, max);
1860 if (min > max) {
1861 dev_warn(dev->ctrl.device,
1862 "min host memory (%lld MiB) above limit (%d MiB).\n",
1863 min >> ilog2(SZ_1M), max_host_mem_size_mb);
1864 nvme_free_host_mem(dev);
9620cfba 1865 return 0;
87ad72a5
CH		 1866 }
1867
1868 /*
1869 * If we already have a buffer allocated check if we can reuse it.
1870 */
1871 if (dev->host_mem_descs) {
1872 if (dev->host_mem_size >= min)
1873 enable_bits |= NVME_HOST_MEM_RETURN;
1874 else
1875 nvme_free_host_mem(dev);
1876 }
1877
1878 if (!dev->host_mem_descs) {
92dc6895
CH		 1879 if (nvme_alloc_host_mem(dev, min, preferred)) {
1880 dev_warn(dev->ctrl.device,
1881 "failed to allocate host memory buffer.\n");
9620cfba 1882 return 0; /* controller must work without HMB */
92dc6895
CH		 1883 }
1884
1885 dev_info(dev->ctrl.device,
1886 "allocated %lld MiB host memory buffer.\n",
1887 dev->host_mem_size >> ilog2(SZ_1M));
87ad72a5
CH		 1888 }
1889
9620cfba
CH		 1890 ret = nvme_set_host_mem(dev, enable_bits);
1891 if (ret)
87ad72a5 1892 nvme_free_host_mem(dev);
9620cfba 1893 return ret;
9d713c2b
KB		 1894}
1895
8d85fce7 1896static int nvme_setup_io_queues(struct nvme_dev *dev)
b60503ba 1897{
a4aea562 1898 struct nvme_queue *adminq = dev->queues[0];
e75ec752 1899 struct pci_dev *pdev = to_pci_dev(dev->dev);
97f6ef64
XY		 1900 int result, nr_io_queues;
1901 unsigned long size;
b60503ba 1902
425a17cb 1903 nr_io_queues = num_present_cpus();
9a0be7ab
CH		 1904 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
1905 if (result < 0)
1b23484b 1906 return result;
9a0be7ab 1907
f5fa90dc 1908 if (nr_io_queues == 0)
a5229050 1909 return 0;
b60503ba 1910
8ffaadf7
JD		 1911 if (dev->cmb && NVME_CMB_SQS(dev->cmbsz)) {
1912 result = nvme_cmb_qdepth(dev, nr_io_queues,
1913 sizeof(struct nvme_command));
1914 if (result > 0)
1915 dev->q_depth = result;
1916 else
1917 nvme_release_cmb(dev);
1918 }
1919
97f6ef64
XY		 1920 do {
1921 size = db_bar_size(dev, nr_io_queues);
1922 result = nvme_remap_bar(dev, size);
1923 if (!result)
1924 break;
1925 if (!--nr_io_queues)
1926 return -ENOMEM;
1927 } while (1);
1928 adminq->q_db = dev->dbs;
f1938f6e 1929
9d713c2b 1930 /* Deregister the admin queue's interrupt */
0ff199cb 1931 pci_free_irq(pdev, 0, adminq);
9d713c2b 1932
e32efbfc
JA		 1933 /*
1934 * If we enable msix early due to not intx, disable it again before
1935 * setting up the full range we need.
1936 */
dca51e78
CH		 1937 pci_free_irq_vectors(pdev);
1938 nr_io_queues = pci_alloc_irq_vectors(pdev, 1, nr_io_queues,
1939 PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY);
1940 if (nr_io_queues <= 0)
1941 return -EIO;
1942 dev->max_qid = nr_io_queues;
fa08a396 1943
063a8096
MW		 1944 /*
1945 * Should investigate if there's a performance win from allocating
1946 * more queues than interrupt vectors; it might allow the submission
1947 * path to scale better, even if the receive path is limited by the
1948 * number of interrupts.
1949 */
063a8096 1950
dca51e78 1951 result = queue_request_irq(adminq);
758dd7fd
JD		 1952 if (result) {
1953 adminq->cq_vector = -1;
d4875622 1954 return result;
758dd7fd 1955 }
749941f2 1956 return nvme_create_io_queues(dev);
b60503ba
MW		 1957}
1958
2a842aca 1959static void nvme_del_queue_end(struct request *req, blk_status_t error)
a5768aa8 1960{
db3cbfff 1961 struct nvme_queue *nvmeq = req->end_io_data;
b5875222 1962
db3cbfff
KB		 1963 blk_mq_free_request(req);
1964 complete(&nvmeq->dev->ioq_wait);
a5768aa8
KB		 1965}
1966
2a842aca 1967static void nvme_del_cq_end(struct request *req, blk_status_t error)
a5768aa8 1968{
db3cbfff 1969 struct nvme_queue *nvmeq = req->end_io_data;
a5768aa8 1970
db3cbfff
KB		 1971 if (!error) {
1972 unsigned long flags;
1973
2e39e0f6
ML		 1974 /*
1975 * We might be called with the AQ q_lock held
1976 * and the I/O queue q_lock should always
1977 * nest inside the AQ one.
1978 */
1979 spin_lock_irqsave_nested(&nvmeq->q_lock, flags,
1980 SINGLE_DEPTH_NESTING);
db3cbfff
KB		 1981 nvme_process_cq(nvmeq);
1982 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
a5768aa8 1983 }
db3cbfff
KB		 1984
1985 nvme_del_queue_end(req, error);
a5768aa8
KB		 1986}
1987
db3cbfff 1988static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
bda4e0fb 1989{
db3cbfff
KB		 1990 struct request_queue *q = nvmeq->dev->ctrl.admin_q;
1991 struct request *req;
1992 struct nvme_command cmd;
bda4e0fb 1993
db3cbfff
KB		 1994 memset(&cmd, 0, sizeof(cmd));
1995 cmd.delete_queue.opcode = opcode;
1996 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
bda4e0fb 1997
eb71f435 1998 req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
db3cbfff
KB		 1999 if (IS_ERR(req))
2000 return PTR_ERR(req);
bda4e0fb 2001
db3cbfff
KB		 2002 req->timeout = ADMIN_TIMEOUT;
2003 req->end_io_data = nvmeq;
2004
2005 blk_execute_rq_nowait(q, NULL, req, false,
2006 opcode == nvme_admin_delete_cq ?
2007 nvme_del_cq_end : nvme_del_queue_end);
2008 return 0;
bda4e0fb
KB		 2009}
2010
70659060 2011static void nvme_disable_io_queues(struct nvme_dev *dev, int queues)
a5768aa8 2012{
70659060 2013 int pass;
db3cbfff
KB		 2014 unsigned long timeout;
2015 u8 opcode = nvme_admin_delete_sq;
a5768aa8 2016
db3cbfff 2017 for (pass = 0; pass < 2; pass++) {
014a0d60 2018 int sent = 0, i = queues;
db3cbfff
KB		 2019
2020 reinit_completion(&dev->ioq_wait);
2021 retry:
2022 timeout = ADMIN_TIMEOUT;
c21377f8
GKB		 2023 for (; i > 0; i--, sent++)
2024 if (nvme_delete_queue(dev->queues[i], opcode))
db3cbfff 2025 break;
c21377f8 2026
db3cbfff
KB		 2027 while (sent--) {
2028 timeout = wait_for_completion_io_timeout(&dev->ioq_wait, timeout);
2029 if (timeout == 0)
2030 return;
2031 if (i)
2032 goto retry;
2033 }
2034 opcode = nvme_admin_delete_cq;
2035 }
a5768aa8
KB		 2036}
2037
422ef0c7
MW		 2038/*
2039 * Return: error value if an error occurred setting up the queues or calling
2040 * Identify Device. 0 if these succeeded, even if adding some of the
2041 * namespaces failed. At the moment, these failures are silent. TBD which
2042 * failures should be reported.
2043 */
8d85fce7 2044static int nvme_dev_add(struct nvme_dev *dev)
b60503ba 2045{
5bae7f73 2046 if (!dev->ctrl.tagset) {
ffe7704d
KB		 2047 dev->tagset.ops = &nvme_mq_ops;
2048 dev->tagset.nr_hw_queues = dev->online_queues - 1;
2049 dev->tagset.timeout = NVME_IO_TIMEOUT;
2050 dev->tagset.numa_node = dev_to_node(dev->dev);
2051 dev->tagset.queue_depth =
a4aea562 2052 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
a7a7cbe3
CK		 2053 dev->tagset.cmd_size = nvme_pci_cmd_size(dev, false);
2054 if ((dev->ctrl.sgls & ((1 << 0) | (1 << 1))) && sgl_threshold) {
2055 dev->tagset.cmd_size = max(dev->tagset.cmd_size,
2056 nvme_pci_cmd_size(dev, true));
2057 }
ffe7704d
KB		 2058 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2059 dev->tagset.driver_data = dev;
b60503ba 2060
ffe7704d
KB		 2061 if (blk_mq_alloc_tag_set(&dev->tagset))
2062 return 0;
5bae7f73 2063 dev->ctrl.tagset = &dev->tagset;
f9f38e33
HK		 2064
2065 nvme_dbbuf_set(dev);
949928c1
KB		 2066 } else {
2067 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2068
2069 /* Free previously allocated queues that are no longer usable */
2070 nvme_free_queues(dev, dev->online_queues);
ffe7704d 2071 }
949928c1 2072
e1e5e564 2073 return 0;
b60503ba
MW		 2074}
2075
b00a726a 2076static int nvme_pci_enable(struct nvme_dev *dev)
0877cb0d 2077{
b00a726a 2078 int result = -ENOMEM;
e75ec752 2079 struct pci_dev *pdev = to_pci_dev(dev->dev);
0877cb0d
KB		 2080
2081 if (pci_enable_device_mem(pdev))
2082 return result;
2083
0877cb0d 2084 pci_set_master(pdev);
0877cb0d 2085
e75ec752
CH		 2086 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) &&
2087 dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32)))
052d0efa 2088 goto disable;
0877cb0d 2089
7a67cbea 2090 if (readl(dev->bar + NVME_REG_CSTS) == -1) {
0e53d180 2091 result = -ENODEV;
b00a726a 2092 goto disable;
0e53d180 2093 }
e32efbfc
JA		 2094
2095 /*
a5229050
KB		 2096 * Some devices and/or platforms don't advertise or work with INTx
2097 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2098 * adjust this later.
e32efbfc 2099 */
dca51e78
CH		 2100 result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
2101 if (result < 0)
2102 return result;
e32efbfc 2103
20d0dfe6 2104 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
7a67cbea 2105
20d0dfe6 2106 dev->q_depth = min_t(int, NVME_CAP_MQES(dev->ctrl.cap) + 1,
b27c1e68 2107 io_queue_depth);
20d0dfe6 2108 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
7a67cbea 2109 dev->dbs = dev->bar + 4096;
1f390c1f
SG		 2110
2111 /*
2112 * Temporary fix for the Apple controller found in the MacBook8,1 and
2113 * some MacBook7,1 to avoid controller resets and data loss.
2114 */
2115 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
2116 dev->q_depth = 2;
9bdcfb10
CH		 2117 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
2118 "set queue depth=%u to work around controller resets\n",
1f390c1f 2119 dev->q_depth);
d554b5e1
MP		 2120 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2121 (pdev->device == 0xa821 || pdev->device == 0xa822) &&
20d0dfe6 2122 NVME_CAP_MQES(dev->ctrl.cap) == 0) {
d554b5e1
MP		 2123 dev->q_depth = 64;
2124 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2125 "set queue depth=%u\n", dev->q_depth);
1f390c1f
SG		 2126 }
2127
202021c1
SB		 2128 /*
2129 * CMBs can currently only exist on >=1.2 PCIe devices. We only
1c78f773
MG		 2130 * populate sysfs if a CMB is implemented. Since nvme_dev_attrs_group
2131 * has no name we can pass NULL as final argument to
2132 * sysfs_add_file_to_group.
202021c1
SB		 2133 */
2134
8ef2074d 2135 if (readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 2, 0)) {
8ffaadf7 2136 dev->cmb = nvme_map_cmb(dev);
1c78f773 2137 if (dev->cmb) {
202021c1
SB		 2138 if (sysfs_add_file_to_group(&dev->ctrl.device->kobj,
2139 &dev_attr_cmb.attr, NULL))
9bdcfb10 2140 dev_warn(dev->ctrl.device,
202021c1
SB		 2141 "failed to add sysfs attribute for CMB\n");
2142 }
2143 }
2144
a0a3408e
KB		 2145 pci_enable_pcie_error_reporting(pdev);
2146 pci_save_state(pdev);
0877cb0d
KB		 2147 return 0;
2148
2149 disable:
0877cb0d
KB		 2150 pci_disable_device(pdev);
2151 return result;
2152}
2153
2154static void nvme_dev_unmap(struct nvme_dev *dev)
b00a726a
KB		 2155{
2156 if (dev->bar)
2157 iounmap(dev->bar);
a1f447b3 2158 pci_release_mem_regions(to_pci_dev(dev->dev));
b00a726a
KB		 2159}
2160
2161static void nvme_pci_disable(struct nvme_dev *dev)
0877cb0d 2162{
e75ec752
CH		 2163 struct pci_dev *pdev = to_pci_dev(dev->dev);
2164
f63572df 2165 nvme_release_cmb(dev);
dca51e78 2166 pci_free_irq_vectors(pdev);
0877cb0d 2167
a0a3408e
KB		 2168 if (pci_is_enabled(pdev)) {
2169 pci_disable_pcie_error_reporting(pdev);
e75ec752 2170 pci_disable_device(pdev);
4d115420 2171 }
4d115420
KB		 2172}
2173
a5cdb68c 2174static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
b60503ba 2175{
70659060 2176 int i, queues;
302ad8cc
KB		 2177 bool dead = true;
2178 struct pci_dev *pdev = to_pci_dev(dev->dev);
22404274 2179
77bf25ea 2180 mutex_lock(&dev->shutdown_lock);
302ad8cc
KB		 2181 if (pci_is_enabled(pdev)) {
2182 u32 csts = readl(dev->bar + NVME_REG_CSTS);
2183
ebef7368
KB		 2184 if (dev->ctrl.state == NVME_CTRL_LIVE ||
2185 dev->ctrl.state == NVME_CTRL_RESETTING)
302ad8cc
KB		 2186 nvme_start_freeze(&dev->ctrl);
2187 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
2188 pdev->error_state != pci_channel_io_normal);
c9d3bf88 2189 }
c21377f8 2190
302ad8cc
KB		 2191 /*
2192 * Give the controller a chance to complete all entered requests if
2193 * doing a safe shutdown.
2194 */
87ad72a5
CH		 2195 if (!dead) {
2196 if (shutdown)
2197 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
2198
2199 /*
2200 * If the controller is still alive tell it to stop using the
2201 * host memory buffer. In theory the shutdown / reset should
2202 * make sure that it doesn't access the host memoery anymore,
2203 * but I'd rather be safe than sorry..
2204 */
2205 if (dev->host_mem_descs)
2206 nvme_set_host_mem(dev, 0);
2207
2208 }
302ad8cc
KB		 2209 nvme_stop_queues(&dev->ctrl);
2210
70659060 2211 queues = dev->online_queues - 1;
d858e5f0 2212 for (i = dev->ctrl.queue_count - 1; i > 0; i--)
c21377f8
GKB		 2213 nvme_suspend_queue(dev->queues[i]);
2214
302ad8cc 2215 if (dead) {
82469c59
GKB		 2216 /* A device might become IO incapable very soon during
2217 * probe, before the admin queue is configured. Thus,
2218 * queue_count can be 0 here.
2219 */
d858e5f0 2220 if (dev->ctrl.queue_count)
82469c59 2221 nvme_suspend_queue(dev->queues[0]);
4d115420 2222 } else {
70659060 2223 nvme_disable_io_queues(dev, queues);
a5cdb68c 2224 nvme_disable_admin_queue(dev, shutdown);
4d115420 2225 }
b00a726a 2226 nvme_pci_disable(dev);
07836e65 2227
e1958e65
ML		 2228 blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
2229 blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
302ad8cc
KB		 2230
2231 /*
2232 * The driver will not be starting up queues again if shutting down so
2233 * must flush all entered requests to their failed completion to avoid
2234 * deadlocking blk-mq hot-cpu notifier.
2235 */
2236 if (shutdown)
2237 nvme_start_queues(&dev->ctrl);
77bf25ea 2238 mutex_unlock(&dev->shutdown_lock);
b60503ba
MW		 2239}
2240
091b6092
MW		 2241static int nvme_setup_prp_pools(struct nvme_dev *dev)
2242{
e75ec752 2243 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
091b6092
MW		 2244 PAGE_SIZE, PAGE_SIZE, 0);
2245 if (!dev->prp_page_pool)
2246 return -ENOMEM;
2247
99802a7a 2248 /* Optimisation for I/Os between 4k and 128k */
e75ec752 2249 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
99802a7a
MW		 2250 256, 256, 0);
2251 if (!dev->prp_small_pool) {
2252 dma_pool_destroy(dev->prp_page_pool);
2253 return -ENOMEM;
2254 }
091b6092
MW		 2255 return 0;
2256}
2257
2258static void nvme_release_prp_pools(struct nvme_dev *dev)
2259{
2260 dma_pool_destroy(dev->prp_page_pool);
99802a7a 2261 dma_pool_destroy(dev->prp_small_pool);
091b6092
MW		 2262}
2263
1673f1f0 2264static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
5e82e952 2265{
1673f1f0 2266 struct nvme_dev *dev = to_nvme_dev(ctrl);
9ac27090 2267
f9f38e33 2268 nvme_dbbuf_dma_free(dev);
e75ec752 2269 put_device(dev->dev);
4af0e21c
KB		 2270 if (dev->tagset.tags)
2271 blk_mq_free_tag_set(&dev->tagset);
1c63dc66
CH		 2272 if (dev->ctrl.admin_q)
2273 blk_put_queue(dev->ctrl.admin_q);
5e82e952 2274 kfree(dev->queues);
e286bcfc 2275 free_opal_dev(dev->ctrl.opal_dev);
5e82e952
KB		 2276 kfree(dev);
2277}
2278
f58944e2
KB		 2279static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status)
2280{
237045fc 2281 dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status);
f58944e2 2282
d22524a4 2283 nvme_get_ctrl(&dev->ctrl);
69d9a99c 2284 nvme_dev_disable(dev, false);
03e0f3a6 2285 if (!queue_work(nvme_wq, &dev->remove_work))
f58944e2
KB		 2286 nvme_put_ctrl(&dev->ctrl);
2287}
2288
fd634f41 2289static void nvme_reset_work(struct work_struct *work)
5e82e952 2290{
d86c4d8e
CH		 2291 struct nvme_dev *dev =
2292 container_of(work, struct nvme_dev, ctrl.reset_work);
a98e58e5 2293 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
f58944e2 2294 int result = -ENODEV;
5e82e952 2295
82b057ca 2296 if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING))
fd634f41 2297 goto out;
5e82e952 2298
fd634f41
CH		 2299 /*
2300 * If we're called to reset a live controller first shut it down before
2301 * moving on.
2302 */
b00a726a 2303 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
a5cdb68c 2304 nvme_dev_disable(dev, false);
5e82e952 2305
b00a726a 2306 result = nvme_pci_enable(dev);
f0b50732 2307 if (result)
3cf519b5 2308 goto out;
f0b50732 2309
01ad0990 2310 result = nvme_pci_configure_admin_queue(dev);
f0b50732 2311 if (result)
f58944e2 2312 goto out;
f0b50732 2313
0fb59cbc
KB		 2314 result = nvme_alloc_admin_tags(dev);
2315 if (result)
f58944e2 2316 goto out;
b9afca3e 2317
ce4541f4
CH		 2318 result = nvme_init_identify(&dev->ctrl);
2319 if (result)
f58944e2 2320 goto out;
ce4541f4 2321
e286bcfc
SB		 2322 if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
2323 if (!dev->ctrl.opal_dev)
2324 dev->ctrl.opal_dev =
2325 init_opal_dev(&dev->ctrl, &nvme_sec_submit);
2326 else if (was_suspend)
2327 opal_unlock_from_suspend(dev->ctrl.opal_dev);
2328 } else {
2329 free_opal_dev(dev->ctrl.opal_dev);
2330 dev->ctrl.opal_dev = NULL;
4f1244c8 2331 }
a98e58e5 2332
f9f38e33
HK		 2333 if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) {
2334 result = nvme_dbbuf_dma_alloc(dev);
2335 if (result)
2336 dev_warn(dev->dev,
2337 "unable to allocate dma for dbbuf\n");
2338 }
2339
9620cfba
CH		 2340 if (dev->ctrl.hmpre) {
2341 result = nvme_setup_host_mem(dev);
2342 if (result < 0)
2343 goto out;
2344 }
87ad72a5 2345
f0b50732 2346 result = nvme_setup_io_queues(dev);
badc34d4 2347 if (result)
f58944e2 2348 goto out;
f0b50732 2349
2659e57b
CH		 2350 /*
2351 * Keep the controller around but remove all namespaces if we don't have
2352 * any working I/O queue.
2353 */
3cf519b5 2354 if (dev->online_queues < 2) {
1b3c47c1 2355 dev_warn(dev->ctrl.device, "IO queues not created\n");
3b24774e 2356 nvme_kill_queues(&dev->ctrl);
5bae7f73 2357 nvme_remove_namespaces(&dev->ctrl);
3cf519b5 2358 } else {
25646264 2359 nvme_start_queues(&dev->ctrl);
302ad8cc 2360 nvme_wait_freeze(&dev->ctrl);
3cf519b5 2361 nvme_dev_add(dev);
302ad8cc 2362 nvme_unfreeze(&dev->ctrl);
3cf519b5
CH		 2363 }
2364
bb8d261e
CH		 2365 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
2366 dev_warn(dev->ctrl.device, "failed to mark controller live\n");
2367 goto out;
2368 }
92911a55 2369
d09f2b45 2370 nvme_start_ctrl(&dev->ctrl);
3cf519b5 2371 return;
f0b50732 2372
3cf519b5 2373 out:
f58944e2 2374 nvme_remove_dead_ctrl(dev, result);
f0b50732
KB		 2375}
2376
5c8809e6 2377static void nvme_remove_dead_ctrl_work(struct work_struct *work)
9a6b9458 2378{
5c8809e6 2379 struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
e75ec752 2380 struct pci_dev *pdev = to_pci_dev(dev->dev);
9a6b9458 2381
69d9a99c 2382 nvme_kill_queues(&dev->ctrl);
9a6b9458 2383 if (pci_get_drvdata(pdev))
921920ab 2384 device_release_driver(&pdev->dev);
1673f1f0 2385 nvme_put_ctrl(&dev->ctrl);
9a6b9458
KB		 2386}
2387
1c63dc66 2388static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
9ca97374 2389{
1c63dc66 2390 *val = readl(to_nvme_dev(ctrl)->bar + off);
90667892 2391 return 0;
9ca97374
TH		 2392}
2393
5fd4ce1b 2394static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
4cc06521 2395{
5fd4ce1b
CH		 2396 writel(val, to_nvme_dev(ctrl)->bar + off);
2397 return 0;
2398}
4cc06521 2399
7fd8930f
CH		 2400static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2401{
2402 *val = readq(to_nvme_dev(ctrl)->bar + off);
2403 return 0;
4cc06521
KB		 2404}
2405
1c63dc66 2406static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
1a353d85 2407 .name = "pcie",
e439bb12 2408 .module = THIS_MODULE,
c81bfba9 2409 .flags = NVME_F_METADATA_SUPPORTED,
1c63dc66 2410 .reg_read32 = nvme_pci_reg_read32,
5fd4ce1b 2411 .reg_write32 = nvme_pci_reg_write32,
7fd8930f 2412 .reg_read64 = nvme_pci_reg_read64,
1673f1f0 2413 .free_ctrl = nvme_pci_free_ctrl,
f866fc42 2414 .submit_async_event = nvme_pci_submit_async_event,
1c63dc66 2415};
4cc06521 2416
b00a726a
KB		 2417static int nvme_dev_map(struct nvme_dev *dev)
2418{
b00a726a
KB		 2419 struct pci_dev *pdev = to_pci_dev(dev->dev);
2420
a1f447b3 2421 if (pci_request_mem_regions(pdev, "nvme"))
b00a726a
KB		 2422 return -ENODEV;
2423
97f6ef64 2424 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
b00a726a
KB		 2425 goto release;
2426
9fa196e7 2427 return 0;
b00a726a 2428 release:
9fa196e7
MG		 2429 pci_release_mem_regions(pdev);
2430 return -ENODEV;
b00a726a
KB		 2431}
2432
8427bbc2 2433static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
ff5350a8
AL		 2434{
2435 if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
2436 /*
2437 * Several Samsung devices seem to drop off the PCIe bus
2438 * randomly when APST is on and uses the deepest sleep state.
2439 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2440 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2441 * 950 PRO 256GB", but it seems to be restricted to two Dell
2442 * laptops.
2443 */
2444 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
2445 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
2446 dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
2447 return NVME_QUIRK_NO_DEEPEST_PS;
8427bbc2
KHF		 2448 } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
2449 /*
2450 * Samsung SSD 960 EVO drops off the PCIe bus after system
2451 * suspend on a Ryzen board, ASUS PRIME B350M-A.
2452 */
2453 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
2454 dmi_match(DMI_BOARD_NAME, "PRIME B350M-A"))
2455 return NVME_QUIRK_NO_APST;
ff5350a8
AL		 2456 }
2457
2458 return 0;
2459}
2460
8d85fce7 2461static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
b60503ba 2462{
a4aea562 2463 int node, result = -ENOMEM;
b60503ba 2464 struct nvme_dev *dev;
ff5350a8 2465 unsigned long quirks = id->driver_data;
b60503ba 2466
a4aea562
MB		 2467 node = dev_to_node(&pdev->dev);
2468 if (node == NUMA_NO_NODE)
2fa84351 2469 set_dev_node(&pdev->dev, first_memory_node);
a4aea562
MB		 2470
2471 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
b60503ba
MW		 2472 if (!dev)
2473 return -ENOMEM;
a4aea562
MB		 2474 dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *),
2475 GFP_KERNEL, node);
b60503ba
MW		 2476 if (!dev->queues)
2477 goto free;
2478
e75ec752 2479 dev->dev = get_device(&pdev->dev);
9a6b9458 2480 pci_set_drvdata(pdev, dev);
1c63dc66 2481
b00a726a
KB		 2482 result = nvme_dev_map(dev);
2483 if (result)
b00c9b7a 2484 goto put_pci;
b00a726a 2485
d86c4d8e 2486 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
5c8809e6 2487 INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
77bf25ea 2488 mutex_init(&dev->shutdown_lock);
db3cbfff 2489 init_completion(&dev->ioq_wait);
b60503ba 2490
091b6092
MW		 2491 result = nvme_setup_prp_pools(dev);
2492 if (result)
b00c9b7a 2493 goto unmap;
4cc06521 2494
8427bbc2 2495 quirks |= check_vendor_combination_bug(pdev);
ff5350a8 2496
f3ca80fc 2497 result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
ff5350a8 2498 quirks);
4cc06521 2499 if (result)
2e1d8448 2500 goto release_pools;
740216fc 2501
82b057ca 2502 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_RESETTING);
1b3c47c1
SG		 2503 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
2504
d86c4d8e 2505 queue_work(nvme_wq, &dev->ctrl.reset_work);
b60503ba
MW		 2506 return 0;
2507
0877cb0d 2508 release_pools:
091b6092 2509 nvme_release_prp_pools(dev);
b00c9b7a
CJ		 2510 unmap:
2511 nvme_dev_unmap(dev);
a96d4f5c 2512 put_pci:
e75ec752 2513 put_device(dev->dev);
b60503ba
MW		 2514 free:
2515 kfree(dev->queues);
b60503ba
MW		 2516 kfree(dev);
2517 return result;
2518}
2519
775755ed 2520static void nvme_reset_prepare(struct pci_dev *pdev)
f0d54a54 2521{
a6739479 2522 struct nvme_dev *dev = pci_get_drvdata(pdev);
f263fbb8 2523 nvme_dev_disable(dev, false);
775755ed 2524}
f0d54a54 2525
775755ed
CH		 2526static void nvme_reset_done(struct pci_dev *pdev)
2527{
f263fbb8
LT		 2528 struct nvme_dev *dev = pci_get_drvdata(pdev);
2529 nvme_reset_ctrl(&dev->ctrl);
f0d54a54
KB		 2530}
2531
09ece142
KB		 2532static void nvme_shutdown(struct pci_dev *pdev)
2533{
2534 struct nvme_dev *dev = pci_get_drvdata(pdev);
a5cdb68c 2535 nvme_dev_disable(dev, true);
09ece142
KB		 2536}
2537
f58944e2
KB		 2538/*
2539 * The driver's remove may be called on a device in a partially initialized
2540 * state. This function must not have any dependencies on the device state in
2541 * order to proceed.
2542 */
8d85fce7 2543static void nvme_remove(struct pci_dev *pdev)
b60503ba
MW		 2544{
2545 struct nvme_dev *dev = pci_get_drvdata(pdev);
9a6b9458 2546
bb8d261e
CH		 2547 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
2548
d86c4d8e 2549 cancel_work_sync(&dev->ctrl.reset_work);
9a6b9458 2550 pci_set_drvdata(pdev, NULL);
0ff9d4e1 2551
6db28eda 2552 if (!pci_device_is_present(pdev)) {
0ff9d4e1 2553 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
6db28eda
KB		 2554 nvme_dev_disable(dev, false);
2555 }
0ff9d4e1 2556
d86c4d8e 2557 flush_work(&dev->ctrl.reset_work);
d09f2b45
SG		 2558 nvme_stop_ctrl(&dev->ctrl);
2559 nvme_remove_namespaces(&dev->ctrl);
a5cdb68c 2560 nvme_dev_disable(dev, true);
87ad72a5 2561 nvme_free_host_mem(dev);
a4aea562 2562 nvme_dev_remove_admin(dev);
a1a5ef99 2563 nvme_free_queues(dev, 0);
d09f2b45 2564 nvme_uninit_ctrl(&dev->ctrl);
9a6b9458 2565 nvme_release_prp_pools(dev);
b00a726a 2566 nvme_dev_unmap(dev);
1673f1f0 2567 nvme_put_ctrl(&dev->ctrl);
b60503ba
MW		 2568}
2569
13880f5b
KB		 2570static int nvme_pci_sriov_configure(struct pci_dev *pdev, int numvfs)
2571{
2572 int ret = 0;
2573
2574 if (numvfs == 0) {
2575 if (pci_vfs_assigned(pdev)) {
2576 dev_warn(&pdev->dev,
2577 "Cannot disable SR-IOV VFs while assigned\n");
2578 return -EPERM;
2579 }
2580 pci_disable_sriov(pdev);
2581 return 0;
2582 }
2583
2584 ret = pci_enable_sriov(pdev, numvfs);
2585 return ret ? ret : numvfs;
2586}
2587
671a6018 2588#ifdef CONFIG_PM_SLEEP
cd638946
KB		 2589static int nvme_suspend(struct device *dev)
2590{
2591 struct pci_dev *pdev = to_pci_dev(dev);
2592 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2593
a5cdb68c 2594 nvme_dev_disable(ndev, true);
cd638946
KB		 2595 return 0;
2596}
2597
2598static int nvme_resume(struct device *dev)
2599{
2600 struct pci_dev *pdev = to_pci_dev(dev);
2601 struct nvme_dev *ndev = pci_get_drvdata(pdev);
cd638946 2602
d86c4d8e 2603 nvme_reset_ctrl(&ndev->ctrl);
9a6b9458 2604 return 0;
cd638946 2605}
671a6018 2606#endif
cd638946
KB		 2607
2608static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
b60503ba 2609
a0a3408e
KB		 2610static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
2611 pci_channel_state_t state)
2612{
2613 struct nvme_dev *dev = pci_get_drvdata(pdev);
2614
2615 /*
2616 * A frozen channel requires a reset. When detected, this method will
2617 * shutdown the controller to quiesce. The controller will be restarted
2618 * after the slot reset through driver's slot_reset callback.
2619 */
a0a3408e
KB		 2620 switch (state) {
2621 case pci_channel_io_normal:
2622 return PCI_ERS_RESULT_CAN_RECOVER;
2623 case pci_channel_io_frozen:
d011fb31
KB		 2624 dev_warn(dev->ctrl.device,
2625 "frozen state error detected, reset controller\n");
a5cdb68c 2626 nvme_dev_disable(dev, false);
a0a3408e
KB		 2627 return PCI_ERS_RESULT_NEED_RESET;
2628 case pci_channel_io_perm_failure:
d011fb31
KB		 2629 dev_warn(dev->ctrl.device,
2630 "failure state error detected, request disconnect\n");
a0a3408e
KB		 2631 return PCI_ERS_RESULT_DISCONNECT;
2632 }
2633 return PCI_ERS_RESULT_NEED_RESET;
2634}
2635
2636static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
2637{
2638 struct nvme_dev *dev = pci_get_drvdata(pdev);
2639
1b3c47c1 2640 dev_info(dev->ctrl.device, "restart after slot reset\n");
a0a3408e 2641 pci_restore_state(pdev);
d86c4d8e 2642 nvme_reset_ctrl(&dev->ctrl);
a0a3408e
KB		 2643 return PCI_ERS_RESULT_RECOVERED;
2644}
2645
2646static void nvme_error_resume(struct pci_dev *pdev)
2647{
2648 pci_cleanup_aer_uncorrect_error_status(pdev);
2649}
2650
1d352035 2651static const struct pci_error_handlers nvme_err_handler = {
b60503ba 2652 .error_detected = nvme_error_detected,
b60503ba
MW		 2653 .slot_reset = nvme_slot_reset,
2654 .resume = nvme_error_resume,
775755ed
CH		 2655 .reset_prepare = nvme_reset_prepare,
2656 .reset_done = nvme_reset_done,
b60503ba
MW		 2657};
2658
6eb0d698 2659static const struct pci_device_id nvme_id_table[] = {
106198ed 2660 { PCI_VDEVICE(INTEL, 0x0953),
08095e70 2661 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 2662 NVME_QUIRK_DEALLOCATE_ZEROES, },
99466e70
KB		 2663 { PCI_VDEVICE(INTEL, 0x0a53),
2664 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 2665 NVME_QUIRK_DEALLOCATE_ZEROES, },
99466e70
KB		 2666 { PCI_VDEVICE(INTEL, 0x0a54),
2667 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 2668 NVME_QUIRK_DEALLOCATE_ZEROES, },
f99cb7af
DWF		 2669 { PCI_VDEVICE(INTEL, 0x0a55),
2670 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2671 NVME_QUIRK_DEALLOCATE_ZEROES, },
50af47d0
AL		 2672 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */
2673 .driver_data = NVME_QUIRK_NO_DEEPEST_PS },
540c801c
KB		 2674 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */
2675 .driver_data = NVME_QUIRK_IDENTIFY_CNS, },
54adc010
GP		 2676 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
2677 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
8c97eecc
JL		 2678 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */
2679 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
015282c9
WW		 2680 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
2681 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
d554b5e1
MP		 2682 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */
2683 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2684 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */
2685 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
608cc4b1
CH		 2686 { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */
2687 .driver_data = NVME_QUIRK_LIGHTNVM, },
2688 { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */
2689 .driver_data = NVME_QUIRK_LIGHTNVM, },
b60503ba 2690 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
c74dc780 2691 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) },
124298bd 2692 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
b60503ba
MW		 2693 { 0, }
2694};
2695MODULE_DEVICE_TABLE(pci, nvme_id_table);
2696
2697static struct pci_driver nvme_driver = {
2698 .name = "nvme",
2699 .id_table = nvme_id_table,
2700 .probe = nvme_probe,
8d85fce7 2701 .remove = nvme_remove,
09ece142 2702 .shutdown = nvme_shutdown,
cd638946
KB		 2703 .driver = {
2704 .pm = &nvme_dev_pm_ops,
2705 },
13880f5b 2706 .sriov_configure = nvme_pci_sriov_configure,
b60503ba
MW		 2707 .err_handler = &nvme_err_handler,
2708};
2709
2710static int __init nvme_init(void)
2711{
9a6327d2 2712 return pci_register_driver(&nvme_driver);
b60503ba
MW		 2713}
2714
2715static void __exit nvme_exit(void)
2716{
2717 pci_unregister_driver(&nvme_driver);
03e0f3a6 2718 flush_workqueue(nvme_wq);
21bd78bc 2719 _nvme_check_size();
b60503ba
MW		 2720}
2721
2722MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2723MODULE_LICENSE("GPL");
c78b4713 2724MODULE_VERSION("1.0");
b60503ba
MW		 2725module_init(nvme_init);
2726module_exit(nvme_exit);
Linux 6.x block layer and io_uring tree(s)