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nvme-pci: unquiesce dead controller queues
[linux-2.6-block.git] / drivers / nvme / host / pci.c
CommitLineData
b60503ba
MW		 1/*
2 * NVM Express device driver
6eb0d698 3 * Copyright (c) 2011-2014, Intel Corporation.
b60503ba
MW		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
b60503ba
MW		 13 */
14
a0a3408e 15#include <linux/aer.h>
18119775 16#include <linux/async.h>
b60503ba 17#include <linux/blkdev.h>
a4aea562 18#include <linux/blk-mq.h>
dca51e78 19#include <linux/blk-mq-pci.h>
ff5350a8 20#include <linux/dmi.h>
b60503ba
MW		 21#include <linux/init.h>
22#include <linux/interrupt.h>
23#include <linux/io.h>
b60503ba
MW		 24#include <linux/mm.h>
25#include <linux/module.h>
77bf25ea 26#include <linux/mutex.h>
d0877473 27#include <linux/once.h>
b60503ba 28#include <linux/pci.h>
e1e5e564 29#include <linux/t10-pi.h>
b60503ba 30#include <linux/types.h>
2f8e2c87 31#include <linux/io-64-nonatomic-lo-hi.h>
a98e58e5 32#include <linux/sed-opal.h>
797a796a 33
f11bb3e2
CH		 34#include "nvme.h"
35
b60503ba
MW		 36#define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
37#define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
c965809c 38
a7a7cbe3 39#define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc))
9d43cf64 40
58ffacb5
MW		 41static int use_threaded_interrupts;
42module_param(use_threaded_interrupts, int, 0);
43
8ffaadf7
JD		 44static bool use_cmb_sqes = true;
45module_param(use_cmb_sqes, bool, 0644);
46MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
47
87ad72a5
CH		 48static unsigned int max_host_mem_size_mb = 128;
49module_param(max_host_mem_size_mb, uint, 0444);
50MODULE_PARM_DESC(max_host_mem_size_mb,
51 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
1fa6aead 52
a7a7cbe3
CK		 53static unsigned int sgl_threshold = SZ_32K;
54module_param(sgl_threshold, uint, 0644);
55MODULE_PARM_DESC(sgl_threshold,
56 "Use SGLs when average request segment size is larger or equal to "
57 "this size. Use 0 to disable SGLs.");
58
b27c1e68 59static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
60static const struct kernel_param_ops io_queue_depth_ops = {
61 .set = io_queue_depth_set,
62 .get = param_get_int,
63};
64
65static int io_queue_depth = 1024;
66module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
67MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2");
68
1c63dc66
CH		 69struct nvme_dev;
70struct nvme_queue;
b3fffdef 71
a5cdb68c 72static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
d4b4ff8e 73
1c63dc66
CH		 74/*
75 * Represents an NVM Express device. Each nvme_dev is a PCI function.
76 */
77struct nvme_dev {
147b27e4 78 struct nvme_queue *queues;
1c63dc66
CH		 79 struct blk_mq_tag_set tagset;
80 struct blk_mq_tag_set admin_tagset;
81 u32 __iomem *dbs;
82 struct device *dev;
83 struct dma_pool *prp_page_pool;
84 struct dma_pool *prp_small_pool;
1c63dc66
CH		 85 unsigned online_queues;
86 unsigned max_qid;
22b55601 87 unsigned int num_vecs;
1c63dc66
CH		 88 int q_depth;
89 u32 db_stride;
1c63dc66 90 void __iomem *bar;
97f6ef64 91 unsigned long bar_mapped_size;
5c8809e6 92 struct work_struct remove_work;
77bf25ea 93 struct mutex shutdown_lock;
1c63dc66 94 bool subsystem;
1c63dc66 95 void __iomem *cmb;
8969f1f8 96 pci_bus_addr_t cmb_bus_addr;
1c63dc66
CH		 97 u64 cmb_size;
98 u32 cmbsz;
202021c1 99 u32 cmbloc;
1c63dc66 100 struct nvme_ctrl ctrl;
db3cbfff 101 struct completion ioq_wait;
87ad72a5
CH		 102
103 /* shadow doorbell buffer support: */
f9f38e33
HK		 104 u32 *dbbuf_dbs;
105 dma_addr_t dbbuf_dbs_dma_addr;
106 u32 *dbbuf_eis;
107 dma_addr_t dbbuf_eis_dma_addr;
87ad72a5
CH		 108
109 /* host memory buffer support: */
110 u64 host_mem_size;
111 u32 nr_host_mem_descs;
4033f35d 112 dma_addr_t host_mem_descs_dma;
87ad72a5
CH		 113 struct nvme_host_mem_buf_desc *host_mem_descs;
114 void **host_mem_desc_bufs;
4d115420 115};
1fa6aead 116
b27c1e68 117static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
118{
119 int n = 0, ret;
120
121 ret = kstrtoint(val, 10, &n);
122 if (ret != 0 || n < 2)
123 return -EINVAL;
124
125 return param_set_int(val, kp);
126}
127
f9f38e33
HK		 128static inline unsigned int sq_idx(unsigned int qid, u32 stride)
129{
130 return qid * 2 * stride;
131}
132
133static inline unsigned int cq_idx(unsigned int qid, u32 stride)
134{
135 return (qid * 2 + 1) * stride;
136}
137
1c63dc66
CH		 138static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
139{
140 return container_of(ctrl, struct nvme_dev, ctrl);
141}
142
b60503ba
MW		 143/*
144 * An NVM Express queue. Each device has at least two (one for admin
145 * commands and one for I/O commands).
146 */
147struct nvme_queue {
148 struct device *q_dmadev;
091b6092 149 struct nvme_dev *dev;
1ab0cd69 150 spinlock_t sq_lock;
b60503ba 151 struct nvme_command *sq_cmds;
8ffaadf7 152 struct nvme_command __iomem *sq_cmds_io;
1ab0cd69 153 spinlock_t cq_lock ____cacheline_aligned_in_smp;
b60503ba 154 volatile struct nvme_completion *cqes;
42483228 155 struct blk_mq_tags **tags;
b60503ba
MW		 156 dma_addr_t sq_dma_addr;
157 dma_addr_t cq_dma_addr;
b60503ba
MW		 158 u32 __iomem *q_db;
159 u16 q_depth;
6222d172 160 s16 cq_vector;
b60503ba
MW		 161 u16 sq_tail;
162 u16 cq_head;
68fa9dbe 163 u16 last_cq_head;
c30341dc 164 u16 qid;
e9539f47 165 u8 cq_phase;
f9f38e33
HK		 166 u32 *dbbuf_sq_db;
167 u32 *dbbuf_cq_db;
168 u32 *dbbuf_sq_ei;
169 u32 *dbbuf_cq_ei;
b60503ba
MW		 170};
171
71bd150c
CH		 172/*
173 * The nvme_iod describes the data in an I/O, including the list of PRP
174 * entries. You can't see it in this data structure because C doesn't let
f4800d6d 175 * me express that. Use nvme_init_iod to ensure there's enough space
71bd150c
CH		 176 * allocated to store the PRP list.
177 */
178struct nvme_iod {
d49187e9 179 struct nvme_request req;
f4800d6d 180 struct nvme_queue *nvmeq;
a7a7cbe3 181 bool use_sgl;
f4800d6d 182 int aborted;
71bd150c 183 int npages; /* In the PRP list. 0 means small pool in use */
71bd150c
CH		 184 int nents; /* Used in scatterlist */
185 int length; /* Of data, in bytes */
186 dma_addr_t first_dma;
bf684057 187 struct scatterlist meta_sg; /* metadata requires single contiguous buffer */
f4800d6d
CH		 188 struct scatterlist *sg;
189 struct scatterlist inline_sg[0];
b60503ba
MW		 190};
191
192/*
193 * Check we didin't inadvertently grow the command struct
194 */
195static inline void _nvme_check_size(void)
196{
197 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
198 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
199 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
200 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
201 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
f8ebf840 202 BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
c30341dc 203 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
b60503ba 204 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
0add5e8e
JT		 205 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != NVME_IDENTIFY_DATA_SIZE);
206 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != NVME_IDENTIFY_DATA_SIZE);
b60503ba 207 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
6ecec745 208 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
f9f38e33
HK		 209 BUILD_BUG_ON(sizeof(struct nvme_dbbuf) != 64);
210}
211
212static inline unsigned int nvme_dbbuf_size(u32 stride)
213{
214 return ((num_possible_cpus() + 1) * 8 * stride);
215}
216
217static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
218{
219 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
220
221 if (dev->dbbuf_dbs)
222 return 0;
223
224 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
225 &dev->dbbuf_dbs_dma_addr,
226 GFP_KERNEL);
227 if (!dev->dbbuf_dbs)
228 return -ENOMEM;
229 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
230 &dev->dbbuf_eis_dma_addr,
231 GFP_KERNEL);
232 if (!dev->dbbuf_eis) {
233 dma_free_coherent(dev->dev, mem_size,
234 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
235 dev->dbbuf_dbs = NULL;
236 return -ENOMEM;
237 }
238
239 return 0;
240}
241
242static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
243{
244 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
245
246 if (dev->dbbuf_dbs) {
247 dma_free_coherent(dev->dev, mem_size,
248 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
249 dev->dbbuf_dbs = NULL;
250 }
251 if (dev->dbbuf_eis) {
252 dma_free_coherent(dev->dev, mem_size,
253 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
254 dev->dbbuf_eis = NULL;
255 }
256}
257
258static void nvme_dbbuf_init(struct nvme_dev *dev,
259 struct nvme_queue *nvmeq, int qid)
260{
261 if (!dev->dbbuf_dbs || !qid)
262 return;
263
264 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
265 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
266 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
267 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
268}
269
270static void nvme_dbbuf_set(struct nvme_dev *dev)
271{
272 struct nvme_command c;
273
274 if (!dev->dbbuf_dbs)
275 return;
276
277 memset(&c, 0, sizeof(c));
278 c.dbbuf.opcode = nvme_admin_dbbuf;
279 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
280 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
281
282 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
9bdcfb10 283 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
f9f38e33
HK		 284 /* Free memory and continue on */
285 nvme_dbbuf_dma_free(dev);
286 }
287}
288
289static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
290{
291 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
292}
293
294/* Update dbbuf and return true if an MMIO is required */
295static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
296 volatile u32 *dbbuf_ei)
297{
298 if (dbbuf_db) {
299 u16 old_value;
300
301 /*
302 * Ensure that the queue is written before updating
303 * the doorbell in memory
304 */
305 wmb();
306
307 old_value = *dbbuf_db;
308 *dbbuf_db = value;
309
310 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value))
311 return false;
312 }
313
314 return true;
b60503ba
MW		 315}
316
ac3dd5bd
JA		 317/*
318 * Max size of iod being embedded in the request payload
319 */
320#define NVME_INT_PAGES 2
5fd4ce1b 321#define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size)
ac3dd5bd
JA		 322
323/*
324 * Will slightly overestimate the number of pages needed. This is OK
325 * as it only leads to a small amount of wasted memory for the lifetime of
326 * the I/O.
327 */
328static int nvme_npages(unsigned size, struct nvme_dev *dev)
329{
5fd4ce1b
CH		 330 unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size,
331 dev->ctrl.page_size);
ac3dd5bd
JA		 332 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
333}
334
a7a7cbe3
CK		 335/*
336 * Calculates the number of pages needed for the SGL segments. For example a 4k
337 * page can accommodate 256 SGL descriptors.
338 */
339static int nvme_pci_npages_sgl(unsigned int num_seg)
ac3dd5bd 340{
a7a7cbe3 341 return DIV_ROUND_UP(num_seg * sizeof(struct nvme_sgl_desc), PAGE_SIZE);
f4800d6d 342}
ac3dd5bd 343
a7a7cbe3
CK		 344static unsigned int nvme_pci_iod_alloc_size(struct nvme_dev *dev,
345 unsigned int size, unsigned int nseg, bool use_sgl)
f4800d6d 346{
a7a7cbe3
CK		 347 size_t alloc_size;
348
349 if (use_sgl)
350 alloc_size = sizeof(__le64 *) * nvme_pci_npages_sgl(nseg);
351 else
352 alloc_size = sizeof(__le64 *) * nvme_npages(size, dev);
353
354 return alloc_size + sizeof(struct scatterlist) * nseg;
f4800d6d 355}
ac3dd5bd 356
a7a7cbe3 357static unsigned int nvme_pci_cmd_size(struct nvme_dev *dev, bool use_sgl)
f4800d6d 358{
a7a7cbe3
CK		 359 unsigned int alloc_size = nvme_pci_iod_alloc_size(dev,
360 NVME_INT_BYTES(dev), NVME_INT_PAGES,
361 use_sgl);
362
363 return sizeof(struct nvme_iod) + alloc_size;
ac3dd5bd
JA		 364}
365
a4aea562
MB		 366static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
367 unsigned int hctx_idx)
e85248e5 368{
a4aea562 369 struct nvme_dev *dev = data;
147b27e4 370 struct nvme_queue *nvmeq = &dev->queues[0];
a4aea562 371
42483228
KB		 372 WARN_ON(hctx_idx != 0);
373 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
374 WARN_ON(nvmeq->tags);
375
a4aea562 376 hctx->driver_data = nvmeq;
42483228 377 nvmeq->tags = &dev->admin_tagset.tags[0];
a4aea562 378 return 0;
e85248e5
MW		 379}
380
4af0e21c
KB		 381static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
382{
383 struct nvme_queue *nvmeq = hctx->driver_data;
384
385 nvmeq->tags = NULL;
386}
387
a4aea562
MB		 388static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
389 unsigned int hctx_idx)
b60503ba 390{
a4aea562 391 struct nvme_dev *dev = data;
147b27e4 392 struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
a4aea562 393
42483228
KB		 394 if (!nvmeq->tags)
395 nvmeq->tags = &dev->tagset.tags[hctx_idx];
b60503ba 396
42483228 397 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
a4aea562
MB		 398 hctx->driver_data = nvmeq;
399 return 0;
b60503ba
MW		 400}
401
d6296d39
CH		 402static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req,
403 unsigned int hctx_idx, unsigned int numa_node)
b60503ba 404{
d6296d39 405 struct nvme_dev *dev = set->driver_data;
f4800d6d 406 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
0350815a 407 int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0;
147b27e4 408 struct nvme_queue *nvmeq = &dev->queues[queue_idx];
a4aea562
MB		 409
410 BUG_ON(!nvmeq);
f4800d6d 411 iod->nvmeq = nvmeq;
a4aea562
MB		 412 return 0;
413}
414
dca51e78
CH		 415static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
416{
417 struct nvme_dev *dev = set->driver_data;
418
22b55601
KB		 419 return blk_mq_pci_map_queues(set, to_pci_dev(dev->dev),
420 dev->num_vecs > 1 ? 1 /* admin queue */ : 0);
dca51e78
CH		 421}
422
b60503ba 423/**
90ea5ca4 424 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
b60503ba
MW		 425 * @nvmeq: The queue to use
426 * @cmd: The command to send
b60503ba 427 */
90ea5ca4 428static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
b60503ba 429{
90ea5ca4 430 spin_lock(&nvmeq->sq_lock);
8ffaadf7 431 if (nvmeq->sq_cmds_io)
90ea5ca4
CH		 432 memcpy_toio(&nvmeq->sq_cmds_io[nvmeq->sq_tail], cmd,
433 sizeof(*cmd));
8ffaadf7 434 else
90ea5ca4 435 memcpy(&nvmeq->sq_cmds[nvmeq->sq_tail], cmd, sizeof(*cmd));
8ffaadf7 436
90ea5ca4
CH		 437 if (++nvmeq->sq_tail == nvmeq->q_depth)
438 nvmeq->sq_tail = 0;
439 if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail,
440 nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei))
441 writel(nvmeq->sq_tail, nvmeq->q_db);
442 spin_unlock(&nvmeq->sq_lock);
b60503ba
MW		 443}
444
a7a7cbe3 445static void **nvme_pci_iod_list(struct request *req)
b60503ba 446{
f4800d6d 447 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3 448 return (void **)(iod->sg + blk_rq_nr_phys_segments(req));
b60503ba
MW		 449}
450
955b1b5a
MI		 451static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req)
452{
453 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
20469a37 454 int nseg = blk_rq_nr_phys_segments(req);
955b1b5a
MI		 455 unsigned int avg_seg_size;
456
20469a37
KB		 457 if (nseg == 0)
458 return false;
459
460 avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
955b1b5a
MI		 461
462 if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1))))
463 return false;
464 if (!iod->nvmeq->qid)
465 return false;
466 if (!sgl_threshold || avg_seg_size < sgl_threshold)
467 return false;
468 return true;
469}
470
fc17b653 471static blk_status_t nvme_init_iod(struct request *rq, struct nvme_dev *dev)
ac3dd5bd 472{
f4800d6d 473 struct nvme_iod *iod = blk_mq_rq_to_pdu(rq);
f9d03f96 474 int nseg = blk_rq_nr_phys_segments(rq);
b131c61d 475 unsigned int size = blk_rq_payload_bytes(rq);
ac3dd5bd 476
955b1b5a
MI		 477 iod->use_sgl = nvme_pci_use_sgls(dev, rq);
478
f4800d6d 479 if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) {
a7a7cbe3
CK		 480 size_t alloc_size = nvme_pci_iod_alloc_size(dev, size, nseg,
481 iod->use_sgl);
482
483 iod->sg = kmalloc(alloc_size, GFP_ATOMIC);
f4800d6d 484 if (!iod->sg)
fc17b653 485 return BLK_STS_RESOURCE;
f4800d6d
CH		 486 } else {
487 iod->sg = iod->inline_sg;
ac3dd5bd
JA		 488 }
489
f4800d6d
CH		 490 iod->aborted = 0;
491 iod->npages = -1;
492 iod->nents = 0;
493 iod->length = size;
f80ec966 494
fc17b653 495 return BLK_STS_OK;
ac3dd5bd
JA		 496}
497
f4800d6d 498static void nvme_free_iod(struct nvme_dev *dev, struct request *req)
b60503ba 499{
f4800d6d 500 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3
CK		 501 const int last_prp = dev->ctrl.page_size / sizeof(__le64) - 1;
502 dma_addr_t dma_addr = iod->first_dma, next_dma_addr;
503
eca18b23 504 int i;
eca18b23
MW		 505
506 if (iod->npages == 0)
a7a7cbe3
CK		 507 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0],
508 dma_addr);
509
eca18b23 510 for (i = 0; i < iod->npages; i++) {
a7a7cbe3
CK		 511 void *addr = nvme_pci_iod_list(req)[i];
512
513 if (iod->use_sgl) {
514 struct nvme_sgl_desc *sg_list = addr;
515
516 next_dma_addr =
517 le64_to_cpu((sg_list[SGES_PER_PAGE - 1]).addr);
518 } else {
519 __le64 *prp_list = addr;
520
521 next_dma_addr = le64_to_cpu(prp_list[last_prp]);
522 }
523
524 dma_pool_free(dev->prp_page_pool, addr, dma_addr);
525 dma_addr = next_dma_addr;
eca18b23 526 }
ac3dd5bd 527
f4800d6d
CH		 528 if (iod->sg != iod->inline_sg)
529 kfree(iod->sg);
b4ff9c8d
KB		 530}
531
52b68d7e 532#ifdef CONFIG_BLK_DEV_INTEGRITY
e1e5e564
KB		 533static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
534{
535 if (be32_to_cpu(pi->ref_tag) == v)
536 pi->ref_tag = cpu_to_be32(p);
537}
538
539static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
540{
541 if (be32_to_cpu(pi->ref_tag) == p)
542 pi->ref_tag = cpu_to_be32(v);
543}
544
545/**
546 * nvme_dif_remap - remaps ref tags to bip seed and physical lba
547 *
548 * The virtual start sector is the one that was originally submitted by the
549 * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical
550 * start sector may be different. Remap protection information to match the
551 * physical LBA on writes, and back to the original seed on reads.
552 *
553 * Type 0 and 3 do not have a ref tag, so no remapping required.
554 */
555static void nvme_dif_remap(struct request *req,
556 void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
557{
558 struct nvme_ns *ns = req->rq_disk->private_data;
559 struct bio_integrity_payload *bip;
560 struct t10_pi_tuple *pi;
561 void *p, *pmap;
562 u32 i, nlb, ts, phys, virt;
563
564 if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3)
565 return;
566
567 bip = bio_integrity(req->bio);
568 if (!bip)
569 return;
570
571 pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset;
e1e5e564
KB		 572
573 p = pmap;
574 virt = bip_get_seed(bip);
575 phys = nvme_block_nr(ns, blk_rq_pos(req));
576 nlb = (blk_rq_bytes(req) >> ns->lba_shift);
ac6fc48c 577 ts = ns->disk->queue->integrity.tuple_size;
e1e5e564
KB		 578
579 for (i = 0; i < nlb; i++, virt++, phys++) {
580 pi = (struct t10_pi_tuple *)p;
581 dif_swap(phys, virt, pi);
582 p += ts;
583 }
584 kunmap_atomic(pmap);
585}
52b68d7e
KB		 586#else /* CONFIG_BLK_DEV_INTEGRITY */
587static void nvme_dif_remap(struct request *req,
588 void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
589{
590}
591static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
592{
593}
594static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
595{
596}
52b68d7e
KB		 597#endif
598
d0877473
KB		 599static void nvme_print_sgl(struct scatterlist *sgl, int nents)
600{
601 int i;
602 struct scatterlist *sg;
603
604 for_each_sg(sgl, sg, nents, i) {
605 dma_addr_t phys = sg_phys(sg);
606 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
607 "dma_address:%pad dma_length:%d\n",
608 i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
609 sg_dma_len(sg));
610 }
611}
612
a7a7cbe3
CK		 613static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
614 struct request *req, struct nvme_rw_command *cmnd)
ff22b54f 615{
f4800d6d 616 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
99802a7a 617 struct dma_pool *pool;
b131c61d 618 int length = blk_rq_payload_bytes(req);
eca18b23 619 struct scatterlist *sg = iod->sg;
ff22b54f
MW		 620 int dma_len = sg_dma_len(sg);
621 u64 dma_addr = sg_dma_address(sg);
5fd4ce1b 622 u32 page_size = dev->ctrl.page_size;
f137e0f1 623 int offset = dma_addr & (page_size - 1);
e025344c 624 __le64 *prp_list;
a7a7cbe3 625 void **list = nvme_pci_iod_list(req);
e025344c 626 dma_addr_t prp_dma;
eca18b23 627 int nprps, i;
ff22b54f 628
1d090624 629 length -= (page_size - offset);
5228b328
JS		 630 if (length <= 0) {
631 iod->first_dma = 0;
a7a7cbe3 632 goto done;
5228b328 633 }
ff22b54f 634
1d090624 635 dma_len -= (page_size - offset);
ff22b54f 636 if (dma_len) {
1d090624 637 dma_addr += (page_size - offset);
ff22b54f
MW		 638 } else {
639 sg = sg_next(sg);
640 dma_addr = sg_dma_address(sg);
641 dma_len = sg_dma_len(sg);
642 }
643
1d090624 644 if (length <= page_size) {
edd10d33 645 iod->first_dma = dma_addr;
a7a7cbe3 646 goto done;
e025344c
SMM		 647 }
648
1d090624 649 nprps = DIV_ROUND_UP(length, page_size);
99802a7a
MW		 650 if (nprps <= (256 / 8)) {
651 pool = dev->prp_small_pool;
eca18b23 652 iod->npages = 0;
99802a7a
MW		 653 } else {
654 pool = dev->prp_page_pool;
eca18b23 655 iod->npages = 1;
99802a7a
MW		 656 }
657
69d2b571 658 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
b77954cb 659 if (!prp_list) {
edd10d33 660 iod->first_dma = dma_addr;
eca18b23 661 iod->npages = -1;
86eea289 662 return BLK_STS_RESOURCE;
b77954cb 663 }
eca18b23
MW		 664 list[0] = prp_list;
665 iod->first_dma = prp_dma;
e025344c
SMM		 666 i = 0;
667 for (;;) {
1d090624 668 if (i == page_size >> 3) {
e025344c 669 __le64 *old_prp_list = prp_list;
69d2b571 670 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
eca18b23 671 if (!prp_list)
86eea289 672 return BLK_STS_RESOURCE;
eca18b23 673 list[iod->npages++] = prp_list;
7523d834
MW		 674 prp_list[0] = old_prp_list[i - 1];
675 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
676 i = 1;
e025344c
SMM		 677 }
678 prp_list[i++] = cpu_to_le64(dma_addr);
1d090624
KB		 679 dma_len -= page_size;
680 dma_addr += page_size;
681 length -= page_size;
e025344c
SMM		 682 if (length <= 0)
683 break;
684 if (dma_len > 0)
685 continue;
86eea289
KB		 686 if (unlikely(dma_len < 0))
687 goto bad_sgl;
e025344c
SMM		 688 sg = sg_next(sg);
689 dma_addr = sg_dma_address(sg);
690 dma_len = sg_dma_len(sg);
ff22b54f
MW		 691 }
692
a7a7cbe3
CK		 693done:
694 cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
695 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
696
86eea289
KB		 697 return BLK_STS_OK;
698
699 bad_sgl:
d0877473
KB		 700 WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents),
701 "Invalid SGL for payload:%d nents:%d\n",
702 blk_rq_payload_bytes(req), iod->nents);
86eea289 703 return BLK_STS_IOERR;
ff22b54f
MW		 704}
705
a7a7cbe3
CK		 706static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
707 struct scatterlist *sg)
708{
709 sge->addr = cpu_to_le64(sg_dma_address(sg));
710 sge->length = cpu_to_le32(sg_dma_len(sg));
711 sge->type = NVME_SGL_FMT_DATA_DESC << 4;
712}
713
714static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
715 dma_addr_t dma_addr, int entries)
716{
717 sge->addr = cpu_to_le64(dma_addr);
718 if (entries < SGES_PER_PAGE) {
719 sge->length = cpu_to_le32(entries * sizeof(*sge));
720 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
721 } else {
722 sge->length = cpu_to_le32(PAGE_SIZE);
723 sge->type = NVME_SGL_FMT_SEG_DESC << 4;
724 }
725}
726
727static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
b0f2853b 728 struct request *req, struct nvme_rw_command *cmd, int entries)
a7a7cbe3
CK		 729{
730 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3
CK		 731 struct dma_pool *pool;
732 struct nvme_sgl_desc *sg_list;
733 struct scatterlist *sg = iod->sg;
a7a7cbe3 734 dma_addr_t sgl_dma;
b0f2853b 735 int i = 0;
a7a7cbe3 736
a7a7cbe3
CK		 737 /* setting the transfer type as SGL */
738 cmd->flags = NVME_CMD_SGL_METABUF;
739
b0f2853b 740 if (entries == 1) {
a7a7cbe3
CK		 741 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
742 return BLK_STS_OK;
743 }
744
745 if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
746 pool = dev->prp_small_pool;
747 iod->npages = 0;
748 } else {
749 pool = dev->prp_page_pool;
750 iod->npages = 1;
751 }
752
753 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
754 if (!sg_list) {
755 iod->npages = -1;
756 return BLK_STS_RESOURCE;
757 }
758
759 nvme_pci_iod_list(req)[0] = sg_list;
760 iod->first_dma = sgl_dma;
761
762 nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
763
764 do {
765 if (i == SGES_PER_PAGE) {
766 struct nvme_sgl_desc *old_sg_desc = sg_list;
767 struct nvme_sgl_desc *link = &old_sg_desc[i - 1];
768
769 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
770 if (!sg_list)
771 return BLK_STS_RESOURCE;
772
773 i = 0;
774 nvme_pci_iod_list(req)[iod->npages++] = sg_list;
775 sg_list[i++] = *link;
776 nvme_pci_sgl_set_seg(link, sgl_dma, entries);
777 }
778
779 nvme_pci_sgl_set_data(&sg_list[i++], sg);
a7a7cbe3 780 sg = sg_next(sg);
b0f2853b 781 } while (--entries > 0);
a7a7cbe3 782
a7a7cbe3
CK		 783 return BLK_STS_OK;
784}
785
fc17b653 786static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
b131c61d 787 struct nvme_command *cmnd)
d29ec824 788{
f4800d6d 789 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
ba1ca37e
CH		 790 struct request_queue *q = req->q;
791 enum dma_data_direction dma_dir = rq_data_dir(req) ?
792 DMA_TO_DEVICE : DMA_FROM_DEVICE;
fc17b653 793 blk_status_t ret = BLK_STS_IOERR;
b0f2853b 794 int nr_mapped;
d29ec824 795
f9d03f96 796 sg_init_table(iod->sg, blk_rq_nr_phys_segments(req));
ba1ca37e
CH		 797 iod->nents = blk_rq_map_sg(q, req, iod->sg);
798 if (!iod->nents)
799 goto out;
d29ec824 800
fc17b653 801 ret = BLK_STS_RESOURCE;
b0f2853b
CH		 802 nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, dma_dir,
803 DMA_ATTR_NO_WARN);
804 if (!nr_mapped)
ba1ca37e 805 goto out;
d29ec824 806
955b1b5a 807 if (iod->use_sgl)
b0f2853b 808 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped);
a7a7cbe3
CK		 809 else
810 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
811
86eea289 812 if (ret != BLK_STS_OK)
ba1ca37e 813 goto out_unmap;
0e5e4f0e 814
fc17b653 815 ret = BLK_STS_IOERR;
ba1ca37e
CH		 816 if (blk_integrity_rq(req)) {
817 if (blk_rq_count_integrity_sg(q, req->bio) != 1)
818 goto out_unmap;
0e5e4f0e 819
bf684057
CH		 820 sg_init_table(&iod->meta_sg, 1);
821 if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1)
ba1ca37e 822 goto out_unmap;
0e5e4f0e 823
b5d8af5b 824 if (req_op(req) == REQ_OP_WRITE)
ba1ca37e 825 nvme_dif_remap(req, nvme_dif_prep);
0e5e4f0e 826
bf684057 827 if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir))
ba1ca37e 828 goto out_unmap;
d29ec824 829 }
00df5cb4 830
ba1ca37e 831 if (blk_integrity_rq(req))
bf684057 832 cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg));
fc17b653 833 return BLK_STS_OK;
00df5cb4 834
ba1ca37e
CH		 835out_unmap:
836 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
837out:
838 return ret;
00df5cb4
MW		 839}
840
f4800d6d 841static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
b60503ba 842{
f4800d6d 843 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
d4f6c3ab
CH		 844 enum dma_data_direction dma_dir = rq_data_dir(req) ?
845 DMA_TO_DEVICE : DMA_FROM_DEVICE;
846
847 if (iod->nents) {
848 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
849 if (blk_integrity_rq(req)) {
b5d8af5b 850 if (req_op(req) == REQ_OP_READ)
d4f6c3ab 851 nvme_dif_remap(req, nvme_dif_complete);
bf684057 852 dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir);
e1e5e564 853 }
e19b127f 854 }
e1e5e564 855
f9d03f96 856 nvme_cleanup_cmd(req);
f4800d6d 857 nvme_free_iod(dev, req);
d4f6c3ab 858}
b60503ba 859
d29ec824
CH		 860/*
861 * NOTE: ns is NULL when called on the admin queue.
862 */
fc17b653 863static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
a4aea562 864 const struct blk_mq_queue_data *bd)
edd10d33 865{
a4aea562
MB		 866 struct nvme_ns *ns = hctx->queue->queuedata;
867 struct nvme_queue *nvmeq = hctx->driver_data;
d29ec824 868 struct nvme_dev *dev = nvmeq->dev;
a4aea562 869 struct request *req = bd->rq;
ba1ca37e 870 struct nvme_command cmnd;
ebe6d874 871 blk_status_t ret;
e1e5e564 872
d1f06f4a
JA		 873 /*
874 * We should not need to do this, but we're still using this to
875 * ensure we can drain requests on a dying queue.
876 */
877 if (unlikely(nvmeq->cq_vector < 0))
878 return BLK_STS_IOERR;
879
f9d03f96 880 ret = nvme_setup_cmd(ns, req, &cmnd);
fc17b653 881 if (ret)
f4800d6d 882 return ret;
a4aea562 883
b131c61d 884 ret = nvme_init_iod(req, dev);
fc17b653 885 if (ret)
f9d03f96 886 goto out_free_cmd;
a4aea562 887
fc17b653 888 if (blk_rq_nr_phys_segments(req)) {
b131c61d 889 ret = nvme_map_data(dev, req, &cmnd);
fc17b653
CH		 890 if (ret)
891 goto out_cleanup_iod;
892 }
a4aea562 893
aae239e1 894 blk_mq_start_request(req);
90ea5ca4 895 nvme_submit_cmd(nvmeq, &cmnd);
fc17b653 896 return BLK_STS_OK;
f9d03f96 897out_cleanup_iod:
f4800d6d 898 nvme_free_iod(dev, req);
f9d03f96
CH		 899out_free_cmd:
900 nvme_cleanup_cmd(req);
ba1ca37e 901 return ret;
b60503ba 902}
e1e5e564 903
77f02a7a 904static void nvme_pci_complete_rq(struct request *req)
eee417b0 905{
f4800d6d 906 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a4aea562 907
77f02a7a
CH		 908 nvme_unmap_data(iod->nvmeq->dev, req);
909 nvme_complete_rq(req);
b60503ba
MW		 910}
911
d783e0bd 912/* We read the CQE phase first to check if the rest of the entry is valid */
750dde44 913static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq)
d783e0bd 914{
750dde44
CH		 915 return (le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) ==
916 nvmeq->cq_phase;
d783e0bd
MR		 917}
918
eb281c82 919static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
b60503ba 920{
eb281c82 921 u16 head = nvmeq->cq_head;
adf68f21 922
397c699f
KB		 923 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
924 nvmeq->dbbuf_cq_ei))
925 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
eb281c82 926}
aae239e1 927
5cb525c8 928static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx)
83a12fb7 929{
5cb525c8 930 volatile struct nvme_completion *cqe = &nvmeq->cqes[idx];
83a12fb7 931 struct request *req;
adf68f21 932
83a12fb7
SG		 933 if (unlikely(cqe->command_id >= nvmeq->q_depth)) {
934 dev_warn(nvmeq->dev->ctrl.device,
935 "invalid id %d completed on queue %d\n",
936 cqe->command_id, le16_to_cpu(cqe->sq_id));
937 return;
b60503ba
MW		 938 }
939
83a12fb7
SG		 940 /*
941 * AEN requests are special as they don't time out and can
942 * survive any kind of queue freeze and often don't respond to
943 * aborts. We don't even bother to allocate a struct request
944 * for them but rather special case them here.
945 */
946 if (unlikely(nvmeq->qid == 0 &&
38dabe21 947 cqe->command_id >= NVME_AQ_BLK_MQ_DEPTH)) {
83a12fb7
SG		 948 nvme_complete_async_event(&nvmeq->dev->ctrl,
949 cqe->status, &cqe->result);
a0fa9647 950 return;
83a12fb7 951 }
b60503ba 952
83a12fb7
SG		 953 req = blk_mq_tag_to_rq(*nvmeq->tags, cqe->command_id);
954 nvme_end_request(req, cqe->status, cqe->result);
955}
b60503ba 956
5cb525c8 957static void nvme_complete_cqes(struct nvme_queue *nvmeq, u16 start, u16 end)
b60503ba 958{
5cb525c8
JA		 959 while (start != end) {
960 nvme_handle_cqe(nvmeq, start);
961 if (++start == nvmeq->q_depth)
962 start = 0;
963 }
964}
adf68f21 965
5cb525c8
JA		 966static inline void nvme_update_cq_head(struct nvme_queue *nvmeq)
967{
968 if (++nvmeq->cq_head == nvmeq->q_depth) {
969 nvmeq->cq_head = 0;
970 nvmeq->cq_phase = !nvmeq->cq_phase;
b60503ba 971 }
a0fa9647
JA		 972}
973
5cb525c8
JA		 974static inline bool nvme_process_cq(struct nvme_queue *nvmeq, u16 *start,
975 u16 *end, int tag)
a0fa9647 976{
5cb525c8 977 bool found = false;
b60503ba 978
5cb525c8
JA		 979 *start = nvmeq->cq_head;
980 while (!found && nvme_cqe_pending(nvmeq)) {
981 if (nvmeq->cqes[nvmeq->cq_head].command_id == tag)
982 found = true;
983 nvme_update_cq_head(nvmeq);
920d13a8 984 }
5cb525c8 985 *end = nvmeq->cq_head;
eb281c82 986
5cb525c8 987 if (*start != *end)
920d13a8 988 nvme_ring_cq_doorbell(nvmeq);
5cb525c8 989 return found;
b60503ba
MW		 990}
991
992static irqreturn_t nvme_irq(int irq, void *data)
58ffacb5 993{
58ffacb5 994 struct nvme_queue *nvmeq = data;
68fa9dbe 995 irqreturn_t ret = IRQ_NONE;
5cb525c8
JA		 996 u16 start, end;
997
1ab0cd69 998 spin_lock(&nvmeq->cq_lock);
68fa9dbe
JA		 999 if (nvmeq->cq_head != nvmeq->last_cq_head)
1000 ret = IRQ_HANDLED;
5cb525c8 1001 nvme_process_cq(nvmeq, &start, &end, -1);
68fa9dbe 1002 nvmeq->last_cq_head = nvmeq->cq_head;
1ab0cd69 1003 spin_unlock(&nvmeq->cq_lock);
5cb525c8 1004
68fa9dbe
JA		 1005 if (start != end) {
1006 nvme_complete_cqes(nvmeq, start, end);
1007 return IRQ_HANDLED;
1008 }
1009
1010 return ret;
58ffacb5
MW		 1011}
1012
1013static irqreturn_t nvme_irq_check(int irq, void *data)
1014{
1015 struct nvme_queue *nvmeq = data;
750dde44 1016 if (nvme_cqe_pending(nvmeq))
d783e0bd
MR		 1017 return IRQ_WAKE_THREAD;
1018 return IRQ_NONE;
58ffacb5
MW		 1019}
1020
7776db1c 1021static int __nvme_poll(struct nvme_queue *nvmeq, unsigned int tag)
a0fa9647 1022{
5cb525c8
JA		 1023 u16 start, end;
1024 bool found;
a0fa9647 1025
750dde44 1026 if (!nvme_cqe_pending(nvmeq))
442e19b7 1027 return 0;
a0fa9647 1028
1ab0cd69 1029 spin_lock_irq(&nvmeq->cq_lock);
5cb525c8 1030 found = nvme_process_cq(nvmeq, &start, &end, tag);
1ab0cd69 1031 spin_unlock_irq(&nvmeq->cq_lock);
442e19b7 1032
5cb525c8 1033 nvme_complete_cqes(nvmeq, start, end);
442e19b7 1034 return found;
a0fa9647
JA		 1035}
1036
7776db1c
KB		 1037static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag)
1038{
1039 struct nvme_queue *nvmeq = hctx->driver_data;
1040
1041 return __nvme_poll(nvmeq, tag);
1042}
1043
ad22c355 1044static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
b60503ba 1045{
f866fc42 1046 struct nvme_dev *dev = to_nvme_dev(ctrl);
147b27e4 1047 struct nvme_queue *nvmeq = &dev->queues[0];
a4aea562 1048 struct nvme_command c;
b60503ba 1049
a4aea562
MB		 1050 memset(&c, 0, sizeof(c));
1051 c.common.opcode = nvme_admin_async_event;
ad22c355 1052 c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
90ea5ca4 1053 nvme_submit_cmd(nvmeq, &c);
f705f837
CH		 1054}
1055
b60503ba 1056static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
f705f837 1057{
b60503ba
MW		 1058 struct nvme_command c;
1059
1060 memset(&c, 0, sizeof(c));
1061 c.delete_queue.opcode = opcode;
1062 c.delete_queue.qid = cpu_to_le16(id);
1063
1c63dc66 1064 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1065}
1066
b60503ba 1067static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
a8e3e0bb 1068 struct nvme_queue *nvmeq, s16 vector)
b60503ba 1069{
b60503ba
MW		 1070 struct nvme_command c;
1071 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
1072
d29ec824 1073 /*
16772ae6 1074 * Note: we (ab)use the fact that the prp fields survive if no data
d29ec824
CH		 1075 * is attached to the request.
1076 */
b60503ba
MW		 1077 memset(&c, 0, sizeof(c));
1078 c.create_cq.opcode = nvme_admin_create_cq;
1079 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1080 c.create_cq.cqid = cpu_to_le16(qid);
1081 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1082 c.create_cq.cq_flags = cpu_to_le16(flags);
a8e3e0bb 1083 c.create_cq.irq_vector = cpu_to_le16(vector);
b60503ba 1084
1c63dc66 1085 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1086}
1087
1088static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1089 struct nvme_queue *nvmeq)
1090{
9abd68ef 1091 struct nvme_ctrl *ctrl = &dev->ctrl;
b60503ba 1092 struct nvme_command c;
81c1cd98 1093 int flags = NVME_QUEUE_PHYS_CONTIG;
b60503ba 1094
9abd68ef
JA		 1095 /*
1096 * Some drives have a bug that auto-enables WRRU if MEDIUM isn't
1097 * set. Since URGENT priority is zeroes, it makes all queues
1098 * URGENT.
1099 */
1100 if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ)
1101 flags |= NVME_SQ_PRIO_MEDIUM;
1102
d29ec824 1103 /*
16772ae6 1104 * Note: we (ab)use the fact that the prp fields survive if no data
d29ec824
CH		 1105 * is attached to the request.
1106 */
b60503ba
MW		 1107 memset(&c, 0, sizeof(c));
1108 c.create_sq.opcode = nvme_admin_create_sq;
1109 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1110 c.create_sq.sqid = cpu_to_le16(qid);
1111 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1112 c.create_sq.sq_flags = cpu_to_le16(flags);
1113 c.create_sq.cqid = cpu_to_le16(qid);
1114
1c63dc66 1115 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1116}
1117
1118static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1119{
1120 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1121}
1122
1123static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1124{
1125 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1126}
1127
2a842aca 1128static void abort_endio(struct request *req, blk_status_t error)
bc5fc7e4 1129{
f4800d6d
CH		 1130 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1131 struct nvme_queue *nvmeq = iod->nvmeq;
e44ac588 1132
27fa9bc5
CH		 1133 dev_warn(nvmeq->dev->ctrl.device,
1134 "Abort status: 0x%x", nvme_req(req)->status);
e7a2a87d 1135 atomic_inc(&nvmeq->dev->ctrl.abort_limit);
e7a2a87d 1136 blk_mq_free_request(req);
bc5fc7e4
MW		 1137}
1138
b2a0eb1a
KB		 1139static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1140{
1141
1142 /* If true, indicates loss of adapter communication, possibly by a
1143 * NVMe Subsystem reset.
1144 */
1145 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1146
ad70062c
JW		 1147 /* If there is a reset/reinit ongoing, we shouldn't reset again. */
1148 switch (dev->ctrl.state) {
1149 case NVME_CTRL_RESETTING:
ad6a0a52 1150 case NVME_CTRL_CONNECTING:
b2a0eb1a 1151 return false;
ad70062c
JW		 1152 default:
1153 break;
1154 }
b2a0eb1a
KB		 1155
1156 /* We shouldn't reset unless the controller is on fatal error state
1157 * _or_ if we lost the communication with it.
1158 */
1159 if (!(csts & NVME_CSTS_CFS) && !nssro)
1160 return false;
1161
b2a0eb1a
KB		 1162 return true;
1163}
1164
1165static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1166{
1167 /* Read a config register to help see what died. */
1168 u16 pci_status;
1169 int result;
1170
1171 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1172 &pci_status);
1173 if (result == PCIBIOS_SUCCESSFUL)
1174 dev_warn(dev->ctrl.device,
1175 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1176 csts, pci_status);
1177 else
1178 dev_warn(dev->ctrl.device,
1179 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1180 csts, result);
1181}
1182
31c7c7d2 1183static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
c30341dc 1184{
f4800d6d
CH		 1185 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1186 struct nvme_queue *nvmeq = iod->nvmeq;
c30341dc 1187 struct nvme_dev *dev = nvmeq->dev;
a4aea562 1188 struct request *abort_req;
a4aea562 1189 struct nvme_command cmd;
b2a0eb1a
KB		 1190 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1191
651438bb
WX		 1192 /* If PCI error recovery process is happening, we cannot reset or
1193 * the recovery mechanism will surely fail.
1194 */
1195 mb();
1196 if (pci_channel_offline(to_pci_dev(dev->dev)))
1197 return BLK_EH_RESET_TIMER;
1198
b2a0eb1a
KB		 1199 /*
1200 * Reset immediately if the controller is failed
1201 */
1202 if (nvme_should_reset(dev, csts)) {
1203 nvme_warn_reset(dev, csts);
1204 nvme_dev_disable(dev, false);
d86c4d8e 1205 nvme_reset_ctrl(&dev->ctrl);
db8c48e4 1206 return BLK_EH_DONE;
b2a0eb1a 1207 }
c30341dc 1208
7776db1c
KB		 1209 /*
1210 * Did we miss an interrupt?
1211 */
1212 if (__nvme_poll(nvmeq, req->tag)) {
1213 dev_warn(dev->ctrl.device,
1214 "I/O %d QID %d timeout, completion polled\n",
1215 req->tag, nvmeq->qid);
db8c48e4 1216 return BLK_EH_DONE;
7776db1c
KB		 1217 }
1218
31c7c7d2 1219 /*
fd634f41
CH		 1220 * Shutdown immediately if controller times out while starting. The
1221 * reset work will see the pci device disabled when it gets the forced
1222 * cancellation error. All outstanding requests are completed on
db8c48e4 1223 * shutdown, so we return BLK_EH_DONE.
fd634f41 1224 */
4244140d
KB		 1225 switch (dev->ctrl.state) {
1226 case NVME_CTRL_CONNECTING:
1227 case NVME_CTRL_RESETTING:
b9cac43c 1228 dev_warn_ratelimited(dev->ctrl.device,
fd634f41
CH		 1229 "I/O %d QID %d timeout, disable controller\n",
1230 req->tag, nvmeq->qid);
a5cdb68c 1231 nvme_dev_disable(dev, false);
27fa9bc5 1232 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
db8c48e4 1233 return BLK_EH_DONE;
4244140d
KB		 1234 default:
1235 break;
c30341dc
KB		 1236 }
1237
fd634f41
CH		 1238 /*
1239 * Shutdown the controller immediately and schedule a reset if the
1240 * command was already aborted once before and still hasn't been
1241 * returned to the driver, or if this is the admin queue.
31c7c7d2 1242 */
f4800d6d 1243 if (!nvmeq->qid || iod->aborted) {
1b3c47c1 1244 dev_warn(dev->ctrl.device,
e1569a16
KB		 1245 "I/O %d QID %d timeout, reset controller\n",
1246 req->tag, nvmeq->qid);
a5cdb68c 1247 nvme_dev_disable(dev, false);
d86c4d8e 1248 nvme_reset_ctrl(&dev->ctrl);
c30341dc 1249
27fa9bc5 1250 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
db8c48e4 1251 return BLK_EH_DONE;
c30341dc 1252 }
c30341dc 1253
e7a2a87d 1254 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
6bf25d16 1255 atomic_inc(&dev->ctrl.abort_limit);
31c7c7d2 1256 return BLK_EH_RESET_TIMER;
6bf25d16 1257 }
7bf7d778 1258 iod->aborted = 1;
a4aea562 1259
c30341dc
KB		 1260 memset(&cmd, 0, sizeof(cmd));
1261 cmd.abort.opcode = nvme_admin_abort_cmd;
a4aea562 1262 cmd.abort.cid = req->tag;
c30341dc 1263 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
c30341dc 1264
1b3c47c1
SG		 1265 dev_warn(nvmeq->dev->ctrl.device,
1266 "I/O %d QID %d timeout, aborting\n",
1267 req->tag, nvmeq->qid);
e7a2a87d
CH		 1268
1269 abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
eb71f435 1270 BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
e7a2a87d
CH		 1271 if (IS_ERR(abort_req)) {
1272 atomic_inc(&dev->ctrl.abort_limit);
1273 return BLK_EH_RESET_TIMER;
1274 }
1275
1276 abort_req->timeout = ADMIN_TIMEOUT;
1277 abort_req->end_io_data = NULL;
1278 blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio);
c30341dc 1279
31c7c7d2
CH		 1280 /*
1281 * The aborted req will be completed on receiving the abort req.
1282 * We enable the timer again. If hit twice, it'll cause a device reset,
1283 * as the device then is in a faulty state.
1284 */
1285 return BLK_EH_RESET_TIMER;
c30341dc
KB		 1286}
1287
a4aea562
MB		 1288static void nvme_free_queue(struct nvme_queue *nvmeq)
1289{
9e866774
MW		 1290 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1291 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
8ffaadf7
JD		 1292 if (nvmeq->sq_cmds)
1293 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
9e866774 1294 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
9e866774
MW		 1295}
1296
a1a5ef99 1297static void nvme_free_queues(struct nvme_dev *dev, int lowest)
22404274
KB		 1298{
1299 int i;
1300
d858e5f0 1301 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
d858e5f0 1302 dev->ctrl.queue_count--;
147b27e4 1303 nvme_free_queue(&dev->queues[i]);
121c7ad4 1304 }
22404274
KB		 1305}
1306
4d115420
KB		 1307/**
1308 * nvme_suspend_queue - put queue into suspended state
1309 * @nvmeq - queue to suspend
4d115420
KB		 1310 */
1311static int nvme_suspend_queue(struct nvme_queue *nvmeq)
b60503ba 1312{
2b25d981 1313 int vector;
b60503ba 1314
1ab0cd69 1315 spin_lock_irq(&nvmeq->cq_lock);
2b25d981 1316 if (nvmeq->cq_vector == -1) {
1ab0cd69 1317 spin_unlock_irq(&nvmeq->cq_lock);
2b25d981
KB		 1318 return 1;
1319 }
0ff199cb 1320 vector = nvmeq->cq_vector;
42f61420 1321 nvmeq->dev->online_queues--;
2b25d981 1322 nvmeq->cq_vector = -1;
1ab0cd69 1323 spin_unlock_irq(&nvmeq->cq_lock);
a09115b2 1324
d1f06f4a
JA		 1325 /*
1326 * Ensure that nvme_queue_rq() sees it ->cq_vector == -1 without
1327 * having to grab the lock.
1328 */
1329 mb();
a09115b2 1330
1c63dc66 1331 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
c81545f9 1332 blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q);
6df3dbc8 1333
0ff199cb 1334 pci_free_irq(to_pci_dev(nvmeq->dev->dev), vector, nvmeq);
b60503ba 1335
4d115420
KB		 1336 return 0;
1337}
b60503ba 1338
a5cdb68c 1339static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
4d115420 1340{
147b27e4 1341 struct nvme_queue *nvmeq = &dev->queues[0];
5cb525c8 1342 u16 start, end;
4d115420 1343
a5cdb68c
KB		 1344 if (shutdown)
1345 nvme_shutdown_ctrl(&dev->ctrl);
1346 else
20d0dfe6 1347 nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap);
07836e65 1348
1ab0cd69 1349 spin_lock_irq(&nvmeq->cq_lock);
5cb525c8 1350 nvme_process_cq(nvmeq, &start, &end, -1);
1ab0cd69 1351 spin_unlock_irq(&nvmeq->cq_lock);
5cb525c8
JA		 1352
1353 nvme_complete_cqes(nvmeq, start, end);
b60503ba
MW		 1354}
1355
8ffaadf7
JD		 1356static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1357 int entry_size)
1358{
1359 int q_depth = dev->q_depth;
5fd4ce1b
CH		 1360 unsigned q_size_aligned = roundup(q_depth * entry_size,
1361 dev->ctrl.page_size);
8ffaadf7
JD		 1362
1363 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
c45f5c99 1364 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
5fd4ce1b 1365 mem_per_q = round_down(mem_per_q, dev->ctrl.page_size);
c45f5c99 1366 q_depth = div_u64(mem_per_q, entry_size);
8ffaadf7
JD		 1367
1368 /*
1369 * Ensure the reduced q_depth is above some threshold where it
1370 * would be better to map queues in system memory with the
1371 * original depth
1372 */
1373 if (q_depth < 64)
1374 return -ENOMEM;
1375 }
1376
1377 return q_depth;
1378}
1379
1380static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1381 int qid, int depth)
1382{
815c6704
KB		 1383 /* CMB SQEs will be mapped before creation */
1384 if (qid && dev->cmb && use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS))
1385 return 0;
8ffaadf7 1386
815c6704
KB		 1387 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
1388 &nvmeq->sq_dma_addr, GFP_KERNEL);
1389 if (!nvmeq->sq_cmds)
1390 return -ENOMEM;
8ffaadf7
JD		 1391 return 0;
1392}
1393
a6ff7262 1394static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
b60503ba 1395{
147b27e4 1396 struct nvme_queue *nvmeq = &dev->queues[qid];
b60503ba 1397
62314e40
KB		 1398 if (dev->ctrl.queue_count > qid)
1399 return 0;
b60503ba 1400
e75ec752 1401 nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth),
4d51abf9 1402 &nvmeq->cq_dma_addr, GFP_KERNEL);
b60503ba
MW		 1403 if (!nvmeq->cqes)
1404 goto free_nvmeq;
b60503ba 1405
8ffaadf7 1406 if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth))
b60503ba
MW		 1407 goto free_cqdma;
1408
e75ec752 1409 nvmeq->q_dmadev = dev->dev;
091b6092 1410 nvmeq->dev = dev;
1ab0cd69
JA		 1411 spin_lock_init(&nvmeq->sq_lock);
1412 spin_lock_init(&nvmeq->cq_lock);
b60503ba 1413 nvmeq->cq_head = 0;
82123460 1414 nvmeq->cq_phase = 1;
b80d5ccc 1415 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
b60503ba 1416 nvmeq->q_depth = depth;
c30341dc 1417 nvmeq->qid = qid;
758dd7fd 1418 nvmeq->cq_vector = -1;
d858e5f0 1419 dev->ctrl.queue_count++;
36a7e993 1420
147b27e4 1421 return 0;
b60503ba
MW		 1422
1423 free_cqdma:
e75ec752 1424 dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes,
b60503ba
MW		 1425 nvmeq->cq_dma_addr);
1426 free_nvmeq:
147b27e4 1427 return -ENOMEM;
b60503ba
MW		 1428}
1429
dca51e78 1430static int queue_request_irq(struct nvme_queue *nvmeq)
3001082c 1431{
0ff199cb
CH		 1432 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1433 int nr = nvmeq->dev->ctrl.instance;
1434
1435 if (use_threaded_interrupts) {
1436 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1437 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1438 } else {
1439 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1440 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1441 }
3001082c
MW		 1442}
1443
22404274 1444static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
b60503ba 1445{
22404274 1446 struct nvme_dev *dev = nvmeq->dev;
b60503ba 1447
1ab0cd69 1448 spin_lock_irq(&nvmeq->cq_lock);
22404274
KB		 1449 nvmeq->sq_tail = 0;
1450 nvmeq->cq_head = 0;
1451 nvmeq->cq_phase = 1;
b80d5ccc 1452 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
22404274 1453 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
f9f38e33 1454 nvme_dbbuf_init(dev, nvmeq, qid);
42f61420 1455 dev->online_queues++;
1ab0cd69 1456 spin_unlock_irq(&nvmeq->cq_lock);
22404274
KB		 1457}
1458
1459static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1460{
1461 struct nvme_dev *dev = nvmeq->dev;
1462 int result;
a8e3e0bb 1463 s16 vector;
3f85d50b 1464
815c6704
KB		 1465 if (dev->cmb && use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
1466 unsigned offset = (qid - 1) * roundup(SQ_SIZE(nvmeq->q_depth),
1467 dev->ctrl.page_size);
1468 nvmeq->sq_dma_addr = dev->cmb_bus_addr + offset;
1469 nvmeq->sq_cmds_io = dev->cmb + offset;
1470 }
1471
22b55601
KB		 1472 /*
1473 * A queue's vector matches the queue identifier unless the controller
1474 * has only one vector available.
1475 */
a8e3e0bb
JW		 1476 vector = dev->num_vecs == 1 ? 0 : qid;
1477 result = adapter_alloc_cq(dev, qid, nvmeq, vector);
ded45505
KB		 1478 if (result)
1479 return result;
b60503ba
MW		 1480
1481 result = adapter_alloc_sq(dev, qid, nvmeq);
1482 if (result < 0)
ded45505
KB		 1483 return result;
1484 else if (result)
b60503ba
MW		 1485 goto release_cq;
1486
a8e3e0bb
JW		 1487 /*
1488 * Set cq_vector after alloc cq/sq, otherwise nvme_suspend_queue will
1489 * invoke free_irq for it and cause a 'Trying to free already-free IRQ
1490 * xxx' warning if the create CQ/SQ command times out.
1491 */
1492 nvmeq->cq_vector = vector;
161b8be2 1493 nvme_init_queue(nvmeq, qid);
dca51e78 1494 result = queue_request_irq(nvmeq);
b60503ba
MW		 1495 if (result < 0)
1496 goto release_sq;
1497
22404274 1498 return result;
b60503ba 1499
a8e3e0bb
JW		 1500release_sq:
1501 nvmeq->cq_vector = -1;
f25a2dfc 1502 dev->online_queues--;
b60503ba 1503 adapter_delete_sq(dev, qid);
a8e3e0bb 1504release_cq:
b60503ba 1505 adapter_delete_cq(dev, qid);
22404274 1506 return result;
b60503ba
MW		 1507}
1508
f363b089 1509static const struct blk_mq_ops nvme_mq_admin_ops = {
d29ec824 1510 .queue_rq = nvme_queue_rq,
77f02a7a 1511 .complete = nvme_pci_complete_rq,
a4aea562 1512 .init_hctx = nvme_admin_init_hctx,
4af0e21c 1513 .exit_hctx = nvme_admin_exit_hctx,
0350815a 1514 .init_request = nvme_init_request,
a4aea562
MB		 1515 .timeout = nvme_timeout,
1516};
1517
f363b089 1518static const struct blk_mq_ops nvme_mq_ops = {
a4aea562 1519 .queue_rq = nvme_queue_rq,
77f02a7a 1520 .complete = nvme_pci_complete_rq,
a4aea562
MB		 1521 .init_hctx = nvme_init_hctx,
1522 .init_request = nvme_init_request,
dca51e78 1523 .map_queues = nvme_pci_map_queues,
a4aea562 1524 .timeout = nvme_timeout,
a0fa9647 1525 .poll = nvme_poll,
a4aea562
MB		 1526};
1527
ea191d2f
KB		 1528static void nvme_dev_remove_admin(struct nvme_dev *dev)
1529{
1c63dc66 1530 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
69d9a99c
KB		 1531 /*
1532 * If the controller was reset during removal, it's possible
1533 * user requests may be waiting on a stopped queue. Start the
1534 * queue to flush these to completion.
1535 */
c81545f9 1536 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1c63dc66 1537 blk_cleanup_queue(dev->ctrl.admin_q);
ea191d2f
KB		 1538 blk_mq_free_tag_set(&dev->admin_tagset);
1539 }
1540}
1541
a4aea562
MB		 1542static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1543{
1c63dc66 1544 if (!dev->ctrl.admin_q) {
a4aea562
MB		 1545 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1546 dev->admin_tagset.nr_hw_queues = 1;
e3e9d50c 1547
38dabe21 1548 dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH;
a4aea562 1549 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
e75ec752 1550 dev->admin_tagset.numa_node = dev_to_node(dev->dev);
a7a7cbe3 1551 dev->admin_tagset.cmd_size = nvme_pci_cmd_size(dev, false);
d3484991 1552 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED;
a4aea562
MB		 1553 dev->admin_tagset.driver_data = dev;
1554
1555 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1556 return -ENOMEM;
34b6c231 1557 dev->ctrl.admin_tagset = &dev->admin_tagset;
a4aea562 1558
1c63dc66
CH		 1559 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1560 if (IS_ERR(dev->ctrl.admin_q)) {
a4aea562
MB		 1561 blk_mq_free_tag_set(&dev->admin_tagset);
1562 return -ENOMEM;
1563 }
1c63dc66 1564 if (!blk_get_queue(dev->ctrl.admin_q)) {
ea191d2f 1565 nvme_dev_remove_admin(dev);
1c63dc66 1566 dev->ctrl.admin_q = NULL;
ea191d2f
KB		 1567 return -ENODEV;
1568 }
0fb59cbc 1569 } else
c81545f9 1570 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
a4aea562
MB		 1571
1572 return 0;
1573}
1574
97f6ef64
XY		 1575static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1576{
1577 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1578}
1579
1580static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1581{
1582 struct pci_dev *pdev = to_pci_dev(dev->dev);
1583
1584 if (size <= dev->bar_mapped_size)
1585 return 0;
1586 if (size > pci_resource_len(pdev, 0))
1587 return -ENOMEM;
1588 if (dev->bar)
1589 iounmap(dev->bar);
1590 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1591 if (!dev->bar) {
1592 dev->bar_mapped_size = 0;
1593 return -ENOMEM;
1594 }
1595 dev->bar_mapped_size = size;
1596 dev->dbs = dev->bar + NVME_REG_DBS;
1597
1598 return 0;
1599}
1600
01ad0990 1601static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
b60503ba 1602{
ba47e386 1603 int result;
b60503ba
MW		 1604 u32 aqa;
1605 struct nvme_queue *nvmeq;
1606
97f6ef64
XY		 1607 result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1608 if (result < 0)
1609 return result;
1610
8ef2074d 1611 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
20d0dfe6 1612 NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
dfbac8c7 1613
7a67cbea
CH		 1614 if (dev->subsystem &&
1615 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1616 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
dfbac8c7 1617
20d0dfe6 1618 result = nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap);
ba47e386
MW		 1619 if (result < 0)
1620 return result;
b60503ba 1621
a6ff7262 1622 result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
147b27e4
SG		 1623 if (result)
1624 return result;
b60503ba 1625
147b27e4 1626 nvmeq = &dev->queues[0];
b60503ba
MW		 1627 aqa = nvmeq->q_depth - 1;
1628 aqa |= aqa << 16;
1629
7a67cbea
CH		 1630 writel(aqa, dev->bar + NVME_REG_AQA);
1631 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1632 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
b60503ba 1633
20d0dfe6 1634 result = nvme_enable_ctrl(&dev->ctrl, dev->ctrl.cap);
025c557a 1635 if (result)
d4875622 1636 return result;
a4aea562 1637
2b25d981 1638 nvmeq->cq_vector = 0;
161b8be2 1639 nvme_init_queue(nvmeq, 0);
dca51e78 1640 result = queue_request_irq(nvmeq);
758dd7fd
JD		 1641 if (result) {
1642 nvmeq->cq_vector = -1;
d4875622 1643 return result;
758dd7fd 1644 }
025c557a 1645
b60503ba
MW		 1646 return result;
1647}
1648
749941f2 1649static int nvme_create_io_queues(struct nvme_dev *dev)
42f61420 1650{
949928c1 1651 unsigned i, max;
749941f2 1652 int ret = 0;
42f61420 1653
d858e5f0 1654 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
a6ff7262 1655 if (nvme_alloc_queue(dev, i, dev->q_depth)) {
749941f2 1656 ret = -ENOMEM;
42f61420 1657 break;
749941f2
CH		 1658 }
1659 }
42f61420 1660
d858e5f0 1661 max = min(dev->max_qid, dev->ctrl.queue_count - 1);
949928c1 1662 for (i = dev->online_queues; i <= max; i++) {
147b27e4 1663 ret = nvme_create_queue(&dev->queues[i], i);
d4875622 1664 if (ret)
42f61420 1665 break;
27e8166c 1666 }
749941f2
CH		 1667
1668 /*
1669 * Ignore failing Create SQ/CQ commands, we can continue with less
8adb8c14
MI		 1670 * than the desired amount of queues, and even a controller without
1671 * I/O queues can still be used to issue admin commands. This might
749941f2
CH		 1672 * be useful to upgrade a buggy firmware for example.
1673 */
1674 return ret >= 0 ? 0 : ret;
b60503ba
MW		 1675}
1676
202021c1
SB		 1677static ssize_t nvme_cmb_show(struct device *dev,
1678 struct device_attribute *attr,
1679 char *buf)
1680{
1681 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
1682
c965809c 1683 return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n",
202021c1
SB		 1684 ndev->cmbloc, ndev->cmbsz);
1685}
1686static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL);
1687
88de4598 1688static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
8ffaadf7 1689{
88de4598
CH		 1690 u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
1691
1692 return 1ULL << (12 + 4 * szu);
1693}
1694
1695static u32 nvme_cmb_size(struct nvme_dev *dev)
1696{
1697 return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
1698}
1699
f65efd6d 1700static void nvme_map_cmb(struct nvme_dev *dev)
8ffaadf7 1701{
88de4598 1702 u64 size, offset;
8ffaadf7
JD		 1703 resource_size_t bar_size;
1704 struct pci_dev *pdev = to_pci_dev(dev->dev);
8969f1f8 1705 int bar;
8ffaadf7 1706
7a67cbea 1707 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
f65efd6d
CH		 1708 if (!dev->cmbsz)
1709 return;
202021c1 1710 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
8ffaadf7 1711
202021c1 1712 if (!use_cmb_sqes)
f65efd6d 1713 return;
8ffaadf7 1714
88de4598
CH		 1715 size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
1716 offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
8969f1f8
CH		 1717 bar = NVME_CMB_BIR(dev->cmbloc);
1718 bar_size = pci_resource_len(pdev, bar);
8ffaadf7
JD		 1719
1720 if (offset > bar_size)
f65efd6d 1721 return;
8ffaadf7
JD		 1722
1723 /*
1724 * Controllers may support a CMB size larger than their BAR,
1725 * for example, due to being behind a bridge. Reduce the CMB to
1726 * the reported size of the BAR
1727 */
1728 if (size > bar_size - offset)
1729 size = bar_size - offset;
1730
f65efd6d
CH		 1731 dev->cmb = ioremap_wc(pci_resource_start(pdev, bar) + offset, size);
1732 if (!dev->cmb)
1733 return;
8969f1f8 1734 dev->cmb_bus_addr = pci_bus_address(pdev, bar) + offset;
8ffaadf7 1735 dev->cmb_size = size;
f65efd6d
CH		 1736
1737 if (sysfs_add_file_to_group(&dev->ctrl.device->kobj,
1738 &dev_attr_cmb.attr, NULL))
1739 dev_warn(dev->ctrl.device,
1740 "failed to add sysfs attribute for CMB\n");
8ffaadf7
JD		 1741}
1742
1743static inline void nvme_release_cmb(struct nvme_dev *dev)
1744{
1745 if (dev->cmb) {
1746 iounmap(dev->cmb);
1747 dev->cmb = NULL;
1c78f773
MG		 1748 sysfs_remove_file_from_group(&dev->ctrl.device->kobj,
1749 &dev_attr_cmb.attr, NULL);
1750 dev->cmbsz = 0;
8ffaadf7
JD		 1751 }
1752}
1753
87ad72a5
CH		 1754static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1755{
4033f35d 1756 u64 dma_addr = dev->host_mem_descs_dma;
87ad72a5 1757 struct nvme_command c;
87ad72a5
CH		 1758 int ret;
1759
87ad72a5
CH		 1760 memset(&c, 0, sizeof(c));
1761 c.features.opcode = nvme_admin_set_features;
1762 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1763 c.features.dword11 = cpu_to_le32(bits);
1764 c.features.dword12 = cpu_to_le32(dev->host_mem_size >>
1765 ilog2(dev->ctrl.page_size));
1766 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr));
1767 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr));
1768 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs);
1769
1770 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1771 if (ret) {
1772 dev_warn(dev->ctrl.device,
1773 "failed to set host mem (err %d, flags %#x).\n",
1774 ret, bits);
1775 }
87ad72a5
CH		 1776 return ret;
1777}
1778
1779static void nvme_free_host_mem(struct nvme_dev *dev)
1780{
1781 int i;
1782
1783 for (i = 0; i < dev->nr_host_mem_descs; i++) {
1784 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
1785 size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size;
1786
1787 dma_free_coherent(dev->dev, size, dev->host_mem_desc_bufs[i],
1788 le64_to_cpu(desc->addr));
1789 }
1790
1791 kfree(dev->host_mem_desc_bufs);
1792 dev->host_mem_desc_bufs = NULL;
4033f35d
CH		 1793 dma_free_coherent(dev->dev,
1794 dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
1795 dev->host_mem_descs, dev->host_mem_descs_dma);
87ad72a5 1796 dev->host_mem_descs = NULL;
7e5dd57e 1797 dev->nr_host_mem_descs = 0;
87ad72a5
CH		 1798}
1799
92dc6895
CH		 1800static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
1801 u32 chunk_size)
9d713c2b 1802{
87ad72a5 1803 struct nvme_host_mem_buf_desc *descs;
92dc6895 1804 u32 max_entries, len;
4033f35d 1805 dma_addr_t descs_dma;
2ee0e4ed 1806 int i = 0;
87ad72a5 1807 void **bufs;
6fbcde66 1808 u64 size, tmp;
87ad72a5 1809
87ad72a5
CH		 1810 tmp = (preferred + chunk_size - 1);
1811 do_div(tmp, chunk_size);
1812 max_entries = tmp;
044a9df1
CH		 1813
1814 if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
1815 max_entries = dev->ctrl.hmmaxd;
1816
4033f35d
CH		 1817 descs = dma_zalloc_coherent(dev->dev, max_entries * sizeof(*descs),
1818 &descs_dma, GFP_KERNEL);
87ad72a5
CH		 1819 if (!descs)
1820 goto out;
1821
1822 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
1823 if (!bufs)
1824 goto out_free_descs;
1825
244a8fe4 1826 for (size = 0; size < preferred && i < max_entries; size += len) {
87ad72a5
CH		 1827 dma_addr_t dma_addr;
1828
50cdb7c6 1829 len = min_t(u64, chunk_size, preferred - size);
87ad72a5
CH		 1830 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
1831 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1832 if (!bufs[i])
1833 break;
1834
1835 descs[i].addr = cpu_to_le64(dma_addr);
1836 descs[i].size = cpu_to_le32(len / dev->ctrl.page_size);
1837 i++;
1838 }
1839
92dc6895 1840 if (!size)
87ad72a5 1841 goto out_free_bufs;
87ad72a5 1842
87ad72a5
CH		 1843 dev->nr_host_mem_descs = i;
1844 dev->host_mem_size = size;
1845 dev->host_mem_descs = descs;
4033f35d 1846 dev->host_mem_descs_dma = descs_dma;
87ad72a5
CH		 1847 dev->host_mem_desc_bufs = bufs;
1848 return 0;
1849
1850out_free_bufs:
1851 while (--i >= 0) {
1852 size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size;
1853
1854 dma_free_coherent(dev->dev, size, bufs[i],
1855 le64_to_cpu(descs[i].addr));
1856 }
1857
1858 kfree(bufs);
1859out_free_descs:
4033f35d
CH		 1860 dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
1861 descs_dma);
87ad72a5 1862out:
87ad72a5
CH		 1863 dev->host_mem_descs = NULL;
1864 return -ENOMEM;
1865}
1866
92dc6895
CH		 1867static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
1868{
1869 u32 chunk_size;
1870
1871 /* start big and work our way down */
30f92d62 1872 for (chunk_size = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
044a9df1 1873 chunk_size >= max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
92dc6895
CH		 1874 chunk_size /= 2) {
1875 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
1876 if (!min || dev->host_mem_size >= min)
1877 return 0;
1878 nvme_free_host_mem(dev);
1879 }
1880 }
1881
1882 return -ENOMEM;
1883}
1884
9620cfba 1885static int nvme_setup_host_mem(struct nvme_dev *dev)
87ad72a5
CH		 1886{
1887 u64 max = (u64)max_host_mem_size_mb * SZ_1M;
1888 u64 preferred = (u64)dev->ctrl.hmpre * 4096;
1889 u64 min = (u64)dev->ctrl.hmmin * 4096;
1890 u32 enable_bits = NVME_HOST_MEM_ENABLE;
6fbcde66 1891 int ret;
87ad72a5
CH		 1892
1893 preferred = min(preferred, max);
1894 if (min > max) {
1895 dev_warn(dev->ctrl.device,
1896 "min host memory (%lld MiB) above limit (%d MiB).\n",
1897 min >> ilog2(SZ_1M), max_host_mem_size_mb);
1898 nvme_free_host_mem(dev);
9620cfba 1899 return 0;
87ad72a5
CH		 1900 }
1901
1902 /*
1903 * If we already have a buffer allocated check if we can reuse it.
1904 */
1905 if (dev->host_mem_descs) {
1906 if (dev->host_mem_size >= min)
1907 enable_bits |= NVME_HOST_MEM_RETURN;
1908 else
1909 nvme_free_host_mem(dev);
1910 }
1911
1912 if (!dev->host_mem_descs) {
92dc6895
CH		 1913 if (nvme_alloc_host_mem(dev, min, preferred)) {
1914 dev_warn(dev->ctrl.device,
1915 "failed to allocate host memory buffer.\n");
9620cfba 1916 return 0; /* controller must work without HMB */
92dc6895
CH		 1917 }
1918
1919 dev_info(dev->ctrl.device,
1920 "allocated %lld MiB host memory buffer.\n",
1921 dev->host_mem_size >> ilog2(SZ_1M));
87ad72a5
CH		 1922 }
1923
9620cfba
CH		 1924 ret = nvme_set_host_mem(dev, enable_bits);
1925 if (ret)
87ad72a5 1926 nvme_free_host_mem(dev);
9620cfba 1927 return ret;
9d713c2b
KB		 1928}
1929
8d85fce7 1930static int nvme_setup_io_queues(struct nvme_dev *dev)
b60503ba 1931{
147b27e4 1932 struct nvme_queue *adminq = &dev->queues[0];
e75ec752 1933 struct pci_dev *pdev = to_pci_dev(dev->dev);
97f6ef64
XY		 1934 int result, nr_io_queues;
1935 unsigned long size;
b60503ba 1936
22b55601
KB		 1937 struct irq_affinity affd = {
1938 .pre_vectors = 1
1939 };
1940
16ccfff2 1941 nr_io_queues = num_possible_cpus();
9a0be7ab
CH		 1942 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
1943 if (result < 0)
1b23484b 1944 return result;
9a0be7ab 1945
f5fa90dc 1946 if (nr_io_queues == 0)
a5229050 1947 return 0;
b60503ba 1948
88de4598 1949 if (dev->cmb && (dev->cmbsz & NVME_CMBSZ_SQS)) {
8ffaadf7
JD		 1950 result = nvme_cmb_qdepth(dev, nr_io_queues,
1951 sizeof(struct nvme_command));
1952 if (result > 0)
1953 dev->q_depth = result;
1954 else
1955 nvme_release_cmb(dev);
1956 }
1957
97f6ef64
XY		 1958 do {
1959 size = db_bar_size(dev, nr_io_queues);
1960 result = nvme_remap_bar(dev, size);
1961 if (!result)
1962 break;
1963 if (!--nr_io_queues)
1964 return -ENOMEM;
1965 } while (1);
1966 adminq->q_db = dev->dbs;
f1938f6e 1967
9d713c2b 1968 /* Deregister the admin queue's interrupt */
0ff199cb 1969 pci_free_irq(pdev, 0, adminq);
9d713c2b 1970
e32efbfc
JA		 1971 /*
1972 * If we enable msix early due to not intx, disable it again before
1973 * setting up the full range we need.
1974 */
dca51e78 1975 pci_free_irq_vectors(pdev);
22b55601
KB		 1976 result = pci_alloc_irq_vectors_affinity(pdev, 1, nr_io_queues + 1,
1977 PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd);
1978 if (result <= 0)
dca51e78 1979 return -EIO;
22b55601
KB		 1980 dev->num_vecs = result;
1981 dev->max_qid = max(result - 1, 1);
fa08a396 1982
063a8096
MW		 1983 /*
1984 * Should investigate if there's a performance win from allocating
1985 * more queues than interrupt vectors; it might allow the submission
1986 * path to scale better, even if the receive path is limited by the
1987 * number of interrupts.
1988 */
063a8096 1989
dca51e78 1990 result = queue_request_irq(adminq);
758dd7fd
JD		 1991 if (result) {
1992 adminq->cq_vector = -1;
d4875622 1993 return result;
758dd7fd 1994 }
749941f2 1995 return nvme_create_io_queues(dev);
b60503ba
MW		 1996}
1997
2a842aca 1998static void nvme_del_queue_end(struct request *req, blk_status_t error)
a5768aa8 1999{
db3cbfff 2000 struct nvme_queue *nvmeq = req->end_io_data;
b5875222 2001
db3cbfff
KB		 2002 blk_mq_free_request(req);
2003 complete(&nvmeq->dev->ioq_wait);
a5768aa8
KB		 2004}
2005
2a842aca 2006static void nvme_del_cq_end(struct request *req, blk_status_t error)
a5768aa8 2007{
db3cbfff 2008 struct nvme_queue *nvmeq = req->end_io_data;
5cb525c8 2009 u16 start, end;
a5768aa8 2010
db3cbfff
KB		 2011 if (!error) {
2012 unsigned long flags;
2013
0bc88192 2014 spin_lock_irqsave(&nvmeq->cq_lock, flags);
5cb525c8 2015 nvme_process_cq(nvmeq, &start, &end, -1);
1ab0cd69 2016 spin_unlock_irqrestore(&nvmeq->cq_lock, flags);
5cb525c8
JA		 2017
2018 nvme_complete_cqes(nvmeq, start, end);
a5768aa8 2019 }
db3cbfff
KB		 2020
2021 nvme_del_queue_end(req, error);
a5768aa8
KB		 2022}
2023
db3cbfff 2024static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
bda4e0fb 2025{
db3cbfff
KB		 2026 struct request_queue *q = nvmeq->dev->ctrl.admin_q;
2027 struct request *req;
2028 struct nvme_command cmd;
bda4e0fb 2029
db3cbfff
KB		 2030 memset(&cmd, 0, sizeof(cmd));
2031 cmd.delete_queue.opcode = opcode;
2032 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
bda4e0fb 2033
eb71f435 2034 req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
db3cbfff
KB		 2035 if (IS_ERR(req))
2036 return PTR_ERR(req);
bda4e0fb 2037
db3cbfff
KB		 2038 req->timeout = ADMIN_TIMEOUT;
2039 req->end_io_data = nvmeq;
2040
2041 blk_execute_rq_nowait(q, NULL, req, false,
2042 opcode == nvme_admin_delete_cq ?
2043 nvme_del_cq_end : nvme_del_queue_end);
2044 return 0;
bda4e0fb
KB		 2045}
2046
ee9aebb2 2047static void nvme_disable_io_queues(struct nvme_dev *dev)
a5768aa8 2048{
ee9aebb2 2049 int pass, queues = dev->online_queues - 1;
db3cbfff
KB		 2050 unsigned long timeout;
2051 u8 opcode = nvme_admin_delete_sq;
a5768aa8 2052
db3cbfff 2053 for (pass = 0; pass < 2; pass++) {
014a0d60 2054 int sent = 0, i = queues;
db3cbfff
KB		 2055
2056 reinit_completion(&dev->ioq_wait);
2057 retry:
2058 timeout = ADMIN_TIMEOUT;
c21377f8 2059 for (; i > 0; i--, sent++)
147b27e4 2060 if (nvme_delete_queue(&dev->queues[i], opcode))
db3cbfff 2061 break;
c21377f8 2062
db3cbfff
KB		 2063 while (sent--) {
2064 timeout = wait_for_completion_io_timeout(&dev->ioq_wait, timeout);
2065 if (timeout == 0)
2066 return;
2067 if (i)
2068 goto retry;
2069 }
2070 opcode = nvme_admin_delete_cq;
2071 }
a5768aa8
KB		 2072}
2073
422ef0c7 2074/*
2b1b7e78 2075 * return error value only when tagset allocation failed
422ef0c7 2076 */
8d85fce7 2077static int nvme_dev_add(struct nvme_dev *dev)
b60503ba 2078{
2b1b7e78
JW		 2079 int ret;
2080
5bae7f73 2081 if (!dev->ctrl.tagset) {
ffe7704d
KB		 2082 dev->tagset.ops = &nvme_mq_ops;
2083 dev->tagset.nr_hw_queues = dev->online_queues - 1;
2084 dev->tagset.timeout = NVME_IO_TIMEOUT;
2085 dev->tagset.numa_node = dev_to_node(dev->dev);
2086 dev->tagset.queue_depth =
a4aea562 2087 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
a7a7cbe3
CK		 2088 dev->tagset.cmd_size = nvme_pci_cmd_size(dev, false);
2089 if ((dev->ctrl.sgls & ((1 << 0) | (1 << 1))) && sgl_threshold) {
2090 dev->tagset.cmd_size = max(dev->tagset.cmd_size,
2091 nvme_pci_cmd_size(dev, true));
2092 }
ffe7704d
KB		 2093 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2094 dev->tagset.driver_data = dev;
b60503ba 2095
2b1b7e78
JW		 2096 ret = blk_mq_alloc_tag_set(&dev->tagset);
2097 if (ret) {
2098 dev_warn(dev->ctrl.device,
2099 "IO queues tagset allocation failed %d\n", ret);
2100 return ret;
2101 }
5bae7f73 2102 dev->ctrl.tagset = &dev->tagset;
f9f38e33
HK		 2103
2104 nvme_dbbuf_set(dev);
949928c1
KB		 2105 } else {
2106 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2107
2108 /* Free previously allocated queues that are no longer usable */
2109 nvme_free_queues(dev, dev->online_queues);
ffe7704d 2110 }
949928c1 2111
e1e5e564 2112 return 0;
b60503ba
MW		 2113}
2114
b00a726a 2115static int nvme_pci_enable(struct nvme_dev *dev)
0877cb0d 2116{
b00a726a 2117 int result = -ENOMEM;
e75ec752 2118 struct pci_dev *pdev = to_pci_dev(dev->dev);
0877cb0d
KB		 2119
2120 if (pci_enable_device_mem(pdev))
2121 return result;
2122
0877cb0d 2123 pci_set_master(pdev);
0877cb0d 2124
e75ec752
CH		 2125 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) &&
2126 dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32)))
052d0efa 2127 goto disable;
0877cb0d 2128
7a67cbea 2129 if (readl(dev->bar + NVME_REG_CSTS) == -1) {
0e53d180 2130 result = -ENODEV;
b00a726a 2131 goto disable;
0e53d180 2132 }
e32efbfc
JA		 2133
2134 /*
a5229050
KB		 2135 * Some devices and/or platforms don't advertise or work with INTx
2136 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2137 * adjust this later.
e32efbfc 2138 */
dca51e78
CH		 2139 result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
2140 if (result < 0)
2141 return result;
e32efbfc 2142
20d0dfe6 2143 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
7a67cbea 2144
20d0dfe6 2145 dev->q_depth = min_t(int, NVME_CAP_MQES(dev->ctrl.cap) + 1,
b27c1e68 2146 io_queue_depth);
20d0dfe6 2147 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
7a67cbea 2148 dev->dbs = dev->bar + 4096;
1f390c1f
SG		 2149
2150 /*
2151 * Temporary fix for the Apple controller found in the MacBook8,1 and
2152 * some MacBook7,1 to avoid controller resets and data loss.
2153 */
2154 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
2155 dev->q_depth = 2;
9bdcfb10
CH		 2156 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
2157 "set queue depth=%u to work around controller resets\n",
1f390c1f 2158 dev->q_depth);
d554b5e1
MP		 2159 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2160 (pdev->device == 0xa821 || pdev->device == 0xa822) &&
20d0dfe6 2161 NVME_CAP_MQES(dev->ctrl.cap) == 0) {
d554b5e1
MP		 2162 dev->q_depth = 64;
2163 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2164 "set queue depth=%u\n", dev->q_depth);
1f390c1f
SG		 2165 }
2166
f65efd6d 2167 nvme_map_cmb(dev);
202021c1 2168
a0a3408e
KB		 2169 pci_enable_pcie_error_reporting(pdev);
2170 pci_save_state(pdev);
0877cb0d
KB		 2171 return 0;
2172
2173 disable:
0877cb0d
KB		 2174 pci_disable_device(pdev);
2175 return result;
2176}
2177
2178static void nvme_dev_unmap(struct nvme_dev *dev)
b00a726a
KB		 2179{
2180 if (dev->bar)
2181 iounmap(dev->bar);
a1f447b3 2182 pci_release_mem_regions(to_pci_dev(dev->dev));
b00a726a
KB		 2183}
2184
2185static void nvme_pci_disable(struct nvme_dev *dev)
0877cb0d 2186{
e75ec752
CH		 2187 struct pci_dev *pdev = to_pci_dev(dev->dev);
2188
f63572df 2189 nvme_release_cmb(dev);
dca51e78 2190 pci_free_irq_vectors(pdev);
0877cb0d 2191
a0a3408e
KB		 2192 if (pci_is_enabled(pdev)) {
2193 pci_disable_pcie_error_reporting(pdev);
e75ec752 2194 pci_disable_device(pdev);
4d115420 2195 }
4d115420
KB		 2196}
2197
a5cdb68c 2198static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
b60503ba 2199{
ee9aebb2 2200 int i;
302ad8cc
KB		 2201 bool dead = true;
2202 struct pci_dev *pdev = to_pci_dev(dev->dev);
22404274 2203
77bf25ea 2204 mutex_lock(&dev->shutdown_lock);
302ad8cc
KB		 2205 if (pci_is_enabled(pdev)) {
2206 u32 csts = readl(dev->bar + NVME_REG_CSTS);
2207
ebef7368
KB		 2208 if (dev->ctrl.state == NVME_CTRL_LIVE ||
2209 dev->ctrl.state == NVME_CTRL_RESETTING)
302ad8cc
KB		 2210 nvme_start_freeze(&dev->ctrl);
2211 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
2212 pdev->error_state != pci_channel_io_normal);
c9d3bf88 2213 }
c21377f8 2214
302ad8cc
KB		 2215 /*
2216 * Give the controller a chance to complete all entered requests if
2217 * doing a safe shutdown.
2218 */
87ad72a5
CH		 2219 if (!dead) {
2220 if (shutdown)
2221 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
9a915a5b
JW		 2222 }
2223
2224 nvme_stop_queues(&dev->ctrl);
87ad72a5 2225
64ee0ac0 2226 if (!dead && dev->ctrl.queue_count > 0) {
ee9aebb2 2227 nvme_disable_io_queues(dev);
a5cdb68c 2228 nvme_disable_admin_queue(dev, shutdown);
4d115420 2229 }
ee9aebb2
KB		 2230 for (i = dev->ctrl.queue_count - 1; i >= 0; i--)
2231 nvme_suspend_queue(&dev->queues[i]);
2232
b00a726a 2233 nvme_pci_disable(dev);
07836e65 2234
e1958e65
ML		 2235 blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
2236 blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
302ad8cc
KB		 2237
2238 /*
2239 * The driver will not be starting up queues again if shutting down so
2240 * must flush all entered requests to their failed completion to avoid
2241 * deadlocking blk-mq hot-cpu notifier.
2242 */
2243 if (shutdown)
2244 nvme_start_queues(&dev->ctrl);
77bf25ea 2245 mutex_unlock(&dev->shutdown_lock);
b60503ba
MW		 2246}
2247
091b6092
MW		 2248static int nvme_setup_prp_pools(struct nvme_dev *dev)
2249{
e75ec752 2250 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
091b6092
MW		 2251 PAGE_SIZE, PAGE_SIZE, 0);
2252 if (!dev->prp_page_pool)
2253 return -ENOMEM;
2254
99802a7a 2255 /* Optimisation for I/Os between 4k and 128k */
e75ec752 2256 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
99802a7a
MW		 2257 256, 256, 0);
2258 if (!dev->prp_small_pool) {
2259 dma_pool_destroy(dev->prp_page_pool);
2260 return -ENOMEM;
2261 }
091b6092
MW		 2262 return 0;
2263}
2264
2265static void nvme_release_prp_pools(struct nvme_dev *dev)
2266{
2267 dma_pool_destroy(dev->prp_page_pool);
99802a7a 2268 dma_pool_destroy(dev->prp_small_pool);
091b6092
MW		 2269}
2270
1673f1f0 2271static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
5e82e952 2272{
1673f1f0 2273 struct nvme_dev *dev = to_nvme_dev(ctrl);
9ac27090 2274
f9f38e33 2275 nvme_dbbuf_dma_free(dev);
e75ec752 2276 put_device(dev->dev);
4af0e21c
KB		 2277 if (dev->tagset.tags)
2278 blk_mq_free_tag_set(&dev->tagset);
1c63dc66
CH		 2279 if (dev->ctrl.admin_q)
2280 blk_put_queue(dev->ctrl.admin_q);
5e82e952 2281 kfree(dev->queues);
e286bcfc 2282 free_opal_dev(dev->ctrl.opal_dev);
5e82e952
KB		 2283 kfree(dev);
2284}
2285
f58944e2
KB		 2286static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status)
2287{
237045fc 2288 dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status);
f58944e2 2289
d22524a4 2290 nvme_get_ctrl(&dev->ctrl);
69d9a99c 2291 nvme_dev_disable(dev, false);
03e0f3a6 2292 if (!queue_work(nvme_wq, &dev->remove_work))
f58944e2
KB		 2293 nvme_put_ctrl(&dev->ctrl);
2294}
2295
fd634f41 2296static void nvme_reset_work(struct work_struct *work)
5e82e952 2297{
d86c4d8e
CH		 2298 struct nvme_dev *dev =
2299 container_of(work, struct nvme_dev, ctrl.reset_work);
a98e58e5 2300 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
f58944e2 2301 int result = -ENODEV;
2b1b7e78 2302 enum nvme_ctrl_state new_state = NVME_CTRL_LIVE;
5e82e952 2303
82b057ca 2304 if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING))
fd634f41 2305 goto out;
5e82e952 2306
fd634f41
CH		 2307 /*
2308 * If we're called to reset a live controller first shut it down before
2309 * moving on.
2310 */
b00a726a 2311 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
a5cdb68c 2312 nvme_dev_disable(dev, false);
5e82e952 2313
ad70062c 2314 /*
ad6a0a52 2315 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
ad70062c
JW		 2316 * initializing procedure here.
2317 */
ad6a0a52 2318 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
ad70062c 2319 dev_warn(dev->ctrl.device,
ad6a0a52 2320 "failed to mark controller CONNECTING\n");
ad70062c
JW		 2321 goto out;
2322 }
2323
b00a726a 2324 result = nvme_pci_enable(dev);
f0b50732 2325 if (result)
3cf519b5 2326 goto out;
f0b50732 2327
01ad0990 2328 result = nvme_pci_configure_admin_queue(dev);
f0b50732 2329 if (result)
f58944e2 2330 goto out;
f0b50732 2331
0fb59cbc
KB		 2332 result = nvme_alloc_admin_tags(dev);
2333 if (result)
f58944e2 2334 goto out;
b9afca3e 2335
ce4541f4
CH		 2336 result = nvme_init_identify(&dev->ctrl);
2337 if (result)
f58944e2 2338 goto out;
ce4541f4 2339
e286bcfc
SB		 2340 if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
2341 if (!dev->ctrl.opal_dev)
2342 dev->ctrl.opal_dev =
2343 init_opal_dev(&dev->ctrl, &nvme_sec_submit);
2344 else if (was_suspend)
2345 opal_unlock_from_suspend(dev->ctrl.opal_dev);
2346 } else {
2347 free_opal_dev(dev->ctrl.opal_dev);
2348 dev->ctrl.opal_dev = NULL;
4f1244c8 2349 }
a98e58e5 2350
f9f38e33
HK		 2351 if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) {
2352 result = nvme_dbbuf_dma_alloc(dev);
2353 if (result)
2354 dev_warn(dev->dev,
2355 "unable to allocate dma for dbbuf\n");
2356 }
2357
9620cfba
CH		 2358 if (dev->ctrl.hmpre) {
2359 result = nvme_setup_host_mem(dev);
2360 if (result < 0)
2361 goto out;
2362 }
87ad72a5 2363
f0b50732 2364 result = nvme_setup_io_queues(dev);
badc34d4 2365 if (result)
f58944e2 2366 goto out;
f0b50732 2367
2659e57b
CH		 2368 /*
2369 * Keep the controller around but remove all namespaces if we don't have
2370 * any working I/O queue.
2371 */
3cf519b5 2372 if (dev->online_queues < 2) {
1b3c47c1 2373 dev_warn(dev->ctrl.device, "IO queues not created\n");
3b24774e 2374 nvme_kill_queues(&dev->ctrl);
5bae7f73 2375 nvme_remove_namespaces(&dev->ctrl);
2b1b7e78 2376 new_state = NVME_CTRL_ADMIN_ONLY;
3cf519b5 2377 } else {
25646264 2378 nvme_start_queues(&dev->ctrl);
302ad8cc 2379 nvme_wait_freeze(&dev->ctrl);
2b1b7e78
JW		 2380 /* hit this only when allocate tagset fails */
2381 if (nvme_dev_add(dev))
2382 new_state = NVME_CTRL_ADMIN_ONLY;
302ad8cc 2383 nvme_unfreeze(&dev->ctrl);
3cf519b5
CH		 2384 }
2385
2b1b7e78
JW		 2386 /*
2387 * If only admin queue live, keep it to do further investigation or
2388 * recovery.
2389 */
2390 if (!nvme_change_ctrl_state(&dev->ctrl, new_state)) {
2391 dev_warn(dev->ctrl.device,
2392 "failed to mark controller state %d\n", new_state);
bb8d261e
CH		 2393 goto out;
2394 }
92911a55 2395
d09f2b45 2396 nvme_start_ctrl(&dev->ctrl);
3cf519b5 2397 return;
f0b50732 2398
3cf519b5 2399 out:
f58944e2 2400 nvme_remove_dead_ctrl(dev, result);
f0b50732
KB		 2401}
2402
5c8809e6 2403static void nvme_remove_dead_ctrl_work(struct work_struct *work)
9a6b9458 2404{
5c8809e6 2405 struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
e75ec752 2406 struct pci_dev *pdev = to_pci_dev(dev->dev);
9a6b9458 2407
69d9a99c 2408 nvme_kill_queues(&dev->ctrl);
9a6b9458 2409 if (pci_get_drvdata(pdev))
921920ab 2410 device_release_driver(&pdev->dev);
1673f1f0 2411 nvme_put_ctrl(&dev->ctrl);
9a6b9458
KB		 2412}
2413
1c63dc66 2414static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
9ca97374 2415{
1c63dc66 2416 *val = readl(to_nvme_dev(ctrl)->bar + off);
90667892 2417 return 0;
9ca97374
TH		 2418}
2419
5fd4ce1b 2420static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
4cc06521 2421{
5fd4ce1b
CH		 2422 writel(val, to_nvme_dev(ctrl)->bar + off);
2423 return 0;
2424}
4cc06521 2425
7fd8930f
CH		 2426static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2427{
2428 *val = readq(to_nvme_dev(ctrl)->bar + off);
2429 return 0;
4cc06521
KB		 2430}
2431
97c12223
KB		 2432static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
2433{
2434 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2435
2436 return snprintf(buf, size, "%s", dev_name(&pdev->dev));
2437}
2438
1c63dc66 2439static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
1a353d85 2440 .name = "pcie",
e439bb12 2441 .module = THIS_MODULE,
c81bfba9 2442 .flags = NVME_F_METADATA_SUPPORTED,
1c63dc66 2443 .reg_read32 = nvme_pci_reg_read32,
5fd4ce1b 2444 .reg_write32 = nvme_pci_reg_write32,
7fd8930f 2445 .reg_read64 = nvme_pci_reg_read64,
1673f1f0 2446 .free_ctrl = nvme_pci_free_ctrl,
f866fc42 2447 .submit_async_event = nvme_pci_submit_async_event,
97c12223 2448 .get_address = nvme_pci_get_address,
1c63dc66 2449};
4cc06521 2450
b00a726a
KB		 2451static int nvme_dev_map(struct nvme_dev *dev)
2452{
b00a726a
KB		 2453 struct pci_dev *pdev = to_pci_dev(dev->dev);
2454
a1f447b3 2455 if (pci_request_mem_regions(pdev, "nvme"))
b00a726a
KB		 2456 return -ENODEV;
2457
97f6ef64 2458 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
b00a726a
KB		 2459 goto release;
2460
9fa196e7 2461 return 0;
b00a726a 2462 release:
9fa196e7
MG		 2463 pci_release_mem_regions(pdev);
2464 return -ENODEV;
b00a726a
KB		 2465}
2466
8427bbc2 2467static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
ff5350a8
AL		 2468{
2469 if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
2470 /*
2471 * Several Samsung devices seem to drop off the PCIe bus
2472 * randomly when APST is on and uses the deepest sleep state.
2473 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2474 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2475 * 950 PRO 256GB", but it seems to be restricted to two Dell
2476 * laptops.
2477 */
2478 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
2479 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
2480 dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
2481 return NVME_QUIRK_NO_DEEPEST_PS;
8427bbc2
KHF		 2482 } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
2483 /*
2484 * Samsung SSD 960 EVO drops off the PCIe bus after system
467c77d4
JJ		 2485 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
2486 * within few minutes after bootup on a Coffee Lake board -
2487 * ASUS PRIME Z370-A
8427bbc2
KHF		 2488 */
2489 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
467c77d4
JJ		 2490 (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") ||
2491 dmi_match(DMI_BOARD_NAME, "PRIME Z370-A")))
8427bbc2 2492 return NVME_QUIRK_NO_APST;
ff5350a8
AL		 2493 }
2494
2495 return 0;
2496}
2497
18119775
KB		 2498static void nvme_async_probe(void *data, async_cookie_t cookie)
2499{
2500 struct nvme_dev *dev = data;
80f513b5 2501
18119775
KB		 2502 nvme_reset_ctrl_sync(&dev->ctrl);
2503 flush_work(&dev->ctrl.scan_work);
80f513b5 2504 nvme_put_ctrl(&dev->ctrl);
18119775
KB		 2505}
2506
8d85fce7 2507static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
b60503ba 2508{
a4aea562 2509 int node, result = -ENOMEM;
b60503ba 2510 struct nvme_dev *dev;
ff5350a8 2511 unsigned long quirks = id->driver_data;
b60503ba 2512
a4aea562
MB		 2513 node = dev_to_node(&pdev->dev);
2514 if (node == NUMA_NO_NODE)
2fa84351 2515 set_dev_node(&pdev->dev, first_memory_node);
a4aea562
MB		 2516
2517 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
b60503ba
MW		 2518 if (!dev)
2519 return -ENOMEM;
147b27e4
SG		 2520
2521 dev->queues = kcalloc_node(num_possible_cpus() + 1,
2522 sizeof(struct nvme_queue), GFP_KERNEL, node);
b60503ba
MW		 2523 if (!dev->queues)
2524 goto free;
2525
e75ec752 2526 dev->dev = get_device(&pdev->dev);
9a6b9458 2527 pci_set_drvdata(pdev, dev);
1c63dc66 2528
b00a726a
KB		 2529 result = nvme_dev_map(dev);
2530 if (result)
b00c9b7a 2531 goto put_pci;
b00a726a 2532
d86c4d8e 2533 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
5c8809e6 2534 INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
77bf25ea 2535 mutex_init(&dev->shutdown_lock);
db3cbfff 2536 init_completion(&dev->ioq_wait);
b60503ba 2537
091b6092
MW		 2538 result = nvme_setup_prp_pools(dev);
2539 if (result)
b00c9b7a 2540 goto unmap;
4cc06521 2541
8427bbc2 2542 quirks |= check_vendor_combination_bug(pdev);
ff5350a8 2543
f3ca80fc 2544 result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
ff5350a8 2545 quirks);
4cc06521 2546 if (result)
2e1d8448 2547 goto release_pools;
740216fc 2548
1b3c47c1
SG		 2549 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
2550
80f513b5 2551 nvme_get_ctrl(&dev->ctrl);
18119775 2552 async_schedule(nvme_async_probe, dev);
4caff8fc 2553
b60503ba
MW		 2554 return 0;
2555
0877cb0d 2556 release_pools:
091b6092 2557 nvme_release_prp_pools(dev);
b00c9b7a
CJ		 2558 unmap:
2559 nvme_dev_unmap(dev);
a96d4f5c 2560 put_pci:
e75ec752 2561 put_device(dev->dev);
b60503ba
MW		 2562 free:
2563 kfree(dev->queues);
b60503ba
MW		 2564 kfree(dev);
2565 return result;
2566}
2567
775755ed 2568static void nvme_reset_prepare(struct pci_dev *pdev)
f0d54a54 2569{
a6739479 2570 struct nvme_dev *dev = pci_get_drvdata(pdev);
f263fbb8 2571 nvme_dev_disable(dev, false);
775755ed 2572}
f0d54a54 2573
775755ed
CH		 2574static void nvme_reset_done(struct pci_dev *pdev)
2575{
f263fbb8 2576 struct nvme_dev *dev = pci_get_drvdata(pdev);
79c48ccf 2577 nvme_reset_ctrl_sync(&dev->ctrl);
f0d54a54
KB		 2578}
2579
09ece142
KB		 2580static void nvme_shutdown(struct pci_dev *pdev)
2581{
2582 struct nvme_dev *dev = pci_get_drvdata(pdev);
a5cdb68c 2583 nvme_dev_disable(dev, true);
09ece142
KB		 2584}
2585
f58944e2
KB		 2586/*
2587 * The driver's remove may be called on a device in a partially initialized
2588 * state. This function must not have any dependencies on the device state in
2589 * order to proceed.
2590 */
8d85fce7 2591static void nvme_remove(struct pci_dev *pdev)
b60503ba
MW		 2592{
2593 struct nvme_dev *dev = pci_get_drvdata(pdev);
9a6b9458 2594
bb8d261e
CH		 2595 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
2596
d86c4d8e 2597 cancel_work_sync(&dev->ctrl.reset_work);
9a6b9458 2598 pci_set_drvdata(pdev, NULL);
0ff9d4e1 2599
6db28eda 2600 if (!pci_device_is_present(pdev)) {
0ff9d4e1 2601 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
1d39e692 2602 nvme_dev_disable(dev, true);
6db28eda 2603 }
0ff9d4e1 2604
d86c4d8e 2605 flush_work(&dev->ctrl.reset_work);
d09f2b45
SG		 2606 nvme_stop_ctrl(&dev->ctrl);
2607 nvme_remove_namespaces(&dev->ctrl);
a5cdb68c 2608 nvme_dev_disable(dev, true);
87ad72a5 2609 nvme_free_host_mem(dev);
a4aea562 2610 nvme_dev_remove_admin(dev);
a1a5ef99 2611 nvme_free_queues(dev, 0);
d09f2b45 2612 nvme_uninit_ctrl(&dev->ctrl);
9a6b9458 2613 nvme_release_prp_pools(dev);
b00a726a 2614 nvme_dev_unmap(dev);
1673f1f0 2615 nvme_put_ctrl(&dev->ctrl);
b60503ba
MW		 2616}
2617
13880f5b
KB		 2618static int nvme_pci_sriov_configure(struct pci_dev *pdev, int numvfs)
2619{
2620 int ret = 0;
2621
2622 if (numvfs == 0) {
2623 if (pci_vfs_assigned(pdev)) {
2624 dev_warn(&pdev->dev,
2625 "Cannot disable SR-IOV VFs while assigned\n");
2626 return -EPERM;
2627 }
2628 pci_disable_sriov(pdev);
2629 return 0;
2630 }
2631
2632 ret = pci_enable_sriov(pdev, numvfs);
2633 return ret ? ret : numvfs;
2634}
2635
671a6018 2636#ifdef CONFIG_PM_SLEEP
cd638946
KB		 2637static int nvme_suspend(struct device *dev)
2638{
2639 struct pci_dev *pdev = to_pci_dev(dev);
2640 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2641
a5cdb68c 2642 nvme_dev_disable(ndev, true);
cd638946
KB		 2643 return 0;
2644}
2645
2646static int nvme_resume(struct device *dev)
2647{
2648 struct pci_dev *pdev = to_pci_dev(dev);
2649 struct nvme_dev *ndev = pci_get_drvdata(pdev);
cd638946 2650
d86c4d8e 2651 nvme_reset_ctrl(&ndev->ctrl);
9a6b9458 2652 return 0;
cd638946 2653}
671a6018 2654#endif
cd638946
KB		 2655
2656static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
b60503ba 2657
a0a3408e
KB		 2658static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
2659 pci_channel_state_t state)
2660{
2661 struct nvme_dev *dev = pci_get_drvdata(pdev);
2662
2663 /*
2664 * A frozen channel requires a reset. When detected, this method will
2665 * shutdown the controller to quiesce. The controller will be restarted
2666 * after the slot reset through driver's slot_reset callback.
2667 */
a0a3408e
KB		 2668 switch (state) {
2669 case pci_channel_io_normal:
2670 return PCI_ERS_RESULT_CAN_RECOVER;
2671 case pci_channel_io_frozen:
d011fb31
KB		 2672 dev_warn(dev->ctrl.device,
2673 "frozen state error detected, reset controller\n");
a5cdb68c 2674 nvme_dev_disable(dev, false);
a0a3408e
KB		 2675 return PCI_ERS_RESULT_NEED_RESET;
2676 case pci_channel_io_perm_failure:
d011fb31
KB		 2677 dev_warn(dev->ctrl.device,
2678 "failure state error detected, request disconnect\n");
a0a3408e
KB		 2679 return PCI_ERS_RESULT_DISCONNECT;
2680 }
2681 return PCI_ERS_RESULT_NEED_RESET;
2682}
2683
2684static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
2685{
2686 struct nvme_dev *dev = pci_get_drvdata(pdev);
2687
1b3c47c1 2688 dev_info(dev->ctrl.device, "restart after slot reset\n");
a0a3408e 2689 pci_restore_state(pdev);
d86c4d8e 2690 nvme_reset_ctrl(&dev->ctrl);
a0a3408e
KB		 2691 return PCI_ERS_RESULT_RECOVERED;
2692}
2693
2694static void nvme_error_resume(struct pci_dev *pdev)
2695{
72cd4cc2
KB		 2696 struct nvme_dev *dev = pci_get_drvdata(pdev);
2697
2698 flush_work(&dev->ctrl.reset_work);
a0a3408e
KB		 2699 pci_cleanup_aer_uncorrect_error_status(pdev);
2700}
2701
1d352035 2702static const struct pci_error_handlers nvme_err_handler = {
b60503ba 2703 .error_detected = nvme_error_detected,
b60503ba
MW		 2704 .slot_reset = nvme_slot_reset,
2705 .resume = nvme_error_resume,
775755ed
CH		 2706 .reset_prepare = nvme_reset_prepare,
2707 .reset_done = nvme_reset_done,
b60503ba
MW		 2708};
2709
6eb0d698 2710static const struct pci_device_id nvme_id_table[] = {
106198ed 2711 { PCI_VDEVICE(INTEL, 0x0953),
08095e70 2712 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 2713 NVME_QUIRK_DEALLOCATE_ZEROES, },
99466e70
KB		 2714 { PCI_VDEVICE(INTEL, 0x0a53),
2715 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 2716 NVME_QUIRK_DEALLOCATE_ZEROES, },
99466e70
KB		 2717 { PCI_VDEVICE(INTEL, 0x0a54),
2718 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 2719 NVME_QUIRK_DEALLOCATE_ZEROES, },
f99cb7af
DWF		 2720 { PCI_VDEVICE(INTEL, 0x0a55),
2721 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2722 NVME_QUIRK_DEALLOCATE_ZEROES, },
50af47d0 2723 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */
9abd68ef
JA		 2724 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
2725 NVME_QUIRK_MEDIUM_PRIO_SQ },
540c801c
KB		 2726 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */
2727 .driver_data = NVME_QUIRK_IDENTIFY_CNS, },
0302ae60
MP		 2728 { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */
2729 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
54adc010
GP		 2730 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
2731 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
8c97eecc
JL		 2732 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */
2733 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
015282c9
WW		 2734 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
2735 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
d554b5e1
MP		 2736 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */
2737 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2738 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */
2739 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
608cc4b1
CH		 2740 { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */
2741 .driver_data = NVME_QUIRK_LIGHTNVM, },
2742 { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */
2743 .driver_data = NVME_QUIRK_LIGHTNVM, },
ea48e877
WX		 2744 { PCI_DEVICE(0x1d1d, 0x2601), /* CNEX Granby */
2745 .driver_data = NVME_QUIRK_LIGHTNVM, },
b60503ba 2746 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
c74dc780 2747 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) },
124298bd 2748 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
b60503ba
MW		 2749 { 0, }
2750};
2751MODULE_DEVICE_TABLE(pci, nvme_id_table);
2752
2753static struct pci_driver nvme_driver = {
2754 .name = "nvme",
2755 .id_table = nvme_id_table,
2756 .probe = nvme_probe,
8d85fce7 2757 .remove = nvme_remove,
09ece142 2758 .shutdown = nvme_shutdown,
cd638946
KB		 2759 .driver = {
2760 .pm = &nvme_dev_pm_ops,
2761 },
13880f5b 2762 .sriov_configure = nvme_pci_sriov_configure,
b60503ba
MW		 2763 .err_handler = &nvme_err_handler,
2764};
2765
2766static int __init nvme_init(void)
2767{
9a6327d2 2768 return pci_register_driver(&nvme_driver);
b60503ba
MW		 2769}
2770
2771static void __exit nvme_exit(void)
2772{
2773 pci_unregister_driver(&nvme_driver);
03e0f3a6 2774 flush_workqueue(nvme_wq);
21bd78bc 2775 _nvme_check_size();
b60503ba
MW		 2776}
2777
2778MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2779MODULE_LICENSE("GPL");
c78b4713 2780MODULE_VERSION("1.0");
b60503ba
MW		 2781module_init(nvme_init);
2782module_exit(nvme_exit);
Linux 6.x block layer and io_uring tree(s)